From: Ralph Ronnquist Date: Mon, 13 Jan 2025 00:06:19 +0000 (+1100) Subject: download 2023-06-01 X-Git-Url: https://git.rrq.au/?a=commitdiff_plain;h=29c394bc91ec741195185e29d6df9e89e30d6150;p=rrq%2Ffasmarm.git download 2023-06-01 --- 29c394bc91ec741195185e29d6df9e89e30d6150 diff --git a/ReadMe.txt b/ReadMe.txt new file mode 100644 index 0000000..6d1583e --- /dev/null +++ b/ReadMe.txt @@ -0,0 +1,781 @@ + +FASMARM v1.44 + +This package is an ARM assembler add-on for FASM. + +FASMARM currently supports the full range of instructions for 32-bit and 64-bit +ARM processors and coprocessors up to and including v8. + +Contents: + + 1. ARM assembly compatibility + 2. UAL and pre-UAL syntaxes + 3. IT block handling + 4. Alternate encodings + 5. Output formats + 6. Control directives + 7. Data definitions + 8. Defining registers lists inside macros + 9. Half-precision number formatting + 10. Variants supported + 11. Further information + 12. Version history + +_______________________________________________________________________________ + 1. ARM assembly compatibility + +There are a few restrictions how the ARM instruction set is implemented. The +changes are minor and mostly have a minor impact. For the most part the basic +instruction outline is the same. Where possible the original style is used but +there are some differences: + +Not everything matches the ARM ADS assembly style, where possible the original +style is used but there are some differences +1) label names cannot begin with a digit +2) CPSIE and CPSID formats are changed, use "iflags_aif" form instead of "aif" + (eg. "CPSIE iflags_i" instead of "CPSID i") +3) SRS with writeback must have a separating space after the mode number and + before "!" (eg. "SRSDB 16 !" instead of "SRSDB 16!") +4) macro, rept, irp, format, if, virtual etc. are all significant changes from + the ARM ADS, so you will need to re-write those sections of existing code + + Original ARM Syntax | fasmarm Syntax + ----------------------+---------------------- + cpsie a | cpsie iflags_a + | + srsdb #29! | srsdb #29 ! ;or, + | srsdb 29 ! + +_______________________________________________________________________________ + 2. UAL and pre-UAL syntaxes + +fasmarm supports the original pre-UAL syntax and the newer UAL syntax. These +two syntaxes only affect THUMB encodings. + +UAL stands for: Universal Assembly Language. + +pre-UAL syntax is selected with the directive CODE16. +UAL syntax is selected with the directive THUMB. + +pre-UAL syntax does not specify the "s" (flag update) in the opcodes for +arithmetic operations involving the low set of registers (r0-r7). For example: + + pre-UAL Syntax | UAL Syntax ;Note + ----------------+------------------------------------------------------ + add r0,r1 | adds r0,r1 ;"s" was implicit with all registers <=r7 + adds r0,r1 | adds r0,r1 + | add r0,r1 ;only available inside an IT block, or + | ;as 32-bit T2 instruction + add r8,r1 | add r8,r1 ;high register used, does not update PSR + adds r8,r1 | adds r8,r1 ;only available as 32-bit T2 instruction + | + mov r0,r1 | movs r0,r1 ;"s" was implicit with all registers <=r7 + mov r8,r1 | mov r8,r1 ;high register used, does not update PSR + movs r0,r1 | movs r0,r1 + movs r8,r1 | movs r8,r1 ;only available as 32-bit T2 instruction + | + cpy r0,r1 | cpy r0,r1 ;also: mov r0,r1 in UAL + +Code written in UAL syntax can generally be assembled without modification in +both ARM and THUMB modes. It is recommended to use UAL syntax for all new code. +UAL syntax is get-what-you-write, whereas pre-UAL syntax has an implicit "s" +flag which can potentially be unclear about what you will get. This is +especially important in macros and structures where register numbers may be +unknown until instantiated. + +Both syntaxes support triple and double register operands: "add r0,r0,r1" can +be shortened to "add r0,r1" + +_______________________________________________________________________________ + 3. IT block handling + +In THUMB mode fasmarm can insert IT blocks automatically: + + thumb ;use UAL syntax + ;itet eq ;fasmarm inserts an automatic "IT EQ" block + subeq r0,r1 ;T(rue) = eq + subsne r2,r3 ;E(lse) = ne + subseq r4,r5 ;T(rue) = eq + + +fasmarm will check that manually placed IT blocks are consistent with +subsequent code: + + thumb ;use UAL syntax + itet eq ;manually placed IT block + subeq r0,r1 ;T(rue) = eq, fasmarm checks the conditions are matched + subsne r2,r3 ;E(lse) = ne, fasmarm checks the conditions are matched + subseq r4,r5 ;T(rue) = eq, fasmarm checks the conditions are matched + + +IT blocks cannot span across labels: + + thumb ;use UAL syntax + ;it eq ;fasmarm inserts an automatic "IT EQ" block + subeq r0,r1 ;T(rue) = eq +lab1: ;ite ne ;fasmarm inserts a new "IT NE" block + subsne r2,r3 ;T(rue) = ne + subseq r4,r5 ;E(lse) = eq + + +fasmarm will check that manually placed IT blocks do not span labels: + + ite mi ;manually placed IT block + submi r0,r1 ;T(rue) = mi, fasmarm checks the conditions are matched +lab2: subspl r2,r3 ;Error: IT block would span across the label + + +IT blocks cannot span across changes to PC: + + thumb ;use UAL syntax + ;ite eq ;fasmarm inserts an automatic "IT EQ" block + subeq r0,r1 ;T(rue) = eq + bne lab2 ;E(lse) = ne, branch will finish the IT block + ;it eq ;fasmarm inserts a new "IT EQ" block + subseq r4,r5 ;T(rue) = eq + +_______________________________________________________________________________ + 4. Alternate encodings + +fasmarm follows this principle: Find a way to encode it, the smaller the better + +What this means is that even though you may write a particular opcocde, fasmarm +may assemble another as a replacement. This can only happen where the +functionality is exactly the same. The reason for doing this is to increase the +likelihood of a successful assembly. This will only affect you if you want to +look at a disassembly listing and match it to the original source. Example: + + What you coded | What is assembled ;reason + -------------------+--------------------------------------------------- + ARM + and r0,0xfffffff0 | bic r0,0x0000000f ;immediate could not be encoded + add r1,-4 | sub r1,4 ;immediate could not be encoded + cmp r2,0xffffe500 | cmn r2,0x00001b00 ;immediate could not be encoded + lsr r1,r2,r3 | mov r1,r2,lsr r3 ;ARM mode does not have LSR + pop {r0-r3} | ldmfd r13!,{r0-r3} ;ARM mode does not have POP + mul r4,r4,r11 | mul r4,r11,r4 ;encoding restriction for + | ;CPU versions before v6 + THUMB + ldmfd r13!,{r0-r3} | pop {r0-r3} ;THUMB mode uses pop + ldmfd r10!,{r8} | ldr r8,[r10],4 ;forbidden single register LDMs + pop {r8} | ldr r8,[r13],4 ;forbidden single register POP + add r2,0x89a | addw r2,0x89a ;immediate could not be encoded + BOTH + mov r1,0x4567 | movw r1,0x4567 ;immediate could not be encoded + +Other instructions than just what is shown above are also affected. + +The last part of the principles, the smaller the better, may impact THUMB code +where a particular alignment is required. If you need to ensure that a +particular instruction is always 32-bit, or always 16-bit, then you can use the +qualifiers ".W" and ".N" after the opcodes and conditions to force either wide +(32-bit) or narrow (16-bit) encodings. If the instruction cannot be encoded in +the desired width fasmarm will give an error. If the instruction does not have +both wide an narrow forms then the .W and .N suffixes are undefined. If you +give no width suffix fasmarm will select the narrow form if it is available and +encodable, and the wide form otherwise. + +To see how this impacts code using IT blocks examine the following example: + + thumb ;use UAL syntax + sub r0,r1 ;only encodable as 32-bit outside an IT block + subs r2,r3 ;fasmarm chooses the 16-bit form + subs.w r4,r5 ;32-bit "wide" encoding forced + b .next1 + ;... + .next1: + ;ittt al ;fasmarm inserts an automatic "IT AL" block + sub r0,r1 ;fasmarm chooses the 16-bit form inside an IT block + sub r2,r3 ;fasmarm chooses the 16-bit form inside an IT block + b .next2 ;IT block extends to here + ;... + .next2: + ;itttt al ;fasmarm inserts an automatic "IT AL" block + sub r0,r1 ;fasmarm chooses the 16-bit form inside an IT block + sub r2,r3 ;fasmarm chooses the 16-bit form inside an IT block + sub r9,r5 ;high register used, only encodable as 32-bit + sub r6,r7 ;fasmarm chooses the 16-bit form inside an IT block + +The insertion of automatic "IT AL" blocks is only done when a reduction in code +size is possible. To inhibit automatic "IT AL" block insertion you can force +affected instructions to use the wide encoding with a .W suffix, or use the +directive ITNOAUTO. To enable automatic insertion of IT AL blocks use the +ITAUTO directive. ITAUTO is the default mode at startup. ITNOAUTO and ITAUTO +directives only affect IT blocks using AL. Other condition codes will still +be inserted automatically if not included explicitly. + + itauto ;enable automatic IT AL insertion from now onwards + thumb ;use UAL syntax + sub.w r0,r1 ;32-bit "wide" encoding forced + sub.w r2,r3 ;32-bit "wide" encoding forced + b .next2 + ;... + .next2: + itnoauto ;inhibit automatic IT AL insertion from now onwards + sub r0,r1 ;32-bit "wide" encoding used + sub r2,r3 ;32-bit "wide" encoding used + +_______________________________________________________________________________ + 5. Output formats + +The "format" directive will produce ARM code in all the same formats as the X86 +version plus one additional format: ELF DWARF. The ELF DWARF is compatible with +the ARM AXD debugger. The DWARF format produced includes all program labels, +line numbers and module names for full symbolic debugging. The ELF format has +been changed to set the FLAGS, code base and machine type compatible for +ARM-LINUX. The PE format has been changed to set the machine type, subsystem +and code base compatible with WinCE. PE64 format is available without +relocations. ELF64 format has not yet been updated. + +Use format like this to get the dwarf output: + + format elf dwarf executable [at ?] + +Line number and the symbol table generation are automatically enabled with this +format. Using "at" is optional and defaults to 0. + +The "section" directive for DWARF output is like this: + + section "name" [executable | readable | writeable | at ?] align ? + +The "name" is required. Align is required and must be a power of 2. All other +attributes are optional except that at least one of executable, readable or +writeable must be specified. Using "at" is optional and defaults to the next +aligned address. Attributes can be specified in any order except "name" which +must be first. + +The "org" directive is not allowed in DWARF output mode, otherwise everything +is the same as for normal ELF output. + +Relocations for ELF and PE are not supported at this time. + +_______________________________________________________________________________ + 6. Control directives + +There are five directives to control the code generation state: + + CODE64 - Switches to ARM64 (64bit instructions) code generation (alias + USE64) + CODE32 - Switches to ARM (32bit instructions) code generation (alias + USE32) + CODE16 - Switches to THUMB pre-UAL (16bit instructions) code + generation (alias USE16) + THUMB - Switches to THUMB UAL (16bit instructions) code generation + THUMBEE - Switches to ThumbEE UAL (16bit instructions) code generation + +At startup the default is CODE32. + +There are two directives to control the instruction set classes enabled: + + PROCESSOR + COPROCESSOR + +Where is a list instruction classes to enable or disable. Use a +plus symbol (+) to enable, and a minus symbol (-) to disable. By default only +the CPU32_* and COPRO_* instructions are enabled. + +To enable or disable one or more instruction classes without changing other +classes use a leading plus (+) or minus (-) to incrementally update the +settings. For example: + + processor cpu64_v8 ;enable only 64-bit version 8 base instructions + ;all other instruction classes are disabled + processor +cpu64_fp ;additionally enable the 64-bit floating point. + ;If they were already enabled then they remain + ;enabled. Other classes are unaffected. + + processor cpu64_v8 +cpu64_fp ;Both combined has the same effect as + ;above two examples. + + coprocessor -copro_vfp_v4 ;disable only the VFP V4 instructions. + ;If they were already disabled then + ;they remain disabled. Other classes + ;are unaffected. + +To query the selected instruction classes you can use the 'if' directive to do +logical tests. For example: + + if processor cpu32_v7 | processor cpu32_7m + ;do something + end if + + if coprocessor copro_vfp_v4 + ;do something + else + ;do something else + end if + +The following is a list of processor instruction classes supported: + CPU32_26BIT, CPU32_V1, CPU32_V2, CPU32_A, CPU32_V3, CPU32_M, CPU32_V4, + CPU32_V4T, CPU32_V5, CPU32_V5T, CPU32_E, CPU32_P, CPU32_J, CPU32_X, + CPU32_V6, CPU32_V6T, CPU32_ALIGN, CPU32_K, CPU32_Z, CPU32_6M, CPU32_7M, + CPU32_T2, CPU32_V7, CPU32_SYNC, CPU32_DIV, CPU32_T2EE, CPU32_MP, + CPU32_VE, CPU32_V8, CPU32_CRC, CPU64_V8, CPU64_FP, CPU64_SIMD, + CPU64_CRC, CPU64_CRYPTO + +The following is a list of coprocessor instruction classes supported: + COPRO_FPA_V1, COPRO_FPA_V2, COPRO_MAVERICK, COPRO_VFP_V1XD, + COPRO_VFP_V1, COPRO_VFP_V2, COPRO_VFP_V3, COPRO_VFP_D32, COPRO_VFP_HP, + COPRO_XSCALE, COPRO_IWMMXT_V1, COPRO_IWMMXT_V2, COPRO_SIMD_INT, + COPRO_SIMD_FLOAT, COPRO_SIMD_HP, COPRO_VFP_V4, COPRO_SIMD_V2, + COPRO_SIMD_V8, COPRO_SIMD_CRYPTO + +There are three combination instruction classes that will either enable or +disable all instructions within the class: + CPU32_ALL, CPU64_ALL, COPRO_ALL + +For backward compatibility with previous versions a single numeric constant can +be specified instead of a list of classes. This is only supported for the +following values: + + PROCESSOR supported immediate values: + CPU32_CAPABILITY_26BIT = 1 shl 00 + CPU32_CAPABILITY_V1 = 1 shl 01 + CPU32_CAPABILITY_V2 = 1 shl 02 + CPU32_CAPABILITY_A = 1 shl 03 + CPU32_CAPABILITY_V3 = 1 shl 04 + CPU32_CAPABILITY_M = 1 shl 05 + CPU32_CAPABILITY_V4 = 1 shl 06 + CPU32_CAPABILITY_V4T = 1 shl 07 + CPU32_CAPABILITY_V5 = 1 shl 08 + CPU32_CAPABILITY_V5T = 1 shl 09 + CPU32_CAPABILITY_E = 1 shl 10 + CPU32_CAPABILITY_P = 1 shl 11 + CPU32_CAPABILITY_J = 1 shl 12 + CPU32_CAPABILITY_X = 1 shl 13 + CPU32_CAPABILITY_V6 = 1 shl 14 + CPU32_CAPABILITY_V6T = 1 shl 15 + CPU32_CAPABILITY_ALIGN = 1 shl 16 + CPU32_CAPABILITY_K = 1 shl 17 + CPU32_CAPABILITY_Z = 1 shl 18 + CPU32_CAPABILITY_6M = 1 shl 19 + CPU32_CAPABILITY_7M = 1 shl 20 + CPU32_CAPABILITY_T2 = 1 shl 21 + CPU32_CAPABILITY_V7 = 1 shl 22 + CPU32_CAPABILITY_SYNC = 1 shl 23 + CPU32_CAPABILITY_DIV = 1 shl 24 + CPU32_CAPABILITY_T2EE = 1 shl 25 + CPU32_CAPABILITY_MP = 1 shl 26 + CPU32_CAPABILITY_VE = 1 shl 27 + CPU32_CAPABILITY_V8 = 1 shl 28 + CPU32_CAPABILITY_CRC = 1 shl 29 + + COPROCESSOR supported immediate values: + COPRO_CAPABILITY_FPA_V1 = 1 shl 00 + COPRO_CAPABILITY_FPA_V2 = 1 shl 01 + COPRO_CAPABILITY_MAVERICK = 1 shl 02 + COPRO_CAPABILITY_VFP_V1xD = 1 shl 03 + COPRO_CAPABILITY_VFP_V1 = 1 shl 04 + COPRO_CAPABILITY_VFP_V2 = 1 shl 05 + COPRO_CAPABILITY_VFP_V3 = 1 shl 06 + COPRO_CAPABILITY_VFP_D32 = 1 shl 07 + COPRO_CAPABILITY_VFP_HP = 1 shl 08 + COPRO_CAPABILITY_XSCALE = 1 shl 09 + COPRO_CAPABILITY_IWMMXT_V1 = 1 shl 10 + COPRO_CAPABILITY_IWMMXT_V2 = 1 shl 11 + COPRO_CAPABILITY_SIMD_INT = 1 shl 12 + COPRO_CAPABILITY_SIMD_FLOAT = 1 shl 13 + COPRO_CAPABILITY_SIMD_HP = 1 shl 14 + COPRO_CAPABILITY_VFP_V4 = 1 shl 15 + COPRO_CAPABILITY_SIMD_V2 = 1 shl 16 + COPRO_CAPABILITY_SIMD_V8 = 1 shl 17 + COPRO_CAPABILITY_SIMD_CRYPTO = 1 shl 18 + +The above symbol names and values are not defined by fasmarm. You can add them +to your source file to use them, or you can use just the raw numbers. + +There are two associated predefined symbols: %c and %p. %c is the bitmap value +of the current coprocessor set enabled. %p is the bitmap value of the current +processor set enabled. These predefined symbols only return values in the range +as shown above. That means you can't the %p value to determine if any of the +CPU64* instruction classes have been enabled. Instead use the 'if' form as +shown earlier. + +Examples using a numeric constant: + For ARM7TDMI CPUs: + processor 0xfe + coprocessor 0x0 + + For PXA25x CPUs: + processor 0x2ffe + coprocessor 0x0200 + + For PXA27x CPUs: + processor 0x2ffe + coprocessor 0x0600 + + For Cortex-A8 CPUs: + processor 0x2fffffe + coprocessor 0x30f8 + + For Cortex-A9 CPUs: + processor 0x6fffffe + coprocessor 0x30f8 + +At start-up the default is to enable the CPU32* instructions and all +coprocessors. It you want to use later instruction classes and any 64-bit +instructions these need to be specified with PROCESSOR before use. + +See the files in the ARMDOC folder for details about which instructions are +enabled by each setting. + +_______________________________________________________________________________ + 7. Data definitions + +Data definitions are different between ARM and X86. A "word" in ARM is 32 bits. + + X86 ARM comment + ---+----+--------- + DB | DB | byte: 8 bits + DW | DH | half word: 16 bits + DU | DU | half word strings: 16 bits + DD | DW | word: 32 bits + DQ | DD | double word: 64 bits + RB | RB | byte: 8 bits + RW | RH | half word: 16 bits + RD | RW | word: 32 bits + RQ | RD | double word: 64 bits + DF | -- | not valid + DP | -- | not valid + DT | -- | not valid + RF | -- | not valid + RP | -- | not valid + RT | -- | not valid + +Address sizes are always 64 bits in ARM64 state and 32 bits in ARM and THUMB +states, you can't use any address overrides. + +Data sizes are different between ARM and X86. A "word" in ARM is 32 bits. + + X86 ARM comment + --------+--------+--------------------- + BYTE | BYTE | same: 8 bits + WORD | HWORD | half word: 16 bits + DWORD | WORD | word: 32 bits + QWORD | DWORD | double word: 64 bits + DQWORD | QWORD | quad word: 128 bits + QQWORD | DQWORD | double quad word: 256 bits + +You can still use all the pre-processor and assembly features of FASM including +macros, structures, repeats etc. + +_______________________________________________________________________________ + 8. Defining registers lists inside macros + +The standard ARM syntax uses curly brackets, {}, to enclose registers lists. +The standard fasm syntax uses curly brackets to enclose macros. Both standards +are supported in fasmarm and you can mix them together. The way to state +registers lists within macros is to escape the closing curly bracket with a +leading backslash. + + macro block_copy destination, source, length { + local .loop + mov r0,source + mov r1,destination + add r2,r0,length + .loop: + ldmia r0!,{r3-r10\} ;we have to escape the closing bracket + stmia r1!,{r3-r10\} ;we have to escape the closing bracket + cmp r0,r2 + blo .loop + } + +_______________________________________________________________________________ + 9. Half-precision number formatting + +The ARM specification allows extended range half-precision numbers. Care must +be taken when defining numbers that fall within the extended range. Numbers in +the range 65520.0 to 131039.0 inclusive can be defined using the DH directive +and do not give any error. Values within this range place the exponent field at +0x1f. If the CPU is not placed into alternative half-precision (AHP) mode then +these numbers fall within the NaN and infinity encoding space. + +_______________________________________________________________________________ + 10. Variants supported + +Five standard variants of FASM binaries can been produced for FASMARM: + + FASMARM.EXE - WIN32 console + FASMWARM.EXE - WIN32 IDE + FASMARM - LINUX + FASMARM.X64 - LINUX64 console + FASMARM.O - LIBC + +_______________________________________________________________________________ + 11. Further information + +Visit http://www.arm.com for information on the ARM instruction sets and +processors. + +Visit http://flatassembler.net for the FASM x86 assembler package and tools. + +If you want to recompile the FASMARM code you will need the flatassembler +package from the above URL. + +To see what others have said and to participate in the development of fasmarm +see the active thread on the fasm message board: +http://board.flatassembler.net/topic.php?t=4191 + +If you have a problem, question, suggestion, comment etc. you can contact me at +http://board.flatassembler.net - my handle is revolution. + +_______________________________________________________________________________ + 12. Version history + +v1.44 2023-Jul-01 - Update for compatibility with fasm v1.73.30 + - MOVN/MOVZ with zero immediate now encodes any given shift + - Add Linux 64-bit version: fasmarm.x64 + - Add PE64 support for PIE code without relocations + - Fix PE header bug in SizeOf(Un)InitializedData values + - Fix errant check for thumb STRD duplicated source registers + - Add allowance for DSB, DMB and ISB to accept numeric values + - Honour two reg encoding for small immediates in thumb code + - Add missing {VPUSH|VPOP}{.32|.64} aliases + - Fix bug with 'IT LE' condition mis-tracking + - Add alias of APSR_NZCV to R15 for VMRS/FMRX + - Encode ROR by 0 to use LSL 0 + - Fix bug using LDMIA/STMDB for LDRB/STRB and LDRH/STRH + - Reduce aggressiveness of register swapping in thumb mode + - Fix detection of invalid values, this improves the + minimisation in thumb mode + - Fix STMDB/LDMIA conversion to PUsH/POP in thumb mode + - Encode single reg LDM as LDM, not as LDR, in thumb mode + - Fix bug with LDRD literal load permitting writeback + - Delay triggering of using wide instructions until 6 passes + before the last + - Add ITAUTO and ITNOAUTO directives + - Add support for '-' as input/output file in Linux, enabling + FASMARM to be used in pipeline + - Add Windows armpe64.asm example + - Add swapping of ADD(S) X?,X?,SP & W?,W?,WSP in 64-bit code + - Fix bug with ADRP erroneously giving unaligned error + - Fix ELF format flags for Version5 EABI + - Fix bug with undefined symbol used as an implicit address + giving unexpected invalid R15 usage error + - Fix crash bug in square and curly expression parsers + - Set machine type for ELF64 to AARCH64 + - Fix bug with explicit register expressions creating bad + immediate offsets + +v1.43 2017-Dec-26 - Fix a code minimisation logic regression + +v1.42 2017-Jul-23 - Fix a bug with unclosed curly and square bracket parsing + +v1.41 2016-Nov-09 - Fix a bug with forward referencing of labels in thumb mode + +v1.40 2016-May-14 - Fix a bug with unexpected size checks in 64-bit code for + immediate values not used for addressing + - Fix a bug with MOVK not respecting the shift amount when + the immediate is zero + - Change the IDE error summary dialog to show the full error + message + +v1.39 2016-May-01 - Add 64-bit v8 instructions + - Add simple expression evaluation inside address fields, + e.g. "ldr x1,[x2-4]" and/or "ldr x1,[x2,-4]" + - Add processing for lists of instruction classes to + PROCESSOR and COPROCESSOR directives + - Add 64-bit SemiHosting example program + +v1.38 2016-Apr-11 - Fixed more bugs with elf dwarf format file corruption + - Fixed a bug with "section ... at 0" not updating PC to 0 + - Fixed an encoding bug with VMULL.P8 + - Add 32-bit v8 instructions + +v1.37 2015-Nov-16 - Added code and data generation from macro lines to the line + number information table + - Fixed a bug with elf dwarf format symbol table corruption + - Fixed a bug where post-update instructions with a positive + sign (eg. ldr r0,[r1],+r2) would always be forced negative + +v1.36 2015-Oct-05 - Fixed another bug with elf dwarf format file corruption + +v1.35 2015-Oct-01 - Fixed a bug with elf dwarf format file corruption + +v1.34 2015-Jun-18 - Fixed a bug with elf section offsets using "at" + +v1.33 2015-May-28 - Added on demand memory allocation for WIN32 + - Fixed MRC bug with R15 as the destination + +v1.32 2014-Dec-21 - Update with all fasm changes as at 1.71.31 + - Change the format of the undocumented CRC32 directive + +v1.31 2014-Jan-29 - Fixed long file names error during line number processing + +v1.30 2013-Sep-12 - Fixed THUMB encoding of LDRB and LDRH. Updated for fasm + v1.71.13 + +v1.29 2012-Dec-24 - Added missing assert directive. Updated for fasm v1.71.07, + address space additions + +v1.28 2012-Jul-11 - Fixed a bug with 65-bit values in section origins + +v1.27 2012-Jun-09 - Updated for compatibility with fasm v1.70.02, 65-bit values + +v1.26 2012-Feb-24 - Added support for ARM/THUMB mode v7VE instructions + - Added support for ARM/THUMB mode VFPv4 instructions + - Added support for ARM/THUMB mode SIMDv2 instructions + - Added alternate two operand forms for absolute difference + - Removed alternate two operand forms for multiply-accumulate + +v1.25 2011-Oct-31 - Fixed a bug with BKPT handling in IT blocks in ARM mode + +v1.24 2011-Oct-29 - Fixed a bug with crashes during expression parsing + +v1.23 2011-Jul-31 - Fixed a bug with relocations corrupting patch code + +v1.22 2010-Nov-24 - Fixed a bug with handling nameless sections in dwarf format + +v1.21 2010-Oct-17 - Minimising the "code cannot be generated" problem. If the + assembler gets to a third repetition at the same state + then it takes action and uses wide instructions in + situations where the narrow instructions are causing + problems + +v1.20 2010-Sep-17 - Fixed a bug with handling of files names in dwarf format + +v1.19 2010-Sep-16 - Add support for half-precision and extended half-precision + number formatting. Compatible with fasm v1.69.24 + +v1.18 2010-Sep-09 - Update for compatibility with fasm v1.69.22 + +v1.17 2010-Sep-08 - Added support to separate byte and rotation values for + immediate values in shifter encoding + +v1.16 2010-Apr-26 - Added experimental instruction CRC32 + - Added experimental operator FIT + - Added alternate encoding logic for VMOV/VMVN 16-bit and + 32-bit forms + - Generate an error with more than 16 double registers in + FLDMD/FSTMD/VLDM/VSTM/VPOP/VPUSH + - Fixed erroneous generation of conditional instructions when + mixing VIRTUAL with IT blocks + - Fixed encoding for THUMB mode PC relative immediate + addressing when placed inside auto IT block + - Fixed encoding for WLDRx/WSTRx with PC relative addressing + +v1.15 2010-Apr-21 - Added support for ARM/THUMB mode v6T2 instructions + - Added support for ARM/THUMB mode v7 instructions + - Added support for ThumbEE instructions + - Added support for FPA coprocessors up to v2 + - Added support for VFP coprocessors up to v3 + - Added support for MAVERICK coprocessors + - Added support for Intel WMMXT coprocessors up to v2 + - Added support for Advanced SIMD coprocessors + - Added support for alternate two register data processing + operands. Implicit destination is the first operand + - Added support for expressions in addresses to access PC + relative variables and locations + - Added support for automatic efficient IT block generation + in THUMB mode + - Added support for UAL assembly syntax + - Added support for an optional hash (#) before literal + values + - Added predefined variables %c and %p + - Added ARMDOC folder with example instruction formats for + each opcode supported + - Extended the alternate encoding logic + - Changed numeric separation character from single quote (') + to underscore (_) + - Changed non-UAL SRS syntax to use a space, instead of a + comma, between the mode number and writeback operator + - Removed directives CODEFP, CODENOFP, CODEV5, CODEV6, + CODEVFP1, CODEVFP2, ARM5, ARM6, VFP1 and VFP2. Use + PROCESSOR and COPROCESSOR instead + +v1.14 2010-Feb-02 - Updated for compatibility with FASM 1.69.11 + - Changed "LDRx reg,[reg,0]!" to generate "LDRx reg,[reg,0]" + - Changed "LDRx reg,[reg],0" to generate "LDRx reg,[reg,0]" + - Changed "LDC Px,Cx,[reg,0]!" to generate + "LDC Px,Cx,[reg,0]" + - Changed "LDC Px,Cx,[reg],0" to generate + "LDC Px,Cx,[reg,0]" + - Fixed encoding for thumb mode BLX + - Fixed encoding for PKHTB without shift + - Fixed encoding for SSAT, SSAT16 + - Fixed encoding for UMAAL + - Allowed rotation parameter for SXTB, SXTH, UXTB, UXTH + +v1.13 2008-Nov-04 - Updated register restrictions for STREX, SMLALD, SMLSLD, + UMAAL, SMLALxy + - Relaxed restriction of rotation count=0 (or omitted) for + PKHTB + - Enabled THUMB mode aliases for SXTB, SXTH, UXTB, UXTH + +v1.12 2008-Jul-13 - Updated for compatibility with FASM 1.67.27 + - Fixed "error: undefined symbol" displaying the wrong line + +v1.11 2008-Mar-20 - Updated for compatibility with FASM 1.67.26 (note: no + version change) + +v1.11 2007-Aug-31 - Updated for compatibility with FASM 1.67.22 + - Fixed an address parser bug allowing "ldr rx,[constant]" + without a register base + +v1.10 2007-Mar-04 - Updated for compatibility with FASM 1.67.21 expression + calculation + - Allowed forward referencing of register based structure + addressing + - Fixed a bug in the ARMLITRL.INC when generating PC relative + offsets + +v1.09 2006-Aug-30 - Updated ARMTABLE.INC for compatibility with FASM 1.67 + binary searches + - Updated PE format to initialise several accounting fields + and also to reset the "relocs stripped" flag if relocs are + included + +v1.08 2006-Jun-09 - Fixed erroneous error with implicit r0 based addressing + - Fixed priority of unary minus to match FASM v1.66 priority + - Relaxed restrictions with register structure addresses when + using zero offset + - Enhanced MOV/MOVS to use ADD/SUB encoding when loading a + register structure member + - Generation of special encoding to allow user code to detect + unencodable immediate values and then select an alternate + coding without causing assembly errors + - Alignment bytes changed to 0xff to facilitate faster FLASH + ROM updates + - Added proc, apscall, import and literals macros to package, + see each individual file for usage and special notes + - STRUCT and RESOURCE converted from x86 to ARM format + - COREDLL.INC converted to an imports definition file + +v1.07 2006-May-26 - Patch for basic "format PE" support for WinCE + - Added ARMPE example for WinCE (2006-06-02) + - COREDLL.DLL import ordinal equates added in "COREDLL.INC" + (2006-06-02) + +v1.06 2006-Mar-03 - Updated to work within FASM version 1.66 + +v1.05 2006-Feb-14 - Patch for basic "format ELF executable" support + - Added ARMELF example + +v1.04 2005-Nov-09 - Fixed incorrect classification of data/code when using + TIMES + - Improved line number embedding generation for more + efficient tables + +v1.03 2005-Oct-20 - Fixed IF/ELSE/END IF skip bug with commas + +v1.02 2005-Oct-03 - Fixed CPS mode change code generation + - Fixed THUMB ASR and LSR shift range check + +v1.01 2005-Oct-01 - Fixed STMIA THUMB instruction checking for base register + validity + - Fixed error deferring for some expressions + - Fixed shift count of 32 + - Added ARMv6 instructions + - Added VFPv2 instructions + - Added register aliases a1-a4, v1-v8, sb, sl, fp, ip + - Added CODE16, CODE32, CODEFP, CODENOFP, CODEV5, CODEV6, + CODEVFP1, CODEVFP2 directives + - Added ARM5, ARM6, VFP1, VFP2 combination directives + - Enforced code typing (generates an error if new + instructions are used but not enabled) + - Enforced VFP to be explicitly enabled before use + - Removed condition code "NV" + +v1 2005-Sep-29 - First public release + +(C) 01-Jul-2023 revolution diff --git a/armdoc/InstructionFormatsARM.asm b/armdoc/InstructionFormatsARM.asm new file mode 100644 index 0000000..2ae7ac5 --- /dev/null +++ b/armdoc/InstructionFormatsARM.asm @@ -0,0 +1,1884 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition or flag +;writeback ("s") syntaxes. Almost all instructions can +;be conditional. The condition code should be added at +;the end of the main opcode and before any size/type +;specifiers. For example: "addhi" and "vaddhi.i16". The +;syntax also supports the pre-UAL style of putting the +;condition before any modifiers like "s" or "fd". For +;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +processor CPU32_26BIT + + cmnp r0,1 + cmnp r0,1,2 + cmnp r0,r1 + cmnp r0,r1,rrx + cmnp r0,r1,lsl 2 + cmnp r0,r1,lsr 2 + cmnp r0,r1,asr 2 + cmnp r0,r1,ror 2 + cmnp r0,r1,lsl r2 + cmnp r0,r1,lsr r2 + cmnp r0,r1,asr r2 + cmnp r0,r1,ror r2 + + cmpp r0,1 + cmpp r0,1,2 + cmpp r0,r1 + cmpp r0,r1,rrx + cmpp r0,r1,lsl 2 + cmpp r0,r1,lsr 2 + cmpp r0,r1,asr 2 + cmpp r0,r1,ror 2 + cmpp r0,r1,lsl r2 + cmpp r0,r1,lsr r2 + cmpp r0,r1,asr r2 + cmpp r0,r1,ror r2 + + teqp r0,1 + teqp r0,1,2 + teqp r0,r1 + teqp r0,r1,rrx + teqp r0,r1,lsl 2 + teqp r0,r1,lsr 2 + teqp r0,r1,asr 2 + teqp r0,r1,ror 2 + teqp r0,r1,lsl r2 + teqp r0,r1,lsr r2 + teqp r0,r1,asr r2 + teqp r0,r1,ror r2 + + tstp r0,1 + tstp r0,1,2 + tstp r0,r1 + tstp r0,r1,rrx + tstp r0,r1,lsl 2 + tstp r0,r1,lsr 2 + tstp r0,r1,asr 2 + tstp r0,r1,ror 2 + tstp r0,r1,lsl r2 + tstp r0,r1,lsr r2 + tstp r0,r1,asr r2 + tstp r0,r1,ror r2 + +processor CPU32_V1 + + adc r0,1 + adc r0,1,2 + adc r0,r1 + adc r0,r1,rrx + adc r0,r1,lsl 2 + adc r0,r1,lsr 2 + adc r0,r1,asr 2 + adc r0,r1,ror 2 + adc r0,r1,lsl r2 + adc r0,r1,lsr r2 + adc r0,r1,asr r2 + adc r0,r1,ror r2 + adc r0,r1,2 + adc r0,r1,2,4 + adc r0,r1,r2 + adc r0,r1,r2,rrx + adc r0,r1,r2,lsl 3 + adc r0,r1,r2,lsr 3 + adc r0,r1,r2,asr 3 + adc r0,r1,r2,ror 3 + adc r0,r1,r2,lsl r3 + adc r0,r1,r2,lsr r3 + adc r0,r1,r2,asr r3 + adc r0,r1,r2,ror r3 + + add r0,1 + add r0,1,2 + add r0,r1 + add r0,r1,rrx + add r0,r1,lsl 2 + add r0,r1,lsr 2 + add r0,r1,asr 2 + add r0,r1,ror 2 + add r0,r1,lsl r2 + add r0,r1,lsr r2 + add r0,r1,asr r2 + add r0,r1,ror r2 + add r0,r1,2 + add r0,r1,2,4 + add r0,r1,r2 + add r0,r1,r2,rrx + add r0,r1,r2,lsl 3 + add r0,r1,r2,lsr 3 + add r0,r1,r2,asr 3 + add r0,r1,r2,ror 3 + add r0,r1,r2,lsl r3 + add r0,r1,r2,lsr r3 + add r0,r1,r2,asr r3 + add r0,r1,r2,ror r3 + + addw r0,1 + addw r0,r1,2 + + label_adr: + adr r0,label_adr + + and r0,1 + and r0,1,2 + and r0,r1 + and r0,r1,rrx + and r0,r1,lsl 2 + and r0,r1,lsr 2 + and r0,r1,asr 2 + and r0,r1,ror 2 + and r0,r1,lsl r2 + and r0,r1,lsr r2 + and r0,r1,asr r2 + and r0,r1,ror r2 + and r0,r1,2 + and r0,r1,2,4 + and r0,r1,r2 + and r0,r1,r2,rrx + and r0,r1,r2,lsl 3 + and r0,r1,r2,lsr 3 + and r0,r1,r2,asr 3 + and r0,r1,r2,ror 3 + and r0,r1,r2,lsl r3 + and r0,r1,r2,lsr r3 + and r0,r1,r2,asr r3 + and r0,r1,r2,ror r3 + + asr r0,1 + asr r0,r1 + asr r0,r1,2 + asr r0,r1,r2 + + label_b: + b label_b + + bic r0,1 + bic r0,1,2 + bic r0,r1 + bic r0,r1,rrx + bic r0,r1,lsl 2 + bic r0,r1,lsr 2 + bic r0,r1,asr 2 + bic r0,r1,ror 2 + bic r0,r1,lsl r2 + bic r0,r1,lsr r2 + bic r0,r1,asr r2 + bic r0,r1,ror r2 + bic r0,r1,2 + bic r0,r1,2,4 + bic r0,r1,r2 + bic r0,r1,r2,rrx + bic r0,r1,r2,lsl 3 + bic r0,r1,r2,lsr 3 + bic r0,r1,r2,asr 3 + bic r0,r1,r2,ror 3 + bic r0,r1,r2,lsl r3 + bic r0,r1,r2,lsr r3 + bic r0,r1,r2,asr r3 + bic r0,r1,r2,ror r3 + + label_bl: + bl label_bl + + cmn r0,1 + cmn r0,1,2 + cmn r0,r1 + cmn r0,r1,rrx + cmn r0,r1,lsl 2 + cmn r0,r1,lsr 2 + cmn r0,r1,asr 2 + cmn r0,r1,ror 2 + cmn r0,r1,lsl r2 + cmn r0,r1,lsr r2 + cmn r0,r1,asr r2 + cmn r0,r1,ror r2 + + cmp r0,1 + cmp r0,1,2 + cmp r0,r1 + cmp r0,r1,rrx + cmp r0,r1,lsl 2 + cmp r0,r1,lsr 2 + cmp r0,r1,asr 2 + cmp r0,r1,ror 2 + cmp r0,r1,lsl r2 + cmp r0,r1,lsr r2 + cmp r0,r1,asr r2 + cmp r0,r1,ror r2 + + cpy r0,r1 + + eor r0,1 + eor r0,1,2 + eor r0,r1 + eor r0,r1,rrx + eor r0,r1,lsl 2 + eor r0,r1,lsr 2 + eor r0,r1,asr 2 + eor r0,r1,ror 2 + eor r0,r1,lsl r2 + eor r0,r1,lsr r2 + eor r0,r1,asr r2 + eor r0,r1,ror r2 + eor r0,r1,2 + eor r0,r1,2,4 + eor r0,r1,r2 + eor r0,r1,r2,rrx + eor r0,r1,r2,lsl 3 + eor r0,r1,r2,lsr 3 + eor r0,r1,r2,asr 3 + eor r0,r1,r2,ror 3 + eor r0,r1,r2,lsl r3 + eor r0,r1,r2,lsr r3 + eor r0,r1,r2,asr r3 + eor r0,r1,r2,ror r3 + + ldm r0,{r1} + ldm r0,{r1,r2} + ldm r0,{r1-r3} + ldm r0,{r1-r3,r5} + ldm r0,{r1}^ + ldm r0,{r1,r2}^ + ldm r0,{r1-r3}^ + ldm r0,{r1-r3,r5}^ + ldm r0!,{r1} + ldm r0!,{r1,r2} + ldm r0!,{r1-r3} + ldm r0!,{r1-r3,r5} + ldm r0!,{r15}^ + ldm r0!,{r1,r2,r15}^ + ldm r0!,{r1-r3,r15}^ + ldm r0!,{r1-r3,r15}^ + + ldmda r0,{r1} + ldmda r0,{r1,r2} + ldmda r0,{r1-r3} + ldmda r0,{r1-r3,r5} + ldmda r0,{r1}^ + ldmda r0,{r1,r2}^ + ldmda r0,{r1-r3}^ + ldmda r0,{r1-r3,r5}^ + ldmda r0!,{r1} + ldmda r0!,{r1,r2} + ldmda r0!,{r1-r3} + ldmda r0!,{r1-r3,r5} + ldmda r0!,{r15}^ + ldmda r0!,{r1,r2,r15}^ + ldmda r0!,{r1-r3,r15}^ + ldmda r0!,{r1-r3,r15}^ + + ldmdb r0,{r1} + ldmdb r0,{r1,r2} + ldmdb r0,{r1-r3} + ldmdb r0,{r1-r3,r5} + ldmdb r0,{r1}^ + ldmdb r0,{r1,r2}^ + ldmdb r0,{r1-r3}^ + ldmdb r0,{r1-r3,r5}^ + ldmdb r0!,{r1} + ldmdb r0!,{r1,r2} + ldmdb r0!,{r1-r3} + ldmdb r0!,{r1-r3,r5} + ldmdb r0!,{r15}^ + ldmdb r0!,{r1,r2,r15}^ + ldmdb r0!,{r1-r3,r15}^ + ldmdb r0!,{r1-r3,r15}^ + + ldmea r0,{r1} + ldmea r0,{r1,r2} + ldmea r0,{r1-r3} + ldmea r0,{r1-r3,r5} + ldmea r0,{r1}^ + ldmea r0,{r1,r2}^ + ldmea r0,{r1-r3}^ + ldmea r0,{r1-r3,r5}^ + ldmea r0!,{r1} + ldmea r0!,{r1,r2} + ldmea r0!,{r1-r3} + ldmea r0!,{r1-r3,r5} + ldmea r0!,{r15}^ + ldmea r0!,{r1,r2,r15}^ + ldmea r0!,{r1-r3,r15}^ + ldmea r0!,{r1-r3,r15}^ + + ldmed r0,{r1} + ldmed r0,{r1,r2} + ldmed r0,{r1-r3} + ldmed r0,{r1-r3,r5} + ldmed r0,{r1}^ + ldmed r0,{r1,r2}^ + ldmed r0,{r1-r3}^ + ldmed r0,{r1-r3,r5}^ + ldmed r0!,{r1} + ldmed r0!,{r1,r2} + ldmed r0!,{r1-r3} + ldmed r0!,{r1-r3,r5} + ldmed r0!,{r15}^ + ldmed r0!,{r1,r2,r15}^ + ldmed r0!,{r1-r3,r15}^ + ldmed r0!,{r1-r3,r15}^ + + ldmfa r0,{r1} + ldmfa r0,{r1,r2} + ldmfa r0,{r1-r3} + ldmfa r0,{r1-r3,r5} + ldmfa r0,{r1}^ + ldmfa r0,{r1,r2}^ + ldmfa r0,{r1-r3}^ + ldmfa r0,{r1-r3,r5}^ + ldmfa r0!,{r1} + ldmfa r0!,{r1,r2} + ldmfa r0!,{r1-r3} + ldmfa r0!,{r1-r3,r5} + ldmfa r0!,{r15}^ + ldmfa r0!,{r1,r2,r15}^ + ldmfa r0!,{r1-r3,r15}^ + ldmfa r0!,{r1-r3,r15}^ + + ldmfd r0,{r1} + ldmfd r0,{r1,r2} + ldmfd r0,{r1-r3} + ldmfd r0,{r1-r3,r5} + ldmfd r0,{r1}^ + ldmfd r0,{r1,r2}^ + ldmfd r0,{r1-r3}^ + ldmfd r0,{r1-r3,r5}^ + ldmfd r0!,{r1} + ldmfd r0!,{r1,r2} + ldmfd r0!,{r1-r3} + ldmfd r0!,{r1-r3,r5} + ldmfd r0!,{r15}^ + ldmfd r0!,{r1,r2,r15}^ + ldmfd r0!,{r1-r3,r15}^ + ldmfd r0!,{r1-r3,r15}^ + + ldmia r0,{r1} + ldmia r0,{r1,r2} + ldmia r0,{r1-r3} + ldmia r0,{r1-r3,r5} + ldmia r0,{r1}^ + ldmia r0,{r1,r2}^ + ldmia r0,{r1-r3}^ + ldmia r0,{r1-r3,r5}^ + ldmia r0!,{r1} + ldmia r0!,{r1,r2} + ldmia r0!,{r1-r3} + ldmia r0!,{r1-r3,r5} + ldmia r0!,{r15}^ + ldmia r0!,{r1,r2,r15}^ + ldmia r0!,{r1-r3,r15}^ + ldmia r0!,{r1-r3,r15}^ + + ldmib r0,{r1} + ldmib r0,{r1,r2} + ldmib r0,{r1-r3} + ldmib r0,{r1-r3,r5} + ldmib r0,{r1}^ + ldmib r0,{r1,r2}^ + ldmib r0,{r1-r3}^ + ldmib r0,{r1-r3,r5}^ + ldmib r0!,{r1} + ldmib r0!,{r1,r2} + ldmib r0!,{r1-r3} + ldmib r0!,{r1-r3,r5} + ldmib r0!,{r15}^ + ldmib r0!,{r1,r2,r15}^ + ldmib r0!,{r1-r3,r15}^ + ldmib r0!,{r1-r3,r15}^ + + label_ldr: + ldr r0,[r1] + ldr r0,[r1],+r2 + ldr r0,[r1],-r2 + ldr r0,[r1],-r2,lsl 3 + ldr r0,[r1],r2,lsr 3 + ldr r0,[r1],r2,asr 3 + ldr r0,[r1],r2,ror 3 + ldr r0,[r1],-r2,lsl 3 + ldr r0,[r1],-r2,lsr 3 + ldr r0,[r1],-r2,asr 3 + ldr r0,[r1],-r2,ror 3 + ldr r0,[r1],r2,rrx + ldr r0,[r1],-r2,rrx + ldr r0,[r1],2 + ldr r0,[r1,2] + ldr r0,[r1,2]! + ldr r0,[r1,r2] + ldr r0,[r1,-r2] + ldr r0,[r1,r2]! + ldr r0,[r1,-r2]! + ldr r0,[r1,r2,lsl 3] + ldr r0,[r1,r2,lsr 3] + ldr r0,[r1,r2,asr 3] + ldr r0,[r1,r2,ror 3] + ldr r0,[r1,-r2,lsl 3] + ldr r0,[r1,-r2,lsr 3] + ldr r0,[r1,-r2,asr 3] + ldr r0,[r1,-r2,ror 3] + ldr r0,[r1,r2,lsl 3]! + ldr r0,[r1,r2,lsr 3]! + ldr r0,[r1,r2,asr 3]! + ldr r0,[r1,r2,ror 3]! + ldr r0,[r1,-r2,lsl 3]! + ldr r0,[r1,-r2,lsr 3]! + ldr r0,[r1,-r2,asr 3]! + ldr r0,[r1,-r2,ror 3]! + ldr r0,[r1,r2,rrx] + ldr r0,[r1,-r2,rrx] + ldr r0,[r1,r2,rrx]! + ldr r0,[r1,-r2,rrx]! + ldr r0,[label_ldr] + ldr r0,[expression.word] + ldr r0,[expression.word]! + + label_ldrb: + ldrb r0,[r1] + ldrb r0,[r1],r2 + ldrb r0,[r1],-r2 + ldrb r0,[r1],-r2,lsl 3 + ldrb r0,[r1],r2,lsr 3 + ldrb r0,[r1],r2,asr 3 + ldrb r0,[r1],r2,ror 3 + ldrb r0,[r1],-r2,lsl 3 + ldrb r0,[r1],-r2,lsr 3 + ldrb r0,[r1],-r2,asr 3 + ldrb r0,[r1],-r2,ror 3 + ldrb r0,[r1],r2,rrx + ldrb r0,[r1],-r2,rrx + ldrb r0,[r1],2 + ldrb r0,[r1,2] + ldrb r0,[r1,2]! + ldrb r0,[r1,r2] + ldrb r0,[r1,-r2] + ldrb r0,[r1,r2]! + ldrb r0,[r1,-r2]! + ldrb r0,[r1,r2,lsl 3] + ldrb r0,[r1,r2,lsr 3] + ldrb r0,[r1,r2,asr 3] + ldrb r0,[r1,r2,ror 3] + ldrb r0,[r1,-r2,lsl 3] + ldrb r0,[r1,-r2,lsr 3] + ldrb r0,[r1,-r2,asr 3] + ldrb r0,[r1,-r2,ror 3] + ldrb r0,[r1,r2,lsl 3]! + ldrb r0,[r1,r2,lsr 3]! + ldrb r0,[r1,r2,asr 3]! + ldrb r0,[r1,r2,ror 3]! + ldrb r0,[r1,-r2,lsl 3]! + ldrb r0,[r1,-r2,lsr 3]! + ldrb r0,[r1,-r2,asr 3]! + ldrb r0,[r1,-r2,ror 3]! + ldrb r0,[r1,r2,rrx] + ldrb r0,[r1,-r2,rrx] + ldrb r0,[r1,r2,rrx]! + ldrb r0,[r1,-r2,rrx]! + ldrb r0,[label_ldrb] + ldrb r0,[expression.byte] + ldrb r0,[expression.byte]! + + ldrbt r0,[r1] + ldrbt r0,[r1],r2 + ldrbt r0,[r1],-r2 + ldrbt r0,[r1],r2,lsl 3 + ldrbt r0,[r1],r2,lsr 3 + ldrbt r0,[r1],r2,asr 3 + ldrbt r0,[r1],r2,ror 3 + ldrbt r0,[r1],-r2,lsl 3 + ldrbt r0,[r1],-r2,lsr 3 + ldrbt r0,[r1],-r2,asr 3 + ldrbt r0,[r1],-r2,ror 3 + ldrbt r0,[r1],r2,rrx + ldrbt r0,[r1],-r2,rrx + ldrbt r0,[r1],2 + + ldrt r0,[r1] + ldrt r0,[r1],r2 + ldrt r0,[r1],-r2 + ldrt r0,[r1],r2,lsl 3 + ldrt r0,[r1],r2,lsr 3 + ldrt r0,[r1],r2,asr 3 + ldrt r0,[r1],r2,ror 3 + ldrt r0,[r1],-r2,lsl 3 + ldrt r0,[r1],-r2,lsr 3 + ldrt r0,[r1],-r2,asr 3 + ldrt r0,[r1],-r2,ror 3 + ldrt r0,[r1],r2,rrx + ldrt r0,[r1],-r2,rrx + ldrt r0,[r1],2 + + lsl r0,1 + lsl r0,r1 + lsl r0,r1,2 + lsl r0,r1,r2 + + lsr r0,1 + lsr r0,r1 + lsr r0,r1,2 + lsr r0,r1,r2 + + mov r0,1 + mov r0,1,2 + mov r0,r1 + mov r0,r1,rrx + mov r0,r1,lsl 2 + mov r0,r1,lsr 2 + mov r0,r1,asr 2 + mov r0,r1,ror 2 + mov r0,r1,lsl r2 + mov r0,r1,lsr r2 + mov r0,r1,asr r2 + mov r0,r1,ror r2 + mov r0,expression.word + + mvn r0,1 + mvn r0,1,2 + mvn r0,r1 + mvn r0,r1,rrx + mvn r0,r1,lsl 2 + mvn r0,r1,lsr 2 + mvn r0,r1,asr 2 + mvn r0,r1,ror 2 + mvn r0,r1,lsl r2 + mvn r0,r1,lsr r2 + mvn r0,r1,asr r2 + mvn r0,r1,ror r2 + + neg r0 + neg r0,r1 + + nop + + orr r0,1 + orr r0,1,2 + orr r0,r1 + orr r0,r1,rrx + orr r0,r1,lsl 2 + orr r0,r1,lsr 2 + orr r0,r1,asr 2 + orr r0,r1,ror 2 + orr r0,r1,lsl r2 + orr r0,r1,lsr r2 + orr r0,r1,asr r2 + orr r0,r1,ror r2 + orr r0,r1,2 + orr r0,r1,2,4 + orr r0,r1,r2 + orr r0,r1,r2,rrx + orr r0,r1,r2,lsl 3 + orr r0,r1,r2,lsr 3 + orr r0,r1,r2,asr 3 + orr r0,r1,r2,ror 3 + orr r0,r1,r2,lsl r3 + orr r0,r1,r2,lsr r3 + orr r0,r1,r2,asr r3 + orr r0,r1,r2,ror r3 + + pop {r0} + pop {r0,r1} + pop {r0-r2} + pop {r0-r2,r4} + + push {r0} + push {r0,r1} + push {r0-r2} + push {r0-r2,r4} + + ror r0,1 + ror r0,r1 + ror r0,r1,2 + ror r0,r1,r2 + + rrx r0 + rrx r0,r1 + + rsb r0,1 + rsb r0,1,2 + rsb r0,r1 + rsb r0,r1,rrx + rsb r0,r1,lsl 2 + rsb r0,r1,lsr 2 + rsb r0,r1,asr 2 + rsb r0,r1,ror 2 + rsb r0,r1,lsl r2 + rsb r0,r1,lsr r2 + rsb r0,r1,asr r2 + rsb r0,r1,ror r2 + rsb r0,r1,2 + rsb r0,r1,2,4 + rsb r0,r1,r2 + rsb r0,r1,r2,rrx + rsb r0,r1,r2,lsl 3 + rsb r0,r1,r2,lsr 3 + rsb r0,r1,r2,asr 3 + rsb r0,r1,r2,ror 3 + rsb r0,r1,r2,lsl r3 + rsb r0,r1,r2,lsr r3 + rsb r0,r1,r2,asr r3 + rsb r0,r1,r2,ror r3 + + rsc r0,1 + rsc r0,1,2 + rsc r0,r1 + rsc r0,r1,rrx + rsc r0,r1,lsl 2 + rsc r0,r1,lsr 2 + rsc r0,r1,asr 2 + rsc r0,r1,ror 2 + rsc r0,r1,lsl r2 + rsc r0,r1,lsr r2 + rsc r0,r1,asr r2 + rsc r0,r1,ror r2 + rsc r0,r1,2 + rsc r0,r1,2,4 + rsc r0,r1,r2 + rsc r0,r1,r2,rrx + rsc r0,r1,r2,lsl 3 + rsc r0,r1,r2,lsr 3 + rsc r0,r1,r2,asr 3 + rsc r0,r1,r2,ror 3 + rsc r0,r1,r2,lsl r3 + rsc r0,r1,r2,lsr r3 + rsc r0,r1,r2,asr r3 + rsc r0,r1,r2,ror r3 + + sbc r0,1 + sbc r0,1,2 + sbc r0,r1 + sbc r0,r1,rrx + sbc r0,r1,lsl 2 + sbc r0,r1,lsr 2 + sbc r0,r1,asr 2 + sbc r0,r1,ror 2 + sbc r0,r1,lsl r2 + sbc r0,r1,lsr r2 + sbc r0,r1,asr r2 + sbc r0,r1,ror r2 + sbc r0,r1,2 + sbc r0,r1,2,4 + sbc r0,r1,r2 + sbc r0,r1,r2,rrx + sbc r0,r1,r2,lsl 3 + sbc r0,r1,r2,lsr 3 + sbc r0,r1,r2,asr 3 + sbc r0,r1,r2,ror 3 + sbc r0,r1,r2,lsl r3 + sbc r0,r1,r2,lsr r3 + sbc r0,r1,r2,asr r3 + sbc r0,r1,r2,ror r3 + + stm r0,{r1} + stm r0,{r1,r2} + stm r0,{r1-r3} + stm r0,{r1-r3,r5} + stm r0,{r1}^ + stm r0,{r1,r2}^ + stm r0,{r1-r3}^ + stm r0,{r1-r3,r5}^ + stm r0!,{r1} + stm r0!,{r1,r2} + stm r0!,{r1-r3} + stm r0!,{r1-r3,r5} + + stmda r0,{r1} + stmda r0,{r1,r2} + stmda r0,{r1-r3} + stmda r0,{r1-r3,r5} + stmda r0,{r1}^ + stmda r0,{r1,r2}^ + stmda r0,{r1-r3}^ + stmda r0,{r1-r3,r5}^ + stmda r0!,{r1} + stmda r0!,{r1,r2} + stmda r0!,{r1-r3} + stmda r0!,{r1-r3,r5} + + stmdb r0,{r1} + stmdb r0,{r1,r2} + stmdb r0,{r1-r3} + stmdb r0,{r1-r3,r5} + stmdb r0,{r1}^ + stmdb r0,{r1,r2}^ + stmdb r0,{r1-r3}^ + stmdb r0,{r1-r3,r5}^ + stmdb r0!,{r1} + stmdb r0!,{r1,r2} + stmdb r0!,{r1-r3} + stmdb r0!,{r1-r3,r5} + + stmea r0,{r1} + stmea r0,{r1,r2} + stmea r0,{r1-r3} + stmea r0,{r1-r3,r5} + stmea r0,{r1}^ + stmea r0,{r1,r2}^ + stmea r0,{r1-r3}^ + stmea r0,{r1-r3,r5}^ + stmea r0!,{r1} + stmea r0!,{r1,r2} + stmea r0!,{r1-r3} + stmea r0!,{r1-r3,r5} + + stmed r0,{r1} + stmed r0,{r1,r2} + stmed r0,{r1-r3} + stmed r0,{r1-r3,r5} + stmed r0,{r1}^ + stmed r0,{r1,r2}^ + stmed r0,{r1-r3}^ + stmed r0,{r1-r3,r5}^ + stmed r0!,{r1} + stmed r0!,{r1,r2} + stmed r0!,{r1-r3} + stmed r0!,{r1-r3,r5} + + stmfa r0,{r1} + stmfa r0,{r1,r2} + stmfa r0,{r1-r3} + stmfa r0,{r1-r3,r5} + stmfa r0,{r1}^ + stmfa r0,{r1,r2}^ + stmfa r0,{r1-r3}^ + stmfa r0,{r1-r3,r5}^ + stmfa r0!,{r1} + stmfa r0!,{r1,r2} + stmfa r0!,{r1-r3} + stmfa r0!,{r1-r3,r5} + + stmfd r0,{r1} + stmfd r0,{r1,r2} + stmfd r0,{r1-r3} + stmfd r0,{r1-r3,r5} + stmfd r0,{r1}^ + stmfd r0,{r1,r2}^ + stmfd r0,{r1-r3}^ + stmfd r0,{r1-r3,r5}^ + stmfd r0!,{r1} + stmfd r0!,{r1,r2} + stmfd r0!,{r1-r3} + stmfd r0!,{r1-r3,r5} + + stmia r0,{r1} + stmia r0,{r1,r2} + stmia r0,{r1-r3} + stmia r0,{r1-r3,r5} + stmia r0,{r1}^ + stmia r0,{r1,r2}^ + stmia r0,{r1-r3}^ + stmia r0,{r1-r3,r5}^ + stmia r0!,{r1} + stmia r0!,{r1,r2} + stmia r0!,{r1-r3} + stmia r0!,{r1-r3,r5} + + stmib r0,{r1} + stmib r0,{r1,r2} + stmib r0,{r1-r3} + stmib r0,{r1-r3,r5} + stmib r0,{r1}^ + stmib r0,{r1,r2}^ + stmib r0,{r1-r3}^ + stmib r0,{r1-r3,r5}^ + stmib r0!,{r1} + stmib r0!,{r1,r2} + stmib r0!,{r1-r3} + stmib r0!,{r1-r3,r5} + + label_str: + str r0,[r1] + str r0,[r1],r2 + str r0,[r1],-r2 + str r0,[r1],-r2,lsl 3 + str r0,[r1],r2,lsr 3 + str r0,[r1],r2,asr 3 + str r0,[r1],r2,ror 3 + str r0,[r1],-r2,lsl 3 + str r0,[r1],-r2,lsr 3 + str r0,[r1],-r2,asr 3 + str r0,[r1],-r2,ror 3 + str r0,[r1],r2,rrx + str r0,[r1],-r2,rrx + str r0,[r1],2 + str r0,[r1,2] + str r0,[r1,2]! + str r0,[r1,r2] + str r0,[r1,-r2] + str r0,[r1,r2]! + str r0,[r1,-r2]! + str r0,[r1,r2,lsl 3] + str r0,[r1,r2,lsr 3] + str r0,[r1,r2,asr 3] + str r0,[r1,r2,ror 3] + str r0,[r1,-r2,lsl 3] + str r0,[r1,-r2,lsr 3] + str r0,[r1,-r2,asr 3] + str r0,[r1,-r2,ror 3] + str r0,[r1,r2,lsl 3]! + str r0,[r1,r2,lsr 3]! + str r0,[r1,r2,asr 3]! + str r0,[r1,r2,ror 3]! + str r0,[r1,-r2,lsl 3]! + str r0,[r1,-r2,lsr 3]! + str r0,[r1,-r2,asr 3]! + str r0,[r1,-r2,ror 3]! + str r0,[r1,r2,rrx] + str r0,[r1,-r2,rrx] + str r0,[r1,r2,rrx]! + str r0,[r1,-r2,rrx]! + str r0,[label_str] + str r0,[expression.word] + str r0,[expression.word]! + + label_strb: + strb r0,[r1] + strb r0,[r1],r2 + strb r0,[r1],-r2 + strb r0,[r1],-r2,lsl 3 + strb r0,[r1],r2,lsr 3 + strb r0,[r1],r2,asr 3 + strb r0,[r1],r2,ror 3 + strb r0,[r1],-r2,lsl 3 + strb r0,[r1],-r2,lsr 3 + strb r0,[r1],-r2,asr 3 + strb r0,[r1],-r2,ror 3 + strb r0,[r1],r2,rrx + strb r0,[r1],-r2,rrx + strb r0,[r1],2 + strb r0,[r1,2] + strb r0,[r1,2]! + strb r0,[r1,r2] + strb r0,[r1,-r2] + strb r0,[r1,r2]! + strb r0,[r1,-r2]! + strb r0,[r1,r2,lsl 3] + strb r0,[r1,r2,lsr 3] + strb r0,[r1,r2,asr 3] + strb r0,[r1,r2,ror 3] + strb r0,[r1,-r2,lsl 3] + strb r0,[r1,-r2,lsr 3] + strb r0,[r1,-r2,asr 3] + strb r0,[r1,-r2,ror 3] + strb r0,[r1,r2,lsl 3]! + strb r0,[r1,r2,lsr 3]! + strb r0,[r1,r2,asr 3]! + strb r0,[r1,r2,ror 3]! + strb r0,[r1,-r2,lsl 3]! + strb r0,[r1,-r2,lsr 3]! + strb r0,[r1,-r2,asr 3]! + strb r0,[r1,-r2,ror 3]! + strb r0,[r1,r2,rrx] + strb r0,[r1,-r2,rrx] + strb r0,[r1,r2,rrx]! + strb r0,[r1,-r2,rrx]! + strb r0,[label_strb] + strb r0,[expression.byte] + strb r0,[expression.byte]! + + strbt r0,[r1] + strbt r0,[r1],r2 + strbt r0,[r1],-r2 + strbt r0,[r1],r2,lsl 3 + strbt r0,[r1],r2,lsr 3 + strbt r0,[r1],r2,asr 3 + strbt r0,[r1],r2,ror 3 + strbt r0,[r1],-r2,lsl 3 + strbt r0,[r1],-r2,lsr 3 + strbt r0,[r1],-r2,asr 3 + strbt r0,[r1],-r2,ror 3 + strbt r0,[r1],r2,rrx + strbt r0,[r1],-r2,rrx + strbt r0,[r1],2 + + strt r0,[r1] + strt r0,[r1],r2 + strt r0,[r1],-r2 + strt r0,[r1],r2,lsl 3 + strt r0,[r1],r2,lsr 3 + strt r0,[r1],r2,asr 3 + strt r0,[r1],r2,ror 3 + strt r0,[r1],-r2,lsl 3 + strt r0,[r1],-r2,lsr 3 + strt r0,[r1],-r2,asr 3 + strt r0,[r1],-r2,ror 3 + strt r0,[r1],r2,rrx + strt r0,[r1],-r2,rrx + strt r0,[r1],2 + + sub r0,1 + sub r0,1,2 + sub r0,r1 + sub r0,r1,rrx + sub r0,r1,lsl 2 + sub r0,r1,lsr 2 + sub r0,r1,asr 2 + sub r0,r1,ror 2 + sub r0,r1,lsl r2 + sub r0,r1,lsr r2 + sub r0,r1,asr r2 + sub r0,r1,ror r2 + sub r0,r1,2 + sub r0,r1,2,4 + sub r0,r1,r2 + sub r0,r1,r2,rrx + sub r0,r1,r2,lsl 3 + sub r0,r1,r2,lsr 3 + sub r0,r1,r2,asr 3 + sub r0,r1,r2,ror 3 + sub r0,r1,r2,lsl r3 + sub r0,r1,r2,lsr r3 + sub r0,r1,r2,asr r3 + sub r0,r1,r2,ror r3 + + subw r0,1 + subw r0,r1,2 + + svc 1 + + swi 1 + + teq r0,1 + teq r0,1,2 + teq r0,r1 + teq r0,r1,rrx + teq r0,r1,lsl 2 + teq r0,r1,lsr 2 + teq r0,r1,asr 2 + teq r0,r1,ror 2 + teq r0,r1,lsl r2 + teq r0,r1,lsr r2 + teq r0,r1,asr r2 + teq r0,r1,ror r2 + + tst r0,1 + tst r0,1,2 + tst r0,r1 + tst r0,r1,rrx + tst r0,r1,lsl 2 + tst r0,r1,lsr 2 + tst r0,r1,asr 2 + tst r0,r1,ror 2 + tst r0,r1,lsl r2 + tst r0,r1,lsr r2 + tst r0,r1,asr r2 + tst r0,r1,ror r2 + +processor CPU32_V2 + + cdp p9,1,c2,c3,c4 + cdp p9,1,c2,c3,c4,5 + + label_ldc: + ldc p9,c1,[r2] + ldc p9,c1,[r2],4 + ldc p9,c1,[r2],{4} + ldc p9,c1,[r2,4] + ldc p9,c1,[r2,4]! + ldc p9,c1,[label_ldc] + ldc p9,c1,[expression.word] + ldc p9,c1,[expression.word]! + + label_ldcl: + ldcl p9,c1,[r2] + ldcl p9,c1,[r2],4 + ldcl p9,c1,[r2],{4} + ldcl p9,c1,[r2,4] + ldcl p9,c1,[r2,4]! + ldcl p9,c1,[label_ldcl] + ldcl p9,c1,[expression.word] + ldcl p9,c1,[expression.word]! + + mcr p9,1,r2,c3,c4 + mcr p9,1,r2,c3,c4,5 + + mla r0,r1,r2,r3 + + mrc p9,1,r2,c3,c4 + mrc p9,1,r15,c3,c4,5 + + mul r0,r1 + mul r0,r1,r2 + + label_stc: + stc p9,c1,[r2] + stc p9,c1,[r2],4 + stc p9,c1,[r2],{4} + stc p9,c1,[r2,4] + stc p9,c1,[r2,4]! + stc p9,c1,[label_stc] + stc p9,c1,[expression.word] + stc p9,c1,[expression.word]! + + label_stcl: + stcl p9,c1,[r2] + stcl p9,c1,[r2],4 + stcl p9,c1,[r2],{4} + stcl p9,c1,[r2,4] + stcl p9,c1,[r2,4]! + stcl p9,c1,[label_stcl] + stcl p9,c1,[expression.word] + stcl p9,c1,[expression.word]! + +processor CPU32_A + + swp r0,r1,[r2] + swpb r0,r1,[r2] + +processor CPU32_V3 + + mrs r0,apsr + mrs r0,cpsr + mrs r0,spsr + + msr cpsr,r1 + msr cpsr_fsxc,r1 + msr cpsr,1 + msr cpsr_fsxc,1 + +processor CPU32_M + + smlal r0,r1,r2,r3 + + smull r0,r1,r2,r3 + + umlal r0,r1,r2,r3 + + umull r0,r1,r2,r3 + +processor CPU32_V4 + + label_ldrh: + ldrh r0,[r1] + ldrh r0,[r1],r2 + ldrh r0,[r1],-r2 + ldrh r0,[r1],2 + ldrh r0,[r1,2] + ldrh r0,[r1,2]! + ldrh r0,[r1,r2] + ldrh r0,[r1,-r2] + ldrh r0,[r1,r2]! + ldrh r0,[r1,-r2]! + ldrh r0,[label_ldrh] + ldrh r0,[expression.hword] + ldrh r0,[expression.hword]! + + label_ldrsb: + ldrsb r0,[r1] + ldrsb r0,[r1],r2 + ldrsb r0,[r1],-r2 + ldrsb r0,[r1],2 + ldrsb r0,[r1,2] + ldrsb r0,[r1,2]! + ldrsb r0,[r1,r2] + ldrsb r0,[r1,-r2] + ldrsb r0,[r1,r2]! + ldrsb r0,[r1,-r2]! + ldrsb r0,[label_ldrsb] + ldrsb r0,[expression.byte] + ldrsb r0,[expression.byte]! + + label_ldrsh: + ldrsh r0,[r1] + ldrsh r0,[r1],r2 + ldrsh r0,[r1],-r2 + ldrsh r0,[r1],2 + ldrsh r0,[r1,2] + ldrsh r0,[r1,2]! + ldrsh r0,[r1,r2] + ldrsh r0,[r1,-r2] + ldrsh r0,[r1,r2]! + ldrsh r0,[r1,-r2]! + ldrsh r0,[label_ldrsh] + ldrsh r0,[expression.hword] + ldrsh r0,[expression.hword]! + + label_strh: + strh r0,[r1] + strh r0,[r1],r2 + strh r0,[r1],-r2 + strh r0,[r1],2 + strh r0,[r1,2] + strh r0,[r1,2]! + strh r0,[r1,r2] + strh r0,[r1,-r2] + strh r0,[r1,r2]! + strh r0,[r1,-r2]! + strh r0,[label_strh] + strh r0,[expression.hword] + strh r0,[expression.hword]! + +processor CPU32_V4T + + bx r0 + +processor CPU32_V5 + + label_blx: + blx label_blx + blx r0 + + bkpt 0 + + cdp2 p9,1,c2,c3,c4 + cdp2 p9,1,c2,c3,c4,5 + + clz r0,r1 + + label_ldc2: + ldc2 p9,c1,[r2] + ldc2 p9,c1,[r2],4 + ldc2 p9,c1,[r2],{4} + ldc2 p9,c1,[r2,4] + ldc2 p9,c1,[r2,4]! + ldc2 p9,c1,[label_ldc2] + ldc2 p9,c1,[expression.word] + ldc2 p9,c1,[expression.word]! + + label_ldc2l: + ldc2l p9,c1,[r2] + ldc2l p9,c1,[r2],4 + ldc2l p9,c1,[r2],{4} + ldc2l p9,c1,[r2,4] + ldc2l p9,c1,[r2,4]! + ldc2l p9,c1,[label_ldc2l] + ldc2l p9,c1,[expression.word] + ldc2l p9,c1,[expression.word]! + + mcr2 p9,1,r2,c3,c4 + mcr2 p9,1,r2,c3,c4,5 + + mrc2 p9,1,r2,c3,c4 + mrc2 p9,1,r15,c3,c4,5 + + label_stc2: + stc2 p9,c1,[r2] + stc2 p9,c1,[r2],4 + stc2 p9,c1,[r2],{4} + stc2 p9,c1,[r2,4] + stc2 p9,c1,[r2,4]! + stc2 p9,c1,[label_stc2] + stc2 p9,c1,[expression.word] + stc2 p9,c1,[expression.word]! + + label_stc2l: + stc2l p9,c1,[r2] + stc2l p9,c1,[r2],4 + stc2l p9,c1,[r2],{4} + stc2l p9,c1,[r2,4] + stc2l p9,c1,[r2,4]! + stc2l p9,c1,[label_stc2l] + stc2l p9,c1,[expression.word] + stc2l p9,c1,[expression.word]! + +processor CPU32_E + + qadd r0,r1 + qadd r0,r1,r2 + + qdadd r0,r1 + qdadd r0,r1,r2 + + qdsub r0,r1 + qdsub r0,r1,r2 + + qsub r0,r1 + qsub r0,r1,r2 + + smlabb r0,r1,r2,r3 + + smlabt r0,r1,r2,r3 + + smlalbb r0,r1,r2,r3 + + smlalbt r0,r1,r2,r3 + + smlaltb r0,r1,r2,r3 + + smlaltt r0,r1,r2,r3 + + smlatb r0,r1,r2,r3 + + smlatt r0,r1,r2,r3 + + smlawb r0,r1,r2,r3 + + smlawt r0,r1,r2,r3 + + smulbb r0,r1 + smulbb r0,r1,r2 + + smulbt r0,r1 + smulbt r0,r1,r2 + + smultb r0,r1 + smultb r0,r1,r2 + + smultt r0,r1 + smultt r0,r1,r2 + + smulwb r0,r1 + smulwb r0,r1,r2 + + smulwt r0,r1 + smulwt r0,r1,r2 + +processor CPU32_P + + label_ldrd: + ldrd r0,[r2] + ldrd r0,[r2],r3 + ldrd r0,[r2],-r3 + ldrd r0,[r2],3 + ldrd r0,[r2,3] + ldrd r0,[r2,3]! + ldrd r0,[r2,r3] + ldrd r0,[r2,-r3] + ldrd r0,[r2,r3]! + ldrd r0,[r2,-r3]! + ldrd r0,[label_ldrd] + ldrd r0,[expression.dword] + ldrd r0,[expression.dword]! + ldrd r0,r1,[r2] + ldrd r0,r1,[r2],r3 + ldrd r0,r1,[r2],-r3 + ldrd r0,r1,[r2],3 + ldrd r0,r1,[r2,3] + ldrd r0,r1,[r2,3]! + ldrd r0,r1,[r2,r3] + ldrd r0,r1,[r2,-r3] + ldrd r0,r1,[r2,r3]! + ldrd r0,r1,[r2,-r3]! + ldrd r0,r1,[label_ldrd] + ldrd r0,r1,[expression.dword] + ldrd r0,r1,[expression.dword]! + + mcrr p9,1,r2,r3,c4 + + mrrc p9,1,r2,r3,c4 + + label_pld: + pld [r0] + pld [r0,1] + pld [r0,r1] + pld [r0,-r1] + pld [r0,r1,lsl 2] + pld [r0,r1,lsr 2] + pld [r0,r1,asr 2] + pld [r0,r1,ror 2] + pld [r0,-r1,lsl 2] + pld [r0,-r1,lsr 2] + pld [r0,-r1,asr 2] + pld [r0,-r1,ror 2] + pld [r0,r1,rrx] + pld [r0,-r1,rrx] + pld [label_pld] + pld [expression.byte] + + label_strd: + strd r0,[r2] + strd r0,[r2],r3 + strd r0,[r2],-r3 + strd r0,[r2],3 + strd r0,[r2,3] + strd r0,[r2,3]! + strd r0,[r2,r3] + strd r0,[r2,-r3] + strd r0,[r2,r3]! + strd r0,[r2,-r3]! + strd r0,[label_strd] + strd r0,[expression.dword] + strd r0,[expression.dword]! + strd r0,r1,[r2] + strd r0,r1,[r2],r3 + strd r0,r1,[r2],-r3 + strd r0,r1,[r2],3 + strd r0,r1,[r2,3] + strd r0,r1,[r2,3]! + strd r0,r1,[r2,r3] + strd r0,r1,[r2,-r3] + strd r0,r1,[r2,r3]! + strd r0,r1,[r2,-r3]! + strd r0,r1,[label_strd] + strd r0,r1,[expression.dword] + strd r0,r1,[expression.dword]! + +processor CPU32_J + + bxj r0 + +processor CPU32_V6 + + cps 0 + + cpsid iflags_a + cpsid iflags_a,1 + + cpsie iflags_a + cpsie iflags_a,1 + + ldrex r0,[r1] + ldrex r0,[r1,0] + + mcrr2 p9,1,r2,r3,c4 + + mrrc2 p9,1,r2,r3,c4 + + pkhbt r0,r1 + pkhbt r0,r1,lsl 3 + pkhbt r0,r1,r2 + pkhbt r0,r1,r2,lsl 3 + + pkhtb r0,r1 + pkhtb r0,r1,asr 3 + pkhtb r0,r1,r2 + pkhtb r0,r1,r2,asr 3 + + qadd16 r0,r1 + qadd16 r0,r1,r2 + + qadd8 r0,r1 + qadd8 r0,r1,r2 + + qaddsubx r0,r1 + qaddsubx r0,r1,r2 + + qasx r0,r1 + qasx r0,r1,r2 + + qsax r0,r1 + qsax r0,r1,r2 + + qsub16 r0,r1 + qsub16 r0,r1,r2 + + qsub8 r0,r1 + qsub8 r0,r1,r2 + + qsubaddx r0,r1 + qsubaddx r0,r1,r2 + + rev r0,r1 + + rev16 r0,r1 + + revsh r0,r1 + + rfe r0 + rfe r0! + + rfeda r0 + rfeda r0! + + rfedb r0 + rfedb r0! + + rfeea r0 + rfeea r0! + + rfeed r0 + rfeed r0! + + rfefa r0 + rfefa r0! + + rfefd r0 + rfefd r0! + + rfeia r0 + rfeia r0! + + rfeib r0 + rfeib r0! + + sadd16 r0,r1 + sadd16 r0,r1,r2 + + sadd8 r0,r1 + sadd8 r0,r1,r2 + + saddsubx r0,r1 + saddsubx r0,r1,r2 + + sasx r0,r1 + sasx r0,r1,r2 + + sel r0,r1 + sel r0,r1,r2 + + setend le + + ssax r0,r1 + ssax r0,r1,r2 + + ssub16 r0,r1 + ssub16 r0,r1,r2 + + ssub8 r0,r1 + ssub8 r0,r1,r2 + + ssubaddx r0,r1 + ssubaddx r0,r1,r2 + + shadd16 r0,r1 + shadd16 r0,r1,r2 + + shadd8 r0,r1 + shadd8 r0,r1,r2 + + shaddsubx r0,r1 + shaddsubx r0,r1,r2 + + shasx r0,r1 + shasx r0,r1,r2 + + shsax r0,r1 + shsax r0,r1,r2 + + shsub16 r0,r1 + shsub16 r0,r1,r2 + + shsub8 r0,r1 + shsub8 r0,r1,r2 + + shsubaddx r0,r1 + shsubaddx r0,r1,r2 + + smlad r0,r1,r2,r3 + + smladx r0,r1,r2,r3 + + smlald r0,r1,r2,r3 + + smlaldx r0,r1,r2,r3 + + smlsd r0,r1,r2,r3 + + smlsdx r0,r1,r2,r3 + + smlsld r0,r1,r2,r3 + + smlsldx r0,r1,r2,r3 + + smmla r0,r1,r2,r3 + + smmlar r0,r1,r2,r3 + + smmls r0,r1,r2,r3 + + smmlsr r0,r1,r2,r3 + + smmul r0,r1 + smmul r0,r1,r2 + + smmulr r0,r1 + smmulr r0,r1,r2 + + smuad r0,r1 + smuad r0,r1,r2 + + smuadx r0,r1 + smuadx r0,r1,r2 + + smusd r0,r1 + smusd r0,r1,r2 + + smusdx r0,r1 + smusdx r0,r1,r2 + + srs 0 + srs 0 ! + srs sp,0 + srs sp!,0 + + srsda 0 + srsda 0 ! + srsda sp,0 + srsda sp!,0 + + srsdb 0 + srsdb 0 ! + srsdb sp,0 + srsdb sp!,0 + + srsea 0 + srsea 0 ! + srsea sp,0 + srsea sp!,0 + + srsed 0 + srsed 0 ! + srsed sp,0 + srsed sp!,0 + + srsfa 0 + srsfa 0 ! + srsfa sp,0 + srsfa sp!,0 + + srsfd 0 + srsfd 0 ! + srsfd sp,0 + srsfd sp!,0 + + srsia 0 + srsia 0 ! + srsia sp,0 + srsia sp!,0 + + srsib 0 + srsib 0 ! + srsib sp,0 + srsib sp!,0 + + ssat r0,1,r2 + ssat r0,1,r2,lsl 3 + ssat r0,1,r2,asr 3 + + ssat16 r0,1,r2 + + strex r0,r1,[r1] + strex r0,r1,[r1,0] + + sxtab r0,r1,r2 + sxtab r0,r1,r2,ror 8 + + sxtab16 r0,r1,r2 + sxtab16 r0,r1,r2,ror 8 + + sxtah r0,r1,r2 + sxtah r0,r1,r2,ror 8 + + sxtb r0,r1 + sxtb r0,r1,ror 8 + + sxtb16 r0,r1 + sxtb16 r0,r1,ror 8 + + sxth r0,r1 + sxth r0,r1,ror 8 + + uadd16 r0,r1 + uadd16 r0,r1,r2 + + uadd8 r0,r1 + uadd8 r0,r1,r2 + + uaddsubx r0,r1 + uaddsubx r0,r1,r2 + + uasx r0,r1 + uasx r0,r1,r2 + + usax r0,r1 + usax r0,r1,r2 + + usub16 r0,r1 + usub16 r0,r1,r2 + + usub8 r0,r1 + usub8 r0,r1,r2 + + usubaddx r0,r1 + usubaddx r0,r1,r2 + + uhadd16 r0,r1 + uhadd16 r0,r1,r2 + + uhadd8 r0,r1 + uhadd8 r0,r1,r2 + + uhaddsubx r0,r1 + uhaddsubx r0,r1,r2 + + uhasx r0,r1 + uhasx r0,r1,r2 + + uhsax r0,r1 + uhsax r0,r1,r2 + + uhsub16 r0,r1 + uhsub16 r0,r1,r2 + + uhsub8 r0,r1 + uhsub8 r0,r1,r2 + + uhsubaddx r0,r1 + uhsubaddx r0,r1,r2 + + umaal r0,r1,r2,r3 + + uqadd16 r0,r1 + uqadd16 r0,r1,r2 + + uqadd8 r0,r1 + uqadd8 r0,r1,r2 + + uqaddsubx r0,r1 + uqaddsubx r0,r1,r2 + + uqasx r0,r1 + uqasx r0,r1,r2 + + uqsax r0,r1 + uqsax r0,r1,r2 + + uqsub16 r0,r1 + uqsub16 r0,r1,r2 + + uqsub8 r0,r1 + uqsub8 r0,r1,r2 + + uqsubaddx r0,r1 + uqsubaddx r0,r1,r2 + + usad8 r0,r1,r2 + + usada8 r0,r1,r2,r3 + + usat r0,1,r2 + usat r0,1,r2,lsl 3 + usat r0,1,r2,asr 3 + + usat16 r0,1,r2 + + uxtab r0,r1,r2 + uxtab r0,r1,r2,ror 8 + + uxtab16 r0,r1,r2 + uxtab16 r0,r1,r2,ror 8 + + uxtah r0,r1,r2 + uxtah r0,r1,r2,ror 8 + + uxtb r0,r1 + uxtb r0,r1,ror 8 + + uxtb16 r0,r1 + uxtb16 r0,r1,ror 8 + + uxth r0,r1 + uxth r0,r1,ror 8 + +processor CPU32_K + + clrex + + ldrexb r0,[r1] + ldrexb r0,[r1,0] + + ldrexd r0,[r1] + ldrexd r0,r1,[r2] + + ldrexh r0,[r1] + ldrexh r0,[r1,0] + + strexb r0,r1,[r2] + strexb r0,r1,[r2,0] + + strexd r0,r2,[r4] + strexd r0,r2,r3,[r4] + + strexh r0,r1,[r2] + strexh r0,r1,[r2,0] + + sev + + wfe + + wfi + + yield + +processor CPU32_Z + + smc 0 + + smi 0 + +processor CPU32_T2 + + bfc r0,1,2 + + bfi r0,r1,2,3 + + mls r0,r1,r2,r3 + + rbit r0,r1 + + ldrht r0,[r1] + ldrht r0,[r1],r2 + ldrht r0,[r1],-r2 + ldrht r0,[r1],2 + + ldrsbt r0,[r1] + ldrsbt r0,[r1],-r2 + ldrsbt r0,[r1],r2 + ldrsbt r0,[r1],2 + + ldrsht r0,[r1] + ldrsht r0,[r1],r2 + ldrsht r0,[r1],-r2 + ldrsht r0,[r1],2 + + movt r0,1 + + movw r0,1 + + sbfx r0,r1,2,3 + + strht r0,[r1] + strht r0,[r1],r2 + strht r0,[r1],-r2 + strht r0,[r1],2 + + ubfx r0,r1,2,3 + +processor CPU32_V7 + + dbg 0 + + dmb + dmb sy + + dsb + dsb sy + + isb + isb sy + + label_pli: + pli [r0] + pli [r0,1] + pli [r0,r1] + pli [r0,-r1] + pli [r0,r1,lsl 2] + pli [r0,r1,lsr 2] + pli [r0,r1,asr 2] + pli [r0,r1,ror 2] + pli [r0,-r1,lsl 2] + pli [r0,-r1,lsr 2] + pli [r0,-r1,asr 2] + pli [r0,-r1,ror 2] + pli [r0,r1,rrx] + pli [r0,-r1,rrx] + pli [label_pli] + pli [expression.byte] + +processor CPU32_MP + + label_pldw: + pldw [r0] + pldw [r0,1] + pldw [r0,r1] + pldw [r0,-r1] + pldw [r0,r1,lsl 2] + pldw [r0,r1,lsr 2] + pldw [r0,r1,asr 2] + pldw [r0,r1,ror 2] + pldw [r0,-r1,lsl 2] + pldw [r0,-r1,lsr 2] + pldw [r0,-r1,asr 2] + pldw [r0,-r1,ror 2] + pldw [r0,r1,rrx] + pldw [r0,-r1,rrx] + pldw [label_pldw] + pldw [expression.byte] + +processor CPU32_VE + + eret + + hvc 0 + + msr lr_fiq,r0 + + mrs r0,lr_fiq + + sdiv r0,r1 + sdiv r0,r1,r2 + + udiv r0,r1 + udiv r0,r1,r2 + +processor CPU32_V8 + + hlt 0 + + lda r0,[r1] + ldab r0,[r1] + ldah r0,[r1] + + ldaex r0,[r1] + ldaexb r0,[r1] + ldaexh r0,[r1] + ldaexd r0,[r2] + ldaexd r0,r1,[r2] + + sevl + + stl r0,[r1] + stlb r0,[r1] + stlh r0,[r1] + + stlex r2,r0,[r3] + stlexb r2,r0,[r3] + stlexh r2,r0,[r3] + stlexd r2,r0,[r3] + stlexd r2,r0,r1,[r3] + +processor CPU32_CRC + + crc32b r0,r1,r2 + crc32h r0,r1,r2 + crc32w r0,r1,r2 + + crc32cb r0,r1,r2 + crc32ch r0,r1,r2 + crc32cw r0,r1,r2 + +processor 0 ;In ARM mode, UND is always encodable, it ignores the processor directive + + und + und 0 diff --git a/armdoc/InstructionFormatsARM64.asm b/armdoc/InstructionFormatsARM64.asm new file mode 100644 index 0000000..d312ed0 --- /dev/null +++ b/armdoc/InstructionFormatsARM64.asm @@ -0,0 +1,3831 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions show the condition or flag +;writeback ("s") syntaxes. Only the branch (b.cc) +;instruction can be conditional. The condition code +;should be added at the end of the main opcode. For +;example: "b.hi". + +;This file can be assembled by fasmarm. + +label expression.byte byte at x2+1 +label expression.hword hword at x2+2 +label expression.word word at x2+4 +label expression.dword dword at x2+8 +label expression.qword qword at x2+16 +label expression.dqword dqword at x2+32 + + ;************************************************** + ;ARM64 mode, all instructions are 32-bits in length + ;************************************************** + + code64 + +processor CPU64_V8 + + adc w0,w1,w2 + adc x0,x1,x2 + + adcs w0,w1,w2 + adcs x0,x1,x2 + + add sp,sp,0x123 + add sp,x2,0x123 + add w1,w2,0x123 + add w4,w8,0x123,lsl 12 + add wsp,w2,0x123 + add wsp,wsp,0x123 + add w1,w2,wzr + add w1,w2,w3 + add w1,w2,w3,asr 1 + add w1,w2,w3,lsl 1 + add w1,w2,w3,lsr 1 + add w1,w2,w3,sxtb + add w1,w2,w3,sxtb 1 + add w1,w2,w3,sxth + add w1,w2,w3,sxth 1 + add w1,w2,w3,sxtw + add w1,w2,w3,sxtw 1 + add w1,w2,w3,uxtb + add w1,w2,w3,uxtb 1 + add w1,w2,w3,uxth + add w1,w2,w3,uxth 1 + add w1,w2,w3,uxtw + add w1,w2,w3,uxtw 1 + add w1,wsp,w2,uxtw 2 + add w1,wsp,w3,uxtw + add w1,wsp,w3,uxtw 1 + add wsp,w2,w3,uxtw + add wsp,wsp,w3,uxtw + add wzr,w2,w3 + add wzr,w2,wzr + add wzr,wzr,w3 + add wzr,wzr,wzr + add x1,x2,x3 + add x1,x2,0x123 + add x1,x2,0xFFF + add x1,x2,0xFFF,lsl 12 + add x1,sp,0x123 + add x1,sp,x3,uxtx + add x1,sp,x3,uxtx 4 + add x1,x2,w3,sxtb + add x1,x2,w3,sxtb 2 + add x1,x2,w3,sxth + add x1,x2,w3,sxth 2 + add x1,x2,w3,sxtw + add x1,x2,w3,sxtw 2 + add x1,x2,w3,uxtb + add x1,x2,w3,uxtb 2 + add x1,x2,w3,uxth + add x1,x2,w3,uxth 2 + add x1,x2,w3,uxtw + add x1,x2,w3,uxtw 2 + add x1,x2,x3,asr 1 + add x1,x2,x3,asr 63 + add x1,x2,x3,lsl 1 + add x1,x2,x3,lsr 1 + add x1,x2,x3,sxtx + add x1,x2,x3,sxtx 3 + add x1,x2,x3,uxtx + add x1,x2,x3,uxtx 2 + add w1,wsp,w3 + add w1,w3,wsp + add x1,sp,x3 + add x1,x3,sp + + adds w1,w2,w3 + adds w1,w2,wzr + adds w1,wsp,0x123 + adds w1,wsp,w3,uxtw + adds w1,wsp,w2,uxtw 2 + adds w1,wzr,w3 + adds w1,wzr,wzr + adds w8,w16,0x123,lsl 12 + adds x8,x16,0x123,lsl 12 + adds x1,x2,x3,asr 63 + adds w1,wsp,w3 + adds w1,w3,wsp + adds x1,sp,x3 + adds x1,x3,sp + + label_adr: + adr x1,label_adr + + adrp x1,$ + + and w1,w2,0x0001FE00 + and w1,w2,w3 + and w1,w2,w3,asr 4 + and w1,w2,w3,lsl 4 + and w1,w2,w3,lsr 4 + and w1,w2,w3,ror 4 + and wzr,w2,w3,ror 4 + and x1,x2,0x0003FC0000000000 + and x1,x2,x3 + and x1,x2,x3,lsl 4 + and x1,x2,x3,ror 4 + and xzr,x2,x3,ror 4 + + ands w1,w2,0xFFFFFFF1 + ands w1,w2,w3 + ands w1,w2,w3,lsl 4 + ands w1,w2,w3,ror 4 + ands x1,x2,0x5555555555555555 + ands x1,x2,x3 + ands x1,x2,x3,lsl 4 + ands x1,x2,x3,ror 4 + + asr w1,w2,1 + asr w1,w2,w3 + asr x1,x2,1 + asr x1,x2,x3 + + asrv w1,w2,w3 + asrv x1,x2,x3 + + at s12e0r,x1 + at s12e0w,x1 + at s12e1r,x1 + at s12e1w,x1 + at s1e0r,x1 + at s1e0w,x1 + at s1e1r,x1 + at s1e1w,x1 + at s1e2r,x1 + at s1e2w,x1 + at s1e3r,x1 + at s1e3w,x1 + + label_b: + b label_b + b.al label_b + b.eq label_b + b.eq label_b + b.ge label_b + b.gt label_b + b.hi label_b + b.hs label_b + b.le label_b + b.lo label_b + b.ls label_b + b.lt label_b + b.mi label_b + b.ne label_b + b.pl label_b + b.vc label_b + b.vs label_b + + bfi w1,w2,3,27 + bfi x1,x2,3,59 + + bfm w1,w2,3,31 + bfm x1,x2,3,45 + + bfxil w1,w2,3,29 + bfxil x1,x2,3,29 + + bic w1,w2,w3 + bic w1,w2,w3,asr 4 + bic w1,w2,w3,lsl 4 + bic w1,w2,w3,lsr 4 + bic w1,w2,w3,ror 4 + bic x1,x2,x3 + bic x1,x2,x3,lsl 4 + bic x1,x2,x3,ror 4 + + bics w1,w2,w3 + bics w1,w2,w3,lsl 4 + bics w1,w2,w3,ror 4 + bics x1,x2,x3 + bics x1,x2,x3,lsl 4 + bics x1,x2,x3,ror 4 + + label_bl: + bl label_bl + + blr x1 + + br x1 + + brk 0xFFFF + + label_cbnz: + cbnz w1,label_cbnz + cbnz x1,label_cbnz + + label_cbz: + cbz w1,label_cbz + cbz x1,label_cbz + + ccmn w1,2,0x0,ls + ccmn w1,w2,0x0,hs + ccmn x1,31,0x0,vs + ccmn x1,x2,0x1,ge + + ccmp w1,2,0x0,ls + ccmp w1,w2,0x0,hs + ccmp x1,31,0x0,vs + ccmp x1,x2,0x1,ge + + cinc w1,w2,hs + + cinv w1,w2,hs + + clrex 0x5 + + cls w1,w2 + cls x1,x2 + + clz w1,w2 + clz x1,x2 + + cmn sp,x3,uxtx + cmn sp,x3,uxtx 1 + cmn w2,w3 + cmn w2,w3,asr 1 + cmn w2,w3,asr 31 + cmn w2,w3,lsl 1 + cmn w2,w3,lsr 1 + cmn wsp,w3,uxtw + cmn wsp,w3,uxtw 1 + cmn x1,0x2 + cmn x2,x3 + cmn x2,x3,asr 1 + cmn x2,x3,asr 63 + cmn x2,x3,lsl 1 + cmn x2,x3,lsr 1 + + cmp sp,x3,uxtx + cmp sp,x3,uxtx 1 + cmp w2,w3 + cmp w2,w3,asr 1 + cmp w2,w3,asr 31 + cmp w2,w3,lsl 1 + cmp w2,w3,lsr 1 + cmp wsp,w3,uxtw + cmp wsp,w3,uxtw 1 + cmp x1,0x2 + cmp x2,x3 + cmp x2,x3,asr 1 + cmp x2,x3,asr 63 + cmp x2,x3,lsl 1 + cmp x2,x3,lsr 1 + + cneg w1,w2,hs + cneg xzr,xzr,hs + + csel w1,w2,w3,ne + csel x1,x2,x3,vs + + cset w1,ne + cset x1,vs + + csetm w1,ne + csetm x1,vs + + csinc w1,w2,w3,ne + csinc x1,x2,x3,vs + + csinv w1,w2,w3,ne + csinv x1,x2,x3,vs + + csneg w1,w2,w3,ne + csneg x1,x2,x3,vs + + dc cisw,x1 + dc civac,x1 + dc csw,x1 + dc cvac,x1 + dc cvau,x1 + dc isw,x1 + dc ivac,x1 + dc zva,x1 + + dcps1 0x0 + + dcps1 0xFFFF + + dcps2 0xFFFF + + dcps3 0xFFFF + + dmb ish + dmb ishld + dmb ishst + dmb ld + dmb nsh + dmb nshld + dmb nshst + dmb osh + dmb oshld + dmb oshst + dmb st + dmb sy + + drps + + dsb ish + dsb ishld + dsb ishst + dsb ld + dsb nsh + dsb nshld + dsb nshst + dsb osh + dsb oshld + dsb oshst + dsb st + dsb sy + + eon w1,w2,w3 + eon w1,w2,w3,asr 4 + eon w1,w2,w3,lsl 4 + eon w1,w2,w3,lsr 4 + eon w1,w2,w3,ror 4 + eon wzr,w2,w3,ror 4 + eon x1,x2,x3 + eon x1,x2,x3,lsl 4 + eon x1,x2,x3,ror 4 + eon xzr,x2,x3,ror 4 + + eor sp,x2,0xAAAAAAAAAAAAAAAA + eor w1,w2,0xFFFFFFF1 + eor w1,w2,w3 + eor w1,w2,w3,asr 4 + eor w1,w2,w3,lsl 4 + eor w1,w2,w3,lsr 4 + eor w1,w2,w3,ror 4 + eor wzr,w2,w3,ror 4 + eor x1,x2,0xFFFFFFFFFFFFFFF1 + eor x1,x2,x3 + eor x1,x2,x3,lsl 4 + eor x1,x2,x3,ror 4 + eor xzr,x2,x3,ror 4 + + eret + + extr w1,w2,w3,3 + extr x1,x2,x3,35 + + hint 4 + + hlt 0xFFFF + + hvc 0xFFFF + + ic iallu + ic ialluis + ic ivau,x1 + ic ivau,xzr + + isb sy + + ldar w1,[x2] + ldar w1,[x2,0] + ldar x3,[x8] + ldar x3,[x8,0] + + ldarb w1,[x2] + ldarb w1,[x2,0] + + ldarh w1,[x2] + ldarh w1,[x2,0] + + ldaxp w1,w8,[x2] + ldaxp w1,w8,[x2,0] + ldaxp x3,x2,[x8] + ldaxp x3,x2,[x8,0] + + ldaxr w1,[x2] + ldaxr w1,[x2,0] + ldaxr x3,[x8] + ldaxr x3,[x8,0] + + ldaxrb w1,[x2] + ldaxrb w1,[x2,0] + + ldaxrh w1,[x2] + ldaxrh w1,[x2,0] + + ldnp w0,w1,[x2] + ldnp w0,w1,[x2,+0x8] + ldnp w0,w1,[expression.dword] + ldnp x0,x1,[x2] + ldnp x0,x1,[x2,+0x8] + ldnp x0,x1,[expression.qword] + + ldp w0,w1,[x2] + ldp w0,w1,[x2,+0x8] + ldp w0,w1,[expression.dword] + ldp w0,w1,[x2,+0x8]! + ldp w0,w1,[expression.dword]! + ldp w0,w1,[x2],+0x8 + ldp x0,x1,[x2] + ldp x0,x1,[x2,+0x8] + ldp x0,x1,[expression.qword] + ldp x0,x1,[x2,+0x8]! + ldp x0,x1,[expression.qword]! + ldp x0,x1,[x2],+0x8 + + ldpsw x0,x1,[x2] + ldpsw x0,x1,[x2,+0x8] + ldpsw x0,x1,[expression.dword] + ldpsw x0,x1,[x2,+0x8]! + ldpsw x0,x1,[expression.dword]! + ldpsw x0,x1,[x2],+0x8 + + label_ldr: + ldr w0,[x2,+0x8] + ldr w0,[expression.word] + ldr w0,[x2,+0x8]! + ldr w0,[expression.word]! + ldr w0,[x2],+0x8 + ldr w0,[x2,w3,sxtw] + ldr w0,[x2,w3,sxtw 2] + ldr w0,[x2,w3,uxtw] + ldr w0,[x2,w3,uxtw 2] + ldr w0,[x2,x3] + ldr w0,[x2,x3,lsl 2] + ldr w0,[x2,x3,sxtx] + ldr w0,[x2,x3,sxtx 2] + ldr w0,label_ldr + ldr w0,[label_ldr] + ldr x0,[x2,+0x8] + ldr x0,[expression.dword] + ldr x0,[x2,+0x8]! + ldr x0,[expression.dword]! + ldr x0,[x2],+0x8 + ldr x0,[x2,w3,sxtw] + ldr x0,[x2,w3,sxtw 3] + ldr x0,[x2,w3,uxtw] + ldr x0,[x2,w3,uxtw 3] + ldr x0,[x2,x3] + ldr x0,[x2,x3,lsl 3] + ldr x0,[x2,x3,sxtx] + ldr x0,[x2,x3,sxtx 3] + ldr x0,label_ldr + ldr x0,[label_ldr] + + ldrb w0,[x2] + ldrb w0,[x2,+0x8] + ldrb w0,[expression.byte] + ldrb w0,[x2,+0x8]! + ldrb w0,[expression.byte]! + ldrb w0,[x2],+0x8 + ldrb w0,[x2,w3,sxtw] + ldrb w0,[x2,w3,sxtw 0] + ldrb w0,[x2,w3,uxtw] + ldrb w0,[x2,w3,uxtw 0] + ldrb w0,[x2,x3] + ldrb w0,[x2,x3,lsl 0] + ldrb w0,[x2,x3,sxtx] + ldrb w0,[x2,x3,sxtx 0] + + ldrh w0,[x2] + ldrh w0,[x2,+0x8] + ldrh w0,[expression.hword] + ldrh w0,[x2,+0x8]! + ldrh w0,[expression.hword]! + ldrh w0,[x2],+0x8 + ldrh w0,[x2,w3,sxtw] + ldrh w0,[x2,w3,sxtw 1] + ldrh w0,[x2,w3,uxtw] + ldrh w0,[x2,w3,uxtw 1] + ldrh w0,[x2,x3] + ldrh w0,[x2,x3,lsl 1] + ldrh w0,[x2,x3,sxtx] + ldrh w0,[x2,x3,sxtx 1] + + ldrsb w0,[x2] + ldrsb w0,[x2,+0x8] + ldrsb w0,[expression.byte] + ldrsb w0,[x2,+0x8]! + ldrsb w0,[expression.byte]! + ldrsb w0,[x2],+0x8 + ldrsb w0,[x2,w3,sxtw] + ldrsb w0,[x2,w3,sxtw 0] + ldrsb w0,[x2,w3,uxtw] + ldrsb w0,[x2,w3,uxtw 0] + ldrsb w0,[x2,x3] + ldrsb w0,[x2,x3,lsl 0] + ldrsb w0,[x2,x3,sxtx] + ldrsb w0,[x2,x3,sxtx 0] + + ldrsh w0,[x2] + ldrsh w0,[x2,+0x8] + ldrsh w0,[expression.hword] + ldrsh w0,[x2,+0x8]! + ldrsh w0,[expression.hword]! + ldrsh w0,[x2],+0x8 + ldrsh w0,[x2,w3,sxtw] + ldrsh w0,[x2,w3,sxtw 1] + ldrsh w0,[x2,w3,uxtw] + ldrsh w0,[x2,w3,uxtw 1] + ldrsh w0,[x2,x3] + ldrsh w0,[x2,x3,lsl 1] + ldrsh w0,[x2,x3,sxtx] + ldrsh w0,[x2,x3,sxtx 1] + + label_ldrsw: + ldrsw x0,[x2] + ldrsw x0,[x2,+0x8] + ldrsw x0,[expression.word] + ldrsw x0,[x2,+0x8]! + ldrsw x0,[expression.word]! + ldrsw x0,[x2],+0x8 + ldrsw x0,[x2,w3,sxtw] + ldrsw x0,[x2,w3,sxtw 2] + ldrsw x0,[x2,w3,uxtw] + ldrsw x0,[x2,w3,uxtw 2] + ldrsw x0,[x2,x3] + ldrsw x0,[x2,x3,lsl 2] + ldrsw x0,[x2,x3,sxtx] + ldrsw x0,[x2,x3,sxtx 2] + ldrsw x1,label_ldrsw + ldrsw x1,[label_ldrsw] + + ldtr w0,[x2] + ldtr w0,[x2,+0x8] + ldtr w0,[expression.word] + ldtr x0,[x2] + ldtr x0,[x2,+0x8] + ldtr x0,[expression.dword] + + ldtrb w0,[x2] + ldtrb w0,[x2,+0x8] + ldtrb w0,[expression.byte] + + ldtrh w0,[x2] + ldtrh w0,[x2,+0x8] + ldtrh w0,[expression.hword] + + ldtrsb w0,[x2] + ldtrsb w0,[x2,+0x8] + ldtrsb w0,[expression.byte] + + ldtrsh w0,[x2] + ldtrsh w0,[x2,+0x8] + ldtrsh w0,[expression.hword] + + ldtrsw x0,[x2] + ldtrsw x0,[x2,+0x8] + ldtrsw x0,[expression.word] + + ldur w0,[x2] + ldur w0,[x2,+0x8] + ldur w0,[expression.word] + ldur x0,[x2] + ldur x0,[x2,+0x8] + ldur x0,[expression.dword] + + ldurb w0,[x2] + ldurb w0,[x2,+0x8] + ldurb w0,[expression.byte] + + ldurh w0,[x2] + ldurh w0,[x2,+0x8] + ldurh w0,[expression.hword] + + ldursb w0,[x2] + ldursb w0,[x2,+0x8] + ldursb w0,[expression.byte] + + ldursh w0,[x2] + ldursh w0,[x2,+0x8] + ldursh w0,[expression.hword] + + ldursw x0,[x2] + ldursw x0,[x2,+0x8] + ldursw x0,[expression.word] + + ldxp w1,w8,[x2] + ldxp w1,w8,[x2,0] + ldxp x3,x2,[x8] + ldxp x3,x2,[x8,0] + + ldxr w1,[x2] + ldxr w1,[x2,0] + ldxr x3,[x8] + ldxr x3,[x8,0] + + ldxrb w1,[x2] + ldxrb w1,[x2,0] + + ldxrh w1,[x2] + ldxrh w1,[x2,0] + + lsl w1,w2,1 + lsl w1,w2,w3 + lsl x1,x2,1 + lsl x1,x2,x3 + + lslv w1,w2,w3 + lslv x1,x2,x3 + + lsr w1,w2,1 + lsr w1,w2,w3 + lsr x1,x2,1 + lsr x1,x2,x3 + + lsrv w1,w2,w3 + lsrv x1,x2,x3 + + madd w1,w2,w3,w4 + madd x1,x2,x3,x4 + + mneg w1,w2,w3 + mneg x1,x2,x3 + + mov sp,sp + mov sp,x1 + mov w0,w1 + mov w1,0x00FFFFF0 + mov w1,0x000FFFFF + mov w1,0x100FFFFF + mov wsp,0x0000FFFF + mov wsp,w1 + mov wsp,wsp + mov wzr,w1 + mov wzr,wzr + mov x0,x1 + mov x1,0x000FFFFFFFFFFFF0 + mov x1,0x0000FFFFFFFFFFFF + mov x1,0x1000FFFFFFFFFFFF + mov x1,sp + mov xzr,x1 + mov xzr,xzr + + movk x0,0,lsl 0 + movk x0,0,lsl 16 + movk x0,0,lsl 32 + movk x0,0,lsl 48 + + movn x0,0,lsl 0 + movn x0,0,lsl 16 + movn x0,0,lsl 32 + movn x0,0,lsl 48 + + movz x0,0,lsl 0 + movz x0,0,lsl 16 + movz x0,0,lsl 32 + movz x0,0,lsl 48 + + movk w1,0xFFFF + movk w1,0xFFFF,lsl 16 + movk x1,0xFFFF,lsl 32 + movk x1,0xFFFF,lsl 48 + + movn w1,0xFFFF + movn w1,0xFFFF,lsl 16 + + movz w1,0xffff + movz w1,0xffff,lsl 0 + movz w1,0xffff,lsl 16 + movz x1,0xffff,lsl 32 + movz x1,0xffff,lsl 48 + + mrs x1,vttbr_el2 + mrs x2,s3_2_c3_c4_5 + mrs x8,spsel + + msr actlr_el1,x1 + msr s3_2_c3_c4_5,x1 + + msub w1,w2,w3,w4 + msub x1,x2,x3,x4 + + mul w1,w2,w3 + mul x2,x3,x4 + + mvn w1,w2 + mvn w1,w2,asr 4 + mvn w1,w2,lsl 4 + mvn w1,w2,lsr 4 + mvn w1,w2,ror 4 + mvn x1,x2 + mvn x1,x2,asr 4 + mvn x1,x2,lsl 4 + mvn x1,x2,lsr 4 + mvn x1,x2,ror 4 + + neg w1,w2 + neg w1,w2,asr 14 + neg w1,w2,lsl 4 + neg w1,w2,lsr 4 + neg x1,x2 + neg x1,x2,asr 14 + neg x1,x2,lsl 4 + neg x1,x2,lsr 4 + + negs w1,w2 + negs x1,x2 + + ngc w1,w2 + ngc x1,x2 + + ngcs w1,w2 + ngcs x1,x2 + + nop + + orn w1,w2,w3 + orn w1,w2,w3,asr 4 + orn w1,w2,w3,lsl 4 + orn w1,w2,w3,lsr 4 + orn w1,w2,w3,ror 4 + orn x1,x2,x3 + orn x1,x2,x3,asr 4 + orn x1,x2,x3,lsl 4 + orn x1,x2,x3,lsr 4 + orn x1,x2,x3,ror 4 + + orr w1,w2,0xFFFFFFF1 + orr w1,w2,w3 + orr w1,w2,w3,asr 4 + orr w1,w2,w3,lsl 4 + orr w1,w2,w3,lsr 4 + orr w1,w2,w3,ror 4 + orr x1,x2,0xAAAAAAAAAAAAAAAA + orr x1,x2,x3 + orr x1,x2,x3,lsl 4 + orr x1,x2,x3,ror 4 + + label_prfm: + prfm pldl2strm,[x2,+0x8] + prfm pldl2strm,[expression.dword] + prfm pldl2strm,[x2,w3,sxtw] + prfm pldl2strm,[x2,w3,sxtw 3] + prfm pldl2strm,[x2,w3,uxtw] + prfm pldl2strm,[x2,w3,uxtw 3] + prfm pldl2strm,[x2,x3] + prfm pldl2strm,[x2,x3,lsl 3] + prfm pldl2strm,[x2,x3,sxtx] + prfm pldl2strm,[x2,x3,sxtx 3] + prfm pldl2strm,label_prfm + prfm pldl2strm,[label_prfm] + prfm 0x00,[x2,+0x8] + prfm 0x01,[expression.dword] + prfm 0x02,[x2,w3,sxtw] + prfm 0x03,[x2,w3,sxtw 3] + prfm 0x04,[x2,w3,uxtw] + prfm 0x05,[x2,w3,uxtw 3] + prfm 0x06,[x2,x3] + prfm 0x07,[x2,x3,lsl 3] + prfm 0x08,[x2,x3,sxtx] + prfm 0x09,[x2,x3,sxtx 3] + prfm 0x0a,label_prfm + prfm 0x0b,[label_prfm] + + rbit w1,w2 + rbit x1,x2 + + ret + ret x1 + + rev w1,w2 + rev x1,x2 + + rev16 w1,w2 + rev16 x1,x2 + + rev32 x1,x2 + + rev64 x1,x2 + + ror w1,w2,1 + ror w1,w2,w3 + ror x1,x2,1 + ror x1,x2,x3 + + rorv w1,w2,w3 + rorv x1,x2,x3 + + sbc w0,w1,w2 + sbc x0,x1,x2 + + sbcs w0,w1,w2 + sbcs x0,x1,x2 + + sbfiz w1,w2,3,28 + sbfiz x1,x2,3,60 + + sbfm w1,w2,3,30 + sbfm x1,x2,3,45 + + sbfx w1,w2,3,4 + sbfx x1,x2,3,29 + + sdiv w1,w2,w3 + sdiv x1,x2,x3 + + sev + + sevl + + smaddl x1,w2,w3,x4 + + smc 0xFFFF + + smnegl x1,w2,w3 + + smsubl x1,w2,w3,x4 + + smulh x1,x2,x3 + + smull x1,w2,w3 + + stlr w1,[x2] + stlr w1,[x2,0] + stlr x3,[x8] + stlr x3,[x8,0] + + stlrb w1,[x2] + stlrb w1,[x2,0] + + stlrh w1,[x2] + stlrh w1,[x2,0] + + stlxp w1,w2,w3,[x4] + stlxp w1,w2,w3,[x4,0] + stlxp w1,x2,x3,[x4] + stlxp w1,x2,x3,[x4,0] + + stlxr w1,w2,[x3] + stlxr w1,w2,[x3,0] + stlxr w1,x2,[x3] + stlxr w1,x2,[x3,0] + + stlxrb w1,w2,[x3] + stlxrb w1,w2,[x3,0] + + stlxrh w1,w2,[x3] + stlxrh w1,w2,[x3,0] + + stnp w0,w1,[x2] + stnp w0,w1,[x2,+0x8] + stnp w0,w1,[expression.dword] + stnp x0,x1,[x2] + stnp x0,x1,[x2,+0x8] + stnp x0,x1,[expression.qword] + + stp w0,w1,[x2] + stp w0,w1,[x2,+0x8] + stp w0,w1,[expression.dword] + stp w0,w1,[x2,+0x8]! + stp w0,w1,[expression.dword]! + stp w0,w1,[x2],+0x8 + stp x0,x1,[x2] + stp x0,x1,[x2,+0x8] + stp x0,x1,[expression.qword] + stp x0,x1,[x2,+0x8]! + stp x0,x1,[expression.qword]! + stp x0,x1,[x2],+0x8 + + str w0,[x2,+0x8] + str w0,[expression.word] + str w0,[x2,+0x8]! + str w0,[expression.word]! + str w0,[x2],+0x8 + str w0,[x2,w3,sxtw] + str w0,[x2,w3,sxtw 2] + str w0,[x2,w3,uxtw] + str w0,[x2,w3,uxtw 2] + str w0,[x2,x3] + str w0,[x2,x3,lsl 2] + str w0,[x2,x3,sxtx] + str w0,[x2,x3,sxtx 2] + str x0,[x2,+0x8] + str x0,[expression.dword] + str x0,[x2,+0x8]! + str x0,[expression.dword]! + str x0,[x2],+0x8 + str x0,[x2,w3,sxtw] + str x0,[x2,w3,sxtw 3] + str x0,[x2,w3,uxtw] + str x0,[x2,w3,uxtw 3] + str x0,[x2,x3] + str x0,[x2,x3,lsl 3] + str x0,[x2,x3,sxtx] + str x0,[x2,x3,sxtx 3] + + strb w0,[x2] + strb w0,[x2,+0x8] + strb w0,[expression.byte] + strb w0,[x2,+0x8]! + strb w0,[expression.byte]! + strb w0,[x2],+0x8 + strb w0,[x2,w3,sxtw] + strb w0,[x2,w3,sxtw 0] + strb w0,[x2,w3,uxtw] + strb w0,[x2,w3,uxtw 0] + strb w0,[x2,x3] + strb w0,[x2,x3,lsl 0] + strb w0,[x2,x3,sxtx] + strb w0,[x2,x3,sxtx 0] + + strh w0,[x2] + strh w0,[x2,+0x8] + strh w0,[expression.hword] + strh w0,[x2,+0x8]! + strh w0,[expression.hword]! + strh w0,[x2],+0x8 + strh w0,[x2,w3,sxtw] + strh w0,[x2,w3,sxtw 1] + strh w0,[x2,w3,uxtw] + strh w0,[x2,w3,uxtw 1] + strh w0,[x2,x3] + strh w0,[x2,x3,lsl 1] + strh w0,[x2,x3,sxtx] + strh w0,[x2,x3,sxtx 1] + + sttr w0,[x2] + sttr w0,[x2,+0x8] + sttr w0,[expression.word] + sttr x0,[x2] + sttr x0,[x2,+0x8] + sttr x0,[expression.dword] + + sttrb w0,[x2] + sttrb w0,[x2,+0x8] + sttrb w0,[expression.byte] + + sttrh w0,[x2] + sttrh w0,[x2,+0x8] + sttrh w0,[expression.hword] + + stur w0,[x2] + stur w0,[x2,+0x8] + stur w0,[expression.word] + stur x0,[x2] + stur x0,[x2,+0x8] + stur x0,[expression.dword] + + sturb w0,[x2] + sturb w0,[x2,+0x8] + sturb w0,[expression.byte] + + sturh w0,[x2] + sturh w0,[x2,+0x8] + sturh w0,[expression.hword] + + stxp w1,w2,w3,[x4] + stxp w1,w2,w3,[x4,0] + stxp w1,x2,x3,[x4] + stxp w1,x2,x3,[x4,0] + + stxr w1,w2,[x3] + stxr w1,w2,[x3,0] + stxr w1,x2,[x3] + stxr w1,x2,[x3,0] + + stxrb w1,w2,[x3] + stxrb w1,w2,[x3,0] + + stxrh w1,w2,[x3] + stxrh w1,w2,[x3,0] + + sub sp,sp,0x123 + sub sp,x2,0x123 + sub w1,w2,0x123 + sub w4,w8,0x123,lsl 12 + sub wsp,w2,0x123 + sub wsp,wsp,0x123 + sub w1,w2,wzr + sub w1,w2,w3 + sub w1,w2,w3,asr 1 + sub w1,w2,w3,lsl 1 + sub w1,w2,w3,lsr 1 + sub w1,w2,w3,sxtb + sub w1,w2,w3,sxtb 1 + sub w1,w2,w3,sxth + sub w1,w2,w3,sxth 1 + sub w1,w2,w3,sxtw + sub w1,w2,w3,sxtw 1 + sub w1,w2,w3,uxtb + sub w1,w2,w3,uxtb 1 + sub w1,w2,w3,uxth + sub w1,w2,w3,uxth 1 + sub w1,w2,w3,uxtw + sub w1,w2,w3,uxtw 1 + sub w1,wsp,w2,uxtw 2 + sub w1,wsp,w3,uxtw + sub w1,wsp,w3,uxtw 1 + sub wsp,w2,w3,uxtw + sub wsp,wsp,w3,uxtw + sub wzr,w2,w3 + sub wzr,w2,wzr + sub wzr,wzr,w3 + sub wzr,wzr,wzr + sub x1,x2,x3 + sub x1,x2,0x123 + sub x1,x2,0xFFF + sub x1,x2,0xFFF,lsl 12 + sub x1,sp,0x123 + sub x1,sp,x3,uxtx + sub x1,sp,x3,uxtx 4 + sub x1,x2,w3,sxtb + sub x1,x2,w3,sxtb 2 + sub x1,x2,w3,sxth + sub x1,x2,w3,sxth 2 + sub x1,x2,w3,sxtw + sub x1,x2,w3,sxtw 2 + sub x1,x2,w3,uxtb + sub x1,x2,w3,uxtb 2 + sub x1,x2,w3,uxth + sub x1,x2,w3,uxth 2 + sub x1,x2,w3,uxtw + sub x1,x2,w3,uxtw 2 + sub x1,x2,x3,asr 1 + sub x1,x2,x3,asr 63 + sub x1,x2,x3,lsl 1 + sub x1,x2,x3,lsr 1 + sub x1,x2,x3,sxtx + sub x1,x2,x3,sxtx 3 + sub x1,x2,x3,uxtx + sub x1,x2,x3,uxtx 2 + + subs w1,w2,w3 + subs w1,w2,wzr + subs w1,wsp,0x123 + subs w1,wsp,w3,uxtw + subs w1,wsp,w2,uxtw 2 + subs w1,wzr,w3 + subs w1,wzr,wzr + subs w8,w16,0x123,lsl 12 + subs x8,x16,0x123,lsl 12 + subs x1,x2,x3,asr 63 + + svc 0xFFFF + + sxtb w1,w2 + sxtb x1,w2 + + sxth w1,w2 + sxth x1,w2 + + sxtw x1,w2 + + sys 1,c2,c3,4 + sys 1,c2,c3,4,x5 + + sysl x1,2,c3,c4,5 + + label_tbnz: + tbnz w1,2,label_tbnz + tbnz x1,63,label_tbnz + + label_tbz: + tbz w1,2,label_tbz + tbz x1,63,label_tbz + + tlbi alle1 + tlbi aside1,x1 + + tst w1,0x0000000E + tst w1,w2 + tst w2,w3,asr 4 + tst w2,w3,lsl 4 + tst w2,w3,lsr 4 + tst w2,w3,ror 4 + tst x1,0x00000000000FFE00 + tst x1,x2 + tst x2,x3,ror 4 + + ubfiz w1,w2,3,28 + ubfiz x1,x2,3,60 + + ubfm w1,w2,3,31 + ubfm x1,x2,3,31 + + ubfx w1,w2,3,4 + ubfx x1,x2,3,29 + + udiv w1,w2,w3 + udiv x1,x2,x3 + + umaddl x1,w2,w3,x4 + + umnegl x1,w2,w3 + + umsubl x1,w2,w3,x4 + + umull x1,w2,w3 + + umulh x1,x2,x3 + + uxtb w1,w2 + + uxth w1,w2 + + wfe + + wfi + + yield + +processor CPU64_FP + + fabd d1,d2,d3 + fabd s1,s2,s3 + fabd v1.2d,v2.2d,v3.2d + fabd v1.2s,v2.2s,v3.2s + fabd v1.4s,v2.4s,v3.4s + + fabs d1,d2 + fabs s1,s2 + fabs v1.2d,v2.2d + fabs v1.2s,v2.2s + fabs v1.4s,v2.4s + + facge d1,d2,d3 + facge s1,s2,s3 + facge v1.2d,v2.2d,v3.2d + facge v1.2s,v2.2s,v3.2s + facge v1.4s,v2.4s,v3.4s + + facgt d1,d2,d3 + facgt s1,s2,s3 + facgt v1.2d,v2.2d,v3.2d + facgt v1.2s,v2.2s,v3.2s + facgt v1.4s,v2.4s,v3.4s + + fadd d1,d2,d3 + fadd s1,s2,s3 + fadd v1.2d,v2.2d,v3.2d + fadd v1.2s,v2.2s,v3.2s + fadd v1.4s,v2.4s,v3.4s + + faddp d1,v2.2d + faddp s1,v2.2s + faddp v1.2d,v2.2d,v3.2d + faddp v1.2s,v2.2s,v3.2s + faddp v1.4s,v2.4s,v3.4s + + fccmp d1,d2,0x1,ge + fccmp s1,s2,0x0,hs + + fccmpe d1,d2,0x1,ge + fccmpe s1,s2,0x0,hs + + fcmeq d1,d2,0 + fcmeq d1,d2,d3 + fcmeq s1,s2,0 + fcmeq s1,s2,s3 + fcmeq v1.2d,v2.2d,0 + fcmeq v1.2d,v2.2d,v3.2d + fcmeq v1.2s,v2.2s,0 + fcmeq v1.2s,v2.2s,v3.2s + fcmeq v1.4s,v2.4s,0 + fcmeq v1.4s,v2.4s,v3.4s + + fcmge d1,d2,0 + fcmge d1,d2,d3 + fcmge s1,s2,0 + fcmge s1,s2,s3 + fcmge v1.2d,v2.2d,0 + fcmge v1.2d,v2.2d,v3.2d + fcmge v1.2s,v2.2s,0 + fcmge v1.2s,v2.2s,v3.2s + fcmge v1.4s,v2.4s,0 + fcmge v1.4s,v2.4s,v3.4s + + fcmgt d1,d2,0 + fcmgt d1,d2,d3 + fcmgt s1,s2,0 + fcmgt s1,s2,s3 + fcmgt v1.2d,v2.2d,0 + fcmgt v1.2d,v2.2d,v3.2d + fcmgt v1.2s,v2.2s,0 + fcmgt v1.2s,v2.2s,v3.2s + fcmgt v1.4s,v2.4s,0 + fcmgt v1.4s,v2.4s,v3.4s + + fcmle d1,d2,0 + fcmle s1,s2,0 + fcmle v1.2d,v2.2d,0 + fcmle v1.2s,v2.2s,0 + fcmle v1.4s,v2.4s,0 + + fcmlt d1,d2,0 + fcmlt s1,s2,0 + fcmlt v1.2d,v2.2d,0 + fcmlt v1.2s,v2.2s,0 + fcmlt v1.4s,v2.4s,0 + + fcmp d1,0.0 + fcmp d1,d2 + fcmp s1,0.0 + fcmp s1,s2 + + fcmpe d1,0.0 + fcmpe d1,d2 + fcmpe s1,0.0 + fcmpe s1,s2 + + fcsel d1,d2,d3,vs + fcsel s1,s2,s3,ls + + fcvt d1,h2 + fcvt d1,s2 + fcvt h1,d2 + fcvt h1,s2 + fcvt s1,d2 + fcvt s1,h2 + + fcvtas d1,d2 + fcvtas s1,s2 + fcvtas v1.2d,v2.2d + fcvtas v1.2s,v2.2s + fcvtas v1.4s,v2.4s + fcvtas w1,d2 + fcvtas w1,s2 + fcvtas x1,d2 + fcvtas x1,s2 + + fcvtau d1,d2 + fcvtau s1,s2 + fcvtau v1.2d,v2.2d + fcvtau v1.2s,v2.2s + fcvtau v1.4s,v2.4s + fcvtau w1,d2 + fcvtau w1,s2 + fcvtau x1,d2 + fcvtau x1,s2 + + fcvtl v1.2d,v2.2s + fcvtl v1.4s,v2.4h + + fcvtl2 v1.2d,v2.4s + fcvtl2 v1.4s,v2.8h + + fcvtms d1,d2 + fcvtms s1,s2 + fcvtms v1.2d,v2.2d + fcvtms v1.2s,v2.2s + fcvtms v1.4s,v2.4s + fcvtms w1,d2 + fcvtms w1,s2 + fcvtms x1,d2 + fcvtms x1,s2 + + fcvtmu d1,d2 + fcvtmu s1,s2 + fcvtmu v1.2d,v2.2d + fcvtmu v1.2s,v2.2s + fcvtmu v1.4s,v2.4s + fcvtmu w1,d2 + fcvtmu w1,s2 + fcvtmu x1,d2 + fcvtmu x1,s2 + + fcvtn v1.2s,v2.2d + fcvtn v1.4h,v2.4s + + fcvtn2 v1.4s,v2.2d + fcvtn2 v1.8h,v2.4s + + fcvtns d1,d2 + fcvtns s1,s2 + fcvtns v1.2d,v2.2d + fcvtns v1.2s,v2.2s + fcvtns v1.4s,v2.4s + fcvtns w1,d2 + fcvtns w1,s2 + fcvtns x1,d2 + fcvtns x1,s2 + + fcvtnu d1,d2 + fcvtnu s1,s2 + fcvtnu v1.2d,v2.2d + fcvtnu v1.2s,v2.2s + fcvtnu v1.4s,v2.4s + fcvtnu w1,d2 + fcvtnu w1,s2 + fcvtnu x1,d2 + fcvtnu x1,s2 + + fcvtps d1,d2 + fcvtps s1,s2 + fcvtps v1.2d,v2.2d + fcvtps v1.2s,v2.2s + fcvtps v1.4s,v2.4s + fcvtps w1,d2 + fcvtps w1,s2 + fcvtps x1,d2 + fcvtps x1,s2 + + fcvtpu d1,d2 + fcvtpu s1,s2 + fcvtpu v1.2d,v2.2d + fcvtpu v1.2s,v2.2s + fcvtpu v1.4s,v2.4s + fcvtpu w1,d2 + fcvtpu w1,s2 + fcvtpu x1,d2 + fcvtpu x1,s2 + + fcvtxn s1,d2 + fcvtxn v1.2s,v2.2d + + fcvtxn2 v1.4s,v2.2d + + fcvtzs d1,d2 + fcvtzs d1,d2,5 + fcvtzs s1,s2 + fcvtzs s1,s2,5 + fcvtzs v1.2d,v2.2d + fcvtzs v1.2d,v2.2d,5 + fcvtzs v1.2s,v2.2s + fcvtzs v1.2s,v2.2s,5 + fcvtzs v1.4s,v2.4s + fcvtzs v1.4s,v2.4s,5 + fcvtzs w1,d2 + fcvtzs w1,d2,5 + fcvtzs w1,s2 + fcvtzs w1,s2,5 + fcvtzs x1,d2 + fcvtzs x1,d2,5 + fcvtzs x1,s2 + fcvtzs x1,s2,5 + + fcvtzu d1,d2 + fcvtzu d1,d2,5 + fcvtzu s1,s2 + fcvtzu s1,s2,5 + fcvtzu v1.2d,v2.2d + fcvtzu v1.2d,v2.2d,5 + fcvtzu v1.2s,v2.2s + fcvtzu v1.2s,v2.2s,5 + fcvtzu v1.4s,v2.4s + fcvtzu v1.4s,v2.4s,5 + fcvtzu w1,d2 + fcvtzu w1,d2,5 + fcvtzu w1,s2 + fcvtzu w1,s2,5 + fcvtzu x1,d2 + fcvtzu x1,d2,5 + fcvtzu x1,s2 + fcvtzu x1,s2,5 + + fdiv d1,d2,d3 + fdiv s1,s2,s3 + fdiv v1.2d,v2.2d,v3.2d + fdiv v1.2s,v2.2s,v3.2s + fdiv v1.4s,v2.4s,v3.4s + + fmadd d1,d2,d3,d4 + fmadd s1,s2,s3,s4 + + fmax d1,d2,d3 + fmax s1,s2,s3 + fmax v1.2d,v2.2d,v3.2d + fmax v1.2s,v2.2s,v3.2s + fmax v1.4s,v2.4s,v3.4s + + fmaxnm d1,d2,d3 + fmaxnm s1,s2,s3 + fmaxnm v1.2d,v2.2d,v3.2d + fmaxnm v1.2s,v2.2s,v3.2s + fmaxnm v1.4s,v2.4s,v3.4s + + fmaxnmp d1,v2.2d + fmaxnmp s1,v2.2s + fmaxnmp v1.2d,v2.2d,v3.2d + fmaxnmp v1.2s,v2.2s,v3.2s + fmaxnmp v1.4s,v2.4s,v3.4s + + fmaxnmv s1,v2.4s + + fmaxp d1,v2.2d + fmaxp s1,v2.2s + fmaxp v1.2d,v2.2d,v3.2d + fmaxp v1.2s,v2.2s,v3.2s + fmaxp v1.4s,v2.4s,v3.4s + + fmaxv s1,v2.4s + + fmin d1,d2,d3 + fmin s1,s2,s3 + fmin v1.2d,v2.2d,v3.2d + fmin v1.2s,v2.2s,v3.2s + fmin v1.4s,v2.4s,v3.4s + + fminnm d1,d2,d3 + fminnm s1,s2,s3 + fminnm v1.2d,v2.2d,v3.2d + fminnm v1.2s,v2.2s,v3.2s + fminnm v1.4s,v2.4s,v3.4s + + fminnmp d1,v2.2d + fminnmp s1,v2.2s + fminnmp v1.2d,v2.2d,v3.2d + fminnmp v1.2s,v2.2s,v3.2s + fminnmp v1.4s,v2.4s,v3.4s + + fminnmv s1,v2.4s + + fminp d1,v2.2d + fminp s1,v2.2s + fminp v1.2d,v2.2d,v3.2d + fminp v1.2s,v2.2s,v3.2s + fminp v1.4s,v2.4s,v3.4s + + fminv s1,v2.4s + + fmla d1,d2,v3.d[1] + fmla s1,s2,v3.s[3] + fmla v1.2d,v2.2d,v3.2d + fmla v1.2d,v2.2d,v3.d[0] + fmla v1.2s,v2.2s,v3.2s + fmla v1.2s,v2.2s,v3.s[2] + fmla v1.4s,v2.4s,v3.4s + fmla v1.4s,v2.4s,v3.s[1] + + fmls d1,d2,v3.d[1] + fmls s1,s2,v3.s[3] + fmls v1.2d,v2.2d,v3.2d + fmls v1.2d,v2.2d,v3.d[0] + fmls v1.2s,v2.2s,v3.2s + fmls v1.2s,v2.2s,v3.s[2] + fmls v1.4s,v2.4s,v3.4s + fmls v1.4s,v2.4s,v3.s[1] + + fmov d1,3.375 + fmov d1,d2 + fmov d1,x2 + fmov s1,4.25 + fmov s1,s2 + fmov s1,w2 + fmov v1.2d,7.75 + fmov v1.2s,5.5 + fmov v1.4s,6.75 + fmov v1.d[1],x2 + fmov w1,s2 + fmov x1,d2 + fmov x1,v2.d[1] + + fmsub d1,d2,d3,d4 + fmsub s1,s2,s3,s4 + + fmul d1,d2,d3 + fmul d1,d2,v3.d[1] + fmul s1,s2,s3 + fmul s1,s2,v3.s[3] + fmul v1.2d,v2.2d,v3.2d + fmul v1.2d,v2.2d,v3.d[0] + fmul v1.2s,v2.2s,v3.2s + fmul v1.2s,v2.2s,v3.s[2] + fmul v1.4s,v2.4s,v3.4s + fmul v1.4s,v2.4s,v3.s[1] + + fmulx d1,d2,d3 + fmulx d1,d2,v3.d[1] + fmulx s1,s2,s3 + fmulx s1,s2,v3.s[3] + fmulx v1.2d,v2.2d,v3.2d + fmulx v1.2d,v2.2d,v3.d[0] + fmulx v1.2s,v2.2s,v3.2s + fmulx v1.2s,v2.2s,v3.s[2] + fmulx v1.4s,v2.4s,v3.4s + fmulx v1.4s,v2.4s,v3.s[1] + + fneg d1,d2 + fneg s1,s2 + fneg v1.2d,v2.2d + fneg v1.2s,v2.2s + fneg v1.4s,v2.4s + + fnmadd d1,d2,d3,d4 + fnmadd s1,s2,s3,s4 + + fnmsub d1,d2,d3,d4 + fnmsub s1,s2,s3,s4 + + fnmul d1,d2,d3 + fnmul s1,s2,s3 + + frecpe d1,d2 + frecpe s1,s2 + frecpe v1.2d,v2.2d + frecpe v1.2s,v2.2s + frecpe v1.4s,v2.4s + + frecps d1,d2,d3 + frecps s1,s2,s3 + frecps v1.2d,v2.2d,v3.2d + frecps v1.2s,v2.2s,v3.2s + frecps v1.4s,v2.4s,v3.4s + + frecpx d1,d2 + frecpx s1,s2 + + frinta d1,d2 + frinta s1,s2 + frinta v1.2d,v2.2d + frinta v1.2s,v2.2s + frinta v1.4s,v2.4s + + frinti d1,d2 + frinti s1,s2 + frinti v1.2d,v2.2d + frinti v1.2s,v2.2s + frinti v1.4s,v2.4s + + frintm d1,d2 + frintm s1,s2 + frintm v1.2d,v2.2d + frintm v1.2s,v2.2s + frintm v1.4s,v2.4s + + frintn d1,d2 + frintn s1,s2 + frintn v1.2d,v2.2d + frintn v1.2s,v2.2s + frintn v1.4s,v2.4s + + frintp d1,d2 + frintp s1,s2 + frintp v1.2d,v2.2d + frintp v1.2s,v2.2s + frintp v1.4s,v2.4s + + frintx d1,d2 + frintx s1,s2 + frintx v1.2d,v2.2d + frintx v1.2s,v2.2s + frintx v1.4s,v2.4s + + frintz d1,d2 + frintz s1,s2 + frintz v1.2d,v2.2d + frintz v1.2s,v2.2s + frintz v1.4s,v2.4s + + frsqrte d1,d2 + frsqrte s1,s2 + frsqrte v1.2d,v2.2d + frsqrte v1.2s,v2.2s + frsqrte v1.4s,v2.4s + frsqrts d1,d2,d3 + frsqrts s1,s2,s3 + frsqrts v1.2d,v2.2d,v3.2d + frsqrts v1.2s,v2.2s,v3.2s + frsqrts v1.4s,v2.4s,v3.4s + + fsqrt d1,d2 + fsqrt s1,s2 + fsqrt v1.2d,v2.2d + fsqrt v1.2s,v2.2s + fsqrt v1.4s,v2.4s + + fsub d1,d2,d3 + fsub s1,s2,s3 + fsub v1.2d,v2.2d,v3.2d + fsub v1.2s,v2.2s,v3.2s + fsub v1.4s,v2.4s,v3.4s + + scvtf d1,d2 + scvtf d1,d2,5 + scvtf d2,w1 + scvtf d2,w1,5 + scvtf d2,x1 + scvtf d2,x1,5 + scvtf s1,s2 + scvtf s1,s2,5 + scvtf s2,w1 + scvtf s2,w1,5 + scvtf s2,x1 + scvtf s2,x1,5 + scvtf v1.2d,v2.2d + scvtf v1.2d,v2.2d,5 + scvtf v1.2s,v2.2s + scvtf v1.2s,v2.2s,5 + scvtf v1.4s,v2.4s + scvtf v1.4s,v2.4s,5 + + ucvtf d1,d2 + ucvtf d1,d2,5 + ucvtf d2,w1 + ucvtf d2,w1,5 + ucvtf d2,x1 + ucvtf d2,x1,5 + ucvtf s1,s2 + ucvtf s1,s2,5 + ucvtf s2,w1 + ucvtf s2,w1,5 + ucvtf s2,x1 + ucvtf s2,x1,5 + ucvtf v1.2d,v2.2d + ucvtf v1.2d,v2.2d,5 + ucvtf v1.2s,v2.2s + ucvtf v1.2s,v2.2s,5 + ucvtf v1.4s,v2.4s + ucvtf v1.4s,v2.4s,5 + + urecpe v1.2s,v2.2s + urecpe v1.4s,v2.4s + + ursqrte v1.2s,v2.2s + ursqrte v1.4s,v2.4s + +processor CPU64_SIMD + + abs d1,d2 + abs v1.16b,v2.16b + abs v1.2d,v2.2d + abs v1.2s,v2.2s + abs v1.4h,v2.4h + abs v1.4s,v2.4s + abs v1.8b,v2.8b + abs v1.8h,v2.8h + + add d1,d2,d3 + add v1.16b,v2.16b,v3.16b + add v1.2d,v2.2d,v3.2d + add v1.2s,v2.2s,v3.2s + add v1.4h,v2.4h,v3.4h + add v1.4s,v2.4s,v3.4s + add v1.8b,v2.8b,v3.8b + add v1.8h,v2.8h,v3.8h + + addhn v1.2s,v2.2d,v3.2d + addhn v1.4h,v2.4s,v3.4s + addhn v1.8b,v2.8h,v3.8h + + addhn2 v1.16b,v2.8h,v3.8h + addhn2 v1.4s,v2.2d,v3.2d + addhn2 v1.8h,v2.4s,v3.4s + + addp d1,v2.2d + addp v1.16b,v2.16b,v3.16b + addp v1.2d,v2.2d,v3.2d + addp v1.2s,v2.2s,v3.2s + addp v1.4h,v2.4h,v3.4h + addp v1.4s,v2.4s,v3.4s + addp v1.8b,v2.8b,v3.8b + addp v1.8h,v2.8h,v3.8h + + addv b1,v2.16b + addv b1,v2.8b + addv h1,v2.4h + addv h1,v2.8h + addv s1,v2.4s + + and v1.16b,v2.16b,v3.16b + and v1.8b,v2.8b,v3.8b + + bic v1.16b,v2.16b,v3.16b + bic v1.2s,0xFF + bic v1.2s,0xFF,lsl 0 + bic v1.2s,0xFF,lsl 8 + bic v1.2s,0xFF,lsl 16 + bic v1.2s,0xFF,lsl 24 + bic v1.4h,0xFE + bic v1.4h,0xFE,lsl 0 + bic v1.4h,0xFF,lsl 8 + bic v1.4s,0xFF + bic v1.4s,0xFF,lsl 0 + bic v1.4s,0xFF,lsl 8 + bic v1.4s,0xFF,lsl 16 + bic v1.4s,0xFF,lsl 24 + bic v1.8b,v2.8b,v3.8b + bic v1.8h,0xFF + bic v1.8h,0xFF,lsl 0 + bic v1.8h,0xFF,lsl 8 + + bif v1.16b,v2.16b,v3.16b + bif v1.8b,v2.8b,v3.8b + + bit v1.16b,v2.16b,v3.16b + bit v1.8b,v2.8b,v3.8b + + bsl v1.16b,v2.16b,v3.16b + bsl v1.8b,v2.8b,v3.8b + + cls v1.16b,v2.16b + cls v1.2s,v2.2s + cls v1.4h,v2.4h + cls v1.4s,v2.4s + cls v1.8b,v2.8b + cls v1.8h,v2.8h + + clz v1.16b,v2.16b + clz v1.2s,v2.2s + clz v1.4h,v2.4h + clz v1.4s,v2.4s + clz v1.8b,v2.8b + clz v1.8h,v2.8h + + cmeq d1,d2,0 + cmeq d1,d2,d3 + cmeq v1.16b,v2.16b,0 + cmeq v1.16b,v2.16b,v3.16b + cmeq v1.2d,v2.2d,0 + cmeq v1.2d,v2.2d,v3.2d + cmeq v1.2s,v2.2s,0 + cmeq v1.2s,v2.2s,v3.2s + cmeq v1.4h,v2.4h,0 + cmeq v1.4h,v2.4h,v3.4h + cmeq v1.4s,v2.4s,0 + cmeq v1.4s,v2.4s,v3.4s + cmeq v1.8b,v2.8b,0 + cmeq v1.8b,v2.8b,v3.8b + cmeq v1.8h,v2.8h,0 + cmeq v1.8h,v2.8h,v3.8h + + cmge d1,d2,0 + cmge d1,d2,d3 + cmge v1.16b,v2.16b,0 + cmge v1.16b,v2.16b,v3.16b + cmge v1.2d,v2.2d,0 + cmge v1.2d,v2.2d,v3.2d + cmge v1.2s,v2.2s,0 + cmge v1.2s,v2.2s,v3.2s + cmge v1.4h,v2.4h,0 + cmge v1.4h,v2.4h,v3.4h + cmge v1.4s,v2.4s,0 + cmge v1.4s,v2.4s,v3.4s + cmge v1.8b,v2.8b,0 + cmge v1.8b,v2.8b,v3.8b + cmge v1.8h,v2.8h,0 + cmge v1.8h,v2.8h,v3.8h + + cmgt d1,d2,0 + cmgt d1,d2,d3 + cmgt v1.16b,v2.16b,0 + cmgt v1.16b,v2.16b,v3.16b + cmgt v1.2d,v2.2d,0 + cmgt v1.2d,v2.2d,v3.2d + cmgt v1.2s,v2.2s,0 + cmgt v1.2s,v2.2s,v3.2s + cmgt v1.4h,v2.4h,0 + cmgt v1.4h,v2.4h,v3.4h + cmgt v1.4s,v2.4s,0 + cmgt v1.4s,v2.4s,v3.4s + cmgt v1.8b,v2.8b,0 + cmgt v1.8b,v2.8b,v3.8b + cmgt v1.8h,v2.8h,0 + cmgt v1.8h,v2.8h,v3.8h + + cmhi d1,d2,d3 + cmhi v1.16b,v2.16b,v3.16b + cmhi v1.2d,v2.2d,v3.2d + cmhi v1.2s,v2.2s,v3.2s + cmhi v1.4h,v2.4h,v3.4h + cmhi v1.4s,v2.4s,v3.4s + cmhi v1.8b,v2.8b,v3.8b + cmhi v1.8h,v2.8h,v3.8h + + cmhs d1,d2,d3 + cmhs v1.16b,v2.16b,v3.16b + cmhs v1.2d,v2.2d,v3.2d + cmhs v1.2s,v2.2s,v3.2s + cmhs v1.4h,v2.4h,v3.4h + cmhs v1.4s,v2.4s,v3.4s + cmhs v1.8b,v2.8b,v3.8b + cmhs v1.8h,v2.8h,v3.8h + + cmle d1,d2,0 + cmle v1.16b,v2.16b,0 + cmle v1.2d,v2.2d,0 + cmle v1.2s,v2.2s,0 + cmle v1.4h,v2.4h,0 + cmle v1.4s,v2.4s,0 + cmle v1.8b,v2.8b,0 + cmle v1.8h,v2.8h,0 + + cmlt d1,d2,0 + cmlt v1.16b,v2.16b,0 + cmlt v1.2d,v2.2d,0 + cmlt v1.2s,v2.2s,0 + cmlt v1.4h,v2.4h,0 + cmlt v1.4s,v2.4s,0 + cmlt v1.8b,v2.8b,0 + cmlt v1.8h,v2.8h,0 + + cmtst d1,d2,d3 + cmtst v1.16b,v2.16b,v3.16b + cmtst v1.2d,v2.2d,v3.2d + cmtst v1.2s,v2.2s,v3.2s + cmtst v1.4h,v2.4h,v3.4h + cmtst v1.4s,v2.4s,v3.4s + cmtst v1.8b,v2.8b,v3.8b + cmtst v1.8h,v2.8h,v3.8h + + cnt v1.16b,v2.16b + cnt v1.8b,v2.8b + + dup v1.16b,v2.b[15] + dup v1.16b,w2 + dup v1.2d,v2.d[1] + dup v1.2d,x2 + dup v1.2s,v2.s[1] + dup v1.2s,w2 + dup v1.4h,v2.h[1] + dup v1.4h,w2 + dup v1.4s,v2.s[3] + dup v1.4s,w2 + dup v1.8b,v2.b[1] + dup v1.8b,w2 + dup v1.8h,v2.h[7] + dup v1.8h,w2 + + eor v1.16b,v2.16b,v3.16b + eor v1.8b,v2.8b,v3.8b + + ext v1.16b,v2.16b,v3.16b,15 + ext v1.8b,v2.8b,v3.8b,7 + + ins v2.b[15],w1 + ins v2.h[7],w1 + ins v2.s[3],w1 + ins v2.d[1],x1 + + ins v1.b[15],v2.b[1] + ins v1.b[1],v2.b[15] + ins v1.h[7],v2.h[1] + ins v1.h[1],v2.h[7] + ins v1.s[3],v2.s[1] + ins v1.s[1],v2.s[3] + ins v1.d[1],v2.d[0] + ins v1.d[0],v2.d[1] + + ld1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp] + ld1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp],64 + ld1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp],x6 + ld1 {v1.16b,v2.16b,v3.16b},[x4] + ld1 {v1.16b,v2.16b,v3.16b},[x4],48 + ld1 {v1.16b,v2.16b,v3.16b},[x4],x5 + ld1 {v1.16b,v2.16b},[x3] + ld1 {v1.16b,v2.16b},[x3],32 + ld1 {v1.16b,v2.16b},[x3],x4 + ld1 {v1.16b},[x2] + ld1 {v1.16b},[x2],16 + ld1 {v1.16b},[x2],x3 + ld1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp] + ld1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp],32 + ld1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp],x6 + ld1 {v1.1d,v2.1d,v3.1d},[x4] + ld1 {v1.1d,v2.1d,v3.1d},[x4],24 + ld1 {v1.1d,v2.1d,v3.1d},[x4],x5 + ld1 {v1.1d,v2.1d},[x3] + ld1 {v1.1d,v2.1d},[x3],16 + ld1 {v1.1d,v2.1d},[x3],x4 + ld1 {v1.1d},[x2] + ld1 {v1.1d},[x2],8 + ld1 {v1.1d},[x2],x3 + ld1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp] + ld1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp],64 + ld1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp],x6 + ld1 {v1.2d,v2.2d,v3.2d},[x4] + ld1 {v1.2d,v2.2d,v3.2d},[x4],48 + ld1 {v1.2d,v2.2d,v3.2d},[x4],x5 + ld1 {v1.2d,v2.2d},[x3] + ld1 {v1.2d,v2.2d},[x3],32 + ld1 {v1.2d,v2.2d},[x3],x4 + ld1 {v1.2d},[x2] + ld1 {v1.2d},[x2],16 + ld1 {v1.2d},[x2],x3 + ld1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp] + ld1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp],32 + ld1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp],x6 + ld1 {v1.2s,v2.2s,v3.2s},[x4] + ld1 {v1.2s,v2.2s,v3.2s},[x4],24 + ld1 {v1.2s,v2.2s,v3.2s},[x4],x5 + ld1 {v1.2s,v2.2s},[x3] + ld1 {v1.2s,v2.2s},[x3],16 + ld1 {v1.2s,v2.2s},[x3],x4 + ld1 {v1.2s},[x2] + ld1 {v1.2s},[x2],8 + ld1 {v1.2s},[x2],x3 + ld1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp] + ld1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp],32 + ld1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp],x6 + ld1 {v1.4h,v2.4h,v3.4h},[x4] + ld1 {v1.4h,v2.4h,v3.4h},[x4],24 + ld1 {v1.4h,v2.4h,v3.4h},[x4],x5 + ld1 {v1.4h,v2.4h},[x3] + ld1 {v1.4h,v2.4h},[x3],16 + ld1 {v1.4h,v2.4h},[x3],x4 + ld1 {v1.4h},[x2] + ld1 {v1.4h},[x2],8 + ld1 {v1.4h},[x2],x3 + ld1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp] + ld1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp],64 + ld1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp],x6 + ld1 {v1.4s,v2.4s,v3.4s},[x4] + ld1 {v1.4s,v2.4s,v3.4s},[x4],48 + ld1 {v1.4s,v2.4s,v3.4s},[x4],x5 + ld1 {v1.4s,v2.4s},[x3] + ld1 {v1.4s,v2.4s},[x3],32 + ld1 {v1.4s,v2.4s},[x3],x4 + ld1 {v1.4s},[x2] + ld1 {v1.4s},[x2],16 + ld1 {v1.4s},[x2],x3 + ld1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp] + ld1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp],32 + ld1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp],x6 + ld1 {v1.8b,v2.8b,v3.8b},[x4] + ld1 {v1.8b,v2.8b,v3.8b},[x4],24 + ld1 {v1.8b,v2.8b,v3.8b},[x4],x5 + ld1 {v1.8b,v2.8b},[x3] + ld1 {v1.8b,v2.8b},[x3],16 + ld1 {v1.8b,v2.8b},[x3],x4 + ld1 {v1.8b},[x2] + ld1 {v1.8b},[x2],8 + ld1 {v1.8b},[x2],x3 + ld1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp] + ld1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp],64 + ld1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp],x6 + ld1 {v1.8h,v2.8h,v3.8h},[x4] + ld1 {v1.8h,v2.8h,v3.8h},[x4],48 + ld1 {v1.8h,v2.8h,v3.8h},[x4],x5 + ld1 {v1.8h,v2.8h},[x3] + ld1 {v1.8h,v2.8h},[x3],32 + ld1 {v1.8h,v2.8h},[x3],x4 + ld1 {v1.8h},[x2] + ld1 {v1.8h},[x2],16 + ld1 {v1.8h},[x2],x3 + ld1 {v1.b}[2],[x3] + ld1 {v1.b}[2],[x3],1 + ld1 {v1.b}[2],[x3],x4 + ld1 {v1.d}[1],[x3] + ld1 {v1.d}[1],[x3],8 + ld1 {v1.d}[1],[x3],x4 + ld1 {v1.h}[2],[x3] + ld1 {v1.h}[2],[x3],2 + ld1 {v1.h}[2],[x3],x4 + ld1 {v1.s}[2],[x3] + ld1 {v1.s}[2],[x3],4 + ld1 {v1.s}[2],[x3],x4 + + ld1r {v1.16b},[x2] + ld1r {v1.16b},[x2],1 + ld1r {v1.16b},[x2],x3 + ld1r {v1.1d},[x2] + ld1r {v1.1d},[x2],8 + ld1r {v1.1d},[x2],x3 + ld1r {v1.2d},[x2] + ld1r {v1.2d},[x2],8 + ld1r {v1.2d},[x2],x3 + ld1r {v1.2s},[x2] + ld1r {v1.2s},[x2],4 + ld1r {v1.2s},[x2],x3 + ld1r {v1.4h},[x2] + ld1r {v1.4h},[x2],2 + ld1r {v1.4h},[x2],x3 + ld1r {v1.4s},[x2] + ld1r {v1.4s},[x2],4 + ld1r {v1.4s},[x2],x3 + ld1r {v1.8b},[x2] + ld1r {v1.8b},[x2],1 + ld1r {v1.8b},[x2],x3 + ld1r {v1.8h},[x2] + ld1r {v1.8h},[x2],2 + ld1r {v1.8h},[x2],x3 + + ld2 {v1.16b,v2.16b},[x3] + ld2 {v1.16b,v2.16b},[x3],32 + ld2 {v1.16b,v2.16b},[x3],x4 + ld2 {v1.2d,v2.2d},[x3] + ld2 {v1.2d,v2.2d},[x3],32 + ld2 {v1.2d,v2.2d},[x3],x4 + ld2 {v1.2s,v2.2s},[x3] + ld2 {v1.2s,v2.2s},[x3],16 + ld2 {v1.2s,v2.2s},[x3],x4 + ld2 {v1.4h,v2.4h},[x3] + ld2 {v1.4h,v2.4h},[x3],16 + ld2 {v1.4h,v2.4h},[x3],x4 + ld2 {v1.4s,v2.4s},[x3] + ld2 {v1.4s,v2.4s},[x3],32 + ld2 {v1.4s,v2.4s},[x3],x4 + ld2 {v1.8b,v2.8b},[x3] + ld2 {v1.8b,v2.8b},[x3],16 + ld2 {v1.8b,v2.8b},[x3],x4 + ld2 {v1.8h,v2.8h},[x3] + ld2 {v1.8h,v2.8h},[x3],32 + ld2 {v1.8h,v2.8h},[x3],x4 + ld2 {v1.b,v2.b}[15],[x3] + ld2 {v1.b,v2.b}[2],[x3],2 + ld2 {v1.b,v2.b}[2],[x3],x4 + ld2 {v1.d,v2.d}[1],[x3] + ld2 {v1.d,v2.d}[1],[x3],16 + ld2 {v1.d,v2.d}[1],[x3],x4 + ld2 {v1.h,v2.h}[2],[x3] + ld2 {v1.h,v2.h}[2],[x3],4 + ld2 {v1.h,v2.h}[2],[x3],x4 + ld2 {v1.s,v2.s}[2],[x3] + ld2 {v1.s,v2.s}[2],[x3],8 + ld2 {v1.s,v2.s}[2],[x3],x4 + + ld2r {v1.16b,v2.16b},[x2] + ld2r {v1.16b,v2.16b},[x2],2 + ld2r {v1.16b,v2.16b},[x2],x3 + ld2r {v1.1d,v2.1d},[x2] + ld2r {v1.1d,v2.1d},[x2],16 + ld2r {v1.1d,v2.1d},[x2],x3 + ld2r {v1.2d,v2.2d},[x2] + ld2r {v1.2d,v2.2d},[x2],16 + ld2r {v1.2d,v2.2d},[x2],x3 + ld2r {v1.2s,v2.2s},[x2] + ld2r {v1.2s,v2.2s},[x2],8 + ld2r {v1.2s,v2.2s},[x2],x3 + ld2r {v1.4h,v2.4h},[x2] + ld2r {v1.4h,v2.4h},[x2],4 + ld2r {v1.4h,v2.4h},[x2],x3 + ld2r {v1.4s,v2.4s},[x2] + ld2r {v1.4s,v2.4s},[x2],8 + ld2r {v1.4s,v2.4s},[x2],x3 + ld2r {v1.8b,v2.8b},[x2] + ld2r {v1.8b,v2.8b},[x2],2 + ld2r {v1.8b,v2.8b},[x2],x3 + ld2r {v1.8h,v2.8h},[x2] + ld2r {v1.8h,v2.8h},[x2],4 + ld2r {v1.8h,v2.8h},[x2],x3 + + ld3 {v1.16b,v2.16b,v3.16b},[x3] + ld3 {v1.16b,v2.16b,v3.16b},[x3],48 + ld3 {v1.16b,v2.16b,v3.16b},[x3],x4 + ld3 {v1.2d,v2.2d,v3.2d},[x3] + ld3 {v1.2d,v2.2d,v3.2d},[x3],48 + ld3 {v1.2d,v2.2d,v3.2d},[x3],x4 + ld3 {v1.2s,v2.2s,v3.2s},[x3] + ld3 {v1.2s,v2.2s,v3.2s},[x3],24 + ld3 {v1.2s,v2.2s,v3.2s},[x3],x4 + ld3 {v1.4h,v2.4h,v3.4h},[x3] + ld3 {v1.4h,v2.4h,v3.4h},[x3],24 + ld3 {v1.4h,v2.4h,v3.4h},[x3],x4 + ld3 {v1.4s,v2.4s,v3.4s},[x3] + ld3 {v1.4s,v2.4s,v3.4s},[x3],48 + ld3 {v1.4s,v2.4s,v3.4s},[x3],x4 + ld3 {v1.8b,v2.8b,v3.8b},[x3] + ld3 {v1.8b,v2.8b,v3.8b},[x3],24 + ld3 {v1.8b,v2.8b,v3.8b},[x3],x4 + ld3 {v1.8h,v2.8h,v3.8h},[x3] + ld3 {v1.8h,v2.8h,v3.8h},[x3],48 + ld3 {v1.8h,v2.8h,v3.8h},[x3],x4 + ld3 {v1.b,v2.b,v3.b}[15],[x3] + ld3 {v1.b,v2.b,v3.b}[2],[x3],3 + ld3 {v1.b,v2.b,v3.b}[2],[x3],x4 + ld3 {v1.d,v2.d,v3.d}[1],[x3] + ld3 {v1.d,v2.d,v3.d}[1],[x3],24 + ld3 {v1.d,v2.d,v3.d}[1],[x3],x4 + ld3 {v1.h,v2.h,v3.h}[2],[x3] + ld3 {v1.h,v2.h,v3.h}[2],[x3],6 + ld3 {v1.h,v2.h,v3.h}[2],[x3],x4 + ld3 {v1.s,v2.s,v3.s}[2],[x3] + ld3 {v1.s,v2.s,v3.s}[2],[x3],12 + ld3 {v1.s,v2.s,v3.s}[2],[x3],x4 + + ld3r {v1.16b,v2.16b,v3.16b},[x2] + ld3r {v1.16b,v2.16b,v3.16b},[x2],3 + ld3r {v1.16b,v2.16b,v3.16b},[x2],x3 + ld3r {v1.1d,v2.1d,v3.1d},[x2] + ld3r {v1.1d,v2.1d,v3.1d},[x2],24 + ld3r {v1.1d,v2.1d,v3.1d},[x2],x3 + ld3r {v1.2d,v2.2d,v3.2d},[x2] + ld3r {v1.2d,v2.2d,v3.2d},[x2],24 + ld3r {v1.2d,v2.2d,v3.2d},[x2],x3 + ld3r {v1.2s,v2.2s,v3.2s},[x2] + ld3r {v1.2s,v2.2s,v3.2s},[x2],12 + ld3r {v1.2s,v2.2s,v3.2s},[x2],x3 + ld3r {v1.4h,v2.4h,v3.4h},[x2] + ld3r {v1.4h,v2.4h,v3.4h},[x2],6 + ld3r {v1.4h,v2.4h,v3.4h},[x2],x3 + ld3r {v1.4s,v2.4s,v3.4s},[x2] + ld3r {v1.4s,v2.4s,v3.4s},[x2],12 + ld3r {v1.4s,v2.4s,v3.4s},[x2],x3 + ld3r {v1.8b,v2.8b,v3.8b},[x2] + ld3r {v1.8b,v2.8b,v3.8b},[x2],3 + ld3r {v1.8b,v2.8b,v3.8b},[x2],x3 + ld3r {v1.8h,v2.8h,v3.8h},[x2] + ld3r {v1.8h,v2.8h,v3.8h},[x2],6 + ld3r {v1.8h,v2.8h,v3.8h},[x2],x3 + + ld4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3] + ld4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3],64 + ld4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3],x4 + ld4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3] + ld4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3],64 + ld4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3],x4 + ld4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3] + ld4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3],32 + ld4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3],x4 + ld4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3] + ld4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3],32 + ld4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3],x4 + ld4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3] + ld4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3],64 + ld4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3],x4 + ld4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3] + ld4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3],32 + ld4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3],x4 + ld4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3] + ld4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3],64 + ld4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3],x4 + ld4 {v1.b,v2.b,v3.b,v4.b}[15],[x3] + ld4 {v1.b,v2.b,v3.b,v4.b}[2],[x3],4 + ld4 {v1.b,v2.b,v3.b,v4.b}[2],[x3],x4 + ld4 {v1.d,v2.d,v3.d,v4.d}[1],[x3] + ld4 {v1.d,v2.d,v3.d,v4.d}[1],[x3],32 + ld4 {v1.d,v2.d,v3.d,v4.d}[1],[x3],x4 + ld4 {v1.h,v2.h,v3.h,v4.h}[2],[x3] + ld4 {v1.h,v2.h,v3.h,v4.h}[2],[x3],8 + ld4 {v1.h,v2.h,v3.h,v4.h}[2],[x3],x4 + ld4 {v1.s,v2.s,v3.s,v4.s}[2],[x3] + ld4 {v1.s,v2.s,v3.s,v4.s}[2],[x3],16 + ld4 {v1.s,v2.s,v3.s,v4.s}[2],[x3],x4 + + ld4r {v1.16b,v2.16b,v3.16b,v4.16b},[x2] + ld4r {v1.16b,v2.16b,v3.16b,v4.16b},[x2],4 + ld4r {v1.16b,v2.16b,v3.16b,v4.16b},[x2],x3 + ld4r {v1.1d,v2.1d,v3.1d,v4.1d},[x2] + ld4r {v1.1d,v2.1d,v3.1d,v4.1d},[x2],32 + ld4r {v1.1d,v2.1d,v3.1d,v4.1d},[x2],x3 + ld4r {v1.2d,v2.2d,v3.2d,v4.2d},[x2] + ld4r {v1.2d,v2.2d,v3.2d,v4.2d},[x2],32 + ld4r {v1.2d,v2.2d,v3.2d,v4.2d},[x2],x3 + ld4r {v1.2s,v2.2s,v3.2s,v4.2s},[x2] + ld4r {v1.2s,v2.2s,v3.2s,v4.2s},[x2],16 + ld4r {v1.2s,v2.2s,v3.2s,v4.2s},[x2],x3 + ld4r {v1.4h,v2.4h,v3.4h,v4.4h},[x2] + ld4r {v1.4h,v2.4h,v3.4h,v4.4h},[x2],8 + ld4r {v1.4h,v2.4h,v3.4h,v4.4h},[x2],x3 + ld4r {v1.4s,v2.4s,v3.4s,v4.4s},[x2] + ld4r {v1.4s,v2.4s,v3.4s,v4.4s},[x2],16 + ld4r {v1.4s,v2.4s,v3.4s,v4.4s},[x2],x3 + ld4r {v1.8b,v2.8b,v3.8b,v4.8b},[x2] + ld4r {v1.8b,v2.8b,v3.8b,v4.8b},[x2],4 + ld4r {v1.8b,v2.8b,v3.8b,v4.8b},[x2],x3 + ld4r {v1.8h,v2.8h,v3.8h,v4.8h},[x2] + ld4r {v1.8h,v2.8h,v3.8h,v4.8h},[x2],8 + ld4r {v1.8h,v2.8h,v3.8h,v4.8h},[x2],x3 + + ldnp d0,d1,[x2] + ldnp d0,d1,[x2,+0x8] + ldnp d0,d1,[expression.qword] + ldnp q0,q1,[x2] + ldnp q0,q1,[x2,+0x20] + ldnp q0,q1,[expression.dqword] + ldnp s0,s1,[x2] + ldnp s0,s1,[x2,+0x8] + ldnp s0,s1,[expression.dword] + + ldp d0,d1,[x2] + ldp d0,d1,[x2,+0x8] + ldp d0,d1,[expression.qword] + ldp d0,d1,[x2,+0x8]! + ldp d0,d1,[expression.qword]! + ldp d0,d1,[x2],+0x8 + ldp q0,q1,[x2] + ldp q0,q1,[x2,+0x10] + ldp q0,q1,[expression.dqword] + ldp q0,q1,[x2,+0x10]! + ldp q0,q1,[expression.dqword]! + ldp q0,q1,[x2],+0x10 + ldp s0,s1,[x2] + ldp s0,s1,[x2,+0x8] + ldp s0,s1,[expression.dword] + ldp s0,s1,[x2,+0x8]! + ldp s0,s1,[expression.dword]! + ldp s0,s1,[x2],+0x8 + + ldr b0,[x2] + ldr b0,[x2,+0x8] + ldr b0,[expression.byte] + ldr b0,[x2,+0x8]! + ldr b0,[expression.byte]! + ldr b0,[x2],+0x8 + ldr b0,[x2,w3,sxtw] + ldr b0,[x2,w3,sxtw 0] + ldr b0,[x2,w3,uxtw] + ldr b0,[x2,w3,uxtw 0] + ldr b0,[x2,x3] + ldr b0,[x2,x3,lsl 0] + ldr b0,[x2,x3,sxtx] + ldr b0,[x2,x3,sxtx 0] + ldr h0,[x2] + ldr h0,[x2,+0x8] + ldr h0,[expression.hword] + ldr h0,[x2,+0x8]! + ldr h0,[expression.hword]! + ldr h0,[x2],+0x8 + ldr h0,[x2,w3,sxtw] + ldr h0,[x2,w3,sxtw 1] + ldr h0,[x2,w3,uxtw] + ldr h0,[x2,w3,uxtw 1] + ldr h0,[x2,x3] + ldr h0,[x2,x3,lsl 1] + ldr h0,[x2,x3,sxtx] + ldr h0,[x2,x3,sxtx 1] + ldr s0,[x2,+0x8] + ldr s0,[expression.word] + ldr s0,[x2,+0x8]! + ldr s0,[expression.word]! + ldr s0,[x2],+0x8 + ldr s0,[x2,w3,sxtw] + ldr s0,[x2,w3,sxtw 2] + ldr s0,[x2,w3,uxtw] + ldr s0,[x2,w3,uxtw 2] + ldr s0,[x2,x3] + ldr s0,[x2,x3,lsl 2] + ldr s0,[x2,x3,sxtx] + ldr s0,[x2,x3,sxtx 2] + ldr s0,label_ldr + ldr s0,[label_ldr] + ldr d0,[x2,+0x8] + ldr d0,[expression.dword] + ldr d0,[x2,+0x8]! + ldr d0,[expression.dword]! + ldr d0,[x2],+0x8 + ldr d0,[x2,w3,sxtw] + ldr d0,[x2,w3,sxtw 3] + ldr d0,[x2,w3,uxtw] + ldr d0,[x2,w3,uxtw 3] + ldr d0,[x2,x3] + ldr d0,[x2,x3,lsl 3] + ldr d0,[x2,x3,sxtx] + ldr d0,[x2,x3,sxtx 3] + ldr d0,label_ldr + ldr d0,[label_ldr] + ldr q0,[x2,+0x8] + ldr q0,[expression.qword] + ldr q0,[x2,+0x8]! + ldr q0,[expression.qword]! + ldr q0,[x2],+0x8 + ldr q0,[x2,w3,sxtw] + ldr q0,[x2,w3,sxtw 4] + ldr q0,[x2,w3,uxtw] + ldr q0,[x2,w3,uxtw 4] + ldr q0,[x2,x3] + ldr q0,[x2,x3,lsl 4] + ldr q0,[x2,x3,sxtx] + ldr q0,[x2,x3,sxtx 4] + ldr q0,label_ldr + ldr q0,[label_ldr] + + ldur b0,[x2] + ldur b0,[x2,+0x8] + ldur b0,[expression.byte] + ldur h0,[x2] + ldur h0,[x2,+0x8] + ldur h0,[expression.hword] + ldur s0,[x2] + ldur s0,[x2,+0x8] + ldur s0,[expression.word] + ldur d0,[x2] + ldur d0,[x2,+0x8] + ldur d0,[expression.dword] + ldur q0,[x2] + ldur q0,[x2,+0x8] + ldur q0,[expression.qword] + + mla v1.16b,v2.16b,v3.16b + mla v1.2s,v2.2s,v3.2s + mla v1.2s,v2.2s,v3.s[0] + mla v1.4h,v2.4h,v3.4h + mla v1.4h,v2.4h,v3.h[0] + mla v1.4s,v2.4s,v3.4s + mla v1.4s,v2.4s,v3.s[3] + mla v1.8b,v2.8b,v3.8b + mla v1.8h,v2.8h,v3.8h + mla v1.8h,v2.8h,v3.h[7] + + mls v1.16b,v2.16b,v3.16b + mls v1.2s,v2.2s,v3.2s + mls v1.2s,v2.2s,v3.s[0] + mls v1.4h,v2.4h,v3.4h + mls v1.4h,v2.4h,v3.h[0] + mls v1.4s,v2.4s,v3.4s + mls v1.4s,v2.4s,v3.s[3] + mls v1.8b,v2.8b,v3.8b + mls v1.8h,v2.8h,v3.8h + mls v1.8h,v2.8h,v3.h[7] + + mov b1,v2.b[0] + mov h1,v2.h[7] + mov s1,v2.s[3] + mov d1,v2.d[1] + + mov v1.16b,v2.16b + mov v1.8b,v2.8b + mov v1.b[1],v2.b[15] + mov v1.d[0],v2.d[1] + mov v1.h[1],v2.h[7] + mov v1.s[1],v2.s[3] + mov v2.b[15],w1 + mov v2.d[1],x1 + mov v2.h[7],w1 + mov v2.s[3],w1 + mov w1,v2.s[0] + mov x1,v2.d[0] + + movi d1,0xFFFFFFFF00FF00FF + movi v1.16b,0xAA + movi v1.2d,0x00FF00FF00FF00FF + movi v1.2s,0xAA,lsl 0 + movi v1.2s,0xAA,lsl 8 + movi v1.2s,0xAA,lsl 16 + movi v1.2s,0xAA,lsl 24 + movi v1.2s,0xAA,msl 8 + movi v1.2s,0xAA,msl 16 + movi v1.4h,0xAA,lsl 0 + movi v1.4h,0xAA,lsl 8 + movi v1.4s,0xAA,lsl 0 + movi v1.4s,0xAA,lsl 8 + movi v1.4s,0xAA,lsl 16 + movi v1.4s,0xAA,lsl 24 + movi v1.4s,0xAA,msl 8 + movi v1.4s,0xAA,msl 16 + movi v1.8b,0xAA + movi v1.8h,0xAA,lsl 0 + movi v1.8h,0xAA,lsl 8 + + mul v1.16b,v2.16b,v3.16b + mul v1.2s,v2.2s,v3.2s + mul v1.2s,v2.2s,v3.s[0] + mul v1.4h,v2.4h,v3.4h + mul v1.4h,v2.4h,v3.h[0] + mul v1.4s,v2.4s,v3.4s + mul v1.4s,v2.4s,v3.s[3] + mul v1.8b,v2.8b,v3.8b + mul v1.8h,v2.8h,v3.8h + mul v1.8h,v2.8h,v3.h[7] + + mvn v1.16b,v2.16b + mvn v1.8b,v2.8b + + mvni v1.2s,0xAA + mvni v1.2s,0xAA,lsl 0 + mvni v1.2s,0xAA,lsl 8 + mvni v1.2s,0xAA,lsl 16 + mvni v1.2s,0xAA,lsl 24 + mvni v1.2s,0xAA,msl 8 + mvni v1.2s,0xAA,msl 16 + mvni v1.4h,0xAA + mvni v1.4h,0xAA,lsl 0 + mvni v1.4h,0xAA,lsl 8 + mvni v1.4s,0xAA + mvni v1.4s,0xAA,lsl 0 + mvni v1.4s,0xAA,lsl 8 + mvni v1.4s,0xAA,lsl 16 + mvni v1.4s,0xAA,lsl 24 + mvni v1.4s,0xAA,msl 8 + mvni v1.4s,0xAA,msl 16 + mvni v1.8h,0xAA + mvni v1.8h,0xAA,lsl 0 + mvni v1.8h,0xAA,lsl 8 + + neg d1,d2 + neg v1.16b,v2.16b + neg v1.2d,v2.2d + neg v1.2s,v2.2s + neg v1.4h,v2.4h + neg v1.4s,v2.4s + neg v1.8b,v2.8b + neg v1.8h,v2.8h + + not v1.8b,v2.8b + not v1.16b,v2.16b + + orn v1.16b,v2.16b,v3.16b + orn v1.8b,v2.8b,v3.8b + + orr v1.16b,v2.16b,v3.16b + orr v1.8b,v2.8b,v3.8b + orr v1.4h,0xFE + orr v1.4h,0xFE,lsl 0 + orr v3.8h,0xFB + orr v3.8h,0xFB,lsl 0 + orr v4.8h,0xF7,lsl 8 + orr v5.2s,0xEF + orr v5.2s,0xEF,lsl 0 + orr v6.2s,0xDF,lsl 16 + orr v7.4s,0xBF + orr v7.4s,0xBF,lsl 0 + orr v8.4s,0x80,lsl 24 + + pmul v1.16b,v2.16b,v3.16b + pmul v1.8b,v2.8b,v3.8b + + pmull v1.8h,v2.8b,v3.8b + + pmull2 v1.8h,v2.16b,v3.16b + + raddhn v1.2s,v2.2d,v3.2d + raddhn v1.4h,v2.4s,v3.4s + raddhn v1.8b,v2.8h,v3.8h + + raddhn2 v1.16b,v2.8h,v3.8h + raddhn2 v1.4s,v2.2d,v3.2d + raddhn2 v1.8h,v2.4s,v3.4s + + rbit v1.16b,v2.16b + rbit v1.8b,v2.8b + + rev16 v1.16b,v2.16b + rev16 v1.8b,v2.8b + + rev32 v1.16b,v2.16b + rev32 v1.4h,v2.4h + rev32 v1.8b,v2.8b + rev32 v1.8h,v2.8h + + rev64 v1.16b,v2.16b + rev64 v1.2s,v2.2s + rev64 v1.4h,v2.4h + rev64 v1.4s,v2.4s + rev64 v1.8b,v2.8b + rev64 v1.8h,v2.8h + + rshrn v1.2s,v2.2d,32 + rshrn v1.4h,v2.4s,16 + rshrn v1.8b,v2.8h,8 + + rshrn2 v1.16b,v2.8h,8 + rshrn2 v1.4s,v2.2d,32 + rshrn2 v1.8h,v2.4s,16 + + rsubhn v1.2s,v2.2d,v3.2d + rsubhn v1.4h,v2.4s,v3.4s + rsubhn v1.8b,v2.8h,v3.8h + + rsubhn2 v1.16b,v2.8h,v3.8h + rsubhn2 v1.4s,v2.2d,v3.2d + rsubhn2 v1.8h,v2.4s,v3.4s + + saba v1.16b,v2.16b,v3.16b + saba v1.2s,v2.2s,v3.2s + saba v1.4h,v2.4h,v3.4h + saba v1.4s,v2.4s,v3.4s + saba v1.8b,v2.8b,v3.8b + saba v1.8h,v2.8h,v3.8h + + sabal v1.2d,v2.2s,v3.2s + sabal v1.4s,v2.4h,v3.4h + sabal v1.8h,v2.8b,v3.8b + + sabal2 v1.2d,v2.4s,v3.4s + sabal2 v1.4s,v2.8h,v3.8h + sabal2 v1.8h,v2.16b,v3.16b + + sabd v1.16b,v2.16b,v3.16b + sabd v1.2s,v2.2s,v3.2s + sabd v1.4h,v2.4h,v3.4h + sabd v1.4s,v2.4s,v3.4s + sabd v1.8b,v2.8b,v3.8b + sabd v1.8h,v2.8h,v3.8h + + sabdl v1.2d,v2.2s,v3.2s + sabdl v1.4s,v2.4h,v3.4h + sabdl v1.8h,v2.8b,v3.8b + + sabdl2 v1.2d,v2.4s,v3.4s + sabdl2 v1.4s,v2.8h,v3.8h + sabdl2 v1.8h,v2.16b,v3.16b + + sadalp v1.1d,v2.2s + sadalp v1.2d,v2.4s + sadalp v1.2s,v2.4h + sadalp v1.4h,v2.8b + sadalp v1.4s,v2.8h + sadalp v1.8h,v2.16b + + saddl v1.2d,v2.2s,v3.2s + saddl v1.4s,v2.4h,v3.4h + saddl v1.8h,v2.8b,v3.8b + + saddl2 v1.2d,v2.4s,v3.4s + saddl2 v1.4s,v2.8h,v3.8h + saddl2 v1.8h,v2.16b,v3.16b + + saddlp v1.1d,v2.2s + saddlp v1.2d,v2.4s + saddlp v1.2s,v2.4h + saddlp v1.4h,v2.8b + saddlp v1.4s,v2.8h + saddlp v1.8h,v2.16b + + saddlv d1,v2.4s + saddlv h1,v2.16b + saddlv h1,v2.8b + saddlv s1,v2.4h + saddlv s1,v2.8h + + saddw v1.2d,v2.2d,v3.2s + saddw v1.4s,v2.4s,v3.4h + saddw v1.8h,v2.8h,v3.8b + + saddw2 v1.2d,v2.2d,v3.4s + saddw2 v1.4s,v2.4s,v3.8h + saddw2 v1.8h,v2.8h,v3.16b + + shadd v1.16b,v2.16b,v3.16b + shadd v1.2s,v2.2s,v3.2s + shadd v1.4h,v2.4h,v3.4h + shadd v1.4s,v2.4s,v3.4s + shadd v1.8b,v2.8b,v3.8b + shadd v1.8h,v2.8h,v3.8h + + shl d1,d2,1 + shl v1.16b,v2.16b,7 + shl v1.2d,v2.2d,63 + shl v1.2s,v2.2s,1 + shl v1.4h,v2.4h,1 + shl v1.4s,v2.4s,31 + shl v1.8b,v2.8b,1 + shl v1.8h,v2.8h,15 + + shll v1.2d,v2.2s,32 + shll v1.4s,v2.4h,16 + shll v1.8h,v2.8b,8 + + shll2 v1.2d,v2.4s,32 + shll2 v1.4s,v2.8h,16 + shll2 v1.8h,v2.16b,8 + + shrn v1.2s,v2.2d,3 + shrn v1.4h,v2.4s,2 + shrn v1.8b,v2.8h,1 + + shrn2 v1.16b,v2.8h,1 + shrn2 v1.4s,v2.2d,3 + shrn2 v1.8h,v2.4s,2 + + shsub v1.16b,v2.16b,v3.16b + shsub v1.2s,v2.2s,v3.2s + shsub v1.4h,v2.4h,v3.4h + shsub v1.4s,v2.4s,v3.4s + shsub v1.8b,v2.8b,v3.8b + shsub v1.8h,v2.8h,v3.8h + + sli d1,d2,1 + sli v1.16b,v2.16b,7 + sli v1.2d,v2.2d,63 + sli v1.2s,v2.2s,1 + sli v1.4h,v2.4h,1 + sli v1.4s,v2.4s,31 + sli v1.8b,v2.8b,1 + sli v1.8h,v2.8h,15 + + smax v1.16b,v2.16b,v3.16b + smax v1.2s,v2.2s,v3.2s + smax v1.4h,v2.4h,v3.4h + smax v1.4s,v2.4s,v3.4s + smax v1.8b,v2.8b,v3.8b + smax v1.8h,v2.8h,v3.8h + + smaxp v1.16b,v2.16b,v3.16b + smaxp v1.2s,v2.2s,v3.2s + smaxp v1.4h,v2.4h,v3.4h + smaxp v1.4s,v2.4s,v3.4s + smaxp v1.8b,v2.8b,v3.8b + smaxp v1.8h,v2.8h,v3.8h + + smaxv b1,v2.16b + smaxv b1,v2.8b + smaxv h1,v2.4h + smaxv h1,v2.8h + smaxv s1,v2.4s + + smin v1.16b,v2.16b,v3.16b + smin v1.2s,v2.2s,v3.2s + smin v1.4h,v2.4h,v3.4h + smin v1.4s,v2.4s,v3.4s + smin v1.8b,v2.8b,v3.8b + smin v1.8h,v2.8h,v3.8h + + sminp v1.16b,v2.16b,v3.16b + sminp v1.2s,v2.2s,v3.2s + sminp v1.4h,v2.4h,v3.4h + sminp v1.4s,v2.4s,v3.4s + sminp v1.8b,v2.8b,v3.8b + sminp v1.8h,v2.8h,v3.8h + + sminv b1,v2.16b + sminv b1,v2.8b + sminv h1,v2.4h + sminv h1,v2.8h + sminv s1,v2.4s + + smlal v1.2d,v2.2s,v3.2s + smlal v1.2d,v2.2s,v31.s[3] + smlal v1.4s,v2.4h,v15.h[7] + smlal v1.4s,v2.4h,v3.4h + smlal v1.8h,v2.8b,v3.8b + + smlal2 v1.2d,v2.4s,v3.4s + smlal2 v1.2d,v2.4s,v31.s[3] + smlal2 v1.4s,v2.8h,v15.h[7] + smlal2 v1.4s,v2.8h,v3.8h + smlal2 v1.8h,v2.16b,v3.16b + + smlsl v1.2d,v2.2s,v3.2s + smlsl v1.2d,v2.2s,v31.s[3] + smlsl v1.4s,v2.4h,v15.h[7] + smlsl v1.4s,v2.4h,v3.4h + smlsl v1.8h,v2.8b,v3.8b + + smlsl2 v1.2d,v2.4s,v3.4s + smlsl2 v1.2d,v2.4s,v31.s[3] + smlsl2 v1.4s,v2.8h,v15.h[7] + smlsl2 v1.4s,v2.8h,v3.8h + smlsl2 v1.8h,v2.16b,v3.16b + + smov w1,v2.b[15] + smov w1,v2.h[7] + smov x1,v2.b[4] + smov x1,v2.h[2] + smov x1,v2.s[1] + + smull v1.2d,v2.2s,v3.2s + smull v1.2d,v2.2s,v3.s[0] + smull v1.2d,v2.2s,v31.s[3] + smull v1.4s,v2.4h,v15.h[7] + smull v1.4s,v2.4h,v3.4h + smull v1.4s,v2.4h,v3.h[0] + smull v1.8h,v2.8b,v3.8b + + smull2 v1.2d,v2.4s,v3.4s + smull2 v1.2d,v2.4s,v31.s[3] + smull2 v1.4s,v2.8h,v15.h[7] + smull2 v1.4s,v2.8h,v3.8h + smull2 v1.8h,v2.16b,v3.16b + + sqabs b1,b2 + sqabs d1,d2 + sqabs h1,h2 + sqabs s1,s2 + sqabs v1.16b,v2.16b + sqabs v1.2d,v2.2d + sqabs v1.2s,v2.2s + sqabs v1.4h,v2.4h + sqabs v1.4s,v2.4s + sqabs v1.8b,v2.8b + sqabs v1.8h,v2.8h + + sqadd b1,b2,b3 + sqadd d1,d2,d3 + sqadd h1,h2,h3 + sqadd s1,s2,s3 + sqadd v1.16b,v2.16b,v3.16b + sqadd v1.2d,v2.2d,v3.2d + sqadd v1.2s,v2.2s,v3.2s + sqadd v1.4h,v2.4h,v3.4h + sqadd v1.4s,v2.4s,v3.4s + sqadd v1.8b,v2.8b,v3.8b + sqadd v1.8h,v2.8h,v3.8h + + sqdmlal v1.2d,v2.2s,v3.2s + sqdmlal v1.2d,v2.2s,v31.s[3] + sqdmlal v1.4s,v2.4h,v15.h[7] + sqdmlal v1.4s,v2.4h,v3.4h + + sqdmlal2 v1.2d,v2.4s,v3.4s + sqdmlal2 v1.2d,v2.4s,v31.s[3] + sqdmlal2 v1.4s,v2.8h,v15.h[7] + sqdmlal2 v1.4s,v2.8h,v3.8h + + sqdmlsl v1.2d,v2.2s,v3.2s + sqdmlsl v1.2d,v2.2s,v31.s[3] + sqdmlsl v1.4s,v2.4h,v15.h[7] + sqdmlsl v1.4s,v2.4h,v3.4h + + sqdmlsl2 v1.2d,v2.4s,v3.4s + sqdmlsl2 v1.2d,v2.4s,v31.s[3] + sqdmlsl2 v1.4s,v2.8h,v15.h[7] + sqdmlsl2 v1.4s,v2.8h,v3.8h + + sqdmulh h1,h2,h3 + sqdmulh h1,h2,v3.h[7] + sqdmulh s1,s2,s3 + sqdmulh s1,s2,v3.s[3] + sqdmulh v1.2s,v2.2s,v3.2s + sqdmulh v1.2s,v2.2s,v3.s[0] + sqdmulh v1.4h,v2.4h,v3.4h + sqdmulh v1.4h,v2.4h,v3.h[0] + sqdmulh v1.4s,v2.4s,v3.4s + sqdmulh v1.4s,v2.4s,v3.s[3] + sqdmulh v1.8h,v2.8h,v3.8h + sqdmulh v1.8h,v2.8h,v3.h[7] + + sqdmull v1.2d,v2.2s,v3.2s + sqdmull v1.2d,v2.2s,v31.s[3] + sqdmull v1.4s,v2.4h,v15.h[7] + sqdmull v1.4s,v2.4h,v3.4h + + sqdmull2 v1.2d,v2.4s,v3.4s + sqdmull2 v1.2d,v2.4s,v31.s[3] + sqdmull2 v1.4s,v2.8h,v15.h[7] + sqdmull2 v1.4s,v2.8h,v3.8h + + sqneg b1,b2 + sqneg d1,d2 + sqneg h1,h2 + sqneg s1,s2 + sqneg v1.16b,v2.16b + sqneg v1.2d,v2.2d + sqneg v1.2s,v2.2s + sqneg v1.4h,v2.4h + sqneg v1.4s,v2.4s + sqneg v1.8b,v2.8b + sqneg v1.8h,v2.8h + + sqrdmulh h1,h2,h3 + sqrdmulh h1,h2,v3.h[7] + sqrdmulh s1,s2,s3 + sqrdmulh s1,s2,v3.s[3] + sqrdmulh v1.2s,v2.2s,v3.2s + sqrdmulh v1.2s,v2.2s,v3.s[0] + sqrdmulh v1.4h,v2.4h,v3.4h + sqrdmulh v1.4h,v2.4h,v3.h[0] + sqrdmulh v1.4s,v2.4s,v3.4s + sqrdmulh v1.4s,v2.4s,v3.s[3] + sqrdmulh v1.8h,v2.8h,v3.8h + sqrdmulh v1.8h,v2.8h,v3.h[7] + + sqrshl b1,b2,b3 + sqrshl d1,d2,d3 + sqrshl h1,h2,h3 + sqrshl s1,s2,s3 + sqrshl v1.16b,v2.16b,v3.16b + sqrshl v1.2d,v2.2d,v3.2d + sqrshl v1.2s,v2.2s,v3.2s + sqrshl v1.4h,v2.4h,v3.4h + sqrshl v1.4s,v2.4s,v3.4s + sqrshl v1.8b,v2.8b,v3.8b + sqrshl v1.8h,v2.8h,v3.8h + + sqrshrn b8,h8,1 + sqrshrn h4,s4,2 + sqrshrn s2,d2,3 + sqrshrn v1.2s,v2.2d,3 + sqrshrn v1.4h,v2.4s,2 + sqrshrn v1.8b,v2.8h,1 + + sqrshrn2 v1.16b,v2.8h,1 + sqrshrn2 v1.4s,v2.2d,3 + sqrshrn2 v1.8h,v2.4s,2 + + sqrshrun b8,h8,1 + sqrshrun h4,s4,2 + sqrshrun s2,d2,3 + sqrshrun v1.8b,v2.8h,1 + sqrshrun v1.4h,v2.4s,2 + sqrshrun v1.2s,v2.2d,3 + + sqrshrun2 v1.16b,v2.8h,1 + sqrshrun2 v1.8h,v2.4s,2 + sqrshrun2 v1.4s,v2.2d,3 + + sqshl b1,b2,1 + sqshl b1,b2,b3 + sqshl d1,d2,1 + sqshl d1,d2,d3 + sqshl h1,h2,1 + sqshl h1,h2,h3 + sqshl s1,s2,1 + sqshl s1,s2,s3 + sqshl v1.16b,v2.16b,7 + sqshl v1.16b,v2.16b,v3.16b + sqshl v1.2d,v2.2d,63 + sqshl v1.2d,v2.2d,v3.2d + sqshl v1.2s,v2.2s,1 + sqshl v1.2s,v2.2s,v3.2s + sqshl v1.4h,v2.4h,1 + sqshl v1.4h,v2.4h,v3.4h + sqshl v1.4s,v2.4s,31 + sqshl v1.4s,v2.4s,v3.4s + sqshl v1.8b,v2.8b,1 + sqshl v1.8b,v2.8b,v3.8b + sqshl v1.8h,v2.8h,15 + sqshl v1.8h,v2.8h,v3.8h + + sqshlu b1,b2,1 + sqshlu d1,d2,1 + sqshlu h1,h2,1 + sqshlu s1,s2,1 + sqshlu v1.16b,v2.16b,7 + sqshlu v1.2d,v2.2d,63 + sqshlu v1.2s,v2.2s,1 + sqshlu v1.4h,v2.4h,1 + sqshlu v1.4s,v2.4s,31 + sqshlu v1.8b,v2.8b,1 + sqshlu v1.8h,v2.8h,15 + + sqshrn b8,h8,1 + sqshrn h4,s4,2 + sqshrn s2,d2,3 + sqshrn v1.2s,v2.2d,3 + sqshrn v1.4h,v2.4s,2 + sqshrn v1.8b,v2.8h,1 + + sqshrn2 v1.16b,v2.8h,1 + sqshrn2 v1.4s,v2.2d,3 + sqshrn2 v1.8h,v2.4s,2 + + sqshrun b8,h8,1 + sqshrun h4,s4,2 + sqshrun s2,d2,3 + sqshrun v1.8b,v2.8h,1 + sqshrun v1.4h,v2.4s,2 + sqshrun v1.2s,v2.2d,3 + + sqshrun2 v1.16b,v2.8h,1 + sqshrun2 v1.8h,v2.4s,2 + sqshrun2 v1.4s,v2.2d,3 + + sqsub b1,b2,b3 + sqsub d1,d2,d3 + sqsub h1,h2,h3 + sqsub s1,s2,s3 + sqsub v1.16b,v2.16b,v3.16b + sqsub v1.2d,v2.2d,v3.2d + sqsub v1.2s,v2.2s,v3.2s + sqsub v1.4h,v2.4h,v3.4h + sqsub v1.4s,v2.4s,v3.4s + sqsub v1.8b,v2.8b,v3.8b + sqsub v1.8h,v2.8h,v3.8h + + sqxtn b8,h8 + sqxtn h4,s4 + sqxtn s2,d2 + sqxtn v1.2s,v2.2d + sqxtn v1.4h,v2.4s + sqxtn v1.8b,v2.8h + + sqxtn2 v1.16b,v2.8h + sqxtn2 v1.4s,v2.2d + sqxtn2 v1.8h,v2.4s + + sqxtun b8,h8 + sqxtun h4,s4 + sqxtun s2,d2 + sqxtun v1.2s,v2.2d + sqxtun v1.4h,v2.4s + sqxtun v1.8b,v2.8h + + sqxtun2 v1.16b,v2.8h + sqxtun2 v1.4s,v2.2d + sqxtun2 v1.8h,v2.4s + + srhadd v1.16b,v2.16b,v3.16b + srhadd v1.2s,v2.2s,v3.2s + srhadd v1.4h,v2.4h,v3.4h + srhadd v1.4s,v2.4s,v3.4s + srhadd v1.8b,v2.8b,v3.8b + srhadd v1.8h,v2.8h,v3.8h + + sri d1,d2,1 + sri v1.16b,v2.16b,8 + sri v1.2d,v2.2d,64 + sri v1.2s,v2.2s,1 + sri v1.4h,v2.4h,1 + sri v1.4s,v2.4s,32 + sri v1.8b,v2.8b,1 + sri v1.8h,v2.8h,16 + + srshl d1,d2,d3 + srshl v1.16b,v2.16b,v3.16b + srshl v1.2d,v2.2d,v3.2d + srshl v1.2s,v2.2s,v3.2s + srshl v1.4h,v2.4h,v3.4h + srshl v1.4s,v2.4s,v3.4s + srshl v1.8b,v2.8b,v3.8b + srshl v1.8h,v2.8h,v3.8h + + srshr d1,d2,1 + srshr v1.16b,v2.16b,8 + srshr v1.2d,v2.2d,64 + srshr v1.2s,v2.2s,1 + srshr v1.4h,v2.4h,1 + srshr v1.4s,v2.4s,32 + srshr v1.8b,v2.8b,1 + srshr v1.8h,v2.8h,16 + + srsra d1,d2,1 + srsra v1.16b,v2.16b,8 + srsra v1.2d,v2.2d,64 + srsra v1.2s,v2.2s,1 + srsra v1.4h,v2.4h,1 + srsra v1.4s,v2.4s,32 + srsra v1.8b,v2.8b,1 + srsra v1.8h,v2.8h,16 + + sshl d1,d2,d3 + sshl v1.16b,v2.16b,v3.16b + sshl v1.2d,v2.2d,v3.2d + sshl v1.2s,v2.2s,v3.2s + sshl v1.4h,v2.4h,v3.4h + sshl v1.4s,v2.4s,v3.4s + sshl v1.8b,v2.8b,v3.8b + sshl v1.8h,v2.8h,v3.8h + + sshll v1.2d,v2.2s,3 + sshll v1.4s,v2.4h,2 + sshll v1.8h,v2.8b,1 + + sshll2 v1.2d,v2.4s,31 + sshll2 v1.4s,v2.8h,15 + sshll2 v1.8h,v2.16b,7 + + sshr d1,d2,1 + sshr v1.16b,v2.16b,8 + sshr v1.2d,v2.2d,64 + sshr v1.2s,v2.2s,1 + sshr v1.4h,v2.4h,1 + sshr v1.4s,v2.4s,32 + sshr v1.8b,v2.8b,1 + sshr v1.8h,v2.8h,16 + + ssra d1,d2,1 + ssra v1.16b,v2.16b,8 + ssra v1.2d,v2.2d,64 + ssra v1.2s,v2.2s,1 + ssra v1.4h,v2.4h,1 + ssra v1.4s,v2.4s,32 + ssra v1.8b,v2.8b,1 + ssra v1.8h,v2.8h,16 + + ssubl v1.2d,v2.2s,v3.2s + ssubl v1.4s,v2.4h,v3.4h + ssubl v1.8h,v2.8b,v3.8b + + ssubl2 v1.2d,v2.4s,v3.4s + ssubl2 v1.4s,v2.8h,v3.8h + ssubl2 v1.8h,v2.16b,v3.16b + + ssubw v1.2d,v2.2d,v3.2s + ssubw v1.4s,v2.4s,v3.4h + ssubw v1.8h,v2.8h,v3.8b + + ssubw2 v1.2d,v2.2d,v3.4s + ssubw2 v1.4s,v2.4s,v3.8h + ssubw2 v1.8h,v2.8h,v3.16b + + st1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp] + st1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp],64 + st1 {v1.16b,v2.16b,v3.16b,v4.16b},[sp],x6 + st1 {v1.16b,v2.16b,v3.16b},[x4] + st1 {v1.16b,v2.16b,v3.16b},[x4],48 + st1 {v1.16b,v2.16b,v3.16b},[x4],x5 + st1 {v1.16b,v2.16b},[x3] + st1 {v1.16b,v2.16b},[x3],32 + st1 {v1.16b,v2.16b},[x3],x4 + st1 {v1.16b},[x2] + st1 {v1.16b},[x2],16 + st1 {v1.16b},[x2],x3 + st1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp] + st1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp],32 + st1 {v1.1d,v2.1d,v3.1d,v4.1d},[sp],x6 + st1 {v1.1d,v2.1d,v3.1d},[x4] + st1 {v1.1d,v2.1d,v3.1d},[x4],24 + st1 {v1.1d,v2.1d,v3.1d},[x4],x5 + st1 {v1.1d,v2.1d},[x3] + st1 {v1.1d,v2.1d},[x3],16 + st1 {v1.1d,v2.1d},[x3],x4 + st1 {v1.1d},[x2] + st1 {v1.1d},[x2],8 + st1 {v1.1d},[x2],x3 + st1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp] + st1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp],64 + st1 {v1.2d,v2.2d,v3.2d,v4.2d},[sp],x6 + st1 {v1.2d,v2.2d,v3.2d},[x4] + st1 {v1.2d,v2.2d,v3.2d},[x4],48 + st1 {v1.2d,v2.2d,v3.2d},[x4],x5 + st1 {v1.2d,v2.2d},[x3] + st1 {v1.2d,v2.2d},[x3],32 + st1 {v1.2d,v2.2d},[x3],x4 + st1 {v1.2d},[x2] + st1 {v1.2d},[x2],16 + st1 {v1.2d},[x2],x3 + st1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp] + st1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp],32 + st1 {v1.2s,v2.2s,v3.2s,v4.2s},[sp],x6 + st1 {v1.2s,v2.2s,v3.2s},[x4] + st1 {v1.2s,v2.2s,v3.2s},[x4],24 + st1 {v1.2s,v2.2s,v3.2s},[x4],x5 + st1 {v1.2s,v2.2s},[x3] + st1 {v1.2s,v2.2s},[x3],16 + st1 {v1.2s,v2.2s},[x3],x4 + st1 {v1.2s},[x2] + st1 {v1.2s},[x2],8 + st1 {v1.2s},[x2],x3 + st1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp] + st1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp],32 + st1 {v1.4h,v2.4h,v3.4h,v4.4h},[sp],x6 + st1 {v1.4h,v2.4h,v3.4h},[x4] + st1 {v1.4h,v2.4h,v3.4h},[x4],24 + st1 {v1.4h,v2.4h,v3.4h},[x4],x5 + st1 {v1.4h,v2.4h},[x3] + st1 {v1.4h,v2.4h},[x3],16 + st1 {v1.4h,v2.4h},[x3],x4 + st1 {v1.4h},[x2] + st1 {v1.4h},[x2],8 + st1 {v1.4h},[x2],x3 + st1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp] + st1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp],64 + st1 {v1.4s,v2.4s,v3.4s,v4.4s},[sp],x6 + st1 {v1.4s,v2.4s,v3.4s},[x4] + st1 {v1.4s,v2.4s,v3.4s},[x4],48 + st1 {v1.4s,v2.4s,v3.4s},[x4],x5 + st1 {v1.4s,v2.4s},[x3] + st1 {v1.4s,v2.4s},[x3],32 + st1 {v1.4s,v2.4s},[x3],x4 + st1 {v1.4s},[x2] + st1 {v1.4s},[x2],16 + st1 {v1.4s},[x2],x3 + st1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp] + st1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp],32 + st1 {v1.8b,v2.8b,v3.8b,v4.8b},[sp],x6 + st1 {v1.8b,v2.8b,v3.8b},[x4] + st1 {v1.8b,v2.8b,v3.8b},[x4],24 + st1 {v1.8b,v2.8b,v3.8b},[x4],x5 + st1 {v1.8b,v2.8b},[x3] + st1 {v1.8b,v2.8b},[x3],16 + st1 {v1.8b,v2.8b},[x3],x4 + st1 {v1.8b},[x2] + st1 {v1.8b},[x2],8 + st1 {v1.8b},[x2],x3 + st1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp] + st1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp],64 + st1 {v1.8h,v2.8h,v3.8h,v4.8h},[sp],x6 + st1 {v1.8h,v2.8h,v3.8h},[x4] + st1 {v1.8h,v2.8h,v3.8h},[x4],48 + st1 {v1.8h,v2.8h,v3.8h},[x4],x5 + st1 {v1.8h,v2.8h},[x3] + st1 {v1.8h,v2.8h},[x3],32 + st1 {v1.8h,v2.8h},[x3],x4 + st1 {v1.8h},[x2] + st1 {v1.8h},[x2],16 + st1 {v1.8h},[x2],x3 + st1 {v1.b}[2],[x3] + st1 {v1.b}[2],[x3],1 + st1 {v1.b}[2],[x3],x4 + st1 {v1.d}[1],[x3] + st1 {v1.d}[1],[x3],8 + st1 {v1.d}[1],[x3],x4 + st1 {v1.h}[2],[x3] + st1 {v1.h}[2],[x3],2 + st1 {v1.h}[2],[x3],x4 + st1 {v1.s}[2],[x3] + st1 {v1.s}[2],[x3],4 + st1 {v1.s}[2],[x3],x4 + + st2 {v1.16b,v2.16b},[x3] + st2 {v1.16b,v2.16b},[x3],32 + st2 {v1.16b,v2.16b},[x3],x4 + st2 {v1.2d,v2.2d},[x3] + st2 {v1.2d,v2.2d},[x3],32 + st2 {v1.2d,v2.2d},[x3],x4 + st2 {v1.2s,v2.2s},[x3] + st2 {v1.2s,v2.2s},[x3],16 + st2 {v1.2s,v2.2s},[x3],x4 + st2 {v1.4h,v2.4h},[x3] + st2 {v1.4h,v2.4h},[x3],16 + st2 {v1.4h,v2.4h},[x3],x4 + st2 {v1.4s,v2.4s},[x3] + st2 {v1.4s,v2.4s},[x3],32 + st2 {v1.4s,v2.4s},[x3],x4 + st2 {v1.8b,v2.8b},[x3] + st2 {v1.8b,v2.8b},[x3],16 + st2 {v1.8b,v2.8b},[x3],x4 + st2 {v1.8h,v2.8h},[x3] + st2 {v1.8h,v2.8h},[x3],32 + st2 {v1.8h,v2.8h},[x3],x4 + st2 {v1.b,v2.b}[15],[x3] + st2 {v1.b,v2.b}[2],[x3],2 + st2 {v1.b,v2.b}[2],[x3],x4 + st2 {v1.d,v2.d}[1],[x3] + st2 {v1.d,v2.d}[1],[x3],16 + st2 {v1.d,v2.d}[1],[x3],x4 + st2 {v1.h,v2.h}[2],[x3] + st2 {v1.h,v2.h}[2],[x3],4 + st2 {v1.h,v2.h}[2],[x3],x4 + st2 {v1.s,v2.s}[2],[x3] + st2 {v1.s,v2.s}[2],[x3],8 + st2 {v1.s,v2.s}[2],[x3],x4 + + st3 {v1.16b,v2.16b,v3.16b},[x3] + st3 {v1.16b,v2.16b,v3.16b},[x3],48 + st3 {v1.16b,v2.16b,v3.16b},[x3],x4 + st3 {v1.2d,v2.2d,v3.2d},[x3] + st3 {v1.2d,v2.2d,v3.2d},[x3],48 + st3 {v1.2d,v2.2d,v3.2d},[x3],x4 + st3 {v1.2s,v2.2s,v3.2s},[x3] + st3 {v1.2s,v2.2s,v3.2s},[x3],24 + st3 {v1.2s,v2.2s,v3.2s},[x3],x4 + st3 {v1.4h,v2.4h,v3.4h},[x3] + st3 {v1.4h,v2.4h,v3.4h},[x3],24 + st3 {v1.4h,v2.4h,v3.4h},[x3],x4 + st3 {v1.4s,v2.4s,v3.4s},[x3] + st3 {v1.4s,v2.4s,v3.4s},[x3],48 + st3 {v1.4s,v2.4s,v3.4s},[x3],x4 + st3 {v1.8b,v2.8b,v3.8b},[x3] + st3 {v1.8b,v2.8b,v3.8b},[x3],24 + st3 {v1.8b,v2.8b,v3.8b},[x3],x4 + st3 {v1.8h,v2.8h,v3.8h},[x3] + st3 {v1.8h,v2.8h,v3.8h},[x3],48 + st3 {v1.8h,v2.8h,v3.8h},[x3],x4 + st3 {v1.b,v2.b,v3.b}[15],[x3] + st3 {v1.b,v2.b,v3.b}[2],[x3],3 + st3 {v1.b,v2.b,v3.b}[2],[x3],x4 + st3 {v1.d,v2.d,v3.d}[1],[x3] + st3 {v1.d,v2.d,v3.d}[1],[x3],24 + st3 {v1.d,v2.d,v3.d}[1],[x3],x4 + st3 {v1.h,v2.h,v3.h}[2],[x3] + st3 {v1.h,v2.h,v3.h}[2],[x3],6 + st3 {v1.h,v2.h,v3.h}[2],[x3],x4 + st3 {v1.s,v2.s,v3.s}[2],[x3] + st3 {v1.s,v2.s,v3.s}[2],[x3],12 + st3 {v1.s,v2.s,v3.s}[2],[x3],x4 + + st4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3] + st4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3],64 + st4 {v1.16b,v2.16b,v3.16b,v4.16b},[x3],x4 + st4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3] + st4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3],64 + st4 {v1.2d,v2.2d,v3.2d,v4.2d},[x3],x4 + st4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3] + st4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3],32 + st4 {v1.2s,v2.2s,v3.2s,v4.2s},[x3],x4 + st4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3] + st4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3],32 + st4 {v1.4h,v2.4h,v3.4h,v4.4h},[x3],x4 + st4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3] + st4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3],64 + st4 {v1.4s,v2.4s,v3.4s,v4.4s},[x3],x4 + st4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3] + st4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3],32 + st4 {v1.8b,v2.8b,v3.8b,v4.8b},[x3],x4 + st4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3] + st4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3],64 + st4 {v1.8h,v2.8h,v3.8h,v4.8h},[x3],x4 + st4 {v1.b,v2.b,v3.b,v4.b}[15],[x3] + st4 {v1.b,v2.b,v3.b,v4.b}[2],[x3],4 + st4 {v1.b,v2.b,v3.b,v4.b}[2],[x3],x4 + st4 {v1.d,v2.d,v3.d,v4.d}[1],[x3] + st4 {v1.d,v2.d,v3.d,v4.d}[1],[x3],32 + st4 {v1.d,v2.d,v3.d,v4.d}[1],[x3],x4 + st4 {v1.h,v2.h,v3.h,v4.h}[2],[x3] + st4 {v1.h,v2.h,v3.h,v4.h}[2],[x3],8 + st4 {v1.h,v2.h,v3.h,v4.h}[2],[x3],x4 + st4 {v1.s,v2.s,v3.s,v4.s}[2],[x3] + st4 {v1.s,v2.s,v3.s,v4.s}[2],[x3],16 + st4 {v1.s,v2.s,v3.s,v4.s}[2],[x3],x4 + + stnp d0,d1,[x2] + stnp d0,d1,[x2,+0x8] + stnp d0,d1,[expression.qword] + stnp q0,q1,[x2] + stnp q0,q1,[x2,+0x20] + stnp q0,q1,[expression.dqword] + stnp s0,s1,[x2] + stnp s0,s1,[x2,+0x8] + stnp s0,s1,[expression.dword] + + stp d0,d1,[x2] + stp d0,d1,[x2,+0x8] + stp d0,d1,[expression.qword] + stp d0,d1,[x2,+0x8]! + stp d0,d1,[expression.qword]! + stp d0,d1,[x2],+0x8 + stp q0,q1,[x2] + stp q0,q1,[x2,+0x10] + stp q0,q1,[expression.dqword] + stp q0,q1,[x2,+0x10]! + stp q0,q1,[expression.dqword]! + stp q0,q1,[x2],+0x10 + stp s0,s1,[x2] + stp s0,s1,[x2,+0x8] + stp s0,s1,[expression.dword] + stp s0,s1,[x2,+0x8]! + stp s0,s1,[expression.dword]! + stp s0,s1,[x2],+0x8 + + str b0,[x2] + str b0,[x2,+0x8] + str b0,[expression.byte] + str b0,[x2,+0x8]! + str b0,[expression.byte]! + str b0,[x2],+0x8 + str b0,[x2,w3,sxtw] + str b0,[x2,w3,sxtw 0] + str b0,[x2,w3,uxtw] + str b0,[x2,w3,uxtw 0] + str b0,[x2,x3] + str b0,[x2,x3,lsl 0] + str b0,[x2,x3,sxtx] + str b0,[x2,x3,sxtx 0] + str h0,[x2] + str h0,[x2,+0x8] + str h0,[expression.hword] + str h0,[x2,+0x8]! + str h0,[expression.hword]! + str h0,[x2],+0x8 + str h0,[x2,w3,sxtw] + str h0,[x2,w3,sxtw 1] + str h0,[x2,w3,uxtw] + str h0,[x2,w3,uxtw 1] + str h0,[x2,x3] + str h0,[x2,x3,lsl 1] + str h0,[x2,x3,sxtx] + str h0,[x2,x3,sxtx 1] + str s0,[x2,+0x8] + str s0,[expression.word] + str s0,[x2,+0x8]! + str s0,[expression.word]! + str s0,[x2],+0x8 + str s0,[x2,w3,sxtw] + str s0,[x2,w3,sxtw 2] + str s0,[x2,w3,uxtw] + str s0,[x2,w3,uxtw 2] + str s0,[x2,x3] + str s0,[x2,x3,lsl 2] + str s0,[x2,x3,sxtx] + str s0,[x2,x3,sxtx 2] + str d0,[x2,+0x8] + str d0,[expression.dword] + str d0,[x2,+0x8]! + str d0,[expression.dword]! + str d0,[x2],+0x8 + str d0,[x2,w3,sxtw] + str d0,[x2,w3,sxtw 3] + str d0,[x2,w3,uxtw] + str d0,[x2,w3,uxtw 3] + str d0,[x2,x3] + str d0,[x2,x3,lsl 3] + str d0,[x2,x3,sxtx] + str d0,[x2,x3,sxtx 3] + str q0,[x2,+0x8] + str q0,[expression.qword] + str q0,[x2,+0x8]! + str q0,[expression.qword]! + str q0,[x2],+0x8 + str q0,[x2,w3,sxtw] + str q0,[x2,w3,sxtw 4] + str q0,[x2,w3,uxtw] + str q0,[x2,w3,uxtw 4] + str q0,[x2,x3] + str q0,[x2,x3,lsl 4] + str q0,[x2,x3,sxtx] + str q0,[x2,x3,sxtx 4] + + stur b0,[x2] + stur b0,[x2,+0x8] + stur b0,[expression.byte] + stur h0,[x2] + stur h0,[x2,+0x8] + stur h0,[expression.hword] + stur s0,[x2] + stur s0,[x2,+0x8] + stur s0,[expression.word] + stur d0,[x2] + stur d0,[x2,+0x8] + stur d0,[expression.dword] + stur q0,[x2] + stur q0,[x2,+0x8] + stur q0,[expression.qword] + + sub d1,d2,d3 + sub v1.16b,v2.16b,v3.16b + sub v1.2d,v2.2d,v3.2d + sub v1.2s,v2.2s,v3.2s + sub v1.4h,v2.4h,v3.4h + sub v1.4s,v2.4s,v3.4s + sub v1.8b,v2.8b,v3.8b + sub v1.8h,v2.8h,v3.8h + + subhn v1.2s,v2.2d,v3.2d + subhn v1.4h,v2.4s,v3.4s + subhn v1.8b,v2.8h,v3.8h + + subhn2 v1.16b,v2.8h,v3.8h + subhn2 v1.4s,v2.2d,v3.2d + subhn2 v1.8h,v2.4s,v3.4s + + suqadd b1,b2 + suqadd d1,d2 + suqadd h1,h2 + suqadd s1,s2 + suqadd v1.16b,v2.16b + suqadd v1.2d,v2.2d + suqadd v1.2s,v2.2s + suqadd v1.4h,v2.4h + suqadd v1.4s,v2.4s + suqadd v1.8b,v2.8b + suqadd v1.8h,v2.8h + + sxtl v1.2d,v2.2s + sxtl v1.4s,v2.4h + sxtl v1.8h,v2.8b + + sxtl2 v1.2d,v2.4s + sxtl2 v1.4s,v2.8h + sxtl2 v1.8h,v2.16b + + tbl v1.8b,{v2.16b},v6.8b + tbl v1.8b,{v2.16b,v3.16b},v6.8b + tbl v1.8b,{v2.16b,v3.16b,v4.16b},v6.8b + tbl v1.8b,{v2.16b,v3.16b,v4.16b,v5.16b},v6.8b + + tbx v1.8b,{v2.16b},v6.8b + tbx v1.8b,{v2.16b,v3.16b},v6.8b + tbx v1.8b,{v2.16b,v3.16b,v4.16b},v6.8b + tbx v1.8b,{v2.16b,v3.16b,v4.16b,v5.16b},v6.8b + + trn1 v1.16b,v2.16b,v3.16b + trn1 v1.2d,v2.2d,v3.2d + trn1 v1.2s,v2.2s,v3.2s + trn1 v1.4h,v2.4h,v3.4h + trn1 v1.4s,v2.4s,v3.4s + trn1 v1.8b,v2.8b,v3.8b + trn1 v1.8h,v2.8h,v3.8h + + trn2 v1.16b,v2.16b,v3.16b + trn2 v1.2d,v2.2d,v3.2d + trn2 v1.2s,v2.2s,v3.2s + trn2 v1.4h,v2.4h,v3.4h + trn2 v1.4s,v2.4s,v3.4s + trn2 v1.8b,v2.8b,v3.8b + trn2 v1.8h,v2.8h,v3.8h + + uaba v1.16b,v2.16b,v3.16b + uaba v1.2s,v2.2s,v3.2s + uaba v1.4h,v2.4h,v3.4h + uaba v1.4s,v2.4s,v3.4s + uaba v1.8b,v2.8b,v3.8b + uaba v1.8h,v2.8h,v3.8h + + uabal v1.2d,v2.2s,v3.2s + uabal v1.4s,v2.4h,v3.4h + uabal v1.8h,v2.8b,v3.8b + + uabal2 v1.2d,v2.4s,v3.4s + uabal2 v1.4s,v2.8h,v3.8h + uabal2 v1.8h,v2.16b,v3.16b + + uabd v1.16b,v2.16b,v3.16b + uabd v1.2s,v2.2s,v3.2s + uabd v1.4h,v2.4h,v3.4h + uabd v1.4s,v2.4s,v3.4s + uabd v1.8b,v2.8b,v3.8b + uabd v1.8h,v2.8h,v3.8h + + uabdl v1.2d,v2.2s,v3.2s + uabdl v1.4s,v2.4h,v3.4h + uabdl v1.8h,v2.8b,v3.8b + + uabdl2 v1.2d,v2.4s,v3.4s + uabdl2 v1.4s,v2.8h,v3.8h + uabdl2 v1.8h,v2.16b,v3.16b + + uadalp v1.1d,v2.2s + uadalp v1.2d,v2.4s + uadalp v1.2s,v2.4h + uadalp v1.4h,v2.8b + uadalp v1.4s,v2.8h + uadalp v1.8h,v2.16b + + uaddl v1.2d,v2.2s,v3.2s + uaddl v1.4s,v2.4h,v3.4h + uaddl v1.8h,v2.8b,v3.8b + + uaddl2 v1.2d,v2.4s,v3.4s + uaddl2 v1.4s,v2.8h,v3.8h + uaddl2 v1.8h,v2.16b,v3.16b + + uaddlp v1.1d,v2.2s + uaddlp v1.2d,v2.4s + uaddlp v1.2s,v2.4h + uaddlp v1.4h,v2.8b + uaddlp v1.4s,v2.8h + uaddlp v1.8h,v2.16b + + uaddlv d1,v2.4s + uaddlv h1,v2.16b + uaddlv h1,v2.8b + uaddlv s1,v2.4h + uaddlv s1,v2.8h + + uaddw v1.2d,v2.2d,v3.2s + uaddw v1.4s,v2.4s,v3.4h + uaddw v1.8h,v2.8h,v3.8b + + uaddw2 v1.2d,v2.2d,v3.4s + uaddw2 v1.4s,v2.4s,v3.8h + uaddw2 v1.8h,v2.8h,v3.16b + + uhadd v1.16b,v2.16b,v3.16b + uhadd v1.2s,v2.2s,v3.2s + uhadd v1.4h,v2.4h,v3.4h + uhadd v1.4s,v2.4s,v3.4s + uhadd v1.8b,v2.8b,v3.8b + uhadd v1.8h,v2.8h,v3.8h + + uhsub v1.16b,v2.16b,v3.16b + uhsub v1.2s,v2.2s,v3.2s + uhsub v1.4h,v2.4h,v3.4h + uhsub v1.4s,v2.4s,v3.4s + uhsub v1.8b,v2.8b,v3.8b + uhsub v1.8h,v2.8h,v3.8h + + umax v1.16b,v2.16b,v3.16b + umax v1.2s,v2.2s,v3.2s + umax v1.4h,v2.4h,v3.4h + umax v1.4s,v2.4s,v3.4s + umax v1.8b,v2.8b,v3.8b + umax v1.8h,v2.8h,v3.8h + + umaxp v1.16b,v2.16b,v3.16b + umaxp v1.2s,v2.2s,v3.2s + umaxp v1.4h,v2.4h,v3.4h + umaxp v1.4s,v2.4s,v3.4s + umaxp v1.8b,v2.8b,v3.8b + umaxp v1.8h,v2.8h,v3.8h + + umaxv b1,v2.16b + umaxv b1,v2.8b + umaxv h1,v2.4h + umaxv h1,v2.8h + umaxv s1,v2.4s + + umin v1.16b,v2.16b,v3.16b + umin v1.2s,v2.2s,v3.2s + umin v1.4h,v2.4h,v3.4h + umin v1.4s,v2.4s,v3.4s + umin v1.8b,v2.8b,v3.8b + umin v1.8h,v2.8h,v3.8h + + uminp v1.16b,v2.16b,v3.16b + uminp v1.2s,v2.2s,v3.2s + uminp v1.4h,v2.4h,v3.4h + uminp v1.4s,v2.4s,v3.4s + uminp v1.8b,v2.8b,v3.8b + uminp v1.8h,v2.8h,v3.8h + + uminv b1,v2.16b + uminv b1,v2.8b + uminv h1,v2.4h + uminv h1,v2.8h + uminv s1,v2.4s + + umlal v1.2d,v2.2s,v3.2s + umlal v1.2d,v2.2s,v31.s[3] + umlal v1.4s,v2.4h,v15.h[7] + umlal v1.4s,v2.4h,v3.4h + umlal v1.8h,v2.8b,v3.8b + + umlal2 v1.2d,v2.4s,v3.4s + umlal2 v1.2d,v2.4s,v31.s[3] + umlal2 v1.4s,v2.8h,v15.h[7] + umlal2 v1.4s,v2.8h,v3.8h + umlal2 v1.8h,v2.16b,v3.16b + + umlsl v1.2d,v2.2s,v3.2s + umlsl v1.2d,v2.2s,v31.s[3] + umlsl v1.4s,v2.4h,v15.h[7] + umlsl v1.4s,v2.4h,v3.4h + umlsl v1.8h,v2.8b,v3.8b + + umlsl2 v1.2d,v2.4s,v3.4s + umlsl2 v1.2d,v2.4s,v31.s[3] + umlsl2 v1.4s,v2.8h,v15.h[7] + umlsl2 v1.4s,v2.8h,v3.8h + umlsl2 v1.8h,v2.16b,v3.16b + + umov w1,v2.b[15] + umov w1,v2.h[4] + umov w1,v2.s[2] + umov x1,v2.d[1] + + umull v1.2d,v2.2s,v3.2s + umull v1.2d,v2.2s,v3.s[0] + umull v1.2d,v2.2s,v3.s[2] + umull v1.4s,v2.4h,v3.4h + umull v1.4s,v2.4h,v3.h[0] + umull v1.4s,v2.4h,v3.h[4] + umull v1.8h,v2.8b,v3.8b + + umull2 v1.2d,v2.4s,v3.4s + umull2 v1.2d,v2.4s,v31.s[3] + umull2 v1.4s,v2.8h,v15.h[7] + umull2 v1.4s,v2.8h,v3.8h + umull2 v1.8h,v2.16b,v3.16b + + uqadd b1,b2,b3 + uqadd d1,d2,d3 + uqadd h1,h2,h3 + uqadd s1,s2,s3 + uqadd v1.16b,v2.16b,v3.16b + uqadd v1.2d,v2.2d,v3.2d + uqadd v1.2s,v2.2s,v3.2s + uqadd v1.4h,v2.4h,v3.4h + uqadd v1.4s,v2.4s,v3.4s + uqadd v1.8b,v2.8b,v3.8b + uqadd v1.8h,v2.8h,v3.8h + + uqrshl b1,b2,b3 + uqrshl d1,d2,d3 + uqrshl h1,h2,h3 + uqrshl s1,s2,s3 + uqrshl v1.16b,v2.16b,v3.16b + uqrshl v1.2d,v2.2d,v3.2d + uqrshl v1.2s,v2.2s,v3.2s + uqrshl v1.4h,v2.4h,v3.4h + uqrshl v1.4s,v2.4s,v3.4s + uqrshl v1.8b,v2.8b,v3.8b + uqrshl v1.8h,v2.8h,v3.8h + + uqrshrn b8,h8,1 + uqrshrn h4,s4,2 + uqrshrn s2,d2,3 + uqrshrn v1.2s,v2.2d,3 + uqrshrn v1.4h,v2.4s,2 + uqrshrn v1.8b,v2.8h,1 + + uqrshrn2 v1.16b,v2.8h,1 + uqrshrn2 v1.4s,v2.2d,3 + uqrshrn2 v1.8h,v2.4s,2 + + uqshl b1,b2,7 + uqshl b1,b2,b3 + uqshl d1,d2,63 + uqshl d1,d2,d3 + uqshl h1,h2,15 + uqshl h1,h2,h3 + uqshl s1,s2,31 + uqshl s1,s2,s3 + uqshl v1.16b,v2.16b,7 + uqshl v1.16b,v2.16b,v3.16b + uqshl v1.2d,v2.2d,63 + uqshl v1.2d,v2.2d,v3.2d + uqshl v1.2s,v2.2s,1 + uqshl v1.2s,v2.2s,v3.2s + uqshl v1.4h,v2.4h,1 + uqshl v1.4h,v2.4h,v3.4h + uqshl v1.4s,v2.4s,31 + uqshl v1.4s,v2.4s,v3.4s + uqshl v1.8b,v2.8b,1 + uqshl v1.8b,v2.8b,v3.8b + uqshl v1.8h,v2.8h,15 + uqshl v1.8h,v2.8h,v3.8h + + uqshrn b8,h8,1 + uqshrn h4,s4,2 + uqshrn s2,d2,3 + uqshrn v1.2s,v2.2d,3 + uqshrn v1.4h,v2.4s,2 + uqshrn v1.8b,v2.8h,1 + + uqshrn2 v1.16b,v2.8h,1 + uqshrn2 v1.4s,v2.2d,3 + uqshrn2 v1.8h,v2.4s,2 + + uqsub b1,b2,b3 + uqsub d1,d2,d3 + uqsub h1,h2,h3 + uqsub s1,s2,s3 + uqsub v1.16b,v2.16b,v3.16b + uqsub v1.2d,v2.2d,v3.2d + uqsub v1.2s,v2.2s,v3.2s + uqsub v1.4h,v2.4h,v3.4h + uqsub v1.4s,v2.4s,v3.4s + uqsub v1.8b,v2.8b,v3.8b + uqsub v1.8h,v2.8h,v3.8h + + uqxtn b8,h8 + uqxtn h4,s4 + uqxtn s2,d2 + uqxtn v1.2s,v2.2d + uqxtn v1.4h,v2.4s + uqxtn v1.8b,v2.8h + + uqxtn2 v1.16b,v2.8h + uqxtn2 v1.4s,v2.2d + uqxtn2 v1.8h,v2.4s + + urhadd v1.16b,v2.16b,v3.16b + urhadd v1.2s,v2.2s,v3.2s + urhadd v1.4h,v2.4h,v3.4h + urhadd v1.4s,v2.4s,v3.4s + urhadd v1.8b,v2.8b,v3.8b + urhadd v1.8h,v2.8h,v3.8h + + urshl d1,d2,d3 + urshl v1.16b,v2.16b,v3.16b + urshl v1.2d,v2.2d,v3.2d + urshl v1.2s,v2.2s,v3.2s + urshl v1.4h,v2.4h,v3.4h + urshl v1.4s,v2.4s,v3.4s + urshl v1.8b,v2.8b,v3.8b + urshl v1.8h,v2.8h,v3.8h + + urshr d1,d2,1 + urshr v1.16b,v2.16b,8 + urshr v1.2d,v2.2d,64 + urshr v1.2s,v2.2s,1 + urshr v1.4h,v2.4h,1 + urshr v1.4s,v2.4s,32 + urshr v1.8b,v2.8b,1 + urshr v1.8h,v2.8h,16 + + ursra d1,d2,1 + ursra v1.16b,v2.16b,8 + ursra v1.2d,v2.2d,64 + ursra v1.2s,v2.2s,1 + ursra v1.4h,v2.4h,1 + ursra v1.4s,v2.4s,32 + ursra v1.8b,v2.8b,1 + ursra v1.8h,v2.8h,16 + + ushl d1,d2,d3 + ushl v1.16b,v2.16b,v3.16b + ushl v1.2d,v2.2d,v3.2d + ushl v1.2s,v2.2s,v3.2s + ushl v1.4h,v2.4h,v3.4h + ushl v1.4s,v2.4s,v3.4s + ushl v1.8b,v2.8b,v3.8b + ushl v1.8h,v2.8h,v3.8h + + ushll v1.2d,v2.2s,3 + ushll v1.4s,v2.4h,2 + ushll v1.8h,v2.8b,1 + + ushll2 v1.2d,v2.4s,31 + ushll2 v1.4s,v2.8h,15 + ushll2 v1.8h,v2.16b,7 + + ushr d1,d2,1 + ushr v1.16b,v2.16b,8 + ushr v1.2d,v2.2d,64 + ushr v1.2s,v2.2s,1 + ushr v1.4h,v2.4h,1 + ushr v1.4s,v2.4s,32 + ushr v1.8b,v2.8b,1 + ushr v1.8h,v2.8h,16 + + usqadd b1,b2 + usqadd d1,d2 + usqadd h1,h2 + usqadd s1,s2 + usqadd v1.16b,v2.16b + usqadd v1.2d,v2.2d + usqadd v1.2s,v2.2s + usqadd v1.4h,v2.4h + usqadd v1.4s,v2.4s + usqadd v1.8b,v2.8b + usqadd v1.8h,v2.8h + + usra d1,d2,1 + usra v1.16b,v2.16b,8 + usra v1.2d,v2.2d,64 + usra v1.2s,v2.2s,1 + usra v1.4h,v2.4h,1 + usra v1.4s,v2.4s,32 + usra v1.8b,v2.8b,1 + usra v1.8h,v2.8h,16 + + usubl v1.2d,v2.2s,v3.2s + usubl v1.4s,v2.4h,v3.4h + usubl v1.8h,v2.8b,v3.8b + + usubl2 v1.2d,v2.4s,v3.4s + usubl2 v1.4s,v2.8h,v3.8h + usubl2 v1.8h,v2.16b,v3.16b + + usubw v1.2d,v2.2d,v3.2s + usubw v1.4s,v2.4s,v3.4h + usubw v1.8h,v2.8h,v3.8b + + usubw2 v1.2d,v2.2d,v3.4s + usubw2 v1.4s,v2.4s,v3.8h + usubw2 v1.8h,v2.8h,v3.16b + + uxtl v1.2d,v2.2s + uxtl v1.4s,v2.4h + uxtl v1.8h,v2.8b + + uxtl2 v1.2d,v2.4s + uxtl2 v1.4s,v2.8h + uxtl2 v1.8h,v2.16b + + uzp1 v1.16b,v2.16b,v3.16b + uzp1 v1.2d,v2.2d,v3.2d + uzp1 v1.2s,v2.2s,v3.2s + uzp1 v1.4h,v2.4h,v3.4h + uzp1 v1.4s,v2.4s,v3.4s + uzp1 v1.8b,v2.8b,v3.8b + uzp1 v1.8h,v2.8h,v3.8h + + uzp2 v1.16b,v2.16b,v3.16b + uzp2 v1.2d,v2.2d,v3.2d + uzp2 v1.2s,v2.2s,v3.2s + uzp2 v1.4h,v2.4h,v3.4h + uzp2 v1.4s,v2.4s,v3.4s + uzp2 v1.8b,v2.8b,v3.8b + uzp2 v1.8h,v2.8h,v3.8h + + xtn v1.8b,v2.8h + xtn v1.4h,v2.4s + xtn v1.2s,v2.2d + + xtn2 v1.16b,v2.8h + xtn2 v1.8h,v2.4s + xtn2 v1.4s,v2.2d + + zip1 v1.16b,v2.16b,v3.16b + zip1 v1.2d,v2.2d,v3.2d + zip1 v1.2s,v2.2s,v3.2s + zip1 v1.4h,v2.4h,v3.4h + zip1 v1.4s,v2.4s,v3.4s + zip1 v1.8b,v2.8b,v3.8b + zip1 v1.8h,v2.8h,v3.8h + + zip2 v1.16b,v2.16b,v3.16b + zip2 v1.2d,v2.2d,v3.2d + zip2 v1.2s,v2.2s,v3.2s + zip2 v1.4h,v2.4h,v3.4h + zip2 v1.4s,v2.4s,v3.4s + zip2 v1.8b,v2.8b,v3.8b + zip2 v1.8h,v2.8h,v3.8h + +processor CPU64_CRC + + crc32b w1,w2,w3 + + crc32cb w1,w2,w3 + + crc32ch w1,w2,w3 + + crc32cw w1,w2,w3 + + crc32cx w1,w2,x3 + + crc32h w1,w2,w3 + + crc32w w1,w2,w3 + + crc32x w1,w2,x3 + +processor CPU64_CRYPTO + + aesd v1.16b,v2.16b + + aese v1.16b,v2.16b + + aesimc v1.16b,v2.16b + + aesmc v1.16b,v2.16b + + pmull v1.1q,v2.1d,v3.1d + + pmull2 v1.1q,v2.2d,v3.2d + + sha1c q1,s2,v3.4s + + sha1h s1,s2 + + sha1m q1,s2,v3.4s + + sha1p q1,s2,v3.4s + + sha1su0 v1.4s,v2.4s,v3.4s + + sha1su1 v1.4s,v2.4s + + sha256h q1,q2,v3.4s + + sha256h2 q1,q2,v3.4s + + sha256su0 v1.4s,v2.4s + + sha256su1 v1.4s,v2.4s,v3.4s + diff --git a/armdoc/InstructionFormatsFPA.asm b/armdoc/InstructionFormatsFPA.asm new file mode 100644 index 0000000..e2df76c --- /dev/null +++ b/armdoc/InstructionFormatsFPA.asm @@ -0,0 +1,1271 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;To avoid unnecessary repetition only ARM mode is used +;here. There is no change needed for THUMB mode except +;to specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;All instructions can be conditional. The condition code +;should be added at the end of the main opcode and +;before any size/type specifiers. For example: "addhi" +;and "vaddhi.i16". The syntax also supports the pre-UAL +;style of putting the condition before any modifiers +;like "s" or "fd". For example: "ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;FPA, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_FPA_V1 + absd f0,1.0 + absd f0,f1 + + absdm f0,1.0 + absdm f0,f1 + + absdp f0,1.0 + absdp f0,f1 + + absdz f0,1.0 + absdz f0,f1 + + abse f0,1.0 + abse f0,f1 + + absem f0,1.0 + absem f0,f1 + + absep f0,1.0 + absep f0,f1 + + absez f0,1.0 + absez f0,f1 + + abss f0,1.0 + abss f0,f1 + + abssm f0,1.0 + abssm f0,f1 + + abssp f0,1.0 + abssp f0,f1 + + abssz f0,1.0 + abssz f0,f1 + + acsd f0,1.0 + acsd f0,f1 + + acsdm f0,1.0 + acsdm f0,f1 + + acsdp f0,1.0 + acsdp f0,f1 + + acsdz f0,1.0 + acsdz f0,f1 + + acse f0,1.0 + acse f0,f1 + + acsem f0,1.0 + acsem f0,f1 + + acsep f0,1.0 + acsep f0,f1 + + acsez f0,1.0 + acsez f0,f1 + + acss f0,1.0 + acss f0,f1 + + acssm f0,1.0 + acssm f0,f1 + + acssp f0,1.0 + acssp f0,f1 + + acssz f0,1.0 + acssz f0,f1 + + adfd f0,f1,2.0 + adfd f0,f1,f2 + + adfdm f0,f1,2.0 + adfdm f0,f1,f2 + + adfdp f0,f1,2.0 + adfdp f0,f1,f2 + + adfdz f0,f1,2.0 + adfdz f0,f1,f2 + + adfe f0,f1,2.0 + adfe f0,f1,f2 + + adfem f0,f1,2.0 + adfem f0,f1,f2 + + adfep f0,f1,2.0 + adfep f0,f1,f2 + + adfez f0,f1,2.0 + adfez f0,f1,f2 + + adfs f0,f1,2.0 + adfs f0,f1,f2 + + adfsm f0,f1,2.0 + adfsm f0,f1,f2 + + adfsp f0,f1,2.0 + adfsp f0,f1,f2 + + adfsz f0,f1,2.0 + adfsz f0,f1,f2 + + asnd f0,1.0 + asnd f0,f1 + + asndm f0,1.0 + asndm f0,f1 + + asndp f0,1.0 + asndp f0,f1 + + asndz f0,1.0 + asndz f0,f1 + + asne f0,1.0 + asne f0,f1 + + asnem f0,1.0 + asnem f0,f1 + + asnep f0,1.0 + asnep f0,f1 + + asnez f0,1.0 + asnez f0,f1 + + asns f0,1.0 + asns f0,f1 + + asnsm f0,1.0 + asnsm f0,f1 + + asnsp f0,1.0 + asnsp f0,f1 + + asnsz f0,1.0 + asnsz f0,f1 + + atnd f0,1.0 + atnd f0,f1 + + atndm f0,1.0 + atndm f0,f1 + + atndp f0,1.0 + atndp f0,f1 + + atndz f0,1.0 + atndz f0,f1 + + atne f0,1.0 + atne f0,f1 + + atnem f0,1.0 + atnem f0,f1 + + atnep f0,1.0 + atnep f0,f1 + + atnez f0,1.0 + atnez f0,f1 + + atns f0,1.0 + atns f0,f1 + + atnsm f0,1.0 + atnsm f0,f1 + + atnsp f0,1.0 + atnsp f0,f1 + + atnsz f0,1.0 + atnsz f0,f1 + + cmf f0,1.0 + cmf f0,f1 + + cmfe f0,1.0 + cmfe f0,f1 + + cnf f0,1.0 + cnf f0,f1 + + cnfe f0,1.0 + cnfe f0,f1 + + cosd f0,1.0 + cosd f0,f1 + + cosdm f0,1.0 + cosdm f0,f1 + + cosdp f0,1.0 + cosdp f0,f1 + + cosdz f0,1.0 + cosdz f0,f1 + + cose f0,1.0 + cose f0,f1 + + cosem f0,1.0 + cosem f0,f1 + + cosep f0,1.0 + cosep f0,f1 + + cosez f0,1.0 + cosez f0,f1 + + coss f0,1.0 + coss f0,f1 + + cossm f0,1.0 + cossm f0,f1 + + cossp f0,1.0 + cossp f0,f1 + + cossz f0,1.0 + cossz f0,f1 + + dvfd f0,f1,2.0 + dvfd f0,f1,f2 + + dvfdm f0,f1,2.0 + dvfdm f0,f1,f2 + + dvfdp f0,f1,2.0 + dvfdp f0,f1,f2 + + dvfdz f0,f1,2.0 + dvfdz f0,f1,f2 + + dvfe f0,f1,2.0 + dvfe f0,f1,f2 + + dvfem f0,f1,2.0 + dvfem f0,f1,f2 + + dvfep f0,f1,2.0 + dvfep f0,f1,f2 + + dvfez f0,f1,2.0 + dvfez f0,f1,f2 + + dvfs f0,f1,2.0 + dvfs f0,f1,f2 + + dvfsm f0,f1,2.0 + dvfsm f0,f1,f2 + + dvfsp f0,f1,2.0 + dvfsp f0,f1,f2 + + dvfsz f0,f1,2.0 + dvfsz f0,f1,f2 + + expd f0,1.0 + expd f0,f1 + + expdm f0,1.0 + expdm f0,f1 + + expdp f0,1.0 + expdp f0,f1 + + expdz f0,1.0 + expdz f0,f1 + + expe f0,1.0 + expe f0,f1 + + expem f0,1.0 + expem f0,f1 + + expep f0,1.0 + expep f0,f1 + + expez f0,1.0 + expez f0,f1 + + exps f0,1.0 + exps f0,f1 + + expsm f0,1.0 + expsm f0,f1 + + expsp f0,1.0 + expsp f0,f1 + + expsz f0,1.0 + expsz f0,f1 + + fdvd f0,f1,2.0 + fdvd f0,f1,f2 + + fdvdm f0,f1,2.0 + fdvdm f0,f1,f2 + + fdvdp f0,f1,2.0 + fdvdp f0,f1,f2 + + fdvdz f0,f1,2.0 + fdvdz f0,f1,f2 + + fdve f0,f1,2.0 + fdve f0,f1,f2 + + fdvem f0,f1,2.0 + fdvem f0,f1,f2 + + fdvep f0,f1,2.0 + fdvep f0,f1,f2 + + fdvez f0,f1,2.0 + fdvez f0,f1,f2 + + fdvs f0,f1,2.0 + fdvs f0,f1,f2 + + fdvsm f0,f1,2.0 + fdvsm f0,f1,f2 + + fdvsp f0,f1,2.0 + fdvsp f0,f1,f2 + + fdvsz f0,f1,2.0 + fdvsz f0,f1,f2 + + fix r0,f1 + + fixm r0,f1 + + fixp r0,f1 + + fixz r0,f1 + + fltd f0,r1 + + fltdm f0,r1 + + fltdp f0,r1 + + fltdz f0,r1 + + flte f0,r1 + + fltem f0,r1 + + fltep f0,r1 + + fltez f0,r1 + + flts f0,r1 + + fltsm f0,r1 + + fltsp f0,r1 + + fltsz f0,r1 + + fmld f0,f1,2.0 + fmld f0,f1,f2 + + fmldm f0,f1,2.0 + fmldm f0,f1,f2 + + fmldp f0,f1,2.0 + fmldp f0,f1,f2 + + fmldz f0,f1,2.0 + fmldz f0,f1,f2 + + fmle f0,f1,2.0 + fmle f0,f1,f2 + + fmlem f0,f1,2.0 + fmlem f0,f1,f2 + + fmlep f0,f1,2.0 + fmlep f0,f1,f2 + + fmlez f0,f1,2.0 + fmlez f0,f1,f2 + + fmls f0,f1,2.0 + fmls f0,f1,f2 + + fmlsm f0,f1,2.0 + fmlsm f0,f1,f2 + + fmlsp f0,f1,2.0 + fmlsp f0,f1,f2 + + fmlsz f0,f1,2.0 + fmlsz f0,f1,f2 + + frdd f0,f1,2.0 + frdd f0,f1,f2 + + frddm f0,f1,2.0 + frddm f0,f1,f2 + + frddp f0,f1,2.0 + frddp f0,f1,f2 + + frddz f0,f1,2.0 + frddz f0,f1,f2 + + frde f0,f1,2.0 + frde f0,f1,f2 + + frdem f0,f1,2.0 + frdem f0,f1,f2 + + frdep f0,f1,2.0 + frdep f0,f1,f2 + + frdez f0,f1,2.0 + frdez f0,f1,f2 + + frds f0,f1,2.0 + frds f0,f1,f2 + + frdsm f0,f1,2.0 + frdsm f0,f1,f2 + + frdsp f0,f1,2.0 + frdsp f0,f1,f2 + + frdsz f0,f1,2.0 + frdsz f0,f1,f2 + + label_ldfd: + ldfd f0,[r1] + ldfd f0,[r1],4 + ldfd f0,[r1],{2} + ldfd f0,[r1,4] + ldfd f0,[r1,4]! + ldfd f0,[label_ldfd] + ldfd f0,[expression.word] + ldfd f0,[expression.word]! + + label_ldfe: + ldfe f0,[r1] + ldfe f0,[r1],4 + ldfe f0,[r1],{2} + ldfe f0,[r1,4] + ldfe f0,[r1,4]! + ldfe f0,[label_ldfe] + ldfe f0,[expression.word] + ldfe f0,[expression.word]! + + label_ldfp: + ldfp f0,[r1] + ldfp f0,[r1],4 + ldfp f0,[r1],{2} + ldfp f0,[r1,4] + ldfp f0,[r1,4]! + ldfp f0,[label_ldfp] + ldfp f0,[expression.word] + ldfp f0,[expression.word]! + + label_ldfs: + ldfs f0,[r1] + ldfs f0,[r1],4 + ldfs f0,[r1],{2} + ldfs f0,[r1,4] + ldfs f0,[r1,4]! + ldfs f0,[label_ldfs] + ldfs f0,[expression.word] + ldfs f0,[expression.word]! + + lgnd f0,1.0 + lgnd f0,f1 + + lgndm f0,1.0 + lgndm f0,f1 + + lgndp f0,1.0 + lgndp f0,f1 + + lgndz f0,1.0 + lgndz f0,f1 + + lgne f0,1.0 + lgne f0,f1 + + lgnem f0,1.0 + lgnem f0,f1 + + lgnep f0,1.0 + lgnep f0,f1 + + lgnez f0,1.0 + lgnez f0,f1 + + lgns f0,1.0 + lgns f0,f1 + + lgnsm f0,1.0 + lgnsm f0,f1 + + lgnsp f0,1.0 + lgnsp f0,f1 + + lgnsz f0,1.0 + lgnsz f0,f1 + + logd f0,1.0 + logd f0,f1 + + logdm f0,1.0 + logdm f0,f1 + + logdp f0,1.0 + logdp f0,f1 + + logdz f0,1.0 + logdz f0,f1 + + loge f0,1.0 + loge f0,f1 + + logem f0,1.0 + logem f0,f1 + + logep f0,1.0 + logep f0,f1 + + logez f0,1.0 + logez f0,f1 + + logs f0,1.0 + logs f0,f1 + + logsm f0,1.0 + logsm f0,f1 + + logsp f0,1.0 + logsp f0,f1 + + logsz f0,1.0 + logsz f0,f1 + + mnfd f0,1.0 + mnfd f0,f1 + + mnfdm f0,1.0 + mnfdm f0,f1 + + mnfdp f0,1.0 + mnfdp f0,f1 + + mnfdz f0,1.0 + mnfdz f0,f1 + + mnfe f0,1.0 + mnfe f0,f1 + + mnfem f0,1.0 + mnfem f0,f1 + + mnfep f0,1.0 + mnfep f0,f1 + + mnfez f0,1.0 + mnfez f0,f1 + + mnfs f0,1.0 + mnfs f0,f1 + + mnfsm f0,1.0 + mnfsm f0,f1 + + mnfsp f0,1.0 + mnfsp f0,f1 + + mnfsz f0,1.0 + mnfsz f0,f1 + + mufd f0,f1,2.0 + mufd f0,f1,f2 + + mufdm f0,f1,2.0 + mufdm f0,f1,f2 + + mufdp f0,f1,2.0 + mufdp f0,f1,f2 + + mufdz f0,f1,2.0 + mufdz f0,f1,f2 + + mufe f0,f1,2.0 + mufe f0,f1,f2 + + mufem f0,f1,2.0 + mufem f0,f1,f2 + + mufep f0,f1,2.0 + mufep f0,f1,f2 + + mufez f0,f1,2.0 + mufez f0,f1,f2 + + mufs f0,f1,2.0 + mufs f0,f1,f2 + + mufsm f0,f1,2.0 + mufsm f0,f1,f2 + + mufsp f0,f1,2.0 + mufsp f0,f1,f2 + + mufsz f0,f1,2.0 + mufsz f0,f1,f2 + + mvfd f0,1.0 + mvfd f0,f1 + + mvfdm f0,1.0 + mvfdm f0,f1 + + mvfdp f0,1.0 + mvfdp f0,f1 + + mvfdz f0,1.0 + mvfdz f0,f1 + + mvfe f0,1.0 + mvfe f0,f1 + + mvfem f0,1.0 + mvfem f0,f1 + + mvfep f0,1.0 + mvfep f0,f1 + + mvfez f0,1.0 + mvfez f0,f1 + + mvfs f0,1.0 + mvfs f0,f1 + + mvfsm f0,1.0 + mvfsm f0,f1 + + mvfsp f0,1.0 + mvfsp f0,f1 + + mvfsz f0,1.0 + mvfsz f0,f1 + + nrmd f0,1.0 + nrmd f0,f1 + + nrmdm f0,1.0 + nrmdm f0,f1 + + nrmdp f0,1.0 + nrmdp f0,f1 + + nrmdz f0,1.0 + nrmdz f0,f1 + + nrme f0,1.0 + nrme f0,f1 + + nrmem f0,1.0 + nrmem f0,f1 + + nrmep f0,1.0 + nrmep f0,f1 + + nrmez f0,1.0 + nrmez f0,f1 + + nrms f0,1.0 + nrms f0,f1 + + nrmsm f0,1.0 + nrmsm f0,f1 + + nrmsp f0,1.0 + nrmsp f0,f1 + + nrmsz f0,1.0 + nrmsz f0,f1 + + pold f0,f1,2.0 + pold f0,f1,f2 + + poldm f0,f1,2.0 + poldm f0,f1,f2 + + poldp f0,f1,2.0 + poldp f0,f1,f2 + + poldz f0,f1,2.0 + poldz f0,f1,f2 + + pole f0,f1,2.0 + pole f0,f1,f2 + + polem f0,f1,2.0 + polem f0,f1,f2 + + polep f0,f1,2.0 + polep f0,f1,f2 + + polez f0,f1,2.0 + polez f0,f1,f2 + + pols f0,f1,2.0 + pols f0,f1,f2 + + polsm f0,f1,2.0 + polsm f0,f1,f2 + + polsp f0,f1,2.0 + polsp f0,f1,f2 + + polsz f0,f1,2.0 + polsz f0,f1,f2 + + powd f0,f1,2.0 + powd f0,f1,f2 + + powdm f0,f1,2.0 + powdm f0,f1,f2 + + powdp f0,f1,2.0 + powdp f0,f1,f2 + + powdz f0,f1,2.0 + powdz f0,f1,f2 + + powe f0,f1,2.0 + powe f0,f1,f2 + + powem f0,f1,2.0 + powem f0,f1,f2 + + powep f0,f1,2.0 + powep f0,f1,f2 + + powez f0,f1,2.0 + powez f0,f1,f2 + + pows f0,f1,2.0 + pows f0,f1,f2 + + powsm f0,f1,2.0 + powsm f0,f1,f2 + + powsp f0,f1,2.0 + powsp f0,f1,f2 + + powsz f0,f1,2.0 + powsz f0,f1,f2 + + rdfd f0,f1,2.0 + rdfd f0,f1,f2 + + rdfdm f0,f1,2.0 + rdfdm f0,f1,f2 + + rdfdp f0,f1,2.0 + rdfdp f0,f1,f2 + + rdfdz f0,f1,2.0 + rdfdz f0,f1,f2 + + rdfe f0,f1,2.0 + rdfe f0,f1,f2 + + rdfem f0,f1,2.0 + rdfem f0,f1,f2 + + rdfep f0,f1,2.0 + rdfep f0,f1,f2 + + rdfez f0,f1,2.0 + rdfez f0,f1,f2 + + rdfs f0,f1,2.0 + rdfs f0,f1,f2 + + rdfsm f0,f1,2.0 + rdfsm f0,f1,f2 + + rdfsp f0,f1,2.0 + rdfsp f0,f1,f2 + + rdfsz f0,f1,2.0 + rdfsz f0,f1,f2 + + rfc r0 + + rfs r0 + + rmfd f0,f1,2.0 + rmfd f0,f1,f2 + + rmfdm f0,f1,2.0 + rmfdm f0,f1,f2 + + rmfdp f0,f1,2.0 + rmfdp f0,f1,f2 + + rmfdz f0,f1,2.0 + rmfdz f0,f1,f2 + + rmfe f0,f1,2.0 + rmfe f0,f1,f2 + + rmfem f0,f1,2.0 + rmfem f0,f1,f2 + + rmfep f0,f1,2.0 + rmfep f0,f1,f2 + + rmfez f0,f1,2.0 + rmfez f0,f1,f2 + + rmfs f0,f1,2.0 + rmfs f0,f1,f2 + + rmfsm f0,f1,2.0 + rmfsm f0,f1,f2 + + rmfsp f0,f1,2.0 + rmfsp f0,f1,f2 + + rmfsz f0,f1,2.0 + rmfsz f0,f1,f2 + + rndd f0,1.0 + rndd f0,f1 + + rnddm f0,1.0 + rnddm f0,f1 + + rnddp f0,1.0 + rnddp f0,f1 + + rnddz f0,1.0 + rnddz f0,f1 + + rnde f0,1.0 + rnde f0,f1 + + rndem f0,1.0 + rndem f0,f1 + + rndep f0,1.0 + rndep f0,f1 + + rndez f0,1.0 + rndez f0,f1 + + rnds f0,1.0 + rnds f0,f1 + + rndsm f0,1.0 + rndsm f0,f1 + + rndsp f0,1.0 + rndsp f0,f1 + + rndsz f0,1.0 + rndsz f0,f1 + + rpwd f0,f1,2.0 + rpwd f0,f1,f2 + + rpwdm f0,f1,2.0 + rpwdm f0,f1,f2 + + rpwdp f0,f1,2.0 + rpwdp f0,f1,f2 + + rpwdz f0,f1,2.0 + rpwdz f0,f1,f2 + + rpwe f0,f1,2.0 + rpwe f0,f1,f2 + + rpwem f0,f1,2.0 + rpwem f0,f1,f2 + + rpwep f0,f1,2.0 + rpwep f0,f1,f2 + + rpwez f0,f1,2.0 + rpwez f0,f1,f2 + + rpws f0,f1,2.0 + rpws f0,f1,f2 + + rpwsm f0,f1,2.0 + rpwsm f0,f1,f2 + + rpwsp f0,f1,2.0 + rpwsp f0,f1,f2 + + rpwsz f0,f1,2.0 + rpwsz f0,f1,f2 + + rsfd f0,f1,2.0 + rsfd f0,f1,f2 + + rsfdm f0,f1,2.0 + rsfdm f0,f1,f2 + + rsfdp f0,f1,2.0 + rsfdp f0,f1,f2 + + rsfdz f0,f1,2.0 + rsfdz f0,f1,f2 + + rsfe f0,f1,2.0 + rsfe f0,f1,f2 + + rsfem f0,f1,2.0 + rsfem f0,f1,f2 + + rsfep f0,f1,2.0 + rsfep f0,f1,f2 + + rsfez f0,f1,2.0 + rsfez f0,f1,f2 + + rsfs f0,f1,2.0 + rsfs f0,f1,f2 + + rsfsm f0,f1,2.0 + rsfsm f0,f1,f2 + + rsfsp f0,f1,2.0 + rsfsp f0,f1,f2 + + rsfsz f0,f1,2.0 + rsfsz f0,f1,f2 + + sind f0,1.0 + sind f0,f1 + + sindm f0,1.0 + sindm f0,f1 + + sindp f0,1.0 + sindp f0,f1 + + sindz f0,1.0 + sindz f0,f1 + + sine f0,1.0 + sine f0,f1 + + sinem f0,1.0 + sinem f0,f1 + + sinep f0,1.0 + sinep f0,f1 + + sinez f0,1.0 + sinez f0,f1 + + sins f0,1.0 + sins f0,f1 + + sinsm f0,1.0 + sinsm f0,f1 + + sinsp f0,1.0 + sinsp f0,f1 + + sinsz f0,1.0 + sinsz f0,f1 + + sqtd f0,1.0 + sqtd f0,f1 + + sqtdm f0,1.0 + sqtdm f0,f1 + + sqtdp f0,1.0 + sqtdp f0,f1 + + sqtdz f0,1.0 + sqtdz f0,f1 + + sqte f0,1.0 + sqte f0,f1 + + sqtem f0,1.0 + sqtem f0,f1 + + sqtep f0,1.0 + sqtep f0,f1 + + sqtez f0,1.0 + sqtez f0,f1 + + sqts f0,1.0 + sqts f0,f1 + + sqtsm f0,1.0 + sqtsm f0,f1 + + sqtsp f0,1.0 + sqtsp f0,f1 + + sqtsz f0,1.0 + sqtsz f0,f1 + + label_stfd: + stfd f0,[r1] + stfd f0,[r1],4 + stfd f0,[r1],{2} + stfd f0,[r1,4] + stfd f0,[r1,4]! + stfd f0,[label_stfd] + stfd f0,[expression.word] + stfd f0,[expression.word]! + + label_stfe: + stfe f0,[r1] + stfe f0,[r1],4 + stfe f0,[r1],{2} + stfe f0,[r1,4] + stfe f0,[r1,4]! + stfe f0,[label_stfe] + stfe f0,[expression.word] + stfe f0,[expression.word]! + + label_stfp: + stfp f0,[r1] + stfp f0,[r1],4 + stfp f0,[r1],{2} + stfp f0,[r1,4] + stfp f0,[r1,4]! + stfp f0,[label_stfp] + stfp f0,[expression.word] + stfp f0,[expression.word]! + + label_stfs: + stfs f0,[r1] + stfs f0,[r1],4 + stfs f0,[r1],{2} + stfs f0,[r1,4] + stfs f0,[r1,4]! + stfs f0,[label_stfs] + stfs f0,[expression.word] + stfs f0,[expression.word]! + + sufd f0,f1,2.0 + sufd f0,f1,f2 + + sufdm f0,f1,2.0 + sufdm f0,f1,f2 + + sufdp f0,f1,2.0 + sufdp f0,f1,f2 + + sufdz f0,f1,2.0 + sufdz f0,f1,f2 + + sufe f0,f1,2.0 + sufe f0,f1,f2 + + sufem f0,f1,2.0 + sufem f0,f1,f2 + + sufep f0,f1,2.0 + sufep f0,f1,f2 + + sufez f0,f1,2.0 + sufez f0,f1,f2 + + sufs f0,f1,2.0 + sufs f0,f1,f2 + + sufsm f0,f1,2.0 + sufsm f0,f1,f2 + + sufsp f0,f1,2.0 + sufsp f0,f1,f2 + + sufsz f0,f1,2.0 + sufsz f0,f1,f2 + + tand f0,1.0 + tand f0,f1 + + tandm f0,1.0 + tandm f0,f1 + + tandp f0,1.0 + tandp f0,f1 + + tandz f0,1.0 + tandz f0,f1 + + tane f0,1.0 + tane f0,f1 + + tanem f0,1.0 + tanem f0,f1 + + tanep f0,1.0 + tanep f0,f1 + + tanez f0,1.0 + tanez f0,f1 + + tans f0,1.0 + tans f0,f1 + + tansm f0,1.0 + tansm f0,f1 + + tansp f0,1.0 + tansp f0,f1 + + tansz f0,1.0 + tansz f0,f1 + + urdd f0,1.0 + urdd f0,f1 + + urddm f0,1.0 + urddm f0,f1 + + urddp f0,1.0 + urddp f0,f1 + + urddz f0,1.0 + urddz f0,f1 + + urde f0,1.0 + urde f0,f1 + + urdem f0,1.0 + urdem f0,f1 + + urdep f0,1.0 + urdep f0,f1 + + urdez f0,1.0 + urdez f0,f1 + + urds f0,1.0 + urds f0,f1 + + urdsm f0,1.0 + urdsm f0,f1 + + urdsp f0,1.0 + urdsp f0,f1 + + urdsz f0,1.0 + urdsz f0,f1 + + wfc r0 + + wfs r0 + +coprocessor COPRO_FPA_V2 + + label_lfm: + lfm f0,1,[r2] + lfm f0,1,[r2],4 + lfm f0,1,[r2],{4} + lfm f0,1,[r2,4] + lfm f0,1,[r2,4]! + lfm f0,1,[label_lfm] + lfm f0,1,[expression.word] + lfm f0,1,[expression.word]! + + lfmea f0,1,[r2] + lfmea f0,1,[r2]! + + lfmfd f0,1,[r2] + lfmfd f0,1,[r2]! + + label_sfm: + sfm f0,1,[r2] + sfm f0,1,[r2],4 + sfm f0,1,[r2],{4} + sfm f0,1,[r2,4] + sfm f0,1,[r2,4]! + sfm f0,1,[label_sfm] + sfm f0,1,[expression.word] + sfm f0,1,[expression.word]! + + sfmea f0,1,[r2] + sfmea f0,1,[r2]! + + sfmfd f0,1,[r2] + sfmfd f0,1,[r2]! diff --git a/armdoc/InstructionFormatsIWMMXT.asm b/armdoc/InstructionFormatsIWMMXT.asm new file mode 100644 index 0000000..b407b82 --- /dev/null +++ b/armdoc/InstructionFormatsIWMMXT.asm @@ -0,0 +1,630 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;To avoid unnecessary repetition only ARM mode is used +;here. There is no change needed for THUMB mode except +;to specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;Almost all instructions can be conditional. The +;condition code should be added at the end of the main +;opcode and before any size/type specifiers. For +;example: "addhi" and "vaddhi.i16". The syntax also +;supports the pre-UAL style of putting the condition +;before any modifiers like "s" or "fd". For example: +;"ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;IWMMXT, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_IWMMXT_V1 + + tandcb r15 + + tandch r15 + + tandcw r15 + + tbcstb wr0,r1 + + tbcsth wr0,r1 + + tbcstw wr0,r1 + + textrcb r15,4 + + textrch r15,2 + + textrcw r15,1 + + textrmsb r0,wr1,2 + + textrmsh r0,wr1,2 + + textrmsw r0,wr1,2 + + textrmub r0,wr1,2 + + textrmuh r0,wr1,2 + + textrmuw r0,wr1,2 + + tinsrb wr0,r1,2 + + tinsrh wr0,r1,2 + + tinsrw wr0,r1,2 + + tmcr wcgr0,r1 + + tmcrr wr0,r1,r2 + + tmia wr0,r1,r2 + + tmiabb wr0,r1,r2 + + tmiabt wr0,r1,r2 + + tmiaph wr0,r1,r2 + + tmiatb wr0,r1,r2 + + tmiatt wr0,r1,r2 + + tmovmskb r0,wr1 + + tmovmskh r0,wr1 + + tmovmskw r0,wr1 + + tmrc r0,wcgr1 + + tmrrc r0,r1,wr2 + + torcb r15 + + torch r15 + + torcw r15 + + waccb wr0,wr1 + + wacch wr0,wr1 + + waccw wr0,wr1 + + waddb wr0,wr1,wr2 + + waddbss wr0,wr1,wr2 + + waddbus wr0,wr1,wr2 + + waddh wr0,wr1,wr2 + + waddhss wr0,wr1,wr2 + + waddhus wr0,wr1,wr2 + + waddw wr0,wr1,wr2 + + waddwss wr0,wr1,wr2 + + waddwus wr0,wr1,wr2 + + waligni wr0,wr1,wr2,3 + + walignr0 wr1,wr1,wr2 + + walignr1 wr1,wr1,wr2 + + walignr2 wr1,wr1,wr2 + + walignr3 wr1,wr1,wr2 + + wand wr0,wr1,wr2 + + wandn wr0,wr1,wr2 + + wavg2b wr0,wr1,wr2 + + wavg2br wr0,wr1,wr2 + + wavg2h wr0,wr1,wr2 + + wavg2hr wr0,wr1,wr2 + + wcmpeqb wr0,wr1,wr2 + + wcmpeqh wr0,wr1,wr2 + + wcmpeqw wr0,wr1,wr2 + + wcmpgtsb wr1,wr1,wr2 + + wcmpgtsh wr1,wr1,wr2 + + wcmpgtsw wr1,wr1,wr2 + + wcmpgtub wr1,wr1,wr2 + + wcmpgtuh wr1,wr1,wr2 + + wcmpgtuw wr1,wr1,wr2 + + label_wldrb: + wldrb wr0,[r1] + wldrb wr0,[r1],4 + wldrb wr0,[r1],{4} + wldrb wr0,[r1,4] + wldrb wr0,[r1,4]! + wldrb wr0,[label_wldrb] + wldrb wr0,[expression.byte] + wldrb wr0,[expression.byte]! + + label_wldrd: + wldrd wr0,[r1] + wldrd wr0,[r1],4 + wldrd wr0,[r1],{4} + wldrd wr0,[r1,4] + wldrd wr0,[r1,4]! + wldrd wr0,[label_wldrd] + wldrd wr0,[expression.dword] + wldrd wr0,[expression.dword]! + + label_wldrh: + wldrh wr0,[r1] + wldrh wr0,[r1],4 + wldrh wr0,[r1],{4} + wldrh wr0,[r1,4] + wldrh wr0,[r1,4]! + wldrh wr0,[label_wldrh] + wldrh wr0,[expression.hword] + wldrh wr0,[expression.hword]! + + label_wldrw: + wldrw wr0,[r1] + wldrw wr0,[r1],4 + wldrw wr0,[r1],{4} + wldrw wr0,[r1,4] + wldrw wr0,[r1,4]! + wldrw wr0,[label_wldrw] + wldrw wr0,[expression.word] + wldrw wr0,[expression.word]! + wldrw wcgr0,[r1] + wldrw wcgr0,[r1],4 + wldrw wcgr0,[r1],{4} + wldrw wcgr0,[r1,4] + wldrw wcgr0,[r1,4]! + wldrw wcgr0,[label_wldrw] + wldrw wcgr0,[expression.word] + wldrw wcgr0,[expression.word]! + + wmacs wr0,wr1,wr2 + + wmacsz wr0,wr1,wr2 + + wmacu wr0,wr1,wr2 + + wmacuz wr0,wr1,wr2 + + wmadds wr0,wr1,wr2 + + wmaddu wr0,wr1,wr2 + + wmaxsb wr0,wr1,wr2 + + wmaxsh wr0,wr1,wr2 + + wmaxsw wr0,wr1,wr2 + + wmaxub wr0,wr1,wr2 + + wmaxuh wr0,wr1,wr2 + + wmaxuw wr0,wr1,wr2 + + wminsb wr0,wr1,wr2 + + wminsh wr0,wr1,wr2 + + wminsw wr0,wr1,wr2 + + wminub wr0,wr1,wr2 + + wminuh wr0,wr1,wr2 + + wminuw wr0,wr1,wr2 + + wmov wr0,wr1 + + wmulsl wr0,wr1,wr2 + + wmulsm wr0,wr1,wr2 + + wmulul wr0,wr1,wr2 + + wmulum wr0,wr1,wr2 + + wor wr0,wr1,wr2 + + wpackdss wr1,wr1,wr2 + + wpackdus wr1,wr1,wr2 + + wpackhss wr1,wr1,wr2 + + wpackhus wr1,wr1,wr2 + + wpackwss wr1,wr1,wr2 + + wpackwus wr1,wr1,wr2 + + wrord wr0,wr1,wr2 + + wrordg wr0,wr1,wcgr2 + + wrorh wr0,wr1,wr2 + + wrorhg wr0,wr1,wcgr2 + + wrorw wr0,wr1,wr2 + + wrorwg wr0,wr1,wcgr2 + + wsadb wr0,wr1,wr2 + + wsadbz wr0,wr1,wr2 + + wsadh wr0,wr1,wr2 + + wsadhz wr0,wr1,wr2 + + wshufh wr0,wr1,2 + + wshufh wr0,wr1,2 + + wslld wr0,wr1,wr2 + + wslldg wr0,wr1,wcgr2 + + wsllh wr0,wr1,wr2 + + wsllhg wr0,wr1,wcgr2 + + wsllw wr0,wr1,wr2 + + wsllwg wr0,wr1,wcgr2 + + wsrad wr0,wr1,wr2 + + wsradg wr0,wr1,wcgr2 + + wsrah wr0,wr1,wr2 + + wsrahg wr0,wr1,wcgr2 + + wsraw wr0,wr1,wr2 + + wsrawg wr0,wr1,wcgr2 + + wsrld wr0,wr1,wr2 + + wsrldg wr0,wr1,wcgr2 + + wsrlh wr0,wr1,wr2 + + wsrlhg wr0,wr1,wcgr2 + + wsrlw wr0,wr1,wr2 + + wsrlwg wr0,wr1,wcgr2 + + label_wstrb: + wstrb wr0,[r1] + wstrb wr0,[r1],4 + wstrb wr0,[r1],{4} + wstrb wr0,[r1,4] + wstrb wr0,[r1,4]! + wstrb wr0,[label_wstrb] + wstrb wr0,[expression.byte] + wstrb wr0,[expression.byte]! + + label_wstrd: + wstrd wr0,[r1] + wstrd wr0,[r1],4 + wstrd wr0,[r1],{4} + wstrd wr0,[r1,4] + wstrd wr0,[r1,4]! + wstrd wr0,[label_wstrd] + wstrd wr0,[expression.dword] + wstrd wr0,[expression.dword]! + + label_wstrh: + wstrh wr0,[r1] + wstrh wr0,[r1],4 + wstrh wr0,[r1],{4} + wstrh wr0,[r1,4] + wstrh wr0,[r1,4]! + wstrh wr0,[label_wstrh] + wstrh wr0,[expression.hword] + wstrh wr0,[expression.hword]! + + label_wstrw: + wstrw wr0,[r1] + wstrw wr0,[r1],4 + wstrw wr0,[r1],{4} + wstrw wr0,[r1,4] + wstrw wr0,[r1,4]! + wstrw wr0,[label_wstrw] + wstrw wr0,[expression.word] + wstrw wr0,[expression.word]! + wstrw wcgr0,[r1] + wstrw wcgr0,[r1],4 + wstrw wcgr0,[r1],{4} + wstrw wcgr0,[r1,4] + wstrw wcgr0,[r1,4]! + wstrw wcgr0,[label_wstrw] + wstrw wcgr0,[expression.word] + wstrw wcgr0,[expression.word]! + + wsubb wr0,wr1,wr2 + + wsubbss wr0,wr1,wr2 + + wsubbus wr0,wr1,wr2 + + wsubh wr0,wr1,wr2 + + wsubhss wr0,wr1,wr2 + + wsubhus wr0,wr1,wr2 + + wsubw wr0,wr1,wr2 + + wsubwss wr0,wr1,wr2 + + wsubwus wr0,wr1,wr2 + + wunpckehsb wr0,wr1 + + wunpckehsh wr0,wr1 + + wunpckehsw wr0,wr1 + + wunpckehub wr0,wr1 + + wunpckehuh wr0,wr1 + + wunpckehuw wr0,wr1 + + wunpckelsb wr0,wr1 + + wunpckelsh wr0,wr1 + + wunpckelsw wr0,wr1 + + wunpckelub wr0,wr1 + + wunpckeluh wr0,wr1 + + wunpckeluw wr0,wr1 + + wunpckihb wr0,wr1,wr2 + + wunpckihh wr0,wr1,wr2 + + wunpckihw wr0,wr1,wr2 + + wunpckilb wr0,wr1,wr2 + + wunpckilh wr0,wr1,wr2 + + wunpckilw wr0,wr1,wr2 + + wxor wr0,wr1,wr2 + + wzero wr0 + +coprocessor COPRO_IWMMXT_V2 + torvscb r15 + + torvsch r15 + + torvscw r15 + + wabsb wr0,wr1 + + wabsdiffb wr0,wr1,wr2 + + wabsdiffh wr0,wr1,wr2 + + wabsdiffw wr0,wr1,wr2 + + wabsh wr0,wr1 + + wabsw wr0,wr1 + + waddhc wr0,wr1,wr2 + + waddsubhx wr0,wr1,wr2 + + waddwc wr0,wr1,wr2 + + wavg4 wr0,wr1,wr2 + + wavg4r wr0,wr1,wr2 + + wldrd wr0,[r1],r2 + wldrd wr0,[r1],-r2 + wldrd wr0,[r1],r2,lsl 2 + wldrd wr0,[r1],-r2,lsl 2 + wldrd wr0,[r1,r2] + wldrd wr0,[r1,-r2] + wldrd wr0,[r1,r2]! + wldrd wr0,[r1,-r2]! + wldrd wr0,[r1,r2,lsl 2] + wldrd wr0,[r1,-r2,lsl 2] + wldrd wr0,[r1,r2,lsl 2]! + wldrd wr0,[r1,-r2,lsl 2]! + + wmaddsn wr0,wr1,wr2 + + wmaddsx wr0,wr1,wr2 + + wmaddun wr0,wr1,wr2 + + wmaddux wr0,wr1,wr2 + + wmerge wr0,wr1,wr2,3 + + wmiabb wr0,wr1,wr2 + + wmiabbn wr0,wr1,wr2 + + wmiabt wr0,wr1,wr2 + + wmiabtn wr0,wr1,wr2 + + wmiatb wr0,wr1,wr2 + + wmiatbn wr0,wr1,wr2 + + wmiatt wr0,wr1,wr2 + + wmiattn wr0,wr1,wr2 + + wmiawbb wr0,wr1,wr2 + + wmiawbbn wr0,wr1,wr2 + + wmiawbt wr0,wr1,wr2 + + wmiawbtn wr0,wr1,wr2 + + wmiawtb wr0,wr1,wr2 + + wmiawtbn wr0,wr1,wr2 + + wmiawtt wr0,wr1,wr2 + + wmiawttn wr0,wr1,wr2 + + wmulsmr wr0,wr1,wr2 + + wmulumr wr0,wr1,wr2 + + wmulwl wr0,wr1,wr2 + + wmulwsm wr0,wr1,wr2 + + wmulwsmr wr0,wr1,wr2 + + wmulwum wr0,wr1,wr2 + + wmulwumr wr0,wr1,wr2 + + wqmiabb wr0,wr1,wr2 + + wqmiabbn wr0,wr1,wr2 + + wqmiabt wr0,wr1,wr2 + + wqmiabtn wr0,wr1,wr2 + + wqmiatb wr0,wr1,wr2 + + wqmiatbn wr0,wr1,wr2 + + wqmiatt wr0,wr1,wr2 + + wqmiattn wr0,wr1,wr2 + + wqmulm wr0,wr1,wr2 + + wqmulmr wr0,wr1,wr2 + + wqmulwm wr0,wr1,wr2 + + wqmulwmr wr0,wr1,wr2 + + wrord wr0,wr1,2 + + wrorh wr0,wr1,2 + + wrorw wr0,wr1,2 + + wslld wr0,wr1,2 + + wsllh wr0,wr1,2 + + wsllw wr0,wr1,2 + + wsrad wr0,wr1,2 + + wsrah wr0,wr1,2 + + wsraw wr0,wr1,2 + + wsrld wr0,wr1,2 + + wsrlh wr0,wr1,2 + + wsrlw wr0,wr1,2 + + wstrd wr0,[r1],r2 + wstrd wr0,[r1],-r2 + wstrd wr0,[r1],r2,lsl 2 + wstrd wr0,[r1],-r2,lsl 2 + wstrd wr0,[r1,r2] + wstrd wr0,[r1,-r2] + wstrd wr0,[r1,r2]! + wstrd wr0,[r1,-r2]! + wstrd wr0,[r1,r2,lsl 2] + wstrd wr0,[r1,-r2,lsl 2] + wstrd wr0,[r1,r2,lsl 2]! + wstrd wr0,[r1,-r2,lsl 2]! + + wsubaddhx wr0,wr1,wr2 diff --git a/armdoc/InstructionFormatsMAVERICK.asm b/armdoc/InstructionFormatsMAVERICK.asm new file mode 100644 index 0000000..e82b768 --- /dev/null +++ b/armdoc/InstructionFormatsMAVERICK.asm @@ -0,0 +1,278 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;To avoid unnecessary repetition only ARM mode is used +;here. There is no change needed for THUMB mode except +;to specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;All instructions can be conditional. The condition code +;should be added at the end of the main opcode and +;before any size/type specifiers. For example: "addhi" +;and "vaddhi.i16". The syntax also supports the pre-UAL +;style of putting the condition before any modifiers +;like "s" or "fd". For example: "ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;MAVERICK, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_MAVERICK + + cfabs32 c0,c1 + + cfabs64 c0,c1 + + cfabsd c0,c1 + + cfabss c0,c1 + + cfadd32 c0,c1,c2 + + cfadd64 c0,c1,c2 + + cfaddd c0,c1,c2 + + cfadds c0,c1,c2 + + cfcmp32 r1,c1,c2 + + cfcmp64 r1,c1,c2 + + cfcmpd r1,c1,c2 + + cfcmps r1,c1,c2 + + cfcpyd c0,c1 + + cfcpys c0,c1 + + cfcvt32d c0,c1 + + cfcvt32s c0,c1 + + cfcvt64d c0,c1 + + cfcvt64s c0,c1 + + cfcvtd32 c0,c1 + + cfcvtds c0,c1 + + cfcvts32 c0,c1 + + cfcvtsd c0,c1 + + label_cfldr32: + cfldr32 c0,[r1] + cfldr32 c0,[r1],4 + cfldr32 c0,[r1],{4} + cfldr32 c0,[r1,4] + cfldr32 c0,[r1,4]! + cfldr32 c0,[label_cfldr32] + cfldr32 c0,[expression.word] + cfldr32 c0,[expression.word]! + + label_cfldr64: + cfldr64 c0,[r1] + cfldr64 c0,[r1],4 + cfldr64 c0,[r1],{4} + cfldr64 c0,[r1,4] + cfldr64 c0,[r1,4]! + cfldr64 c0,[label_cfldr64] + cfldr64 c0,[expression.word] + cfldr64 c0,[expression.word]! + + label_cfldrd: + cfldrd c0,[r1] + cfldrd c0,[r1],4 + cfldrd c0,[r1],{4} + cfldrd c0,[r1,4] + cfldrd c0,[r1,4]! + cfldrd c0,[label_cfldrd] + cfldrd c0,[expression.word] + cfldrd c0,[expression.word]! + + label_cfldrs: + cfldrs c0,[r1] + cfldrs c0,[r1],4 + cfldrs c0,[r1],{4} + cfldrs c0,[r1,4] + cfldrs c0,[r1,4]! + cfldrs c0,[label_cfldrs] + cfldrs c0,[expression.word] + cfldrs c0,[expression.word]! + + cfmac32 c0,c1,c2 + + cfmadd32 a0,c1,c2,c3 + + cfmadda32 a0,a1,c2,c4 + + cfmsc32 c0,c1,c2 + + cfmsub32 a0,c1,c2,c4 + + cfmsuba32 a0,a1,c2,c4 + + cfmul32 c0,c1,c2 + + cfmul64 c0,c1,c2 + + cfmuld c0,c1,c2 + + cfmuls c0,c1,c2 + + cfmv32a c0,a1 + + cfmv32ah c0,a1 + + cfmv32al c0,a1 + + cfmv32am c0,a1 + + cfmv32sc c0,dspsc + + cfmv64a c0,a1 + + cfmv64hr c0,r1 + + cfmv64lr c0,r1 + + cfmva32 a0,c1 + + cfmva64 a0,c1 + + cfmvah32 a0,c1 + + cfmval32 a0,c1 + + cfmvam32 a0,c1 + + cfmvdhr c0,r1 + + cfmvdlr c0,r1 + + cfmvr64h r1,c1 + + cfmvr64l r1,c1 + + cfmvrdh r1,c1 + + cfmvrdl r1,c1 + + cfmvrs r1,c1 + + cfmvsc32 dspsc,c0 + + cfmvsr c0,r1 + + cfneg32 c0,c1 + + cfneg64 c0,c1 + + cfnegd c0,c1 + + cfnegs c0,c1 + + cfrshl32 c0,c1,r3 + + cfrshl64 c0,c1,r3 + + cfsh32 c0,c1,2 + + cfsh64 c0,c1,2 + + label_cfstr32: + cfstr32 c0,[r1] + cfstr32 c0,[r1],4 + cfstr32 c0,[r1],{4} + cfstr32 c0,[r1,4] + cfstr32 c0,[r1,4]! + cfstr32 c0,[label_cfstr32] + cfstr32 c0,[expression.word] + cfstr32 c0,[expression.word]! + + label_cfstr64: + cfstr64 c0,[r1] + cfstr64 c0,[r1],4 + cfstr64 c0,[r1],{4} + cfstr64 c0,[r1,4] + cfstr64 c0,[r1,4]! + cfstr64 c0,[label_cfstr64] + cfstr64 c0,[expression.word] + cfstr64 c0,[expression.word]! + + label_cfstrd: + cfstrd c0,[r1] + cfstrd c0,[r1],4 + cfstrd c0,[r1],{4} + cfstrd c0,[r1,4] + cfstrd c0,[r1,4]! + cfstrd c0,[label_cfstrd] + cfstrd c0,[expression.word] + cfstrd c0,[expression.word]! + + label_cfstrs: + cfstrs c0,[r1] + cfstrs c0,[r1],4 + cfstrs c0,[r1],{4} + cfstrs c0,[r1,4] + cfstrs c0,[r1,4]! + cfstrs c0,[label_cfstrs] + cfstrs c0,[expression.word] + cfstrs c0,[expression.word]! + + cfsub32 c0,c1,c2 + + cfsub64 c0,c1,c2 + + cfsubd c0,c1,c2 + + cfsubs c0,c1,c2 + + cftruncd32 c0,c1 + + cftruncs32 c0,c1 diff --git a/armdoc/InstructionFormatsSIMD.asm b/armdoc/InstructionFormatsSIMD.asm new file mode 100644 index 0000000..d24dc0d --- /dev/null +++ b/armdoc/InstructionFormatsSIMD.asm @@ -0,0 +1,3056 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;To avoid unnecessary repetition only ARM mode is used +;here. There is no change needed for THUMB mode except +;to specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;In THUMB mode all instructions can be conditional. In +;ARM mode most instructions are unconditional. The +;condition code should be added at the end of the main +;opcode and before any size/type specifiers. For +;example: "addhi" and "vaddhi.i16". The syntax also +;supports the pre-UAL style of putting the condition +;before any modifiers like "s" or "fd". For example: +;"ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;SIMD, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_SIMD_INT + + vaba.s16 d0,d1,d2 + vaba.s16 q0,q1,q2 + + vaba.s32 d0,d1,d2 + vaba.s32 q0,q1,q2 + + vaba.s8 d0,d1,d2 + vaba.s8 q0,q1,q2 + + vaba.u16 d0,d1,d2 + vaba.u16 q0,q1,q2 + + vaba.u32 d0,d1,d2 + vaba.u32 q0,q1,q2 + + vaba.u8 d0,d1,d2 + vaba.u8 q0,q1,q2 + + vabal.s16 q0,d1,d2 + + vabal.s32 q0,d1,d2 + + vabal.s8 q0,d1,d2 + + vabal.u16 q0,d1,d2 + + vabal.u32 q0,d1,d2 + + vabal.u8 q0,d1,d2 + + vabd.s16 d0,d1 + vabd.s16 d0,d1,d2 + vabd.s16 q0,q1 + vabd.s16 q0,q1,q2 + + vabd.s32 d0,d1 + vabd.s32 d0,d1,d2 + vabd.s32 q0,q1 + vabd.s32 q0,q1,q2 + + vabd.s8 d0,d1 + vabd.s8 d0,d1,d2 + vabd.s8 q0,q1 + vabd.s8 q0,q1,q2 + + vabd.u16 d0,d1 + vabd.u16 d0,d1,d2 + vabd.u16 q0,q1 + vabd.u16 q0,q1,q2 + + vabd.u32 d0,d1 + vabd.u32 d0,d1,d2 + vabd.u32 q0,q1 + vabd.u32 q0,q1,q2 + + vabd.u8 d0,d1 + vabd.u8 d0,d1,d2 + vabd.u8 q0,q1 + vabd.u8 q0,q1,q2 + + vabdl.s16 q0,d1,d2 + + vabdl.s32 q0,d1,d2 + + vabdl.s8 q0,d1,d2 + + vabdl.u16 q0,d1,d2 + + vabdl.u32 q0,d1,d2 + + vabdl.u8 q0,d1,d2 + + vabs.s16 d0,d1 + vabs.s16 q0,q1 + + vabs.s32 d0,d1 + vabs.s32 q0,q1 + + vabs.s8 d0,d1 + vabs.s8 q0,q1 + + vadd.i16 d0,d1 + vadd.i16 d0,d1,d2 + vadd.i16 q0,q1 + vadd.i16 q0,q1,q2 + + vadd.i32 d0,d1 + vadd.i32 d0,d1,d2 + vadd.i32 q0,q1 + vadd.i32 q0,q1,q2 + + vadd.i64 d0,d1 + vadd.i64 d0,d1,d2 + vadd.i64 q0,q1 + vadd.i64 q0,q1,q2 + + vadd.i8 d0,d1 + vadd.i8 d0,d1,d2 + vadd.i8 q0,q1 + vadd.i8 q0,q1,q2 + + vaddhn.i16 d0,q1,q2 + + vaddhn.i32 d0,q1,q2 + + vaddhn.i64 d0,q1,q2 + + vaddl.s16 q0,d1,d2 + + vaddl.s32 q0,d1,d2 + + vaddl.s8 q0,d1,d2 + + vaddl.u16 q0,d1,d2 + + vaddl.u32 q0,d1,d2 + + vaddl.u8 q0,d1,d2 + + vaddw.s16 q0,d1 + vaddw.s16 q0,q1,d2 + + vaddw.s32 q0,d1 + vaddw.s32 q0,q1,d2 + + vaddw.s8 q0,d1 + vaddw.s8 q0,q1,d2 + + vaddw.u16 q0,d1 + vaddw.u16 q0,q1,d2 + + vaddw.u32 q0,d1 + vaddw.u32 q0,q1,d2 + + vaddw.u8 q0,d1 + vaddw.u8 q0,q1,d2 + + vand d0,d1 + vand d0,d1,d2 + vand q0,q1 + vand q0,q1,q2 + + vand.i16 d0,not 1 + vand.i16 q0,0xfffe + + vand.i32 d0,not 1 + vand.i32 q0,not 1 + + vbic d0,d1 + vbic d0,d1,d2 + vbic q0,q1 + vbic q0,q1,q2 + + vbic.i16 d0,1 + vbic.i16 q0,not -2 + + vbic.i32 d0,1 + vbic.i32 q0,1 + + vbif d0,d1 + vbif d0,d1,d2 + vbif q0,q1 + vbif q0,q1,q2 + + vbit d0,d1 + vbit d0,d1,d2 + vbit q0,q1 + vbit q0,q1,q2 + + vbsl d0,d1 + vbsl d0,d1,d2 + vbsl q0,q1 + vbsl q0,q1,q2 + + vceq.i16 d0,0 + vceq.i16 d0,d1 + vceq.i16 d0,d1,0 + vceq.i16 d0,d1,d2 + vceq.i16 q0,0 + vceq.i16 q0,q1 + vceq.i16 q0,q1,0 + vceq.i16 q0,q1,q2 + + vceq.i32 d0,0 + vceq.i32 d0,d1 + vceq.i32 d0,d1,0 + vceq.i32 d0,d1,d2 + vceq.i32 q0,0 + vceq.i32 q0,q1 + vceq.i32 q0,q1,0 + vceq.i32 q0,q1,q2 + + vceq.i8 d0,0 + vceq.i8 d0,d1 + vceq.i8 d0,d1,0 + vceq.i8 d0,d1,d2 + vceq.i8 q0,0 + vceq.i8 q0,q1 + vceq.i8 q0,q1,0 + vceq.i8 q0,q1,q2 + + vcge.s16 d0,0 + vcge.s16 d0,d1 + vcge.s16 d0,d1,0 + vcge.s16 d0,d1,d2 + vcge.s16 q0,0 + vcge.s16 q0,q1 + vcge.s16 q0,q1,0 + vcge.s16 q0,q1,q2 + + vcge.s32 d0,0 + vcge.s32 d0,d1 + vcge.s32 d0,d1,0 + vcge.s32 d0,d1,d2 + vcge.s32 q0,0 + vcge.s32 q0,q1 + vcge.s32 q0,q1,0 + vcge.s32 q0,q1,q2 + + vcge.s8 d0,0 + vcge.s8 d0,d1 + vcge.s8 d0,d1,0 + vcge.s8 d0,d1,d2 + vcge.s8 q0,0 + vcge.s8 q0,q1 + vcge.s8 q0,q1,0 + vcge.s8 q0,q1,q2 + + vcge.u16 d0,d1 + vcge.u16 d0,d1,d2 + vcge.u16 q0,q1 + vcge.u16 q0,q1,q2 + + vcge.u32 d0,d1 + vcge.u32 d0,d1,d2 + vcge.u32 q0,q1 + vcge.u32 q0,q1,q2 + + vcge.u8 d0,d1 + vcge.u8 d0,d1,d2 + vcge.u8 q0,q1 + vcge.u8 q0,q1,q2 + + vcgt.s16 d0,0 + vcgt.s16 d0,d1 + vcgt.s16 d0,d1,0 + vcgt.s16 d0,d1,d2 + vcgt.s16 q0,0 + vcgt.s16 q0,q1 + vcgt.s16 q0,q1,0 + vcgt.s16 q0,q1,q2 + + vcgt.s32 d0,0 + vcgt.s32 d0,d1 + vcgt.s32 d0,d1,0 + vcgt.s32 d0,d1,d2 + vcgt.s32 q0,0 + vcgt.s32 q0,q1 + vcgt.s32 q0,q1,0 + vcgt.s32 q0,q1,q2 + + vcgt.s8 d0,0 + vcgt.s8 d0,d1 + vcgt.s8 d0,d1,0 + vcgt.s8 d0,d1,d2 + vcgt.s8 q0,0 + vcgt.s8 q0,q1 + vcgt.s8 q0,q1,0 + vcgt.s8 q0,q1,q2 + + vcgt.u16 d0,d1 + vcgt.u16 d0,d1,d2 + vcgt.u16 q0,q1 + vcgt.u16 q0,q1,q2 + + vcgt.u32 d0,d1 + vcgt.u32 d0,d1,d2 + vcgt.u32 q0,q1 + vcgt.u32 q0,q1,q2 + + vcgt.u8 d0,d1 + vcgt.u8 d0,d1,d2 + vcgt.u8 q0,q1 + vcgt.u8 q0,q1,q2 + + vcle.s16 d0,0 + vcle.s16 d0,d1 + vcle.s16 d0,d1,0 + vcle.s16 d0,d1,d2 + vcle.s16 q0,0 + vcle.s16 q0,q1 + vcle.s16 q0,q1,0 + vcle.s16 q0,q1,q2 + + vcle.s32 d0,0 + vcle.s32 d0,d1 + vcle.s32 d0,d1,0 + vcle.s32 d0,d1,d2 + vcle.s32 q0,0 + vcle.s32 q0,q1 + vcle.s32 q0,q1,0 + vcle.s32 q0,q1,q2 + + vcle.s8 d0,0 + vcle.s8 d0,d1 + vcle.s8 d0,d1,0 + vcle.s8 d0,d1,d2 + vcle.s8 q0,0 + vcle.s8 q0,q1 + vcle.s8 q0,q1,0 + vcle.s8 q0,q1,q2 + + vcle.u16 d0,d1 + vcle.u16 d0,d1,d2 + vcle.u16 q0,q1 + vcle.u16 q0,q1,q2 + + vcle.u32 d0,d1 + vcle.u32 d0,d1,d2 + vcle.u32 q0,q1 + vcle.u32 q0,q1,q2 + + vcle.u8 d0,d1 + vcle.u8 d0,d1,d2 + vcle.u8 q0,q1 + vcle.u8 q0,q1,q2 + + vcls.s16 d0,d1 + vcls.s16 q0,q1 + + vcls.s32 d0,d1 + vcls.s32 q0,q1 + + vcls.s8 d0,d1 + vcls.s8 q0,q1 + + vclt.s16 d0,0 + vclt.s16 d0,d1 + vclt.s16 d0,d1,0 + vclt.s16 d0,d1,d2 + vclt.s16 q0,0 + vclt.s16 q0,q1 + vclt.s16 q0,q1,0 + vclt.s16 q0,q1,q2 + + vclt.s32 d0,0 + vclt.s32 d0,d1 + vclt.s32 d0,d1,0 + vclt.s32 d0,d1,d2 + vclt.s32 q0,0 + vclt.s32 q0,q1 + vclt.s32 q0,q1,0 + vclt.s32 q0,q1,q2 + + vclt.s8 d0,0 + vclt.s8 d0,d1 + vclt.s8 d0,d1,0 + vclt.s8 d0,d1,d2 + vclt.s8 q0,0 + vclt.s8 q0,q1 + vclt.s8 q0,q1,0 + vclt.s8 q0,q1,q2 + + vclt.u16 d0,d1 + vclt.u16 d0,d1,d2 + vclt.u16 q0,q1 + vclt.u16 q0,q1,q2 + + vclt.u32 d0,d1 + vclt.u32 d0,d1,d2 + vclt.u32 q0,q1 + vclt.u32 q0,q1,q2 + + vclt.u8 d0,d1 + vclt.u8 d0,d1,d2 + vclt.u8 q0,q1 + vclt.u8 q0,q1,q2 + + vclz.i16 d0,d1 + vclz.i16 q0,q1 + + vclz.i32 d0,d1 + vclz.i32 q0,q1 + + vclz.i8 d0,d1 + vclz.i8 q0,q1 + + vcnt.8 d0,d1 + vcnt.8 q0,q1 + + vdup.16 d0,d1[0] + vdup.16 d0,r1 + vdup.16 q0,d1[1] + vdup.16 q0,r1 + + vdup.32 d0,d1[0] + vdup.32 d0,r1 + vdup.32 q0,d1[1] + vdup.32 q0,r1 + + vdup.8 d0,d1[0] + vdup.8 d0,r1 + vdup.8 q0,d1[1] + vdup.8 q0,r1 + + veor d0,d1 + veor d0,d1,d2 + veor q0,q1 + veor q0,q1,q2 + + vext.16 d0,d1,1 + vext.16 d0,d1,d2,1 + vext.16 q0,q1,1 + vext.16 q0,q1,q2,1 + + vext.32 d0,d1,1 + vext.32 d0,d1,d2,1 + vext.32 q0,q1,1 + vext.32 q0,q1,q2,1 + + vext.64 d0,d1,0 + vext.64 d0,d1,d2,0 + vext.64 q0,q1,1 + vext.64 q0,q1,q2,1 + + vext.8 d0,d1,2 + vext.8 d0,d1,d2,1 + vext.8 q0,q1,2 + vext.8 q0,q1,q2,1 + + vhadd.s16 d0,d1 + vhadd.s16 d0,d1,d2 + vhadd.s16 q0,q1 + vhadd.s16 q0,q1,q2 + + vhadd.s32 d0,d1 + vhadd.s32 d0,d1,d2 + vhadd.s32 q0,q1 + vhadd.s32 q0,q1,q2 + + vhadd.s8 d0,d1 + vhadd.s8 d0,d1,d2 + vhadd.s8 q0,q1 + vhadd.s8 q0,q1,q2 + + vhadd.u16 d0,d1 + vhadd.u16 d0,d1,d2 + vhadd.u16 q0,q1 + vhadd.u16 q0,q1,q2 + + vhadd.u32 d0,d1 + vhadd.u32 d0,d1,d2 + vhadd.u32 q0,q1 + vhadd.u32 q0,q1,q2 + + vhadd.u8 d0,d1 + vhadd.u8 d0,d1,d2 + vhadd.u8 q0,q1 + vhadd.u8 q0,q1,q2 + + vhsub.s16 d0,d1 + vhsub.s16 d0,d1,d2 + vhsub.s16 q0,q1 + vhsub.s16 q0,q1,q2 + + vhsub.s32 d0,d1 + vhsub.s32 d0,d1,d2 + vhsub.s32 q0,q1 + vhsub.s32 q0,q1,q2 + + vhsub.s8 d0,d1 + vhsub.s8 d0,d1,d2 + vhsub.s8 q0,q1 + vhsub.s8 q0,q1,q2 + + vhsub.u16 d0,d1 + vhsub.u16 d0,d1,d2 + vhsub.u16 q0,q1 + vhsub.u16 q0,q1,q2 + + vhsub.u32 d0,d1 + vhsub.u32 d0,d1,d2 + vhsub.u32 q0,q1 + vhsub.u32 q0,q1,q2 + + vhsub.u8 d0,d1 + vhsub.u8 d0,d1,d2 + vhsub.u8 q0,q1 + vhsub.u8 q0,q1,q2 + + vld1.16 {d0},[r1] + vld1.16 {d0},[r1]! + vld1.16 {d0},[r1],8 + vld1.16 {d0},[r1],r2 + vld1.16 {d0},[r1@64] + vld1.16 {d0},[r1@64]! + vld1.16 {d0},[r1@64],8 + vld1.16 {d0},[r1@64],r2 + vld1.16 {d0,d1},[r2] + vld1.16 {d0,d1},[r2]! + vld1.16 {d0,d1},[r2],16 + vld1.16 {d0,d1},[r2],r3 + vld1.16 {d0,d1},[r2@64] + vld1.16 {d0,d1},[r2@64]! + vld1.16 {d0,d1},[r2@64],16 + vld1.16 {d0,d1},[r2@64],r3 + vld1.16 {d0,d1,d2},[r3] + vld1.16 {d0,d1,d2},[r3]! + vld1.16 {d0,d1,d2},[r3],24 + vld1.16 {d0,d1,d2},[r3],r4 + vld1.16 {d0,d1,d2},[r3@64] + vld1.16 {d0,d1,d2},[r3@64]! + vld1.16 {d0,d1,d2},[r3@64],24 + vld1.16 {d0,d1,d2},[r3@64],r4 + vld1.16 {d0,d1,d2,d3},[r4] + vld1.16 {d0,d1,d2,d3},[r4]! + vld1.16 {d0,d1,d2,d3},[r4],32 + vld1.16 {d0,d1,d2,d3},[r4],r5 + vld1.16 {d0,d1,d2,d3},[r4@64] + vld1.16 {d0,d1,d2,d3},[r4@64]! + vld1.16 {d0,d1,d2,d3},[r4@64],32 + vld1.16 {d0,d1,d2,d3},[r4@64],r5 + vld1.16 {d0[1]},[r2] + vld1.16 {d0[1]},[r2]! + vld1.16 {d0[1]},[r2],2 + vld1.16 {d0[1]},[r2],r3 + vld1.16 {d0[1]},[r2@16] + vld1.16 {d0[1]},[r2@16]! + vld1.16 {d0[1]},[r2@16],2 + vld1.16 {d0[1]},[r2@16],r3 + vld1.16 {d0[]},[r1] + vld1.16 {d0[]},[r1]! + vld1.16 {d0[]},[r1],2 + vld1.16 {d0[]},[r1],r2 + vld1.16 {d0[]},[r1@16] + vld1.16 {d0[]},[r1@16]! + vld1.16 {d0[]},[r1@16],2 + vld1.16 {d0[]},[r1@16],r2 + vld1.16 {d0[],d1[]},[r2] + vld1.16 {d0[],d1[]},[r2]! + vld1.16 {d0[],d1[]},[r2],2 + vld1.16 {d0[],d1[]},[r2],r3 + vld1.16 {d0[],d1[]},[r2@16] + vld1.16 {d0[],d1[]},[r2@16]! + vld1.16 {d0[],d1[]},[r2@16],2 + vld1.16 {d0[],d1[]},[r2@16],r3 + + vld1.32 {d0},[r1] + vld1.32 {d0},[r1]! + vld1.32 {d0},[r1],8 + vld1.32 {d0},[r1],r2 + vld1.32 {d0},[r1@64] + vld1.32 {d0},[r1@64]! + vld1.32 {d0},[r1@64],8 + vld1.32 {d0},[r1@64],r2 + vld1.32 {d0,d1},[r2] + vld1.32 {d0,d1},[r2]! + vld1.32 {d0,d1},[r2],16 + vld1.32 {d0,d1},[r2],r3 + vld1.32 {d0,d1},[r2@64] + vld1.32 {d0,d1},[r2@64]! + vld1.32 {d0,d1},[r2@64],16 + vld1.32 {d0,d1},[r2@64],r3 + vld1.32 {d0,d1,d2},[r3] + vld1.32 {d0,d1,d2},[r3]! + vld1.32 {d0,d1,d2},[r3],24 + vld1.32 {d0,d1,d2},[r3],r4 + vld1.32 {d0,d1,d2},[r3@64] + vld1.32 {d0,d1,d2},[r3@64]! + vld1.32 {d0,d1,d2},[r3@64],24 + vld1.32 {d0,d1,d2},[r3@64],r4 + vld1.32 {d0,d1,d2,d3},[r4] + vld1.32 {d0,d1,d2,d3},[r4]! + vld1.32 {d0,d1,d2,d3},[r4],32 + vld1.32 {d0,d1,d2,d3},[r4],r5 + vld1.32 {d0,d1,d2,d3},[r4@64] + vld1.32 {d0,d1,d2,d3},[r4@64]! + vld1.32 {d0,d1,d2,d3},[r4@64],32 + vld1.32 {d0,d1,d2,d3},[r4@64],r5 + vld1.32 {d0[1]},[r2] + vld1.32 {d0[1]},[r2]! + vld1.32 {d0[1]},[r2],4 + vld1.32 {d0[1]},[r2],r3 + vld1.32 {d0[1]},[r2@32] + vld1.32 {d0[1]},[r2@32]! + vld1.32 {d0[1]},[r2@32],4 + vld1.32 {d0[1]},[r2@32],r3 + vld1.32 {d0[]},[r1] + vld1.32 {d0[]},[r1]! + vld1.32 {d0[]},[r1],4 + vld1.32 {d0[]},[r1],r2 + vld1.32 {d0[]},[r1@32] + vld1.32 {d0[]},[r1@32]! + vld1.32 {d0[]},[r1@32],4 + vld1.32 {d0[]},[r1@32],r2 + vld1.32 {d0[],d1[]},[r2] + vld1.32 {d0[],d1[]},[r2]! + vld1.32 {d0[],d1[]},[r2],4 + vld1.32 {d0[],d1[]},[r2],r3 + vld1.32 {d0[],d1[]},[r2@32] + vld1.32 {d0[],d1[]},[r2@32]! + vld1.32 {d0[],d1[]},[r2@32],4 + vld1.32 {d0[],d1[]},[r2@32],r3 + + vld1.64 {d0},[r1] + vld1.64 {d0},[r1]! + vld1.64 {d0},[r1],8 + vld1.64 {d0},[r1],r2 + vld1.64 {d0},[r1@64] + vld1.64 {d0},[r1@64]! + vld1.64 {d0},[r1@64],8 + vld1.64 {d0},[r1@64],r2 + vld1.64 {d0,d1},[r2] + vld1.64 {d0,d1},[r2]! + vld1.64 {d0,d1},[r2],16 + vld1.64 {d0,d1},[r2],r3 + vld1.64 {d0,d1},[r2@64] + vld1.64 {d0,d1},[r2@64]! + vld1.64 {d0,d1},[r2@64],16 + vld1.64 {d0,d1},[r2@64],r3 + vld1.64 {d0,d1,d2},[r3] + vld1.64 {d0,d1,d2},[r3]! + vld1.64 {d0,d1,d2},[r3],24 + vld1.64 {d0,d1,d2},[r3],r4 + vld1.64 {d0,d1,d2},[r3@64] + vld1.64 {d0,d1,d2},[r3@64]! + vld1.64 {d0,d1,d2},[r3@64],24 + vld1.64 {d0,d1,d2},[r3@64],r4 + vld1.64 {d0,d1,d2,d3},[r4] + vld1.64 {d0,d1,d2,d3},[r4]! + vld1.64 {d0,d1,d2,d3},[r4],32 + vld1.64 {d0,d1,d2,d3},[r4],r5 + vld1.64 {d0,d1,d2,d3},[r4@64] + vld1.64 {d0,d1,d2,d3},[r4@64]! + vld1.64 {d0,d1,d2,d3},[r4@64],32 + vld1.64 {d0,d1,d2,d3},[r4@64],r5 + + vld1.8 {d0},[r1] + vld1.8 {d0},[r1]! + vld1.8 {d0},[r1],8 + vld1.8 {d0},[r1],r2 + vld1.8 {d0},[r1@64] + vld1.8 {d0},[r1@64]! + vld1.8 {d0},[r1@64],8 + vld1.8 {d0},[r1@64],r2 + vld1.8 {d0,d1},[r2] + vld1.8 {d0,d1},[r2]! + vld1.8 {d0,d1},[r2],16 + vld1.8 {d0,d1},[r2],r3 + vld1.8 {d0,d1},[r2@64] + vld1.8 {d0,d1},[r2@64]! + vld1.8 {d0,d1},[r2@64],16 + vld1.8 {d0,d1},[r2@64],r3 + vld1.8 {d0,d1,d2},[r3] + vld1.8 {d0,d1,d2},[r3]! + vld1.8 {d0,d1,d2},[r3],24 + vld1.8 {d0,d1,d2},[r3],r4 + vld1.8 {d0,d1,d2},[r3@64] + vld1.8 {d0,d1,d2},[r3@64]! + vld1.8 {d0,d1,d2},[r3@64],24 + vld1.8 {d0,d1,d2},[r3@64],r4 + vld1.8 {d0,d1,d2,d3},[r4] + vld1.8 {d0,d1,d2,d3},[r4]! + vld1.8 {d0,d1,d2,d3},[r4],32 + vld1.8 {d0,d1,d2,d3},[r4],r5 + vld1.8 {d0,d1,d2,d3},[r4@64] + vld1.8 {d0,d1,d2,d3},[r4@64]! + vld1.8 {d0,d1,d2,d3},[r4@64],32 + vld1.8 {d0,d1,d2,d3},[r4@64],r5 + vld1.8 {d0[1]},[r2] + vld1.8 {d0[1]},[r2]! + vld1.8 {d0[1]},[r2],1 + vld1.8 {d0[1]},[r2],r3 + vld1.8 {d0[]},[r1] + vld1.8 {d0[]},[r1]! + vld1.8 {d0[]},[r1],1 + vld1.8 {d0[]},[r1],r2 + vld1.8 {d0[],d1[]},[r2] + vld1.8 {d0[],d1[]},[r2]! + vld1.8 {d0[],d1[]},[r2],1 + vld1.8 {d0[],d1[]},[r2],r3 + + vld2.16 {d0,d1},[r2] + vld2.16 {d0,d1},[r2]! + vld2.16 {d0,d1},[r2],16 + vld2.16 {d0,d1},[r2],r3 + vld2.16 {d0,d1},[r2@64] + vld2.16 {d0,d1},[r2@64]! + vld2.16 {d0,d1},[r2@64],16 + vld2.16 {d0,d1},[r2@64],r3 + vld2.16 {d0,d2},[r3] + vld2.16 {d0,d2},[r3]! + vld2.16 {d0,d2},[r3],16 + vld2.16 {d0,d2},[r3],r4 + vld2.16 {d0,d2},[r3@64] + vld2.16 {d0,d2},[r3@64]! + vld2.16 {d0,d2},[r3@64],16 + vld2.16 {d0,d2},[r3@64],r4 + vld2.16 {d0,d1,d2,d3},[r4] + vld2.16 {d0,d1,d2,d3},[r4]! + vld2.16 {d0,d1,d2,d3},[r4],32 + vld2.16 {d0,d1,d2,d3},[r4],r5 + vld2.16 {d0,d1,d2,d3},[r4@64] + vld2.16 {d0,d1,d2,d3},[r4@64]! + vld2.16 {d0,d1,d2,d3},[r4@64],32 + vld2.16 {d0,d1,d2,d3},[r4@64],r5 + vld2.16 {d0[1],d1[1]},[r2] + vld2.16 {d0[1],d1[1]},[r2]! + vld2.16 {d0[1],d1[1]},[r2],4 + vld2.16 {d0[1],d1[1]},[r2],r3 + vld2.16 {d0[1],d1[1]},[r2@32] + vld2.16 {d0[1],d1[1]},[r2@32]! + vld2.16 {d0[1],d1[1]},[r2@32],4 + vld2.16 {d0[1],d1[1]},[r2@32],r3 + vld2.16 {d0[1],d2[1]},[r2] + vld2.16 {d0[1],d2[1]},[r2]! + vld2.16 {d0[1],d2[1]},[r2],4 + vld2.16 {d0[1],d2[1]},[r2],r3 + vld2.16 {d0[1],d2[1]},[r2@32] + vld2.16 {d0[1],d2[1]},[r2@32]! + vld2.16 {d0[1],d2[1]},[r2@32],4 + vld2.16 {d0[1],d2[1]},[r2@32],r3 + vld2.16 {d0[],d1[]},[r2] + vld2.16 {d0[],d1[]},[r2]! + vld2.16 {d0[],d1[]},[r2],4 + vld2.16 {d0[],d1[]},[r2],r3 + vld2.16 {d0[],d1[]},[r2@32] + vld2.16 {d0[],d1[]},[r2@32]! + vld2.16 {d0[],d1[]},[r2@32],4 + vld2.16 {d0[],d1[]},[r2@32],r3 + vld2.16 {d0[],d2[]},[r2] + vld2.16 {d0[],d2[]},[r2]! + vld2.16 {d0[],d2[]},[r2],4 + vld2.16 {d0[],d2[]},[r2],r3 + vld2.16 {d0[],d2[]},[r2@32] + vld2.16 {d0[],d2[]},[r2@32]! + vld2.16 {d0[],d2[]},[r2@32],4 + vld2.16 {d0[],d2[]},[r2@32],r3 + + vld2.32 {d0,d1},[r2] + vld2.32 {d0,d1},[r2]! + vld2.32 {d0,d1},[r2],16 + vld2.32 {d0,d1},[r2],r3 + vld2.32 {d0,d1},[r2@64] + vld2.32 {d0,d1},[r2@64]! + vld2.32 {d0,d1},[r2@64],16 + vld2.32 {d0,d1},[r2@64],r3 + vld2.32 {d0,d2},[r3] + vld2.32 {d0,d2},[r3]! + vld2.32 {d0,d2},[r3],16 + vld2.32 {d0,d2},[r3],r4 + vld2.32 {d0,d2},[r3@64] + vld2.32 {d0,d2},[r3@64]! + vld2.32 {d0,d2},[r3@64],16 + vld2.32 {d0,d2},[r3@64],r4 + vld2.32 {d0,d1,d2,d3},[r4] + vld2.32 {d0,d1,d2,d3},[r4]! + vld2.32 {d0,d1,d2,d3},[r4],32 + vld2.32 {d0,d1,d2,d3},[r4],r5 + vld2.32 {d0,d1,d2,d3},[r4@64] + vld2.32 {d0,d1,d2,d3},[r4@64]! + vld2.32 {d0,d1,d2,d3},[r4@64],32 + vld2.32 {d0,d1,d2,d3},[r4@64],r5 + vld2.32 {d0[1],d1[1]},[r2] + vld2.32 {d0[1],d1[1]},[r2]! + vld2.32 {d0[1],d1[1]},[r2],8 + vld2.32 {d0[1],d1[1]},[r2],r3 + vld2.32 {d0[1],d1[1]},[r2@64] + vld2.32 {d0[1],d1[1]},[r2@64]! + vld2.32 {d0[1],d1[1]},[r2@64],8 + vld2.32 {d0[1],d1[1]},[r2@64],r3 + vld2.32 {d0[1],d2[1]},[r2] + vld2.32 {d0[1],d2[1]},[r2]! + vld2.32 {d0[1],d2[1]},[r2],8 + vld2.32 {d0[1],d2[1]},[r2],r3 + vld2.32 {d0[1],d2[1]},[r2@64] + vld2.32 {d0[1],d2[1]},[r2@64]! + vld2.32 {d0[1],d2[1]},[r2@64],8 + vld2.32 {d0[1],d2[1]},[r2@64],r3 + vld2.32 {d0[],d1[]},[r2] + vld2.32 {d0[],d1[]},[r2]! + vld2.32 {d0[],d1[]},[r2],8 + vld2.32 {d0[],d1[]},[r2],r3 + vld2.32 {d0[],d1[]},[r2@64] + vld2.32 {d0[],d1[]},[r2@64]! + vld2.32 {d0[],d1[]},[r2@64],8 + vld2.32 {d0[],d1[]},[r2@64],r3 + vld2.32 {d0[],d2[]},[r2] + vld2.32 {d0[],d2[]},[r2]! + vld2.32 {d0[],d2[]},[r2],8 + vld2.32 {d0[],d2[]},[r2],r3 + vld2.32 {d0[],d2[]},[r2@64] + vld2.32 {d0[],d2[]},[r2@64]! + vld2.32 {d0[],d2[]},[r2@64],8 + vld2.32 {d0[],d2[]},[r2@64],r3 + + vld2.8 {d0,d1},[r2] + vld2.8 {d0,d1},[r2]! + vld2.8 {d0,d1},[r2],16 + vld2.8 {d0,d1},[r2],r3 + vld2.8 {d0,d1},[r2@64] + vld2.8 {d0,d1},[r2@64]! + vld2.8 {d0,d1},[r2@64],16 + vld2.8 {d0,d1},[r2@64],r3 + vld2.8 {d0,d2},[r3] + vld2.8 {d0,d2},[r3]! + vld2.8 {d0,d2},[r3],16 + vld2.8 {d0,d2},[r3],r4 + vld2.8 {d0,d2},[r3@64] + vld2.8 {d0,d2},[r3@64]! + vld2.8 {d0,d2},[r3@64],16 + vld2.8 {d0,d2},[r3@64],r4 + vld2.8 {d0,d1,d2,d3},[r4] + vld2.8 {d0,d1,d2,d3},[r4]! + vld2.8 {d0,d1,d2,d3},[r4],32 + vld2.8 {d0,d1,d2,d3},[r4],r5 + vld2.8 {d0,d1,d2,d3},[r4@64] + vld2.8 {d0,d1,d2,d3},[r4@64]! + vld2.8 {d0,d1,d2,d3},[r4@64],32 + vld2.8 {d0,d1,d2,d3},[r4@64],r5 + vld2.8 {d0[1],d1[1]},[r2] + vld2.8 {d0[1],d1[1]},[r2]! + vld2.8 {d0[1],d1[1]},[r2],2 + vld2.8 {d0[1],d1[1]},[r2],r3 + vld2.8 {d0[1],d1[1]},[r2@16] + vld2.8 {d0[1],d1[1]},[r2@16]! + vld2.8 {d0[1],d1[1]},[r2@16],2 + vld2.8 {d0[1],d1[1]},[r2@16],r3 + vld2.8 {d0[],d1[]},[r2] + vld2.8 {d0[],d1[]},[r2]! + vld2.8 {d0[],d1[]},[r2],2 + vld2.8 {d0[],d1[]},[r2],r3 + vld2.8 {d0[],d1[]},[r2@16] + vld2.8 {d0[],d1[]},[r2@16]! + vld2.8 {d0[],d1[]},[r2@16],2 + vld2.8 {d0[],d1[]},[r2@16],r3 + vld2.8 {d0[],d2[]},[r2] + vld2.8 {d0[],d2[]},[r2]! + vld2.8 {d0[],d2[]},[r2],2 + vld2.8 {d0[],d2[]},[r2],r3 + vld2.8 {d0[],d2[]},[r2@16] + vld2.8 {d0[],d2[]},[r2@16]! + vld2.8 {d0[],d2[]},[r2@16],2 + vld2.8 {d0[],d2[]},[r2@16],r3 + + vld3.16 {d0,d1,d2},[r2] + vld3.16 {d0,d1,d2},[r2]! + vld3.16 {d0,d1,d2},[r2],24 + vld3.16 {d0,d1,d2},[r2],r3 + vld3.16 {d0,d1,d2},[r2@64] + vld3.16 {d0,d1,d2},[r2@64]! + vld3.16 {d0,d1,d2},[r2@64],24 + vld3.16 {d0,d1,d2},[r2@64],r3 + vld3.16 {d0,d2,d4},[r3] + vld3.16 {d0,d2,d4},[r3]! + vld3.16 {d0,d2,d4},[r3],24 + vld3.16 {d0,d2,d4},[r3],r4 + vld3.16 {d0,d2,d4},[r3@64] + vld3.16 {d0,d2,d4},[r3@64]! + vld3.16 {d0,d2,d4},[r3@64],24 + vld3.16 {d0,d2,d4},[r3@64],r4 + vld3.16 {d0[1],d1[1],d2[1]},[r2] + vld3.16 {d0[1],d1[1],d2[1]},[r2]! + vld3.16 {d0[1],d1[1],d2[1]},[r2],6 + vld3.16 {d0[1],d1[1],d2[1]},[r2],r3 + vld3.16 {d0[1],d2[1],d4[1]},[r2] + vld3.16 {d0[1],d2[1],d4[1]},[r2]! + vld3.16 {d0[1],d2[1],d4[1]},[r2],6 + vld3.16 {d0[1],d2[1],d4[1]},[r2],r3 + vld3.16 {d0[],d1[],d2[]},[r2] + vld3.16 {d0[],d1[],d2[]},[r2]! + vld3.16 {d0[],d1[],d2[]},[r2],6 + vld3.16 {d0[],d1[],d2[]},[r2],r3 + vld3.16 {d0[],d2[],d4[]},[r2] + vld3.16 {d0[],d2[],d4[]},[r2]! + vld3.16 {d0[],d2[],d4[]},[r2],6 + vld3.16 {d0[],d2[],d4[]},[r2],r3 + + vld3.32 {d0,d1,d2},[r2] + vld3.32 {d0,d1,d2},[r2]! + vld3.32 {d0,d1,d2},[r2],24 + vld3.32 {d0,d1,d2},[r2],r3 + vld3.32 {d0,d1,d2},[r2@64] + vld3.32 {d0,d1,d2},[r2@64]! + vld3.32 {d0,d1,d2},[r2@64],24 + vld3.32 {d0,d1,d2},[r2@64],r3 + vld3.32 {d0,d2,d4},[r3] + vld3.32 {d0,d2,d4},[r3]! + vld3.32 {d0,d2,d4},[r3],24 + vld3.32 {d0,d2,d4},[r3],r4 + vld3.32 {d0,d2,d4},[r3@64] + vld3.32 {d0,d2,d4},[r3@64]! + vld3.32 {d0,d2,d4},[r3@64],24 + vld3.32 {d0,d2,d4},[r3@64],r4 + vld3.32 {d0[1],d1[1],d2[1]},[r2] + vld3.32 {d0[1],d1[1],d2[1]},[r2]! + vld3.32 {d0[1],d1[1],d2[1]},[r2],12 + vld3.32 {d0[1],d1[1],d2[1]},[r2],r3 + vld3.32 {d0[1],d2[1],d4[1]},[r2] + vld3.32 {d0[1],d2[1],d4[1]},[r2]! + vld3.32 {d0[1],d2[1],d4[1]},[r2],12 + vld3.32 {d0[1],d2[1],d4[1]},[r2],r3 + vld3.32 {d0[],d1[],d2[]},[r2] + vld3.32 {d0[],d1[],d2[]},[r2]! + vld3.32 {d0[],d1[],d2[]},[r2],12 + vld3.32 {d0[],d1[],d2[]},[r2],r3 + vld3.32 {d0[],d2[],d4[]},[r2] + vld3.32 {d0[],d2[],d4[]},[r2]! + vld3.32 {d0[],d2[],d4[]},[r2],12 + vld3.32 {d0[],d2[],d4[]},[r2],r3 + + vld3.8 {d0,d1,d2},[r2] + vld3.8 {d0,d1,d2},[r2]! + vld3.8 {d0,d1,d2},[r2],24 + vld3.8 {d0,d1,d2},[r2],r3 + vld3.8 {d0,d1,d2},[r2@64] + vld3.8 {d0,d1,d2},[r2@64]! + vld3.8 {d0,d1,d2},[r2@64],24 + vld3.8 {d0,d1,d2},[r2@64],r3 + vld3.8 {d0,d2,d4},[r3] + vld3.8 {d0,d2,d4},[r3]! + vld3.8 {d0,d2,d4},[r3],24 + vld3.8 {d0,d2,d4},[r3],r4 + vld3.8 {d0,d2,d4},[r3@64] + vld3.8 {d0,d2,d4},[r3@64]! + vld3.8 {d0,d2,d4},[r3@64],24 + vld3.8 {d0,d2,d4},[r3@64],r4 + vld3.8 {d0[1],d1[1],d2[1]},[r2] + vld3.8 {d0[1],d1[1],d2[1]},[r2]! + vld3.8 {d0[1],d1[1],d2[1]},[r2],3 + vld3.8 {d0[1],d1[1],d2[1]},[r2],r3 + vld3.8 {d0[],d1[],d2[]},[r2] + vld3.8 {d0[],d1[],d2[]},[r2]! + vld3.8 {d0[],d1[],d2[]},[r2],3 + vld3.8 {d0[],d1[],d2[]},[r2],r3 + vld3.8 {d0[],d2[],d4[]},[r2] + vld3.8 {d0[],d2[],d4[]},[r2]! + vld3.8 {d0[],d2[],d4[]},[r2],3 + vld3.8 {d0[],d2[],d4[]},[r2],r3 + + vld4.16 {d0,d1,d2,d3},[r4] + vld4.16 {d0,d1,d2,d3},[r4]! + vld4.16 {d0,d1,d2,d3},[r4],32 + vld4.16 {d0,d1,d2,d3},[r4],r5 + vld4.16 {d0,d1,d2,d3},[r4@64] + vld4.16 {d0,d1,d2,d3},[r4@64]! + vld4.16 {d0,d1,d2,d3},[r4@64],32 + vld4.16 {d0,d1,d2,d3},[r4@64],r5 + vld4.16 {d0,d2,d4,d6},[r4] + vld4.16 {d0,d2,d4,d6},[r4]! + vld4.16 {d0,d2,d4,d6},[r4],32 + vld4.16 {d0,d2,d4,d6},[r4],r5 + vld4.16 {d0,d2,d4,d6},[r4@64] + vld4.16 {d0,d2,d4,d6},[r4@64]! + vld4.16 {d0,d2,d4,d6},[r4@64],32 + vld4.16 {d0,d2,d4,d6},[r4@64],r5 + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2] + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],8 + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64] + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]! + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],8 + vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3 + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2] + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]! + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],8 + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],r3 + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64] + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]! + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],8 + vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3 + vld4.16 {d0[],d1[],d2[],d3[]},[r2] + vld4.16 {d0[],d1[],d2[],d3[]},[r2]! + vld4.16 {d0[],d1[],d2[],d3[]},[r2],8 + vld4.16 {d0[],d1[],d2[],d3[]},[r2],r3 + vld4.16 {d0[],d1[],d2[],d3[]},[r2@64] + vld4.16 {d0[],d1[],d2[],d3[]},[r2@64]! + vld4.16 {d0[],d1[],d2[],d3[]},[r2@64],8 + vld4.16 {d0[],d1[],d2[],d3[]},[r2@64],r3 + vld4.16 {d0[],d2[],d4[],d6[]},[r2] + vld4.16 {d0[],d2[],d4[],d6[]},[r2]! + vld4.16 {d0[],d2[],d4[],d6[]},[r2],8 + vld4.16 {d0[],d2[],d4[],d6[]},[r2],r3 + vld4.16 {d0[],d2[],d4[],d6[]},[r2@64] + vld4.16 {d0[],d2[],d4[],d6[]},[r2@64]! + vld4.16 {d0[],d2[],d4[],d6[]},[r2@64],8 + vld4.16 {d0[],d2[],d4[],d6[]},[r2@64],r3 + + vld4.32 {d0,d1,d2,d3},[r4] + vld4.32 {d0,d1,d2,d3},[r4]! + vld4.32 {d0,d1,d2,d3},[r4],32 + vld4.32 {d0,d1,d2,d3},[r4],r5 + vld4.32 {d0,d1,d2,d3},[r4@64] + vld4.32 {d0,d1,d2,d3},[r4@64]! + vld4.32 {d0,d1,d2,d3},[r4@64],32 + vld4.32 {d0,d1,d2,d3},[r4@64],r5 + vld4.32 {d0,d2,d4,d6},[r4] + vld4.32 {d0,d2,d4,d6},[r4]! + vld4.32 {d0,d2,d4,d6},[r4],32 + vld4.32 {d0,d2,d4,d6},[r4],r5 + vld4.32 {d0,d2,d4,d6},[r4@64] + vld4.32 {d0,d2,d4,d6},[r4@64]! + vld4.32 {d0,d2,d4,d6},[r4@64],32 + vld4.32 {d0,d2,d4,d6},[r4@64],r5 + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2] + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],16 + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64] + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]! + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],16 + vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3 + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2] + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]! + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],16 + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],r3 + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64] + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]! + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],16 + vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3 + vld4.32 {d0[],d1[],d2[],d3[]},[r2] + vld4.32 {d0[],d1[],d2[],d3[]},[r2]! + vld4.32 {d0[],d1[],d2[],d3[]},[r2],16 + vld4.32 {d0[],d1[],d2[],d3[]},[r2],r3 + vld4.32 {d0[],d1[],d2[],d3[]},[r2@64] + vld4.32 {d0[],d1[],d2[],d3[]},[r2@64]! + vld4.32 {d0[],d1[],d2[],d3[]},[r2@64],16 + vld4.32 {d0[],d1[],d2[],d3[]},[r2@64],r3 + vld4.32 {d0[],d2[],d4[],d6[]},[r2] + vld4.32 {d0[],d2[],d4[],d6[]},[r2]! + vld4.32 {d0[],d2[],d4[],d6[]},[r2],16 + vld4.32 {d0[],d2[],d4[],d6[]},[r2],r3 + vld4.32 {d0[],d2[],d4[],d6[]},[r2@64] + vld4.32 {d0[],d2[],d4[],d6[]},[r2@64]! + vld4.32 {d0[],d2[],d4[],d6[]},[r2@64],16 + vld4.32 {d0[],d2[],d4[],d6[]},[r2@64],r3 + + vld4.8 {d0,d1,d2,d3},[r4] + vld4.8 {d0,d1,d2,d3},[r4]! + vld4.8 {d0,d1,d2,d3},[r4],32 + vld4.8 {d0,d1,d2,d3},[r4],r5 + vld4.8 {d0,d1,d2,d3},[r4@64] + vld4.8 {d0,d1,d2,d3},[r4@64]! + vld4.8 {d0,d1,d2,d3},[r4@64],32 + vld4.8 {d0,d1,d2,d3},[r4@64],r5 + vld4.8 {d0,d2,d4,d6},[r4] + vld4.8 {d0,d2,d4,d6},[r4]! + vld4.8 {d0,d2,d4,d6},[r4],32 + vld4.8 {d0,d2,d4,d6},[r4],r5 + vld4.8 {d0,d2,d4,d6},[r4@64] + vld4.8 {d0,d2,d4,d6},[r4@64]! + vld4.8 {d0,d2,d4,d6},[r4@64],32 + vld4.8 {d0,d2,d4,d6},[r4@64],r5 + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2] + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2],4 + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32] + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32]! + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32],4 + vld4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32],r3 + vld4.8 {d0[],d1[],d2[],d3[]},[r2] + vld4.8 {d0[],d1[],d2[],d3[]},[r2]! + vld4.8 {d0[],d1[],d2[],d3[]},[r2],4 + vld4.8 {d0[],d1[],d2[],d3[]},[r2],r3 + vld4.8 {d0[],d1[],d2[],d3[]},[r2@32] + vld4.8 {d0[],d1[],d2[],d3[]},[r2@32]! + vld4.8 {d0[],d1[],d2[],d3[]},[r2@32],4 + vld4.8 {d0[],d1[],d2[],d3[]},[r2@32],r3 + vld4.8 {d0[],d2[],d4[],d6[]},[r2] + vld4.8 {d0[],d2[],d4[],d6[]},[r2]! + vld4.8 {d0[],d2[],d4[],d6[]},[r2],4 + vld4.8 {d0[],d2[],d4[],d6[]},[r2],r3 + vld4.8 {d0[],d2[],d4[],d6[]},[r2@32] + vld4.8 {d0[],d2[],d4[],d6[]},[r2@32]! + vld4.8 {d0[],d2[],d4[],d6[]},[r2@32],4 + vld4.8 {d0[],d2[],d4[],d6[]},[r2@32],r3 + + vmax.s16 d0,d1 + vmax.s16 d0,d1,d2 + vmax.s16 q0,q1 + vmax.s16 q0,q1,q2 + + vmax.s32 d0,d1 + vmax.s32 d0,d1,d2 + vmax.s32 q0,q1 + vmax.s32 q0,q1,q2 + + vmax.s8 d0,d1 + vmax.s8 d0,d1,d2 + vmax.s8 q0,q1 + vmax.s8 q0,q1,q2 + + vmax.u16 d0,d1 + vmax.u16 d0,d1,d2 + vmax.u16 q0,q1 + vmax.u16 q0,q1,q2 + + vmax.u32 d0,d1 + vmax.u32 d0,d1,d2 + vmax.u32 q0,q1 + vmax.u32 q0,q1,q2 + + vmax.u8 d0,d1 + vmax.u8 d0,d1,d2 + vmax.u8 q0,q1 + vmax.u8 q0,q1,q2 + + vmin.s16 d0,d1 + vmin.s16 d0,d1,d2 + vmin.s16 q0,q1 + vmin.s16 q0,q1,q2 + + vmin.s32 d0,d1 + vmin.s32 d0,d1,d2 + vmin.s32 q0,q1 + vmin.s32 q0,q1,q2 + + vmin.s8 d0,d1 + vmin.s8 d0,d1,d2 + vmin.s8 q0,q1 + vmin.s8 q0,q1,q2 + + vmin.u16 d0,d1 + vmin.u16 d0,d1,d2 + vmin.u16 q0,q1 + vmin.u16 q0,q1,q2 + + vmin.u32 d0,d1 + vmin.u32 d0,d1,d2 + vmin.u32 q0,q1 + vmin.u32 q0,q1,q2 + + vmin.u8 d0,d1 + vmin.u8 d0,d1,d2 + vmin.u8 q0,q1 + vmin.u8 q0,q1,q2 + + vmla.i16 d0,d1,d2 + vmla.i16 d0,d1,d2[0] + vmla.i16 q0,q1,q2 + vmla.i16 q0,q1,d2[1] + + vmla.i32 d0,d1,d2 + vmla.i32 d0,d1,d2[0] + vmla.i32 q0,q1,q2 + vmla.i32 q0,q1,d2[1] + + vmla.i8 d0,d1,d2 + vmla.i8 q0,q1,q2 + + vmla.s16 d0,d1,d2 + vmla.s16 q0,q1,q2 + + vmla.s32 d0,d1,d2 + vmla.s32 q0,q1,q2 + + vmla.s8 d0,d1,d2 + vmla.s8 q0,q1,q2 + + vmla.u16 d0,d1,d2 + vmla.u16 q0,q1,q2 + + vmla.u32 d0,d1,d2 + vmla.u32 q0,q1,q2 + + vmla.u8 d0,d1,d2 + vmla.u8 q0,q1,q2 + + vmlal.s16 q0,d1,d2 + vmlal.s16 q0,d1,d2[0] + + vmlal.s32 q0,d1,d2 + vmlal.s32 q0,d1,d2[0] + + vmlal.s8 q0,d1,d2 + + vmlal.u16 q0,d1,d2 + vmlal.u16 q0,d1,d2[1] + + vmlal.u32 q0,d1,d2 + vmlal.u32 q0,d1,d2[0] + + vmlal.u8 q0,d1,d2 + + vmls.i16 d0,d1,d2 + vmls.i16 d0,d1,d2[0] + vmls.i16 q0,q1,q2 + vmls.i16 q0,q1,d2[1] + + vmls.i32 d0,d1,d2 + vmls.i32 d0,d1,d2[0] + vmls.i32 q0,q1,q2 + vmls.i32 q0,q1,d2[1] + + vmls.i8 d0,d1,d2 + vmls.i8 q0,q1,q2 + + vmls.s16 d0,d1,d2 + vmls.s16 q0,q1,q2 + + vmls.s32 d0,d1,d2 + vmls.s32 q0,q1,q2 + + vmls.s8 d0,d1,d2 + vmls.s8 q0,q1,q2 + + vmls.u16 d0,d1,d2 + vmls.u16 q0,q1,q2 + + vmls.u32 d0,d1,d2 + vmls.u32 q0,q1,q2 + + vmls.u8 d0,d1,d2 + vmls.u8 q0,q1,q2 + + vmlsl.s16 q0,d1,d2 + vmlsl.s16 q0,d1,d2[1] + + vmlsl.s32 q0,d1,d2 + vmlsl.s32 q0,d1,d2[0] + + vmlsl.s8 q0,d1,d2 + + vmlsl.u16 q0,d1,d2 + vmlsl.u16 q0,d1,d2[1] + + vmlsl.u32 q0,d1,d2 + vmlsl.u32 q0,d1,d2[0] + + vmlsl.u8 q0,d1,d2 + + vmov d0,d1 + vmov q0,q1 + + vmov.16 d0[1],r1 + + vmov.8 d0[1],r1 + + vmov.i16 d0,1 + vmov.i16 q0,1 + + vmov.i32 d0,1 + vmov.i32 q0,1 + + vmov.i64 d0,1 + vmov.i64 q0,1 + + vmov.i8 d0,1 + vmov.i8 q0,1 + + vmov.s16 r0,d1[1] + + vmov.s8 r0,d1[1] + + vmov.u16 r0,d1[1] + + vmov.u8 r0,d1[1] + + vmovl.s16 q0,d1 + + vmovl.s32 q0,d1 + + vmovl.s8 q0,d1 + + vmovl.u16 q0,d1 + + vmovl.u32 q0,d1 + + vmovl.u8 q0,d1 + + vmovn.i16 d0,q1 + + vmovn.i32 d0,q1 + + vmovn.i8 d0,q1 + + vmul.i16 d0,d1 + vmul.i16 d0,d1,d2 + vmul.i16 d0,d1[1] + vmul.i16 d0,d1,d2[1] + vmul.i16 q0,q1 + vmul.i16 q0,q1,q2 + vmul.i16 q0,d1[1] + vmul.i16 q0,q1,d2[1] + + vmul.i32 d0,d1 + vmul.i32 d0,d1,d2 + vmul.i32 d0,d1[0] + vmul.i32 d0,d1,d2[0] + vmul.i32 q0,q1 + vmul.i32 q0,q1,q2 + vmul.i32 q0,d1[0] + vmul.i32 q0,q1,d2[0] + + vmul.i8 d0,d1 + vmul.i8 d0,d1,d2 + vmul.i8 q0,q1 + vmul.i8 q0,q1,q2 + + vmul.p8 d0,d1 + vmul.p8 d0,d1,d2 + + vmul.s16 d0,d1 + vmul.s16 d0,d1,d2 + + vmul.s32 d0,d1 + vmul.s32 d0,d1,d2 + + vmul.s8 d0,d1 + vmul.s8 d0,d1,d2 + vmul.s8 q0,q1 + vmul.s8 q0,q1,q2 + + vmul.u16 d0,d1 + vmul.u16 d0,d1,d2 + + vmul.u32 d0,d1 + vmul.u32 d0,d1,d2 + + vmul.u8 d0,d1 + vmul.u8 d0,d1,d2 + vmul.u8 q0,q1 + vmul.u8 q0,q1,q2 + + vmull.p8 q0,d1,d2 + + vmull.s16 q0,d1,d2 + vmull.s16 q0,d1,d2[0] + + vmull.s32 q0,d1,d2 + vmull.s32 q0,d1,d2[0] + + vmull.s8 q0,d1,d2 + + vmull.u16 q0,d1,d2 + vmull.u16 q0,d1,d2[1] + + vmull.u32 q0,d1,d2 + vmull.u32 q0,d1,d2[0] + + vmull.u8 q0,d1,d2 + + vmvn d0,d1 + vmvn q0,q1 + + vmvn.i16 d0,1 + vmvn.i16 q0,1 + + vmvn.i32 d0,1 + vmvn.i32 q0,1 + + vneg.s16 d0,d1 + vneg.s16 q0,q1 + + vneg.s32 d0,d1 + vneg.s32 q0,q1 + + vneg.s8 d0,d1 + vneg.s8 q0,q1 + + vorn d0,d1 + vorn d0,d1,d2 + vorn q0,q1 + vorn q0,q1,q2 + + vorn.i16 d0,not 1 + vorn.i16 q0,0xfffe + + vorn.i32 d0,not 1 + vorn.i32 q0,not 1 + + vorr d0,d1 + vorr d0,d1,d2 + vorr q0,q1 + vorr q0,q1,q2 + + vorr.i16 d0,1 + vorr.i16 q0,not -2 + + vorr.i32 d0,1 + vorr.i32 q0,1 + + vpadal.s16 d0,d1 + vpadal.s16 q0,q1 + + vpadal.s32 d0,d1 + vpadal.s32 q0,q1 + + vpadal.s8 d0,d1 + vpadal.s8 q0,q1 + + vpadal.u16 d0,d1 + vpadal.u16 q0,q1 + + vpadal.u32 d0,d1 + vpadal.u32 q0,q1 + + vpadal.u8 d0,d1 + vpadal.u8 q0,q1 + + vpadd.i16 d0,d1 + vpadd.i16 d0,d1,d2 + + vpadd.i32 d0,d1 + vpadd.i32 d0,d1,d2 + + vpadd.i8 d0,d1 + vpadd.i8 d0,d1,d2 + + vpaddl.s16 d0,d1 + vpaddl.s16 q0,q1 + + vpaddl.s32 d0,d1 + vpaddl.s32 q0,q1 + + vpaddl.s8 d0,d1 + vpaddl.s8 q0,q1 + + vpaddl.u16 d0,d1 + vpaddl.u16 q0,q1 + + vpaddl.u32 d0,d1 + vpaddl.u32 q0,q1 + + vpaddl.u8 d0,d1 + vpaddl.u8 q0,q1 + + vpmax.s16 d0,d1 + vpmax.s16 d0,d1,d2 + + vpmax.s32 d0,d1 + vpmax.s32 d0,d1,d2 + + vpmax.s8 d0,d1 + vpmax.s8 d0,d1,d2 + + vpmax.u16 d0,d1 + vpmax.u16 d0,d1,d2 + + vpmax.u32 d0,d1 + vpmax.u32 d0,d1,d2 + + vpmax.u8 d0,d1 + vpmax.u8 d0,d1,d2 + + vpmin.s16 d0,d1 + vpmin.s16 d0,d1,d2 + + vpmin.s32 d0,d1 + vpmin.s32 d0,d1,d2 + + vpmin.s8 d0,d1 + vpmin.s8 d0,d1,d2 + + vpmin.u16 d0,d1 + vpmin.u16 d0,d1,d2 + + vpmin.u32 d0,d1 + vpmin.u32 d0,d1,d2 + + vpmin.u8 d0,d1 + vpmin.u8 d0,d1,d2 + + vqabs.s16 d0,d1 + vqabs.s16 q0,q1 + + vqabs.s32 d0,d1 + vqabs.s32 q0,q1 + + vqabs.s8 d0,d1 + vqabs.s8 q0,q1 + + vqadd.s16 d0,d1 + vqadd.s16 d0,d1,d2 + vqadd.s16 q0,q1 + vqadd.s16 q0,q1,q2 + + vqadd.s32 d0,d1 + vqadd.s32 d0,d1,d2 + vqadd.s32 q0,q1 + vqadd.s32 q0,q1,q2 + + vqadd.s64 d0,d1 + vqadd.s64 d0,d1,d2 + vqadd.s64 q0,q1 + vqadd.s64 q0,q1,q2 + + vqadd.s8 d0,d1 + vqadd.s8 d0,d1,d2 + vqadd.s8 q0,q1 + vqadd.s8 q0,q1,q2 + + vqadd.u16 d0,d1 + vqadd.u16 d0,d1,d2 + vqadd.u16 q0,q1 + vqadd.u16 q0,q1,q2 + + vqadd.u32 d0,d1 + vqadd.u32 d0,d1,d2 + vqadd.u32 q0,q1 + vqadd.u32 q0,q1,q2 + + vqadd.u64 d0,d1 + vqadd.u64 d0,d1,d2 + vqadd.u64 q0,q1 + vqadd.u64 q0,q1,q2 + + vqadd.u8 d0,d1 + vqadd.u8 d0,d1,d2 + vqadd.u8 q0,q1 + vqadd.u8 q0,q1,q2 + + vqdmlal.s16 q0,d1,d2 + vqdmlal.s16 q0,d1,d2[0] + + vqdmlal.s32 q0,d1,d2 + vqdmlal.s32 q0,d1,d2[0] + + vqdmlsl.s16 q0,d1,d2 + vqdmlsl.s16 q0,d1,d2[0] + + vqdmlsl.s32 q0,d1,d2 + vqdmlsl.s32 q0,d1,d2[0] + + vqdmulh.s16 d0,d1 + vqdmulh.s16 d0,d1,d2 + vqdmulh.s16 d0,d1[1] + vqdmulh.s16 d0,d1,d2[1] + vqdmulh.s16 q0,q1 + vqdmulh.s16 q0,q1,q2 + vqdmulh.s16 q0,d1[1] + vqdmulh.s16 q0,q1,d2[1] + + vqdmulh.s32 d0,d1 + vqdmulh.s32 d0,d1,d2 + vqdmulh.s32 d0,d1[0] + vqdmulh.s32 d0,d1,d2[0] + vqdmulh.s32 q0,q1 + vqdmulh.s32 q0,q1,q2 + vqdmulh.s32 q0,d1[0] + vqdmulh.s32 q0,q1,d2[0] + + vqdmull.s16 q0,d1,d2 + vqdmull.s16 q0,d1,d2[0] + + vqdmull.s32 q0,d1,d2 + vqdmull.s32 q0,d1,d2[0] + + vqmovn.s16 d0,q1 + + vqmovn.s32 d0,q1 + + vqmovn.s64 d0,q1 + + vqmovn.u16 d0,q1 + + vqmovn.u32 d0,q1 + + vqmovn.u64 d0,q1 + + vqmovun.s16 d0,q1 + + vqmovun.s32 d0,q1 + + vqmovun.s64 d0,q1 + + vqneg.s16 d0,d1 + vqneg.s16 q0,q1 + + vqneg.s32 d0,d1 + vqneg.s32 q0,q1 + + vqneg.s8 d0,d1 + vqneg.s8 q0,q1 + + vqrdmulh.s16 d0,d1 + vqrdmulh.s16 d0,d1,d2 + vqrdmulh.s16 d0,d1[1] + vqrdmulh.s16 d0,d1,d2[1] + vqrdmulh.s16 q0,q1 + vqrdmulh.s16 q0,q1,q2 + vqrdmulh.s16 q0,d1[1] + vqrdmulh.s16 q0,q1,d2[1] + + vqrdmulh.s32 d0,d1 + vqrdmulh.s32 d0,d1,d2 + vqrdmulh.s32 d0,d1[0] + vqrdmulh.s32 d0,d1,d2[0] + vqrdmulh.s32 q0,q1 + vqrdmulh.s32 q0,q1,q2 + vqrdmulh.s32 q0,d1[0] + vqrdmulh.s32 q0,q1,d1[0] + + vqrshl.s16 d0,d1 + vqrshl.s16 d0,d1,d2 + vqrshl.s16 q0,q1 + vqrshl.s16 q0,q1,q2 + + vqrshl.s32 d0,d1 + vqrshl.s32 d0,d1,d2 + vqrshl.s32 q0,q1 + vqrshl.s32 q0,q1,q2 + + vqrshl.s64 d0,d1 + vqrshl.s64 d0,d1,d2 + vqrshl.s64 q0,q1 + vqrshl.s64 q0,q1,q2 + + vqrshl.s8 d0,d1 + vqrshl.s8 d0,d1,d2 + vqrshl.s8 q0,q1 + vqrshl.s8 q0,q1,q2 + + vqrshl.u16 d0,d1 + vqrshl.u16 d0,d1,d2 + vqrshl.u16 q0,q1 + vqrshl.u16 q0,q1,q2 + + vqrshl.u32 d0,d1 + vqrshl.u32 d0,d1,d2 + vqrshl.u32 q0,q1 + vqrshl.u32 q0,q1,q2 + + vqrshl.u64 d0,d1 + vqrshl.u64 d0,d1,d2 + vqrshl.u64 q0,q1 + vqrshl.u64 q0,q1,q2 + + vqrshl.u8 d0,d1 + vqrshl.u8 d0,d1,d2 + vqrshl.u8 q0,q1 + vqrshl.u8 q0,q1,q2 + + vqrshrn.s16 d0,q1,1 + + vqrshrn.s32 d0,q1,1 + + vqrshrn.s64 d0,q1,1 + + vqrshrn.u16 d0,q1,1 + + vqrshrn.u32 d0,q1,1 + + vqrshrn.u64 d0,q1,1 + + vqrshrun.s16 d0,q1,1 + + vqrshrun.s32 d0,q1,1 + + vqrshrun.s64 d0,q1,1 + + vqshl.s16 d0,1 + vqshl.s16 d0,d1 + vqshl.s16 d0,d1,1 + vqshl.s16 d0,d1,d2 + vqshl.s16 q0,1 + vqshl.s16 q0,q1 + vqshl.s16 q0,q1,1 + vqshl.s16 q0,q1,q2 + + vqshl.s32 d0,1 + vqshl.s32 d0,d1 + vqshl.s32 d0,d1,1 + vqshl.s32 d0,d1,d2 + vqshl.s32 q0,1 + vqshl.s32 q0,q1 + vqshl.s32 q0,q1,1 + vqshl.s32 q0,q1,q2 + + vqshl.s64 d0,1 + vqshl.s64 d0,d1 + vqshl.s64 d0,d1,1 + vqshl.s64 d0,d1,d2 + vqshl.s64 q0,1 + vqshl.s64 q0,q1 + vqshl.s64 q0,q1,1 + vqshl.s64 q0,q1,q2 + + vqshl.s8 d0,1 + vqshl.s8 d0,d1 + vqshl.s8 d0,d1,1 + vqshl.s8 d0,d1,d2 + vqshl.s8 q0,1 + vqshl.s8 q0,q1 + vqshl.s8 q0,q1,1 + vqshl.s8 q0,q1,q2 + + vqshl.u16 d0,1 + vqshl.u16 d0,d1 + vqshl.u16 d0,d1,1 + vqshl.u16 d0,d1,d2 + vqshl.u16 q0,1 + vqshl.u16 q0,q1 + vqshl.u16 q0,q1,1 + vqshl.u16 q0,q1,q2 + + vqshl.u32 d0,1 + vqshl.u32 d0,d1 + vqshl.u32 d0,d1,1 + vqshl.u32 d0,d1,d2 + vqshl.u32 q0,1 + vqshl.u32 q0,q1 + vqshl.u32 q0,q1,1 + vqshl.u32 q0,q1,q2 + + vqshl.u64 d0,1 + vqshl.u64 d0,d1 + vqshl.u64 d0,d1,1 + vqshl.u64 d0,d1,d2 + vqshl.u64 q0,1 + vqshl.u64 q0,q1 + vqshl.u64 q0,q1,1 + vqshl.u64 q0,q1,q2 + + vqshl.u8 d0,1 + vqshl.u8 d0,d1 + vqshl.u8 d0,d1,1 + vqshl.u8 d0,d1,d2 + vqshl.u8 q0,1 + vqshl.u8 q0,q1 + vqshl.u8 q0,q1,1 + vqshl.u8 q0,q1,q2 + + vqshlu.s16 d0,1 + vqshlu.s16 d0,d1,1 + vqshlu.s16 q0,1 + vqshlu.s16 q0,q1,1 + + vqshlu.s32 d0,1 + vqshlu.s32 d0,d1,1 + vqshlu.s32 q0,1 + vqshlu.s32 q0,q1,1 + + vqshlu.s64 d0,1 + vqshlu.s64 d0,d1,1 + vqshlu.s64 q0,1 + vqshlu.s64 q0,q1,1 + + vqshlu.s8 d0,1 + vqshlu.s8 d0,d1,1 + vqshlu.s8 q0,1 + vqshlu.s8 q0,q1,1 + + vqshrn.s16 d0,q1,1 + + vqshrn.s32 d0,q1,1 + + vqshrn.s64 d0,q1,1 + + vqshrn.u16 d0,q1,1 + + vqshrn.u32 d0,q1,1 + + vqshrn.u64 d0,q1,1 + + vqshrun.s16 d0,q1,1 + + vqshrun.s32 d0,q1,1 + + vqshrun.s64 d0,q1,1 + + vqsub.s16 d0,d1 + vqsub.s16 d0,d1,d2 + vqsub.s16 q0,q1 + vqsub.s16 q0,q1,q2 + + vqsub.s32 d0,d1 + vqsub.s32 d0,d1,d2 + vqsub.s32 q0,q1 + vqsub.s32 q0,q1,q2 + + vqsub.s64 d0,d1 + vqsub.s64 d0,d1,d2 + vqsub.s64 q0,q1 + vqsub.s64 q0,q1,q2 + + vqsub.s8 d0,d1 + vqsub.s8 d0,d1,d2 + vqsub.s8 q0,q1 + vqsub.s8 q0,q1,q2 + + vqsub.u16 d0,d1 + vqsub.u16 d0,d1,d2 + vqsub.u16 q0,q1 + vqsub.u16 q0,q1,q2 + + vqsub.u32 d0,d1 + vqsub.u32 d0,d1,d2 + vqsub.u32 q0,q1 + vqsub.u32 q0,q1,q2 + + vqsub.u64 d0,d1 + vqsub.u64 d0,d1,d2 + vqsub.u64 q0,q1 + vqsub.u64 q0,q1,q2 + + vqsub.u8 d0,d1 + vqsub.u8 d0,d1,d2 + vqsub.u8 q0,q1 + vqsub.u8 q0,q1,q2 + + vraddhn.i16 d0,q1,q2 + + vraddhn.i32 d0,q1,q2 + + vraddhn.i64 d0,q1,q2 + + vrecpe.u32 d0,d1 + vrecpe.u32 q0,q1 + + vrev16.8 d0,d1 + vrev16.8 q0,q1 + + vrev32.16 d0,d1 + vrev32.16 q0,q1 + + vrev32.8 d0,d1 + vrev32.8 q0,q1 + + vrev64.16 d0,d1 + vrev64.16 q0,q1 + + vrev64.32 d0,d1 + vrev64.32 q0,q1 + + vrev64.8 d0,d1 + vrev64.8 q0,q1 + + vrhadd.s16 d0,d1 + vrhadd.s16 d0,d1,d2 + vrhadd.s16 q0,q1 + vrhadd.s16 q0,q1,q2 + + vrhadd.s32 d0,d1 + vrhadd.s32 d0,d1,d2 + vrhadd.s32 q0,q1 + vrhadd.s32 q0,q1,q2 + + vrhadd.s8 d0,d1 + vrhadd.s8 d0,d1,d2 + vrhadd.s8 q0,q1 + vrhadd.s8 q0,q1,q2 + + vrhadd.u16 d0,d1 + vrhadd.u16 d0,d1,d2 + vrhadd.u16 q0,q1 + vrhadd.u16 q0,q1,q2 + + vrhadd.u32 d0,d1 + vrhadd.u32 d0,d1,d2 + vrhadd.u32 q0,q1 + vrhadd.u32 q0,q1,q2 + + vrhadd.u8 d0,d1 + vrhadd.u8 d0,d1,d2 + vrhadd.u8 q0,q1 + vrhadd.u8 q0,q1,q2 + + vrshl.s16 d0,d1 + vrshl.s16 d0,d1,d2 + vrshl.s16 q0,q1 + vrshl.s16 q0,q1,q2 + + vrshl.s32 d0,d1 + vrshl.s32 d0,d1,d2 + vrshl.s32 q0,q1 + vrshl.s32 q0,q1,q2 + + vrshl.s64 d0,d1 + vrshl.s64 d0,d1,d2 + vrshl.s64 q0,q1 + vrshl.s64 q0,q1,q2 + + vrshl.s8 d0,d1 + vrshl.s8 d0,d1,d2 + vrshl.s8 q0,q1 + vrshl.s8 q0,q1,q2 + + vrshl.u16 d0,d1 + vrshl.u16 d0,d1,d2 + vrshl.u16 q0,q1 + vrshl.u16 q0,q1,q2 + + vrshl.u32 d0,d1 + vrshl.u32 d0,d1,d2 + vrshl.u32 q0,q1 + vrshl.u32 q0,q1,q2 + + vrshl.u64 d0,d1 + vrshl.u64 d0,d1,d2 + vrshl.u64 q0,q1 + vrshl.u64 q0,q1,q2 + + vrshl.u8 d0,d1 + vrshl.u8 d0,d1,d2 + vrshl.u8 q0,q1 + vrshl.u8 q0,q1,q2 + + vrshr.s16 d0,1 + vrshr.s16 d0,d1,1 + vrshr.s16 q0,1 + vrshr.s16 q0,q1,1 + + vrshr.s32 d0,1 + vrshr.s32 d0,d1,1 + vrshr.s32 q0,1 + vrshr.s32 q0,q1,1 + + vrshr.s64 d0,1 + vrshr.s64 d0,d1,1 + vrshr.s64 q0,1 + vrshr.s64 q0,q1,1 + + vrshr.s8 d0,1 + vrshr.s8 d0,d1,1 + vrshr.s8 q0,1 + vrshr.s8 q0,q1,1 + + vrshr.u16 d0,1 + vrshr.u16 d0,d1,1 + vrshr.u16 q0,1 + vrshr.u16 q0,q1,1 + + vrshr.u32 d0,1 + vrshr.u32 d0,d1,1 + vrshr.u32 q0,1 + vrshr.u32 q0,q1,1 + + vrshr.u64 d0,1 + vrshr.u64 d0,d1,1 + vrshr.u64 q0,1 + vrshr.u64 q0,q1,1 + + vrshr.u8 d0,1 + vrshr.u8 d0,d1,1 + vrshr.u8 q0,1 + vrshr.u8 q0,q1,1 + + vrshrn.i16 d0,q1,1 + + vrshrn.i32 d0,q1,1 + + vrshrn.i64 d0,q1,1 + + vrsqrte.u32 d0,d1 + vrsqrte.u32 q0,q1 + + vrsra.s16 d0,1 + vrsra.s16 d0,d1,1 + vrsra.s16 q0,1 + vrsra.s16 q0,q1,1 + + vrsra.s32 d0,1 + vrsra.s32 d0,d1,1 + vrsra.s32 q0,1 + vrsra.s32 q0,q1,1 + + vrsra.s64 d0,1 + vrsra.s64 d0,d1,1 + vrsra.s64 q0,1 + vrsra.s64 q0,q1,1 + + vrsra.s8 d0,1 + vrsra.s8 d0,d1,1 + vrsra.s8 q0,1 + vrsra.s8 q0,q1,1 + + vrsra.u16 d0,1 + vrsra.u16 d0,d1,1 + vrsra.u16 q0,1 + vrsra.u16 q0,q1,1 + + vrsra.u32 d0,1 + vrsra.u32 d0,d1,1 + vrsra.u32 q0,1 + vrsra.u32 q0,q1,1 + + vrsra.u64 d0,1 + vrsra.u64 d0,d1,1 + vrsra.u64 q0,1 + vrsra.u64 q0,q1,1 + + vrsra.u8 d0,1 + vrsra.u8 d0,d1,1 + vrsra.u8 q0,1 + vrsra.u8 q0,q1,1 + + vrsubhn.i16 d0,q1,q2 + + vrsubhn.i32 d0,q1,q2 + + vrsubhn.i64 d0,q1,q2 + + vshl.i16 d0,1 + vshl.i16 d0,d1,1 + vshl.i16 q0,1 + vshl.i16 q0,q1,1 + + vshl.i32 d0,1 + vshl.i32 d0,d1,1 + vshl.i32 q0,1 + vshl.i32 q0,q1,1 + + vshl.i64 d0,1 + vshl.i64 d0,d1,1 + vshl.i64 q0,1 + vshl.i64 q0,q1,1 + + vshl.i8 d0,1 + vshl.i8 d0,d1,1 + vshl.i8 q0,1 + vshl.i8 q0,q1,1 + + vshl.s16 d0,d1 + vshl.s16 d0,d1,d2 + vshl.s16 q0,q1 + vshl.s16 q0,q1,q2 + + vshl.s32 d0,d1 + vshl.s32 d0,d1,d2 + vshl.s32 q0,q1 + vshl.s32 q0,q1,q2 + + vshl.s64 d0,d1 + vshl.s64 d0,d1,d2 + vshl.s64 q0,q1 + vshl.s64 q0,q1,q2 + + vshl.s8 d0,d1 + vshl.s8 d0,d1,d2 + vshl.s8 q0,q1 + vshl.s8 q0,q1,q2 + + vshl.u16 d0,d1 + vshl.u16 d0,d1,d2 + vshl.u16 q0,q1 + vshl.u16 q0,q1,q2 + + vshl.u32 d0,d1 + vshl.u32 d0,d1,d2 + vshl.u32 q0,q1 + vshl.u32 q0,q1,q2 + + vshl.u64 d0,d1 + vshl.u64 d0,d1,d2 + vshl.u64 q0,q1 + vshl.u64 q0,q1,q2 + + vshl.u8 d0,d1 + vshl.u8 d0,d1,d2 + vshl.u8 q0,q1 + vshl.u8 q0,q1,q2 + + vshll.i16 q0,d1,16 + + vshll.i32 q0,d1,32 + + vshll.i8 q0,d1,8 + + vshll.s16 q0,d1,1 + vshll.s16 q0,d1,16 + + vshll.s32 q0,d1,1 + vshll.s32 q0,d1,32 + + vshll.s8 q0,d1,1 + vshll.s8 q0,d1,8 + + vshll.u16 q0,d1,1 + vshll.u16 q0,d1,16 + + vshll.u32 q0,d1,1 + vshll.u32 q0,d1,32 + + vshll.u8 q0,d1,1 + vshll.u8 q0,d1,8 + + vshr.s16 d0,1 + vshr.s16 d0,d1,1 + vshr.s16 q0,1 + vshr.s16 q0,q1,1 + + vshr.s32 d0,1 + vshr.s32 d0,d1,1 + vshr.s32 q0,1 + vshr.s32 q0,q1,1 + + vshr.s64 d0,1 + vshr.s64 d0,d1,1 + vshr.s64 q0,1 + vshr.s64 q0,q1,1 + + vshr.s8 d0,1 + vshr.s8 d0,d1,1 + vshr.s8 q0,1 + vshr.s8 q0,q1,1 + + vshr.u16 d0,1 + vshr.u16 d0,d1,1 + vshr.u16 q0,1 + vshr.u16 q0,q1,1 + + vshr.u32 d0,1 + vshr.u32 d0,d1,1 + vshr.u32 q0,1 + vshr.u32 q0,q1,1 + + vshr.u64 d0,1 + vshr.u64 d0,d1,1 + vshr.u64 q0,1 + vshr.u64 q0,q1,1 + + vshr.u8 d0,1 + vshr.u8 d0,d1,1 + vshr.u8 q0,1 + vshr.u8 q0,q1,1 + + vshrn.i16 d0,q1,1 + + vshrn.i32 d0,q1,1 + + vshrn.i64 d0,q1,1 + + vsli.16 d0,1 + vsli.16 d0,d1,1 + vsli.16 q0,1 + vsli.16 q0,q1,1 + + vsli.32 d0,1 + vsli.32 d0,d1,1 + vsli.32 q0,1 + vsli.32 q0,q1,1 + + vsli.64 d0,1 + vsli.64 d0,d1,1 + vsli.64 q0,1 + vsli.64 q0,q1,1 + + vsli.8 d0,1 + vsli.8 d0,d1,1 + vsli.8 q0,1 + vsli.8 q0,q1,1 + + vsra.s16 d0,1 + vsra.s16 d0,d1,1 + vsra.s16 q0,1 + vsra.s16 q0,q1,1 + + vsra.s32 d0,1 + vsra.s32 d0,d1,1 + vsra.s32 q0,1 + vsra.s32 q0,q1,1 + + vsra.s64 d0,1 + vsra.s64 d0,d1,1 + vsra.s64 q0,1 + vsra.s64 q0,q1,1 + + vsra.s8 d0,1 + vsra.s8 d0,d1,1 + vsra.s8 q0,1 + vsra.s8 q0,q1,1 + + vsra.u16 d0,1 + vsra.u16 d0,d1,1 + vsra.u16 q0,1 + vsra.u16 q0,q1,1 + + vsra.u32 d0,1 + vsra.u32 d0,d1,1 + vsra.u32 q0,1 + vsra.u32 q0,q1,1 + + vsra.u64 d0,1 + vsra.u64 d0,d1,1 + vsra.u64 q0,1 + vsra.u64 q0,q1,1 + + vsra.u8 d0,1 + vsra.u8 d0,d1,1 + vsra.u8 q0,1 + vsra.u8 q0,q1,1 + + vsri.16 d0,1 + vsri.16 d0,d1,1 + vsri.16 q0,1 + vsri.16 q0,q1,1 + + vsri.32 d0,1 + vsri.32 d0,d1,1 + vsri.32 q0,1 + vsri.32 q0,q1,1 + + vsri.64 d0,1 + vsri.64 d0,d1,1 + vsri.64 q0,1 + vsri.64 q0,q1,1 + + vsri.8 d0,1 + vsri.8 d0,d1,1 + vsri.8 q0,1 + vsri.8 q0,q1,1 + + vst1.16 {d0},[r1] + vst1.16 {d0},[r1]! + vst1.16 {d0},[r1],8 + vst1.16 {d0},[r1],r2 + vst1.16 {d0},[r1@64] + vst1.16 {d0},[r1@64]! + vst1.16 {d0},[r1@64],8 + vst1.16 {d0},[r1@64],r2 + vst1.16 {d0,d1},[r2] + vst1.16 {d0,d1},[r2]! + vst1.16 {d0,d1},[r2],16 + vst1.16 {d0,d1},[r2],r3 + vst1.16 {d0,d1},[r2@64] + vst1.16 {d0,d1},[r2@64]! + vst1.16 {d0,d1},[r2@64],16 + vst1.16 {d0,d1},[r2@64],r3 + vst1.16 {d0,d1,d2},[r3] + vst1.16 {d0,d1,d2},[r3]! + vst1.16 {d0,d1,d2},[r3],24 + vst1.16 {d0,d1,d2},[r3],r4 + vst1.16 {d0,d1,d2},[r3@64] + vst1.16 {d0,d1,d2},[r3@64]! + vst1.16 {d0,d1,d2},[r3@64],24 + vst1.16 {d0,d1,d2},[r3@64],r4 + vst1.16 {d0,d1,d2,d3},[r4] + vst1.16 {d0,d1,d2,d3},[r4]! + vst1.16 {d0,d1,d2,d3},[r4],32 + vst1.16 {d0,d1,d2,d3},[r4],r5 + vst1.16 {d0,d1,d2,d3},[r4@64] + vst1.16 {d0,d1,d2,d3},[r4@64]! + vst1.16 {d0,d1,d2,d3},[r4@64],32 + vst1.16 {d0,d1,d2,d3},[r4@64],r5 + vst1.16 {d0[1]},[r2] + vst1.16 {d0[1]},[r2]! + vst1.16 {d0[1]},[r2],2 + vst1.16 {d0[1]},[r2],r3 + vst1.16 {d0[1]},[r2@16] + vst1.16 {d0[1]},[r2@16]! + vst1.16 {d0[1]},[r2@16],2 + vst1.16 {d0[1]},[r2@16],r3 + + vst1.32 {d0},[r1] + vst1.32 {d0},[r1]! + vst1.32 {d0},[r1],8 + vst1.32 {d0},[r1],r2 + vst1.32 {d0},[r1@64] + vst1.32 {d0},[r1@64]! + vst1.32 {d0},[r1@64],8 + vst1.32 {d0},[r1@64],r2 + vst1.32 {d0,d1},[r2] + vst1.32 {d0,d1},[r2]! + vst1.32 {d0,d1},[r2],16 + vst1.32 {d0,d1},[r2],r3 + vst1.32 {d0,d1},[r2@64] + vst1.32 {d0,d1},[r2@64]! + vst1.32 {d0,d1},[r2@64],16 + vst1.32 {d0,d1},[r2@64],r3 + vst1.32 {d0,d1,d2},[r3] + vst1.32 {d0,d1,d2},[r3]! + vst1.32 {d0,d1,d2},[r3],24 + vst1.32 {d0,d1,d2},[r3],r4 + vst1.32 {d0,d1,d2},[r3@64] + vst1.32 {d0,d1,d2},[r3@64]! + vst1.32 {d0,d1,d2},[r3@64],24 + vst1.32 {d0,d1,d2},[r3@64],r4 + vst1.32 {d0,d1,d2,d3},[r4] + vst1.32 {d0,d1,d2,d3},[r4]! + vst1.32 {d0,d1,d2,d3},[r4],32 + vst1.32 {d0,d1,d2,d3},[r4],r5 + vst1.32 {d0,d1,d2,d3},[r4@64] + vst1.32 {d0,d1,d2,d3},[r4@64]! + vst1.32 {d0,d1,d2,d3},[r4@64],32 + vst1.32 {d0,d1,d2,d3},[r4@64],r5 + vst1.32 {d0[1]},[r2] + vst1.32 {d0[1]},[r2]! + vst1.32 {d0[1]},[r2],4 + vst1.32 {d0[1]},[r2],r3 + vst1.32 {d0[1]},[r2@32] + vst1.32 {d0[1]},[r2@32]! + vst1.32 {d0[1]},[r2@32],4 + vst1.32 {d0[1]},[r2@32],r3 + + vst1.64 {d0},[r1] + vst1.64 {d0},[r1]! + vst1.64 {d0},[r1],8 + vst1.64 {d0},[r1],r2 + vst1.64 {d0},[r1@64] + vst1.64 {d0},[r1@64]! + vst1.64 {d0},[r1@64],8 + vst1.64 {d0},[r1@64],r2 + vst1.64 {d0,d1},[r2] + vst1.64 {d0,d1},[r2]! + vst1.64 {d0,d1},[r2],16 + vst1.64 {d0,d1},[r2],r3 + vst1.64 {d0,d1},[r2@64] + vst1.64 {d0,d1},[r2@64]! + vst1.64 {d0,d1},[r2@64],16 + vst1.64 {d0,d1},[r2@64],r3 + vst1.64 {d0,d1,d2},[r3] + vst1.64 {d0,d1,d2},[r3]! + vst1.64 {d0,d1,d2},[r3],24 + vst1.64 {d0,d1,d2},[r3],r4 + vst1.64 {d0,d1,d2},[r3@64] + vst1.64 {d0,d1,d2},[r3@64]! + vst1.64 {d0,d1,d2},[r3@64],24 + vst1.64 {d0,d1,d2},[r3@64],r4 + vst1.64 {d0,d1,d2,d3},[r4] + vst1.64 {d0,d1,d2,d3},[r4]! + vst1.64 {d0,d1,d2,d3},[r4],32 + vst1.64 {d0,d1,d2,d3},[r4],r5 + vst1.64 {d0,d1,d2,d3},[r4@64] + vst1.64 {d0,d1,d2,d3},[r4@64]! + vst1.64 {d0,d1,d2,d3},[r4@64],32 + vst1.64 {d0,d1,d2,d3},[r4@64],r5 + + vst1.8 {d0},[r1] + vst1.8 {d0},[r1]! + vst1.8 {d0},[r1],8 + vst1.8 {d0},[r1],r2 + vst1.8 {d0},[r1@64] + vst1.8 {d0},[r1@64]! + vst1.8 {d0},[r1@64],8 + vst1.8 {d0},[r1@64],r2 + vst1.8 {d0,d1},[r2] + vst1.8 {d0,d1},[r2]! + vst1.8 {d0,d1},[r2],16 + vst1.8 {d0,d1},[r2],r3 + vst1.8 {d0,d1},[r2@64] + vst1.8 {d0,d1},[r2@64]! + vst1.8 {d0,d1},[r2@64],16 + vst1.8 {d0,d1},[r2@64],r3 + vst1.8 {d0,d1,d2},[r3] + vst1.8 {d0,d1,d2},[r3]! + vst1.8 {d0,d1,d2},[r3],24 + vst1.8 {d0,d1,d2},[r3],r4 + vst1.8 {d0,d1,d2},[r3@64] + vst1.8 {d0,d1,d2},[r3@64]! + vst1.8 {d0,d1,d2},[r3@64],24 + vst1.8 {d0,d1,d2},[r3@64],r4 + vst1.8 {d0,d1,d2,d3},[r4] + vst1.8 {d0,d1,d2,d3},[r4]! + vst1.8 {d0,d1,d2,d3},[r4],32 + vst1.8 {d0,d1,d2,d3},[r4],r5 + vst1.8 {d0,d1,d2,d3},[r4@64] + vst1.8 {d0,d1,d2,d3},[r4@64]! + vst1.8 {d0,d1,d2,d3},[r4@64],32 + vst1.8 {d0,d1,d2,d3},[r4@64],r5 + vst1.8 {d0[1]},[r2] + vst1.8 {d0[1]},[r2]! + vst1.8 {d0[1]},[r2],1 + vst1.8 {d0[1]},[r2],r3 + + vst2.16 {d0,d1},[r2] + vst2.16 {d0,d1},[r2]! + vst2.16 {d0,d1},[r2],16 + vst2.16 {d0,d1},[r2],r3 + vst2.16 {d0,d1},[r2@64] + vst2.16 {d0,d1},[r2@64]! + vst2.16 {d0,d1},[r2@64],16 + vst2.16 {d0,d1},[r2@64],r3 + vst2.16 {d0,d2},[r3] + vst2.16 {d0,d2},[r3]! + vst2.16 {d0,d2},[r3],16 + vst2.16 {d0,d2},[r3],r4 + vst2.16 {d0,d2},[r3@64] + vst2.16 {d0,d2},[r3@64]! + vst2.16 {d0,d2},[r3@64],16 + vst2.16 {d0,d2},[r3@64],r4 + vst2.16 {d0,d1,d2,d3},[r4] + vst2.16 {d0,d1,d2,d3},[r4]! + vst2.16 {d0,d1,d2,d3},[r4],32 + vst2.16 {d0,d1,d2,d3},[r4],r5 + vst2.16 {d0,d1,d2,d3},[r4@64] + vst2.16 {d0,d1,d2,d3},[r4@64]! + vst2.16 {d0,d1,d2,d3},[r4@64],32 + vst2.16 {d0,d1,d2,d3},[r4@64],r5 + vst2.16 {d0[1],d1[1]},[r2] + vst2.16 {d0[1],d1[1]},[r2]! + vst2.16 {d0[1],d1[1]},[r2],4 + vst2.16 {d0[1],d1[1]},[r2],r3 + vst2.16 {d0[1],d1[1]},[r2@32] + vst2.16 {d0[1],d1[1]},[r2@32]! + vst2.16 {d0[1],d1[1]},[r2@32],4 + vst2.16 {d0[1],d1[1]},[r2@32],r3 + vst2.16 {d0[1],d2[1]},[r2] + vst2.16 {d0[1],d2[1]},[r2]! + vst2.16 {d0[1],d2[1]},[r2],4 + vst2.16 {d0[1],d2[1]},[r2],r3 + vst2.16 {d0[1],d2[1]},[r2@32] + vst2.16 {d0[1],d2[1]},[r2@32]! + vst2.16 {d0[1],d2[1]},[r2@32],4 + vst2.16 {d0[1],d2[1]},[r2@32],r3 + vst2.32 {d0,d1},[r2] + vst2.32 {d0,d1},[r2]! + vst2.32 {d0,d1},[r2],16 + vst2.32 {d0,d1},[r2],r3 + vst2.32 {d0,d1},[r2@64] + vst2.32 {d0,d1},[r2@64]! + vst2.32 {d0,d1},[r2@64],16 + vst2.32 {d0,d1},[r2@64],r3 + vst2.32 {d0,d2},[r3] + vst2.32 {d0,d2},[r3]! + vst2.32 {d0,d2},[r3],16 + vst2.32 {d0,d2},[r3],r4 + vst2.32 {d0,d2},[r3@64] + vst2.32 {d0,d2},[r3@64]! + vst2.32 {d0,d2},[r3@64],16 + vst2.32 {d0,d2},[r3@64],r4 + vst2.32 {d0,d1,d2,d3},[r4] + vst2.32 {d0,d1,d2,d3},[r4]! + vst2.32 {d0,d1,d2,d3},[r4],32 + vst2.32 {d0,d1,d2,d3},[r4],r5 + vst2.32 {d0,d1,d2,d3},[r4@64] + vst2.32 {d0,d1,d2,d3},[r4@64]! + vst2.32 {d0,d1,d2,d3},[r4@64],32 + vst2.32 {d0,d1,d2,d3},[r4@64],r5 + vst2.32 {d0[1],d1[1]},[r2] + vst2.32 {d0[1],d1[1]},[r2]! + vst2.32 {d0[1],d1[1]},[r2],8 + vst2.32 {d0[1],d1[1]},[r2],r3 + vst2.32 {d0[1],d1[1]},[r2@64] + vst2.32 {d0[1],d1[1]},[r2@64]! + vst2.32 {d0[1],d1[1]},[r2@64],8 + vst2.32 {d0[1],d1[1]},[r2@64],r3 + vst2.32 {d0[1],d2[1]},[r2] + vst2.32 {d0[1],d2[1]},[r2]! + vst2.32 {d0[1],d2[1]},[r2],8 + vst2.32 {d0[1],d2[1]},[r2],r3 + vst2.32 {d0[1],d2[1]},[r2@64] + vst2.32 {d0[1],d2[1]},[r2@64]! + vst2.32 {d0[1],d2[1]},[r2@64],8 + vst2.32 {d0[1],d2[1]},[r2@64],r3 + + vst2.8 {d0,d1},[r2] + vst2.8 {d0,d1},[r2]! + vst2.8 {d0,d1},[r2],16 + vst2.8 {d0,d1},[r2],r3 + vst2.8 {d0,d1},[r2@64] + vst2.8 {d0,d1},[r2@64]! + vst2.8 {d0,d1},[r2@64],16 + vst2.8 {d0,d1},[r2@64],r3 + vst2.8 {d0,d2},[r3] + vst2.8 {d0,d2},[r3]! + vst2.8 {d0,d2},[r3],16 + vst2.8 {d0,d2},[r3],r4 + vst2.8 {d0,d2},[r3@64] + vst2.8 {d0,d2},[r3@64]! + vst2.8 {d0,d2},[r3@64],16 + vst2.8 {d0,d2},[r3@64],r4 + vst2.8 {d0,d1,d2,d3},[r4] + vst2.8 {d0,d1,d2,d3},[r4]! + vst2.8 {d0,d1,d2,d3},[r4],32 + vst2.8 {d0,d1,d2,d3},[r4],r5 + vst2.8 {d0,d1,d2,d3},[r4@64] + vst2.8 {d0,d1,d2,d3},[r4@64]! + vst2.8 {d0,d1,d2,d3},[r4@64],32 + vst2.8 {d0,d1,d2,d3},[r4@64],r5 + vst2.8 {d0[1],d1[1]},[r2] + vst2.8 {d0[1],d1[1]},[r2]! + vst2.8 {d0[1],d1[1]},[r2],2 + vst2.8 {d0[1],d1[1]},[r2],r3 + vst2.8 {d0[1],d1[1]},[r2@16] + vst2.8 {d0[1],d1[1]},[r2@16]! + vst2.8 {d0[1],d1[1]},[r2@16],2 + vst2.8 {d0[1],d1[1]},[r2@16],r3 + + vst3.16 {d0,d1,d2},[r2] + vst3.16 {d0,d1,d2},[r2]! + vst3.16 {d0,d1,d2},[r2],24 + vst3.16 {d0,d1,d2},[r2],r3 + vst3.16 {d0,d1,d2},[r2@64] + vst3.16 {d0,d1,d2},[r2@64]! + vst3.16 {d0,d1,d2},[r2@64],24 + vst3.16 {d0,d1,d2},[r2@64],r3 + vst3.16 {d0,d2,d4},[r3] + vst3.16 {d0,d2,d4},[r3]! + vst3.16 {d0,d2,d4},[r3],24 + vst3.16 {d0,d2,d4},[r3],r4 + vst3.16 {d0,d2,d4},[r3@64] + vst3.16 {d0,d2,d4},[r3@64]! + vst3.16 {d0,d2,d4},[r3@64],24 + vst3.16 {d0,d2,d4},[r3@64],r4 + vst3.16 {d0[1],d1[1],d2[1]},[r2] + vst3.16 {d0[1],d1[1],d2[1]},[r2]! + vst3.16 {d0[1],d1[1],d2[1]},[r2],6 + vst3.16 {d0[1],d1[1],d2[1]},[r2],r3 + vst3.16 {d0[1],d2[1],d4[1]},[r2] + vst3.16 {d0[1],d2[1],d4[1]},[r2]! + vst3.16 {d0[1],d2[1],d4[1]},[r2],6 + vst3.16 {d0[1],d2[1],d4[1]},[r2],r3 + + vst3.32 {d0,d1,d2},[r2] + vst3.32 {d0,d1,d2},[r2]! + vst3.32 {d0,d1,d2},[r2],24 + vst3.32 {d0,d1,d2},[r2],r3 + vst3.32 {d0,d1,d2},[r2@64] + vst3.32 {d0,d1,d2},[r2@64]! + vst3.32 {d0,d1,d2},[r2@64],24 + vst3.32 {d0,d1,d2},[r2@64],r3 + vst3.32 {d0,d2,d4},[r3] + vst3.32 {d0,d2,d4},[r3]! + vst3.32 {d0,d2,d4},[r3],24 + vst3.32 {d0,d2,d4},[r3],r4 + vst3.32 {d0,d2,d4},[r3@64] + vst3.32 {d0,d2,d4},[r3@64]! + vst3.32 {d0,d2,d4},[r3@64],24 + vst3.32 {d0,d2,d4},[r3@64],r4 + vst3.32 {d0[1],d1[1],d2[1]},[r2] + vst3.32 {d0[1],d1[1],d2[1]},[r2]! + vst3.32 {d0[1],d1[1],d2[1]},[r2],12 + vst3.32 {d0[1],d1[1],d2[1]},[r2],r3 + vst3.32 {d0[1],d2[1],d4[1]},[r2] + vst3.32 {d0[1],d2[1],d4[1]},[r2]! + vst3.32 {d0[1],d2[1],d4[1]},[r2],12 + vst3.32 {d0[1],d2[1],d4[1]},[r2],r3 + + vst3.8 {d0,d1,d2},[r2] + vst3.8 {d0,d1,d2},[r2]! + vst3.8 {d0,d1,d2},[r2],24 + vst3.8 {d0,d1,d2},[r2],r3 + vst3.8 {d0,d1,d2},[r2@64] + vst3.8 {d0,d1,d2},[r2@64]! + vst3.8 {d0,d1,d2},[r2@64],24 + vst3.8 {d0,d1,d2},[r2@64],r3 + vst3.8 {d0,d2,d4},[r3] + vst3.8 {d0,d2,d4},[r3]! + vst3.8 {d0,d2,d4},[r3],24 + vst3.8 {d0,d2,d4},[r3],r4 + vst3.8 {d0,d2,d4},[r3@64] + vst3.8 {d0,d2,d4},[r3@64]! + vst3.8 {d0,d2,d4},[r3@64],24 + vst3.8 {d0,d2,d4},[r3@64],r4 + vst3.8 {d0[1],d1[1],d2[1]},[r2] + vst3.8 {d0[1],d1[1],d2[1]},[r2]! + vst3.8 {d0[1],d1[1],d2[1]},[r2],3 + vst3.8 {d0[1],d1[1],d2[1]},[r2],r3 + + vst4.16 {d0,d1,d2,d3},[r4] + vst4.16 {d0,d1,d2,d3},[r4]! + vst4.16 {d0,d1,d2,d3},[r4],32 + vst4.16 {d0,d1,d2,d3},[r4],r5 + vst4.16 {d0,d1,d2,d3},[r4@64] + vst4.16 {d0,d1,d2,d3},[r4@64]! + vst4.16 {d0,d1,d2,d3},[r4@64],32 + vst4.16 {d0,d1,d2,d3},[r4@64],r5 + vst4.16 {d0,d2,d4,d6},[r4] + vst4.16 {d0,d2,d4,d6},[r4]! + vst4.16 {d0,d2,d4,d6},[r4],32 + vst4.16 {d0,d2,d4,d6},[r4],r5 + vst4.16 {d0,d2,d4,d6},[r4@64] + vst4.16 {d0,d2,d4,d6},[r4@64]! + vst4.16 {d0,d2,d4,d6},[r4@64],32 + vst4.16 {d0,d2,d4,d6},[r4@64],r5 + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2] + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],8 + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64] + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]! + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],8 + vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3 + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2] + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]! + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],8 + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],r3 + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64] + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]! + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],8 + vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3 + + vst4.32 {d0,d1,d2,d3},[r4] + vst4.32 {d0,d1,d2,d3},[r4]! + vst4.32 {d0,d1,d2,d3},[r4],32 + vst4.32 {d0,d1,d2,d3},[r4],r5 + vst4.32 {d0,d1,d2,d3},[r4@64] + vst4.32 {d0,d1,d2,d3},[r4@64]! + vst4.32 {d0,d1,d2,d3},[r4@64],32 + vst4.32 {d0,d1,d2,d3},[r4@64],r5 + vst4.32 {d0,d2,d4,d6},[r4] + vst4.32 {d0,d2,d4,d6},[r4]! + vst4.32 {d0,d2,d4,d6},[r4],32 + vst4.32 {d0,d2,d4,d6},[r4],r5 + vst4.32 {d0,d2,d4,d6},[r4@64] + vst4.32 {d0,d2,d4,d6},[r4@64]! + vst4.32 {d0,d2,d4,d6},[r4@64],32 + vst4.32 {d0,d2,d4,d6},[r4@64],r5 + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2] + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],16 + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64] + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]! + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],16 + vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3 + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2] + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]! + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],16 + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],r3 + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64] + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]! + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],16 + vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3 + + vst4.8 {d0,d1,d2,d3},[r4] + vst4.8 {d0,d1,d2,d3},[r4]! + vst4.8 {d0,d1,d2,d3},[r4],32 + vst4.8 {d0,d1,d2,d3},[r4],r5 + vst4.8 {d0,d1,d2,d3},[r4@64] + vst4.8 {d0,d1,d2,d3},[r4@64]! + vst4.8 {d0,d1,d2,d3},[r4@64],32 + vst4.8 {d0,d1,d2,d3},[r4@64],r5 + vst4.8 {d0,d2,d4,d6},[r4] + vst4.8 {d0,d2,d4,d6},[r4]! + vst4.8 {d0,d2,d4,d6},[r4],32 + vst4.8 {d0,d2,d4,d6},[r4],r5 + vst4.8 {d0,d2,d4,d6},[r4@64] + vst4.8 {d0,d2,d4,d6},[r4@64]! + vst4.8 {d0,d2,d4,d6},[r4@64],32 + vst4.8 {d0,d2,d4,d6},[r4@64],r5 + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2] + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2]! + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2],4 + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2],r3 + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32] + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32]! + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32],4 + vst4.8 {d0[1],d1[1],d2[1],d3[1]},[r2@32],r3 + + vsub.i16 d0,d1 + vsub.i16 d0,d1,d2 + vsub.i16 q0,q1 + vsub.i16 q0,q1,q2 + + vsub.i32 d0,d1 + vsub.i32 d0,d1,d2 + vsub.i32 q0,q1 + vsub.i32 q0,q1,q2 + + vsub.i64 d0,d1 + vsub.i64 d0,d1,d2 + vsub.i64 q0,q1 + vsub.i64 q0,q1,q2 + + vsub.i8 d0,d1 + vsub.i8 d0,d1,d2 + vsub.i8 q0,q1 + vsub.i8 q0,q1,q2 + + vsubhn.i16 d0,q1,q2 + + vsubhn.i32 d0,q1,q2 + + vsubhn.i64 d0,q1,q2 + + vsubl.s16 q0,d1,d2 + + vsubl.s32 q0,d1,d2 + + vsubl.s8 q0,d1,d2 + + vsubl.u16 q0,d1,d2 + + vsubl.u32 q0,d1,d2 + + vsubl.u8 q0,d1,d2 + + vsubw.s16 q0,d1 + vsubw.s16 q0,q1,d2 + + vsubw.s32 q0,d1 + vsubw.s32 q0,q1,d2 + + vsubw.s8 q0,d1 + vsubw.s8 q0,q1,d2 + + vsubw.u16 q0,d1 + vsubw.u16 q0,q1,d2 + + vsubw.u32 q0,d1 + vsubw.u32 q0,q1,d2 + + vsubw.u8 q0,d1 + vsubw.u8 q0,q1,d2 + + vswp d0,d1 + vswp q0,q1 + + vtbl.8 d0,{d1},d2 + vtbl.8 d0,{d1,d2},d3 + vtbl.8 d0,{d1,d2,d3},d4 + vtbl.8 d0,{d1,d2,d3,d4},d5 + + vtbx.8 d0,{d1},d2 + vtbx.8 d0,{d1,d2},d3 + vtbx.8 d0,{d1,d2,d3},d4 + vtbx.8 d0,{d1,d2,d3,d4},d5 + + vtrn.16 d0,d1 + vtrn.16 q0,q1 + + vtrn.32 d0,d1 + vtrn.32 q0,q1 + + vtrn.8 d0,d1 + vtrn.8 q0,q1 + + vtst.16 d0,d1 + vtst.16 d0,d1,d2 + vtst.16 q0,q1 + vtst.16 q0,q1,q2 + + vtst.32 d0,d1 + vtst.32 d0,d1,d2 + vtst.32 q0,q1 + vtst.32 q0,q1,q2 + + vtst.8 d0,d1 + vtst.8 d0,d1,d2 + vtst.8 q0,q1 + vtst.8 q0,q1,q2 + + vuzp.16 d0,d1 + vuzp.16 q0,q1 + + vuzp.32 d0,d1 + vuzp.32 q0,q1 + + vuzp.8 d0,d1 + vuzp.8 q0,q1 + + vzip.16 d0,d1 + vzip.16 q0,q1 + + vzip.32 d0,d1 + vzip.32 q0,q1 + + vzip.8 d0,d1 + vzip.8 q0,q1 + +coprocessor COPRO_SIMD_FLOAT + + vabd.f32 d0,d1 + vabd.f32 d0,d1,d2 + vabd.f32 q0,q1 + vabd.f32 q0,q1,q2 + + vabs.f32 d0,d1 + vabs.f32 q0,q1 + + vacge.f32 d0,d1 + vacge.f32 d0,d1,d2 + vacge.f32 q0,q1 + vacge.f32 q0,q1,q2 + + vacgt.f32 d0,d1 + vacgt.f32 d0,d1,d2 + vacgt.f32 q0,q1 + vacgt.f32 q0,q1,q2 + + vacle.f32 d0,d1 + vacle.f32 d0,d1,d2 + vacle.f32 q0,q1 + vacle.f32 q0,q1,q2 + + vaclt.f32 d0,d1 + vaclt.f32 d0,d1,d2 + vaclt.f32 q0,q1 + vaclt.f32 q0,q1,q2 + + vadd.f32 d0,d1 + vadd.f32 d0,d1,d2 + vadd.f32 q0,q1 + vadd.f32 q0,q1,q2 + + vceq.f32 d0,0 + vceq.f32 d0,d1 + vceq.f32 d0,d1,0 + vceq.f32 d0,d1,d2 + vceq.f32 q0,0 + vceq.f32 q0,q1 + vceq.f32 q0,q1,0 + vceq.f32 q0,q1,q2 + + vcge.f32 d0,0 + vcge.f32 d0,d1 + vcge.f32 d0,d1,0 + vcge.f32 d0,d1,d2 + vcge.f32 q0,0 + vcge.f32 q0,q1 + vcge.f32 q0,q1,0 + vcge.f32 q0,q1,q2 + + vcgt.f32 d0,0 + vcgt.f32 d0,d1 + vcgt.f32 d0,d1,0 + vcgt.f32 d0,d1,d2 + vcgt.f32 q0,0 + vcgt.f32 q0,q1 + vcgt.f32 q0,q1,0 + vcgt.f32 q0,q1,q2 + + vcle.f32 d0,0 + vcle.f32 d0,d1 + vcle.f32 d0,d1,0 + vcle.f32 d0,d1,d2 + vcle.f32 q0,0 + vcle.f32 q0,q1 + vcle.f32 q0,q1,0 + vcle.f32 q0,q1,q2 + + vclt.f32 d0,0 + vclt.f32 d0,d1 + vclt.f32 d0,d1,0 + vclt.f32 d0,d1,d2 + vclt.f32 q0,0 + vclt.f32 q0,q1 + vclt.f32 q0,q1,0 + vclt.f32 q0,q1,q2 + + vcvt.f32.s32 d0,d1 + vcvt.f32.s32 d0,d1,2 + vcvt.f32.s32 q0,q1 + vcvt.f32.s32 q0,q1,2 + + vcvt.f32.u32 d0,d1 + vcvt.f32.u32 d0,d1,2 + vcvt.f32.u32 q0,q1 + vcvt.f32.u32 q0,q1,2 + + vcvt.s32.f32 d0,d1 + vcvt.s32.f32 d0,d1,2 + vcvt.s32.f32 q0,q1 + vcvt.s32.f32 q0,q1,2 + + vcvt.u32.f32 d0,d1 + vcvt.u32.f32 d0,d1,2 + vcvt.u32.f32 q0,q1 + vcvt.u32.f32 q0,q1,2 + + vmax.f32 d0,d1 + vmax.f32 d0,d1,d2 + vmax.f32 q0,q1 + vmax.f32 q0,q1,q2 + + vmin.f32 d0,d1 + vmin.f32 d0,d1,d2 + vmin.f32 q0,q1 + vmin.f32 q0,q1,q2 + + vmla.f32 d0,d1,d2 + vmla.f32 d0,d1,d2[0] + vmla.f32 q0,q1,q2 + vmla.f32 q0,q1,d2[1] + + vmls.f32 d0,d1,d2 + vmls.f32 d0,d1,d2[0] + vmls.f32 q0,q1,q2 + vmls.f32 q0,q1,d2[1] + + vmov.f32 d0,1 + vmov.f32 d0,1.0 + vmov.f32 q0,1 + vmov.f32 q0,1.0 + + vmul.f32 d0,d1 + vmul.f32 d0,d1,d2 + vmul.f32 d0,d1[0] + vmul.f32 d0,d1,d2[0] + vmul.f32 q0,q1 + vmul.f32 q0,q1,q2 + vmul.f32 q0,d1[0] + vmul.f32 q0,q1,d1[0] + + vneg.f32 d0,d1 + vneg.f32 q0,q1 + + vpadd.f32 d0,d1 + vpadd.f32 d0,d1,d2 + + vpmax.f32 d0,d1 + vpmax.f32 d0,d1,d2 + + vpmin.f32 d0,d1 + vpmin.f32 d0,d1,d2 + + vrecpe.f32 d0,d1 + vrecpe.f32 q0,q1 + + vrecps.f32 d0,d1 + vrecps.f32 d0,d1,d2 + vrecps.f32 q0,q1 + vrecps.f32 q0,q1,q2 + + vrsqrte.f32 d0,d1 + vrsqrte.f32 q0,q1 + + vrsqrts.f32 d0,d1 + vrsqrts.f32 d0,d1,d2 + vrsqrts.f32 q0,q1 + vrsqrts.f32 q0,q1,q2 + + vsub.f32 d0,d1 + vsub.f32 d0,d1,d2 + vsub.f32 q0,q1 + vsub.f32 q0,q1,q2 + +coprocessor COPRO_SIMD_HP + + vcvt.f32.f16 q0,d1 + + vcvt.f16.f32 d0,q1 + +coprocessor COPRO_SIMD_V2 + + vfma.f32 q0,q1,q2 + vfma.f32 d0,d1,d2 + + vfms.f32 q0,q1,q2 + vfms.f32 d0,d1,d2 + +coprocessor COPRO_SIMD_V8 + + vcvtm.s32.f32 d0,d1 + vcvtm.u32.f32 d0,d1 + vcvtm.s32.f32 q0,q1 + vcvtm.u32.f32 q0,q1 + + vcvtp.s32.f32 d0,d1 + vcvtp.u32.f32 d0,d1 + vcvtp.s32.f32 q0,q1 + vcvtp.u32.f32 q0,q1 + + vcvtn.s32.f32 d0,d1 + vcvtn.u32.f32 d0,d1 + vcvtn.s32.f32 q0,q1 + vcvtn.u32.f32 q0,q1 + + vcvta.s32.f32 d0,d1 + vcvta.u32.f32 d0,d1 + vcvta.s32.f32 q0,q1 + vcvta.u32.f32 q0,q1 + + vmaxnm.f32 d0,d1,d2 + vmaxnm.f32 q0,q1,q2 + + vminnm.f32 d0,d1,d2 + vminnm.f32 q0,q1,q2 + + vrintm.f32.f32 d0,d1 + vrintm.f32.f32 q0,q1 + + vrintp.f32.f32 d0,d1 + vrintp.f32.f32 q0,q1 + + vrintn.f32.f32 d0,d1 + vrintn.f32.f32 q0,q1 + + vrinta.f32.f32 d0,d1 + vrinta.f32.f32 q0,q1 + + vrintx.f32.f32 d0,d1 + vrintx.f32.f32 q0,q1 + + vrintz.f32.f32 d0,d1 + vrintz.f32.f32 q0,q1 + +coprocessor COPRO_SIMD_CRYPTO + + aese.8 q0,q1 + aesd.8 q0,q1 + aesmc.8 q0,q1 + aesimc.8 q0,q1 + + sha1h.32 q0,q1 + sha1c.32 q0,q1,q2 + sha1p.32 q0,q1,q2 + sha1m.32 q0,q1,q2 + sha1su0.32 q0,q1,q2 + sha1su1.32 q0,q1 + + sha256h.32 q0,q1,q2 + sha256h2.32 q0,q1,q2 + sha256su0.32 q0,q1 + sha256su1.32 q0,q1,q2 + + vmull.p64 q0,d1,d2 diff --git a/armdoc/InstructionFormatsTHUMB16.asm b/armdoc/InstructionFormatsTHUMB16.asm new file mode 100644 index 0000000..42f492a --- /dev/null +++ b/armdoc/InstructionFormatsTHUMB16.asm @@ -0,0 +1,477 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition or flag +;writeback ("s") syntaxes. Almost all instructions can +;be conditional. The condition code should be added at +;the end of the main opcode and before any size/type +;specifiers. For example: "addhi" and "vaddhi.i16". The +;syntax also supports the pre-UAL style of putting the +;condition before any modifiers like "s" or "fd". For +;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;THUMB mode, pre-UAL 16-bit instructions + ;*********************************************** + + code16 ;pre-UAL syntax, the 's' is otional + +macro align {times(($ and 2)shr 1)dh 0xde_00} + +processor CPU32_V4T + + adc r0,r1 + adc r0,r0,r1 + + add r0,r1,2 + add r0,1 + add r0,r1,r2 + add r0,r0,3 + + and r0,r1 + and r0,r0,r1 + + asr r0,1 + asr r0,r1,2 + asr r0,r1 + asr r0,r0,r1 + + bic r0,r1 + bic r0,r0,r1 + + eor r0,r1 + eor r0,r0,r1 + + ldm r0!,{r1} + ldm r0!,{r0} + + ldmia r0!,{r1} + ldmia r0!,{r0} + + lsl r0,1 + lsl r0,r1,2 + lsl r0,r1 + lsl r0,r0,r1 + + lsr r0,1 + lsr r0,r1,2 + lsr r0,r1 + lsr r0,r0,r1 + + mov r0,1 + mov r0,r1 + mov r0,expression.dword + + mul r0,r1 + mul r0,r1,r0 + mul r0,r0,r1 + + mvn r0,r1 + + neg r0 + neg r0,r1 + + orr r0,r1 + orr r0,r0,r1 + + ror r0,r1 + ror r0,r0,r1 + + rsb r0,0 + rsb r0,r1,0 + + sbc r0,r1 + sbc r0,r0,r1 + + sub r0,r1,2 + sub r0,1 + sub r0,r1,r2 + sub r0,r0,3 + + ;*********************************************** + ;THUMB mode, UAL 16-bit instructions + ;*********************************************** + + thumb ;UAL syntax, the 's', if given, is mandatory + + adcs r0,r1 + adcs r0,r0,r1 + + adds r0,r1,2 + adds r0,1 + adds r0,r1,r2 + + ands r0,r1 + ands r0,r0,r1 + + asrs r0,1 + asrs r0,r1,2 + asrs r0,r1 + asrs r0,r0,r1 + + bics r0,r1 + bics r0,r0,r1 + + eors r0,r1 + eors r0,r0,r1 + + ldm r0!,{r1} + ldm r0,{r0} + + ldmia r0!,{r1} + ldmia r0,{r0} + + lsls r0,1 + lsls r0,r1,2 + lsls r0,r1 + lsls r0,r0,r1 + + lsrs r0,1 + lsrs r0,r1,2 + lsrs r0,r1 + lsrs r0,r0,r1 + + movs r0,1 + movs r0,r1 + movs r0,expression.dword + + muls r0,r1 + muls r0,r1,r0 + muls r0,r0,r1 + + mvns r0,r1 + + negs r0 + negs r0,r1 + + orrs r0,r1 + orrs r0,r0,r1 + + rors r0,r1 + rors r0,r0,r1 + + rsbs r0,0 + rsbs r0,r1,0 + + sbcs r0,r1 + sbcs r0,r0,r1 + + subs r0,r1,2 + subs r0,1 + subs r0,r1,r2 + + ;both pre-UAL and UAL syntaxes, no 's' is allowed + + add r8,r9 + add r0,sp,4 + add sp,4 + add sp,sp,4 + add r0,pc,4 + + adr r0,label_adr_t16 + align + label_adr_t16: + + bx r0 + + cmn r0,r1 + + cmp r0,1 + cmp r0,r1 + cmp r8,r9 + + ldr r0,[r1] + ldr r0,[r1,4] + ldr r0,[sp] + ldr r0,[sp,4] + ldr r0,[label_ldr_t16] + ldr r0,[pc] + ldr r0,[pc,4] + ldr r0,[r1,r2] + ldr r1,[sp],4 + ldr r15,[sp],4 + align + label_ldr_t16: + + ldrb r0,[r1] + ldrb r0,[r1,2] + ldrb r0,[r1,r2] + + ldrh r0,[r1] + ldrh r0,[r1,2] + ldrh r0,[r1,r2] + + ldrsb r0,[r1,r2] + + ldrsh r0,[r1,r2] + + mov r8,r9 + + nop + + pop {r0} + pop {r0,r15} + + push {r0} + push {r0,r14} + + stm r0!,{r1} + stm r0!,{r1,r2} + + stmia r0!,{r1} + stmia r0!,{r1,r2} + + str r0,[r1] + str r0,[r1,4] + str r0,[sp] + str r0,[sp,4] + str r0,[r1,r2] + str r1,[sp,-4]! + str r14,[sp,-4]! + + strb r0,[r1] + strb r0,[r1,4] + strb r0,[r1,r2] + + strh r0,[r1] + strh r0,[r1,4] + strb r0,[r1,r2] + + sub sp,4 + sub sp,sp,4 + + svc 0 + + swi 0 + + tst r0,r1 + + bcc label_bcc_t16 + label_bcc_t16: + + b label_b_t16 + label_b_t16: + +processor CPU32_V5T + + bkpt 0 + + blx r0 + +processor CPU32_V6T + + cpy r0,r1 + + rev r0,r1 + + rev16 r0,r1 + + revsh r0,r1 + + sxtb r0 + sxtb r0,r1 + + sxth r0 + sxth r0,r1 + + uxtb r0 + uxtb r0,r1 + + uxth r0 + uxth r0,r1 + +processor CPU32_ALIGN + + cpsie iflags_a + + cpsid iflags_a + + setend le + +processor CPU32_6M + + add r0,r1 + + yield + + wfe + + wfi + + sev + +processor CPU32_7M + + cbnz r0,label_cbnz_t16 + dh 0xde00 + label_cbnz_t16: + + cbz r0,label_cbz_t16 + dh 0xde00 + label_cbz_t16: + +processor CPU32_7M + CPU32_V5T + + it cc + bkpt 0 ;dummy fill to satisfy IT checks + + ite cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itee cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + iteee cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + iteet cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itet cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itete cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itett cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itt cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itte cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + ittee cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + ittet cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + ittt cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + ittte cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + itttt cc + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + bkpt 0 ;dummy fill to satisfy IT checks + + ;*********************************************** + ;THUMBEE mode, 16-bit instructions + ;*********************************************** + + thumbee + +processor CPU32_T2EE + + chka r0,r1 + + hb 0 + hbl 0 + hblp 0,0 + hbp 0,0 + + ldr r0,[r1,r2,lsl 2] + ldr r0,[r1,-4] + ldr r0,[r9] + ldr r0,[r9,4] + ldr r0,[r10] + ldr r0,[r10,4] + + ldrb r0,[r1,r2] + + ldrh r0,[r1,r2,lsl 1] + + ldrsb r0,[r1,r2] + + ldrsh r0,[r1,r2,lsl 1] + + str r0,[r1,r2,lsl 2] + str r0,[r9] + str r0,[r9,4] + + strb r0,[r1,r2] + + strh r0,[r1,r2,lsl 1] + +processor CPU32_V8 + + hlt 0 + + sevl + sevl.n + +processor 0 ;16-bit UND is always encodable, it ignores the processor directive + + und + und 0 diff --git a/armdoc/InstructionFormatsTHUMB32.asm b/armdoc/InstructionFormatsTHUMB32.asm new file mode 100644 index 0000000..67b0ba3 --- /dev/null +++ b/armdoc/InstructionFormatsTHUMB32.asm @@ -0,0 +1,1226 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition or flag +;writeback ("s") syntaxes. Almost all instructions can +;be conditional. The condition code should be added at +;the end of the main opcode and before any size/type +;specifiers. For example: "addhi" and "vaddhi.i16". The +;syntax also supports the pre-UAL style of putting the +;condition before any modifiers like "s" or "fd". For +;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;THUMB mode, 32-bit instructions + ;*********************************************** + + thumb + +processor CPU32_V4T + + label_bl_t32: + bl label_bl_t32 + +processor CPU32_X + + label_blx_t32: + blx label_blx_t32 + +processor CPU32_Z + + smc 0 + + smi 0 + +processor CPU32_6M + + dmb + dmb sy + + dsb + dsb sy + + isb + isb sy + + mrs r0,primask + + msr primask,r0 + +processor CPU32_7M + + adc r0,1 + adc r0,r1 + adc r0,r1,rrx + adc r0,r1,lsl 2 + adc r0,r1,lsr 2 + adc r0,r1,asr 2 + adc r0,r1,ror 2 + adc r0,r1,2 + adc r0,r1,r2 + adc r0,r1,r2,rrx + adc r0,r1,r2,lsl 3 + adc r0,r1,r2,lsr 3 + adc r0,r1,r2,asr 3 + adc r0,r1,r2,ror 3 + + add r0,1 + add r0,r1 + add r0,r1,rrx + add r0,r1,lsl 2 + add r0,r1,lsr 2 + add r0,r1,asr 2 + add r0,r1,ror 2 + add r0,r1,2 + add r0,r1,r2 + add r0,r1,r2,rrx + add r0,r1,r2,lsl 3 + add r0,r1,r2,lsr 3 + add r0,r1,r2,asr 3 + add r0,r1,r2,ror 3 + + addw r0,1 + addw r0,r1,2 + + label_adr_t32: + adr r0,label_adr_t32 + + and r0,1 + and r0,r1 + and r0,r1,rrx + and r0,r1,lsl 2 + and r0,r1,lsr 2 + and r0,r1,asr 2 + and r0,r1,ror 2 + and r0,r1,2 + and r0,r1,r2 + and r0,r1,r2,rrx + and r0,r1,r2,lsl 3 + and r0,r1,r2,lsr 3 + and r0,r1,r2,asr 3 + and r0,r1,r2,ror 3 + + asr r0,1 + asr r0,r1 + asr r0,r1,2 + asr r0,r1,r2 + + label_b_t32: + b label_b_t32 + + label_bcc_t32: + bcc label_bcc_t32 + + bfc r0,1,2 + + bfi r0,r1,2,3 + + bic r0,1 + bic r0,r1 + bic r0,r1,rrx + bic r0,r1,lsl 2 + bic r0,r1,lsr 2 + bic r0,r1,asr 2 + bic r0,r1,ror 2 + bic r0,r1,2 + bic r0,r1,r2 + bic r0,r1,r2,rrx + bic r0,r1,r2,lsl 3 + bic r0,r1,r2,lsr 3 + bic r0,r1,r2,asr 3 + bic r0,r1,r2,ror 3 + + cdp p9,1,c2,c3,c4 + cdp p9,1,c2,c3,c4,5 + + cdp2 p9,1,c2,c3,c4 + cdp2 p9,1,c2,c3,c4,5 + + clrex + + clz r0,r1 + + cmn r0,1 + cmn r0,r1 + cmn r0,r1,rrx + cmn r0,r1,lsl 2 + cmn r0,r1,lsr 2 + cmn r0,r1,asr 2 + cmn r0,r1,ror 2 + + cmp r0,1 + cmp r0,r1 + cmp r0,r1,rrx + cmp r0,r1,lsl 2 + cmp r0,r1,lsr 2 + cmp r0,r1,asr 2 + cmp r0,r1,ror 2 + + cpy r0,r1 + + dbg 0 + + eor r0,1 + eor r0,r1 + eor r0,r1,rrx + eor r0,r1,lsl 2 + eor r0,r1,lsr 2 + eor r0,r1,asr 2 + eor r0,r1,ror 2 + eor r0,r1,2 + eor r0,r1,r2 + eor r0,r1,r2,rrx + eor r0,r1,r2,lsl 3 + eor r0,r1,r2,lsr 3 + eor r0,r1,r2,asr 3 + eor r0,r1,r2,ror 3 + + label_ldc_t32: + ldc p9,c1,[r2] + ldc p9,c1,[r2],4 + ldc p9,c1,[r2],{4} + ldc p9,c1,[r2,4] + ldc p9,c1,[r2,4]! + ldc p9,c1,[label_ldc_t32] + ldc p9,c1,[expression.word] + ldc p9,c1,[expression.word]! + + label_ldc2_t32: + ldc2 p9,c1,[r2] + ldc2 p9,c1,[r2],4 + ldc2 p9,c1,[r2],{4} + ldc2 p9,c1,[r2,4] + ldc2 p9,c1,[r2,4]! + ldc2 p9,c1,[label_ldc2_t32] + ldc2 p9,c1,[expression.word] + ldc2 p9,c1,[expression.word]! + + label_ldc2l_t32: + ldc2l p9,c1,[r2] + ldc2l p9,c1,[r2],4 + ldc2l p9,c1,[r2],{4} + ldc2l p9,c1,[r2,4] + ldc2l p9,c1,[r2,4]! + ldc2l p9,c1,[label_ldc2l_t32] + ldc2l p9,c1,[expression.word] + ldc2l p9,c1,[expression.word]! + + label_ldcl_t32: + ldcl p9,c1,[r2] + ldcl p9,c1,[r2],4 + ldcl p9,c1,[r2],{4} + ldcl p9,c1,[r2,4] + ldcl p9,c1,[r2,4]! + ldcl p9,c1,[label_ldcl_t32] + ldcl p9,c1,[expression.word] + ldcl p9,c1,[expression.word]! + + ldm r0,{r1} + ldm r0,{r1,r2} + ldm r0,{r1-r3} + ldm r0,{r1-r3,r5} + ldm r0!,{r1} + ldm r0!,{r1,r2} + ldm r0!,{r1-r3} + ldm r0!,{r1-r3,r5} + + ldmia r0,{r1} + ldmia r0,{r1,r2} + ldmia r0,{r1-r3} + ldmia r0,{r1-r3,r5} + ldmia r0!,{r1} + ldmia r0!,{r1,r2} + ldmia r0!,{r1-r3} + ldmia r0!,{r1-r3,r5} + + ldmdb r0,{r1} + ldmdb r0,{r1,r2} + ldmdb r0,{r1-r3} + ldmdb r0,{r1-r3,r5} + ldmdb r0!,{r1} + ldmdb r0!,{r1,r2} + ldmdb r0!,{r1-r3} + ldmdb r0!,{r1-r3,r5} + + ldmea r0,{r1} + ldmea r0,{r1,r2} + ldmea r0,{r1-r3} + ldmea r0,{r1-r3,r5} + ldmea r0!,{r1} + ldmea r0!,{r1,r2} + ldmea r0!,{r1-r3} + ldmea r0!,{r1-r3,r5} + + ldmfd r0,{r1} + ldmfd r0,{r1,r2} + ldmfd r0,{r1-r3} + ldmfd r0,{r1-r3,r5} + ldmfd r0!,{r1} + ldmfd r0!,{r1,r2} + ldmfd r0!,{r1-r3} + ldmfd r0!,{r1-r3,r5} + + label_ldr_t32: + ldr r0,[r1] + ldr r0,[r1],2 + ldr r0,[r1],4 + ldr r0,[r1,2] + ldr r0,[r1,2]! + ldr r0,[r1,r2] + ldr r0,[r1,r2,lsl 3] + ldr r0,[label_ldr_t32] + ldr r0,[expression.word] + ldr r0,[expression.word]! + + label_ldrb_t32: + ldrb r0,[r1] + ldrb r0,[r1],2 + ldrb r0,[r1],4 + ldrb r0,[r1,2] + ldrb r0,[r1,2]! + ldrb r0,[r1,r2] + ldrb r0,[r1,r2,lsl 3] + ldrb r0,[label_ldrb_t32] + ldrb r0,[expression.byte] + ldrb r0,[expression.byte]! + + ldrb r0,[r13] + ldrb r0,[r13,2] + ldrb r0,[r13,r2] + + ldrbt r0,[r1] + ldrbt r0,[r1,2] + ldrbt r0,[expression.byte] + + label_ldrd_t32: + ldrd r0,[r1] + ldrd r0,[r2],4 + ldrd r0,[r1,4] + ldrd r0,[r2,4]! + ldrd r0,[label_ldrd_t32] + ldrd r2,[expression.dword] + ldrd r2,[expression.dword]! + ldrd r0,r1,[r2] + ldrd r0,r1,[r2],4 + ldrd r0,r1,[r2,4] + ldrd r0,r1,[r2,4]! + ldrd r0,r1,[label_ldrd_t32] + ldrd r0,r2,[expression.dword] + ldrd r0,r2,[expression.dword]! + + ldrex r0,[r1] + ldrex r0,[r1,4] + ldrex r0,[expression.word] + + label_ldrh_t32: + ldrh r0,[r1] + ldrh r0,[r1],2 + ldrh r0,[r1],4 + ldrh r0,[r1,2] + ldrh r0,[r1,2]! + ldrh r0,[r1,r2] + ldrh r0,[r1,r2,lsl 3] + ldrh r0,[label_ldrh_t32] + ldrh r0,[expression.hword] + ldrh r0,[expression.hword]! + + ldrh r0,[r13] + ldrh r0,[r13,2] + ldrh r0,[r13,r2] + + ldrht r0,[r1] + ldrht r0,[r1,2] + ldrht r0,[expression.hword] + + label_ldrsb_t32: + ldrsb r0,[r1] + ldrsb r0,[r1],2 + ldrsb r0,[r1],4 + ldrsb r0,[r1,2] + ldrsb r0,[r1,2]! + ldrsb r0,[r1,r2] + ldrsb r0,[r1,r2,lsl 3] + ldrsb r0,[label_ldrsb_t32] + ldrsb r0,[expression.byte] + ldrsb r0,[expression.byte]! + + ldrsbt r0,[r1] + ldrsbt r0,[r1,2] + ldrsbt r0,[expression.byte] + + label_ldrsh_t32: + ldrsh r0,[r1] + ldrsh r0,[r1],2 + ldrsh r0,[r1],4 + ldrsh r0,[r1,2] + ldrsh r0,[r1,2]! + ldrsh r0,[r1,r2] + ldrsh r0,[r1,r2,lsl 3] + ldrsh r0,[label_ldrsh_t32] + ldrsh r0,[expression.hword] + ldrsh r0,[expression.hword]! + + ldrsht r0,[r1] + ldrsht r0,[r1,2] + ldrsht r0,[expression.hword] + + ldrt r0,[r1] + ldrt r0,[r1,2] + ldrt r0,[expression.word] + + lsl r0,1 + lsl r0,r1 + lsl r0,r1,2 + lsl r0,r1,r2 + + lsr r0,1 + lsr r0,r1 + lsr r0,r1,2 + lsr r0,r1,r2 + + mcr p9,1,r2,c3,c4 + mcr p9,1,r2,c3,c4,5 + + mcr2 p9,1,r2,c3,c4 + mcr2 p9,1,r2,c3,c4,5 + + mcrr p9,1,r2,r3,c4 + + mcrr2 p9,1,r2,r3,c4 + + mla r0,r1,r2,r3 + + mls r0,r1,r2,r3 + + mov r0,1 + mov r0,r1 + mov r0,r1,rrx + mov r0,r1,lsl 2 + mov r0,r1,lsr 2 + mov r0,r1,asr 2 + mov r0,r1,ror 2 + mov r0,r1,lsl r2 + mov r0,r1,lsr r2 + mov r0,r1,asr r2 + mov r0,r1,ror r2 + mov r0,expression.word + + movt r0,1 + + movw r0,1 + + mrc p9,1,r2,c3,c4 + mrc p9,1,r15,c3,c4,5 + + mrc2 p9,1,r2,c3,c4 + mrc2 p9,1,r15,c3,c4,5 + + mrrc p9,1,r2,r3,c4 + + mrrc2 p9,1,r2,r3,c4 + + mrs r0,basepri + + msr basepri,r0 + + mul r0,r1 + mul r0,r1,r2 + + mvn r0,1 + mvn r0,r1 + mvn r0,r1,rrx + mvn r0,r1,lsl 2 + mvn r0,r1,lsr 2 + mvn r0,r1,asr 2 + mvn r0,r1,ror 2 + + neg r0 + neg r0,r1 + + nop + + orn r0,1 + orn r0,r1 + orn r0,r1,rrx + orn r0,r1,lsl 2 + orn r0,r1,lsr 2 + orn r0,r1,asr 2 + orn r0,r1,ror 2 + orn r0,r1,2 + orn r0,r1,r2 + orn r0,r1,r2,rrx + orn r0,r1,r2,lsl 3 + orn r0,r1,r2,lsr 3 + orn r0,r1,r2,asr 3 + orn r0,r1,r2,ror 3 + + orr r0,1 + orr r0,r1 + orr r0,r1,rrx + orr r0,r1,lsl 2 + orr r0,r1,lsr 2 + orr r0,r1,asr 2 + orr r0,r1,ror 2 + orr r0,r1,2 + orr r0,r1,r2 + orr r0,r1,r2,rrx + orr r0,r1,r2,lsl 3 + orr r0,r1,r2,lsr 3 + orr r0,r1,r2,asr 3 + orr r0,r1,r2,ror 3 + + label_pld_t32: + pld [r1] + pld [r1,2] + pld [r1,r2] + pld [r1,r2,lsl 3] + pld [label_pld_t32] + pld [expression.byte] + + pop {r0} + pop {r0,r1} + pop {r0-r2} + pop {r0-r2,r4} + + push {r0} + push {r0,r1} + push {r0-r2} + push {r0-r2,r4} + + rbit r0,r1 + + rev r0,r1 + + rev16 r0,r1 + + revsh r0,r1 + + ror r0,1 + ror r0,r1 + ror r0,r1,2 + ror r0,r1,r2 + + rrx r0 + rrx r0,r1 + + rsb r0,1 + rsb r0,r1 + rsb r0,r1,rrx + rsb r0,r1,lsl 2 + rsb r0,r1,lsr 2 + rsb r0,r1,asr 2 + rsb r0,r1,ror 2 + rsb r0,r1,2 + rsb r0,r1,r2 + rsb r0,r1,r2,rrx + rsb r0,r1,r2,lsl 3 + rsb r0,r1,r2,lsr 3 + rsb r0,r1,r2,asr 3 + rsb r0,r1,r2,ror 3 + + sbc r0,1 + sbc r0,r1 + sbc r0,r1,rrx + sbc r0,r1,lsl 2 + sbc r0,r1,lsr 2 + sbc r0,r1,asr 2 + sbc r0,r1,ror 2 + sbc r0,r1,2 + sbc r0,r1,r2 + sbc r0,r1,r2,rrx + sbc r0,r1,r2,lsl 3 + sbc r0,r1,r2,lsr 3 + sbc r0,r1,r2,asr 3 + sbc r0,r1,r2,ror 3 + + sbfx r0,r1,2,3 + + sev + + smlal r0,r1,r2,r3 + + smull r0,r1,r2,r3 + + label_stc_t32: + stc p9,c1,[r2] + stc p9,c1,[r2],4 + stc p9,c1,[r2],{4} + stc p9,c1,[r2,4] + stc p9,c1,[r2,4]! + stc p9,c1,[label_stc_t32] + stc p9,c1,[expression.word] + stc p9,c1,[expression.word]! + + label_stc2_t32: + stc2 p9,c1,[r2] + stc2 p9,c1,[r2],4 + stc2 p9,c1,[r2],{4} + stc2 p9,c1,[r2,4] + stc2 p9,c1,[r2,4]! + stc2 p9,c1,[label_stc2_t32] + stc2 p9,c1,[expression.word] + stc2 p9,c1,[expression.word]! + + label_stc2l_t32: + stc2l p9,c1,[r2] + stc2l p9,c1,[r2],4 + stc2l p9,c1,[r2],{4} + stc2l p9,c1,[r2,4] + stc2l p9,c1,[r2,4]! + stc2l p9,c1,[label_stc2l_t32] + stc2l p9,c1,[expression.word] + stc2l p9,c1,[expression.word]! + + label_stcl_t32: + stcl p9,c1,[r2] + stcl p9,c1,[r2],4 + stcl p9,c1,[r2],{4} + stcl p9,c1,[r2,4] + stcl p9,c1,[r2,4]! + stcl p9,c1,[label_stcl_t32] + stcl p9,c1,[expression.word] + stcl p9,c1,[expression.word]! + + stm r0,{r1} + stm r0,{r1,r2} + stm r0,{r1-r3} + stm r0,{r1-r3,r5} + stm r0!,{r1} + stm r0!,{r1,r2} + stm r0!,{r1-r3} + stm r0!,{r1-r3,r5} + + stmia r0,{r1} + stmia r0,{r1,r2} + stmia r0,{r1-r3} + stmia r0,{r1-r3,r5} + stmia r0!,{r1} + stmia r0!,{r1,r2} + stmia r0!,{r1-r3} + stmia r0!,{r1-r3,r5} + + stmdb r0,{r1} + stmdb r0,{r1,r2} + stmdb r0,{r1-r3} + stmdb r0,{r1-r3,r5} + stmdb r0!,{r1} + stmdb r0!,{r1,r2} + stmdb r0!,{r1-r3} + stmdb r0!,{r1-r3,r5} + + stmea r0,{r1} + stmea r0,{r1,r2} + stmea r0,{r1-r3} + stmea r0,{r1-r3,r5} + stmea r0!,{r1} + stmea r0!,{r1,r2} + stmea r0!,{r1-r3} + stmea r0!,{r1-r3,r5} + + stmfd r0,{r1} + stmfd r0,{r1,r2} + stmfd r0,{r1-r3} + stmfd r0,{r1-r3,r5} + stmfd r0!,{r1} + stmfd r0!,{r1,r2} + stmfd r0!,{r1-r3} + stmfd r0!,{r1-r3,r5} + + str r0,[r1] + str r0,[r1],2 + str r0,[r1,2] + str r0,[r1,2]! + str r0,[r1,r2] + str r0,[r1,r2,lsl 3] + str r0,[expression.word] + str r0,[expression.word]! + + strb r0,[r1] + strb r0,[r1],2 + strb r0,[r1,2] + strb r0,[r1,2]! + strb r0,[r1,r2] + strb r0,[r1,r2,lsl 3] + strb r0,[expression.byte] + strb r0,[expression.byte]! + + strbt r0,[r1] + strbt r0,[r1,2] + strbt r0,[expression.byte] + + strd r0,[r1] + strd r0,[r2],4 + strd r0,[r1,4] + strd r0,[r2,4]! + strd r2,[expression.dword] + strd r2,[expression.dword]! + strd r0,r1,[r2] + strd r0,r1,[r2],4 + strd r0,r1,[r2,4] + strd r0,r1,[r2,4]! + strd r0,r2,[expression.dword] + strd r0,r2,[expression.dword]! + + strex r0,r1,[r2] + strex r0,r1,[r2,4] + strex r2,r4,[expression.word] + + strh r0,[r1] + strh r0,[r1],2 + strh r0,[r1,2] + strh r0,[r1,2]! + strh r0,[r1,r2] + strh r0,[r1,r2,lsl 3] + strh r0,[expression.hword] + strh r0,[expression.hword]! + + strht r0,[r1] + strht r0,[r1,2] + strht r0,[expression.hword] + + strt r0,[r1] + strt r0,[r1,2] + strt r0,[expression.word] + + sub r0,1 + sub r0,r1 + sub r0,r1,rrx + sub r0,r1,lsl 2 + sub r0,r1,lsr 2 + sub r0,r1,asr 2 + sub r0,r1,ror 2 + sub r0,r1,2 + sub r0,r1,r2 + sub r0,r1,r2,rrx + sub r0,r1,r2,lsl 3 + sub r0,r1,r2,lsr 3 + sub r0,r1,r2,asr 3 + sub r0,r1,r2,ror 3 + + subw r0,1 + subw r0,r1,2 + + sxtb r0,r1 + sxtb r0,r1,ror 8 + + sxth r0,r1 + sxth r0,r1,ror 8 + + tbb [r0,r1] + + tbh [r0,r1,lsl 1] + + teq r0,1 + teq r0,r1 + teq r0,r1,rrx + teq r0,r1,lsl 2 + teq r0,r1,lsr 2 + teq r0,r1,asr 2 + teq r0,r1,ror 2 + + tst r0,1 + tst r0,r1 + tst r0,r1,rrx + tst r0,r1,lsl 2 + tst r0,r1,lsr 2 + tst r0,r1,asr 2 + tst r0,r1,ror 2 + + ubfx r0,r1,2,3 + + umlal r0,r1,r2,r3 + + umull r0,r1,r2,r3 + + und.w + und 0x100 + + uxtb r0,r1 + uxtb r0,r1,ror 8 + + uxth r0,r1 + uxth r0,r1,ror 8 + + wfe + + wfi + + yield + +processor CPU32_T2 + + bxj r0 + + cps 0 + + cpsid iflags_a + cpsid iflags_a,0 + + cpsie iflags_a + cpsie iflags_a,0 + + mrs r0,cpsr + mrs r0,spsr + + msr cpsr,r1 + msr cpsr_fsxc,r1 + + pkhbt r0,r1 + pkhbt r0,r1,lsl 3 + pkhbt r0,r1,r2 + pkhbt r0,r1,r2,lsl 3 + + pkhtb r0,r1 + pkhtb r0,r1,asr 3 + pkhtb r0,r1,r2 + pkhtb r0,r1,r2,asr 3 + + qadd r0,r1 + qadd r0,r1,r2 + + qadd16 r0,r1 + qadd16 r0,r1,r2 + + qadd8 r0,r1 + qadd8 r0,r1,r2 + + qaddsubx r0,r1 + qaddsubx r0,r1,r2 + + qasx r0,r1 + qasx r0,r1,r2 + + qdadd r0,r1 + qdadd r0,r1,r2 + + qdsub r0,r1 + qdsub r0,r1,r2 + + qsub r0,r1 + qsub r0,r1,r2 + + qsax r0,r1 + qsax r0,r1,r2 + + qsub16 r0,r1 + qsub16 r0,r1,r2 + + qsub8 r0,r1 + qsub8 r0,r1,r2 + + qsubaddx r0,r1 + qsubaddx r0,r1,r2 + + rfe r0 + rfe r0! + + rfedb r0 + rfedb r0! + + rfeea r0 + rfeea r0! + + rfefd r0 + rfefd r0! + + rfeia r0 + rfeia r0! + + sadd16 r0,r1 + sadd16 r0,r1,r2 + + sadd8 r0,r1 + sadd8 r0,r1,r2 + + saddsubx r0,r1 + saddsubx r0,r1,r2 + + sasx r0,r1 + sasx r0,r1,r2 + + sel r0,r1 + sel r0,r1,r2 + + shadd16 r0,r1 + shadd16 r0,r1,r2 + + shadd8 r0,r1 + shadd8 r0,r1,r2 + + shaddsubx r0,r1 + shaddsubx r0,r1,r2 + + shasx r0,r1 + shasx r0,r1,r2 + + shsax r0,r1 + shsax r0,r1,r2 + + shsub16 r0,r1 + shsub16 r0,r1,r2 + + shsub8 r0,r1 + shsub8 r0,r1,r2 + + shsubaddx r0,r1 + shsubaddx r0,r1,r2 + + smlad r0,r1,r2,r3 + + smladx r0,r1,r2,r3 + + smlabb r0,r1,r2,r3 + + smlabt r0,r1,r2,r3 + + smlalbb r0,r1,r2,r3 + + smlalbt r0,r1,r2,r3 + + smlald r0,r1,r2,r3 + + smlaldx r0,r1,r2,r3 + + smlaltb r0,r1,r2,r3 + + smlaltt r0,r1,r2,r3 + + smlatb r0,r1,r2,r3 + + smlatt r0,r1,r2,r3 + + smlawb r0,r1,r2,r3 + + smlawt r0,r1,r2,r3 + + smlsd r0,r1,r2,r3 + + smlsdx r0,r1,r2,r3 + + smlsld r0,r1,r2,r3 + + smlsldx r0,r1,r2,r3 + + smmla r0,r1,r2,r3 + + smmlar r0,r1,r2,r3 + + smmls r0,r1,r2,r3 + + smmlsr r0,r1,r2,r3 + + smmul r0,r1 + smmul r0,r1,r2 + + smmulr r0,r1 + smmulr r0,r1,r2 + + smuad r0,r1 + smuad r0,r1,r2 + + smuadx r0,r1 + smuadx r0,r1,r2 + + smulbb r0,r1 + smulbb r0,r1,r2 + + smulbt r0,r1 + smulbt r0,r1,r2 + + smultb r0,r1 + smultb r0,r1,r2 + + smultt r0,r1 + smultt r0,r1,r2 + + smulwb r0,r1 + smulwb r0,r1,r2 + + smulwt r0,r1 + smulwt r0,r1,r2 + + smusd r0,r1 + smusd r0,r1,r2 + + smusdx r0,r1 + smusdx r0,r1,r2 + + srs 0 + srs 0 ! + srs sp,0 + srs sp!,0 + + srsdb 0 + srsdb 0 ! + srsdb sp,0 + srsdb sp!,0 + + srsea 0 + srsea 0 ! + srsea sp,0 + srsea sp!,0 + + srsfd 0 + srsfd 0 ! + srsfd sp,0 + srsfd sp!,0 + + srsia 0 + srsia 0 ! + srsia sp,0 + srsia sp!,0 + + ssat r0,1,r2 + ssat r0,1,r2,lsl 3 + ssat r0,1,r2,asr 3 + + ssat16 r0,1,r2 + + ssax r0,r1 + ssax r0,r1,r2 + + ssub16 r0,r1 + ssub16 r0,r1,r2 + + ssub8 r0,r1 + ssub8 r0,r1,r2 + + ssubaddx r0,r1 + ssubaddx r0,r1,r2 + + sxtab r0,r1,r2 + sxtab r0,r1,r2,ror 8 + + sxtab16 r0,r1,r2 + sxtab16 r0,r1,r2,ror 8 + + sxtah r0,r1,r2 + sxtah r0,r1,r2,ror 8 + + sxtb16 r0,r1 + sxtb16 r0,r1,ror 8 + + uadd16 r0,r1 + uadd16 r0,r1,r2 + + uadd8 r0,r1 + uadd8 r0,r1,r2 + + uaddsubx r0,r1 + uaddsubx r0,r1,r2 + + uasx r0,r1 + uasx r0,r1,r2 + + uhadd16 r0,r1 + uhadd16 r0,r1,r2 + + uhadd8 r0,r1 + uhadd8 r0,r1,r2 + + uhaddsubx r0,r1 + uhaddsubx r0,r1,r2 + + uhasx r0,r1 + uhasx r0,r1,r2 + + uhsax r0,r1 + uhsax r0,r1,r2 + + uhsub16 r0,r1 + uhsub16 r0,r1,r2 + + uhsub8 r0,r1 + uhsub8 r0,r1,r2 + + uhsubaddx r0,r1 + uhsubaddx r0,r1,r2 + + umaal r0,r1,r2,r3 + + uqadd16 r0,r1 + uqadd16 r0,r1,r2 + + uqadd8 r0,r1 + uqadd8 r0,r1,r2 + + uqaddsubx r0,r1 + uqaddsubx r0,r1,r2 + + uqasx r0,r1 + uqasx r0,r1,r2 + + uqsax r0,r1 + uqsax r0,r1,r2 + + uqsub16 r0,r1 + uqsub16 r0,r1,r2 + + uqsub8 r0,r1 + uqsub8 r0,r1,r2 + + uqsubaddx r0,r1 + uqsubaddx r0,r1,r2 + + usad8 r0,r1,r2 + + usada8 r0,r1,r2,r3 + + usat r0,1,r2 + usat r0,1,r2,lsl 3 + usat r0,1,r2,asr 3 + + usat16 r0,1,r2 + + usax r0,r1 + usax r0,r1,r2 + + usub16 r0,r1 + usub16 r0,r1,r2 + + usub8 r0,r1 + usub8 r0,r1,r2 + + usubaddx r0,r1 + usubaddx r0,r1,r2 + + uxtab r0,r1,r2 + uxtab r0,r1,r2,ror 8 + + uxtab16 r0,r1,r2 + uxtab16 r0,r1,r2,ror 8 + + uxtah r0,r1,r2 + uxtah r0,r1,r2,ror 8 + + uxtb16 r0,r1 + uxtb16 r0,r1,ror 8 + +processor CPU32_V7 + + ldrexd r0,[r2] + ldrexd r0,r1,[r2] + + label_pli_t32: + pli [r1] + pli [r1,2] + pli [r1,r2] + pli [r1,r2,lsl 3] + pli [label_pli_t32] + pli [expression.byte] + + strexd r0,r1,[r3] + strexd r0,r1,r2,[r3] + +processor CPU32_SYNC + + ldrexb r0,[r1] + ldrexb r0,[r1,0] + ldrexb r0,byte[expression.dword] + + ldrexh r0,[r1] + ldrexh r0,[r1,0] + ldrexh r0,hword[expression.dword] + + strexb r0,r1,[r2] + strexb r0,r1,[r2,0] + strexb r0,r1,byte[expression.dword] + + strexh r0,r1,[r2] + strexh r0,r1,[r2,0] + strexh r0,r1,hword[expression.dword] + +processor CPU32_DIV + + sdiv r0,r1 + sdiv r0,r1,r2 + + udiv r0,r1 + udiv r0,r1,r2 + +processor CPU32_T2EE + + enterx + + leavex + +processor CPU32_MP + + pldw [r1] + pldw [r1,2] + pldw [r1,r2] + pldw [r1,r2,lsl 3] + pldw [expression.byte] + +processor CPU32_V8 + + dcps1 + dcps2 + dcps3 + + lda r0,[r1] + ldab r0,[r1] + ldah r0,[r1] + + ldaex r0,[r1] + ldaexb r0,[r1] + ldaexh r0,[r1] + ldaexd r0,[r2] + ldaexd r0,r1,[r2] + + sevl.w + + stl r0,[r1] + stlb r0,[r1] + stlh r0,[r1] + + stlex r2,r0,[r3] + stlexb r2,r0,[r3] + stlexh r2,r0,[r3] + stlexd r2,r0,[r3] + stlexd r2,r0,r1,[r3] + +processor CPU32_CRC + + crc32b r0,r1,r2 + crc32h r0,r1,r2 + crc32w r0,r1,r2 + + crc32cb r0,r1,r2 + crc32ch r0,r1,r2 + crc32cw r0,r1,r2 diff --git a/armdoc/InstructionFormatsVFP.asm b/armdoc/InstructionFormatsVFP.asm new file mode 100644 index 0000000..1cb7b40 --- /dev/null +++ b/armdoc/InstructionFormatsVFP.asm @@ -0,0 +1,1120 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;To avoid unnecessary repetition only ARM mode is used +;here. There is no change needed for THUMB mode except +;to specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;All instructions can be conditional. The condition code +;should be added at the end of the main opcode and +;before any size/type specifiers. For example: "addhi" +;and "vaddhi.i16". The syntax also supports the pre-UAL +;style of putting the condition before any modifiers +;like "s" or "fd". For example: "ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;VFP, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_VFP_V1xD + + fabss s0,s1 + + fadds s0,s1 + fadds s0,s1,s2 + + fcmpes s0,s1 + fcmpes s0,0.0 + + fcmpezs s0 + + fcmps s0,s1 + fcmps s0,0.0 + + fcmpzs s0 + + fcpys s0,s1 + + fdivs s0,s1 + fdivs s0,s1,s2 + + label_fldd: + fldd d0,[r1] + fldd d0,[r1,4] + fldd d0,[label_fldd] + fldd d0,[expression.word] + + fldmdbd r0!,{d0-d3} + + fldmdbs r0!,{s0-s3} + + fldmdbx r0!,{d0-d3} + + fldmead r0!,{d0-d3} + + fldmeas r0!,{s0-s3} + + fldmeax r0!,{d0-d3} + + fldmfdd r0,{d0-d3} + fldmfdd r0!,{d0-d3} + + fldmfds r0,{s0-s3} + fldmfds r0!,{s0-s3} + + fldmfdx r0,{d0-d3} + fldmfdx r0!,{d0-d3} + + fldmiad r0,{d0-d3} + fldmiad r0!,{d0-d3} + + fldmias r0,{s0-s3} + fldmias r0!,{s0-s3} + + fldmiax r0,{d0-d3} + fldmiax r0!,{d0-d3} + + fldmd r0,{d0-d3} + fldmd r0!,{d0-d3} + + fldms r0,{s0-s3} + fldms r0!,{s0-s3} + + fldmx r0,{d0-d3} + fldmx r0!,{d0-d3} + + label_flds: + flds s0,[r1] + flds s0,[r1,4] + flds s0,[label_flds] + flds s0,[expression.word] + + fmacs s0,s1,s2 + + fmdhr d0,r1 + + fmdlr d0,r1 + + fmrdh r0,d1 + + fmrdl r0,d1 + + fmrs r0,s1 + + fmrx r0,fpscr + + fmscs s0,s1,s2 + + fmsr s0,r1 + + fmstat + + fmuls s0,s1 + fmuls s0,s1,s2 + + fmxr fpscr,r1 + + fnegs s0,s1 + + fnmacs s0,s1,s2 + + fnmscs s0,s1,s2 + + fnmuls s0,s1 + fnmuls s0,s1,s2 + + fsqrts s0,s1 + + fstmdbd r0!,{d0-d3} + + fstmdbs r0!,{s0-s3} + + fstmdbx r0!,{d0-d3} + + fstmead r0,{d0-d3} + fstmead r0!,{d0-d3} + + fstmeas r0,{s0-s3} + fstmeas r0!,{s0-s3} + + fstmeax r0,{d0-d3} + fstmeax r0!,{d0-d3} + + fstmfdd r0!,{d0-d3} + + fstmfds r0!,{s0-s3} + + fstmfdx r0!,{d0-d3} + + fstmiad r0,{d0-d3} + fstmiad r0!,{d0-d3} + + fstmias r0,{s0-s3} + fstmias r0!,{s0-s3} + + fstmiax r0,{d0-d3} + fstmiax r0!,{d0-d3} + + fstmd r0,{d0-d3} + fstmd r0!,{d0-d3} + + fstms r0,{s0-s3} + fstms r0!,{s0-s3} + + fstmx r0,{d0-d3} + fstmx r0!,{d0-d3} + + label_fstd: + fstd d0,[r1] + fstd d0,[r1,4] + fstd d0,[label_fstd] + fstd d0,[expression.word] + + label_fsts: + fsts s0,[r1] + fsts s0,[r1,4] + fsts s0,[label_fsts] + fsts s0,[expression.word] + + fsubs s0,s1 + fsubs s0,s1,s2 + + fsitos s0,s1 + + ftosis s0,s1 + + ftosizs s0,s1 + + ftouis s0,s1 + + ftouizs s0,s1 + + fuitos s0,s1 + + vabs.f32 s0,s1 + + vadd.f32 s0,s1 + vadd.f32 s0,s1,s2 + + vcmp.f32 s0,0.0 + vcmp.f32 s0,s1 + + vcmpe.f32 s0,0.0 + vcmpe.f32 s0,s1 + + vcvt.f32.s32 s0,s1 + + vcvt.f32.u32 s0,s1 + + vcvt.s32.f32 s0,s1 + + vcvt.u32.f32 s0,s1 + + vcvtr.s32.f32 s0,s1 + + vcvtr.u32.f32 s0,s1 + + vdiv.f32 s0,s1 + vdiv.f32 s0,s1,s2 + + vldm r0!,{d0-d3} + vldm r0!,{s0-s3} + vldm r0,{d0-d3} + vldm r0,{s0-s3} + + vldm.32 r0!,{s0-s3} + vldm.32 r0,{s0-s3} + + vldm.64 r0!,{d0-d3} + vldm.64 r0,{d0-d3} + + vldmdb r0!,{d0-d3} + vldmdb r0!,{s0-s3} + + vldmdb.32 r0!,{s0-s3} + + vldmdb.64 r0!,{d0-d3} + + vldmea r0!,{d0-d3} + vldmea r0!,{s0-s3} + + vldmea.32 r0!,{s0-s3} + + vldmea.64 r0!,{d0-d3} + + vldmfd r0!,{d0-d3} + vldmfd r0!,{s0-s3} + vldmfd r0,{d0-d3} + vldmfd r0,{s0-s3} + + vldmfd.32 r0!,{s0-s3} + vldmfd.32 r0,{s0-s3} + + vldmfd.64 r0!,{d0-d3} + vldmfd.64 r0,{d0-d3} + + vldmia r0!,{d0-d3} + vldmia r0!,{s0-s3} + vldmia r0,{d0-d3} + vldmia r0,{s0-s3} + + vldmia.32 r0!,{s0-s3} + vldmia.32 r0,{s0-s3} + + vldmia.64 r0!,{d0-d3} + vldmia.64 r0,{d0-d3} + + label_vldr: + vldr d0,[expression.word] + vldr d0,[label_vldr] + vldr d0,[r1,4] + vldr d0,[r1] + vldr s0,[expression.word] + vldr s0,[label_vldr] + vldr s0,[r1,4] + vldr s0,[r1] + + label_vldr.32: + vldr.32 s0,[expression.word] + vldr.32 s0,[label_vldr.32] + vldr.32 s0,[r1,4] + vldr.32 s0,[r1] + + label_vldr.64: + vldr.64 d0,[expression.word] + vldr.64 d0,[label_vldr.64] + vldr.64 d0,[r1,4] + vldr.64 d0,[r1] + + vmla.f32 s0,s1,s2 + + vmls.f32 s0,s1,s2 + + vmov d0[1],r1 + vmov r0,d1[1] + vmov r0,s1 + vmov s0,r1 + + vmov.32 d0[1],r1 + vmov.32 r0,d1[1] + + vmov.f32 s0,s1 + + vmrs r0,fpscr + vmrs apsr_nzcv,fpscr + + vmsr fpscr,r1 + + vmul.f32 s0,s1 + vmul.f32 s0,s1,s2 + + vneg.f32 s0,s1 + + vnmla.f32 s0,s1,s2 + + vnmls.f32 s0,s1,s2 + + vnmul.f32 s0,s1 + vnmul.f32 s0,s1,s2 + + vpop {d0,d2,d1} + vpop {s0,s2,s1} + + vpush {d0,d2,d1} + vpush {s0,s2,s1} + + vsqrt.f32 s0,s1 + + vstm r0!,{d0-d3} + vstm r0!,{s0-s3} + vstm r0,{d0-d3} + vstm r0,{s0-s3} + + vstm.32 r0!,{s0-s3} + vstm.32 r0,{s0-s3} + + vstm.64 r0!,{d0-d3} + vstm.64 r0,{d0-d3} + + vstmdb r0!,{d0-d3} + vstmdb r0!,{s0-s3} + + vstmdb.32 r0!,{s0-s3} + + vstmdb.64 r0!,{d0-d3} + + vstmea r0!,{d0-d3} + vstmea r0!,{s0-s3} + vstmea r0,{d0-d3} + vstmea r0,{s0-s3} + + vstmea.32 r0!,{s0-s3} + vstmea.32 r0,{s0-s3} + + vstmea.64 r0!,{d0-d3} + vstmea.64 r0,{d0-d3} + + vstmfd r0!,{d0-d3} + vstmfd r0!,{s0-s3} + + vstmfd.32 r0!,{s0-s3} + + vstmfd.64 r0!,{d0-d3} + + vstmia r0!,{d0-d3} + vstmia r0!,{s0-s3} + vstmia r0,{d0-d3} + vstmia r0,{s0-s3} + + vstmia.32 r0!,{s0-s3} + vstmia.32 r0,{s0-s3} + + vstmia.64 r0!,{d0-d3} + vstmia.64 r0,{d0-d3} + + label_vstr: + vstr d0,[expression.word] + vstr d0,[label_vstr] + vstr d0,[r1,4] + vstr d0,[r1] + vstr s0,[expression.word] + vstr s0,[label_vstr] + vstr s0,[r1,4] + vstr s0,[r1] + + label_vstr.32: + vstr.32 s0,[expression.word] + vstr.32 s0,[label_vstr.32] + vstr.32 s0,[r1,4] + vstr.32 s0,[r1] + + label_vstr.64: + vstr.64 d0,[expression.word] + vstr.64 d0,[label_vstr.64] + vstr.64 d0,[r1,4] + vstr.64 d0,[r1] + + vsub.f32 s0,s1 + vsub.f32 s0,s1,s2 + +coprocessor COPRO_VFP_V1xD + COPRO_VFP_D32 + + label_fldd_d32: + fldd d20,[r1] + fldd d20,[r1,4] + fldd d20,[label_fldd_d32] + fldd d20,[expression.word] + + fldmdbd r0!,{d20-d23} + + fldmdbx r0!,{d20-d23} + + fldmead r0!,{d20-d23} + + fldmeax r0!,{d20-d23} + + fldmfdd r0,{d20-d23} + fldmfdd r0!,{d20-d23} + + fldmfdx r0,{d20-d23} + fldmfdx r0!,{d20-d23} + + fldmiad r0,{d20-d23} + fldmiad r0!,{d20-d23} + + fldmiax r0,{d20-d23} + fldmiax r0!,{d20-d23} + + fldmd r0,{d20-d23} + fldmd r0!,{d20-d23} + + fldmx r0,{d20-d23} + fldmx r0!,{d20-d23} + + fmdhr d20,r1 + + fmdlr d20,r1 + + fmrdh r0,d21 + + fmrdl r0,d21 + + fstmdbd r0!,{d20-d23} + + fstmdbx r0!,{d20-d23} + + fstmead r0,{d20-d23} + fstmead r0!,{d20-d23} + + fstmeax r0,{d20-d23} + fstmeax r0!,{d20-d23} + + fstmfdd r0!,{d20-d23} + + fstmfdx r0!,{d20-d23} + + fstmiad r0,{d20-d23} + fstmiad r0!,{d20-d23} + + fstmiax r0,{d20-d23} + fstmiax r0!,{d20-d23} + + fstmd r0,{d20-d23} + fstmd r0!,{d20-d23} + + fstmx r0,{d20-d23} + fstmx r0!,{d20-d23} + + label_fstd_d32: + fstd d20,[r1] + fstd d20,[r1,4] + fstd d20,[label_fstd_d32] + fstd d20,[expression.word] + + vldm r0!,{d20-d23} + vldm r0,{d20-d23} + + vldm.64 r0!,{d20-d23} + vldm.64 r0,{d20-d23} + + vldmdb r0!,{d20-d23} + + vldmdb.64 r0!,{d20-d23} + + vldmea r0!,{d20-d23} + + vldmea.64 r0!,{d20-d23} + + vldmfd r0!,{d20-d23} + vldmfd r0,{d20-d23} + + vldmfd.64 r0!,{d20-d23} + vldmfd.64 r0,{d20-d23} + + vldmia r0!,{d20-d23} + vldmia r0,{d20-d23} + + vldmia.64 r0!,{d20-d23} + vldmia.64 r0,{d20-d23} + + label_vldr_d32: + vldr d20,[expression.word] + vldr d20,[label_vldr_d32] + vldr d20,[r1,4] + vldr d20,[r1] + + label_vldr.64_d32: + vldr.64 d20,[expression.word] + vldr.64 d20,[label_vldr.64_d32] + vldr.64 d20,[r1,4] + vldr.64 d20,[r1] + + vmov d20[0],r1 + vmov r0,d21[0] + + vmov.32 d20[0],r1 + vmov.32 r0,d21[0] + + vpop {d5-d20} + + vpush {d5-d20} + + vstm r0!,{d20-d23} + vstm r0,{d20-d23} + + vstm.64 r0!,{d20-d23} + vstm.64 r0,{d20-d23} + + vstmdb r0!,{d20-d23} + + vstmdb.64 r0!,{d20-d23} + + vstmea r0!,{d20-d23} + vstmea r0,{d20-d23} + + vstmea.64 r0!,{d20-d23} + vstmea.64 r0,{d20-d23} + + vstmfd r0!,{d20-d23} + + vstmfd.64 r0!,{d20-d23} + + vstmia r0!,{d20-d23} + vstmia r0,{d20-d23} + + vstmia.64 r0!,{d20-d23} + vstmia.64 r0,{d20-d23} + + label_vstr_d32: + vstr d20,[expression.word] + vstr d20,[label_vstr_d32] + vstr d20,[r1,4] + vstr d20,[r1] + + label_vstr.64_d32: + vstr.64 d20,[expression.word] + vstr.64 d20,[label_vstr.64_d32] + vstr.64 d20,[r1,4] + vstr.64 d20,[r1] + +coprocessor COPRO_VFP_V1 + + fabsd d0,d1 + + faddd d0,d1 + faddd d0,d1,d2 + + fcmpd d0,d1 + fcmpd d0,0.0 + + fcmped d0,d1 + fcmped d0,0.0 + + fcmpezd d0 + + fcmpzd d0 + + fcpyd d0,d1 + + fcvtds d0,s1 + + fcvtsd s0,d1 + + fdivd d0,d1 + fdivd d0,d1,d2 + + fmacd d0,d1,d2 + + fmscd d0,d1,d2 + + fmuld d0,d1 + fmuld d0,d1,d2 + + fnegd d0,d1 + + fnmacd d0,d1,d2 + + fnmscd d0,d1,d2 + + fnmuld d0,d1 + fnmuld d0,d1,d2 + + fsitod d0,s1 + + fsqrtd d0,d1 + + fsubd d0,d1 + fsubd d0,d1,d2 + + ftosid s0,d1 + + ftosizd s0,d1 + + ftouid s0,d1 + + ftouizd s0,d1 + + fuitod d0,s0 + + vabs.f64 d0,d1 + + vadd.f64 d0,d1 + vadd.f64 d0,d1,d2 + + vcmp.f64 d0,0.0 + vcmp.f64 d0,d1 + + vcmpe.f64 d0,0.0 + vcmpe.f64 d0,d1 + + vcvt.f32.f64 s0,d1 + + vcvt.f64.f32 d0,s1 + + vcvt.f64.s32 d0,s1 + + vcvt.f64.u32 d0,s0 + + vcvt.s32.f64 s0,d1 + + vcvt.u32.f64 s0,d1 + + vcvtr.s32.f64 s0,d1 + + vcvtr.u32.f64 s0,d1 + + vdiv.f64 d0,d1 + vdiv.f64 d0,d1,d2 + + vmla.f64 d0,d1,d2 + + vmls.f64 d0,d1,d2 + + vmov.f64 d0,d1 + + vmul.f64 d0,d1 + vmul.f64 d0,d1,d2 + + vneg.f64 d0,d1 + + vnmla.f64 d0,d1,d2 + + vnmls.f64 d0,d1,d2 + + vnmul.f64 d0,d1 + vnmul.f64 d0,d1,d2 + + vsqrt.f64 d0,d1 + + vsub.f64 d0,d1 + vsub.f64 d0,d1,d2 + +coprocessor COPRO_VFP_V1 + COPRO_VFP_D32 + + fabsd d20,d21 + + faddd d20,d21 + faddd d20,d21,d22 + + fcmpd d20,d21 + fcmpd d20,0.0 + + fcmped d20,d21 + fcmped d20,0.0 + + fcmpezd d20 + + fcmpzd d20 + + fcpyd d20,d21 + + fcvtds d20,s1 + + fcvtsd s0,d21 + + fdivd d20,d21 + fdivd d20,d21,d22 + + fmacd d20,d21,d22 + + fmscd d20,d21,d22 + + fmuld d20,d21 + fmuld d20,d21,d22 + + fnegd d20,d21 + + fnmacd d20,d21,d22 + + fnmscd d20,d21,d22 + + fnmuld d20,d21 + fnmuld d20,d21,d22 + + fsitod d20,s1 + + fsqrtd d20,d21 + + fsubd d20,d21 + fsubd d20,d21,d22 + + ftosid s0,d21 + + ftosizd s0,d21 + + ftouid s0,d21 + + ftouizd s0,d21 + + fuitod d20,s0 + + vabs.f64 d20,d21 + + vadd.f64 d20,d21 + vadd.f64 d20,d21,d22 + + vcmp.f64 d20,0.0 + vcmp.f64 d20,d21 + + vcmpe.f64 d20,0.0 + vcmpe.f64 d20,d21 + + vcvt.f32.f64 s0,d21 + + vcvt.f64.f32 d20,s1 + + vcvt.f64.s32 d20,s1 + + vcvt.f64.u32 d20,s0 + + vcvt.s32.f64 s0,d21 + + vcvt.u32.f64 s0,d21 + + vcvtr.s32.f64 s0,d21 + + vcvtr.u32.f64 s0,d21 + + vdiv.f64 d20,d21 + vdiv.f64 d20,d21,d22 + + vmla.f64 d20,d21,d22 + + vmls.f64 d20,d21,d22 + + vmov.f64 d20,d21 + + vmul.f64 d20,d21 + vmul.f64 d20,d21,d22 + + vneg.f64 d20,d21 + + vnmla.f64 d20,d21,d22 + + vnmls.f64 d20,d21,d22 + + vnmul.f64 d20,d21 + vnmul.f64 d20,d21,d22 + + vsqrt.f64 d20,d21 + + vsub.f64 d20,d21 + vsub.f64 d20,d21,d22 + +coprocessor COPRO_VFP_V2 + + fmdrr d0,r1,r2 + + fmrrd r0,r1,d2 + + fmrrs r0,r1,{s2,s3} + + fmsrr {s0,s1},r2,r3 + + vmov d0,r1,r2 + vmov r0,r1,d2 + vmov r0,r1,s2,s3 + vmov s0,s1,r2,r3 + +coprocessor COPRO_VFP_V2 + COPRO_VFP_D32 + + fmdrr d20,r1,r2 + + fmrrd r0,r1,d22 + + vmov d20,r1,r2 + vmov r0,r1,d22 + +coprocessor COPRO_VFP_V3 + + fconsts s0,1.0 + fconsts s0,1 + + fconstd d0,1.0 + fconstd d0,1 + + fshtod d0,1 + fshtod d0,d0,1 + + fshtos s0,1 + fshtos s0,s0,1 + + fsltod d0,1 + fsltod d0,d0,1 + + fsltos s0,1 + fsltos s0,s0,1 + + ftoshd d0,1 + ftoshd d0,d0,1 + + ftoshs s0,1 + ftoshs s0,s0,1 + + ftosld d0,1 + ftosld d0,d0,1 + + ftosls s0,1 + ftosls s0,s0,1 + + ftouhd d0,1 + ftouhd d0,d0,1 + + ftouhs s0,1 + ftouhs s0,s0,1 + + ftould d0,1 + ftould d0,d0,1 + + ftouls s0,1 + ftouls s0,s0,1 + + fuhtod d0,1 + fuhtod d0,d0,1 + + fuhtos s0,1 + fuhtos s0,s0,1 + + fultod d0,1 + fultod d0,d0,1 + + fultos s0,1 + fultos s0,s0,1 + + vcvt.f32.s16 s0,1 + vcvt.f32.s16 s0,s0,1 + + vcvt.f32.s32 s0,1 + vcvt.f32.s32 s0,s0,1 + + vcvt.f32.u16 s0,1 + vcvt.f32.u16 s0,s0,1 + + vcvt.f32.u32 s0,1 + vcvt.f32.u32 s0,s0,1 + + vcvt.f64.s16 d0,1 + vcvt.f64.s16 d0,d0,1 + + vcvt.f64.s32 d0,3 + vcvt.f64.s32 d0,d0,3 + + vcvt.f64.u16 d0,1 + vcvt.f64.u16 d0,d0,1 + + vcvt.f64.u32 d0,3 + vcvt.f64.u32 d0,d0,3 + + vcvt.s16.f32 s0,1 + vcvt.s16.f32 s0,s0,1 + + vcvt.s16.f64 d0,1 + vcvt.s16.f64 d0,d0,1 + + vcvt.s32.f32 s0,1 + vcvt.s32.f32 s0,s0,1 + + vcvt.s32.f64 d0,3 + vcvt.s32.f64 d0,d0,3 + + vcvt.u16.f32 s0,1 + vcvt.u16.f32 s0,s0,1 + + vcvt.u16.f64 d0,1 + vcvt.u16.f64 d0,d0,1 + + vcvt.u32.f32 s0,1 + vcvt.u32.f32 s0,s0,1 + + vcvt.u32.f64 d0,3 + vcvt.u32.f64 d0,d0,3 + + vmov.f32 s0,1 + vmov.f32 s0,1.0 + + vmov.f64 d0,1 + vmov.f64 d0,1.0 + +coprocessor COPRO_VFP_V3 + COPRO_VFP_D32 + + fconstd d20,1.0 + fconstd d20,1 + + fshtod d20,1 + fshtod d20,d20,1 + + fsltod d20,1 + fsltod d20,d20,1 + + ftoshd d20,1 + ftoshd d20,d20,1 + + ftosld d20,1 + ftosld d20,d20,1 + + ftouhd d20,1 + ftouhd d20,d20,1 + + ftould d20,1 + ftould d20,d20,1 + + fuhtod d20,1 + fuhtod d20,d20,1 + + fultod d20,1 + fultod d20,d20,1 + + vcvt.f64.s16 d20,1 + vcvt.f64.s16 d20,d20,1 + + vcvt.f64.s32 d20,1 + vcvt.f64.s32 d20,d20,1 + + vcvt.f64.u16 d20,1 + vcvt.f64.u16 d20,d20,1 + + vcvt.f64.u32 d20,1 + vcvt.f64.u32 d20,d20,1 + + vcvt.s16.f64 d20,1 + vcvt.s16.f64 d20,d20,1 + + vcvt.s32.f64 d20,1 + vcvt.s32.f64 d20,d20,1 + + vcvt.u16.f64 d20,1 + vcvt.u16.f64 d20,d20,1 + + vcvt.u32.f64 d20,1 + vcvt.u32.f64 d20,d20,1 + + vmov.f64 d20,1 + vmov.f64 d20,1.0 + +coprocessor COPRO_VFP_HP + + vcvtb.f32.f16 s0,s1 + + vcvtb.f16.f32 s0,s1 + + vcvtt.f32.f16 s0,s1 + + vcvtt.f16.f32 s0,s1 + +coprocessor COPRO_VFP_V4 + + vfma.f32 s0,s1,s2 + + vfma.f64 d0,d1,d2 + + vfms.f32 s0,s1,s2 + + vfms.f64 d0,d1,d2 + + vfnma.f32 s0,s1,s2 + + vfnma.f64 d0,d1,d2 + + vfnms.f32 s0,s1,s2 + + vfnms.f64 d0,d1,d2 + +coprocessor COPRO_VFP_V4 + COPRO_VFP_D32 + + vfma.f64 d20,d21,d22 + + vfnma.f64 d20,d21,d22 + + vfms.f64 d20,d21,d22 + + vfnms.f64 d20,d21,d22 + +coprocessor COPRO_SIMD_V8 + + vcvtm.s32.f32 s0,s1 + vcvtm.u32.f32 s0,s1 + vcvtm.s32.f64 s0,d1 + vcvtm.u32.f64 s0,d1 + + vcvtp.s32.f32 s0,s1 + vcvtp.u32.f32 s0,s1 + vcvtp.s32.f64 s0,d1 + vcvtp.u32.f64 s0,d1 + + vcvtn.s32.f32 s0,s1 + vcvtn.u32.f32 s0,s1 + vcvtn.s32.f64 s0,d1 + vcvtn.u32.f64 s0,d1 + + vcvta.s32.f32 s0,s1 + vcvta.u32.f32 s0,s1 + vcvta.s32.f64 s0,d1 + vcvta.u32.f64 s0,d1 + + vcvtb.f16.f64 s0,d1 + vcvtb.f64.f16 d0,s1 + + vcvtt.f16.f64 s0,d1 + vcvtt.f64.f16 d0,s1 + + vmaxnm.f32 s0,s1,s2 + vmaxnm.f64 d0,d1,d2 + + vminnm.f32 s0,s1,s2 + vminnm.f64 d0,d1,d2 + + vrintm.f32.f32 s0,s1 + vrintm.f64.f64 d0,d1 + + vrintp.f32.f32 s0,s1 + vrintp.f64.f64 d0,d1 + + vrintn.f32.f32 s0,s1 + vrintn.f64.f64 d0,d1 + + vrinta.f32.f32 s0,s1 + vrinta.f64.f64 d0,d1 + + vrintx.f32.f32 s0,s1 + vrintx.f64.f64 d0,d1 + + vrintz.f32.f32 s0,s1 + vrintz.f64.f64 d0,d1 + + vrintr.f32.f32 s0,s1 + vrintr.f64.f64 d0,d1 + + vseleq.f32 s0,s1,s2 + vseleq.f64 d0,d1,d2 + + vselvs.f32 s0,s1,s2 + vselvs.f64 d0,d1,d2 + + vselge.f32 s0,s1,s2 + vselge.f64 d0,d1,d2 + + vselgt.f32 s0,s1,s2 + vselgt.f64 d0,d1,d2 diff --git a/armdoc/InstructionFormatsXSCALE.asm b/armdoc/InstructionFormatsXSCALE.asm new file mode 100644 index 0000000..0338e3e --- /dev/null +++ b/armdoc/InstructionFormatsXSCALE.asm @@ -0,0 +1,101 @@ +;This document is intended to show the basic formats for +;all of the instructions supported by fasmarm. + +;These formats are divided into sections showing the CPU +;processor directive needed to enable the instruction. + +;Opcodes are listed in alphabetical order within each +;section. A blank line separates each opcode from the +;next. + +;Instructions can appear in many places. Different +;versions of the instruction set can allow for different +;sets of available parameters so be sure to check for +;instructions listed in more than one place. If you are +;having trouble working out what format fasmarm is +;expecting then you can search through here for all +;instances to find the situation that matches your code. + +;Coprocessor formats are divided firstly by the +;coprocessor type and secondly by the implementation +;version. Coprocessor instructions are available in both +;ARM and THUMB modes and use the same format for both. +;There is no change needed for THUMB mode except to +;specify that the processor supports version 7M +;architecture instructions. + +;The example codes given here are merely indicative of +;which parameters go where. They are not intended as an +;enumeration of all possible allowed values of the +;parameters. Usually only one register or one immediate +;value for each parameter is given so as to show what +;type of parameter is expected at each position. If you +;try to assemble a value that is undefined, +;unpredictable or not encodable fasmarm will give a +;short error message complaining that the parameter is +;invalid. + +;These instructions do not show any condition syntax. +;All instructions can be conditional. The condition code +;should be added at the end of the main opcode and +;before any size/type specifiers. For example: "addhi" +;and "vaddhi.i16". The syntax also supports the pre-UAL +;style of putting the condition before any modifiers +;like "s" or "fd". For example: "ldmhifd", "ldmfdhi". + +;This file can be assembled by fasmarm. + +virtual at r1 + expression.dword rd 1 + expression.word rw 1 + expression.hword rh 1 + expression.byte rb 1 +end virtual + + ;*********************************************** + ;xScale, ARM mode, all instructions are 32-bit + ;*********************************************** + + code32 + +coprocessor COPRO_XSCALE + + mia acc0,r1,r2 + + miaph acc0,r1,r2 + + miabb acc0,r1,r2 + + miabt acc0,r1,r2 + + miatb acc0,r1,r2 + + miatt acc0,r1,r2 + + mar acc0,r1,r2 + + mra r0,r1,acc0 + + ;*********************************************** + ;xScale, THUMB mode, all instructions are 32-bit + ;*********************************************** + +processor CPU32_7M + + thumb + + mia acc0,r1,r2 + + miaph acc0,r1,r2 + + miabb acc0,r1,r2 + + miabt acc0,r1,r2 + + miatb acc0,r1,r2 + + miatt acc0,r1,r2 + + mar acc0,r1,r2 + + mra r0,r1,acc0 diff --git a/examples/arm64/armpe64.asm b/examples/arm64/armpe64.asm new file mode 100644 index 0000000..e1ae1a6 --- /dev/null +++ b/examples/arm64/armpe64.asm @@ -0,0 +1,40 @@ +format pe64 gui nx at 0x140000000 +processor cpu64_v8 + +section '.text' code executable + +entry $ + mov x0,xzr + adr x1,hello + adr x2,title + mov x3,xzr + ldr x8,[MessageBox] + blr x8 + mov x0,xzr + ldr x8,[ExitProcess] + blr x8 + +section '.data' data readable + + hello db 'Hello, Win64 ARM world!',0 + title db 'Win64 ARM',0 + +section '.idata' import data readable + + dw 0,0,0,rva user_name,rva user_table + dw 0,0,0,rva kernel_name,rva kernel_table + dw 0,0,0,0,0 + + user_name db 'user32.dll',0 + kernel_name db 'kernel32.dll',0 + + sMessageBox db 0,0,'MessageBoxA',0 + sExitProcess db 0,0,'ExitProcess',0 + + align 8 + user_table: + MessageBox dd rva sMessageBox + dd 0 + kernel_table: + ExitProcess dd rva sExitProcess + dd 0 diff --git a/examples/arm64/armpe64.exe b/examples/arm64/armpe64.exe new file mode 100644 index 0000000..700afa7 Binary files /dev/null and b/examples/arm64/armpe64.exe differ diff --git a/examples/arm64/semihosting.asm b/examples/arm64/semihosting.asm new file mode 100644 index 0000000..7f9bb71 --- /dev/null +++ b/examples/arm64/semihosting.asm @@ -0,0 +1,68 @@ +SemiHosting = 0xf000 +SYS_WRITEC = 3 +SYS_WRITE0 = 4 +ADP_Stopped_ApplicationExit = 0x20026 +angel_SWIreason_ReportException = 0x18 + + processor cpu64_v8 + code64 + + adr x0,stack_base + mov sp,x0 + adr x1,hello_world + bl show_string + + adr x1,running_at + bl show_string + adr x0,$$ + bl show_hex + + adr x1,exec_level + bl show_string + mrs x0,CurrentEL + ubfx x0,x0,2,2 + bl show_hex + + movz x1,ADP_Stopped_ApplicationExit and 0xffff + movk x1,ADP_Stopped_ApplicationExit and 0xffff shl 16 + stp x1,xzr,[sp,-16]! + mov x1,sp + mov x0,angel_SWIreason_ReportException + hlt SemiHosting + +show_hex: + ;x0 = the value + clz x2,x0 + bic x2,x2,3 + lslv x3,x0,x2 + sub sp,sp,16 + .loop: + ror x3,x3,64-4 + and x1,x3,0xf + cmp x1,9 + add x0,x1,'A'-10 + add x1,x1,'0' + csel x1,x1,x0,ls + strb w1,[sp] + mov x1,sp + mov x0,SYS_WRITEC + hlt SemiHosting + add x2,x2,4 + tbz x2,6,.loop + add sp,sp,16 +show_crlf: + adr x1,crlf +show_string: + ;x1 = the string + mov x0,SYS_WRITE0 + hlt SemiHosting + ret + +hello_world: db 'Hello World!',13,10 +crlf: db 13,10,0 +running_at: db ' Start address: 0x',0 +exec_level: db 'Execution level: ',0 + + align 16 + rb 0x20 +stack_base: diff --git a/examples/arm64/semihosting.bin b/examples/arm64/semihosting.bin new file mode 100644 index 0000000..d3dc692 Binary files /dev/null and b/examples/arm64/semihosting.bin differ diff --git a/examples/armdwarf/armdwarf.asm b/examples/armdwarf/armdwarf.asm new file mode 100644 index 0000000..cdad5f8 --- /dev/null +++ b/examples/armdwarf/armdwarf.asm @@ -0,0 +1,13 @@ + format ELF dwarf executable at 0 + entry start + section 'one' executable readable writeable align 020h + +start: mov r1,string_hello + mov r0,4 ;SYS_WRITE0 + swi 0x123456 ;Multi-ICE DCC semihosting + mov r0,18h ;angel_SWIreason_ReportException + mov r1,20000h ;Software reason code + orr r1,r1,26h ;ADP_Stopped_ApplicationExit + swi 0x123456 ;Multi-ICE DCC semihosting + +string_hello db 'Hello ARM semi-hosting world',13,10,0 diff --git a/examples/armdwarf/armdwarf.axf b/examples/armdwarf/armdwarf.axf new file mode 100755 index 0000000..dfc5920 Binary files /dev/null and b/examples/armdwarf/armdwarf.axf differ diff --git a/examples/armelf/armelf b/examples/armelf/armelf new file mode 100755 index 0000000..cf1ead1 Binary files /dev/null and b/examples/armelf/armelf differ diff --git a/examples/armelf/armelf.asm b/examples/armelf/armelf.asm new file mode 100644 index 0000000..adf397c --- /dev/null +++ b/examples/armelf/armelf.asm @@ -0,0 +1,17 @@ + format ELF executable + entry start + + segment readable executable + +start: mov r0,0 + add r1,pc,hello-$-8 + mov r2,hello_len + swi 0x900004 + mov r0,6 + swi 0x900001 + +hello: db 'Hello world',10 +hello_len=$-hello + + ;dummy section for bss, see http://board.flatassembler.net/topic.php?t=3689 + segment writeable diff --git a/examples/armpe/armpe.asm b/examples/armpe/armpe.asm new file mode 100644 index 0000000..0a84be9 --- /dev/null +++ b/examples/armpe/armpe.asm @@ -0,0 +1,34 @@ + +; Example of building a WinCE executable using direct coding + + format PE GUI + entry Start + +section '.text' data code readable writeable executable + +Start: + mov r0,0 ;window owner (NULL) + adr r1,Text ;the text + adr r2,Caption ;the caption + mov r3,0 ;style (MB_OK) + ldr pc,[MessageBoxW] ;display message and exit + +Text du 'Hello WinCE world',0 +Caption du 'ARM small PE',0 + + align 4 + +data import + + dw RVA core_imports,0,0,RVA core_name,RVA core_imports + rw 5 + + core_imports: + MessageBoxW dw 0x8000035A + dw 0 + + core_name db 'COREDLL.DLL',0 + + align 4 + +end data diff --git a/examples/armpe/armpe.exe b/examples/armpe/armpe.exe new file mode 100644 index 0000000..3c5dc60 Binary files /dev/null and b/examples/armpe/armpe.exe differ diff --git a/examples/armpe/armpe2.asm b/examples/armpe/armpe2.asm new file mode 100644 index 0000000..23dd036 --- /dev/null +++ b/examples/armpe/armpe2.asm @@ -0,0 +1,21 @@ + +; Example of building a WinCE executable using medium level macros + + include 'wince.inc' + format PE GUI + entry Start + +section '.text' code readable executable + +proc Start uses[lr] + apscall MessageBoxW,0,addr Text,addr Caption,0 + ret +endp + +Caption du 'ARM example MLI macros',0 +Text du 'Hello ArmCE world',0 + +section '.idata' import readable writeable + + library coredll,'COREDLL.DLL' + include 'apice\coredll.inc' diff --git a/examples/armpe/armpe2.exe b/examples/armpe/armpe2.exe new file mode 100644 index 0000000..d9b9754 Binary files /dev/null and b/examples/armpe/armpe2.exe differ diff --git a/examples/armpe/armpe3.asm b/examples/armpe/armpe3.asm new file mode 100644 index 0000000..55f1aef --- /dev/null +++ b/examples/armpe/armpe3.asm @@ -0,0 +1,13 @@ + +; Example of building a WinCE executable using high level macros + + include 'wincex.inc' + +.code + +proc Start uses [lr] + apscall MessageBoxW,0,*'Hello ArmCE world',*'ARM example HLI macros',0 + ret +endp + +.end Start diff --git a/examples/armpe/armpe3.exe b/examples/armpe/armpe3.exe new file mode 100644 index 0000000..d904a66 Binary files /dev/null and b/examples/armpe/armpe3.exe differ diff --git a/examples/armpe/armpe4.asm b/examples/armpe/armpe4.asm new file mode 100644 index 0000000..a934201 --- /dev/null +++ b/examples/armpe/armpe4.asm @@ -0,0 +1,122 @@ + +; Example of building a simple WinCE application using high level macros + + include 'wincex.inc' + +.code + +proc Start base sp uses[r0-r12,r14] + locals + outbuff rb 0x400 + virtual + regs rw 14 + stack dw ? + end virtual + endl + mov v7,outbuff + mov v1,0 + .again: + mov a1,'R' + strh a1,[v7],2 + apscall itou32,v7,v1 + sub v7,a1,2 + apscall string_copy_atou32,v7,'=0x' + sub v7,a1,2 + cmp v1,13 + lealt v2,[regs] + ldrlt v3,[v2,v1,lsl 2] ;Get registers R0-R12 + leaeq v3,[stack] ;Calculate original R13 (SP) + cmp v1,14 + ldreq v3,[regs+13*4] ;Get register R14 + leahi v3,[Start] ;Calculate original R15 (PC) + apscall htou32,v7,v3,8 + sub v7,a1,2 + apscall string_copy_atou32,v7,' (' + sub v7,a1,2 + apscall itou32,v7,v3 + sub v7,a1,2 + apscall string_copy_atou32,v7,<')',13,10> + sub v7,a1,2 + add v1,v1,1 + cmp v1,15 + bls .again + apscall MessageBoxW,0,addr outbuff,*'WinCE Start registers',0 + ret +endp + +proc string_copy_atou32 nospill,dest,source + .again: + ldrb a3,[source],1 + strh a3,[dest],2 + cmp a3,0 + bne .again + ret +endp + +proc itou32 nospill,dest,value + mov ip,0xffffffcd + and ip,ip,0xffffccff + mov a4,0 + add ip,ip,ip,lsl 16 ;ip=0xcccccccd == int(2^35/10+.5) + .next: + strb a4,[sp,-1]! + mov a3,value + umull a4,value,ip,value + movs value,value,lsr 3 ;value=quotient + sub a4,a3,value,lsl 3 + sub a4,a4,value,lsl 1 ;a4=remainder + add a4,a4,'0' + bne .next + .digit: + strh a4,[dest],2 + ldrb a4,[sp],1 + cmp a4,0 + bne .digit + strh a4,[dest],2 + ret +endp + +proc htou32 nospill,dest,value,nibbles + ;if "nibbles" is zero then leading zeros are suppressed + clz a4,value + rsb a4,a4,35 + cmp nibbles,8 + movhi nibbles,8 + cmp nibbles,0 + andeq nibbles,a4,not 3 + movne nibbles,nibbles,lsl 2 + .again: + sub nibbles,nibbles,4 + mov a4,value,ror nibbles + and a4,a4,0xf + add a4,a4,'0' + cmp a4,'9' + addhi a4,a4,'A'-'9'-1 + strh a4,[dest],2 + cmp nibbles,0 + bgt .again + mov a4,0 + strh a4,[dest],2 + ret +endp + +.end Start + +section '.rsrc' resource data readable + + RT_VERSION =16 + LANG_NEUTRAL =0 + LANG_ENGLISH =9 + SUBLANG_DEFAULT =400h + VOS__WINDOWS32 =4 + VFT_APP =1 + VFT2_UNKNOWN =0 + + directory RT_VERSION,versions + resource versions,1,LANG_NEUTRAL,version + versioninfo version,VOS__WINDOWS32,VFT_APP,VFT2_UNKNOWN,LANG_ENGLISH+SUBLANG_DEFAULT,0,\ + 'FileDescription','Demonstration of FASMARM for WinCE assembly',\ + 'LegalCopyright','Copyright (C) 2006, revolution',\ + 'FileVersion','0.0.0.0',\ + 'ProductVersion','0.0.0.0',\ + 'OriginalFilename','ARMPE4.EXE' diff --git a/examples/armpe/armpe4.exe b/examples/armpe/armpe4.exe new file mode 100644 index 0000000..965c9c9 Binary files /dev/null and b/examples/armpe/armpe4.exe differ diff --git a/fasmarm.exe b/fasmarm.exe new file mode 100755 index 0000000..6d4dbb3 Binary files /dev/null and b/fasmarm.exe differ diff --git a/fasmarm.o b/fasmarm.o new file mode 100644 index 0000000..aa78699 Binary files /dev/null and b/fasmarm.o differ diff --git a/fasmarm.orig-20250113 b/fasmarm.orig-20250113 new file mode 100755 index 0000000..30aa231 Binary files /dev/null and b/fasmarm.orig-20250113 differ diff --git a/fasmarm.x64 b/fasmarm.x64 new file mode 100755 index 0000000..edda42f Binary files /dev/null and b/fasmarm.x64 differ diff --git a/fasmwarm.exe b/fasmwarm.exe new file mode 100644 index 0000000..5181324 Binary files /dev/null and b/fasmwarm.exe differ diff --git a/include/apice/coredll.inc b/include/apice/coredll.inc new file mode 100644 index 0000000..6e7056b --- /dev/null +++ b/include/apice/coredll.inc @@ -0,0 +1,1231 @@ + +;Define WinCE ordinals for symbolic OS calls. +;By default this file is included from "WINCEX.INC". + +import coredll,\ + __2_YAPAXI_Z,0x80000447,\ + __3_YAXPAX_Z,0x80000446,\ + __addd,0x80000805,\ + __adds,0x80000803,\ + __C_specific_handler,0x80000057,\ + __cmpd,0x80000802,\ + __cmps,0x80000801,\ + __divd,0x80000800,\ + __divs,0x800007FF,\ + __dtoi,0x800007FE,\ + __dtoi64,0x800007FD,\ + __dtos,0x800007FC,\ + __dtou,0x800007FB,\ + __dtou64,0x800007FA,\ + __eqd,0x800007F9,\ + __eqs,0x800007F8,\ + __ged,0x800007F7,\ + __ges,0x800007F6,\ + __gtd,0x800007F5,\ + __gts,0x800007F4,\ + __i64tod,0x800007F3,\ + __i64tos,0x800007F2,\ + __itod,0x800007F1,\ + __itos,0x800007F0,\ + __led,0x800007EF,\ + __les,0x800007EE,\ + __ltd,0x800007ED,\ + __lts,0x800007EC,\ + __muld,0x800007EB,\ + __muls,0x800007EA,\ + __ned,0x800007E9,\ + __negd,0x800007E8,\ + __negs,0x800007E7,\ + __nes,0x800007E6,\ + __rt_div0,0x800007D4,\ + __rt_divtest,0x800007D7,\ + __rt_sdiv,0x800007D5,\ + __rt_sdiv10,0x800007D6,\ + __rt_sdiv64by64,0x800007D0,\ + __rt_srem64by64,0x800007D1,\ + __rt_srsh,0x800007DA,\ + __rt_udiv,0x800007D8,\ + __rt_udiv10,0x800007D9,\ + __rt_udiv64by64,0x800007D2,\ + __rt_urem64by64,0x800007D3,\ + __rt_ursh,0x800007DB,\ + __stod,0x800007E5,\ + __stoi,0x800007E4,\ + __stoi64,0x800007E3,\ + __stou,0x800007E2,\ + __stou64,0x800007E1,\ + __strgtold12,0x80000441,\ + __subd,0x800007E0,\ + __subs,0x800007DF,\ + __u64tod,0x800007DE,\ + __u64tos,0x800007DD,\ + __utod,0x800007DC,\ + __utos,0x80000804,\ + _atodbl,0x800003E4,\ + _atoflt,0x800003E5,\ + _cabs,0x800003E6,\ + _chgsign,0x800003E8,\ + _clearfp,0x800003E9,\ + _controlfp,0x800003EA,\ + _copysign,0x800003EB,\ + _DefaultImcGet__YAKXZ,0x800004C2,\ + _DefaultImeWndGet__YAPAUHWND____XZ,0x800004C3,\ + _ecvt,0x800003F0,\ + _ExitWindowsEx__YAHIK_Z,0x80000127,\ + _fcloseall,0x8000045F,\ + _fcvt,0x800003F3,\ + _fileno,0x80000464,\ + _finite,0x800003F4,\ + _fltused,0x80000445,\ + _flushall,0x80000463,\ + _fpclass,0x800003F7,\ + _fpieee_flt,0x800003F8,\ + _fpreset,0x800003F9,\ + _frnd,0x800003FC,\ + _fsqrt,0x800003FD,\ + _gcvt,0x800003FE,\ + _getstdfilex,0x8000044C,\ + _getws,0x80000472,\ + _HUGE,0x8000049D,\ + _hypot,0x800003FF,\ + _ImmGetUIClassName__YAXPAG_Z,0x800004C7,\ + _ImmProcessKey__YAKPAUHWND____IJKI_Z,0x800004C4,\ + _ImmSetActiveContext__YAHPAUHWND____KH_Z,0x80000326,\ + _ImmTranslateMessage__YAHPAUHWND____IIJHIIPAH_Z,0x800004C5,\ + _InitStdioLib,0x8000047F,\ + _isnan,0x80000400,\ + _itoa,0x80000401,\ + _itow,0x80000402,\ + _j0,0x80000403,\ + _j1,0x80000404,\ + _jn,0x80000405,\ + _ld12tod,0x8000043F,\ + _ld12tof,0x80000440,\ + _logb,0x8000040B,\ + _lrotl,0x8000040D,\ + _lrotr,0x8000040E,\ + _ltoa,0x8000040F,\ + _ltow,0x80000410,\ + _memccpy,0x80000412,\ + _memicmp,0x80000415,\ + _msize,0x80000419,\ + _nextafter,0x8000041A,\ + _purecall,0x80000444,\ + _putws,0x80000473,\ + _rotl,0x8000041F,\ + _rotr,0x80000420,\ + _scalb,0x80000421,\ + _setmode,0x800004A3,\ + _snprintf,0x800002D9,\ + _snwprintf,0x80000448,\ + _statusfp,0x80000426,\ + _swab,0x80000432,\ + _ultoa,0x80000437,\ + _ultow,0x80000438,\ + _vsnprintf,0x8000047B,\ + _vsnwprintf,0x8000046C,\ + _wcsdup,0x8000004A,\ + _wcsicmp,0x800000E6,\ + _wcslwr,0x800000E7,\ + _wcsnicmp,0x800000E5,\ + _wcsnset,0x80000043,\ + _wcsrev,0x80000046,\ + _wcsset,0x80000047,\ + _wcsupr,0x800000E8,\ + _wfdopen,0x8000045D,\ + _wfopen,0x80000479,\ + _wfreopen,0x800004B1,\ + _wtol,0x8000004E,\ + _wtoll,0x8000004F,\ + _y0,0x8000043C,\ + _y1,0x8000043D,\ + _yn,0x8000043E,\ + AbortDoc,0x800003BB,\ + abs_,0x800003DC,\ + acmDriverAdd,0x8000019E,\ + acmDriverClose,0x8000019F,\ + acmDriverDetails,0x800001A0,\ + acmDriverEnum,0x800001A1,\ + acmDriverID,0x800001A2,\ + acmDriverMessage,0x800001A3,\ + acmDriverOpen,0x800001A4,\ + acmDriverPriority,0x800001A5,\ + acmDriverRemove,0x800001A6,\ + acmFilterChoose,0x800001A7,\ + acmFilterDetails,0x800001A8,\ + acmFilterEnum,0x800001A9,\ + acmFilterTagDetails,0x800001AA,\ + acmFilterTagEnum,0x800001AB,\ + acmFormatChoose,0x800001AC,\ + acmFormatDetails,0x800001AD,\ + acmFormatEnum,0x800001AE,\ + acmFormatSuggest,0x800001AF,\ + acmFormatTagDetails,0x800001B0,\ + acmFormatTagEnum,0x800001B1,\ + acmGetVersion,0x800001BA,\ + acmMetrics,0x800001BB,\ + acmStreamClose,0x800001B2,\ + acmStreamConvert,0x800001B3,\ + acmStreamMessage,0x800001B4,\ + acmStreamOpen,0x800001B5,\ + acmStreamPrepareHeader,0x800001B6,\ + acmStreamReset,0x800001B7,\ + acmStreamSize,0x800001B8,\ + acmStreamUnprepareHeader,0x800001B9,\ + acos,0x800003DD,\ + ActivateDevice,0x8000049B,\ + AddEventAccess,0x8000022E,\ + AddFontResourceW,0x8000037D,\ + AddTrackedItem,0x80000242,\ + AdjustWindowRectEx,0x80000377,\ + AFS_CloseAllFileHandles,0x8000028F,\ + AFS_CreateDirectoryW,0x80000284,\ + AFS_CreateFileW,0x80000288,\ + AFS_DeleteFileW,0x80000289,\ + AFS_FindFirstFileW,0x8000028B,\ + AFS_GetDiskFreeSpace,0x80000290,\ + AFS_GetFileAttributesW,0x80000286,\ + AFS_MoveFileW,0x8000028A,\ + AFS_NotifyMountedFS,0x80000291,\ + AFS_PrestoChangoFileName,0x8000028E,\ + AFS_RegisterFileSystemFunction,0x8000028C,\ + AFS_RemoveDirectoryW,0x80000285,\ + AFS_SetFileAttributesW,0x80000287,\ + AFS_Unmount,0x80000283,\ + AppendMenuW,0x8000034A,\ + asin,0x800003DE,\ + atan,0x800003DF,\ + atan2,0x800003E0,\ + atof,0x800003E3,\ + atoi,0x800003E1,\ + atol,0x800003E2,\ + AttachDebugger,0x8000009D,\ + AudioUpdateFromRegistry,0x80000178,\ + BatteryDrvrGetLevels,0x80000129,\ + BatteryDrvrSupportsChangeNotification,0x8000012A,\ + BatteryGetLifeTimeInfo,0x800002C9,\ + BatteryNotifyOfTimeChange,0x800002CA,\ + BeginDeferWindowPos,0x80000485,\ + BeginPaint,0x80000104,\ + BinaryCompress,0x80000251,\ + BinaryDecompress,0x80000252,\ + BitBlt,0x80000387,\ + BringWindowToTop,0x80000113,\ + CacheSync,0x80000241,\ + CallNextHookEx,0x800004B4,\ + CallWindowProcW,0x8000011D,\ + CeChangeDatabaseLCID,0x80000154,\ + CeClearReplChangeBitsEx,0x80000148,\ + CeClearUserNotification,0x800001DA,\ + CeCreateDatabase,0x8000013B,\ + CeCreateDatabaseEx,0x800004A6,\ + CeDeleteDatabase,0x8000013E,\ + CeDeleteDatabaseEx,0x800004A9,\ + CeDeleteRecord,0x80000140,\ + CeEnumDBVolumes,0x8000048D,\ + CeEventHasOccurred,0x800001DF,\ + CeFindFirstDatabase,0x80000139,\ + CeFindFirstDatabaseEx,0x800004AC,\ + CeFindNextDatabase,0x8000013A,\ + CeFindNextDatabaseEx,0x800004A5,\ + CeFlushDBVol,0x800004C1,\ + CeFreeNotification,0x800004CA,\ + CeGetReplChangeBitsEx,0x80000146,\ + CeGetReplChangeMask,0x80000144,\ + CeGetReplOtherBitsEx,0x80000149,\ + CeGetUserNotificationPreferences,0x800001DE,\ + CeHandleAppNotifications,0x800001DD,\ + ceil,0x800003E7,\ + CeMountDBVol,0x8000048C,\ + CeOidGetInfo,0x80000138,\ + CeOidGetInfoEx,0x800004AB,\ + CeOpenDatabase,0x8000013D,\ + CeOpenDatabaseEx,0x800004A8,\ + CeReadRecordProps,0x80000141,\ + CeReadRecordPropsEx,0x800004AA,\ + CeRegisterFileSystemNotification,0x8000014B,\ + CeRegisterReplNotification,0x8000014C,\ + CeRemoveFontResource,0x8000037E,\ + CeRunAppAtEvent,0x800001DC,\ + CeRunAppAtTime,0x800001DB,\ + CeSeekDatabase,0x8000013F,\ + CeSetDatabaseInfo,0x8000013C,\ + CeSetDatabaseInfoEx,0x800004A7,\ + CeSetReplChangeBitsEx,0x80000147,\ + CeSetReplChangeMask,0x80000145,\ + CeSetReplOtherBitsEx,0x8000014A,\ + CeSetUserNotification,0x800001D9,\ + CeUnmountDBVol,0x800004AD,\ + CeWriteRecordProps,0x80000142,\ + CharLowerBuffW,0x800000DE,\ + CharLowerW,0x800000DD,\ + CharNextW,0x800000E2,\ + CharPrevW,0x800000E1,\ + CharUpperBuffW,0x800000DF,\ + CharUpperW,0x800000E0,\ + CheckMenuItem,0x80000350,\ + CheckMenuRadioItem,0x80000351,\ + CheckPassword,0x800000B6,\ + CheckRadioButton,0x800002AC,\ + ChildWindowFromPoint,0x800000FD,\ + ClearCommBreak,0x8000006B,\ + ClearCommError,0x8000006C,\ + clearerr,0x80000467,\ + ClientToScreen,0x800000FE,\ + ClipCursor,0x800002DB,\ + CloseAllDeviceHandles,0x800000F4,\ + CloseAllFileHandles,0x800000F2,\ + CloseClipboard,0x8000029D,\ + CloseEnhMetaFile,0x800003BC,\ + CloseHandle,0x80000229,\ + CloseProcOE,0x8000024D,\ + CombineRgn,0x800003C8,\ + CompactAllHeaps,0x80000036,\ + CompareFileTime,0x80000012,\ + CompareStringW,0x800000C6,\ + ConnectDebugger,0x80000279,\ + ContinueDebugEvent,0x800001F8,\ + ConvertDefaultLocale,0x800000D2,\ + CopyFileW,0x800000A4,\ + CopyRect,0x80000060,\ + cos,0x800003EC,\ + cosh,0x800003ED,\ + CountClipboardFormats,0x800002A2,\ + CreateAcceleratorTableW,0x8000005C,\ + CreateAPIHandle,0x8000027C,\ + CreateAPISet,0x8000022F,\ + CreateBitmap,0x80000385,\ + CreateCaret,0x80000292,\ + CreateCompatibleBitmap,0x80000386,\ + CreateCompatibleDC,0x8000038E,\ + CreateCrit,0x80000268,\ + CreateDCW,0x8000038D,\ + CreateDeviceHandle,0x800000F5,\ + CreateDialogIndirectParamW,0x800002B0,\ + CreateDIBPatternBrushPt,0x800003A1,\ + CreateDIBSection,0x8000005A,\ + CreateDirectoryW,0x800000A0,\ + CreateEnhMetaFileW,0x800003BD,\ + CreateEventW,0x800001EF,\ + CreateFileForMapping,0x80000228,\ + CreateFileForMappingW,0x8000048F,\ + CreateFileMappingW,0x80000224,\ + CreateFileW,0x800000A8,\ + CreateFontIndirectW,0x8000037F,\ + CreateIconIndirect,0x800002D3,\ + CreateMenu,0x80000353,\ + CreateMutexW,0x8000022B,\ + CreatePalette,0x800003B3,\ + CreatePatternBrush,0x8000039D,\ + CreatePen,0x8000039E,\ + CreatePenIndirect,0x800003A2,\ + CreatePopupMenu,0x80000354,\ + CreateProcessW,0x800001ED,\ + CreateRectRgn,0x800003D4,\ + CreateRectRgnIndirect,0x800003C9,\ + CreateSolidBrush,0x800003A3,\ + CreateThread,0x800001EC,\ + CreateWindowExW,0x800000F6,\ + DBCanonicalize,0x800000E9,\ + DeactivateDevice,0x8000049C,\ + DebugActiveProcess,0x800001F9,\ + DebugNotify,0x80000282,\ + DefDlgProcW,0x800002B1,\ + DeferWindowPos,0x80000486,\ + DefWindowProcW,0x80000108,\ + DeleteAndRenameFile,0x800000B7,\ + DeleteCriticalSection,0x80000003,\ + DeleteDC,0x8000038F,\ + DeleteEnhMetaFile,0x800003BE,\ + DeleteFileW,0x800000A5,\ + DeleteMenu,0x80000352,\ + DeleteObject,0x80000390,\ + DeleteTrackedItem,0x80000243,\ + DeregisterAFS,0x8000014F,\ + DeregisterAFSName,0x80000153,\ + DeregisterDevice,0x800000EC,\ + DestroyAcceleratorTable,0x8000005D,\ + DestroyCaret,0x80000293,\ + DestroyIcon,0x800002D5,\ + DestroyMenu,0x8000034C,\ + DestroyWindow,0x80000109,\ + DeviceIoControl,0x800000B3,\ + DialogBoxIndirectParamW,0x800002B2,\ + difftime,0x800003EE,\ + DisableCaretSystemWide,0x8000029A,\ + DispatchMessageW,0x8000035B,\ + div,0x800003EF,\ + DrawEdge,0x800003A4,\ + DrawFocusRect,0x800003A5,\ + DrawFrameControl,0x800003DB,\ + DrawIconEx,0x800002D6,\ + DrawMenuBar,0x80000358,\ + DrawTextW,0x800003B1,\ + DumpFileSystemHeap,0x80000155,\ + DumpKCallProfile,0x800001FE,\ + Ellipse,0x800003A6,\ + EmptyClipboard,0x800002A5,\ + EnableCaretSystemWide,0x8000029B,\ + EnableEUDC,0x800003DA,\ + EnableHardwareKeyboard,0x80000339,\ + EnableMenuItem,0x8000034F,\ + EnableWindow,0x8000011F,\ + EndDeferWindowPos,0x80000487,\ + EndDialog,0x800002B3,\ + EndDoc,0x800003BF,\ + EndPage,0x800003C0,\ + EndPaint,0x80000105,\ + EnterCriticalSection,0x80000004,\ + EnumCalendarInfoW,0x800000CE,\ + EnumClipboardFormats,0x800002A3,\ + EnumDateFormatsW,0x800000D0,\ + EnumDevices,0x8000007C,\ + EnumFontFamiliesW,0x800003C5,\ + EnumFontsW,0x800003C6,\ + EnumPnpIds,0x8000007B,\ + EnumSystemCodePagesW,0x800000DC,\ + EnumSystemLocalesW,0x800000DB,\ + EnumTimeFormatsW,0x800000CF,\ + EnumWindows,0x80000123,\ + EqualRect,0x80000061,\ + EqualRgn,0x8000005B,\ + EscapeCommFunction,0x8000006D,\ + EventModify,0x800001EE,\ + ExcludeClipRect,0x800003CA,\ + ExitThread,0x80000006,\ + exp,0x800003F1,\ + ExtEscape,0x8000049E,\ + ExtractIconExW,0x800002D7,\ + ExtractResource,0x8000023D,\ + ExtTextOutW,0x80000380,\ + fabs_,0x800003F2,\ + fclose,0x8000045E,\ + feof,0x80000465,\ + ferror,0x80000466,\ + fflush,0x80000462,\ + fgetc,0x80000454,\ + fgetpos,0x80000468,\ + fgets,0x80000455,\ + fgetwc,0x80000474,\ + fgetws,0x80000477,\ + FileSystemPowerFunction,0x800000F1,\ + FileTimeToLocalFileTime,0x80000015,\ + FileTimeToSystemTime,0x80000014,\ + FillRect,0x800003A7,\ + FillRgn,0x8000039F,\ + FilterTrackedItem,0x80000249,\ + FindClose,0x800000B4,\ + FindFirstFileW,0x800000A7,\ + FindNextFileW,0x800000B5,\ + FindResource,0x80000213,\ + FindResourceW,0x80000214,\ + FindWindowW,0x8000011E,\ + floor,0x800003F5,\ + FlushFileBuffers,0x800000AF,\ + FlushInstructionCache,0x800001FC,\ + FlushViewOfFile,0x80000227,\ + FlushViewOfFileMaybe,0x800004BF,\ + fmod,0x800003F6,\ + FoldStringW,0x800000DA,\ + fopen,0x80000459,\ + ForcePageout,0x8000021C,\ + FormatMessageW,0x800000EA,\ + fprintf,0x8000045B,\ + fputc,0x80000456,\ + fputs,0x80000457,\ + fputwc,0x80000475,\ + fputws,0x80000478,\ + fread,0x80000460,\ + free,0x800003FA,\ + FreeLibrary,0x80000211,\ + FreeLibraryAndExitThread,0x800004C0,\ + frexp,0x800003FB,\ + fscanf,0x8000045A,\ + fseek,0x8000046A,\ + fsetpos,0x80000469,\ + ftell,0x8000046B,\ + fwprintf,0x80000363,\ + fwrite,0x80000461,\ + fwscanf,0x800002DF,\ + GetACP,0x800000BA,\ + GetActiveWindow,0x800002C2,\ + GetAPIAddress,0x80000020,\ + GetAssociatedMenu,0x8000012C,\ + GetAsyncKeyState,0x8000033A,\ + GetAsyncShiftFlags,0x80000342,\ + GetBkColor,0x80000391,\ + GetBkMode,0x80000392,\ + GetCallerProcess,0x8000025F,\ + GetCallerProcessIndex,0x80000281,\ + GetCapture,0x800002C3,\ + GetCaretBlinkTime,0x80000299,\ + GetCaretPos,0x80000297,\ + getchar,0x80000450,\ + GetClassInfoW,0x8000036E,\ + GetClassLong,0x80000371,\ + GetClassLongW,0x8000036F,\ + GetClassNameW,0x8000011B,\ + GetClientRect,0x800000F9,\ + GetClipboardData,0x800002A0,\ + GetClipboardDataAlloc,0x800002A9,\ + GetClipboardFormatNameW,0x800002A4,\ + GetClipboardOwner,0x8000029E,\ + GetClipBox,0x800003CB,\ + GetClipCursor,0x800002DC,\ + GetClipRgn,0x800003CC,\ + GetCommMask,0x8000006E,\ + GetCommModemStatus,0x8000006F,\ + GetCommProperties,0x80000070,\ + GetCommState,0x80000071,\ + GetCommTimeouts,0x80000072,\ + GetCPInfo,0x800000BC,\ + GetCRTFlags,0x800004CC,\ + GetCRTStorageEx,0x800004CB,\ + GetCurrencyFormatW,0x800000CD,\ + GetCurrentFT,0x8000001D,\ + GetCurrentObject,0x80000393,\ + GetCurrentPermissions,0x80000264,\ + GetCursor,0x800002DD,\ + GetCursorPos,0x800002DE,\ + GetDateFormatW,0x800000CB,\ + GetDC,0x80000106,\ + GetDCEx,0x800004A1,\ + GetDeviceCaps,0x80000394,\ + GetDeviceKeys,0x8000007D,\ + GetDialogBaseUnits,0x800002B6,\ + GetDiskFreeSpaceExW,0x800000B8,\ + GetDlgCtrlID,0x800002B5,\ + GetDlgItem,0x800002B4,\ + GetDlgItemInt,0x800002B7,\ + GetDlgItemTextW,0x800002AF,\ + GetDoubleClickTime,0x80000378,\ + GetExitCodeProcess,0x80000207,\ + GetExitCodeThread,0x80000206,\ + GetFileAttributesW,0x800000A6,\ + GetFileInformationByHandle,0x800000AE,\ + GetFileSize,0x800000AC,\ + GetFileTime,0x800000B0,\ + GetFocus,0x800002C1,\ + GetForegroundInfo,0x800004C8,\ + GetForegroundKeyboardTarget,0x800004C9,\ + GetForegroundWindow,0x800002BD,\ + GetFSHeapInfo,0x8000025B,\ + GetHeapSnapshot,0x80000034,\ + GetIdleTime,0x80000260,\ + GetKeyboardLayout,0x800004CD,\ + GetKeyboardLayoutNameW,0x80000488,\ + GetKeyboardStatus,0x8000033B,\ + GetKeyboardTarget,0x800002C7,\ + GetKeyState,0x8000035C,\ + GetKPhys,0x80000245,\ + GetLastError,0x80000204,\ + GetLocaleInfoW,0x800000C8,\ + GetLocalTime,0x80000017,\ + GetMenuItemInfoW,0x80000356,\ + GetMessagePos,0x8000035E,\ + GetMessageSource,0x80000368,\ + GetMessageW,0x8000035D,\ + GetMessageWNoWait,0x8000035F,\ + GetModuleFileNameW,0x80000219,\ + GetModuleHandleW,0x80000499,\ + GetMouseMovePoints,0x80000334,\ + GetNearestColor,0x800003B8,\ + GetNearestPaletteIndex,0x800003B4,\ + GetNextDlgGroupItem,0x800002B9,\ + GetNextDlgTabItem,0x800002B8,\ + GetNumberFormatW,0x800000CC,\ + GetObjectType,0x80000395,\ + GetObjectW,0x80000396,\ + GetOEMCP,0x800000BB,\ + GetOpenClipboardWindow,0x800002A8,\ + GetOpenFileNameW,0x800001E8,\ + GetOwnerProcess,0x8000025E,\ + GetPaletteEntries,0x800003B5,\ + GetParent,0x8000010D,\ + GetPasswordActive,0x800000EF,\ + GetPixel,0x800003A8,\ + GetPriorityClipboardFormat,0x800002A7,\ + GetProcAddrBits,0x8000025A,\ + GetProcAddressW,0x80000212,\ + GetProcessHeap,0x80000032,\ + GetProcessIndexFromID,0x80000280,\ + GetProcessVersion,0x80000218,\ + GetProcFromPtr,0x80000258,\ + GetProcName,0x80000270,\ + GetRealTime,0x8000023A,\ + GetRegionData,0x800003CD,\ + GetRgnBox,0x800003CE,\ + GetRomFileBytes,0x80000240,\ + GetRomFileInfo,0x8000023F,\ + gets,0x80000452,\ + GetSaveFileNameW,0x800001E9,\ + GetScrollInfo,0x8000011A,\ + GetStdioPathW,0x8000047D,\ + GetStockObject,0x80000397,\ + GetStoreInformation,0x80000143,\ + GetStringTypeExW,0x800000D9,\ + GetStringTypeW,0x800000D8,\ + GetSubMenu,0x80000357,\ + GetSysColor,0x80000379,\ + GetSysColorBrush,0x800003A9,\ + GetSystemDefaultLangID,0x800000D3,\ + GetSystemDefaultLCID,0x800000D5,\ + GetSystemInfo,0x8000021E,\ + GetSystemMemoryDivision,0x80000150,\ + GetSystemMetrics,0x80000375,\ + GetSystemPaletteEntries,0x800003B6,\ + GetSystemPowerStatusEx,0x800002CB,\ + GetSystemTime,0x80000019,\ + GetTempPathW,0x800000A2,\ + GetTextColor,0x80000398,\ + GetTextExtentExPointW,0x80000381,\ + GetTextFaceW,0x800003C7,\ + GetTextMetricsW,0x80000382,\ + GetThreadContext,0x8000047C,\ + GetThreadPriority,0x80000203,\ + GetThreadTimes,0x800004A2,\ + GetTickCount,0x80000217,\ + GetTimeFormatW,0x800000CA,\ + GetTimeZoneInformation,0x8000001B,\ + GetUpdateRect,0x80000112,\ + GetUpdateRgn,0x80000111,\ + GetUserDefaultLangID,0x800000D4,\ + GetUserDefaultLCID,0x800000D7,\ + GetVersionEx,0x80000011,\ + GetVersionExW,0x800002CD,\ + getwchar,0x80000470,\ + GetWindow,0x800000FB,\ + GetWindowDC,0x8000010E,\ + GetWindowLongW,0x80000103,\ + GetWindowRect,0x800000F8,\ + GetWindowTextLengthW,0x80000114,\ + GetWindowTextW,0x80000101,\ + GetWindowThreadProcessId,0x80000124,\ + GiveKPhys,0x80000246,\ + GlobalMemoryStatus,0x80000058,\ + GwesPowerOffSystem,0x80000128,\ + HeapAlloc,0x8000002E,\ + HeapCreate,0x8000002C,\ + HeapDestroy,0x8000002D,\ + HeapFree,0x80000031,\ + HeapReAlloc,0x8000002F,\ + HeapSize,0x80000030,\ + HeapValidate,0x80000033,\ + HideCaret,0x80000294,\ + ImageList_Add,0x800002E2,\ + ImageList_AddMasked,0x800002E3,\ + ImageList_BeginDrag,0x800002E4,\ + ImageList_Copy,0x800002FF,\ + ImageList_CopyDitherImage,0x800002E5,\ + ImageList_Create,0x800002E6,\ + ImageList_Destroy,0x800002E7,\ + ImageList_DragEnter,0x800002E8,\ + ImageList_DragLeave,0x800002E9,\ + ImageList_DragMove,0x800002EA,\ + ImageList_DragShowNolock,0x800002EB,\ + ImageList_Draw,0x800002EC,\ + ImageList_DrawEx,0x800002ED,\ + ImageList_DrawIndirect,0x800002EE,\ + ImageList_Duplicate,0x80000300,\ + ImageList_EndDrag,0x800002EF,\ + ImageList_GetBkColor,0x800002F0,\ + ImageList_GetDragImage,0x800002F1,\ + ImageList_GetIcon,0x800002F2,\ + ImageList_GetIconSize,0x800002F3,\ + ImageList_GetImageCount,0x800002F4,\ + ImageList_GetImageInfo,0x800002F5,\ + ImageList_LoadImage,0x800002F6,\ + ImageList_Merge,0x800002F7,\ + ImageList_Remove,0x800002F8,\ + ImageList_Replace,0x800002F9,\ + ImageList_ReplaceIcon,0x800002FA,\ + ImageList_SetBkColor,0x800002FB,\ + ImageList_SetDragCursorImage,0x800002FC,\ + ImageList_SetIconSize,0x800002FD,\ + ImageList_SetImageCount,0x80000301,\ + ImageList_SetOverlayImage,0x800002FE,\ + ImmAssociateContext,0x80000302,\ + ImmAssociateContextEx,0x800004B5,\ + ImmConfigureIMEW,0x80000303,\ + ImmCreateContext,0x800004AE,\ + ImmCreateIMCC,0x80000304,\ + ImmDestroyContext,0x800004AF,\ + ImmDestroyIMCC,0x80000305,\ + ImmDisableIME,0x800004B6,\ + ImmEnumRegisterWordW,0x80000306,\ + ImmEscapeW,0x80000307,\ + ImmGenerateMessage,0x80000308,\ + ImmGetCandidateListCountW,0x8000030A,\ + ImmGetCandidateListW,0x80000309,\ + ImmGetCandidateWindow,0x8000030B,\ + ImmGetCompositionFontW,0x8000030C,\ + ImmGetCompositionStringW,0x8000030D,\ + ImmGetCompositionWindow,0x8000030E,\ + ImmGetContext,0x8000030F,\ + ImmGetConversionListW,0x80000310,\ + ImmGetConversionStatus,0x80000311,\ + ImmGetDefaultIMEWnd,0x80000312,\ + ImmGetDescriptionW,0x80000313,\ + ImmGetGuideLineW,0x80000314,\ + ImmGetHotKey,0x8000032D,\ + ImmGetIMCCLockCount,0x80000315,\ + ImmGetIMCCSize,0x80000316,\ + ImmGetIMCLockCount,0x80000317,\ + ImmGetIMEFileNameW,0x800004B7,\ + ImmGetImeMenuItemsW,0x800004BB,\ + ImmGetOpenStatus,0x80000318,\ + ImmGetProperty,0x80000319,\ + ImmGetRegisterWordStyleW,0x8000031A,\ + ImmGetStatusWindowPos,0x800004B0,\ + ImmGetVirtualKey,0x800004BA,\ + ImmIsIME,0x800004B9,\ + ImmIsUIMessageW,0x8000031C,\ + ImmLockIMC,0x8000031D,\ + ImmLockIMCC,0x8000031E,\ + ImmNotifyIME,0x80000320,\ + ImmRegisterWordW,0x80000322,\ + ImmReleaseContext,0x80000323,\ + ImmRequestMessageW,0x800004DA,\ + ImmReSizeIMCC,0x80000321,\ + ImmSetCandidateWindow,0x80000327,\ + ImmSetCompositionFontW,0x80000328,\ + ImmSetCompositionStringW,0x80000329,\ + ImmSetCompositionWindow,0x8000032A,\ + ImmSetConversionStatus,0x8000032B,\ + ImmSetHotKey,0x8000032C,\ + ImmSetImeWndIMC,0x800004C6,\ + ImmSetOpenStatus,0x8000032E,\ + ImmSetStatusWindowPos,0x8000032F,\ + ImmSimulateHotKey,0x80000330,\ + ImmSIPanelState,0x80000324,\ + ImmUnlockIMC,0x80000331,\ + ImmUnlockIMCC,0x80000332,\ + ImmUnregisterWordW,0x80000333,\ + InflateRect,0x80000062,\ + InitializeCriticalSection,0x80000002,\ + InitLocale,0x80000008,\ + InputDebugCharW,0x80000253,\ + InsertMenuW,0x80000349,\ + InterlockedDecrement,0x8000000B,\ + InterlockedExchange,0x8000000C,\ + InterlockedIncrement,0x8000000A,\ + InterlockedTestExchange,0x80000009,\ + InterruptDisable,0x80000275,\ + InterruptDone,0x80000274,\ + InterruptInitialize,0x80000273,\ + IntersectClipRect,0x800003CF,\ + IntersectRect,0x80000063,\ + InvalidateRect,0x800000FA,\ + IsAPIReady,0x8000001E,\ + IsBadCodePtr,0x80000209,\ + IsBadPtr,0x80000259,\ + IsBadReadPtr,0x8000020A,\ + IsBadWritePtr,0x8000020B,\ + IsChild,0x80000115,\ + IsClipboardFormatAvailable,0x800002A6,\ + IsDBCSLeadByte,0x800000BF,\ + IsDBCSLeadByteEx,0x800000C0,\ + IsDialogMessageW,0x800002BA,\ + IsExiting,0x8000009F,\ + IsPrimaryThread,0x80000262,\ + IsProcessDying,0x800004BD,\ + IsRectEmpty,0x80000064,\ + IsValidCodePage,0x800000B9,\ + IsValidLocale,0x800000D1,\ + iswctype,0x800000C1,\ + IsWindow,0x8000010F,\ + IsWindowEnabled,0x80000120,\ + IsWindowVisible,0x80000376,\ + KernelIoControl,0x8000022D,\ + KernExtractIcons,0x8000023E,\ + keybd_event,0x80000341,\ + KeybdGetDeviceInfo,0x8000033C,\ + KeybdInitStates,0x8000033D,\ + KeybdVKeyToUnicode,0x8000033E,\ + KillAllOtherThreads,0x8000025D,\ + KillTimer,0x8000036C,\ + labs,0x80000406,\ + LCMapStringW,0x800000C7,\ + ldexp,0x80000407,\ + ldiv,0x80000408,\ + LeaveCriticalSection,0x80000005,\ + LeaveCritSec,0x80000255,\ + lineAddProvider,0x80000177,\ + lineClose,0x80000166,\ + lineConfigDialogEdit,0x80000176,\ + lineDeallocateCall,0x80000167,\ + lineDrop,0x80000168,\ + lineGetDevCaps,0x80000169,\ + lineGetDevConfig,0x8000016A,\ + lineGetID,0x80000174,\ + lineGetTranslateCaps,0x8000016B,\ + lineInitialize,0x8000016C,\ + lineMakeCall,0x8000016D,\ + lineNegotiateAPIVersion,0x8000016E,\ + lineOpen,0x8000016F,\ + lineSetCurrentLocation,0x80000490,\ + lineSetDevConfig,0x80000170,\ + lineSetStatusMessages,0x80000171,\ + lineShutdown,0x80000172,\ + lineTranslateAddress,0x80000173,\ + lineTranslateDialog,0x80000175,\ + LoadAcceleratorsW,0x8000005E,\ + LoadBitmapW,0x80000369,\ + LoadCursorW,0x800002AB,\ + LoadDriver,0x80000272,\ + LoadFSD,0x800000ED,\ + LoadIconW,0x800002D8,\ + LoadImageW,0x800002DA,\ + LoadLibraryW,0x80000210,\ + LoadMenuW,0x8000034E,\ + LoadResource,0x80000215,\ + LoadStringW,0x8000036A,\ + LocalAlloc,0x80000021,\ + LocalAllocInProcess,0x80000029,\ + LocalFileTimeToFileTime,0x80000016,\ + LocalFree,0x80000024,\ + LocalFreeInProcess,0x8000002A,\ + LocalReAlloc,0x80000022,\ + LocalSize,0x80000023,\ + LocalSizeInProcess,0x8000002B,\ + LockPages,0x80000489,\ + log,0x80000409,\ + log10,0x8000040A,\ + longjmp,0x8000040C,\ + lstrcmpiW,0x800000E4,\ + lstrcmpW,0x800000E3,\ + MainThreadBaseFunc,0x8000000E,\ + malloc,0x80000411,\ + MapDialogRect,0x800002BB,\ + MapPtrToProcess,0x80000256,\ + MapPtrUnsecure,0x80000257,\ + MapUncompressedFileW,0x8000022A,\ + MapViewOfFile,0x80000225,\ + MapVirtualKeyW,0x8000033F,\ + MapWindowPoints,0x8000011C,\ + MaskBlt,0x80000388,\ + mbstowcs,0x8000004C,\ + memchr,0x8000001F,\ + memcmp,0x80000413,\ + memcpy,0x80000414,\ + memmove,0x80000416,\ + memset,0x80000417,\ + MessageBeep,0x80000359,\ + MessageBoxW,0x8000035A,\ + modf,0x80000418,\ + mouse_event,0x80000338,\ + MoveFileW,0x800000A3,\ + MoveWindow,0x80000110,\ + MsgWaitForMultipleObjectsEx,0x80000367,\ + MultiByteToWideChar,0x800000C4,\ + NKDbgPrintfW,0x80000221,\ + NKTerminateThread,0x8000026F,\ + NKvDbgPrintfW,0x80000238,\ + NLedGetDeviceInfo,0x80000347,\ + NLedSetDevice,0x80000348,\ + NotifyForceCleanboot,0x80000201,\ + NotifyWinUserSystem,0x800002CC,\ + OffsetRect,0x80000065,\ + OffsetRgn,0x800003D0,\ + OpenClipboard,0x8000029C,\ + OpenProcess,0x800001FD,\ + OtherThreadsRunning,0x8000025C,\ + OutputDebugStringW,0x8000021D,\ + PatBlt,0x800003AA,\ + PeekMessageW,0x80000360,\ + PegClearUserNotification,0x800001D4,\ + PegCreateDatabase,0x80000130,\ + PegDeleteDatabase,0x80000133,\ + PegDeleteRecord,0x80000135,\ + PegFindFirstDatabase,0x8000012E,\ + PegFindNextDatabase,0x8000012F,\ + PegGetUserNotificationPreferences,0x800001D8,\ + PegHandleAppNotifications,0x800001D7,\ + PegOidGetInfo,0x8000012D,\ + PegOpenDatabase,0x80000132,\ + PegReadRecordProps,0x80000136,\ + PegRemoveFontResource,0x80000383,\ + PegRunAppAtEvent,0x800001D6,\ + PegRunAppAtTime,0x800001D5,\ + PegSeekDatabase,0x80000134,\ + PegSetDatabaseInfo,0x80000131,\ + PegSetUserNotification,0x800001D3,\ + PegWriteRecordProps,0x80000137,\ + PlayEnhMetaFile,0x800003C1,\ + PlaySoundW,0x8000017A,\ + Polygon,0x800003AB,\ + Polyline,0x800003AC,\ + PostKeybdMessage,0x80000340,\ + PostMessageW,0x80000361,\ + PostQuitMessage,0x80000362,\ + PostThreadMessageW,0x80000122,\ + pow,0x8000041B,\ + PowerOffSystem,0x80000269,\ + PPSHRestart,0x8000027E,\ + printf,0x8000044E,\ + PrintTrackedItem,0x80000244,\ + ProcessDetachAllDLLs,0x8000023C,\ + ProfileStart,0x80000052,\ + ProfileStop,0x80000053,\ + ProfileSyscall,0x80000239,\ + PSLNotify,0x80000007,\ + PtInRect,0x80000066,\ + PtInRegion,0x800003D1,\ + PurgeComm,0x80000073,\ + putchar,0x80000451,\ + puts,0x80000453,\ + putwchar,0x80000471,\ + QASetWindowsJournalHook,0x80000335,\ + QAUnhookWindowsJournalHook,0x80000336,\ + qsort,0x8000041C,\ + QueryAPISetID,0x800001EA,\ + QueryPerformanceCounter,0x8000021A,\ + QueryPerformanceFrequency,0x8000021B,\ + RaiseException,0x8000021F,\ + rand,0x8000041D,\ + Random,0x80000050,\ + RasDeleteEntry,0x8000015F,\ + RasDial,0x80000156,\ + RasEnumConnections,0x80000161,\ + RasEnumEntries,0x80000159,\ + RasGetConnectStatus,0x80000162,\ + RasGetEntryDevConfig,0x80000163,\ + RasGetEntryDialParams,0x8000015A,\ + RasGetEntryProperties,0x8000015C,\ + RasHangup,0x80000157,\ + RasHangUp,0x80000158,\ + RasIOControl,0x80000165,\ + RasRenameEntry,0x80000160,\ + RasSetEntryDevConfig,0x80000164,\ + RasSetEntryDialParams,0x8000015B,\ + RasSetEntryProperties,0x8000015D,\ + RasValidateEntryName,0x8000015E,\ + ReadFile,0x800000AA,\ + ReadFileWithSeek,0x800000F3,\ + ReadProcessMemory,0x800001FA,\ + ReadRegistryFromOEM,0x80000481,\ + RealizePalette,0x800003B9,\ + realloc,0x8000041E,\ + Rectangle,0x800003AD,\ + RectangleAnimation,0x80000126,\ + RectInRegion,0x800003D2,\ + RectVisible,0x800003D5,\ + RefreshKernelAlarm,0x8000024B,\ + RegCloseKey,0x800001C7,\ + RegCopyFile,0x800001D1,\ + RegCreateKeyExW,0x800001C8,\ + RegDeleteKeyW,0x800001C9,\ + RegDeleteValueW,0x800001CA,\ + RegEnumKeyExW,0x800001CC,\ + RegEnumValueW,0x800001CB,\ + RegFlushKey,0x80000480,\ + RegisterAFS,0x8000014D,\ + RegisterAFSName,0x80000152,\ + RegisterAPISet,0x8000027B,\ + RegisterClassW,0x8000005F,\ + RegisterClassWStub,0x80000373,\ + RegisterClipboardFormatW,0x800002A1,\ + RegisterDbgZones,0x80000222,\ + RegisterDevice,0x800000EB,\ + RegisterHiddenAFS,0x8000014E,\ + RegisterHotKey,0x80000343,\ + RegisterSIPanel,0x80000125,\ + RegisterTaskBar,0x8000037C,\ + RegisterTrackedItem,0x80000248,\ + RegisterWindowMessageW,0x8000037B,\ + RegOpenKeyExW,0x800001CD,\ + RegQueryInfoKeyW,0x800001CE,\ + RegQueryValueExW,0x800001CF,\ + RegRestoreFile,0x800001D2,\ + RegSetValueExW,0x800001D0,\ + ReleaseCapture,0x800002C5,\ + ReleaseDC,0x80000107,\ + ReleaseMutex,0x8000022C,\ + RemoteLocalAlloc,0x80000025,\ + RemoteLocalFree,0x80000028,\ + RemoteLocalReAlloc,0x80000026,\ + RemoteLocalSize,0x80000027,\ + RemoveDirectoryW,0x800000A1,\ + RemoveFontResourceW,0x80000384,\ + RemoveMenu,0x8000034B,\ + RestoreDC,0x8000038B,\ + ResumeThread,0x800001F4,\ + RoundRect,0x800003AE,\ + SaveDC,0x8000038C,\ + scanf,0x8000044D,\ + ScreenToClient,0x800000FF,\ + ScrollDC,0x800003D9,\ + ScrollWindowEx,0x80000121,\ + SelectClipRgn,0x800003D3,\ + SelectObject,0x80000399,\ + SelectPalette,0x800003BA,\ + SendDlgItemMessageW,0x800002AD,\ + SendInput,0x80000337,\ + SendMessageW,0x80000364,\ + SendNotifyMessageW,0x80000365,\ + SetAbortProc,0x800003C2,\ + SetACP,0x800000BD,\ + SetActiveWindow,0x800002BF,\ + SetAssociatedMenu,0x8000012B,\ + SetBkColor,0x8000039A,\ + SetBkMode,0x8000039B,\ + SetBrushOrgEx,0x800003AF,\ + SetCapture,0x800002C4,\ + SetCaretBlinkTime,0x80000298,\ + SetCaretPos,0x80000296,\ + SetClassLong,0x80000372,\ + SetClassLongW,0x80000370,\ + SetCleanRebootFlag,0x80000267,\ + SetClipboardData,0x8000029F,\ + SetCommBreak,0x80000074,\ + SetCommMask,0x80000075,\ + SetCommState,0x80000076,\ + SetCommTimeouts,0x80000077,\ + SetCursor,0x800002AA,\ + SetCursorPos,0x800002E0,\ + SetDaylightTime,0x80000223,\ + SetDbgZone,0x8000026A,\ + SetDlgItemInt,0x800002BC,\ + SetDlgItemTextW,0x800002AE,\ + SetEndOfFile,0x800000B2,\ + SetExceptionHandler,0x80000247,\ + SetFileAttributesW,0x800000A9,\ + SetFilePointer,0x800000AD,\ + SetFileTime,0x800000B1,\ + SetFocus,0x800002C0,\ + SetForegroundWindow,0x800002BE,\ + SetGwesHeapMark,0x80000265,\ + SetGwesOOMEvent,0x8000024E,\ + SetGwesPowerHandler,0x80000278,\ + SetHandleOwner,0x80000271,\ + SetHardwareWatch,0x8000027A,\ + SetInterruptEvent,0x8000009E,\ + setjmp,0x80000806,\ + SetKernelAlarm,0x8000024A,\ + SetKeyboardTarget,0x800002C6,\ + SetKMode,0x80000276,\ + SetLastError,0x80000205,\ + SetLocaleInfoW,0x800000C9,\ + SetLocalTime,0x80000018,\ + SetLowestScheduledPriority,0x80000261,\ + SetMenuItemInfoW,0x80000355,\ + SetObjectOwner,0x800003D8,\ + SetOEMCP,0x800000BE,\ + SetPaletteEntries,0x800003B7,\ + SetParent,0x8000010C,\ + SetPassword,0x800000EE,\ + SetPasswordActive,0x800000F0,\ + SetPFHandle,0x8000024C,\ + SetPixel,0x800003B0,\ + SetPowerOffHandler,0x80000277,\ + SetProcPermissions,0x80000263,\ + SetRealTime,0x8000023B,\ + SetRect,0x80000067,\ + SetRectEmpty,0x80000068,\ + SetRectRgn,0x800003D6,\ + SetROP2,0x800003A0,\ + SetScrollInfo,0x80000117,\ + SetScrollPos,0x80000118,\ + SetScrollRange,0x80000119,\ + SetStdioPathW,0x8000047E,\ + SetSysColors,0x8000037A,\ + SetSystemDefaultLCID,0x800000D6,\ + SetSystemMemoryDivision,0x80000151,\ + SetSystemTime,0x8000001A,\ + SetTextColor,0x8000039C,\ + SetThreadContext,0x800001F6,\ + SetThreadPriority,0x80000202,\ + SetTimer,0x8000036B,\ + SetTimeZoneBias,0x80000266,\ + SetTimeZoneInformation,0x8000001C,\ + SetupComm,0x80000078,\ + SetViewportOrgEx,0x800003D7,\ + SetWDevicePowerHandler,0x8000049A,\ + SetWindowLongW,0x80000102,\ + SetWindowPos,0x800000F7,\ + SetWindowsHookExW,0x800004B2,\ + SetWindowTextW,0x80000100,\ + SHAddToRecentDocs,0x800001E3,\ + SHCreateExplorerInstance,0x8000048B,\ + SHCreateShortcut,0x800001E4,\ + Shell_NotifyIcon,0x800001E1,\ + ShellExecuteEx,0x800001E0,\ + ShellModalEnd,0x800002C8,\ + SHGetFileInfo,0x800001E2,\ + SHGetShortcutTarget,0x800001E5,\ + SHLoadDIBitmap,0x800001E7,\ + ShowCaret,0x80000295,\ + ShowCursor,0x800002E1,\ + ShowWindow,0x8000010A,\ + SHShowOutOfMemory,0x800001E6,\ + SignalStarted,0x8000027F,\ + sin,0x80000422,\ + sinh,0x80000423,\ + SizeofResource,0x80000216,\ + Sleep,0x800001F0,\ + sndPlaySoundW,0x80000179,\ + sprintf,0x800002CF,\ + sqrt,0x80000424,\ + srand,0x80000425,\ + sscanf,0x8000028D,\ + StartDocW,0x800003C3,\ + StartPage,0x800003C4,\ + strcat,0x80000427,\ + strchr,0x80000428,\ + strcmp,0x80000429,\ + strcpy,0x8000042A,\ + strcspn,0x8000042B,\ + StretchBlt,0x80000389,\ + StringCompress,0x8000024F,\ + StringDecompress,0x80000250,\ + strlen,0x8000042C,\ + strncat,0x8000042D,\ + strncmp,0x8000042E,\ + strncpy,0x8000042F,\ + strstr,0x80000430,\ + strtok,0x80000431,\ + SubtractRect,0x80000069,\ + SuspendThread,0x800001F3,\ + swprintf,0x80000449,\ + swscanf,0x8000044A,\ + SystemIdleTimerReset,0x80000345,\ + SystemMemoryLow,0x800002D0,\ + SystemParametersInfoW,0x80000059,\ + SystemStarted,0x80000001,\ + SystemTimeToFileTime,0x80000013,\ + TakeCritSec,0x80000254,\ + tan,0x80000433,\ + tanh,0x80000434,\ + TerminateProcess,0x80000220,\ + TerminateThread,0x800001EB,\ + THCreateSnapshot,0x800001FF,\ + THGrow,0x80000200,\ + ThisIsGwes,0x80000035,\ + ThreadAttachAllDLLs,0x80000231,\ + ThreadBaseFunc,0x8000000D,\ + ThreadDetachAllDLLs,0x80000232,\ + TlsCall,0x80000208,\ + TlsGetValue,0x8000000F,\ + TlsSetValue,0x80000010,\ + tolower,0x80000442,\ + TouchCalibrate,0x8000036D,\ + toupper,0x80000443,\ + towlower,0x800000C2,\ + towupper,0x800000C3,\ + TrackPopupMenuEx,0x8000034D,\ + TranslateAcceleratorW,0x80000346,\ + TranslateCharsetInfo,0x8000048E,\ + TranslateMessage,0x80000366,\ + TransmitCommChar,0x80000079,\ + TransparentImage,0x8000038A,\ + TurnOffProfiling,0x8000026C,\ + TurnOffSyscallProfiling,0x8000026E,\ + TurnOnProfiling,0x8000026B,\ + TurnOnSyscallProfiling,0x8000026D,\ + U_rclose,0x80000237,\ + U_rlseek,0x80000236,\ + U_ropen,0x80000233,\ + U_rread,0x80000234,\ + U_rwrite,0x80000235,\ + ungetc,0x80000458,\ + ungetwc,0x80000476,\ + UnhookWindowsHookEx,0x800004B3,\ + UnionRect,0x8000006A,\ + UnlockPages,0x8000048A,\ + UnmapViewOfFile,0x80000226,\ + UnregisterClassW,0x80000374,\ + UnregisterFunc1,0x80000484,\ + UnregisterHotKey,0x80000344,\ + UpdateWindow,0x8000010B,\ + ValidateRect,0x80000116,\ + VerifyAPIHandle,0x8000027D,\ + vfprintf,0x8000045C,\ + vfwprintf,0x800002D1,\ + VirtualAlloc,0x8000020C,\ + VirtualCopy,0x80000230,\ + VirtualFree,0x8000020D,\ + VirtualProtect,0x8000020E,\ + VirtualQuery,0x8000020F,\ + vprintf,0x8000044F,\ + vsprintf,0x8000047A,\ + vswprintf,0x8000044B,\ + vwprintf,0x8000046F,\ + WaitCommEvent,0x8000007A,\ + WaitForDebugEvent,0x800001F7,\ + WaitForMultipleObjects,0x800001F2,\ + WaitForSingleObject,0x800001F1,\ + waveInAddBuffer,0x80000196,\ + waveInClose,0x80000193,\ + waveInGetDevCaps,0x80000191,\ + waveInGetErrorText,0x80000192,\ + waveInGetID,0x8000019B,\ + waveInGetNumDevs,0x80000190,\ + waveInGetPosition,0x8000019A,\ + waveInMessage,0x8000019C,\ + waveInOpen,0x8000019D,\ + waveInPrepareHeader,0x80000194,\ + waveInReset,0x80000199,\ + waveInStart,0x80000197,\ + waveInStop,0x80000198,\ + waveInUnprepareHeader,0x80000195,\ + waveOutBreakLoop,0x80000187,\ + waveOutClose,0x80000180,\ + waveOutGetDevCaps,0x8000017C,\ + waveOutGetErrorText,0x8000017F,\ + waveOutGetID,0x8000018D,\ + waveOutGetNumDevs,0x8000017B,\ + waveOutGetPitch,0x80000189,\ + waveOutGetPlaybackRate,0x8000018B,\ + waveOutGetPosition,0x80000188,\ + waveOutGetVolume,0x8000017D,\ + waveOutMessage,0x8000018E,\ + waveOutOpen,0x8000018F,\ + waveOutPause,0x80000184,\ + waveOutPrepareHeader,0x80000181,\ + waveOutReset,0x80000186,\ + waveOutRestart,0x80000185,\ + waveOutSetPitch,0x8000018A,\ + waveOutSetPlaybackRate,0x8000018C,\ + waveOutSetVolume,0x8000017E,\ + waveOutUnprepareHeader,0x80000182,\ + waveOutWrite,0x80000183,\ + wcscat,0x8000003A,\ + wcschr,0x8000003B,\ + wcscmp,0x8000003C,\ + wcscpy,0x8000003D,\ + wcscspn,0x8000003E,\ + wcslen,0x8000003F,\ + wcsncat,0x80000040,\ + wcsncmp,0x80000041,\ + wcsncpy,0x80000042,\ + wcspbrk,0x80000044,\ + wcsrchr,0x80000045,\ + wcsspn,0x80000048,\ + wcsstr,0x80000049,\ + wcstod,0x80000439,\ + wcstok,0x8000004D,\ + wcstol,0x8000043A,\ + wcstombs,0x8000004B,\ + wcstoul,0x8000043B,\ + WideCharToMultiByte,0x800000C5,\ + WindowFromPoint,0x800000FC,\ + WNetAddConnection3W,0x800001BC,\ + WNetCancelConnection2W,0x800001BD,\ + WNetCloseEnum,0x800001C5,\ + WNetConnectionDialog1W,0x800001BE,\ + WNetDisconnectDialog,0x800001BF,\ + WNetDisconnectDialog1W,0x800001C0,\ + WNetEnumResourceW,0x800001C6,\ + WNetGetConnectionW,0x800001C1,\ + WNetGetUniversalNameW,0x800001C2,\ + WNetGetUserW,0x800001C3,\ + WNetOpenEnumW,0x800001C4,\ + wprintf,0x8000046E,\ + WriteDebugLED,0x80000483,\ + WriteFile,0x800000AB,\ + WriteFileWithSeek,0x800002CE,\ + WriteProcessMemory,0x800001FB,\ + WriteRegistryToOEM,0x80000482,\ + wscanf,0x8000046D,\ + wsprintfW,0x80000038,\ + wvsprintfW,0x80000039 diff --git a/include/macro/armlitrl.inc b/include/macro/armlitrl.inc new file mode 100644 index 0000000..7ed58c2 --- /dev/null +++ b/include/macro/armlitrl.inc @@ -0,0 +1,223 @@ +;FASMARM extension macros: +; +;Macros for using large constants directly with data processing and memory instructions +; +;Access to the macros is always with the first three characters as uppercase. +;This is necessary to prevent excess memory usage with normal instructions not requiring this functionality. +; +;NOTE: these macro use R12 (ip) for intermediate values. Don't rely on R12 being preserved. +; +;These macros are NOT compatible with thumb mode +; +;These macros allow you to do things like this: +; +;ADDne r11,r2,0x12345678 ;compiles to "ldrne r11,[pc,..lit?0]" and "addne r11,r2,r11" with "..lit?0 dw 0x12345678" +;ADD r11,r11,0x12345678 ;compiles to "ldr r12,[pc,..lit?0]" and "add r11,r11,r12" +;LDRhi r0,[r0,-0x12345678] ;compiles to "ldrhi r12,[pc,..lit?0]" and "ldrhi r0,[r0,-r12]" +;STRb r0,[r3,0xcc000000] ;compiles to "mov r12,0xcc000000" and "strb r0,[r3,r12]" +;CMP r2,0x101 ;compiles to "ldr r12,[pc,..lit?1]" and "cmp r2,r12" with "..lit?1 dw 0x101" +;CMP r2,0x100 ;compiles to "cmp r2,0x100" +; +;Notice that the allocation of literals is optimised to reuse values where possible and only allocated when necessary. +; +;You will need to periodically dump the literals to the output before the labels get more than 4Kbytes distant +;from the source instruction. Generally you can do this after an unconditional branch, and usually at the +;end of a procedure. Simply dump at an appropriate place with "literals". +; +;These macros will correctly handle any ARM format the assembler can handle, so you could do all your code by using +;these macros, but this can create excessive demands on memory and increases compilation time. These macros are +;especially useful where you might use symbolic constants and not be sure of the required size. Just put the base +;instruction in uppercase and let the macros decide the best encoding for you. +; +;The PROCAPS.INC macros have ben designed to use these macros also. When you include this file along with PROCAPS.INC +;then they will cooperate to produce easy to program and also optimised output for your project. +; +;By default this file is included from "WINCEX.INC". + +macro make_dp_instr instr,suffix,regs,flag { + irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{ + match inst,instr\#cond\#suffix\\{ + macro inst regs,[arg] \\\{ + \\\common + \\\local encoding,..lit,z,c,..pc,arg_pc + if ~ defined encoding | encoding <> 0xf7ffffff + inst regs,arg + load encoding word from $-4 + else + ..pc=$ + match billg =$ lots,:arg: \\\\{match :a:,billg\\\\#..pc\\\\#lots \\\\\{arg_pc equ a\\\\\}\\\\} + match =arg_pc,arg_pc \\\\{arg_pc equ arg\\\\} + match ra=,rb:ld,regs:ldr\#cond \\\\{ + match =pc,rb\\\\\{arg_pc equ arg_pc-4\\\\\} + match =r15,rb\\\\\{arg_pc equ arg_pc-4\\\\\} + if ra eq rb + if ra eq ip + halt ;cannot use ip,ip,large constant + end if + ld ip,[pc,..lit-$-8] + inst regs,ip + else + ld ra,[pc,..lit-$-8] + inst regs,ra + end if + \\\\} + match =0:ld,flag:ldr\#cond \\\\{ + ld ip,[pc,..lit-$-8] + instr regs,ip + \\\\} + match =1:ld,flag:ldr\#cond \\\\{ + ld regs,[pc,..lit-$-8] + \\\\} + if arg eqtype 0 + virtual + dW arg_pc + load c word from $-4 + end virtual + repeat 17 + if %=17 + encoding=0xf7ffffff + break + end if + if (c shl(%*2-2))or(c shr(34-%*2))and 0xffffff00=0 + encoding=0 + break + end if + end repeat + end if + macro z \\\\{ + if defined encoding & encoding = 0xf7ffffff + literal@found=0 + repeat ($-literals@start)/4 + load literal@value word from literals@start+(%-1)*4 + if literal@value=c + label ..lit word at literals@start+(%-1)*4 + literal@found=1 + break + end if + end repeat + if ~ literal@found + ..lit dW arg_pc + end if + end if + \\\\} + literal@words equ literal@words,z + end if + \\\} + \\} + \} +} + +irps instr,ADC ADD AND BIC EOR ORR RSB RSC SBC SUB { + make_dp_instr instr,, + make_dp_instr instr,s, +} +irps instr,CMN CMP TST TEQ { + make_dp_instr instr,,rn,0 +} +irps instr,MOV MVN { + make_dp_instr instr,,rd,1 + make_dp_instr instr,s,rd,1 +} +purge make_dp_instr + +macro make_mem_instr instr,suffix,limit { + irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{ + match inst,instr\#cond\#suffix\\{ + macro inst reg,[arg] \\\{ + \\\common + \\\local off,pre,rn,bru,minus + minus equ + off equ + match [r=,o],arg \\\\{ + rn equ r + bru equ + off equ o + pre equ 1 + \\\\} + match [r=,o]=!,arg \\\\{ + rn equ r + bru equ ! + off equ o + pre equ 1 + \\\\} + match [r]=,o,arg \\\\{ + rn equ r + off equ o + pre equ 0 + \\\\} + match ,off \\\\{ + inst reg,arg + \\\\} + match val:mv,off:MOV\#cond \\\\{ + if off eqtype 0 + if off>=limit | off<=-limit + match -o,off\\\\\{ + off equ o + minus equ - + \\\\\} + mv ip,off + match =1,pre\\\\\{inst reg,[rn,minus ip]bru\\\\\} + match =0,pre\\\\\{inst reg,[rn],minus ip\\\\\} + else + inst reg,arg + end if + else + inst reg,arg + end if + \\\\} + \\\} + \\} + \} +} +irps instr,LDR STR { + make_mem_instr instr,,4096 + make_mem_instr instr,b,4096 + make_mem_instr instr,bt,4096 + make_mem_instr instr,t,4096 + make_mem_instr instr,h,256 + make_mem_instr instr,d,256 +} +make_mem_instr LDR,sh,256 +make_mem_instr LDR,sb,256 + +purge make_mem_instr + +macro def_astring labl,[string] { + common + local ..db,z + labl=..db + macro z \{ + if defined labl + ..db dB string + end if + \} + literal@astrings equ literal@astrings,z +} + +macro def_ustring labl,[string] { + common + local ..du,z + labl=..du + macro z \{ + if defined labl + align 2 + ..du dU string + end if + \} + literal@ustrings equ literal@ustrings,z +} + +literal@words equ align 4,literals@start=$ +literal@ustrings equ align 2 +literal@astrings equ align 1 + +macro literals { + match j,literal@words,literal@ustrings,literal@astrings\{ + irp i,j\\{ + i + \\} + \} + literal@words equ align 4,literals@start=$ + literal@ustrings equ align 2 + literal@astrings equ align 1 +} diff --git a/include/macro/armresrc.inc b/include/macro/armresrc.inc new file mode 100644 index 0000000..2c5028c --- /dev/null +++ b/include/macro/armresrc.inc @@ -0,0 +1,19 @@ + +;Macroinstructions for making resources for WinCE with FASMARM +;By default this file is included from "WINCE.INC". + + dq fix dd + dd fix dw + dw fix dh + rq fix rd + rd fix rw + rw fix rh + + include 'macro\resource.inc' + + rw fix rw + rd fix rd + rq fix rq + dw fix dw + dd fix dd + dq fix dq diff --git a/include/macro/armstruc.inc b/include/macro/armstruc.inc new file mode 100644 index 0000000..b98956f --- /dev/null +++ b/include/macro/armstruc.inc @@ -0,0 +1,199 @@ + +;Macroinstructions for defining data structures with FASMARM +;By default this file is included from "WINCE.INC". + +macro struct name + { fields@struct equ name + match child parent, name \{ fields@struct equ child,fields@\#parent \} + sub@struct equ + struc db [val] \{ \common define field@struct .,db, + fields@struct equ fields@struct,field@struct \} + struc dh [val] \{ \common define field@struct .,dh, + fields@struct equ fields@struct,field@struct \} + struc du [val] \{ \common define field@struct .,du, + fields@struct equ fields@struct,field@struct \} + struc dw [val] \{ \common define field@struct .,dw, + fields@struct equ fields@struct,field@struct \} + struc dd [val] \{ \common define field@struct .,dd, + fields@struct equ fields@struct,field@struct \} + struc rb count \{ define field@struct .,db,count dup (?) + fields@struct equ fields@struct,field@struct \} + struc rh count \{ define field@struct .,dh,count dup (?) + fields@struct equ fields@struct,field@struct \} + struc rw count \{ define field@struct .,dw,count dup (?) + fields@struct equ fields@struct,field@struct \} + struc rd count \{ define field@struct .,dd,count dup (?) + fields@struct equ fields@struct,field@struct \} + macro db [val] \{ \common \local anonymous + define field@struct anonymous,db, + fields@struct equ fields@struct,field@struct \} + macro dh [val] \{ \common \local anonymous + define field@struct anonymous,dh, + fields@struct equ fields@struct,field@struct \} + macro du [val] \{ \common \local anonymous + define field@struct anonymous,du, + fields@struct equ fields@struct,field@struct \} + macro dw [val] \{ \common \local anonymous + define field@struct anonymous,dw, + fields@struct equ fields@struct,field@struct \} + macro dd [val] \{ \common \local anonymous + define field@struct anonymous,dd, + fields@struct equ fields@struct,field@struct \} + macro rb count \{ \local anonymous + define field@struct anonymous,db,count dup (?) + fields@struct equ fields@struct,field@struct \} + macro rh count \{ \local anonymous + define field@struct anonymous,dh,count dup (?) + fields@struct equ fields@struct,field@struct \} + macro rw count \{ \local anonymous + define field@struct anonymous,dw,count dup (?) + fields@struct equ fields@struct,field@struct \} + macro rd count \{ \local anonymous + define field@struct anonymous,dd,count dup (?) + fields@struct equ fields@struct,field@struct \} + macro union \{ fields@struct equ fields@struct,,union,< + sub@struct equ union \} + macro struct \{ fields@struct equ fields@struct,,substruct,< + sub@struct equ substruct \} + virtual at 0 } + +macro ends + { match , sub@struct \{ restruc db,dh,du,dw,dd + restruc rb,rh,rw,rd + purge db,dh,du,dw,dd + purge rb,rh,rw,rd + purge union,struct + match name=,fields,fields@struct \\{ fields@struct equ + make@struct name,fields + define fields@\\#name fields \\} + end virtual \} + match any, sub@struct \{ fields@struct equ fields@struct> \} + restore sub@struct } + +macro make@struct name,[field,type,def] + { common + if $ + display 'Error: definition of ',`name,' contains illegal instructions.',0Dh,0Ah + err + end if + local define + define equ name + forward + local sub + match , field \{ make@substruct type,name,sub def + define equ define,.,sub, \} + match any, field \{ define equ define,.#field,type, \} + common + match fields, define \{ define@struct fields \} } + +macro define@struct name,[field,type,def] + { common + local list + list equ + forward + if ~ field eq . + name#field type def + sizeof.#name#field = $ - name#field + else + label name#.#type + rb sizeof.#type + end if + local value + match any, list \{ list equ list, \} + list equ list + common + sizeof.#name = $ + restruc name + match values, list \{ + struc name value \\{ + match any, fields@struct \\\{ fields@struct equ fields@struct,.,name, \\\} + match , fields@struct \\\{ label . + forward + match , value \\\\{ field type def \\\\} + match any, value \\\\{ field type value + if ~ field eq . + rb sizeof.#name#field - ($-field) + end if \\\\} + common \\\} \\} + macro name value \\{ + forward + match , value \\\{ type def \\\} + match any, value \\\{ \\\local ..field + ..field: type value + if ~ field eq . + rb sizeof.#name#field - ($-..field) + end if \\\} + common \\} \} } +macro enable@substruct + { macro make@substruct substruct,parent,name,[field,type,def] + \{ \common + \local define + define equ parent,name + \forward + \local sub + match , field \\{ match any, type \\\{ enable@substruct + make@substruct type,name,sub def + purge make@substruct + define equ define,.,sub, \\\} \\} + match any, field \\{ define equ define,.\#field,type, \\} + \common + match fields, define \\{ define@\#substruct fields \\} \} } + +enable@substruct + +macro define@union parent,name,[field,type,def] + { common + virtual at parent#.#name + forward + if ~ field eq . + virtual at parent#.#name + parent#field type def + sizeof.#parent#field = $ - parent#field + end virtual + if sizeof.#parent#field > $ - parent#.#name + rb sizeof.#parent#field - ($ - parent#.#name) + end if + else + label name#.#type at parent#.#name + if sizeof.#type > $ - parent#.#name + rb sizeof.#type - ($ - parent#.#name) + end if + end if + common + sizeof.#name = $ - parent#.#name + end virtual + struc name [value] \{ \common + label .\#name + last@union equ + forward + match any, last@union \\{ virtual at .\#name + field type def + end virtual \\} + match , last@union \\{ match , value \\\{ field type def \\\} + match any, value \\\{ field type value \\\} \\} + last@union equ field + common rb sizeof.#name - ($ - .\#name) \} } + +macro define@substruct parent,name,[field,type,def] + { common + virtual at parent#.#name + forward + if ~ field eq . + parent#field type def + sizeof.#parent#field = $ - parent#field + else + label name#.#type + rb sizeof.#type + end if + common + sizeof.#name = $ - parent#.#name + end virtual + struc name value \{ + label .\#name + forward + match , value \\{ field type def \\} + match any, value \\{ field type value + if ~ field eq . + rb sizeof.#parent#field - ($-field) + end if \\} + common \} } diff --git a/include/macro/importce.inc b/include/macro/importce.inc new file mode 100644 index 0000000..e681daf --- /dev/null +++ b/include/macro/importce.inc @@ -0,0 +1,67 @@ +;FASMARM extension macros: +; +;Macros for imports section in PE file generation +; +;LIBRARY: +; +; Usage: library name1,string1,name2,string2,... +; +; name - a prefix for program labels identifying data structures +; string - a text ascii string identifying the DLL filename +; +; +;IMPORT: +; +; Usage: import name,function1,ordinal1,function2,ordinal2,... +; +; name - a prefix for program labels identifying data structures +; function - program label for the import +; ordinal - the DLL exported ordinal +; +;By default this file is included from "WINCE.INC". + + +macro library [name,string] { + common + align 4 + ;; data import + forward + if defined name#_required + dw RVA name,0,0,RVA name#_name,RVA name + end if + common + rw 5 + ;; end data + forward + if defined name#_required + name#_name: db string,0 + end if + common + align 4 +} + +macro import name,[function,ordinal] { + common + align 4 + name: + forward + if used _#function + _#function dw ordinal + end if + common + if $-name>0 + name#_required=1 + dw 0 + end if + forward + if used function + function: + if $+8-_#function<4096 + ldr pc,[pc,_#function-$-8] + else + ldr r12,[pc] + ldr pc,[r12] + dw _#function + end if + end if +} diff --git a/include/macro/procaps.inc b/include/macro/procaps.inc new file mode 100644 index 0000000..f71443c --- /dev/null +++ b/include/macro/procaps.inc @@ -0,0 +1,690 @@ +;FASMARM extension macros: +; +;High level procedure macros for APS (ARM Procedure Standard) calling +; +;The APS call standard requires the first four parameters to be passed in registers r0-r3, any remaining +;parameters are placed on the stack and pushed in reverse order. The stack is always full descending. +;Caller always restores the stack. Any return values are in r0-r3. +; +;r4-r11 must always be preserved by procedures. +;r12 is always a scratch register and considered corruptable. +;r13 is always the stack register and is always used in full descending mode. +;r14 is always the return address and considered corruptable. +; +;These macros are NOT compatible with thumb mode +; +; +;APSCALL: +; +; Usage: apscall name, arg1, size[arg2], addr arg3, [arg4], 'string', *'string', 'A'+0, ... +; +; name - required - specifies the name of the target procedure +; args - optional - any arguments required by the target procedure +; addr - refers to a PC relative address or a frame pointer relative address +; size - size override operator, can be byte, sbyte, hword, shword or word +; byte - zero extended byte value to 32 bit +; sbyte - sign extended byte value to 32 bit +; hword - zero extended half word value to 32 bit +; shword - sign extended half word value to 32 bit +; word - 32 bit value +; [arg] - value stored at address arg +; 'string' - literal ascii string placed directly in the code stream. For convenience +; *'string' - literal unicode string placed directly in the code stream. For convenience +; 'A'+0 - immediate value zero extended to 32 bit, can be 1 through 4 characters in length +; +; NOTE: "apscall" is safe to use inside an SP frame based procedure. The macro properly allocates the stack. +; +; +;PROC: +; +; Usage: proc name base reg uses [reg, reg-reg, reg] nospill ,arg1, arg2, arg3, ... +; +; paramters: +; +; name - required - specifies the name of the procedure +; base reg - optional - specifies the base register to use for the stack frame, default is R11 (fp) +; uses [.] - optional - lists registers to be saved upon entry and restored upon exit. Square brackets are required. +; NOTE: if you specify LR to be saved it will be automatically restored to PC upon exit +; nospill - optional - specifies the first four parameters are not to be spilled to the stack upon entry +; See the "To spill or not to spill?" note +; args - optional - input arguments from calling procedure, must be started with and separated by commas +; +; "name" must be first. +; "base reg", "uses [.]" and "nospill" can be specified in any order after "name". +; "args" must be placed last. +; +; To spill or not to spill? +; +; By omitting the "nospill" optional the proc macro will spill the first four arguments to the stack upon entry. +; This creates the most reliable way to access input parameters at the small cost of extra object code. +; By using the "nospill" option the first four arguments are aliased to the registers r0-r3 directly. +; "nospill" mode is best suited for leaf and "register light" procedures where using the stack is unneccesary. +; Accessing the first four parameters is different between the two cases: +; +; eg1. proc foo nospill, bar1, bar2, bar3, bar4, bar5 +; mov r3,bar2 ;mov r3,r1 - from here on bar4 (r3) has been lost! +; mov r0,bar2 ;mov r0,r1 - from here on bar1 (r0) has been lost! +; mov r5,bar1 ;ERROR: bar1 (r0) was destroyed above +; lea r4,[bar3] ;invalid: bar3 (r2) is not in memory +; ldr r4,[bar3] ;invalid: bar3 (r2) is not in memory +; ldr r4,[bar5] ;okay: ldr r0,[fp] +; endp +; +; compare to this: +; +; eg2. proc foo, bar1, bar2, bar3, bar4, bar5 +; mov r3,bar2 ;add r3,fp,4 +; lea r3,[bar2] ;add r3,fp,4 +; ldr r0,[bar2] ;ldr r0,[fp,4] +; ldr r5,[bar1] ;ldr r5,[fp] +; lea r4,[bar3] ;add r4,fp,8 +; ldr r4,[bar5] ;ldr r4,[fp,10h] +; endp +; +; and also compare to this: +; +; eg3. proc foo uses[r4-r6, lr], bar1, bar2, bar3, bar4, bar5 +; mov r3,bar2 ;add r3,fp,4 +; ldr r0,[bar2] ;ldr r0,[fp,4] +; ldr r5,[bar1] ;ldr r5,[fp] +; lea r4,[bar3] ;add r4,fp,8 +; ldr r4,[bar5] ;ldr r4,[fp,20h] ;note the different offset from above +; endp +; +; +; The stack frame: +; +; eg4. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6", +; then: "proc MyFunc uses [fp, r4, lr], arg1, ..." creates a stack frame that looks like this: +; +; arg6 - pushed by calling procedure higher addresses up here +; arg5 - pushed by calling procedure <---------------^------------- FP points here +; saved reg lr - pushed by proc | +; saved reg fp - pushed by proc | +; saved reg r4 - pushed by proc | +; arg4 (reg r3) - pushed by proc | +; arg3 (reg r2) - pushed by proc | +; arg2 (reg r1) - pushed by proc v +; arg1 (reg r0) - pushed by proc lower addresses down here +; locals data - uninitialised data <-- SP points here +; +; NOTE: the order of register saving is always highest (r15) to lowest (r0) regardless of the +; order they are specified in the "uses" statement. +; +; +; eg5. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6", +; then: "proc MyFunc base r4 uses [r4, lr] nospill, arg1, ..." creates a stack frame that looks like this: +; +; arg6 - pushed by calling procedure higher addresses up here +; arg5 - pushed by calling procedure <---------------^------------- R4 points here +; saved reg lr - pushed by proc v +; saved reg r4 - pushed by proc lower addresses down here +; locals data - uninitialised data <-- SP points here +; +; NOTE: The first four arguments are still in registers r0-r3 and have not been spilled to the stack +; +; +; eg6. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6", +; then: "proc MyFunc base sp uses [lr] nospill, arg1, ..." creates a stack frame that looks like this: +; +; arg6 - pushed by calling procedure higher addresses up here +; arg5 - pushed by calling procedure | +; saved reg lr - pushed by proc lower addresses down here +; locals data - uninitialised data <-- SP points here +; +; NOTE: Using sp based addressing requires special attention. The "apscall" macro has been +; designed to properly issue parameters when using sp based variables but your code must +; always restore sp before executing "apscall" or "ret". +; +; +;LOCALS/ENDL: +; +; Usage: locals | endl +; +; Valid inside a proc/endp pair only. Declares uninitialised locally addressable variables. +; You can use any number of locals/endl pairs, they are all concatenated together on the stack at runtime. +; +; eg7. proc foo +; locals +; varw dw ? +; varh dh ? +; varb db 100 dup (?) +; endl +; mov r1,'x' +; strb r1,[varb+2] +; lea r2,[varw] +; ... +; endp +; +; +;LOCAL: +; +; Usage: local name definition | local name:type | local name[count]:type +; +; Valid inside a proc/endp pair only. Declares uninitialised locally addressable variables. +; You can use any number of local definitions, they are all concatenated together on the stack at runtime. +; +; name - the symbolic name of the variable +; count - must be numeric +; type - one of BYTE, HWORD, WORD, DWORD or a structure name +; definition - the variable's definition statement +; +; eg8. local MyVar1 db ? +; local MyVar2 rb 8 +; local MyVar3:HWORD +; local MyVar4[0x100]:BYTE +; +; +;RET: +; +; Usage: ret(cond) +; +; Valid inside a proc/endp pair only. Restores the state and returns to the calling procedure. +; +; The worst case generated code by ret is three instructions for non-sp based procedures, and four +; instructions plus one literal for sp based precedures. +; +; +;ENDP: +; +; Usage: endp +; +; Ends the current "proc", freeing all local scope equates. +; +; +;POP/PUSH: +; +; Usage: push reg, reg-reg, reg, ... | pop reg, reg-reg, reg, ... +; +; At least one reg required in the list. Convience macros for optimal full descending stack operations. +; +; +;LEA: +; +; Usage: lea(cond) reg, [address] +; +; Convienience macro to access locations that are PC or local frame based. +; The macro automatically determines whether the address is a local variable or external variable +; and generates the appropriate code. +; +; +; General note: You may notice that some instructions below use uppercase, this is to integrate with the +; literals macros in ARMLIRTL.INC. +; +;By default this file is included from "WINCE.INC". + +macro def_ustring labl,[string] {common labl dU string} +macro def_astring labl,[string] {common labl dB string} + +macro apscall function,[parameter] { + common + local pcount,tempcount,found,.skip,.size,param,last_value,temp,size,instr,i_s,msize + virtual + nop + temp=$-$$ + end virtual + if temp<>4 + halt ;APSCALL macro NOT usable in thumb mode + end if + if ~ parameter eq + if .size + b .skip + end if + temp=$ + tempcount=0 + reverse + local ..arg + found equ no + match i[like]za,:parameter: \{ found equ \} + match =no:*ustring,found:parameter \{ + def_ustring ..arg,ustring,0 + found equ \} + match =no:some=,more,found:parameter \{ + def_astring ..arg,parameter,0 + found equ \} + match =no,found \{ + if parameter eqtype '' + def_astring ..arg,parameter,0 + end if \} + tempcount=tempcount+1 + common + pcount=tempcount + align 4 + .size=$-temp + if .size + .skip: + end if + lastvalue=1 shl 63 + tempcount=0 + reverse + if tempcount<(pcount-4) + found equ no + define param parameter + match [address],parameter \{ + LDR lr,[address] + lastvalue=1 shl 63 + str lr,[sp,-tempcount*4-4] + found equ yes \} + irp i_s,b:byte:byte,sb:sbyte:byte,h:hword:hword,sh:shword:hword,:word:word \{ + match instr:msize:size,LDR\#i_s \\{ + match =msize[address],parameter \\\{ + instr lr,size[address] + lastvalue=1 shl 63 + str lr,[sp,-tempcount*4-4] + found equ yes \\\}\\}\} + match =addr address,param \{ + lea lr,[address] + lastvalue=1 shl 63 + str lr,[sp,-tempcount*4-4] + found equ yes \} + match value =no,parameter found \{ + if defined ..arg + lastvalue=1 shl 63 + ADD lr,pc,..arg-$-8 + str lr,[sp,-tempcount*4-4] + else if value eqtype r0 + str value,[sp,-tempcount*4-4] + else if value eqtype 0 + virtual + dw value + load temp word from $-4 + end virtual + if temp <> lastvalue + MOV lr,value + end if + lastvalue=temp + str lr,[sp,-tempcount*4-4] + else + MOV lr,value + lastvalue=1 shl 63 + str lr,[sp,-tempcount*4-4] + end if \} + end if + rept 4 p:0 \{\reverse + if tempcount=pcount-p-1 + found equ no + match [address],parameter \\{ + LDR r\#p,[address] + found equ yes \\} + irp i_s,b:byte:byte,sb:sbyte:byte,h:hword:hword,sh:shword:hword,:word:word \\{ + match instr:msize:size,LDR\\#i_s \\\{ + match =msize[address],parameter \\\\{ + instr r\#p,size[address] + found equ yes \\\\}\\\}\\} + match =addr address,param \\{ + lea r\#p,[address] + found equ yes \\} + match value =no,parameter found \\{ + if ~ defined ..arg & value eqtype 0 + virtual + dw value + load temp word from $-4 + end virtual + end if + if defined ..arg + ADD r\#p,pc,..arg-$-8 + else if value eqtype 0 & lastvalue = temp + MOV r\#p,lr + else if ~ r\#p eq value + MOV r\#p,value + end if \\} + end if + \} + tempcount=tempcount+1 + common + else + pcount=0 + end if + if pcount>4 + sub sp,sp,(pcount-4)*4 + end if + if defined _#function & _#function-$-8<4096 & _#function-$-8>-4096 + mov lr,pc + ldr pc,[pc,_#function-$-8] + else + bl function + end if + if pcount>4 + add sp,sp,(pcount-4)*4 + end if +} + +macro popcount val,result { + local r + r=0 + repeat 16 + r=r+(((val)shr(%-1))and 1) + end repeat + result=r +} + +macro push [list] { + common + local bits,popc + virtual + stmdb sp!,{list\} + load bits hword from $-4 + end virtual + popcount bits,popc + if popc=1 + str list,[sp,-4]! + else + stmdb sp!,{list\} + end if +} + +macro pop [list] { + common + local bits,popc + virtual + ldmia sp!,{list\} + load bits hword from $-4 + end virtual + popcount bits,popc + if popc=1 + ldr list,[sp],+4 + else + ldmia sp!,{list\} + end if +} + +irp cond,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo { + macro push#cond [list] \{ + \common + \local bits,popc + virtual + stm#cond#db sp!,\\{list\\} + load bits hword from $-4 + end virtual + popcount bits,popc + if popc=1 + str#cond list,[sp,-4]! + else + stm#cond#db sp!,\\{list\\} + end if + \} + macro pop#cond [list] \{ + \common + \local bits,popc + virtual + ldm#cond#ia sp!,\\{list\\} + load bits hword from $-4 + end virtual + popcount bits,popc + if popc=1 + ldr#cond list,[sp],+4 + else + ldm#cond#ia sp!,\\{list\\} + end if + \} +} + +macro proc [parameter] { + common + local use,pname,parg,stack_count,bits,curr_off,locals_size,regbase,locals_names,spill,spill_size,param_count + match n remaining,parameter: \{pname equ n\} + if used pname + use equ + parg equ + locals_names equ + regbase equ fp + spill equ all + match junk =uses[u] remaining,parameter: \{use equ u\} + match junk =base b remaining,parameter: \{regbase equ b\} + match junk =nospill remaining,parameter: \{spill equ no\} + match :junk=,remaining,use:parameter \{parg equ remaining\} + match u:junk]=,remaining,use:parameter \{parg equ remaining\} + match :u:junk]foo=,remaining,parg:use:parameter \{parg equ remaining\} + match ,parg \{spill equ no\} + match =all:p1=,p2=,p3=,more,spill:parg\{spill equ ,r0,r1,r2,r3\} + match =all:p1=,p2=,p3,spill:parg\{spill equ ,r0,r1,r2\} + match =all:p1=,p2,spill:parg\{spill equ ,r0,r1\} + match =all:p1,spill:parg\{spill equ ,r0\} + match =no:p1=,p2=,p3=,p4=,more,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2,p4 r3\\{match a r,arg\\\{a equ r\\\}\\}spill equ\} + match =no:p1=,p2=,p3=,p4,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2,p4 r3\\{match a r,arg\\\{a equ r\\\}\\}spill equ\} + match =no:p1=,p2=,p3,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2\\{match a r,arg\\\{a equ r\\\}\\}spill equ\} + match =no:p1=,p2,spill:parg\{irp arg,p1 r0,p2 r1\\{match a r,arg\\\{a equ r\\\}\\}spill equ\} + match =no:p1,spill:parg\{p1 equ r0\} + match =no,spill\{spill equ\} + match =,any,spill \{ + virtual at 0 + ldmia sp!,{any\\} + load bits hword from $-4 + popcount bits,spill_count + end virtual + \} + match ,spill\{spill_count=0\} + match any,use \{ + virtual at 0 + ldmia sp!,{any\\} + load bits hword from $-4 + popcount bits,stack_count + end virtual + \} + match ,use\{stack_count=0\} + curr_off=0 + match =,junk:args,spill:parg \{ + irp arg,args \\{ + \\local ..arg + arg equ ..arg + if curr_off<4 + if regbase eq sp + virtual at regbase+curr_off*4+locals_size + else if param_count >= 4 + virtual at regbase-(4-curr_off+stack_count)*4 + else + virtual at regbase-(param_count-curr_off+stack_count)*4 + end if + ..arg dw ? + end virtual + else + if regbase eq sp + virtual at regbase+stack_count*4+curr_off*4+locals_size + else + virtual at regbase+(curr_off-4)*4 + end if + ..arg dw ? + end virtual + end if + curr_off=curr_off+1 + \\} + param_count=curr_off + \} + match :p1=,p2=,p3=,p4=,others,spill:parg \{ + param_count=5 + if regbase eq sp + virtual at regbase+(stack_count+spill_count)*4+locals_size + else + virtual at regbase + end if + irp arg,others \\{ + \\local ..arg + arg equ ..arg + ..arg dw ? + \\} + end virtual + \} + align 4 + use32 + pname: + match :=,regs,use:spill\{push regs\} + match junk,use\{push use spill\} + if (~ regbase eq sp) & ((locals_size+spill_count) | (defined param_count & param_count>4)) + add regbase,sp,(stack_count+spill_count)*4 + end if + if (locals_size) + SUB sp,sp,locals_size + end if + irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{ + match rt:sb1:AD2:ld:ldia:xb,ret\#cond:sub\#cond:ADD\#cond:ldr\#cond:ldm\#cond\#ia:bx\#cond\\{ + macro rt \\\{ + if (~ regbase eq sp) & ((locals_size+spill_count) | (defined param_count & param_count>4)) + sb1 sp,regbase,stack_count*4 + end if + if (regbase eq sp) & locals_size+spill_count + AD2 sp,sp,locals_size+spill_count*4 + end if + if stack_count>1 + ldia sp!,{use\\\\} + store hword ((bits and 0x3fff)+((bits and 0x4000)shl 1)) at $-4 + if ~ bits and 0x4000 + xb lr + end if + else if stack_count=1 + if use eq lr + ld pc,[sp],+4 + else + ld use,[sp],+4 + xb lr + end if + else + xb lr + end if + \\\} + \\} + \} + curr_off=0 + local in_locals + in_locals=0 + macro locals \{ + if in_locals + halt - locals is not allowed to be recursive + end if + if regbase eq sp + virtual at regbase+curr_off + else + virtual at regbase-locals_size+curr_off-((stack_count+spill_count)*4) + end if + in_locals=1 + \} + local ..s,size,reserve,op,def,copy + macro \local [arg] \{ + \common + locals + \forward + found equ no + define copy arg + match name[count]:type,copy \\{ + irp op,BYTE rb,HWORD rh,WORD rw,DWORD rd \\\{ + match size reserve,op \\\\{ + match =size,type \\\\\{ + name reserve count + found equ \\\\\}\\\\}\\\} + match =no,found \\\{ + virtual + name type + ..s=$-$$ + end virtual + rb count*..s + found equ \\\} + \\} + match =no:name:type,found:copy \\{ + irp op,BYTE db,HWORD dh,WORD dw,DWORD dd \\\{ + match size def,op \\\\{ + match =size,type \\\\\{ + name def ? + found equ \\\\\}\\\\}\\\} + match =no,found \\\{ + name type + found equ \\\} + \\} + match =no,found \\{ arg \\} + \common + endl + \} + macro endl \{ + in_locals=0 + curr_off=curr_off+$-$$ + end virtual + \} + macro close_proc \{ + locals_size=(curr_off+3)and not 3 + match a,parg \\{ restore a \\} + match =,a,locals_names \\{ restore a \\} + restruc db,dh,du,dw,dd,rb,rh,rw,rd + \} + irp op,db 1,dh 2,du 2,dw 4,dd 4,rb 1,rh 2,rw 4,rd 4 \{ + \local already + match str bytes,op \\{ + struc str [v]\\\{ + \\\common + \\\local ..arg + already equ no + match foo =. bar,:locals_names:\\\\{already equ\\\\} + match =no,already\\\\{ + locals_names equ locals_names,. + . equ ..arg + \\\\} + times ($$-$-curr_off)and(bytes-1) db ? + . str v + \\\} + \\} + \} + irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{ + \local ad + match inst,lea\#cond\\{ + macro inst dest,var \\\{ + found equ no + define copy var + match [v=+off],copy \\\\{ + match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{ + ad dest,regbase,v-regbase+off + found equ + \\\\\} + \\\\} + match [v=-off],copy \\\\{ + match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{ + ad dest,regbase,v-regbase-off + found equ + \\\\\} + \\\\} + match [v=,off],copy \\\\{ + match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{ + ad dest,regbase,v-regbase+off + found equ + \\\\\} + \\\\} + match [v]:=no,copy:found \\\\{ + match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{ + ad dest,regbase,v-regbase + found equ + \\\\\} + \\\\} + match ad:[v]:=no,ADD\#cond:copy:found \\\\{ + ad dest,pc,v-$-8 + found equ + \\\\} + match =no,found\\\\{ + halt ;malformed expression, use: lea reg,[address] + \\\\} + \\\} + \\} + \} +} + +macro endp { + close_proc + purge locals,endl,close_proc,local + irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo\{ + purge lea\#cond + purge ret\#cond + \} + end if +} + +irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo { + local found,inst,ad,d,v + match inst,lea#cond\{ + macro inst dest,var \\{ + found equ no + match ad:d:[v],ADD#cond:dest:var \\\{ + ad d,pc,v-$-8 + found equ + \\\} + match =no,found \\\{ + halt ;malformed expression, use: lea reg,[address] + \\\} + \\} + \} +} + diff --git a/include/wince.inc b/include/wince.inc new file mode 100644 index 0000000..58dad25 --- /dev/null +++ b/include/wince.inc @@ -0,0 +1,8 @@ + +;WinCE programming headers +;By default this file is included from "WINCEX.INC". + +include 'macro\procaps.inc' +include 'macro\importce.inc' +include 'macro\armresrc.inc' +include 'macro\armstruc.inc' diff --git a/include/wincex.inc b/include/wincex.inc new file mode 100644 index 0000000..b34afe3 --- /dev/null +++ b/include/wincex.inc @@ -0,0 +1,22 @@ + +;Extended WinCE programming headers + + format PE GUI + + include 'wince.inc' + include 'macro\armlitrl.inc' + +macro .code {section '.text' code readable executable} +macro .data {section '.data' data readable writeable} + +macro .end begin { + entry begin + section '.idata' import readable writeable + library coredll,'COREDLL.DLL' + include 'apice\coredll.inc' +} + +macro endp { + literals + endp +} diff --git a/source/armtable.inc b/source/armtable.inc new file mode 100644 index 0000000..b22ac3e --- /dev/null +++ b/source/armtable.inc @@ -0,0 +1,11321 @@ +; ARMv8 assembler core module v1.44 for flat assembler, +; Copyright (c) 2005-2023, Revolution. +; All rights reserved. +; +; Some portions are Copyright (c) 1999-2016, Tomasz Grysztar. +; All rights reserved. + +macro dw [value] { + forward + assert value >= 0 + dw value +} + +include_variable db 'INCLUDE',0 + +symbol_characters db 27 + db 9,0Ah,0Dh,1Ah,20h,'+-/*=<>()[]{}:,|&~#`;\' + +preprocessor_directives: + db 6,'define' + dw define_symbolic_constant-directive_handler + db 7,'include' + dw include_file-directive_handler + db 3,'irp' + dw irp_directive-directive_handler + db 4,'irps' + dw irps_directive-directive_handler + db 4,'irpv' + dw irpv_directive-directive_handler + db 5,'macro' + dw define_macro-directive_handler + db 5,'match' + dw match_directive-directive_handler + db 8,'postpone' + dw postpone_directive-directive_handler + db 5,'purge' + dw purge_macro-directive_handler + db 4,'rept' + dw rept_directive-directive_handler + db 7,'restore' + dw restore_equ_constant-directive_handler + db 7,'restruc' + dw purge_struc-directive_handler + db 5,'struc' + dw define_struc-directive_handler + db 0 + +macro_directives: + db 6,'common' + dw common_block-directive_handler + db 7,'forward' + dw forward_block-directive_handler + db 5,'local' + dw local_symbols-directive_handler + db 7,'reverse' + dw reverse_block-directive_handler + db 0 + +preprocessor_special_symbols: + db 4,'file' + dw preprocessed_file_value-directive_handler + db 4,'line' + dw preprocessed_line_value-directive_handler + db 0 + +operators: + db 1,'+',80h + db 1,'-',81h + db 1,'*',90h + db 1,'/',91h + db 3,'and',0B0h + db 3,'mod',0A0h + db 2,'or',0B1h + db 3,'shl',0C0h + db 3,'shr',0C1h + db 3,'xor',0B2h + db 0 + +single_operand_operators: + db 1,'+',082h + db 1,'-',083h + db 3,'bsf',0E0h + db 3,'bsr',0E1h + db 3,'fit',0D1h ;ARM operator fit + db 3,'not',0D0h + db 3,'plt',0F1h + db 3,'rva',0F0h + db 0 + +directive_operators: + db 5,'align',8Ch + db 2,'as',86h + db 2,'at',80h + db 11,'coprocessor',08Eh ;ARM coprocessor instructions selected + db 7,'defined',88h + db 8,'definite',8Ah + db 3,'dup',81h + db 2,'eq',0F0h + db 6,'eqtype',0F7h + db 4,'from',82h + db 2,'in',0F6h + db 2,'on',84h + db 9,'processor',08Fh ;ARM processor instructions selected + db 3,'ptr',85h + db 10,'relativeto',0F8h + db 4,'used',89h + db 0 + +address_sizes: + db 0 + +symbols: + dw symbols_1-symbols,(symbols_2-symbols_1)/(1+2) + dw symbols_2-symbols,(symbols_3-symbols_2)/(2+2) + dw symbols_3-symbols,(symbols_4-symbols_3)/(3+2) + dw symbols_4-symbols,(symbols_5-symbols_4)/(4+2) + dw symbols_5-symbols,(symbols_6-symbols_5)/(5+2) + dw symbols_6-symbols,(symbols_7-symbols_6)/(6+2) + dw symbols_7-symbols,(symbols_8-symbols_7)/(7+2) + dw symbols_8-symbols,(symbols_9-symbols_8)/(8+2) + dw symbols_9-symbols,(symbols_10-symbols_9)/(9+2) + dw symbols_10-symbols,(symbols_11-symbols_10)/(10+2) + dw symbols_11-symbols,(symbols_12-symbols_11)/(11+2) + dw symbols_12-symbols,(symbols_13-symbols_12)/(12+2) + dw symbols_13-symbols,(symbols_14-symbols_13)/(13+2) + dw symbols_14-symbols,(symbols_15-symbols_14)/(14+2) + dw symbols_15-symbols,(symbols_16-symbols_15)/(15+2) + dw symbols_16-symbols,(symbols_17-symbols_16)/(16+2) + dw symbols_17-symbols,(symbols_end-symbols_17)/(17+2) + +base_@16 = 0x1010 +base_@16.size = 0x10 ;r0@16-r15@16 + +base_@32 = base_@16+base_@16.size +base_@32.size = 0x10 ;r0@32-r15@32 + +base_@64 = base_@32+base_@32.size +base_@64.size = 0x10 ;r0@64-r15@64 + +base_@128 = base_@64+base_@64.size +base_@128.size = 0x10 ;r0@128-r15@128 + +base_@256 = base_@128+base_@128.size +base_@256.size = 0x10 ;r0@256-r15@256 + +base_reg = base_@256+base_@256.size +base_reg.size = 0x10 ;r0-r15 + +dword_reg = base_reg+base_reg.size +dword_reg.size = 0x20 ;x0-x30,xzr + +size_opr = 0x1100 +size_opr.size = 33 ;byte,hword,word,dword,qword,dqword + +sys_at = 0x1200 +sys_at.size = 12 ;0-11 + +sys_dc = sys_at+sys_at.size +sys_dc.size = 8 ;0-7 + +sys_ic = sys_dc+sys_dc.size +sys_ic.size = 3 ;0-2 + +sys_tlbi = sys_ic+sys_ic.size +sys_tlbi.size = 32 ;0-31 + +sys_msr = sys_tlbi+sys_tlbi.size +sys_msr.size = 384 ;0-383 + +sys_pstate = sys_msr+sys_msr.size +sys_pstate.size = 2 ;daifclr, daifset + +base_reg! = sys_pstate+sys_pstate.size +base_reg!.size = 0x10 ;r0!-r15! + +vect_breg = base_reg!+base_reg!.size +vect_breg.size = 0x20 ;b0-b31 + +vect_hreg = vect_breg+vect_breg.size +vect_hreg.size = 0x20 ;h0-h31 + +vect_sreg = vect_hreg+vect_hreg.size +vect_sreg.size = 0x20 ;s0-s31 + +vfps_reg = vect_sreg +vfps_reg.size = 0x20 ;s0-s31 + +vect_dreg = vect_sreg+vect_sreg.size +vect_dreg.size = 0x20 ;d0-d31 + +vfpd_reg = vect_dreg +vfpd_reg.size = 0x20 ;d0-d31 + +vect_qreg = vect_dreg+vect_dreg.size +vect_qreg.size = 0x20 ;q0-q31 + +simd_qreg = vect_qreg +simd_qreg.size = 0x10 ;q0-q15 + +word_reg = vect_qreg+vect_qreg.size +word_reg.size = 0x21 ;w0-w30,wzr,wsp + +banked_reg = word_reg+word_reg.size +banked_reg.size = 0x3f ;0-62 + +vect_v8b = banked_reg+banked_reg.size +vect_v8b.size = 0x20 ;v0.8b-v31.8b + +vect_v16b = vect_v8b+vect_v8b.size +vect_v16b.size = 0x20 ;v0.16b-v31.16b + +vect_v4h = vect_v16b+vect_v16b.size +vect_v4h.size = 0x20 ;v0.4h-v31.4h + +vect_v8h = vect_v4h+vect_v4h.size +vect_v8h.size = 0x20 ;v0.8h-v31.8h + +vect_v2s = vect_v8h+vect_v8h.size +vect_v2s.size = 0x20 ;v0.2s-v31.2s + +vect_v4s = vect_v2s+vect_v2s.size +vect_v4s.size = 0x20 ;v0.4s-v31.4s + +vect_v2d = vect_v4s+vect_v4s.size +vect_v2d.size = 0x20 ;v0.2d-v31.2d + +vect_v1d = vect_v2d+vect_v2d.size +vect_v1d.size = 0x20 ;v0.1d-v31.1d + +vect_v1q = vect_v1d+vect_v1d.size +vect_v1q.size = 0x20 ;v0.1q-v31.1q + +vect_vb = vect_v1q+vect_v1q.size +vect_vb.size = 0x20 ;v0.b-v31.b + +vect_vh = vect_vb+vect_vb.size +vect_vh.size = 0x20 ;v0.h-v31.h + +vect_vs = vect_vh+vect_vh.size +vect_vs.size = 0x20 ;v0.s-v31.s + +vect_vd = vect_vs+vect_vs.size +vect_vd.size = 0x20 ;v0.d-v31.d + +cpro_sel = vect_vd+vect_vd.size +cpro_sel.size = 0x10 ;p0-p15 + +cpro_reg = cpro_sel+cpro_sel.size +cpro_reg.size = 0x10 ;c0-c15 + +shift_op = cpro_reg+cpro_reg.size +shift_op.size = 4 ;asr, lsl, lsr, ror + +rrx_op = shift_op+shift_op.size +rrx_op.size = 1 ;rrx + +msl_op = rrx_op+rrx_op.size +msl_op.size = 1 ;msl + +endian = msl_op+msl_op.size +endian.size = 2 ;be, le + +modifier = endian+endian.size +modifier.size = 2 ;!, ^ + +psr_reg = modifier+modifier.size +psr_reg.size = 16+16+3 ;cpse, spsr + +iflags = psr_reg+psr_reg.size +iflags.size = 8 ;a, i, f + +vfp_syst = iflags+iflags.size +vfp_syst.size = 11 ; + +acc_40bt = vfp_syst+vfp_syst.size +acc_40bt.size = 8 ;acc0-acc7 + +iwmmx_wreg = acc_40bt+acc_40bt.size +iwmmx_wreg.size = 0x10 ;wr0-wr15 + +iwmmx_creg = iwmmx_wreg+iwmmx_wreg.size +iwmmx_creg.size = 12 ; + +mvrk_areg = iwmmx_creg+iwmmx_creg.size +mvrk_areg.size = 1 ;a0 + +mvrk_psc = mvrk_areg+mvrk_areg.size +mvrk_psc.size = 1 ;dspsc + +fpa_freg = mvrk_psc+mvrk_psc.size +fpa_freg.size = 8 ;f0-f7 + +barrier = fpa_freg+fpa_freg.size +barrier.size = 0x10 ; + +condition = barrier+barrier.size +condition.size = 16 ; + +sysm_reg = condition+condition.size +sysm_reg.size = 21 ; + +xtnd_op = sysm_reg+sysm_reg.size +xtnd_op.size = 8 ; + +prf_op = xtnd_op+xtnd_op.size +prf_op.size = 2*8+2*2+1 + 1 ; + +assert prf_op+prf_op.size <= 0x1800 + + ; 0x18 mz, pe, elf, coff, pe64, elf64, binary + ; 0x19 code, data, dwarf, linkinfo, readable, writable, shareable, writeable, executable, linkremove, discardable, notpageable + ; 0x1a export, fixups, import, resource + ; 0x1b nx, dll, efi, gui, wdm, large, native, console, efiboot, efiruntime + ; 0x1c ms, ms64 + ; 0x1d static + ; 0x1e note, dynamic, interpreter + ; 0x1f cpu_sel, copro_sel + +cpu_sel.all32 = 0x1f00 +cpu_sel.all64 = 0x1f01 +copro_sel.all = 0x1f02 + +cpu_sel = 0x1f03 +cpu_sel.size = 37 + +copro_sel = cpu_sel+cpu_sel.size +copro_sel.size = 19 + +macro symbol_maker symbol,value {db symbol,(value) shr 8,(value) and 0xff} + +symbols_1: + symbol_maker '!',modifier+0 + symbol_maker '^',modifier+1 +symbols_2: + symbol_maker 'a0',mvrk_areg + symbol_maker 'a1',base_reg+0 + symbol_maker 'a2',base_reg+1 + symbol_maker 'a3',base_reg+2 + symbol_maker 'a4',base_reg+3 + symbol_maker 'al',condition+0xe + symbol_maker 'b0',vect_breg+0 + symbol_maker 'b1',vect_breg+1 + symbol_maker 'b2',vect_breg+2 + symbol_maker 'b3',vect_breg+3 + symbol_maker 'b4',vect_breg+4 + symbol_maker 'b5',vect_breg+5 + symbol_maker 'b6',vect_breg+6 + symbol_maker 'b7',vect_breg+7 + symbol_maker 'b8',vect_breg+8 + symbol_maker 'b9',vect_breg+9 + symbol_maker 'be',endian+1 + symbol_maker 'c0',cpro_reg+0 + symbol_maker 'c1',cpro_reg+1 + symbol_maker 'c2',cpro_reg+2 + symbol_maker 'c3',cpro_reg+3 + symbol_maker 'c4',cpro_reg+4 + symbol_maker 'c5',cpro_reg+5 + symbol_maker 'c6',cpro_reg+6 + symbol_maker 'c7',cpro_reg+7 + symbol_maker 'c8',cpro_reg+8 + symbol_maker 'c9',cpro_reg+9 + symbol_maker 'cc',condition+0x3 + symbol_maker 'cs',condition+0x2 + symbol_maker 'd0',vect_dreg+0 + symbol_maker 'd1',vect_dreg+1 + symbol_maker 'd2',vect_dreg+2 + symbol_maker 'd3',vect_dreg+3 + symbol_maker 'd4',vect_dreg+4 + symbol_maker 'd5',vect_dreg+5 + symbol_maker 'd6',vect_dreg+6 + symbol_maker 'd7',vect_dreg+7 + symbol_maker 'd8',vect_dreg+8 + symbol_maker 'd9',vect_dreg+9 +;; symbol_maker 'eq',condition+0x0 + symbol_maker 'f0',fpa_freg+0 + symbol_maker 'f1',fpa_freg+1 + symbol_maker 'f2',fpa_freg+2 + symbol_maker 'f3',fpa_freg+3 + symbol_maker 'f4',fpa_freg+4 + symbol_maker 'f5',fpa_freg+5 + symbol_maker 'f6',fpa_freg+6 + symbol_maker 'f7',fpa_freg+7 + symbol_maker 'fp',base_reg+11 + symbol_maker 'ge',condition+0xa + symbol_maker 'gt',condition+0xc + symbol_maker 'h0',vect_hreg+0 + symbol_maker 'h1',vect_hreg+1 + symbol_maker 'h2',vect_hreg+2 + symbol_maker 'h3',vect_hreg+3 + symbol_maker 'h4',vect_hreg+4 + symbol_maker 'h5',vect_hreg+5 + symbol_maker 'h6',vect_hreg+6 + symbol_maker 'h7',vect_hreg+7 + symbol_maker 'h8',vect_hreg+8 + symbol_maker 'h9',vect_hreg+9 + symbol_maker 'hi',condition+0x8 + symbol_maker 'hs',condition+0x2 + symbol_maker 'ip',base_reg+12 + symbol_maker 'ld',barrier+1101b + symbol_maker 'le',endian+0 +;; symbol_maker 'le',condition+0xd + symbol_maker 'lo',condition+0x3 + symbol_maker 'lr',base_reg+14 + symbol_maker 'ls',condition+0x9 + symbol_maker 'lt',condition+0xb + symbol_maker 'mi',condition+0x4 + symbol_maker 'ms',1Ch shl 8 + 41h + symbol_maker 'mz',18h shl 8 + 20h + symbol_maker 'ne',condition+0x1 + symbol_maker 'nv',condition+0xf + symbol_maker 'nx',1Bh shl 8 + 83h + symbol_maker 'p0',cpro_sel+0 + symbol_maker 'p1',cpro_sel+1 + symbol_maker 'p2',cpro_sel+2 + symbol_maker 'p3',cpro_sel+3 + symbol_maker 'p4',cpro_sel+4 + symbol_maker 'p5',cpro_sel+5 + symbol_maker 'p6',cpro_sel+6 + symbol_maker 'p7',cpro_sel+7 + symbol_maker 'p8',cpro_sel+8 + symbol_maker 'p9',cpro_sel+9 + symbol_maker 'pc',base_reg+15 + symbol_maker 'pe',18h shl 8 + 30h + symbol_maker 'pl',condition+0x5 + symbol_maker 'q0',vect_qreg+0 + symbol_maker 'q1',vect_qreg+1 + symbol_maker 'q2',vect_qreg+2 + symbol_maker 'q3',vect_qreg+3 + symbol_maker 'q4',vect_qreg+4 + symbol_maker 'q5',vect_qreg+5 + symbol_maker 'q6',vect_qreg+6 + symbol_maker 'q7',vect_qreg+7 + symbol_maker 'q8',vect_qreg+8 + symbol_maker 'q9',vect_qreg+9 + symbol_maker 'r0',base_reg+0 + symbol_maker 'r1',base_reg+1 + symbol_maker 'r2',base_reg+2 + symbol_maker 'r3',base_reg+3 + symbol_maker 'r4',base_reg+4 + symbol_maker 'r5',base_reg+5 + symbol_maker 'r6',base_reg+6 + symbol_maker 'r7',base_reg+7 + symbol_maker 'r8',base_reg+8 + symbol_maker 'r9',base_reg+9 + symbol_maker 's0',vect_sreg+0 + symbol_maker 's1',vect_sreg+1 + symbol_maker 's2',vect_sreg+2 + symbol_maker 's3',vect_sreg+3 + symbol_maker 's4',vect_sreg+4 + symbol_maker 's5',vect_sreg+5 + symbol_maker 's6',vect_sreg+6 + symbol_maker 's7',vect_sreg+7 + symbol_maker 's8',vect_sreg+8 + symbol_maker 's9',vect_sreg+9 + symbol_maker 'sb',base_reg+9 + symbol_maker 'sl',base_reg+10 + symbol_maker 'sp',base_reg+13 + symbol_maker 'st',barrier+1110b + symbol_maker 'sy',barrier+1111b + symbol_maker 'v1',base_reg+4 + symbol_maker 'v2',base_reg+5 + symbol_maker 'v3',base_reg+6 + symbol_maker 'v4',base_reg+7 + symbol_maker 'v5',base_reg+8 + symbol_maker 'v6',base_reg+9 + symbol_maker 'v7',base_reg+10 + symbol_maker 'v8',base_reg+11 + symbol_maker 'vc',condition+0x7 + symbol_maker 'vs',condition+0x6 + symbol_maker 'w0',word_reg+0 + symbol_maker 'w1',word_reg+1 + symbol_maker 'w2',word_reg+2 + symbol_maker 'w3',word_reg+3 + symbol_maker 'w4',word_reg+4 + symbol_maker 'w5',word_reg+5 + symbol_maker 'w6',word_reg+6 + symbol_maker 'w7',word_reg+7 + symbol_maker 'w8',word_reg+8 + symbol_maker 'w9',word_reg+9 + symbol_maker 'x0',dword_reg+0 + symbol_maker 'x1',dword_reg+1 + symbol_maker 'x2',dword_reg+2 + symbol_maker 'x3',dword_reg+3 + symbol_maker 'x4',dword_reg+4 + symbol_maker 'x5',dword_reg+5 + symbol_maker 'x6',dword_reg+6 + symbol_maker 'x7',dword_reg+7 + symbol_maker 'x8',dword_reg+8 + symbol_maker 'x9',dword_reg+9 +symbols_3: + symbol_maker 'a1!',base_reg!+0 + symbol_maker 'a2!',base_reg!+1 + symbol_maker 'a3!',base_reg!+2 + symbol_maker 'a4!',base_reg!+3 + symbol_maker 'asr',shift_op+2 + symbol_maker 'b10',vect_breg+10 + symbol_maker 'b11',vect_breg+11 + symbol_maker 'b12',vect_breg+12 + symbol_maker 'b13',vect_breg+13 + symbol_maker 'b14',vect_breg+14 + symbol_maker 'b15',vect_breg+15 + symbol_maker 'b16',vect_breg+16 + symbol_maker 'b17',vect_breg+17 + symbol_maker 'b18',vect_breg+18 + symbol_maker 'b19',vect_breg+19 + symbol_maker 'b20',vect_breg+20 + symbol_maker 'b21',vect_breg+21 + symbol_maker 'b22',vect_breg+22 + symbol_maker 'b23',vect_breg+23 + symbol_maker 'b24',vect_breg+24 + symbol_maker 'b25',vect_breg+25 + symbol_maker 'b26',vect_breg+26 + symbol_maker 'b27',vect_breg+27 + symbol_maker 'b28',vect_breg+28 + symbol_maker 'b29',vect_breg+29 + symbol_maker 'b30',vect_breg+30 + symbol_maker 'b31',vect_breg+31 + symbol_maker 'c10',cpro_reg+10 + symbol_maker 'c11',cpro_reg+11 + symbol_maker 'c12',cpro_reg+12 + symbol_maker 'c13',cpro_reg+13 + symbol_maker 'c14',cpro_reg+14 + symbol_maker 'c15',cpro_reg+15 + symbol_maker 'csw',sys_dc+(sys_encode_csw-sys_encode_table_dc) shr 1 + symbol_maker 'd10',vect_dreg+10 + symbol_maker 'd11',vect_dreg+11 + symbol_maker 'd12',vect_dreg+12 + symbol_maker 'd13',vect_dreg+13 + symbol_maker 'd14',vect_dreg+14 + symbol_maker 'd15',vect_dreg+15 + symbol_maker 'd16',vect_dreg+16 + symbol_maker 'd17',vect_dreg+17 + symbol_maker 'd18',vect_dreg+18 + symbol_maker 'd19',vect_dreg+19 + symbol_maker 'd20',vect_dreg+20 + symbol_maker 'd21',vect_dreg+21 + symbol_maker 'd22',vect_dreg+22 + symbol_maker 'd23',vect_dreg+23 + symbol_maker 'd24',vect_dreg+24 + symbol_maker 'd25',vect_dreg+25 + symbol_maker 'd26',vect_dreg+26 + symbol_maker 'd27',vect_dreg+27 + symbol_maker 'd28',vect_dreg+28 + symbol_maker 'd29',vect_dreg+29 + symbol_maker 'd30',vect_dreg+30 + symbol_maker 'd31',vect_dreg+31 + symbol_maker 'dll',1Bh shl 8 + 80h + symbol_maker 'efi',1Bh shl 10 + symbol_maker 'elf',18h shl 8 + 50h + symbol_maker 'fp!',base_reg!+11 + symbol_maker 'gui',1Bh shl 8 + 2 + symbol_maker 'h10',vect_hreg+10 + symbol_maker 'h11',vect_hreg+11 + symbol_maker 'h12',vect_hreg+12 + symbol_maker 'h13',vect_hreg+13 + symbol_maker 'h14',vect_hreg+14 + symbol_maker 'h15',vect_hreg+15 + symbol_maker 'h16',vect_hreg+16 + symbol_maker 'h17',vect_hreg+17 + symbol_maker 'h18',vect_hreg+18 + symbol_maker 'h19',vect_hreg+19 + symbol_maker 'h20',vect_hreg+20 + symbol_maker 'h21',vect_hreg+21 + symbol_maker 'h22',vect_hreg+22 + symbol_maker 'h23',vect_hreg+23 + symbol_maker 'h24',vect_hreg+24 + symbol_maker 'h25',vect_hreg+25 + symbol_maker 'h26',vect_hreg+26 + symbol_maker 'h27',vect_hreg+27 + symbol_maker 'h28',vect_hreg+28 + symbol_maker 'h29',vect_hreg+29 + symbol_maker 'h30',vect_hreg+30 + symbol_maker 'h31',vect_hreg+31 + symbol_maker 'ip!',base_reg!+12 + symbol_maker 'ish',barrier+1011b + symbol_maker 'isw',sys_dc+(sys_encode_isw-sys_encode_table_dc) shr 1 + symbol_maker 'lr!',base_reg!+14 + symbol_maker 'lsl',shift_op+0 + symbol_maker 'lsr',shift_op+1 + symbol_maker 'msl',msl_op+0 + symbol_maker 'msp',sysm_reg+8 + symbol_maker 'nsh',barrier+0111b + symbol_maker 'osh',barrier+0011b + symbol_maker 'p10',cpro_sel+10 + symbol_maker 'p11',cpro_sel+11 + symbol_maker 'p12',cpro_sel+12 + symbol_maker 'p13',cpro_sel+13 + symbol_maker 'p14',cpro_sel+14 + symbol_maker 'p15',cpro_sel+15 + symbol_maker 'pc!',base_reg!+15 + symbol_maker 'psp',sysm_reg+9 + symbol_maker 'q10',vect_qreg+10 + symbol_maker 'q11',vect_qreg+11 + symbol_maker 'q12',vect_qreg+12 + symbol_maker 'q13',vect_qreg+13 + symbol_maker 'q14',vect_qreg+14 + symbol_maker 'q15',vect_qreg+15 + symbol_maker 'q16',vect_qreg+16 + symbol_maker 'q17',vect_qreg+17 + symbol_maker 'q18',vect_qreg+18 + symbol_maker 'q19',vect_qreg+19 + symbol_maker 'q20',vect_qreg+20 + symbol_maker 'q21',vect_qreg+21 + symbol_maker 'q22',vect_qreg+22 + symbol_maker 'q23',vect_qreg+23 + symbol_maker 'q24',vect_qreg+24 + symbol_maker 'q25',vect_qreg+25 + symbol_maker 'q26',vect_qreg+26 + symbol_maker 'q27',vect_qreg+27 + symbol_maker 'q28',vect_qreg+28 + symbol_maker 'q29',vect_qreg+29 + symbol_maker 'q30',vect_qreg+30 + symbol_maker 'q31',vect_qreg+31 + symbol_maker 'r0!',base_reg!+0 + symbol_maker 'r1!',base_reg!+1 + symbol_maker 'r10',base_reg+10 + symbol_maker 'r11',base_reg+11 + symbol_maker 'r12',base_reg+12 + symbol_maker 'r13',base_reg+13 + symbol_maker 'r14',base_reg+14 + symbol_maker 'r15',base_reg+15 + symbol_maker 'r2!',base_reg!+2 + symbol_maker 'r3!',base_reg!+3 + symbol_maker 'r4!',base_reg!+4 + symbol_maker 'r5!',base_reg!+5 + symbol_maker 'r6!',base_reg!+6 + symbol_maker 'r7!',base_reg!+7 + symbol_maker 'r8!',base_reg!+8 + symbol_maker 'r9!',base_reg!+9 + symbol_maker 'ror',shift_op+3 + symbol_maker 'rrx',rrx_op+0 + symbol_maker 's10',vect_sreg+10 + symbol_maker 's11',vect_sreg+11 + symbol_maker 's12',vect_sreg+12 + symbol_maker 's13',vect_sreg+13 + symbol_maker 's14',vect_sreg+14 + symbol_maker 's15',vect_sreg+15 + symbol_maker 's16',vect_sreg+16 + symbol_maker 's17',vect_sreg+17 + symbol_maker 's18',vect_sreg+18 + symbol_maker 's19',vect_sreg+19 + symbol_maker 's20',vect_sreg+20 + symbol_maker 's21',vect_sreg+21 + symbol_maker 's22',vect_sreg+22 + symbol_maker 's23',vect_sreg+23 + symbol_maker 's24',vect_sreg+24 + symbol_maker 's25',vect_sreg+25 + symbol_maker 's26',vect_sreg+26 + symbol_maker 's27',vect_sreg+27 + symbol_maker 's28',vect_sreg+28 + symbol_maker 's29',vect_sreg+29 + symbol_maker 's30',vect_sreg+30 + symbol_maker 's31',vect_sreg+31 + symbol_maker 'sb!',base_reg!+9 + symbol_maker 'sl!',base_reg!+10 + symbol_maker 'sp!',base_reg!+13 + symbol_maker 'v1!',base_reg!+4 + symbol_maker 'v2!',base_reg!+5 + symbol_maker 'v3!',base_reg!+6 + symbol_maker 'v4!',base_reg!+7 + symbol_maker 'v5!',base_reg!+8 + symbol_maker 'v6!',base_reg!+9 + symbol_maker 'v7!',base_reg!+10 + symbol_maker 'v8!',base_reg!+11 + symbol_maker 'w10',word_reg+10 + symbol_maker 'w11',word_reg+11 + symbol_maker 'w12',word_reg+12 + symbol_maker 'w13',word_reg+13 + symbol_maker 'w14',word_reg+14 + symbol_maker 'w15',word_reg+15 + symbol_maker 'w16',word_reg+16 + symbol_maker 'w17',word_reg+17 + symbol_maker 'w18',word_reg+18 + symbol_maker 'w19',word_reg+19 + symbol_maker 'w20',word_reg+20 + symbol_maker 'w21',word_reg+21 + symbol_maker 'w22',word_reg+22 + symbol_maker 'w23',word_reg+23 + symbol_maker 'w24',word_reg+24 + symbol_maker 'w25',word_reg+25 + symbol_maker 'w26',word_reg+26 + symbol_maker 'w27',word_reg+27 + symbol_maker 'w28',word_reg+28 + symbol_maker 'w29',word_reg+29 + symbol_maker 'w30',word_reg+30 + symbol_maker 'wdm',1Bh shl 8 + 81h + symbol_maker 'wr0',iwmmx_wreg+0 + symbol_maker 'wr1',iwmmx_wreg+1 + symbol_maker 'wr2',iwmmx_wreg+2 + symbol_maker 'wr3',iwmmx_wreg+3 + symbol_maker 'wr4',iwmmx_wreg+4 + symbol_maker 'wr5',iwmmx_wreg+5 + symbol_maker 'wr6',iwmmx_wreg+6 + symbol_maker 'wr7',iwmmx_wreg+7 + symbol_maker 'wr8',iwmmx_wreg+8 + symbol_maker 'wr9',iwmmx_wreg+9 + symbol_maker 'wsp',word_reg+32 + symbol_maker 'wzr',word_reg+31 + symbol_maker 'x10',dword_reg+10 + symbol_maker 'x11',dword_reg+11 + symbol_maker 'x12',dword_reg+12 + symbol_maker 'x13',dword_reg+13 + symbol_maker 'x14',dword_reg+14 + symbol_maker 'x15',dword_reg+15 + symbol_maker 'x16',dword_reg+16 + symbol_maker 'x17',dword_reg+17 + symbol_maker 'x18',dword_reg+18 + symbol_maker 'x19',dword_reg+19 + symbol_maker 'x20',dword_reg+20 + symbol_maker 'x21',dword_reg+21 + symbol_maker 'x22',dword_reg+22 + symbol_maker 'x23',dword_reg+23 + symbol_maker 'x24',dword_reg+24 + symbol_maker 'x25',dword_reg+25 + symbol_maker 'x26',dword_reg+26 + symbol_maker 'x27',dword_reg+27 + symbol_maker 'x28',dword_reg+28 + symbol_maker 'x29',dword_reg+29 + symbol_maker 'x30',dword_reg+30 + symbol_maker 'xzr',dword_reg+31 + symbol_maker 'zva',sys_dc+(sys_encode_zva-sys_encode_table_dc) shr 1 +symbols_4: + symbol_maker 'acc0',acc_40bt+0 + symbol_maker 'acc1',acc_40bt+1 + symbol_maker 'acc2',acc_40bt+2 + symbol_maker 'acc3',acc_40bt+3 + symbol_maker 'acc4',acc_40bt+4 + symbol_maker 'acc5',acc_40bt+5 + symbol_maker 'acc6',acc_40bt+6 + symbol_maker 'acc7',acc_40bt+7 + symbol_maker 'apsr',psr_reg+34 + symbol_maker 'byte',size_opr+1 + symbol_maker 'cisw',sys_dc+(sys_encode_cisw-sys_encode_table_dc) shr 1 + symbol_maker 'code',19h shl 8 + 5 + symbol_maker 'coff',18h shl 8 + 40h + symbol_maker 'cpsr',psr_reg+32 + symbol_maker 'cvac',sys_dc+(sys_encode_cvac-sys_encode_table_dc) shr 1 + symbol_maker 'cvau',sys_dc+(sys_encode_cvau-sys_encode_table_dc) shr 1 + symbol_maker 'daif',sys_msr+(sys_encode_daif-sys_encode_table_msr) shr 1 + symbol_maker 'data',19h shl 8 + 6 + symbol_maker 'epsr',sysm_reg+6 + symbol_maker 'fpcr',sys_msr+(sys_encode_fpcr-sys_encode_table_msr) shr 1 + symbol_maker 'fpsr',sys_msr+(sys_encode_fpsr-sys_encode_table_msr) shr 1 + symbol_maker 'ipsr',sysm_reg+5 + symbol_maker 'ivac',sys_dc+(sys_encode_ivac-sys_encode_table_dc) shr 1 + symbol_maker 'ivau',sys_ic+(sys_encode_ivau-sys_encode_table_ic) shr 1 + symbol_maker 'ms64',1Ch shl 8 + 49h + symbol_maker 'note',1Eh shl 8 + 4 + symbol_maker 'nzcv',sys_msr+(sys_encode_nzcv-sys_encode_table_msr) shr 1 + symbol_maker 'pe64',18h shl 8 + 3ch + symbol_maker 'r10!',base_reg!+10 + symbol_maker 'r11!',base_reg!+11 + symbol_maker 'r12!',base_reg!+12 + symbol_maker 'r13!',base_reg!+13 + symbol_maker 'r14!',base_reg!+14 + symbol_maker 'r15!',base_reg!+15 + symbol_maker 'spsr',psr_reg+33 + symbol_maker 'sxtb',xtnd_op+4 + symbol_maker 'sxth',xtnd_op+5 + symbol_maker 'sxtw',xtnd_op+6 + symbol_maker 'sxtx',xtnd_op+7 + symbol_maker 'syst',barrier+1110b + symbol_maker 'uxtb',xtnd_op+0 + symbol_maker 'uxth',xtnd_op+1 + symbol_maker 'uxtw',xtnd_op+2 + symbol_maker 'uxtx',xtnd_op+3 + symbol_maker 'v0.b',vect_vb+0 + symbol_maker 'v0.d',vect_vd+0 + symbol_maker 'v0.h',vect_vh+0 + symbol_maker 'v0.s',vect_vs+0 + symbol_maker 'v1.b',vect_vb+1 + symbol_maker 'v1.d',vect_vd+1 + symbol_maker 'v1.h',vect_vh+1 + symbol_maker 'v1.s',vect_vs+1 + symbol_maker 'v2.b',vect_vb+2 + symbol_maker 'v2.d',vect_vd+2 + symbol_maker 'v2.h',vect_vh+2 + symbol_maker 'v2.s',vect_vs+2 + symbol_maker 'v3.b',vect_vb+3 + symbol_maker 'v3.d',vect_vd+3 + symbol_maker 'v3.h',vect_vh+3 + symbol_maker 'v3.s',vect_vs+3 + symbol_maker 'v4.b',vect_vb+4 + symbol_maker 'v4.d',vect_vd+4 + symbol_maker 'v4.h',vect_vh+4 + symbol_maker 'v4.s',vect_vs+4 + symbol_maker 'v5.b',vect_vb+5 + symbol_maker 'v5.d',vect_vd+5 + symbol_maker 'v5.h',vect_vh+5 + symbol_maker 'v5.s',vect_vs+5 + symbol_maker 'v6.b',vect_vb+6 + symbol_maker 'v6.d',vect_vd+6 + symbol_maker 'v6.h',vect_vh+6 + symbol_maker 'v6.s',vect_vs+6 + symbol_maker 'v7.b',vect_vb+7 + symbol_maker 'v7.d',vect_vd+7 + symbol_maker 'v7.h',vect_vh+7 + symbol_maker 'v7.s',vect_vs+7 + symbol_maker 'v8.b',vect_vb+8 + symbol_maker 'v8.d',vect_vd+8 + symbol_maker 'v8.h',vect_vh+8 + symbol_maker 'v8.s',vect_vs+8 + symbol_maker 'v9.b',vect_vb+9 + symbol_maker 'v9.d',vect_vd+9 + symbol_maker 'v9.h',vect_vh+9 + symbol_maker 'v9.s',vect_vs+9 + symbol_maker 'vae1',sys_tlbi+(sys_encode_vae1-sys_encode_table_tlbi) shr 1 + symbol_maker 'vae2',sys_tlbi+(sys_encode_vae2-sys_encode_table_tlbi) shr 1 + symbol_maker 'vae3',sys_tlbi+(sys_encode_vae3-sys_encode_table_tlbi) shr 1 + symbol_maker 'wcid',iwmmx_creg+0 + symbol_maker 'wcon',iwmmx_creg+1 + symbol_maker 'word',size_opr+4 + symbol_maker 'wr10',iwmmx_wreg+10 + symbol_maker 'wr11',iwmmx_wreg+11 + symbol_maker 'wr12',iwmmx_wreg+12 + symbol_maker 'wr13',iwmmx_wreg+13 + symbol_maker 'wr14',iwmmx_wreg+14 + symbol_maker 'wr15',iwmmx_wreg+15 + symbol_maker 'xpsr',sysm_reg+3 +symbols_5: + symbol_maker 'alle1',sys_tlbi+(sys_encode_alle1-sys_encode_table_tlbi) shr 1 + symbol_maker 'alle2',sys_tlbi+(sys_encode_alle2-sys_encode_table_tlbi) shr 1 + symbol_maker 'alle3',sys_tlbi+(sys_encode_alle3-sys_encode_table_tlbi) shr 1 + symbol_maker 'civac',sys_dc+(sys_encode_civac-sys_encode_table_dc) shr 1 + symbol_maker 'dspsc',mvrk_psc+0 + symbol_maker 'dwarf',19h shl 8 + 0C0h + symbol_maker 'dword',size_opr+8 + symbol_maker 'eapsr',sysm_reg+2 + symbol_maker 'elf64',18h shl 8 + 58h + symbol_maker 'fpexc',vfp_syst+8 + symbol_maker 'fpscr',vfp_syst+1 + symbol_maker 'fpsid',vfp_syst+0 + symbol_maker 'hword',size_opr+2 + symbol_maker 'iallu',sys_ic+(sys_encode_iallu-sys_encode_table_ic) shr 1 + symbol_maker 'iapsr',sysm_reg+1 + symbol_maker 'iepsr',sysm_reg+7 + symbol_maker 'ishld',barrier+1001b + symbol_maker 'ishst',barrier+1010b + symbol_maker 'large',1Bh shl 8 + 82h + symbol_maker 'mvfr0',vfp_syst+7 + symbol_maker 'mvfr1',vfp_syst+6 + symbol_maker 'nshld',barrier+0101b + symbol_maker 'nshst',barrier+0110b + symbol_maker 'oshld',barrier+0001b + symbol_maker 'oshst',barrier+0010b + symbol_maker 'qword',size_opr+16 + symbol_maker 'r0@16',base_@16+0 + symbol_maker 'r0@32',base_@32+0 + symbol_maker 'r0@64',base_@64+0 + symbol_maker 'r1@16',base_@16+1 + symbol_maker 'r1@32',base_@32+1 + symbol_maker 'r1@64',base_@64+1 + symbol_maker 'r2@16',base_@16+2 + symbol_maker 'r2@32',base_@32+2 + symbol_maker 'r2@64',base_@64+2 + symbol_maker 'r3@16',base_@16+3 + symbol_maker 'r3@32',base_@32+3 + symbol_maker 'r3@64',base_@64+3 + symbol_maker 'r4@16',base_@16+4 + symbol_maker 'r4@32',base_@32+4 + symbol_maker 'r4@64',base_@64+4 + symbol_maker 'r5@16',base_@16+5 + symbol_maker 'r5@32',base_@32+5 + symbol_maker 'r5@64',base_@64+5 + symbol_maker 'r6@16',base_@16+6 + symbol_maker 'r6@32',base_@32+6 + symbol_maker 'r6@64',base_@64+6 + symbol_maker 'r7@16',base_@16+7 + symbol_maker 'r7@32',base_@32+7 + symbol_maker 'r7@64',base_@64+7 + symbol_maker 'r8@16',base_@16+8 + symbol_maker 'r8@32',base_@32+8 + symbol_maker 'r8@64',base_@64+8 + symbol_maker 'r9@16',base_@16+9 + symbol_maker 'r9@32',base_@32+9 + symbol_maker 'r9@64',base_@64+9 + symbol_maker 's1e0r',sys_at+(sys_encode_s1e0r-sys_encode_table_at) shr 1 + symbol_maker 's1e0w',sys_at+(sys_encode_s1e0w-sys_encode_table_at) shr 1 + symbol_maker 's1e1r',sys_at+(sys_encode_s1e1r-sys_encode_table_at) shr 1 + symbol_maker 's1e1w',sys_at+(sys_encode_s1e1w-sys_encode_table_at) shr 1 + symbol_maker 's1e2r',sys_at+(sys_encode_s1e2r-sys_encode_table_at) shr 1 + symbol_maker 's1e2w',sys_at+(sys_encode_s1e2w-sys_encode_table_at) shr 1 + symbol_maker 's1e3r',sys_at+(sys_encode_s1e3r-sys_encode_table_at) shr 1 + symbol_maker 's1e3w',sys_at+(sys_encode_s1e3w-sys_encode_table_at) shr 1 + symbol_maker 'spsel',sys_msr+(sys_encode_spsel-sys_encode_table_msr) shr 1 +;; symbol_maker 'spsel',sys_pstate+(sys_pencode_spsel-sys_encode_table_pstate) shr 1 + symbol_maker 'v0.1d',vect_v1d+0 + symbol_maker 'v0.1q',vect_v1q+0 + symbol_maker 'v0.2d',vect_v2d+0 + symbol_maker 'v0.2s',vect_v2s+0 + symbol_maker 'v0.4h',vect_v4h+0 + symbol_maker 'v0.4s',vect_v4s+0 + symbol_maker 'v0.8b',vect_v8b+0 + symbol_maker 'v0.8h',vect_v8h+0 + symbol_maker 'v1.1d',vect_v1d+1 + symbol_maker 'v1.1q',vect_v1q+1 + symbol_maker 'v1.2d',vect_v2d+1 + symbol_maker 'v1.2s',vect_v2s+1 + symbol_maker 'v1.4h',vect_v4h+1 + symbol_maker 'v1.4s',vect_v4s+1 + symbol_maker 'v1.8b',vect_v8b+1 + symbol_maker 'v1.8h',vect_v8h+1 + symbol_maker 'v10.b',vect_vb+10 + symbol_maker 'v10.d',vect_vd+10 + symbol_maker 'v10.h',vect_vh+10 + symbol_maker 'v10.s',vect_vs+10 + symbol_maker 'v11.b',vect_vb+11 + symbol_maker 'v11.d',vect_vd+11 + symbol_maker 'v11.h',vect_vh+11 + symbol_maker 'v11.s',vect_vs+11 + symbol_maker 'v12.b',vect_vb+12 + symbol_maker 'v12.d',vect_vd+12 + symbol_maker 'v12.h',vect_vh+12 + symbol_maker 'v12.s',vect_vs+12 + symbol_maker 'v13.b',vect_vb+13 + symbol_maker 'v13.d',vect_vd+13 + symbol_maker 'v13.h',vect_vh+13 + symbol_maker 'v13.s',vect_vs+13 + symbol_maker 'v14.b',vect_vb+14 + symbol_maker 'v14.d',vect_vd+14 + symbol_maker 'v14.h',vect_vh+14 + symbol_maker 'v14.s',vect_vs+14 + symbol_maker 'v15.b',vect_vb+15 + symbol_maker 'v15.d',vect_vd+15 + symbol_maker 'v15.h',vect_vh+15 + symbol_maker 'v15.s',vect_vs+15 + symbol_maker 'v16.b',vect_vb+16 + symbol_maker 'v16.d',vect_vd+16 + symbol_maker 'v16.h',vect_vh+16 + symbol_maker 'v16.s',vect_vs+16 + symbol_maker 'v17.b',vect_vb+17 + symbol_maker 'v17.d',vect_vd+17 + symbol_maker 'v17.h',vect_vh+17 + symbol_maker 'v17.s',vect_vs+17 + symbol_maker 'v18.b',vect_vb+18 + symbol_maker 'v18.d',vect_vd+18 + symbol_maker 'v18.h',vect_vh+18 + symbol_maker 'v18.s',vect_vs+18 + symbol_maker 'v19.b',vect_vb+19 + symbol_maker 'v19.d',vect_vd+19 + symbol_maker 'v19.h',vect_vh+19 + symbol_maker 'v19.s',vect_vs+19 + symbol_maker 'v2.1d',vect_v1d+2 + symbol_maker 'v2.1q',vect_v1q+2 + symbol_maker 'v2.2d',vect_v2d+2 + symbol_maker 'v2.2s',vect_v2s+2 + symbol_maker 'v2.4h',vect_v4h+2 + symbol_maker 'v2.4s',vect_v4s+2 + symbol_maker 'v2.8b',vect_v8b+2 + symbol_maker 'v2.8h',vect_v8h+2 + symbol_maker 'v20.b',vect_vb+20 + symbol_maker 'v20.d',vect_vd+20 + symbol_maker 'v20.h',vect_vh+20 + symbol_maker 'v20.s',vect_vs+20 + symbol_maker 'v21.b',vect_vb+21 + symbol_maker 'v21.d',vect_vd+21 + symbol_maker 'v21.h',vect_vh+21 + symbol_maker 'v21.s',vect_vs+21 + symbol_maker 'v22.b',vect_vb+22 + symbol_maker 'v22.d',vect_vd+22 + symbol_maker 'v22.h',vect_vh+22 + symbol_maker 'v22.s',vect_vs+22 + symbol_maker 'v23.b',vect_vb+23 + symbol_maker 'v23.d',vect_vd+23 + symbol_maker 'v23.h',vect_vh+23 + symbol_maker 'v23.s',vect_vs+23 + symbol_maker 'v24.b',vect_vb+24 + symbol_maker 'v24.d',vect_vd+24 + symbol_maker 'v24.h',vect_vh+24 + symbol_maker 'v24.s',vect_vs+24 + symbol_maker 'v25.b',vect_vb+25 + symbol_maker 'v25.d',vect_vd+25 + symbol_maker 'v25.h',vect_vh+25 + symbol_maker 'v25.s',vect_vs+25 + symbol_maker 'v26.b',vect_vb+26 + symbol_maker 'v26.d',vect_vd+26 + symbol_maker 'v26.h',vect_vh+26 + symbol_maker 'v26.s',vect_vs+26 + symbol_maker 'v27.b',vect_vb+27 + symbol_maker 'v27.d',vect_vd+27 + symbol_maker 'v27.h',vect_vh+27 + symbol_maker 'v27.s',vect_vs+27 + symbol_maker 'v28.b',vect_vb+28 + symbol_maker 'v28.d',vect_vd+28 + symbol_maker 'v28.h',vect_vh+28 + symbol_maker 'v28.s',vect_vs+28 + symbol_maker 'v29.b',vect_vb+29 + symbol_maker 'v29.d',vect_vd+29 + symbol_maker 'v29.h',vect_vh+29 + symbol_maker 'v29.s',vect_vs+29 + symbol_maker 'v3.1d',vect_v1d+3 + symbol_maker 'v3.1q',vect_v1q+3 + symbol_maker 'v3.2d',vect_v2d+3 + symbol_maker 'v3.2s',vect_v2s+3 + symbol_maker 'v3.4h',vect_v4h+3 + symbol_maker 'v3.4s',vect_v4s+3 + symbol_maker 'v3.8b',vect_v8b+3 + symbol_maker 'v3.8h',vect_v8h+3 + symbol_maker 'v30.b',vect_vb+30 + symbol_maker 'v30.d',vect_vd+30 + symbol_maker 'v30.h',vect_vh+30 + symbol_maker 'v30.s',vect_vs+30 + symbol_maker 'v31.b',vect_vb+31 + symbol_maker 'v31.d',vect_vd+31 + symbol_maker 'v31.h',vect_vh+31 + symbol_maker 'v31.s',vect_vs+31 + symbol_maker 'v4.1d',vect_v1d+4 + symbol_maker 'v4.1q',vect_v1q+4 + symbol_maker 'v4.2d',vect_v2d+4 + symbol_maker 'v4.2s',vect_v2s+4 + symbol_maker 'v4.4h',vect_v4h+4 + symbol_maker 'v4.4s',vect_v4s+4 + symbol_maker 'v4.8b',vect_v8b+4 + symbol_maker 'v4.8h',vect_v8h+4 + symbol_maker 'v5.1d',vect_v1d+5 + symbol_maker 'v5.1q',vect_v1q+5 + symbol_maker 'v5.2d',vect_v2d+5 + symbol_maker 'v5.2s',vect_v2s+5 + symbol_maker 'v5.4h',vect_v4h+5 + symbol_maker 'v5.4s',vect_v4s+5 + symbol_maker 'v5.8b',vect_v8b+5 + symbol_maker 'v5.8h',vect_v8h+5 + symbol_maker 'v6.1d',vect_v1d+6 + symbol_maker 'v6.1q',vect_v1q+6 + symbol_maker 'v6.2d',vect_v2d+6 + symbol_maker 'v6.2s',vect_v2s+6 + symbol_maker 'v6.4h',vect_v4h+6 + symbol_maker 'v6.4s',vect_v4s+6 + symbol_maker 'v6.8b',vect_v8b+6 + symbol_maker 'v6.8h',vect_v8h+6 + symbol_maker 'v7.1d',vect_v1d+7 + symbol_maker 'v7.1q',vect_v1q+7 + symbol_maker 'v7.2d',vect_v2d+7 + symbol_maker 'v7.2s',vect_v2s+7 + symbol_maker 'v7.4h',vect_v4h+7 + symbol_maker 'v7.4s',vect_v4s+7 + symbol_maker 'v7.8b',vect_v8b+7 + symbol_maker 'v7.8h',vect_v8h+7 + symbol_maker 'v8.1d',vect_v1d+8 + symbol_maker 'v8.1q',vect_v1q+8 + symbol_maker 'v8.2d',vect_v2d+8 + symbol_maker 'v8.2s',vect_v2s+8 + symbol_maker 'v8.4h',vect_v4h+8 + symbol_maker 'v8.4s',vect_v4s+8 + symbol_maker 'v8.8b',vect_v8b+8 + symbol_maker 'v8.8h',vect_v8h+8 + symbol_maker 'v9.1d',vect_v1d+9 + symbol_maker 'v9.1q',vect_v1q+9 + symbol_maker 'v9.2d',vect_v2d+9 + symbol_maker 'v9.2s',vect_v2s+9 + symbol_maker 'v9.4h',vect_v4h+9 + symbol_maker 'v9.4s',vect_v4s+9 + symbol_maker 'v9.8b',vect_v8b+9 + symbol_maker 'v9.8h',vect_v8h+9 + symbol_maker 'vaae1',sys_tlbi+(sys_encode_vaae1-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale1',sys_tlbi+(sys_encode_vale1-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale2',sys_tlbi+(sys_encode_vale2-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale3',sys_tlbi+(sys_encode_vale3-sys_encode_table_tlbi) shr 1 + symbol_maker 'wcasf',iwmmx_creg+3 + symbol_maker 'wcgr0',iwmmx_creg+8 + symbol_maker 'wcgr1',iwmmx_creg+9 + symbol_maker 'wcgr2',iwmmx_creg+10 + symbol_maker 'wcgr3',iwmmx_creg+11 + symbol_maker 'wcssf',iwmmx_creg+2 +symbols_6: + symbol_maker 'apsr_g',psr_reg+4 + symbol_maker 'aside1',sys_tlbi+(sys_encode_aside1-sys_encode_table_tlbi) shr 1 + symbol_maker 'binary',18h shl 8 + 10h + symbol_maker 'cpsr_c',psr_reg+1 + symbol_maker 'cpsr_f',psr_reg+8 + symbol_maker 'cpsr_s',psr_reg+4 + symbol_maker 'cpsr_x',psr_reg+2 + symbol_maker 'dqword',size_opr+32 + symbol_maker 'export',1Ah shl 8 + 0 + symbol_maker 'fixups',1Ah shl 8 + 5 + symbol_maker 'fpinst',vfp_syst+9 + symbol_maker 'import',1Ah shl 8 + 1 + symbol_maker 'lr_abt',banked_reg+20 + symbol_maker 'lr_fiq',banked_reg+14 + symbol_maker 'lr_irq',banked_reg+16 + symbol_maker 'lr_mon',banked_reg+28 + symbol_maker 'lr_svc',banked_reg+18 + symbol_maker 'lr_und',banked_reg+22 + symbol_maker 'lr_usr',banked_reg+6 + symbol_maker 'native',1Bh shl 8 + 1 + symbol_maker 'r0@128',base_@128+0 + symbol_maker 'r0@256',base_@256+0 + symbol_maker 'r10@16',base_@16+10 + symbol_maker 'r10@32',base_@32+10 + symbol_maker 'r10@64',base_@64+10 + symbol_maker 'r11@16',base_@16+11 + symbol_maker 'r11@32',base_@32+11 + symbol_maker 'r11@64',base_@64+11 + symbol_maker 'r12@16',base_@16+12 + symbol_maker 'r12@32',base_@32+12 + symbol_maker 'r12@64',base_@64+12 + symbol_maker 'r13@16',base_@16+13 + symbol_maker 'r13@32',base_@32+13 + symbol_maker 'r13@64',base_@64+13 + symbol_maker 'r14@16',base_@16+14 + symbol_maker 'r14@32',base_@32+14 + symbol_maker 'r14@64',base_@64+14 + symbol_maker 'r15@16',base_@16+15 + symbol_maker 'r15@32',base_@32+15 + symbol_maker 'r15@64',base_@64+15 + symbol_maker 'r1@128',base_@128+1 + symbol_maker 'r1@256',base_@256+1 + symbol_maker 'r2@128',base_@128+2 + symbol_maker 'r2@256',base_@256+2 + symbol_maker 'r3@128',base_@128+3 + symbol_maker 'r3@256',base_@256+3 + symbol_maker 'r4@128',base_@128+4 + symbol_maker 'r4@256',base_@256+4 + symbol_maker 'r5@128',base_@128+5 + symbol_maker 'r5@256',base_@256+5 + symbol_maker 'r6@128',base_@128+6 + symbol_maker 'r6@256',base_@256+6 + symbol_maker 'r7@128',base_@128+7 + symbol_maker 'r7@256',base_@256+7 + symbol_maker 'r8@128',base_@128+8 + symbol_maker 'r8@256',base_@256+8 + symbol_maker 'r8_fiq',banked_reg+8 + symbol_maker 'r8_usr',banked_reg+0 + symbol_maker 'r9@128',base_@128+9 + symbol_maker 'r9@256',base_@256+9 + symbol_maker 'r9_fiq',banked_reg+9 + symbol_maker 'r9_usr',banked_reg+1 + symbol_maker 's12e0r',sys_at+(sys_encode_s12e0r-sys_encode_table_at) shr 1 + symbol_maker 's12e0w',sys_at+(sys_encode_s12e0w-sys_encode_table_at) shr 1 + symbol_maker 's12e1r',sys_at+(sys_encode_s12e1r-sys_encode_table_at) shr 1 + symbol_maker 's12e1w',sys_at+(sys_encode_s12e1w-sys_encode_table_at) shr 1 + symbol_maker 'sp_abt',banked_reg+21 + symbol_maker 'sp_el0',sys_msr+(sys_encode_sp_el0-sys_encode_table_msr) shr 1 + symbol_maker 'sp_el1',sys_msr+(sys_encode_sp_el1-sys_encode_table_msr) shr 1 + symbol_maker 'sp_el2',sys_msr+(sys_encode_sp_el2-sys_encode_table_msr) shr 1 + symbol_maker 'sp_fiq',banked_reg+13 + symbol_maker 'sp_hyp',banked_reg+31 + symbol_maker 'sp_irq',banked_reg+17 + symbol_maker 'sp_mon',banked_reg+29 + symbol_maker 'sp_svc',banked_reg+19 + symbol_maker 'sp_und',banked_reg+23 + symbol_maker 'sp_usr',banked_reg+5 + symbol_maker 'spsr_c',psr_reg+1 + symbol_maker 'spsr_f',psr_reg+8 + symbol_maker 'spsr_s',psr_reg+4 + symbol_maker 'spsr_x',psr_reg+2 + symbol_maker 'static',1Dh shl 8 + 1 + symbol_maker 'v0.16b',vect_v16b+0 + symbol_maker 'v1.16b',vect_v16b+1 + symbol_maker 'v10.1d',vect_v1d+10 + symbol_maker 'v10.1q',vect_v1q+20 + symbol_maker 'v10.2d',vect_v2d+10 + symbol_maker 'v10.2s',vect_v2s+10 + symbol_maker 'v10.4h',vect_v4h+10 + symbol_maker 'v10.4s',vect_v4s+10 + symbol_maker 'v10.8b',vect_v8b+10 + symbol_maker 'v10.8h',vect_v8h+10 + symbol_maker 'v11.1d',vect_v1d+11 + symbol_maker 'v11.1q',vect_v1q+21 + symbol_maker 'v11.2d',vect_v2d+11 + symbol_maker 'v11.2s',vect_v2s+11 + symbol_maker 'v11.4h',vect_v4h+11 + symbol_maker 'v11.4s',vect_v4s+11 + symbol_maker 'v11.8b',vect_v8b+11 + symbol_maker 'v11.8h',vect_v8h+11 + symbol_maker 'v12.1d',vect_v1d+12 + symbol_maker 'v12.1q',vect_v1q+22 + symbol_maker 'v12.2d',vect_v2d+12 + symbol_maker 'v12.2s',vect_v2s+12 + symbol_maker 'v12.4h',vect_v4h+12 + symbol_maker 'v12.4s',vect_v4s+12 + symbol_maker 'v12.8b',vect_v8b+12 + symbol_maker 'v12.8h',vect_v8h+12 + symbol_maker 'v13.1d',vect_v1d+13 + symbol_maker 'v13.1q',vect_v1q+23 + symbol_maker 'v13.2d',vect_v2d+13 + symbol_maker 'v13.2s',vect_v2s+13 + symbol_maker 'v13.4h',vect_v4h+13 + symbol_maker 'v13.4s',vect_v4s+13 + symbol_maker 'v13.8b',vect_v8b+13 + symbol_maker 'v13.8h',vect_v8h+13 + symbol_maker 'v14.1d',vect_v1d+14 + symbol_maker 'v14.1q',vect_v1q+24 + symbol_maker 'v14.2d',vect_v2d+14 + symbol_maker 'v14.2s',vect_v2s+14 + symbol_maker 'v14.4h',vect_v4h+14 + symbol_maker 'v14.4s',vect_v4s+14 + symbol_maker 'v14.8b',vect_v8b+14 + symbol_maker 'v14.8h',vect_v8h+14 + symbol_maker 'v15.1d',vect_v1d+15 + symbol_maker 'v15.1q',vect_v1q+25 + symbol_maker 'v15.2d',vect_v2d+15 + symbol_maker 'v15.2s',vect_v2s+15 + symbol_maker 'v15.4h',vect_v4h+15 + symbol_maker 'v15.4s',vect_v4s+15 + symbol_maker 'v15.8b',vect_v8b+15 + symbol_maker 'v15.8h',vect_v8h+15 + symbol_maker 'v16.1d',vect_v1d+16 + symbol_maker 'v16.1q',vect_v1q+26 + symbol_maker 'v16.2d',vect_v2d+16 + symbol_maker 'v16.2s',vect_v2s+16 + symbol_maker 'v16.4h',vect_v4h+16 + symbol_maker 'v16.4s',vect_v4s+16 + symbol_maker 'v16.8b',vect_v8b+16 + symbol_maker 'v16.8h',vect_v8h+16 + symbol_maker 'v17.1d',vect_v1d+17 + symbol_maker 'v17.1q',vect_v1q+27 + symbol_maker 'v17.2d',vect_v2d+17 + symbol_maker 'v17.2s',vect_v2s+17 + symbol_maker 'v17.4h',vect_v4h+17 + symbol_maker 'v17.4s',vect_v4s+17 + symbol_maker 'v17.8b',vect_v8b+17 + symbol_maker 'v17.8h',vect_v8h+17 + symbol_maker 'v18.1d',vect_v1d+18 + symbol_maker 'v18.1q',vect_v1q+28 + symbol_maker 'v18.2d',vect_v2d+18 + symbol_maker 'v18.2s',vect_v2s+18 + symbol_maker 'v18.4h',vect_v4h+18 + symbol_maker 'v18.4s',vect_v4s+18 + symbol_maker 'v18.8b',vect_v8b+18 + symbol_maker 'v18.8h',vect_v8h+18 + symbol_maker 'v19.1d',vect_v1d+19 + symbol_maker 'v19.1q',vect_v1q+29 + symbol_maker 'v19.2d',vect_v2d+19 + symbol_maker 'v19.2s',vect_v2s+19 + symbol_maker 'v19.4h',vect_v4h+19 + symbol_maker 'v19.4s',vect_v4s+19 + symbol_maker 'v19.8b',vect_v8b+19 + symbol_maker 'v19.8h',vect_v8h+19 + symbol_maker 'v2.16b',vect_v16b+2 + symbol_maker 'v20.1d',vect_v1d+20 + symbol_maker 'v20.1q',vect_v1q+20 + symbol_maker 'v20.2d',vect_v2d+20 + symbol_maker 'v20.2s',vect_v2s+20 + symbol_maker 'v20.4h',vect_v4h+20 + symbol_maker 'v20.4s',vect_v4s+20 + symbol_maker 'v20.8b',vect_v8b+20 + symbol_maker 'v20.8h',vect_v8h+20 + symbol_maker 'v21.1d',vect_v1d+21 + symbol_maker 'v21.1q',vect_v1q+21 + symbol_maker 'v21.2d',vect_v2d+21 + symbol_maker 'v21.2s',vect_v2s+21 + symbol_maker 'v21.4h',vect_v4h+21 + symbol_maker 'v21.4s',vect_v4s+21 + symbol_maker 'v21.8b',vect_v8b+21 + symbol_maker 'v21.8h',vect_v8h+21 + symbol_maker 'v22.1d',vect_v1d+22 + symbol_maker 'v22.1q',vect_v1q+22 + symbol_maker 'v22.2d',vect_v2d+22 + symbol_maker 'v22.2s',vect_v2s+22 + symbol_maker 'v22.4h',vect_v4h+22 + symbol_maker 'v22.4s',vect_v4s+22 + symbol_maker 'v22.8b',vect_v8b+22 + symbol_maker 'v22.8h',vect_v8h+22 + symbol_maker 'v23.1d',vect_v1d+23 + symbol_maker 'v23.1q',vect_v1q+23 + symbol_maker 'v23.2d',vect_v2d+23 + symbol_maker 'v23.2s',vect_v2s+23 + symbol_maker 'v23.4h',vect_v4h+23 + symbol_maker 'v23.4s',vect_v4s+23 + symbol_maker 'v23.8b',vect_v8b+23 + symbol_maker 'v23.8h',vect_v8h+23 + symbol_maker 'v24.1d',vect_v1d+24 + symbol_maker 'v24.1q',vect_v1q+24 + symbol_maker 'v24.2d',vect_v2d+24 + symbol_maker 'v24.2s',vect_v2s+24 + symbol_maker 'v24.4h',vect_v4h+24 + symbol_maker 'v24.4s',vect_v4s+24 + symbol_maker 'v24.8b',vect_v8b+24 + symbol_maker 'v24.8h',vect_v8h+24 + symbol_maker 'v25.1d',vect_v1d+25 + symbol_maker 'v25.1q',vect_v1q+25 + symbol_maker 'v25.2d',vect_v2d+25 + symbol_maker 'v25.2s',vect_v2s+25 + symbol_maker 'v25.4h',vect_v4h+25 + symbol_maker 'v25.4s',vect_v4s+25 + symbol_maker 'v25.8b',vect_v8b+25 + symbol_maker 'v25.8h',vect_v8h+25 + symbol_maker 'v26.1d',vect_v1d+26 + symbol_maker 'v26.1q',vect_v1q+26 + symbol_maker 'v26.2d',vect_v2d+26 + symbol_maker 'v26.2s',vect_v2s+26 + symbol_maker 'v26.4h',vect_v4h+26 + symbol_maker 'v26.4s',vect_v4s+26 + symbol_maker 'v26.8b',vect_v8b+26 + symbol_maker 'v26.8h',vect_v8h+26 + symbol_maker 'v27.1d',vect_v1d+27 + symbol_maker 'v27.1q',vect_v1q+27 + symbol_maker 'v27.2d',vect_v2d+27 + symbol_maker 'v27.2s',vect_v2s+27 + symbol_maker 'v27.4h',vect_v4h+27 + symbol_maker 'v27.4s',vect_v4s+27 + symbol_maker 'v27.8b',vect_v8b+27 + symbol_maker 'v27.8h',vect_v8h+27 + symbol_maker 'v28.1d',vect_v1d+28 + symbol_maker 'v28.1q',vect_v1q+28 + symbol_maker 'v28.2d',vect_v2d+28 + symbol_maker 'v28.2s',vect_v2s+28 + symbol_maker 'v28.4h',vect_v4h+28 + symbol_maker 'v28.4s',vect_v4s+28 + symbol_maker 'v28.8b',vect_v8b+28 + symbol_maker 'v28.8h',vect_v8h+28 + symbol_maker 'v29.1d',vect_v1d+29 + symbol_maker 'v29.1q',vect_v1q+29 + symbol_maker 'v29.2d',vect_v2d+29 + symbol_maker 'v29.2s',vect_v2s+29 + symbol_maker 'v29.4h',vect_v4h+29 + symbol_maker 'v29.4s',vect_v4s+29 + symbol_maker 'v29.8b',vect_v8b+29 + symbol_maker 'v29.8h',vect_v8h+29 + symbol_maker 'v3.16b',vect_v16b+3 + symbol_maker 'v30.1d',vect_v1d+30 + symbol_maker 'v30.1q',vect_v1q+30 + symbol_maker 'v30.2d',vect_v2d+30 + symbol_maker 'v30.2s',vect_v2s+30 + symbol_maker 'v30.4h',vect_v4h+30 + symbol_maker 'v30.4s',vect_v4s+30 + symbol_maker 'v30.8b',vect_v8b+30 + symbol_maker 'v30.8h',vect_v8h+30 + symbol_maker 'v31.1d',vect_v1d+31 + symbol_maker 'v31.1q',vect_v1q+31 + symbol_maker 'v31.2d',vect_v2d+31 + symbol_maker 'v31.2s',vect_v2s+31 + symbol_maker 'v31.4h',vect_v4h+31 + symbol_maker 'v31.4s',vect_v4s+31 + symbol_maker 'v31.8b',vect_v8b+31 + symbol_maker 'v31.8h',vect_v8h+31 + symbol_maker 'v4.16b',vect_v16b+4 + symbol_maker 'v5.16b',vect_v16b+5 + symbol_maker 'v6.16b',vect_v16b+6 + symbol_maker 'v7.16b',vect_v16b+7 + symbol_maker 'v8.16b',vect_v16b+8 + symbol_maker 'v9.16b',vect_v16b+9 + symbol_maker 'vaale1',sys_tlbi+(sys_encode_vaale1-sys_encode_table_tlbi) shr 1 + symbol_maker 'vae1is',sys_tlbi+(sys_encode_vae1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vae2is',sys_tlbi+(sys_encode_vae2is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vae3is',sys_tlbi+(sys_encode_vae3is-sys_encode_table_tlbi) shr 1 +symbols_7: + symbol_maker 'alle1is',sys_tlbi+(sys_encode_alle1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'alle2is',sys_tlbi+(sys_encode_alle2is-sys_encode_table_tlbi) shr 1 + symbol_maker 'alle3is',sys_tlbi+(sys_encode_alle3is-sys_encode_table_tlbi) shr 1 + symbol_maker 'basepri',sysm_reg+17 + symbol_maker 'console',1Bh shl 8 + 3 + symbol_maker 'control',sysm_reg+20 + symbol_maker 'cpsr_cf',psr_reg+1 + symbol_maker 'cpsr_cs',psr_reg+1 + symbol_maker 'cpsr_cx',psr_reg+1 + symbol_maker 'cpsr_fc',psr_reg+8 + symbol_maker 'cpsr_fs',psr_reg+8 + symbol_maker 'cpsr_fx',psr_reg+8 + symbol_maker 'cpsr_sc',psr_reg+4 + symbol_maker 'cpsr_sf',psr_reg+4 + symbol_maker 'cpsr_sx',psr_reg+4 + symbol_maker 'cpsr_xc',psr_reg+2 + symbol_maker 'cpsr_xf',psr_reg+2 + symbol_maker 'cpsr_xs',psr_reg+2 + symbol_maker 'cpu32_a',cpu_sel+CPU32_CAPABILITY_A + symbol_maker 'cpu32_e',cpu_sel+CPU32_CAPABILITY_E + symbol_maker 'cpu32_j',cpu_sel+CPU32_CAPABILITY_J + symbol_maker 'cpu32_k',cpu_sel+CPU32_CAPABILITY_K + symbol_maker 'cpu32_m',cpu_sel+CPU32_CAPABILITY_M + symbol_maker 'cpu32_p',cpu_sel+CPU32_CAPABILITY_P + symbol_maker 'cpu32_x',cpu_sel+CPU32_CAPABILITY_X + symbol_maker 'cpu32_z',cpu_sel+CPU32_CAPABILITY_Z + symbol_maker 'ctr_el0',sys_msr+(sys_encode_ctr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'daifclr',sys_pstate+(sys_pencode_daifclr-sys_encode_table_pstate) shr 1 + symbol_maker 'daifset',sys_pstate+(sys_pencode_daifset-sys_encode_table_pstate) shr 1 + symbol_maker 'dlr_el0',sys_msr+(sys_encode_dlr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'dynamic',1Eh shl 8 + 2 + symbol_maker 'efiboot',1Bh shl 8 + 11 + symbol_maker 'elr_el1',sys_msr+(sys_encode_elr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'elr_el2',sys_msr+(sys_encode_elr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'elr_el3',sys_msr+(sys_encode_elr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'elr_hyp',banked_reg+30 + symbol_maker 'esr_el1',sys_msr+(sys_encode_esr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'esr_el2',sys_msr+(sys_encode_esr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'esr_el3',sys_msr+(sys_encode_esr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'far_el1',sys_msr+(sys_encode_far_el1-sys_encode_table_msr) shr 1 + symbol_maker 'far_el2',sys_msr+(sys_encode_far_el2-sys_encode_table_msr) shr 1 + symbol_maker 'far_el3',sys_msr+(sys_encode_far_el3-sys_encode_table_msr) shr 1 + symbol_maker 'fpinst2',vfp_syst+10 + symbol_maker 'hcr_el2',sys_msr+(sys_encode_hcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ialluis',sys_ic+(sys_encode_ialluis-sys_encode_table_ic) shr 1 + symbol_maker 'ipas2e1',sys_tlbi+(sys_encode_ipas2e1-sys_encode_table_tlbi) shr 1 + symbol_maker 'isr_el1',sys_msr+(sys_encode_isr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'par_el1',sys_msr+(sys_encode_par_el1-sys_encode_table_msr) shr 1 + symbol_maker 'primask',sysm_reg+16 + symbol_maker 'r10@128',base_@128+10 + symbol_maker 'r10@256',base_@256+10 + symbol_maker 'r10_fiq',banked_reg+10 + symbol_maker 'r10_usr',banked_reg+2 + symbol_maker 'r11@128',base_@128+11 + symbol_maker 'r11@256',base_@256+11 + symbol_maker 'r11_fiq',banked_reg+11 + symbol_maker 'r11_usr',banked_reg+3 + symbol_maker 'r12@128',base_@128+12 + symbol_maker 'r12@256',base_@256+12 + symbol_maker 'r12_fiq',banked_reg+12 + symbol_maker 'r12_usr',banked_reg+4 + symbol_maker 'r13@128',base_@128+13 + symbol_maker 'r13@256',base_@256+13 + symbol_maker 'r14@128',base_@128+14 + symbol_maker 'r14@256',base_@256+14 + symbol_maker 'r15@128',base_@128+15 + symbol_maker 'r15@256',base_@256+15 + symbol_maker 'rmr_el1',sys_msr+(sys_encode_rmr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'rmr_el2',sys_msr+(sys_encode_rmr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'rmr_el3',sys_msr+(sys_encode_rmr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'scr_el3',sys_msr+(sys_encode_scr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_cf',psr_reg+16+8+1 + symbol_maker 'spsr_cs',psr_reg+16+4+1 + symbol_maker 'spsr_cx',psr_reg+16+2+1 + symbol_maker 'spsr_fc',psr_reg+16+1+8 + symbol_maker 'spsr_fs',psr_reg+16+4+8 + symbol_maker 'spsr_fx',psr_reg+16+2+8 + symbol_maker 'spsr_sc',psr_reg+16+1+4 + symbol_maker 'spsr_sf',psr_reg+16+8+4 + symbol_maker 'spsr_sx',psr_reg+16+2+4 + symbol_maker 'spsr_xc',psr_reg+16+1+2 + symbol_maker 'spsr_xf',psr_reg+16+8+2 + symbol_maker 'spsr_xs',psr_reg+16+4+2 + symbol_maker 'tcr_el1',sys_msr+(sys_encode_tcr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'tcr_el2',sys_msr+(sys_encode_tcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'tcr_el3',sys_msr+(sys_encode_tcr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'v10.16b',vect_v16b+10 + symbol_maker 'v11.16b',vect_v16b+11 + symbol_maker 'v12.16b',vect_v16b+12 + symbol_maker 'v13.16b',vect_v16b+13 + symbol_maker 'v14.16b',vect_v16b+14 + symbol_maker 'v15.16b',vect_v16b+15 + symbol_maker 'v16.16b',vect_v16b+16 + symbol_maker 'v17.16b',vect_v16b+17 + symbol_maker 'v18.16b',vect_v16b+18 + symbol_maker 'v19.16b',vect_v16b+19 + symbol_maker 'v20.16b',vect_v16b+20 + symbol_maker 'v21.16b',vect_v16b+21 + symbol_maker 'v22.16b',vect_v16b+22 + symbol_maker 'v23.16b',vect_v16b+23 + symbol_maker 'v24.16b',vect_v16b+24 + symbol_maker 'v25.16b',vect_v16b+25 + symbol_maker 'v26.16b',vect_v16b+26 + symbol_maker 'v27.16b',vect_v16b+27 + symbol_maker 'v28.16b',vect_v16b+28 + symbol_maker 'v29.16b',vect_v16b+29 + symbol_maker 'v30.16b',vect_v16b+30 + symbol_maker 'v31.16b',vect_v16b+31 + symbol_maker 'vaae1is',sys_tlbi+(sys_encode_vaae1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale1is',sys_tlbi+(sys_encode_vale1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale2is',sys_tlbi+(sys_encode_vale2is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vale3is',sys_tlbi+(sys_encode_vale3is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vmalle1',sys_tlbi+(sys_encode_vmalle1-sys_encode_table_tlbi) shr 1 +symbols_8: + symbol_maker 'aidr_el1',sys_msr+(sys_encode_aidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'aside1is',sys_tlbi+(sys_encode_aside1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'cpsr_all',psr_reg+8+1 + symbol_maker 'cpsr_cfs',psr_reg+8+4+1 + symbol_maker 'cpsr_cfx',psr_reg+8+2+1 + symbol_maker 'cpsr_csf',psr_reg+8+4+1 + symbol_maker 'cpsr_csx',psr_reg+4+2+1 + symbol_maker 'cpsr_ctl',psr_reg+1 + symbol_maker 'cpsr_cxf',psr_reg+8+2+1 + symbol_maker 'cpsr_cxs',psr_reg+4+2+1 + symbol_maker 'cpsr_fcs',psr_reg+1+4+8 + symbol_maker 'cpsr_fcx',psr_reg+1+2+8 + symbol_maker 'cpsr_flg',psr_reg+8 + symbol_maker 'cpsr_fsc',psr_reg+1+4+8 + symbol_maker 'cpsr_fsx',psr_reg+4+2+8 + symbol_maker 'cpsr_fxc',psr_reg+1+2+8 + symbol_maker 'cpsr_fxs',psr_reg+4+2+8 + symbol_maker 'cpsr_scf',psr_reg+8+1+4 + symbol_maker 'cpsr_scx',psr_reg+1+2+4 + symbol_maker 'cpsr_sfc',psr_reg+8+1+4 + symbol_maker 'cpsr_sfx',psr_reg+8+2+4 + symbol_maker 'cpsr_sxc',psr_reg+1+2+4 + symbol_maker 'cpsr_sxf',psr_reg+8+2+4 + symbol_maker 'cpsr_xcf',psr_reg+8+1+2 + symbol_maker 'cpsr_xcs',psr_reg+4+1+2 + symbol_maker 'cpsr_xfc',psr_reg+8+1+2 + symbol_maker 'cpsr_xfs',psr_reg+8+4+2 + symbol_maker 'cpsr_xsc',psr_reg+4+1+2 + symbol_maker 'cpsr_xsf',psr_reg+8+4+2 + symbol_maker 'cptr_el2',sys_msr+(sys_encode_cptr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cptr_el3',sys_msr+(sys_encode_cptr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'cpu32_6m',cpu_sel+CPU32_CAPABILITY_6M + symbol_maker 'cpu32_7m',cpu_sel+CPU32_CAPABILITY_7M + symbol_maker 'cpu32_mp',cpu_sel+CPU32_CAPABILITY_MP + symbol_maker 'cpu32_t2',cpu_sel+CPU32_CAPABILITY_T2 + symbol_maker 'cpu32_v1',cpu_sel+CPU32_CAPABILITY_V1 + symbol_maker 'cpu32_v2',cpu_sel+CPU32_CAPABILITY_V2 + symbol_maker 'cpu32_v3',cpu_sel+CPU32_CAPABILITY_V3 + symbol_maker 'cpu32_v4',cpu_sel+CPU32_CAPABILITY_V4 + symbol_maker 'cpu32_v5',cpu_sel+CPU32_CAPABILITY_V5 + symbol_maker 'cpu32_v6',cpu_sel+CPU32_CAPABILITY_V6 + symbol_maker 'cpu32_v7',cpu_sel+CPU32_CAPABILITY_V7 + symbol_maker 'cpu32_v8',cpu_sel+CPU32_CAPABILITY_V8 + symbol_maker 'cpu32_ve',cpu_sel+CPU32_CAPABILITY_VE + symbol_maker 'cpu64_fp',cpu_sel+CPU64_CAPABILITY_FP + symbol_maker 'cpu64_v8',cpu_sel+CPU64_CAPABILITY_V8 + symbol_maker 'hacr_el2',sys_msr+(sys_encode_hacr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'hstr_el2',sys_msr+(sys_encode_hstr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'iflags_a',iflags+4 + symbol_maker 'iflags_f',iflags+1 + symbol_maker 'iflags_i',iflags+2 + symbol_maker 'ipas2le1',sys_tlbi+(sys_encode_ipas2le1-sys_encode_table_tlbi) shr 1 + symbol_maker 'linkinfo',19h shl 8 + 9 + symbol_maker 'mair_el1',sys_msr+(sys_encode_mair_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mair_el2',sys_msr+(sys_encode_mair_el2-sys_encode_table_msr) shr 1 + symbol_maker 'mair_el3',sys_msr+(sys_encode_mair_el3-sys_encode_table_msr) shr 1 + symbol_maker 'mdcr_el2',sys_msr+(sys_encode_mdcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'mdcr_el3',sys_msr+(sys_encode_mdcr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'midr_el1',sys_msr+(sys_encode_midr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmcr_el0',sys_msr+(sys_encode_pmcr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'readable',19h shl 8 + 30 + symbol_maker 'resource',1Ah shl 8 + 2 + symbol_maker 'spsr_abt',banked_reg+32+20 +;; symbol_maker 'spsr_abt',sys_msr+(sys_encode_spsr_abt-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_all',psr_reg+16+8+1 + symbol_maker 'spsr_cfs',psr_reg+16+8+4+1 + symbol_maker 'spsr_cfx',psr_reg+16+8+2+1 + symbol_maker 'spsr_csf',psr_reg+16+8+4+1 + symbol_maker 'spsr_csx',psr_reg+16+4+2+1 + symbol_maker 'spsr_ctl',psr_reg+16+1 + symbol_maker 'spsr_cxf',psr_reg+16+8+2+1 + symbol_maker 'spsr_cxs',psr_reg+16+4+2+1 + symbol_maker 'spsr_el1',sys_msr+(sys_encode_spsr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_el2',sys_msr+(sys_encode_spsr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_el3',sys_msr+(sys_encode_spsr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_fcs',psr_reg+16+1+4+8 + symbol_maker 'spsr_fcx',psr_reg+16+1+2+8 + symbol_maker 'spsr_fiq',banked_reg+32+14 +;; symbol_maker 'spsr_fiq',sys_msr+(sys_encode_spsr_fiq-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_flg',psr_reg+16+8 + symbol_maker 'spsr_fsc',psr_reg+16+1+4+8 + symbol_maker 'spsr_fsx',psr_reg+16+4+2+8 + symbol_maker 'spsr_fxc',psr_reg+16+1+2+8 + symbol_maker 'spsr_fxs',psr_reg+16+4+2+8 + symbol_maker 'spsr_hyp',banked_reg+32+30 + symbol_maker 'spsr_irq',banked_reg+32+16 +;; symbol_maker 'spsr_irq',sys_msr+(sys_encode_spsr_irq-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_mon',banked_reg+32+28 + symbol_maker 'spsr_scf',psr_reg+16+8+1+4 + symbol_maker 'spsr_scx',psr_reg+16+1+2+4 + symbol_maker 'spsr_sfc',psr_reg+16+8+1+4 + symbol_maker 'spsr_sfx',psr_reg+16+8+2+4 + symbol_maker 'spsr_svc',banked_reg+32+18 + symbol_maker 'spsr_sxc',psr_reg+16+1+2+4 + symbol_maker 'spsr_sxf',psr_reg+16+8+2+4 + symbol_maker 'spsr_und',banked_reg+32+22 +;; symbol_maker 'spsr_und',sys_msr+(sys_encode_spsr_und-sys_encode_table_msr) shr 1 + symbol_maker 'spsr_xcf',psr_reg+16+8+1+2 + symbol_maker 'spsr_xcs',psr_reg+16+4+1+2 + symbol_maker 'spsr_xfc',psr_reg+16+8+1+2 + symbol_maker 'spsr_xfs',psr_reg+16+8+4+2 + symbol_maker 'spsr_xsc',psr_reg+16+4+1+2 + symbol_maker 'spsr_xsf',psr_reg+16+8+4+2 + symbol_maker 'vaale1is',sys_tlbi+(sys_encode_vaale1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vbar_el1',sys_msr+(sys_encode_vbar_el1-sys_encode_table_msr) shr 1 + symbol_maker 'vbar_el2',sys_msr+(sys_encode_vbar_el2-sys_encode_table_msr) shr 1 + symbol_maker 'vbar_el3',sys_msr+(sys_encode_vbar_el3-sys_encode_table_msr) shr 1 + symbol_maker 'vtcr_el2',sys_msr+(sys_encode_vtcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'writable',19h shl 8 + 31 +symbols_9: + symbol_maker 'actlr_el1',sys_msr+(sys_encode_actlr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'actlr_el2',sys_msr+(sys_encode_actlr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'actlr_el3',sys_msr+(sys_encode_actlr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'afsr0_el1',sys_msr+(sys_encode_afsr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'afsr0_el2',sys_msr+(sys_encode_afsr0_el2-sys_encode_table_msr) shr 1 + symbol_maker 'afsr0_el3',sys_msr+(sys_encode_afsr0_el3-sys_encode_table_msr) shr 1 + symbol_maker 'afsr1_el1',sys_msr+(sys_encode_afsr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'afsr1_el2',sys_msr+(sys_encode_afsr1_el2-sys_encode_table_msr) shr 1 + symbol_maker 'afsr1_el3',sys_msr+(sys_encode_afsr1_el3-sys_encode_table_msr) shr 1 + symbol_maker 'amair_el1',sys_msr+(sys_encode_amair_el1-sys_encode_table_msr) shr 1 + symbol_maker 'amair_el2',sys_msr+(sys_encode_amair_el2-sys_encode_table_msr) shr 1 + symbol_maker 'amair_el3',sys_msr+(sys_encode_amair_el3-sys_encode_table_msr) shr 1 + symbol_maker 'apsr_nzcv',psr_reg+34 + symbol_maker 'clidr_el1',sys_msr+(sys_encode_clidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'copro_all',copro_sel.all + symbol_maker 'cpacr_el1',sys_msr+(sys_encode_cpacr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'cpsr_cfsx',psr_reg+8+4+2+1 + symbol_maker 'cpsr_cfxs',psr_reg+8+4+2+1 + symbol_maker 'cpsr_csfx',psr_reg+8+4+2+1 + symbol_maker 'cpsr_csxf',psr_reg+8+4+2+1 + symbol_maker 'cpsr_cxfs',psr_reg+8+4+2+1 + symbol_maker 'cpsr_cxsf',psr_reg+8+4+2+1 + symbol_maker 'cpsr_fcsx',psr_reg+1+4+2+8 + symbol_maker 'cpsr_fcxs',psr_reg+1+4+2+8 + symbol_maker 'cpsr_fscx',psr_reg+1+4+2+8 + symbol_maker 'cpsr_fsxc',psr_reg+1+4+2+8 + symbol_maker 'cpsr_fxcs',psr_reg+1+4+2+8 + symbol_maker 'cpsr_fxsc',psr_reg+1+4+2+8 + symbol_maker 'cpsr_scfx',psr_reg+8+1+2+4 + symbol_maker 'cpsr_scxf',psr_reg+8+1+2+4 + symbol_maker 'cpsr_sfcx',psr_reg+8+1+2+4 + symbol_maker 'cpsr_sfxc',psr_reg+8+1+2+4 + symbol_maker 'cpsr_sxcf',psr_reg+8+1+2+4 + symbol_maker 'cpsr_sxfc',psr_reg+8+1+2+4 + symbol_maker 'cpsr_xcfs',psr_reg+8+4+1+2 + symbol_maker 'cpsr_xcsf',psr_reg+8+4+1+2 + symbol_maker 'cpsr_xfcs',psr_reg+8+4+1+2 + symbol_maker 'cpsr_xfsc',psr_reg+8+4+1+2 + symbol_maker 'cpsr_xscf',psr_reg+8+4+1+2 + symbol_maker 'cpsr_xsfc',psr_reg+8+4+1+2 + symbol_maker 'cpu32_all',cpu_sel.all32 + symbol_maker 'cpu32_crc',cpu_sel+CPU32_CAPABILITY_CRC + symbol_maker 'cpu32_div',cpu_sel+CPU32_CAPABILITY_DIV + symbol_maker 'cpu32_v4t',cpu_sel+CPU32_CAPABILITY_V4T + symbol_maker 'cpu32_v5t',cpu_sel+CPU32_CAPABILITY_V5T + symbol_maker 'cpu32_v6t',cpu_sel+CPU32_CAPABILITY_V6T + symbol_maker 'cpu64_all',cpu_sel.all64 + symbol_maker 'cpu64_crc',cpu_sel+CPU64_CAPABILITY_CRC + symbol_maker 'currentel',sys_msr+(sys_encode_currentel-sys_encode_table_msr) shr 1 + symbol_maker 'dczid_el0',sys_msr+(sys_encode_dczid_el0-sys_encode_table_msr) shr 1 + symbol_maker 'dspsr_el0',sys_msr+(sys_encode_dspsr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'faultmask',sysm_reg+19 + symbol_maker 'hpfar_el2',sys_msr+(sys_encode_hpfar_el2-sys_encode_table_msr) shr 1 + symbol_maker 'iflags_af',iflags+4+1 + symbol_maker 'iflags_ai',iflags+4+2 + symbol_maker 'iflags_fa',iflags+1+4 + symbol_maker 'iflags_fi',iflags+1+2 + symbol_maker 'iflags_ia',iflags+2+4 + symbol_maker 'iflags_if',iflags+2+1 + symbol_maker 'ipas2e1is',sys_tlbi+(sys_encode_ipas2e1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'mdrar_el1',sys_msr+(sys_encode_mdrar_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mdscr_el1',sys_msr+(sys_encode_mdscr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mpidr_el1',sys_msr+(sys_encode_mpidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mvfr0_el1',sys_msr+(sys_encode_mvfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mvfr1_el1',sys_msr+(sys_encode_mvfr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'mvfr2_el1',sys_msr+(sys_encode_mvfr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'osdlr_el1',sys_msr+(sys_encode_osdlr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'oslar_el1',sys_msr+(sys_encode_oslar_el1-sys_encode_table_msr) shr 1 + symbol_maker 'oslsr_el1',sys_msr+(sys_encode_oslsr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pldl1keep',prf_op+0*8+0*2+0 + symbol_maker 'pldl1strm',prf_op+0*8+0*2+1 + symbol_maker 'pldl2keep',prf_op+0*8+1*2+0 + symbol_maker 'pldl2strm',prf_op+0*8+1*2+1 + symbol_maker 'pldl3keep',prf_op+0*8+2*2+0 + symbol_maker 'pldl3strm',prf_op+0*8+2*2+1 + symbol_maker 'plil1keep',prf_op+1*8+0*2+0 + symbol_maker 'plil1strm',prf_op+1*8+0*2+1 + symbol_maker 'plil2keep',prf_op+1*8+1*2+0 + symbol_maker 'plil2strm',prf_op+1*8+1*2+1 + symbol_maker 'plil3keep',prf_op+1*8+2*2+0 + symbol_maker 'plil3strm',prf_op+1*8+2*2+1 + symbol_maker 'pstl1keep',prf_op+2*8+0*2+0 + symbol_maker 'pstl1strm',prf_op+2*8+0*2+1 + symbol_maker 'pstl2keep',prf_op+2*8+1*2+0 + symbol_maker 'pstl2strm',prf_op+2*8+1*2+1 + symbol_maker 'pstl3keep',prf_op+2*8+2*2+0 + symbol_maker 'pstl3strm',prf_op+2*8+2*2+1 + symbol_maker 'rvbar_el1',sys_msr+(sys_encode_rvbar_el1-sys_encode_table_msr) shr 1 + symbol_maker 'rvbar_el2',sys_msr+(sys_encode_rvbar_el2-sys_encode_table_msr) shr 1 + symbol_maker 'rvbar_el3',sys_msr+(sys_encode_rvbar_el3-sys_encode_table_msr) shr 1 + symbol_maker 'sctlr_el1',sys_msr+(sys_encode_sctlr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'sctlr_el2',sys_msr+(sys_encode_sctlr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'sctlr_el3',sys_msr+(sys_encode_sctlr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'shareable',19h shl 8 + 28 + symbol_maker 'spsr_cfsx',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_cfxs',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_csfx',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_csxf',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_cxfs',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_cxsf',psr_reg+16+8+4+2+1 + symbol_maker 'spsr_fcsx',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_fcxs',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_fscx',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_fsxc',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_fxcs',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_fxsc',psr_reg+16+1+4+2+8 + symbol_maker 'spsr_scfx',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_scxf',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_sfcx',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_sfxc',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_sxcf',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_sxfc',psr_reg+16+8+1+2+4 + symbol_maker 'spsr_xcfs',psr_reg+16+8+4+1+2 + symbol_maker 'spsr_xcsf',psr_reg+16+8+4+1+2 + symbol_maker 'spsr_xfcs',psr_reg+16+8+4+1+2 + symbol_maker 'spsr_xfsc',psr_reg+16+8+4+1+2 + symbol_maker 'spsr_xscf',psr_reg+16+8+4+1+2 + symbol_maker 'spsr_xsfc',psr_reg+16+8+4+1+2 + symbol_maker 'tpidr_el0',sys_msr+(sys_encode_tpidr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'tpidr_el1',sys_msr+(sys_encode_tpidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'tpidr_el2',sys_msr+(sys_encode_tpidr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'tpidr_el3',sys_msr+(sys_encode_tpidr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'ttbr0_el1',sys_msr+(sys_encode_ttbr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'ttbr0_el2',sys_msr+(sys_encode_ttbr0_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ttbr0_el3',sys_msr+(sys_encode_ttbr0_el3-sys_encode_table_msr) shr 1 + symbol_maker 'ttbr1_el1',sys_msr+(sys_encode_ttbr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'vmalle1is',sys_tlbi+(sys_encode_vmalle1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'vpidr_el2',sys_msr+(sys_encode_vpidr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'vttbr_el2',sys_msr+(sys_encode_vttbr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'writeable',19h shl 8 + 31 +symbols_10: + symbol_maker 'apsr_nzcvq',psr_reg+8 + symbol_maker 'ccsidr_el1',sys_msr+(sys_encode_ccsidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'cntfrq_el0',sys_msr+(sys_encode_cntfrq_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntpct_el0',sys_msr+(sys_encode_cntpct_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntvct_el0',sys_msr+(sys_encode_cntvct_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cpu32_sync',cpu_sel+CPU32_CAPABILITY_SYNC + symbol_maker 'cpu32_t2ee',cpu_sel+CPU32_CAPABILITY_T2EE + symbol_maker 'cpu64_simd',cpu_sel+CPU64_CAPABILITY_SIMD + symbol_maker 'csselr_el1',sys_msr+(sys_encode_csselr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dacr32_el2',sys_msr+(sys_encode_dacr32_el2-sys_encode_table_msr) shr 1 + symbol_maker 'dbgdtr_el0',sys_msr+(sys_encode_dbgdtr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'efiruntime',1Bh shl 8 + 12 + symbol_maker 'executable',19h shl 8 + 29 + symbol_maker 'iflags_afi',iflags+4+1+2 + symbol_maker 'iflags_aif',iflags+4+2+1 + symbol_maker 'iflags_fai',iflags+1+4+2 + symbol_maker 'iflags_fia',iflags+1+2+4 + symbol_maker 'iflags_iaf',iflags+2+4+1 + symbol_maker 'iflags_ifa',iflags+2+1+4 + symbol_maker 'ifsr32_el2',sys_msr+(sys_encode_ifsr32_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ipas2le1is',sys_tlbi+(sys_encode_ipas2le1is-sys_encode_table_tlbi) shr 1 + symbol_maker 'linkremove',19h shl 8 + 11 + symbol_maker 'mdccsr_el0',sys_msr+(sys_encode_mdccsr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'oseccr_el1',sys_msr+(sys_encode_oseccr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmselr_el0',sys_msr+(sys_encode_pmselr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'revidr_el1',sys_msr+(sys_encode_revidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'sder32_el3',sys_msr+(sys_encode_sder32_el3-sys_encode_table_msr) shr 1 + symbol_maker 'vmalls12e1',sys_tlbi+(sys_encode_vmalls12e1-sys_encode_table_tlbi) shr 1 + symbol_maker 'vmpidr_el2',sys_msr+(sys_encode_vmpidr_el2-sys_encode_table_msr) shr 1 +symbols_11: + symbol_maker 'apsr_nzcvqg',psr_reg+8+4 + symbol_maker 'basepri_max',sysm_reg+18 + symbol_maker 'cnthctl_el2',sys_msr+(sys_encode_cnthctl_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cntkctl_el1',sys_msr+(sys_encode_cntkctl_el1-sys_encode_table_msr) shr 1 + symbol_maker 'cntvoff_el2',sys_msr+(sys_encode_cntvoff_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cpu32_26bit',cpu_sel+CPU32_CAPABILITY_26BIT + symbol_maker 'cpu32_align',cpu_sel+CPU32_CAPABILITY_ALIGN + symbol_maker 'dbgbcr0_el1',sys_msr+(sys_encode_dbgbcr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr1_el1',sys_msr+(sys_encode_dbgbcr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr2_el1',sys_msr+(sys_encode_dbgbcr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr3_el1',sys_msr+(sys_encode_dbgbcr3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr4_el1',sys_msr+(sys_encode_dbgbcr4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr5_el1',sys_msr+(sys_encode_dbgbcr5_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr6_el1',sys_msr+(sys_encode_dbgbcr6_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr7_el1',sys_msr+(sys_encode_dbgbcr7_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr8_el1',sys_msr+(sys_encode_dbgbcr8_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr9_el1',sys_msr+(sys_encode_dbgbcr9_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr0_el1',sys_msr+(sys_encode_dbgbvr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr1_el1',sys_msr+(sys_encode_dbgbvr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr2_el1',sys_msr+(sys_encode_dbgbvr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr3_el1',sys_msr+(sys_encode_dbgbvr3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr4_el1',sys_msr+(sys_encode_dbgbvr4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr5_el1',sys_msr+(sys_encode_dbgbvr5_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr6_el1',sys_msr+(sys_encode_dbgbvr6_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr7_el1',sys_msr+(sys_encode_dbgbvr7_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr8_el1',sys_msr+(sys_encode_dbgbvr8_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr9_el1',sys_msr+(sys_encode_dbgbvr9_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgprcr_el1',sys_msr+(sys_encode_dbgprcr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr0_el1',sys_msr+(sys_encode_dbgwcr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr1_el1',sys_msr+(sys_encode_dbgwcr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr2_el1',sys_msr+(sys_encode_dbgwcr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr3_el1',sys_msr+(sys_encode_dbgwcr3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr4_el1',sys_msr+(sys_encode_dbgwcr4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr5_el1',sys_msr+(sys_encode_dbgwcr5_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr6_el1',sys_msr+(sys_encode_dbgwcr6_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr7_el1',sys_msr+(sys_encode_dbgwcr7_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr8_el1',sys_msr+(sys_encode_dbgwcr8_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr9_el1',sys_msr+(sys_encode_dbgwcr9_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr0_el1',sys_msr+(sys_encode_dbgwvr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr1_el1',sys_msr+(sys_encode_dbgwvr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr2_el1',sys_msr+(sys_encode_dbgwvr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr3_el1',sys_msr+(sys_encode_dbgwvr3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr4_el1',sys_msr+(sys_encode_dbgwvr4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr5_el1',sys_msr+(sys_encode_dbgwvr5_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr6_el1',sys_msr+(sys_encode_dbgwvr6_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr7_el1',sys_msr+(sys_encode_dbgwvr7_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr8_el1',sys_msr+(sys_encode_dbgwvr8_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr9_el1',sys_msr+(sys_encode_dbgwvr9_el1-sys_encode_table_msr) shr 1 + symbol_maker 'discardable',19h shl 8 + 25 + symbol_maker 'fpexc32_el2',sys_msr+(sys_encode_fpexc32_el2-sys_encode_table_msr) shr 1 + symbol_maker 'icc_dir_el1',sys_msr+(sys_encode_icc_dir_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_pmr_el1',sys_msr+(sys_encode_icc_pmr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_rpr_el1',sys_msr+(sys_encode_icc_rpr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_sre_el1',sys_msr+(sys_encode_icc_sre_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_sre_el2',sys_msr+(sys_encode_icc_sre_el2-sys_encode_table_msr) shr 1 + symbol_maker 'icc_sre_el3',sys_msr+(sys_encode_icc_sre_el3-sys_encode_table_msr) shr 1 + symbol_maker 'ich_hcr_el2',sys_msr+(sys_encode_ich_hcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr0_el2',sys_msr+(sys_encode_ich_lr0_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr1_el2',sys_msr+(sys_encode_ich_lr1_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr2_el2',sys_msr+(sys_encode_ich_lr2_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr3_el2',sys_msr+(sys_encode_ich_lr3_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr4_el2',sys_msr+(sys_encode_ich_lr4_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr5_el2',sys_msr+(sys_encode_ich_lr5_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr6_el2',sys_msr+(sys_encode_ich_lr6_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr7_el2',sys_msr+(sys_encode_ich_lr7_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr8_el2',sys_msr+(sys_encode_ich_lr8_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr9_el2',sys_msr+(sys_encode_ich_lr9_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_vtr_el2',sys_msr+(sys_encode_ich_vtr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'icv_dir_el1',sys_msr+(sys_encode_icv_dir_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_pmr_el1',sys_msr+(sys_encode_icv_pmr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_rpr_el1',sys_msr+(sys_encode_icv_rpr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_afr0_el1',sys_msr+(sys_encode_id_afr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_dfr0_el1',sys_msr+(sys_encode_id_dfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_pfr0_el1',sys_msr+(sys_encode_id_pfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_pfr1_el1',sys_msr+(sys_encode_id_pfr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'interpreter',1Eh shl 8 + 3 + symbol_maker 'mdccint_el1',sys_msr+(sys_encode_mdccint_el1-sys_encode_table_msr) shr 1 + symbol_maker 'notpageable',19h shl 8 + 27 + symbol_maker 'osdtrrx_el1',sys_msr+(sys_encode_osdtrrx_el1-sys_encode_table_msr) shr 1 + symbol_maker 'osdtrtx_el1',sys_msr+(sys_encode_osdtrtx_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmccntr_el0',sys_msr+(sys_encode_pmccntr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmceid0_el0',sys_msr+(sys_encode_pmceid0_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmceid1_el0',sys_msr+(sys_encode_pmceid1_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmswinc_el0',sys_msr+(sys_encode_pmswinc_el0-sys_encode_table_msr) shr 1 + symbol_maker 'tpidrro_el0',sys_msr+(sys_encode_tpidrro_el0-sys_encode_table_msr) shr 1 +symbols_12: + symbol_maker 'cntp_ctl_el0',sys_msr+(sys_encode_cntp_ctl_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntv_ctl_el0',sys_msr+(sys_encode_cntv_ctl_el0-sys_encode_table_msr) shr 1 + symbol_maker 'copro_fpa_v1',copro_sel+COPRO_CAPABILITY_FPA_V1 + symbol_maker 'copro_fpa_v2',copro_sel+COPRO_CAPABILITY_FPA_V2 + symbol_maker 'copro_vfp_hp',copro_sel+COPRO_CAPABILITY_VFP_HP + symbol_maker 'copro_vfp_v1',copro_sel+COPRO_CAPABILITY_VFP_V1 + symbol_maker 'copro_vfp_v2',copro_sel+COPRO_CAPABILITY_VFP_V2 + symbol_maker 'copro_vfp_v3',copro_sel+COPRO_CAPABILITY_VFP_V3 + symbol_maker 'copro_vfp_v4',copro_sel+COPRO_CAPABILITY_VFP_V4 + symbol_maker 'copro_xscale',copro_sel+COPRO_CAPABILITY_XSCALE + symbol_maker 'cpu64_crypto',cpu_sel+CPU64_CAPABILITY_CRYPTO + symbol_maker 'dbgbcr10_el1',sys_msr+(sys_encode_dbgbcr10_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr11_el1',sys_msr+(sys_encode_dbgbcr11_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr12_el1',sys_msr+(sys_encode_dbgbcr12_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr13_el1',sys_msr+(sys_encode_dbgbcr13_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr14_el1',sys_msr+(sys_encode_dbgbcr14_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbcr15_el1',sys_msr+(sys_encode_dbgbcr15_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr10_el1',sys_msr+(sys_encode_dbgbvr10_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr11_el1',sys_msr+(sys_encode_dbgbvr11_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr12_el1',sys_msr+(sys_encode_dbgbvr12_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr13_el1',sys_msr+(sys_encode_dbgbvr13_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr14_el1',sys_msr+(sys_encode_dbgbvr14_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgbvr15_el1',sys_msr+(sys_encode_dbgbvr15_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgdtrrx_el0',sys_msr+(sys_encode_dbgdtrrx_el0-sys_encode_table_msr) shr 1 + symbol_maker 'dbgdtrtx_el0',sys_msr+(sys_encode_dbgdtrtx_el0-sys_encode_table_msr) shr 1 + symbol_maker 'dbgvcr32_el2',sys_msr+(sys_encode_dbgvcr32_el2-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr10_el1',sys_msr+(sys_encode_dbgwcr10_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr11_el1',sys_msr+(sys_encode_dbgwcr11_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr12_el1',sys_msr+(sys_encode_dbgwcr12_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr13_el1',sys_msr+(sys_encode_dbgwcr13_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr14_el1',sys_msr+(sys_encode_dbgwcr14_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwcr15_el1',sys_msr+(sys_encode_dbgwcr15_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr10_el1',sys_msr+(sys_encode_dbgwvr10_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr11_el1',sys_msr+(sys_encode_dbgwvr11_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr12_el1',sys_msr+(sys_encode_dbgwvr12_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr13_el1',sys_msr+(sys_encode_dbgwvr13_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr14_el1',sys_msr+(sys_encode_dbgwvr14_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgwvr15_el1',sys_msr+(sys_encode_dbgwvr15_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_bpr0_el1',sys_msr+(sys_encode_icc_bpr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_bpr1_el1',sys_msr+(sys_encode_icc_bpr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ctlr_el1',sys_msr+(sys_encode_icc_ctlr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ctlr_el3',sys_msr+(sys_encode_icc_ctlr_el3-sys_encode_table_msr) shr 1 + symbol_maker 'icc_iar0_el1',sys_msr+(sys_encode_icc_iar0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_iar1_el1',sys_msr+(sys_encode_icc_iar1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'ich_eisr_el2',sys_msr+(sys_encode_ich_eisr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr10_el2',sys_msr+(sys_encode_ich_lr10_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr11_el2',sys_msr+(sys_encode_ich_lr11_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr12_el2',sys_msr+(sys_encode_ich_lr12_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr13_el2',sys_msr+(sys_encode_ich_lr13_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr14_el2',sys_msr+(sys_encode_ich_lr14_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_lr15_el2',sys_msr+(sys_encode_ich_lr15_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_misr_el2',sys_msr+(sys_encode_ich_misr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_vmcr_el2',sys_msr+(sys_encode_ich_vmcr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'icv_bpr0_el1',sys_msr+(sys_encode_icv_bpr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_bpr1_el1',sys_msr+(sys_encode_icv_bpr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ctlr_el1',sys_msr+(sys_encode_icv_ctlr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_iar0_el1',sys_msr+(sys_encode_icv_iar0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_iar1_el1',sys_msr+(sys_encode_icv_iar1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar0_el1',sys_msr+(sys_encode_id_isar0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar1_el1',sys_msr+(sys_encode_id_isar1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar2_el1',sys_msr+(sys_encode_id_isar2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar3_el1',sys_msr+(sys_encode_id_isar3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar4_el1',sys_msr+(sys_encode_id_isar4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_isar5_el1',sys_msr+(sys_encode_id_isar5_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_mmfr0_el1',sys_msr+(sys_encode_id_mmfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_mmfr1_el1',sys_msr+(sys_encode_id_mmfr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_mmfr2_el1',sys_msr+(sys_encode_id_mmfr2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_mmfr3_el1',sys_msr+(sys_encode_id_mmfr3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_mmfr4_el1',sys_msr+(sys_encode_id_mmfr4_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmovsclr_el0',sys_msr+(sys_encode_pmovsclr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmovsset_el0',sys_msr+(sys_encode_pmovsset_el0-sys_encode_table_msr) shr 1 + symbol_maker 'vmalls12e1is',sys_tlbi+(sys_encode_vmalls12e1is-sys_encode_table_tlbi) shr 1 +symbols_13: + symbol_maker 'cnthp_ctl_el2',sys_msr+(sys_encode_cnthp_ctl_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cntp_cval_el0',sys_msr+(sys_encode_cntp_cval_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntp_tval_el0',sys_msr+(sys_encode_cntp_tval_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntps_ctl_el1',sys_msr+(sys_encode_cntps_ctl_el1-sys_encode_table_msr) shr 1 + symbol_maker 'cntv_cval_el0',sys_msr+(sys_encode_cntv_cval_el0-sys_encode_table_msr) shr 1 + symbol_maker 'cntv_tval_el0',sys_msr+(sys_encode_cntv_tval_el0-sys_encode_table_msr) shr 1 + symbol_maker 'copro_simd_hp',copro_sel+COPRO_CAPABILITY_SIMD_HP + symbol_maker 'copro_simd_v2',copro_sel+COPRO_CAPABILITY_SIMD_V2 + symbol_maker 'copro_simd_v8',copro_sel+COPRO_CAPABILITY_SIMD_V8 + symbol_maker 'copro_vfp_d32',copro_sel+COPRO_CAPABILITY_VFP_D32 + symbol_maker 'icc_ap0r0_el1',sys_msr+(sys_encode_icc_ap0r0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap0r1_el1',sys_msr+(sys_encode_icc_ap0r1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap0r2_el1',sys_msr+(sys_encode_icc_ap0r2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap0r3_el1',sys_msr+(sys_encode_icc_ap0r3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap1r0_el1',sys_msr+(sys_encode_icc_ap1r0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap1r1_el1',sys_msr+(sys_encode_icc_ap1r1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap1r2_el1',sys_msr+(sys_encode_icc_ap1r2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_ap1r3_el1',sys_msr+(sys_encode_icc_ap1r3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_eoir0_el1',sys_msr+(sys_encode_icc_eoir0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_eoir1_el1',sys_msr+(sys_encode_icc_eoir1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_sgi0r_el1',sys_msr+(sys_encode_icc_sgi0r_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_sgi1r_el1',sys_msr+(sys_encode_icc_sgi1r_el1-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap0r0_el2',sys_msr+(sys_encode_ich_ap0r0_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap0r1_el2',sys_msr+(sys_encode_ich_ap0r1_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap0r2_el2',sys_msr+(sys_encode_ich_ap0r2_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap0r3_el2',sys_msr+(sys_encode_ich_ap0r3_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap1r0_el2',sys_msr+(sys_encode_ich_ap1r0_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap1r1_el2',sys_msr+(sys_encode_ich_ap1r1_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap1r2_el2',sys_msr+(sys_encode_ich_ap1r2_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_ap1r3_el2',sys_msr+(sys_encode_ich_ap1r3_el2-sys_encode_table_msr) shr 1 + symbol_maker 'ich_elrsr_el2',sys_msr+(sys_encode_ich_elrsr_el2-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap0r0_el1',sys_msr+(sys_encode_icv_ap0r0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap0r1_el1',sys_msr+(sys_encode_icv_ap0r1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap0r2_el1',sys_msr+(sys_encode_icv_ap0r2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap0r3_el1',sys_msr+(sys_encode_icv_ap0r3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap1r0_el1',sys_msr+(sys_encode_icv_ap1r0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap1r1_el1',sys_msr+(sys_encode_icv_ap1r1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap1r2_el1',sys_msr+(sys_encode_icv_ap1r2_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_ap1r3_el1',sys_msr+(sys_encode_icv_ap1r3_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_eoir0_el1',sys_msr+(sys_encode_icv_eoir0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_eoir1_el1',sys_msr+(sys_encode_icv_eoir1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmccfiltr_el0',sys_msr+(sys_encode_pmccfiltr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr0_el0',sys_msr+(sys_encode_pmevcntr0_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr1_el0',sys_msr+(sys_encode_pmevcntr1_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr2_el0',sys_msr+(sys_encode_pmevcntr2_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr3_el0',sys_msr+(sys_encode_pmevcntr3_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr4_el0',sys_msr+(sys_encode_pmevcntr4_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr5_el0',sys_msr+(sys_encode_pmevcntr5_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr6_el0',sys_msr+(sys_encode_pmevcntr6_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr7_el0',sys_msr+(sys_encode_pmevcntr7_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr8_el0',sys_msr+(sys_encode_pmevcntr8_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr9_el0',sys_msr+(sys_encode_pmevcntr9_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmuserenr_el0',sys_msr+(sys_encode_pmuserenr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmxevcntr_el0',sys_msr+(sys_encode_pmxevcntr_el0-sys_encode_table_msr) shr 1 +symbols_14: + symbol_maker 'cnthp_cval_el2',sys_msr+(sys_encode_cnthp_cval_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cnthp_tval_el2',sys_msr+(sys_encode_cnthp_tval_el2-sys_encode_table_msr) shr 1 + symbol_maker 'cntps_cval_el1',sys_msr+(sys_encode_cntps_cval_el1-sys_encode_table_msr) shr 1 + symbol_maker 'cntps_tval_el1',sys_msr+(sys_encode_cntps_tval_el1-sys_encode_table_msr) shr 1 + symbol_maker 'contextidr_el1',sys_msr+(sys_encode_contextidr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'copro_maverick',copro_sel+COPRO_CAPABILITY_MAVERICK + symbol_maker 'copro_simd_int',copro_sel+COPRO_CAPABILITY_SIMD_INT + symbol_maker 'copro_vfp_v1xd',copro_sel+COPRO_CAPABILITY_VFP_V1xD + symbol_maker 'icc_asgi1r_el1',sys_msr+(sys_encode_icc_asgi1r_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_hppir0_el1',sys_msr+(sys_encode_icc_hppir0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_hppir1_el1',sys_msr+(sys_encode_icc_hppir1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_hppir0_el1',sys_msr+(sys_encode_icv_hppir0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_hppir1_el1',sys_msr+(sys_encode_icv_hppir1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmcntenclr_el0',sys_msr+(sys_encode_pmcntenclr_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmcntenset_el0',sys_msr+(sys_encode_pmcntenset_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr10_el0',sys_msr+(sys_encode_pmevcntr10_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr11_el0',sys_msr+(sys_encode_pmevcntr11_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr12_el0',sys_msr+(sys_encode_pmevcntr12_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr13_el0',sys_msr+(sys_encode_pmevcntr13_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr14_el0',sys_msr+(sys_encode_pmevcntr14_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr15_el0',sys_msr+(sys_encode_pmevcntr15_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr16_el0',sys_msr+(sys_encode_pmevcntr16_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr17_el0',sys_msr+(sys_encode_pmevcntr17_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr18_el0',sys_msr+(sys_encode_pmevcntr18_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr19_el0',sys_msr+(sys_encode_pmevcntr19_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr20_el0',sys_msr+(sys_encode_pmevcntr20_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr21_el0',sys_msr+(sys_encode_pmevcntr21_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr22_el0',sys_msr+(sys_encode_pmevcntr22_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr23_el0',sys_msr+(sys_encode_pmevcntr23_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr24_el0',sys_msr+(sys_encode_pmevcntr24_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr25_el0',sys_msr+(sys_encode_pmevcntr25_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr26_el0',sys_msr+(sys_encode_pmevcntr26_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr27_el0',sys_msr+(sys_encode_pmevcntr27_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr28_el0',sys_msr+(sys_encode_pmevcntr28_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr29_el0',sys_msr+(sys_encode_pmevcntr29_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevcntr30_el0',sys_msr+(sys_encode_pmevcntr30_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper0_el0',sys_msr+(sys_encode_pmevtyper0_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper1_el0',sys_msr+(sys_encode_pmevtyper1_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper2_el0',sys_msr+(sys_encode_pmevtyper2_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper3_el0',sys_msr+(sys_encode_pmevtyper3_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper4_el0',sys_msr+(sys_encode_pmevtyper4_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper5_el0',sys_msr+(sys_encode_pmevtyper5_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper6_el0',sys_msr+(sys_encode_pmevtyper6_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper7_el0',sys_msr+(sys_encode_pmevtyper7_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper8_el0',sys_msr+(sys_encode_pmevtyper8_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper9_el0',sys_msr+(sys_encode_pmevtyper9_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmintenclr_el1',sys_msr+(sys_encode_pmintenclr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmintenset_el1',sys_msr+(sys_encode_pmintenset_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmxevtyper_el0',sys_msr+(sys_encode_pmxevtyper_el0-sys_encode_table_msr) shr 1 +symbols_15: + symbol_maker 'copro_iwmmxt_v1',copro_sel+COPRO_CAPABILITY_IWMMXT_V1 + symbol_maker 'copro_iwmmxt_v2',copro_sel+COPRO_CAPABILITY_IWMMXT_V2 + symbol_maker 'dbgclaimclr_el1',sys_msr+(sys_encode_dbgclaimclr_el1-sys_encode_table_msr) shr 1 + symbol_maker 'dbgclaimset_el1',sys_msr+(sys_encode_dbgclaimset_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_igrpen0_el1',sys_msr+(sys_encode_icc_igrpen0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_igrpen1_el1',sys_msr+(sys_encode_icc_igrpen1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icc_igrpen1_el3',sys_msr+(sys_encode_icc_igrpen1_el3-sys_encode_table_msr) shr 1 + symbol_maker 'icv_igrpen0_el1',sys_msr+(sys_encode_icv_igrpen0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'icv_igrpen1_el1',sys_msr+(sys_encode_icv_igrpen1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64afr0_el1',sys_msr+(sys_encode_id_aa64afr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64afr1_el1',sys_msr+(sys_encode_id_aa64afr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64dfr0_el1',sys_msr+(sys_encode_id_aa64dfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64dfr1_el1',sys_msr+(sys_encode_id_aa64dfr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64pfr0_el1',sys_msr+(sys_encode_id_aa64pfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64pfr1_el1',sys_msr+(sys_encode_id_aa64pfr1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper10_el0',sys_msr+(sys_encode_pmevtyper10_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper11_el0',sys_msr+(sys_encode_pmevtyper11_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper12_el0',sys_msr+(sys_encode_pmevtyper12_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper13_el0',sys_msr+(sys_encode_pmevtyper13_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper14_el0',sys_msr+(sys_encode_pmevtyper14_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper15_el0',sys_msr+(sys_encode_pmevtyper15_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper16_el0',sys_msr+(sys_encode_pmevtyper16_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper17_el0',sys_msr+(sys_encode_pmevtyper17_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper18_el0',sys_msr+(sys_encode_pmevtyper18_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper19_el0',sys_msr+(sys_encode_pmevtyper19_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper20_el0',sys_msr+(sys_encode_pmevtyper20_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper21_el0',sys_msr+(sys_encode_pmevtyper21_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper22_el0',sys_msr+(sys_encode_pmevtyper22_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper23_el0',sys_msr+(sys_encode_pmevtyper23_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper24_el0',sys_msr+(sys_encode_pmevtyper24_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper25_el0',sys_msr+(sys_encode_pmevtyper25_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper26_el0',sys_msr+(sys_encode_pmevtyper26_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper27_el0',sys_msr+(sys_encode_pmevtyper27_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper28_el0',sys_msr+(sys_encode_pmevtyper28_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper29_el0',sys_msr+(sys_encode_pmevtyper29_el0-sys_encode_table_msr) shr 1 + symbol_maker 'pmevtyper30_el0',sys_msr+(sys_encode_pmevtyper30_el0-sys_encode_table_msr) shr 1 +symbols_16: + symbol_maker 'copro_simd_float',copro_sel+COPRO_CAPABILITY_SIMD_FLOAT + symbol_maker 'id_aa64isar0_el1',sys_msr+(sys_encode_id_aa64isar0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64isar1_el1',sys_msr+(sys_encode_id_aa64isar1_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64mmfr0_el1',sys_msr+(sys_encode_id_aa64mmfr0_el1-sys_encode_table_msr) shr 1 + symbol_maker 'id_aa64mmfr1_el1',sys_msr+(sys_encode_id_aa64mmfr1_el1-sys_encode_table_msr) shr 1 +symbols_17: + symbol_maker 'copro_simd_crypto',copro_sel+COPRO_CAPABILITY_SIMD_CRYPTO + symbol_maker 'dbgauthstatus_el1',sys_msr+(sys_encode_dbgauthstatus_el1-sys_encode_table_msr) shr 1 +symbols_end: + +purge symbol_maker + + align 2 +sys_encode_table_at: + ;at op0 op1 crn crm op2 + sys_encode_s12e0r: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0110b + sys_encode_s12e0w: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0111b + sys_encode_s12e1r: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0100b + sys_encode_s12e1w: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0101b + sys_encode_s1e0r: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0010b + sys_encode_s1e0w: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0011b + sys_encode_s1e1r: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b + sys_encode_s1e1w: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b + sys_encode_s1e2r: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b + sys_encode_s1e2w: dw 001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b + sys_encode_s1e3r: dw 001b shl 14 + 0110b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b + sys_encode_s1e3w: dw 001b shl 14 + 0110b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b +sys_encode_table_dc: + ;dc op0 op1 crn crm op2 + sys_encode_cisw: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01110b shl 3 + 0010b + sys_encode_civac: dw 001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01110b shl 3 + 0001b + sys_encode_csw: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01010b shl 3 + 0010b + sys_encode_cvac: dw 001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01010b shl 3 + 0001b + sys_encode_cvau: dw 001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01011b shl 3 + 0001b + sys_encode_isw: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00110b shl 3 + 0010b + sys_encode_ivac: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00110b shl 3 + 0001b + sys_encode_zva: dw 001b shl 14 + 0011b shl 11 + 00111b shl 7 + 00100b shl 3 + 0001b +sys_encode_table_ic: + ;ic op0 op1 crn crm op2 + sys_encode_iallu: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00101b shl 3 + 0000b + sys_encode_ialluis: dw 001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00001b shl 3 + 0000b + sys_encode_ivau: dw 001b shl 14 + 0011b shl 11 + 00111b shl 7 + 00101b shl 3 + 0001b +sys_encode_table_tlbi: + ;tlbi op0 op1 crn crm op2 + sys_encode_alle1: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0100b + sys_encode_alle1is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0100b + sys_encode_alle2: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b + sys_encode_alle2is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b + sys_encode_alle3: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b + sys_encode_alle3is: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b + sys_encode_aside1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0010b + sys_encode_aside1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0010b + sys_encode_ipas2e1: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00100b shl 3 + 0001b + sys_encode_ipas2e1is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00000b shl 3 + 0001b + sys_encode_ipas2le1: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00100b shl 3 + 0101b + sys_encode_ipas2le1is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00000b shl 3 + 0101b + sys_encode_vaae1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0011b + sys_encode_vaae1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0011b + sys_encode_vaale1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0111b + sys_encode_vaale1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0111b + sys_encode_vae1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b + sys_encode_vae1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b + sys_encode_vae2: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b + sys_encode_vae2is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b + sys_encode_vae3: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b + sys_encode_vae3is: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b + sys_encode_vale1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b + sys_encode_vale1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b + sys_encode_vale2: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b + sys_encode_vale2is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b + sys_encode_vale3: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b + sys_encode_vale3is: dw 001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b + sys_encode_vmalle1: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b + sys_encode_vmalle1is: dw 001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b + sys_encode_vmalls12e1: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0110b + sys_encode_vmalls12e1is: dw 001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0110b +sys_encode_table_msr: + ;msr/mrs op0 op1 crn crm op2 + sys_encode_actlr_el1: dw 011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b + sys_encode_actlr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b + sys_encode_actlr_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b + sys_encode_afsr0_el1: dw 011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b + sys_encode_afsr0_el2: dw 011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b + sys_encode_afsr0_el3: dw 011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b + sys_encode_afsr1_el1: dw 011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b + sys_encode_afsr1_el2: dw 011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b + sys_encode_afsr1_el3: dw 011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b + sys_encode_aidr_el1: dw 011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b + sys_encode_amair_el1: dw 011b shl 14 + 0000b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b + sys_encode_amair_el2: dw 011b shl 14 + 0100b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b + sys_encode_amair_el3: dw 011b shl 14 + 0110b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b + sys_encode_ccsidr_el1: dw 011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b + sys_encode_clidr_el1: dw 011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0001b + sys_encode_cntfrq_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0000b + sys_encode_cnthctl_el2: dw 011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00001b shl 3 + 0000b + sys_encode_cnthp_ctl_el2: dw 011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b + sys_encode_cnthp_cval_el2: dw 011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b + sys_encode_cnthp_tval_el2: dw 011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b + sys_encode_cntkctl_el1: dw 011b shl 14 + 0000b shl 11 + 01110b shl 7 + 00001b shl 3 + 0000b + sys_encode_cntp_ctl_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b + sys_encode_cntp_cval_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b + sys_encode_cntp_tval_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b + sys_encode_cntpct_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0001b + sys_encode_cntps_ctl_el1: dw 011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b + sys_encode_cntps_cval_el1: dw 011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b + sys_encode_cntps_tval_el1: dw 011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b + sys_encode_cntv_ctl_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0001b + sys_encode_cntv_cval_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0010b + sys_encode_cntv_tval_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0000b + sys_encode_cntvct_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0010b + sys_encode_cntvoff_el2: dw 011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00000b shl 3 + 0011b + sys_encode_contextidr_el1: dw 011b shl 14 + 0000b shl 11 + 01101b shl 7 + 00000b shl 3 + 0001b + sys_encode_cpacr_el1: dw 011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0010b + sys_encode_cptr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0010b + sys_encode_cptr_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0010b + sys_encode_csselr_el1: dw 011b shl 14 + 0010b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b + sys_encode_ctr_el0: dw 011b shl 14 + 0011b shl 11 + 00000b shl 7 + 00000b shl 3 + 0001b + sys_encode_currentel: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00010b shl 3 + 0010b + sys_encode_dacr32_el2: dw 011b shl 14 + 0100b shl 11 + 00011b shl 7 + 00000b shl 3 + 0000b + sys_encode_daif: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00010b shl 3 + 0001b + sys_encode_dbgauthstatus_el1: dw 010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01110b shl 3 + 0110b + sys_encode_dbgbcr0_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b + sys_encode_dbgbcr1_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0101b + sys_encode_dbgbcr10_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0101b + sys_encode_dbgbcr11_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0101b + sys_encode_dbgbcr12_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0101b + sys_encode_dbgbcr13_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0101b + sys_encode_dbgbcr14_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0101b + sys_encode_dbgbcr15_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0101b + sys_encode_dbgbcr2_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0101b + sys_encode_dbgbcr3_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0101b + sys_encode_dbgbcr4_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0101b + sys_encode_dbgbcr5_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0101b + sys_encode_dbgbcr6_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0101b + sys_encode_dbgbcr7_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0101b + sys_encode_dbgbcr8_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0101b + sys_encode_dbgbcr9_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0101b + sys_encode_dbgbvr0_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0100b + sys_encode_dbgbvr1_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0100b + sys_encode_dbgbvr10_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0100b + sys_encode_dbgbvr11_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0100b + sys_encode_dbgbvr12_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0100b + sys_encode_dbgbvr13_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0100b + sys_encode_dbgbvr14_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0100b + sys_encode_dbgbvr15_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0100b + sys_encode_dbgbvr2_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0100b + sys_encode_dbgbvr3_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0100b + sys_encode_dbgbvr4_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0100b + sys_encode_dbgbvr5_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0100b + sys_encode_dbgbvr6_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0100b + sys_encode_dbgbvr7_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0100b + sys_encode_dbgbvr8_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0100b + sys_encode_dbgbvr9_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0100b + sys_encode_dbgclaimclr_el1: dw 010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01001b shl 3 + 0110b + sys_encode_dbgclaimset_el1: dw 010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0110b + sys_encode_dbgdtr_el0: dw 010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00100b shl 3 + 0000b + sys_encode_dbgdtrrx_el0: dw 010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b + sys_encode_dbgdtrtx_el0: dw 010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b + sys_encode_dbgprcr_el1: dw 010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00100b shl 3 + 0100b + sys_encode_dbgvcr32_el2: dw 010b shl 14 + 0100b shl 11 + 00000b shl 7 + 00111b shl 3 + 0000b + sys_encode_dbgwcr0_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b + sys_encode_dbgwcr1_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0111b + sys_encode_dbgwcr10_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0111b + sys_encode_dbgwcr11_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0111b + sys_encode_dbgwcr12_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0111b + sys_encode_dbgwcr13_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0111b + sys_encode_dbgwcr14_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0111b + sys_encode_dbgwcr15_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0111b + sys_encode_dbgwcr2_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0111b + sys_encode_dbgwcr3_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0111b + sys_encode_dbgwcr4_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0111b + sys_encode_dbgwcr5_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0111b + sys_encode_dbgwcr6_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0111b + sys_encode_dbgwcr7_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0111b + sys_encode_dbgwcr8_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0111b + sys_encode_dbgwcr9_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0111b + sys_encode_dbgwvr0_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0110b + sys_encode_dbgwvr1_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0110b + sys_encode_dbgwvr10_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0110b + sys_encode_dbgwvr11_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0110b + sys_encode_dbgwvr12_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0110b + sys_encode_dbgwvr13_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0110b + sys_encode_dbgwvr14_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0110b + sys_encode_dbgwvr15_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0110b + sys_encode_dbgwvr2_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0110b + sys_encode_dbgwvr3_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0110b + sys_encode_dbgwvr4_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0110b + sys_encode_dbgwvr5_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0110b + sys_encode_dbgwvr6_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0110b + sys_encode_dbgwvr7_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0110b + sys_encode_dbgwvr8_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0110b + sys_encode_dbgwvr9_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0110b + sys_encode_dczid_el0: dw 011b shl 14 + 0011b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b + sys_encode_dlr_el0: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00101b shl 3 + 0001b + sys_encode_dspsr_el0: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00101b shl 3 + 0000b + sys_encode_elr_el1: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b + sys_encode_elr_el2: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b + sys_encode_elr_el3: dw 011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b + sys_encode_esr_el1: dw 011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b + sys_encode_esr_el2: dw 011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b + sys_encode_esr_el3: dw 011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b + sys_encode_far_el1: dw 011b shl 14 + 0000b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b + sys_encode_far_el2: dw 011b shl 14 + 0100b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b + sys_encode_far_el3: dw 011b shl 14 + 0110b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b + sys_encode_fpcr: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00100b shl 3 + 0000b + sys_encode_fpexc32_el2: dw 011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00011b shl 3 + 0000b + sys_encode_fpsr: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00100b shl 3 + 0001b + sys_encode_hacr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0111b + sys_encode_hcr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0000b + sys_encode_hpfar_el2: dw 011b shl 14 + 0100b shl 11 + 00110b shl 7 + 00000b shl 3 + 0100b + sys_encode_hstr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0011b + sys_encode_icc_ap0r0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0100b + sys_encode_icc_ap0r1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0101b + sys_encode_icc_ap0r2_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0110b + sys_encode_icc_ap0r3_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0111b + sys_encode_icc_ap1r0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b + sys_encode_icc_ap1r1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b + sys_encode_icc_ap1r2_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b + sys_encode_icc_ap1r3_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b + sys_encode_icc_asgi1r_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0110b + sys_encode_icc_bpr0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b + sys_encode_icc_bpr1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b + sys_encode_icc_ctlr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b + sys_encode_icc_ctlr_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b + sys_encode_icc_dir_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b + sys_encode_icc_eoir0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b + sys_encode_icc_eoir1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b + sys_encode_icc_hppir0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b + sys_encode_icc_hppir1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b + sys_encode_icc_iar0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b + sys_encode_icc_iar1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b + sys_encode_icc_igrpen0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b + sys_encode_icc_igrpen1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b + sys_encode_icc_igrpen1_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b + sys_encode_icc_pmr_el1: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00110b shl 3 + 0000b + sys_encode_icc_rpr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b + sys_encode_icc_sgi0r_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0111b + sys_encode_icc_sgi1r_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0101b + sys_encode_icc_sre_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b + sys_encode_icc_sre_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0101b + sys_encode_icc_sre_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b + sys_encode_ich_ap0r0_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b + sys_encode_ich_ap0r1_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b + sys_encode_ich_ap0r2_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b + sys_encode_ich_ap0r3_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b + sys_encode_ich_ap1r0_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b + sys_encode_ich_ap1r1_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b + sys_encode_ich_ap1r2_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b + sys_encode_ich_ap1r3_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b + sys_encode_ich_eisr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b + sys_encode_ich_elrsr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0101b + sys_encode_ich_hcr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0000b + sys_encode_ich_lr0_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b + sys_encode_ich_lr1_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b + sys_encode_ich_lr10_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0010b + sys_encode_ich_lr11_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0011b + sys_encode_ich_lr12_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0100b + sys_encode_ich_lr13_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0101b + sys_encode_ich_lr14_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0110b + sys_encode_ich_lr15_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0111b + sys_encode_ich_lr2_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b + sys_encode_ich_lr3_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b + sys_encode_ich_lr4_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b + sys_encode_ich_lr5_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b + sys_encode_ich_lr6_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b + sys_encode_ich_lr7_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b + sys_encode_ich_lr8_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0000b + sys_encode_ich_lr9_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0001b + sys_encode_ich_misr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0010b + sys_encode_ich_vmcr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0111b + sys_encode_ich_vtr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b + sys_encode_icv_ap0r0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0100b + sys_encode_icv_ap0r1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0101b + sys_encode_icv_ap0r2_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0110b + sys_encode_icv_ap0r3_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0111b + sys_encode_icv_ap1r0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b + sys_encode_icv_ap1r1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b + sys_encode_icv_ap1r2_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b + sys_encode_icv_ap1r3_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b + sys_encode_icv_bpr0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b + sys_encode_icv_bpr1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b + sys_encode_icv_ctlr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b + sys_encode_icv_dir_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b + sys_encode_icv_eoir0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b + sys_encode_icv_eoir1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b + sys_encode_icv_hppir0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b + sys_encode_icv_hppir1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b + sys_encode_icv_iar0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b + sys_encode_icv_iar1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b + sys_encode_icv_igrpen0_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b + sys_encode_icv_igrpen1_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b + sys_encode_icv_pmr_el1: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00110b shl 3 + 0000b + sys_encode_icv_rpr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b + sys_encode_id_aa64afr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0100b + sys_encode_id_aa64afr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0101b + sys_encode_id_aa64dfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b + sys_encode_id_aa64dfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0001b + sys_encode_id_aa64isar0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0000b + sys_encode_id_aa64isar1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0001b + sys_encode_id_aa64mmfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0000b + sys_encode_id_aa64mmfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0001b + sys_encode_id_aa64pfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0000b + sys_encode_id_aa64pfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0001b + sys_encode_id_afr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0011b + sys_encode_id_dfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0010b + sys_encode_id_isar0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0000b + sys_encode_id_isar1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0001b + sys_encode_id_isar2_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0010b + sys_encode_id_isar3_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0011b + sys_encode_id_isar4_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0100b + sys_encode_id_isar5_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0101b + sys_encode_id_mmfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0100b + sys_encode_id_mmfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0101b + sys_encode_id_mmfr2_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0110b + sys_encode_id_mmfr3_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0111b + sys_encode_id_mmfr4_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0110b + sys_encode_id_pfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0000b + sys_encode_id_pfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0001b + sys_encode_ifsr32_el2: dw 011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00000b shl 3 + 0001b + sys_encode_isr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00001b shl 3 + 0000b + sys_encode_mair_el1: dw 011b shl 14 + 0000b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b + sys_encode_mair_el2: dw 011b shl 14 + 0100b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b + sys_encode_mair_el3: dw 011b shl 14 + 0110b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b + sys_encode_mdccint_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0000b + sys_encode_mdccsr_el0: dw 010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00001b shl 3 + 0000b + sys_encode_mdcr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0001b + sys_encode_mdcr_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00011b shl 3 + 0001b + sys_encode_mdrar_el1: dw 010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b + sys_encode_mdscr_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0010b + sys_encode_midr_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b + sys_encode_mpidr_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b + sys_encode_mvfr0_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0000b + sys_encode_mvfr1_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0001b + sys_encode_mvfr2_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0010b + sys_encode_nzcv: dw 011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00010b shl 3 + 0000b + sys_encode_osdlr_el1: dw 010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00011b shl 3 + 0100b + sys_encode_osdtrrx_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0010b + sys_encode_osdtrtx_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0010b + sys_encode_oseccr_el1: dw 010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0010b + sys_encode_oslar_el1: dw 010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0100b + sys_encode_oslsr_el1: dw 010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00001b shl 3 + 0100b + sys_encode_par_el1: dw 011b shl 14 + 0000b shl 11 + 00111b shl 7 + 00100b shl 3 + 0000b + sys_encode_pmccfiltr_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0111b + sys_encode_pmccntr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0000b + sys_encode_pmceid0_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0110b + sys_encode_pmceid1_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0111b + sys_encode_pmcntenclr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0010b + sys_encode_pmcntenset_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0001b + sys_encode_pmcr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0000b + sys_encode_pmevcntr0_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0000b + sys_encode_pmevcntr1_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0001b + sys_encode_pmevcntr10_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0010b + sys_encode_pmevcntr11_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0011b + sys_encode_pmevcntr12_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0100b + sys_encode_pmevcntr13_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0101b + sys_encode_pmevcntr14_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0110b + sys_encode_pmevcntr15_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0111b + sys_encode_pmevcntr16_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0000b + sys_encode_pmevcntr17_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0001b + sys_encode_pmevcntr18_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0010b + sys_encode_pmevcntr19_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0011b + sys_encode_pmevcntr2_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0010b + sys_encode_pmevcntr20_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0100b + sys_encode_pmevcntr21_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0101b + sys_encode_pmevcntr22_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0110b + sys_encode_pmevcntr23_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0111b + sys_encode_pmevcntr24_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0000b + sys_encode_pmevcntr25_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0001b + sys_encode_pmevcntr26_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0010b + sys_encode_pmevcntr27_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0011b + sys_encode_pmevcntr28_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0100b + sys_encode_pmevcntr29_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0101b + sys_encode_pmevcntr3_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0011b + sys_encode_pmevcntr30_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0110b + sys_encode_pmevcntr4_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0100b + sys_encode_pmevcntr5_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0101b + sys_encode_pmevcntr6_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0110b + sys_encode_pmevcntr7_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0111b + sys_encode_pmevcntr8_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0000b + sys_encode_pmevcntr9_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0001b + sys_encode_pmevtyper0_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0000b + sys_encode_pmevtyper1_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0001b + sys_encode_pmevtyper10_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0010b + sys_encode_pmevtyper11_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0011b + sys_encode_pmevtyper12_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0100b + sys_encode_pmevtyper13_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0101b + sys_encode_pmevtyper14_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0110b + sys_encode_pmevtyper15_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0111b + sys_encode_pmevtyper16_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0000b + sys_encode_pmevtyper17_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0001b + sys_encode_pmevtyper18_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0010b + sys_encode_pmevtyper19_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0011b + sys_encode_pmevtyper2_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0010b + sys_encode_pmevtyper20_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0100b + sys_encode_pmevtyper21_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0101b + sys_encode_pmevtyper22_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0110b + sys_encode_pmevtyper23_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0111b + sys_encode_pmevtyper24_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0000b + sys_encode_pmevtyper25_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0001b + sys_encode_pmevtyper26_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0010b + sys_encode_pmevtyper27_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0011b + sys_encode_pmevtyper28_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0100b + sys_encode_pmevtyper29_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0101b + sys_encode_pmevtyper3_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0011b + sys_encode_pmevtyper30_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0110b + sys_encode_pmevtyper4_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0100b + sys_encode_pmevtyper5_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0101b + sys_encode_pmevtyper6_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0110b + sys_encode_pmevtyper7_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0111b + sys_encode_pmevtyper8_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0000b + sys_encode_pmevtyper9_el0: dw 011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0001b + sys_encode_pmintenclr_el1: dw 011b shl 14 + 0000b shl 11 + 01001b shl 7 + 01110b shl 3 + 0010b + sys_encode_pmintenset_el1: dw 011b shl 14 + 0000b shl 11 + 01001b shl 7 + 01110b shl 3 + 0001b + sys_encode_pmovsclr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0011b + sys_encode_pmovsset_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01110b shl 3 + 0011b + sys_encode_pmselr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0101b + sys_encode_pmswinc_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0100b + sys_encode_pmuserenr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01110b shl 3 + 0000b + sys_encode_pmxevcntr_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0010b + sys_encode_pmxevtyper_el0: dw 011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0001b + sys_encode_revidr_el1: dw 011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0110b + sys_encode_rmr_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b + sys_encode_rmr_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b + sys_encode_rmr_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b + sys_encode_rvbar_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b + sys_encode_rvbar_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b + sys_encode_rvbar_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b + sys_encode_scr_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0000b + sys_encode_sctlr_el1: dw 011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b + sys_encode_sctlr_el2: dw 011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b + sys_encode_sctlr_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b + sys_encode_sder32_el3: dw 011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0001b + sys_encode_sp_el0: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b + sys_encode_sp_el1: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b + sys_encode_sp_el2: dw 011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b + sys_encode_spsel: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00010b shl 3 + 0000b + sys_encode_spsr_abt: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0001b + sys_encode_spsr_el1: dw 011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b + sys_encode_spsr_el2: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b + sys_encode_spsr_el3: dw 011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b + sys_encode_spsr_fiq: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0011b + sys_encode_spsr_irq: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0000b + sys_encode_spsr_und: dw 011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0010b + sys_encode_tcr_el1: dw 011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b + sys_encode_tcr_el2: dw 011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b + sys_encode_tcr_el3: dw 011b shl 14 + 0110b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b + sys_encode_tpidr_el0: dw 011b shl 14 + 0011b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b + sys_encode_tpidr_el1: dw 011b shl 14 + 0000b shl 11 + 01101b shl 7 + 00000b shl 3 + 0100b + sys_encode_tpidr_el2: dw 011b shl 14 + 0100b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b + sys_encode_tpidr_el3: dw 011b shl 14 + 0110b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b + sys_encode_tpidrro_el0: dw 011b shl 14 + 0011b shl 11 + 01101b shl 7 + 00000b shl 3 + 0011b + sys_encode_ttbr0_el1: dw 011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b + sys_encode_ttbr0_el2: dw 011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b + sys_encode_ttbr0_el3: dw 011b shl 14 + 0110b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b + sys_encode_ttbr1_el1: dw 011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0001b + sys_encode_vbar_el1: dw 011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b + sys_encode_vbar_el2: dw 011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b + sys_encode_vbar_el3: dw 011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b + sys_encode_vmpidr_el2: dw 011b shl 14 + 0100b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b + sys_encode_vpidr_el2: dw 011b shl 14 + 0100b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b + sys_encode_vtcr_el2: dw 011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00001b shl 3 + 0010b + sys_encode_vttbr_el2: dw 011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00001b shl 3 + 0000b +sys_encode_table_pstate: + ;msr imm op0 op1 crn crm op2 + sys_pencode_daifclr: dw 000b shl 14 + 0011b shl 11 + 00100b shl 7 + 00000b shl 3 + 0111b + sys_pencode_daifset: dw 000b shl 14 + 0011b shl 11 + 00100b shl 7 + 00000b shl 3 + 0110b + sys_pencode_spsel: dw 000b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0101b + +data_directives: + dw data_directives_2-data_directives,(data_directives_3-data_directives_2)/(2+3) + dw data_directives_3-data_directives,(data_directives_4-data_directives_3)/(3+3) + dw data_directives_4-data_directives,(data_directives_end-data_directives_4)/(4+3) + +data_directives_2: + db 'db',1 + dw data_bytes-instruction_handler + db 'dd',8 + dw data_qwords-instruction_handler ;ARM dwords + db 'dh',2 + dw data_words-instruction_handler ;ARM hwords + db 'du',2 + dw data_unicode-instruction_handler + db 'dw',4 + dw data_dwords-instruction_handler ;ARM words + db 'rb',1 + dw reserve_bytes-instruction_handler + db 'rd',8 + dw reserve_qwords-instruction_handler ;ARM dwords + db 'rh',2 + dw reserve_words-instruction_handler ;ARM hwords + db 'rw',4 + dw reserve_dwords-instruction_handler ;ARM words +data_directives_3: +data_directives_4: + db 'file',1 + dw data_file-instruction_handler +data_directives_end: + +instructions: + dd instructions_1-instructions,(instructions_2-instructions_1)/(1+3) + dd instructions_2-instructions,(instructions_3-instructions_2)/(2+3) + dd instructions_3-instructions,(instructions_4-instructions_3)/(3+3) + dd instructions_4-instructions,(instructions_5-instructions_4)/(4+3) + dd instructions_5-instructions,(instructions_6-instructions_5)/(5+3) + dd instructions_6-instructions,(instructions_7-instructions_6)/(6+3) + dd instructions_7-instructions,(instructions_8-instructions_7)/(7+3) + dd instructions_8-instructions,(instructions_9-instructions_8)/(8+3) + dd instructions_9-instructions,(instructions_10-instructions_9)/(9+3) + dd instructions_10-instructions,(instructions_11-instructions_10)/(10+3) + dd instructions_11-instructions,(instructions_12-instructions_11)/(11+3) + dd instructions_12-instructions,(instructions_13-instructions_12)/(12+3) + dd instructions_13-instructions,(instructions_14-instructions_13)/(13+3) + dd instructions_14-instructions,(instructions_15-instructions_14)/(14+3) + dd instructions_15-instructions,(instructions_16-instructions_15)/(15+3) + dd instructions_16-instructions,(instructions_end-instructions_16)/(16+3) +instructions_1: + db 'b',0xe0 + dw ARM_instruction_b-instruction_handler + db 0 +instructions_2: + db 'at',0xf0 + dw ARM_instruction_at-instruction_handler + db 'bl',0xe0 + dw ARM_instruction_bl-instruction_handler + db 'br',0xf0 + dw ARM_instruction_br-instruction_handler + db 'bx',0xe0 + dw ARM_instruction_bx-instruction_handler + db 'dc',0xf0 + dw ARM_instruction_dc-instruction_handler + db 'hb',0xe0 + dw ARM_instruction_hb-instruction_handler + db 'ic',0xf0 + dw ARM_instruction_ic-instruction_handler + db 'if',0x00 + dw if_directive-instruction_handler + db 'it',0xf0 + dw ARM_instruction_it-instruction_handler + db 0 +instructions_3: + db 'abs',0xf0 + dw ARM_instruction_abs-instruction_handler + db 'adc',0xe0 + dw ARM_instruction_adc-instruction_handler + db 'add',0xe0 + dw ARM_instruction_add-instruction_handler + db 'adr',0xe0 + dw ARM_instruction_adr-instruction_handler + db 'and',0xe0 + dw ARM_instruction_and-instruction_handler + db 'asr',0xe0 + dw ARM_instruction_asr-instruction_handler + db 'b.n',0xe4 + dw ARM_instruction_b-instruction_handler + db 'b.w',0xe2 + dw ARM_instruction_b-instruction_handler + db 'bfc',0xe0 + dw ARM_instruction_bfc-instruction_handler + db 'bfi',0xe0 + dw ARM_instruction_bfi-instruction_handler + db 'bfm',0xf0 + dw ARM_instruction_bfm-instruction_handler + db 'bic',0xe0 + dw ARM_instruction_bic-instruction_handler + db 'bif',0xf0 + dw ARM_instruction_bif-instruction_handler + db 'bit',0xf0 + dw ARM_instruction_bit-instruction_handler + db 'blr',0xf0 + dw ARM_instruction_blr-instruction_handler + db 'blx',0xe0 + dw ARM_instruction_blx-instruction_handler + db 'brk',0xf0 + dw ARM_instruction_brk-instruction_handler + db 'bsl',0xf0 + dw ARM_instruction_bsl-instruction_handler + db 'bxj',0xe0 + dw ARM_instruction_bxj-instruction_handler + db 'b~~',0x00 + dw ARM_instruction_b-instruction_handler + db 'cbz',0xf0 + dw ARM_instruction_cbz-instruction_handler + db 'cdp',0xe0 + dw ARM_instruction_cdp-instruction_handler + db 'cls',0xf0 + dw ARM_instruction_cls-instruction_handler + db 'clz',0xe0 + dw ARM_instruction_clz-instruction_handler + db 'cmf',0xe0 + dw ARM_instruction_cmf-instruction_handler + db 'cmn',0xe0 + dw ARM_instruction_cmn-instruction_handler + db 'cmp',0xe0 + dw ARM_instruction_cmp-instruction_handler + db 'cnf',0xe0 + dw ARM_instruction_cnf-instruction_handler + db 'cnt',0xf0 + dw ARM_instruction_cnt-instruction_handler + db 'cps',0xf0 + dw ARM_instruction_cps-instruction_handler + db 'cpy',0xe0 + dw ARM_instruction_cpy-instruction_handler + db 'dbg',0xe0 + dw ARM_instruction_dbg-instruction_handler + db 'dmb',0xf0 + dw ARM_instruction_dmb-instruction_handler + db 'dsb',0xf0 + dw ARM_instruction_dsb-instruction_handler + db 'dup',0xf0 + dw ARM_instruction_dup-instruction_handler + db 'end',0x00 + dw end_directive-instruction_handler + db 'eon',0xf0 + dw ARM_instruction_eon-instruction_handler + db 'eor',0xe0 + dw ARM_instruction_eor-instruction_handler + db 'err',0x00 + dw err_directive-instruction_handler + db 'ext',0xf0 + dw ARM_instruction_ext-instruction_handler + db 'fix',0xe0 + dw ARM_instruction_fix-instruction_handler + db 'hbl',0xe0 + dw ARM_instruction_hbl-instruction_handler + db 'hbp',0xe0 + dw ARM_instruction_hbp-instruction_handler + db 'hlt',0xe0 + dw ARM_instruction_hlt-instruction_handler + db 'hvc',0xe0 + dw ARM_instruction_hvc-instruction_handler + db 'ins',0xf0 + dw ARM_instruction_ins-instruction_handler + db 'isb',0xf0 + dw ARM_instruction_isb-instruction_handler + db 'ite',0xf0 + dw ARM_instruction_ite-instruction_handler + db 'itt',0xf0 + dw ARM_instruction_itt-instruction_handler + db 'ld1',0xf0 + dw ARM_instruction_ld1-instruction_handler + db 'ld2',0xf0 + dw ARM_instruction_ld2-instruction_handler + db 'ld3',0xf0 + dw ARM_instruction_ld3-instruction_handler + db 'ld4',0xf0 + dw ARM_instruction_ld4-instruction_handler + db 'lda',0xe0 + dw ARM_instruction_lda-instruction_handler + db 'ldc',0xe0 + dw ARM_instruction_ldc-instruction_handler + db 'ldm',0xe0 + dw ARM_instruction_ldm-instruction_handler + db 'ldp',0xf0 + dw ARM_instruction_ldp-instruction_handler + db 'ldr',0xe0 + dw ARM_instruction_ldr-instruction_handler + db 'lfm',0xe0 + dw ARM_instruction_lfm-instruction_handler + db 'lsl',0xe0 + dw ARM_instruction_lsl-instruction_handler + db 'lsr',0xe0 + dw ARM_instruction_lsr-instruction_handler + db 'mar',0xe0 + dw ARM_instruction_mar-instruction_handler + db 'mcr',0xe0 + dw ARM_instruction_mcr-instruction_handler + db 'mia',0xe0 + dw ARM_instruction_mia-instruction_handler + db 'mla',0xe0 + dw ARM_instruction_mla-instruction_handler + db 'mls',0xe0 + dw ARM_instruction_mls-instruction_handler + db 'mov',0xe0 + dw ARM_instruction_mov-instruction_handler + db 'mra',0xe0 + dw ARM_instruction_mra-instruction_handler + db 'mrc',0xe0 + dw ARM_instruction_mrc-instruction_handler + db 'mrs',0xe0 + dw ARM_instruction_mrs-instruction_handler + db 'msr',0xe0 + dw ARM_instruction_msr-instruction_handler + db 'mul',0xe0 + dw ARM_instruction_mul-instruction_handler + db 'mvn',0xe0 + dw ARM_instruction_mvn-instruction_handler + db 'neg',0xe0 + dw ARM_instruction_neg-instruction_handler + db 'ngc',0xf0 + dw ARM_instruction_ngc-instruction_handler + db 'nop',0xe0 + dw ARM_instruction_nop-instruction_handler + db 'not',0xf0 + dw ARM_instruction_not-instruction_handler + db 'org',0x00 + dw ARM_org_directive-instruction_handler + db 'orn',0xe0 + dw ARM_instruction_orn-instruction_handler + db 'orr',0xe0 + dw ARM_instruction_orr-instruction_handler + db 'pld',0xe0 + dw ARM_instruction_pld-instruction_handler + db 'pli',0xe0 + dw ARM_instruction_pli-instruction_handler + db 'pop',0xe0 + dw ARM_instruction_pop-instruction_handler + db 'ret',0xf0 + dw ARM_instruction_ret-instruction_handler + db 'rev',0xe0 + dw ARM_instruction_rev-instruction_handler + db 'rfc',0xe0 + dw ARM_instruction_rfc-instruction_handler + db 'rfe',0xf0 + dw ARM_instruction_rfe-instruction_handler + db 'rfs',0xe0 + dw ARM_instruction_rfs-instruction_handler + db 'ror',0xe0 + dw ARM_instruction_ror-instruction_handler + db 'rrx',0xe0 + dw ARM_instruction_rrx-instruction_handler + db 'rsb',0xe0 + dw ARM_instruction_rsb-instruction_handler + db 'rsc',0xe0 + dw ARM_instruction_rsc-instruction_handler + db 'sbc',0xe0 + dw ARM_instruction_sbc-instruction_handler + db 'sel',0xe0 + dw ARM_instruction_sel-instruction_handler + db 'sev',0xe0 + dw ARM_instruction_sev-instruction_handler + db 'sfm',0xe0 + dw ARM_instruction_sfm-instruction_handler + db 'shl',0xf0 + dw ARM_instruction_shl-instruction_handler + db 'sli',0xf0 + dw ARM_instruction_sli-instruction_handler + db 'smc',0xe0 + dw ARM_instruction_smc-instruction_handler + db 'smi',0xe0 + dw ARM_instruction_smi-instruction_handler + db 'sri',0xf0 + dw ARM_instruction_sri-instruction_handler + db 'srs',0xf0 + dw ARM_instruction_srs-instruction_handler + db 'st1',0xf0 + dw ARM_instruction_st1-instruction_handler + db 'st2',0xf0 + dw ARM_instruction_st2-instruction_handler + db 'st3',0xf0 + dw ARM_instruction_st3-instruction_handler + db 'st4',0xf0 + dw ARM_instruction_st4-instruction_handler + db 'stc',0xe0 + dw ARM_instruction_stc-instruction_handler + db 'stl',0xe0 + dw ARM_instruction_stl-instruction_handler + db 'stm',0xe0 + dw ARM_instruction_stm-instruction_handler + db 'stp',0xf0 + dw ARM_instruction_stp-instruction_handler + db 'str',0xe0 + dw ARM_instruction_str-instruction_handler + db 'sub',0xe0 + dw ARM_instruction_sub-instruction_handler + db 'svc',0xe0 + dw ARM_instruction_svc-instruction_handler + db 'swi',0xe0 + dw ARM_instruction_swi-instruction_handler + db 'swp',0xe0 + dw ARM_instruction_swp-instruction_handler + db 'sys',0xf0 + dw ARM_instruction_sys-instruction_handler + db 'tbb',0xe0 + dw ARM_instruction_tbb-instruction_handler + db 'tbh',0xe0 + dw ARM_instruction_tbh-instruction_handler + db 'tbl',0xf0 + dw ARM_instruction_tbl-instruction_handler + db 'tbx',0xf0 + dw ARM_instruction_tbx-instruction_handler + db 'tbz',0xf0 + dw ARM_instruction_tbz-instruction_handler + db 'teq',0xe0 + dw ARM_instruction_teq-instruction_handler + db 'tst',0xe0 + dw ARM_instruction_tst-instruction_handler + db 'und',0xe0 + dw ARM_instruction_und-instruction_handler + db 'wfc',0xe0 + dw ARM_instruction_wfc-instruction_handler + db 'wfe',0xe0 + dw ARM_instruction_wfe-instruction_handler + db 'wfi',0xe0 + dw ARM_instruction_wfi-instruction_handler + db 'wfs',0xe0 + dw ARM_instruction_wfs-instruction_handler + db 'wor',0xe0 + dw ARM_instruction_wor-instruction_handler + db 'xtn',0xf0 + dw ARM_instruction_xtn-instruction_handler + db 0 +instructions_4: + db 'absd',0xe0 + dw ARM_instruction_absd-instruction_handler + db 'abse',0xe0 + dw ARM_instruction_abse-instruction_handler + db 'abss',0xe0 + dw ARM_instruction_abss-instruction_handler + db 'acsd',0xe0 + dw ARM_instruction_acsd-instruction_handler + db 'acse',0xe0 + dw ARM_instruction_acse-instruction_handler + db 'acss',0xe0 + dw ARM_instruction_acss-instruction_handler + db 'adcs',0xe1 + dw ARM_instruction_adc-instruction_handler + db 'addp',0xf0 + dw ARM_instruction_addp-instruction_handler + db 'adds',0xe1 + dw ARM_instruction_add-instruction_handler + db 'addv',0xf0 + dw ARM_instruction_addv-instruction_handler + db 'addw',0xe0 + dw ARM_instruction_addw-instruction_handler + db 'adfd',0xe0 + dw ARM_instruction_adfd-instruction_handler + db 'adfe',0xe0 + dw ARM_instruction_adfe-instruction_handler + db 'adfs',0xe0 + dw ARM_instruction_adfs-instruction_handler + db 'adrp',0xf0 + dw ARM_instruction_adrp-instruction_handler + db 'aesd',0xf0 + dw ARM_instruction_aesd-instruction_handler + db 'aese',0xf0 + dw ARM_instruction_aese-instruction_handler + db 'ands',0xe1 + dw ARM_instruction_and-instruction_handler + db 'asnd',0xe0 + dw ARM_instruction_asnd-instruction_handler + db 'asne',0xe0 + dw ARM_instruction_asne-instruction_handler + db 'asns',0xe0 + dw ARM_instruction_asns-instruction_handler + db 'asrs',0xe1 + dw ARM_instruction_asr-instruction_handler + db 'asrv',0xf0 + dw ARM_instruction_asrv-instruction_handler + db 'atnd',0xe0 + dw ARM_instruction_atnd-instruction_handler + db 'atne',0xe0 + dw ARM_instruction_atne-instruction_handler + db 'atns',0xe0 + dw ARM_instruction_atns-instruction_handler + db 'b.al',0xf0 + dw ARM_instruction_b.al-instruction_handler + db 'b.cc',0xf0 + dw ARM_instruction_b.cc-instruction_handler + db 'b.cs',0xf0 + dw ARM_instruction_b.cs-instruction_handler + db 'b.eq',0xf0 + dw ARM_instruction_b.eq-instruction_handler + db 'b.ge',0xf0 + dw ARM_instruction_b.ge-instruction_handler + db 'b.gt',0xf0 + dw ARM_instruction_b.gt-instruction_handler + db 'b.hi',0xf0 + dw ARM_instruction_b.hi-instruction_handler + db 'b.hs',0xf0 + dw ARM_instruction_b.hs-instruction_handler + db 'b.le',0xf0 + dw ARM_instruction_b.le-instruction_handler + db 'b.lo',0xf0 + dw ARM_instruction_b.lo-instruction_handler + db 'b.ls',0xf0 + dw ARM_instruction_b.ls-instruction_handler + db 'b.lt',0xf0 + dw ARM_instruction_b.lt-instruction_handler + db 'b.mi',0xf0 + dw ARM_instruction_b.mi-instruction_handler + db 'b.ne',0xf0 + dw ARM_instruction_b.ne-instruction_handler + db 'b.nv',0xf0 + dw ARM_instruction_b.nv-instruction_handler + db 'b.pl',0xf0 + dw ARM_instruction_b.pl-instruction_handler + db 'b.vc',0xf0 + dw ARM_instruction_b.vc-instruction_handler + db 'b.vs',0xf0 + dw ARM_instruction_b.vs-instruction_handler + db 'bics',0xe1 + dw ARM_instruction_bic-instruction_handler + db 'bkpt',0xe0 + dw ARM_instruction_bkpt-instruction_handler + db 'bl~~',0x00 + dw ARM_instruction_bl-instruction_handler + db 'bx.n',0xe4 + dw ARM_instruction_bx-instruction_handler + db 'bx.w',0xe2 + dw ARM_instruction_bx-instruction_handler + db 'bx~~',0x00 + dw ARM_instruction_bx-instruction_handler + db 'cbnz',0xf0 + dw ARM_instruction_cbnz-instruction_handler + db 'ccmn',0xf0 + dw ARM_instruction_ccmn-instruction_handler + db 'ccmp',0xf0 + dw ARM_instruction_ccmp-instruction_handler + db 'cdp2',0xe0 + dw ARM_instruction_cdp2-instruction_handler + db 'chka',0xe0 + dw ARM_instruction_chka-instruction_handler + db 'cinc',0xf0 + dw ARM_instruction_cinc-instruction_handler + db 'cinv',0xf0 + dw ARM_instruction_cinv-instruction_handler + db 'cmeq',0xf0 + dw ARM_instruction_cmeq-instruction_handler + db 'cmfe',0xe0 + dw ARM_instruction_cmfe-instruction_handler + db 'cmge',0xf0 + dw ARM_instruction_cmge-instruction_handler + db 'cmgt',0xf0 + dw ARM_instruction_cmgt-instruction_handler + db 'cmhi',0xf0 + dw ARM_instruction_cmhi-instruction_handler + db 'cmhs',0xf0 + dw ARM_instruction_cmhs-instruction_handler + db 'cmle',0xf0 + dw ARM_instruction_cmle-instruction_handler + db 'cmlt',0xf0 + dw ARM_instruction_cmlt-instruction_handler + db 'cmnp',0xe0 + dw ARM_instruction_cmnp-instruction_handler + db 'cmpp',0xe0 + dw ARM_instruction_cmpp-instruction_handler + db 'cneg',0xf0 + dw ARM_instruction_cneg-instruction_handler + db 'cnfe',0xe0 + dw ARM_instruction_cnfe-instruction_handler + db 'cosd',0xe0 + dw ARM_instruction_cosd-instruction_handler + db 'cose',0xe0 + dw ARM_instruction_cose-instruction_handler + db 'coss',0xe0 + dw ARM_instruction_coss-instruction_handler + db 'csel',0xf0 + dw ARM_instruction_csel-instruction_handler + db 'cset',0xf0 + dw ARM_instruction_cset-instruction_handler + db 'data',0x00 + dw data_directive-instruction_handler + db 'drps',0xf0 + dw ARM_instruction_drps-instruction_handler + db 'dvfd',0xe0 + dw ARM_instruction_dvfd-instruction_handler + db 'dvfe',0xe0 + dw ARM_instruction_dvfe-instruction_handler + db 'dvfs',0xe0 + dw ARM_instruction_dvfs-instruction_handler + db 'else',0x00 + dw else_directive-instruction_handler + db 'eors',0xe1 + dw ARM_instruction_eor-instruction_handler + db 'eret',0xe0 + dw ARM_instruction_eret-instruction_handler + db 'expd',0xe0 + dw ARM_instruction_expd-instruction_handler + db 'expe',0xe0 + dw ARM_instruction_expe-instruction_handler + db 'exps',0xe0 + dw ARM_instruction_exps-instruction_handler + db 'extr',0xf0 + dw ARM_instruction_extr-instruction_handler + db 'fabd',0xf0 + dw ARM_instruction_fabd-instruction_handler + db 'fabs',0xf0 + dw ARM_instruction_fabs-instruction_handler + db 'fadd',0xf0 + dw ARM_instruction_fadd-instruction_handler + db 'fcmp',0xf0 + dw ARM_instruction_fcmp-instruction_handler + db 'fcvt',0xf0 + dw ARM_instruction_fcvt-instruction_handler + db 'fdiv',0xf0 + dw ARM_instruction_fdiv-instruction_handler + db 'fdvd',0xe0 + dw ARM_instruction_fdvd-instruction_handler + db 'fdve',0xe0 + dw ARM_instruction_fdve-instruction_handler + db 'fdvs',0xe0 + dw ARM_instruction_fdvs-instruction_handler + db 'fixm',0xe0 + dw ARM_instruction_fixm-instruction_handler + db 'fixp',0xe0 + dw ARM_instruction_fixp-instruction_handler + db 'fixz',0xe0 + dw ARM_instruction_fixz-instruction_handler + db 'fldd',0xe0 + dw ARM_instruction_fldd-instruction_handler + db 'flds',0xe0 + dw ARM_instruction_flds-instruction_handler + db 'fltd',0xe0 + dw ARM_instruction_fltd-instruction_handler + db 'flte',0xe0 + dw ARM_instruction_flte-instruction_handler + db 'flts',0xe0 + dw ARM_instruction_flts-instruction_handler + db 'fmax',0xf0 + dw ARM_instruction_fmax-instruction_handler + db 'fmin',0xf0 + dw ARM_instruction_fmin-instruction_handler + db 'fmla',0xf0 + dw ARM_instruction_fmla-instruction_handler + db 'fmld',0xe0 + dw ARM_instruction_fmld-instruction_handler + db 'fmle',0xe0 + dw ARM_instruction_fmle-instruction_handler + db 'fmls',0xe0 + dw ARM_instruction_fmls-instruction_handler + db 'fmov',0xf0 + dw ARM_instruction_fmov-instruction_handler + db 'fmrs',0xe0 + dw ARM_instruction_fmrs-instruction_handler + db 'fmrx',0xe0 + dw ARM_instruction_fmrx-instruction_handler + db 'fmsr',0xe0 + dw ARM_instruction_fmsr-instruction_handler + db 'fmul',0xf0 + dw ARM_instruction_fmul-instruction_handler + db 'fmxr',0xe0 + dw ARM_instruction_fmxr-instruction_handler + db 'fneg',0xf0 + dw ARM_instruction_fneg-instruction_handler + db 'frdd',0xe0 + dw ARM_instruction_frdd-instruction_handler + db 'frde',0xe0 + dw ARM_instruction_frde-instruction_handler + db 'frds',0xe0 + dw ARM_instruction_frds-instruction_handler + db 'fstd',0xe0 + dw ARM_instruction_fstd-instruction_handler + db 'fsts',0xe0 + dw ARM_instruction_fsts-instruction_handler + db 'fsub',0xf0 + dw ARM_instruction_fsub-instruction_handler + db 'hblp',0xe0 + dw ARM_instruction_hblp-instruction_handler + db 'hb~~',0x00 + dw ARM_instruction_hb-instruction_handler + db 'heap',0x00 + dw heap_directive-instruction_handler + db 'hint',0xf0 + dw ARM_instruction_hint-instruction_handler + db 'itee',0xf0 + dw ARM_instruction_itee-instruction_handler + db 'itet',0xf0 + dw ARM_instruction_itet-instruction_handler + db 'itte',0xf0 + dw ARM_instruction_itte-instruction_handler + db 'ittt',0xf0 + dw ARM_instruction_ittt-instruction_handler + db 'ld1r',0xf0 + dw ARM_instruction_ld1r-instruction_handler + db 'ld2r',0xf0 + dw ARM_instruction_ld2r-instruction_handler + db 'ld3r',0xf0 + dw ARM_instruction_ld3r-instruction_handler + db 'ld4r',0xf0 + dw ARM_instruction_ld4r-instruction_handler + db 'ldab',0xe0 + dw ARM_instruction_ldab-instruction_handler + db 'ldah',0xe0 + dw ARM_instruction_ldah-instruction_handler + db 'ldar',0xf0 + dw ARM_instruction_ldar-instruction_handler + db 'ldc2',0xe0 + dw ARM_instruction_ldc2-instruction_handler + db 'ldcl',0xe0 + dw ARM_instruction_ldcl-instruction_handler + db 'ldfd',0xe0 + dw ARM_instruction_ldfd-instruction_handler + db 'ldfe',0xe0 + dw ARM_instruction_ldfe-instruction_handler + db 'ldfp',0xe0 + dw ARM_instruction_ldfp-instruction_handler + db 'ldfs',0xe0 + dw ARM_instruction_ldfs-instruction_handler + db 'ldnp',0xf0 + dw ARM_instruction_ldnp-instruction_handler + db 'ldrb',0xe0 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrd',0xe0 + dw ARM_instruction_ldrd-instruction_handler + db 'ldrh',0xe0 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrt',0xe0 + dw ARM_instruction_ldrt-instruction_handler + db 'ldtr',0xf0 + dw ARM_instruction_ldtr-instruction_handler + db 'ldur',0xf0 + dw ARM_instruction_ldur-instruction_handler + db 'ldxp',0xf0 + dw ARM_instruction_ldxp-instruction_handler + db 'ldxr',0xf0 + dw ARM_instruction_ldxr-instruction_handler + db 'lgnd',0xe0 + dw ARM_instruction_lgnd-instruction_handler + db 'lgne',0xe0 + dw ARM_instruction_lgne-instruction_handler + db 'lgns',0xe0 + dw ARM_instruction_lgns-instruction_handler + db 'load',0x00 + dw load_directive-instruction_handler + db 'logd',0xe0 + dw ARM_instruction_logd-instruction_handler + db 'loge',0xe0 + dw ARM_instruction_loge-instruction_handler + db 'logs',0xe0 + dw ARM_instruction_logs-instruction_handler + db 'lsls',0xe1 + dw ARM_instruction_lsl-instruction_handler + db 'lslv',0xf0 + dw ARM_instruction_lslv-instruction_handler + db 'lsrs',0xe1 + dw ARM_instruction_lsr-instruction_handler + db 'lsrv',0xf0 + dw ARM_instruction_lsrv-instruction_handler + db 'madd',0xf0 + dw ARM_instruction_madd-instruction_handler + db 'mcr2',0xe0 + dw ARM_instruction_mcr2-instruction_handler + db 'mcrr',0xe0 + dw ARM_instruction_mcrr-instruction_handler + db 'mlas',0xe1 + dw ARM_instruction_mla-instruction_handler + db 'mneg',0xf0 + dw ARM_instruction_mneg-instruction_handler + db 'mnfd',0xe0 + dw ARM_instruction_mnfd-instruction_handler + db 'mnfe',0xe0 + dw ARM_instruction_mnfe-instruction_handler + db 'mnfs',0xe0 + dw ARM_instruction_mnfs-instruction_handler + db 'movi',0xf0 + dw ARM_instruction_movi-instruction_handler + db 'movk',0xf0 + dw ARM_instruction_movk-instruction_handler + db 'movn',0xf0 + dw ARM_instruction_movn-instruction_handler + db 'movs',0xe1 + dw ARM_instruction_mov-instruction_handler + db 'movt',0xe0 + dw ARM_instruction_movt-instruction_handler + db 'movw',0xe0 + dw ARM_instruction_movw-instruction_handler + db 'movz',0xf0 + dw ARM_instruction_movz-instruction_handler + db 'mrc2',0xe0 + dw ARM_instruction_mrc2-instruction_handler + db 'mrrc',0xe0 + dw ARM_instruction_mrrc-instruction_handler + db 'msub',0xf0 + dw ARM_instruction_msub-instruction_handler + db 'mufd',0xe0 + dw ARM_instruction_mufd-instruction_handler + db 'mufe',0xe0 + dw ARM_instruction_mufe-instruction_handler + db 'mufs',0xe0 + dw ARM_instruction_mufs-instruction_handler + db 'muls',0xe1 + dw ARM_instruction_mul-instruction_handler + db 'mvfd',0xe0 + dw ARM_instruction_mvfd-instruction_handler + db 'mvfe',0xe0 + dw ARM_instruction_mvfe-instruction_handler + db 'mvfs',0xe0 + dw ARM_instruction_mvfs-instruction_handler + db 'mvni',0xf0 + dw ARM_instruction_mvni-instruction_handler + db 'mvns',0xe1 + dw ARM_instruction_mvn-instruction_handler + db 'negs',0xe1 + dw ARM_instruction_neg-instruction_handler + db 'ngcs',0xf1 + dw ARM_instruction_ngc-instruction_handler + db 'nrmd',0xe0 + dw ARM_instruction_nrmd-instruction_handler + db 'nrme',0xe0 + dw ARM_instruction_nrme-instruction_handler + db 'nrms',0xe0 + dw ARM_instruction_nrms-instruction_handler + db 'orns',0xe1 + dw ARM_instruction_orn-instruction_handler + db 'orrs',0xe1 + dw ARM_instruction_orr-instruction_handler + db 'pldw',0xe0 + dw ARM_instruction_pldw-instruction_handler + db 'pmul',0xf0 + dw ARM_instruction_pmul-instruction_handler + db 'pold',0xe0 + dw ARM_instruction_pold-instruction_handler + db 'pole',0xe0 + dw ARM_instruction_pole-instruction_handler + db 'pols',0xe0 + dw ARM_instruction_pols-instruction_handler + db 'powd',0xe0 + dw ARM_instruction_powd-instruction_handler + db 'powe',0xe0 + dw ARM_instruction_powe-instruction_handler + db 'pows',0xe0 + dw ARM_instruction_pows-instruction_handler + db 'prfm',0xf0 + dw ARM_instruction_prfm-instruction_handler + db 'push',0xe0 + dw ARM_instruction_push-instruction_handler + db 'qadd',0xe0 + dw ARM_instruction_qadd-instruction_handler + db 'qasx',0xe0 + dw ARM_instruction_qasx-instruction_handler + db 'qsax',0xe0 + dw ARM_instruction_qsax-instruction_handler + db 'qsub',0xe0 + dw ARM_instruction_qsub-instruction_handler + db 'rbit',0xe0 + dw ARM_instruction_rbit-instruction_handler + db 'rdfd',0xe0 + dw ARM_instruction_rdfd-instruction_handler + db 'rdfe',0xe0 + dw ARM_instruction_rdfe-instruction_handler + db 'rdfs',0xe0 + dw ARM_instruction_rdfs-instruction_handler + db 'rmfd',0xe0 + dw ARM_instruction_rmfd-instruction_handler + db 'rmfe',0xe0 + dw ARM_instruction_rmfe-instruction_handler + db 'rmfs',0xe0 + dw ARM_instruction_rmfs-instruction_handler + db 'rndd',0xe0 + dw ARM_instruction_rndd-instruction_handler + db 'rnde',0xe0 + dw ARM_instruction_rnde-instruction_handler + db 'rnds',0xe0 + dw ARM_instruction_rnds-instruction_handler + db 'rors',0xe1 + dw ARM_instruction_ror-instruction_handler + db 'rorv',0xf0 + dw ARM_instruction_rorv-instruction_handler + db 'rpwd',0xe0 + dw ARM_instruction_rpwd-instruction_handler + db 'rpwe',0xe0 + dw ARM_instruction_rpwe-instruction_handler + db 'rpws',0xe0 + dw ARM_instruction_rpws-instruction_handler + db 'rrxs',0xe1 + dw ARM_instruction_rrx-instruction_handler + db 'rsbs',0xe1 + dw ARM_instruction_rsb-instruction_handler + db 'rscs',0xe1 + dw ARM_instruction_rsc-instruction_handler + db 'rsfd',0xe0 + dw ARM_instruction_rsfd-instruction_handler + db 'rsfe',0xe0 + dw ARM_instruction_rsfe-instruction_handler + db 'rsfs',0xe0 + dw ARM_instruction_rsfs-instruction_handler + db 'saba',0xf0 + dw ARM_instruction_saba-instruction_handler + db 'sabd',0xf0 + dw ARM_instruction_sabd-instruction_handler + db 'sasx',0xe0 + dw ARM_instruction_sasx-instruction_handler + db 'sbcs',0xe1 + dw ARM_instruction_sbc-instruction_handler + db 'sbfm',0xf0 + dw ARM_instruction_sbfm-instruction_handler + db 'sbfx',0xe0 + dw ARM_instruction_sbfx-instruction_handler + db 'sdiv',0xe0 + dw ARM_instruction_sdiv-instruction_handler + db 'sevl',0xe0 + dw ARM_instruction_sevl-instruction_handler + db 'shll',0xf0 + dw ARM_instruction_shll-instruction_handler + db 'shrn',0xf0 + dw ARM_instruction_shrn-instruction_handler + db 'sind',0xe0 + dw ARM_instruction_sind-instruction_handler + db 'sine',0xe0 + dw ARM_instruction_sine-instruction_handler + db 'sins',0xe0 + dw ARM_instruction_sins-instruction_handler + db 'smax',0xf0 + dw ARM_instruction_smax-instruction_handler + db 'smin',0xf0 + dw ARM_instruction_smin-instruction_handler + db 'smov',0xf0 + dw ARM_instruction_smov-instruction_handler + db 'sqtd',0xe0 + dw ARM_instruction_sqtd-instruction_handler + db 'sqte',0xe0 + dw ARM_instruction_sqte-instruction_handler + db 'sqts',0xe0 + dw ARM_instruction_sqts-instruction_handler + db 'ssat',0xe0 + dw ARM_instruction_ssat-instruction_handler + db 'ssax',0xe0 + dw ARM_instruction_ssax-instruction_handler + db 'sshl',0xf0 + dw ARM_instruction_sshl-instruction_handler + db 'sshr',0xf0 + dw ARM_instruction_sshr-instruction_handler + db 'ssra',0xf0 + dw ARM_instruction_ssra-instruction_handler + db 'stc2',0xe0 + dw ARM_instruction_stc2-instruction_handler + db 'stcl',0xe0 + dw ARM_instruction_stcl-instruction_handler + db 'stfd',0xe0 + dw ARM_instruction_stfd-instruction_handler + db 'stfe',0xe0 + dw ARM_instruction_stfe-instruction_handler + db 'stfp',0xe0 + dw ARM_instruction_stfp-instruction_handler + db 'stfs',0xe0 + dw ARM_instruction_stfs-instruction_handler + db 'stlb',0xe0 + dw ARM_instruction_stlb-instruction_handler + db 'stlh',0xe0 + dw ARM_instruction_stlh-instruction_handler + db 'stlr',0xf0 + dw ARM_instruction_stlr-instruction_handler + db 'stnp',0xf0 + dw ARM_instruction_stnp-instruction_handler + db 'strb',0xe0 + dw ARM_instruction_strb-instruction_handler + db 'strd',0xe0 + dw ARM_instruction_strd-instruction_handler + db 'strh',0xe0 + dw ARM_instruction_strh-instruction_handler + db 'strt',0xe0 + dw ARM_instruction_strt-instruction_handler + db 'sttr',0xf0 + dw ARM_instruction_sttr-instruction_handler + db 'stur',0xf0 + dw ARM_instruction_stur-instruction_handler + db 'stxp',0xf0 + dw ARM_instruction_stxp-instruction_handler + db 'stxr',0xf0 + dw ARM_instruction_stxr-instruction_handler + db 'subs',0xe1 + dw ARM_instruction_sub-instruction_handler + db 'subw',0xe0 + dw ARM_instruction_subw-instruction_handler + db 'sufd',0xe0 + dw ARM_instruction_sufd-instruction_handler + db 'sufe',0xe0 + dw ARM_instruction_sufe-instruction_handler + db 'sufs',0xe0 + dw ARM_instruction_sufs-instruction_handler + db 'swpb',0xe0 + dw ARM_instruction_swpb-instruction_handler + db 'sxtb',0xe0 + dw ARM_instruction_sxtb-instruction_handler + db 'sxth',0xe0 + dw ARM_instruction_sxth-instruction_handler + db 'sxtl',0xf0 + dw ARM_instruction_sxtl-instruction_handler + db 'sxtw',0xf0 + dw ARM_instruction_sxtw-instruction_handler + db 'sysl',0xf0 + dw ARM_instruction_sysl-instruction_handler + db 'tand',0xe0 + dw ARM_instruction_tand-instruction_handler + db 'tane',0xe0 + dw ARM_instruction_tane-instruction_handler + db 'tans',0xe0 + dw ARM_instruction_tans-instruction_handler + db 'tbnz',0xf0 + dw ARM_instruction_tbnz-instruction_handler + db 'teqp',0xe0 + dw ARM_instruction_teqp-instruction_handler + db 'tlbi',0xf0 + dw ARM_instruction_tlbi-instruction_handler + db 'tmcr',0xe0 + dw ARM_instruction_tmcr-instruction_handler + db 'tmia',0xe0 + dw ARM_instruction_tmia-instruction_handler + db 'tmrc',0xe0 + dw ARM_instruction_tmrc-instruction_handler + db 'trn1',0xf0 + dw ARM_instruction_trn1-instruction_handler + db 'trn2',0xf0 + dw ARM_instruction_trn2-instruction_handler + db 'tstp',0xe0 + dw ARM_instruction_tstp-instruction_handler + db 'uaba',0xf0 + dw ARM_instruction_uaba-instruction_handler + db 'uabd',0xf0 + dw ARM_instruction_uabd-instruction_handler + db 'uasx',0xe0 + dw ARM_instruction_uasx-instruction_handler + db 'ubfm',0xf0 + dw ARM_instruction_ubfm-instruction_handler + db 'ubfx',0xe0 + dw ARM_instruction_ubfx-instruction_handler + db 'udiv',0xe0 + dw ARM_instruction_udiv-instruction_handler + db 'umax',0xf0 + dw ARM_instruction_umax-instruction_handler + db 'umin',0xf0 + dw ARM_instruction_umin-instruction_handler + db 'umov',0xf0 + dw ARM_instruction_umov-instruction_handler + db 'urdd',0xe0 + dw ARM_instruction_urdd-instruction_handler + db 'urde',0xe0 + dw ARM_instruction_urde-instruction_handler + db 'urds',0xe0 + dw ARM_instruction_urds-instruction_handler + db 'usat',0xe0 + dw ARM_instruction_usat-instruction_handler + db 'usax',0xe0 + dw ARM_instruction_usax-instruction_handler + db 'ushl',0xf0 + dw ARM_instruction_ushl-instruction_handler + db 'ushr',0xf0 + dw ARM_instruction_ushr-instruction_handler + db 'usra',0xf0 + dw ARM_instruction_usra-instruction_handler + db 'uxtb',0xe0 + dw ARM_instruction_uxtb-instruction_handler + db 'uxth',0xe0 + dw ARM_instruction_uxth-instruction_handler + db 'uxtl',0xf0 + dw ARM_instruction_uxtl-instruction_handler + db 'uzp1',0xf0 + dw ARM_instruction_uzp1-instruction_handler + db 'uzp2',0xf0 + dw ARM_instruction_uzp2-instruction_handler + db 'vand',0xe0 + dw ARM_instruction_vand-instruction_handler + db 'vbic',0xe0 + dw ARM_instruction_vbic-instruction_handler + db 'vbif',0xe0 + dw ARM_instruction_vbif-instruction_handler + db 'vbit',0xe0 + dw ARM_instruction_vbit-instruction_handler + db 'vbsl',0xe0 + dw ARM_instruction_vbsl-instruction_handler + db 'veor',0xe0 + dw ARM_instruction_veor-instruction_handler + db 'vldm',0xe0 + dw ARM_instruction_vldm-instruction_handler + db 'vldr',0xe0 + dw ARM_instruction_vldr-instruction_handler + db 'vmov',0xe0 + dw ARM_instruction_vmov-instruction_handler + db 'vmrs',0xe0 + dw ARM_instruction_vmrs-instruction_handler + db 'vmsr',0xe0 + dw ARM_instruction_vmsr-instruction_handler + db 'vmvn',0xe0 + dw ARM_instruction_vmvn-instruction_handler + db 'vorn',0xe0 + dw ARM_instruction_vorn-instruction_handler + db 'vorr',0xe0 + dw ARM_instruction_vorr-instruction_handler + db 'vpop',0xe0 + dw ARM_instruction_vpop-instruction_handler + db 'vstm',0xe0 + dw ARM_instruction_vstm-instruction_handler + db 'vstr',0xe0 + dw ARM_instruction_vstr-instruction_handler + db 'vswp',0xe0 + dw ARM_instruction_vswp-instruction_handler + db 'wand',0xe0 + dw ARM_instruction_wand-instruction_handler + db 'wmov',0xe0 + dw ARM_instruction_wmov-instruction_handler + db 'wxor',0xe0 + dw ARM_instruction_wxor-instruction_handler + db 'xtn2',0xf0 + dw ARM_instruction_xtn2-instruction_handler + db 'zip1',0xf0 + dw ARM_instruction_zip1-instruction_handler + db 'zip2',0xf0 + dw ARM_instruction_zip2-instruction_handler + db 0 +instructions_5: + db 'absdm',0xe0 + dw ARM_instruction_absdm-instruction_handler + db 'absdp',0xe0 + dw ARM_instruction_absdp-instruction_handler + db 'absdz',0xe0 + dw ARM_instruction_absdz-instruction_handler + db 'absem',0xe0 + dw ARM_instruction_absem-instruction_handler + db 'absep',0xe0 + dw ARM_instruction_absep-instruction_handler + db 'absez',0xe0 + dw ARM_instruction_absez-instruction_handler + db 'abssm',0xe0 + dw ARM_instruction_abssm-instruction_handler + db 'abssp',0xe0 + dw ARM_instruction_abssp-instruction_handler + db 'abssz',0xe0 + dw ARM_instruction_abssz-instruction_handler + db 'acsdm',0xe0 + dw ARM_instruction_acsdm-instruction_handler + db 'acsdp',0xe0 + dw ARM_instruction_acsdp-instruction_handler + db 'acsdz',0xe0 + dw ARM_instruction_acsdz-instruction_handler + db 'acsem',0xe0 + dw ARM_instruction_acsem-instruction_handler + db 'acsep',0xe0 + dw ARM_instruction_acsep-instruction_handler + db 'acsez',0xe0 + dw ARM_instruction_acsez-instruction_handler + db 'acssm',0xe0 + dw ARM_instruction_acssm-instruction_handler + db 'acssp',0xe0 + dw ARM_instruction_acssp-instruction_handler + db 'acssz',0xe0 + dw ARM_instruction_acssz-instruction_handler + db 'adc.n',0xe4 + dw ARM_instruction_adc-instruction_handler + db 'adc.w',0xe2 + dw ARM_instruction_adc-instruction_handler + db 'adc~~',0x00 + dw ARM_instruction_adc-instruction_handler + db 'add.n',0xe4 + dw ARM_instruction_add-instruction_handler + db 'add.w',0xe2 + dw ARM_instruction_add-instruction_handler + db 'addhn',0xf0 + dw ARM_instruction_addhn-instruction_handler + db 'add~~',0x00 + dw ARM_instruction_add-instruction_handler + db 'adfdm',0xe0 + dw ARM_instruction_adfdm-instruction_handler + db 'adfdp',0xe0 + dw ARM_instruction_adfdp-instruction_handler + db 'adfdz',0xe0 + dw ARM_instruction_adfdz-instruction_handler + db 'adfem',0xe0 + dw ARM_instruction_adfem-instruction_handler + db 'adfep',0xe0 + dw ARM_instruction_adfep-instruction_handler + db 'adfez',0xe0 + dw ARM_instruction_adfez-instruction_handler + db 'adfsm',0xe0 + dw ARM_instruction_adfsm-instruction_handler + db 'adfsp',0xe0 + dw ARM_instruction_adfsp-instruction_handler + db 'adfsz',0xe0 + dw ARM_instruction_adfsz-instruction_handler + db 'adr.n',0xe4 + dw ARM_instruction_adr-instruction_handler + db 'adr.w',0xe2 + dw ARM_instruction_adr-instruction_handler + db 'adr~~',0x00 + dw ARM_instruction_adr-instruction_handler + db 'aesmc',0xf0 + dw ARM_instruction_aesmc-instruction_handler + db 'align',0x00 + dw align_directive-instruction_handler + db 'and.n',0xe4 + dw ARM_instruction_and-instruction_handler + db 'and.w',0xe2 + dw ARM_instruction_and-instruction_handler + db 'and~~',0x00 + dw ARM_instruction_and-instruction_handler + db 'asndm',0xe0 + dw ARM_instruction_asndm-instruction_handler + db 'asndp',0xe0 + dw ARM_instruction_asndp-instruction_handler + db 'asndz',0xe0 + dw ARM_instruction_asndz-instruction_handler + db 'asnem',0xe0 + dw ARM_instruction_asnem-instruction_handler + db 'asnep',0xe0 + dw ARM_instruction_asnep-instruction_handler + db 'asnez',0xe0 + dw ARM_instruction_asnez-instruction_handler + db 'asnsm',0xe0 + dw ARM_instruction_asnsm-instruction_handler + db 'asnsp',0xe0 + dw ARM_instruction_asnsp-instruction_handler + db 'asnsz',0xe0 + dw ARM_instruction_asnsz-instruction_handler + db 'asr.n',0xe4 + dw ARM_instruction_asr-instruction_handler + db 'asr.w',0xe2 + dw ARM_instruction_asr-instruction_handler + db 'asr~~',0x00 + dw ARM_instruction_asr-instruction_handler + db 'atndm',0xe0 + dw ARM_instruction_atndm-instruction_handler + db 'atndp',0xe0 + dw ARM_instruction_atndp-instruction_handler + db 'atndz',0xe0 + dw ARM_instruction_atndz-instruction_handler + db 'atnem',0xe0 + dw ARM_instruction_atnem-instruction_handler + db 'atnep',0xe0 + dw ARM_instruction_atnep-instruction_handler + db 'atnez',0xe0 + dw ARM_instruction_atnez-instruction_handler + db 'atnsm',0xe0 + dw ARM_instruction_atnsm-instruction_handler + db 'atnsp',0xe0 + dw ARM_instruction_atnsp-instruction_handler + db 'atnsz',0xe0 + dw ARM_instruction_atnsz-instruction_handler + db 'bfc~~',0x00 + dw ARM_instruction_bfc-instruction_handler + db 'bfi~~',0x00 + dw ARM_instruction_bfi-instruction_handler + db 'bfxil',0xf0 + dw ARM_instruction_bfxil-instruction_handler + db 'bic.n',0xe4 + dw ARM_instruction_bic-instruction_handler + db 'bic.w',0xe2 + dw ARM_instruction_bic-instruction_handler + db 'bic~~',0x00 + dw ARM_instruction_bic-instruction_handler + db 'blx.n',0xe4 + dw ARM_instruction_blx-instruction_handler + db 'blx.w',0xe2 + dw ARM_instruction_blx-instruction_handler + db 'blx~~',0x00 + dw ARM_instruction_blx-instruction_handler + db 'break',0x00 + dw break_directive-instruction_handler + db 'bxj~~',0x00 + dw ARM_instruction_bxj-instruction_handler + db 'b~~.n',0x04 + dw ARM_instruction_b-instruction_handler + db 'b~~.w',0x02 + dw ARM_instruction_b-instruction_handler + db 'cbz.n',0xf4 + dw ARM_instruction_cbz-instruction_handler + db 'cbz.w',0xf2 + dw ARM_instruction_cbz-instruction_handler + db 'cdp~~',0x00 + dw ARM_instruction_cdp-instruction_handler + db 'clrex',0xe0 + dw ARM_instruction_clrex-instruction_handler + db 'clz~~',0x00 + dw ARM_instruction_clz-instruction_handler + db 'cmf~~',0x00 + dw ARM_instruction_cmf-instruction_handler + db 'cmn.n',0xe4 + dw ARM_instruction_cmn-instruction_handler + db 'cmn.w',0xe2 + dw ARM_instruction_cmn-instruction_handler + db 'cmn~~',0x00 + dw ARM_instruction_cmn-instruction_handler + db 'cmp.n',0xe4 + dw ARM_instruction_cmp-instruction_handler + db 'cmp.w',0xe2 + dw ARM_instruction_cmp-instruction_handler + db 'cmp~~',0x00 + dw ARM_instruction_cmp-instruction_handler + db 'cmtst',0xf0 + dw ARM_instruction_cmtst-instruction_handler + db 'cnf~~',0x00 + dw ARM_instruction_cnf-instruction_handler + db 'cosdm',0xe0 + dw ARM_instruction_cosdm-instruction_handler + db 'cosdp',0xe0 + dw ARM_instruction_cosdp-instruction_handler + db 'cosdz',0xe0 + dw ARM_instruction_cosdz-instruction_handler + db 'cosem',0xe0 + dw ARM_instruction_cosem-instruction_handler + db 'cosep',0xe0 + dw ARM_instruction_cosep-instruction_handler + db 'cosez',0xe0 + dw ARM_instruction_cosez-instruction_handler + db 'cossm',0xe0 + dw ARM_instruction_cossm-instruction_handler + db 'cossp',0xe0 + dw ARM_instruction_cossp-instruction_handler + db 'cossz',0xe0 + dw ARM_instruction_cossz-instruction_handler + db 'cps.n',0xf4 + dw ARM_instruction_cps-instruction_handler + db 'cps.w',0xf2 + dw ARM_instruction_cps-instruction_handler + db 'cpsid',0xf0 + dw ARM_instruction_cpsid-instruction_handler + db 'cpsie',0xf0 + dw ARM_instruction_cpsie-instruction_handler + db 'cpy.n',0xe4 + dw ARM_instruction_cpy-instruction_handler + db 'cpy.w',0xe2 + dw ARM_instruction_cpy-instruction_handler + db 'cpy~~',0x00 + dw ARM_instruction_cpy-instruction_handler + db 'crc32',0xf0 + dw ARM_instruction_crc32-instruction_handler + db 'csetm',0xf0 + dw ARM_instruction_csetm-instruction_handler + db 'csinc',0xf0 + dw ARM_instruction_csinc-instruction_handler + db 'csinv',0xf0 + dw ARM_instruction_csinv-instruction_handler + db 'csneg',0xf0 + dw ARM_instruction_csneg-instruction_handler + db 'dbg~~',0x00 + dw ARM_instruction_dbg-instruction_handler + db 'dcps1',0xe0 + dw ARM_instruction_dcps1-instruction_handler + db 'dcps2',0xe0 + dw ARM_instruction_dcps2-instruction_handler + db 'dcps3',0xe0 + dw ARM_instruction_dcps3-instruction_handler + db 'dvfdm',0xe0 + dw ARM_instruction_dvfdm-instruction_handler + db 'dvfdp',0xe0 + dw ARM_instruction_dvfdp-instruction_handler + db 'dvfdz',0xe0 + dw ARM_instruction_dvfdz-instruction_handler + db 'dvfem',0xe0 + dw ARM_instruction_dvfem-instruction_handler + db 'dvfep',0xe0 + dw ARM_instruction_dvfep-instruction_handler + db 'dvfez',0xe0 + dw ARM_instruction_dvfez-instruction_handler + db 'dvfsm',0xe0 + dw ARM_instruction_dvfsm-instruction_handler + db 'dvfsp',0xe0 + dw ARM_instruction_dvfsp-instruction_handler + db 'dvfsz',0xe0 + dw ARM_instruction_dvfsz-instruction_handler + db 'entry',0x00 + dw entry_directive-instruction_handler + db 'eor.n',0xe4 + dw ARM_instruction_eor-instruction_handler + db 'eor.w',0xe2 + dw ARM_instruction_eor-instruction_handler + db 'eor~~',0x00 + dw ARM_instruction_eor-instruction_handler + db 'expdm',0xe0 + dw ARM_instruction_expdm-instruction_handler + db 'expdp',0xe0 + dw ARM_instruction_expdp-instruction_handler + db 'expdz',0xe0 + dw ARM_instruction_expdz-instruction_handler + db 'expem',0xe0 + dw ARM_instruction_expem-instruction_handler + db 'expep',0xe0 + dw ARM_instruction_expep-instruction_handler + db 'expez',0xe0 + dw ARM_instruction_expez-instruction_handler + db 'expsm',0xe0 + dw ARM_instruction_expsm-instruction_handler + db 'expsp',0xe0 + dw ARM_instruction_expsp-instruction_handler + db 'expsz',0xe0 + dw ARM_instruction_expsz-instruction_handler + db 'extrn',0x00 + dw extrn_directive-instruction_handler + db 'fabsd',0xe0 + dw ARM_instruction_fabsd-instruction_handler + db 'fabss',0xe0 + dw ARM_instruction_fabss-instruction_handler + db 'facge',0xf0 + dw ARM_instruction_facge-instruction_handler + db 'facgt',0xf0 + dw ARM_instruction_facgt-instruction_handler + db 'faddd',0xe0 + dw ARM_instruction_faddd-instruction_handler + db 'faddp',0xf0 + dw ARM_instruction_faddp-instruction_handler + db 'fadds',0xe0 + dw ARM_instruction_fadds-instruction_handler + db 'fccmp',0xf0 + dw ARM_instruction_fccmp-instruction_handler + db 'fcmeq',0xf0 + dw ARM_instruction_fcmeq-instruction_handler + db 'fcmge',0xf0 + dw ARM_instruction_fcmge-instruction_handler + db 'fcmgt',0xf0 + dw ARM_instruction_fcmgt-instruction_handler + db 'fcmle',0xf0 + dw ARM_instruction_fcmle-instruction_handler + db 'fcmlt',0xf0 + dw ARM_instruction_fcmlt-instruction_handler + db 'fcmpd',0xe0 + dw ARM_instruction_fcmpd-instruction_handler + db 'fcmpe',0xf0 + dw ARM_instruction_fcmpe-instruction_handler + db 'fcmps',0xe0 + dw ARM_instruction_fcmps-instruction_handler + db 'fcpyd',0xe0 + dw ARM_instruction_fcpyd-instruction_handler + db 'fcpys',0xe0 + dw ARM_instruction_fcpys-instruction_handler + db 'fcsel',0xf0 + dw ARM_instruction_fcsel-instruction_handler + db 'fcvtl',0xf0 + dw ARM_instruction_fcvtl-instruction_handler + db 'fcvtn',0xf0 + dw ARM_instruction_fcvtn-instruction_handler + db 'fdivd',0xe0 + dw ARM_instruction_fdivd-instruction_handler + db 'fdivs',0xe0 + dw ARM_instruction_fdivs-instruction_handler + db 'fdvdm',0xe0 + dw ARM_instruction_fdvdm-instruction_handler + db 'fdvdp',0xe0 + dw ARM_instruction_fdvdp-instruction_handler + db 'fdvdz',0xe0 + dw ARM_instruction_fdvdz-instruction_handler + db 'fdvem',0xe0 + dw ARM_instruction_fdvem-instruction_handler + db 'fdvep',0xe0 + dw ARM_instruction_fdvep-instruction_handler + db 'fdvez',0xe0 + dw ARM_instruction_fdvez-instruction_handler + db 'fdvsm',0xe0 + dw ARM_instruction_fdvsm-instruction_handler + db 'fdvsp',0xe0 + dw ARM_instruction_fdvsp-instruction_handler + db 'fdvsz',0xe0 + dw ARM_instruction_fdvsz-instruction_handler + db 'fix~~',0x00 + dw ARM_instruction_fix-instruction_handler + db 'fldmd',0xe0 + dw ARM_instruction_fldmd-instruction_handler + db 'fldms',0xe0 + dw ARM_instruction_fldms-instruction_handler + db 'fldmx',0xe0 + dw ARM_instruction_fldmx-instruction_handler + db 'fltdm',0xe0 + dw ARM_instruction_fltdm-instruction_handler + db 'fltdp',0xe0 + dw ARM_instruction_fltdp-instruction_handler + db 'fltdz',0xe0 + dw ARM_instruction_fltdz-instruction_handler + db 'fltem',0xe0 + dw ARM_instruction_fltem-instruction_handler + db 'fltep',0xe0 + dw ARM_instruction_fltep-instruction_handler + db 'fltez',0xe0 + dw ARM_instruction_fltez-instruction_handler + db 'fltsm',0xe0 + dw ARM_instruction_fltsm-instruction_handler + db 'fltsp',0xe0 + dw ARM_instruction_fltsp-instruction_handler + db 'fltsz',0xe0 + dw ARM_instruction_fltsz-instruction_handler + db 'fmacd',0xe0 + dw ARM_instruction_fmacd-instruction_handler + db 'fmacs',0xe0 + dw ARM_instruction_fmacs-instruction_handler + db 'fmadd',0xf0 + dw ARM_instruction_fmadd-instruction_handler + db 'fmaxp',0xf0 + dw ARM_instruction_fmaxp-instruction_handler + db 'fmaxv',0xf0 + dw ARM_instruction_fmaxv-instruction_handler + db 'fmdhr',0xe0 + dw ARM_instruction_fmdhr-instruction_handler + db 'fmdlr',0xe0 + dw ARM_instruction_fmdlr-instruction_handler + db 'fmdrr',0xe0 + dw ARM_instruction_fmdrr-instruction_handler + db 'fminp',0xf0 + dw ARM_instruction_fminp-instruction_handler + db 'fminv',0xf0 + dw ARM_instruction_fminv-instruction_handler + db 'fmldm',0xe0 + dw ARM_instruction_fmldm-instruction_handler + db 'fmldp',0xe0 + dw ARM_instruction_fmldp-instruction_handler + db 'fmldz',0xe0 + dw ARM_instruction_fmldz-instruction_handler + db 'fmlem',0xe0 + dw ARM_instruction_fmlem-instruction_handler + db 'fmlep',0xe0 + dw ARM_instruction_fmlep-instruction_handler + db 'fmlez',0xe0 + dw ARM_instruction_fmlez-instruction_handler + db 'fmlsm',0xe0 + dw ARM_instruction_fmlsm-instruction_handler + db 'fmlsp',0xe0 + dw ARM_instruction_fmlsp-instruction_handler + db 'fmlsz',0xe0 + dw ARM_instruction_fmlsz-instruction_handler + db 'fmrdh',0xe0 + dw ARM_instruction_fmrdh-instruction_handler + db 'fmrdl',0xe0 + dw ARM_instruction_fmrdl-instruction_handler + db 'fmrrd',0xe0 + dw ARM_instruction_fmrrd-instruction_handler + db 'fmrrs',0xe0 + dw ARM_instruction_fmrrs-instruction_handler + db 'fmscd',0xe0 + dw ARM_instruction_fmscd-instruction_handler + db 'fmscs',0xe0 + dw ARM_instruction_fmscs-instruction_handler + db 'fmsrr',0xe0 + dw ARM_instruction_fmsrr-instruction_handler + db 'fmsub',0xf0 + dw ARM_instruction_fmsub-instruction_handler + db 'fmuld',0xe0 + dw ARM_instruction_fmuld-instruction_handler + db 'fmuls',0xe0 + dw ARM_instruction_fmuls-instruction_handler + db 'fmulx',0xf0 + dw ARM_instruction_fmulx-instruction_handler + db 'fnegd',0xe0 + dw ARM_instruction_fnegd-instruction_handler + db 'fnegs',0xe0 + dw ARM_instruction_fnegs-instruction_handler + db 'fnmul',0xf0 + dw ARM_instruction_fnmul-instruction_handler + db 'frddm',0xe0 + dw ARM_instruction_frddm-instruction_handler + db 'frddp',0xe0 + dw ARM_instruction_frddp-instruction_handler + db 'frddz',0xe0 + dw ARM_instruction_frddz-instruction_handler + db 'frdem',0xe0 + dw ARM_instruction_frdem-instruction_handler + db 'frdep',0xe0 + dw ARM_instruction_frdep-instruction_handler + db 'frdez',0xe0 + dw ARM_instruction_frdez-instruction_handler + db 'frdsm',0xe0 + dw ARM_instruction_frdsm-instruction_handler + db 'frdsp',0xe0 + dw ARM_instruction_frdsp-instruction_handler + db 'frdsz',0xe0 + dw ARM_instruction_frdsz-instruction_handler + db 'fsqrt',0xf0 + dw ARM_instruction_fsqrt-instruction_handler + db 'fstmd',0xe0 + dw ARM_instruction_fstmd-instruction_handler + db 'fstms',0xe0 + dw ARM_instruction_fstms-instruction_handler + db 'fstmx',0xe0 + dw ARM_instruction_fstmx-instruction_handler + db 'fsubd',0xe0 + dw ARM_instruction_fsubd-instruction_handler + db 'fsubs',0xe0 + dw ARM_instruction_fsubs-instruction_handler + db 'hbl~~',0x00 + dw ARM_instruction_hbl-instruction_handler + db 'hbp~~',0x00 + dw ARM_instruction_hbp-instruction_handler + db 'iteee',0xf0 + dw ARM_instruction_iteee-instruction_handler + db 'iteet',0xf0 + dw ARM_instruction_iteet-instruction_handler + db 'itete',0xf0 + dw ARM_instruction_itete-instruction_handler + db 'itett',0xf0 + dw ARM_instruction_itett-instruction_handler + db 'ittee',0xf0 + dw ARM_instruction_ittee-instruction_handler + db 'ittet',0xf0 + dw ARM_instruction_ittet-instruction_handler + db 'ittte',0xf0 + dw ARM_instruction_ittte-instruction_handler + db 'itttt',0xf0 + dw ARM_instruction_itttt-instruction_handler + db 'label',0x00 + dw label_directive-instruction_handler + db 'ldaex',0xe0 + dw ARM_instruction_ldaex-instruction_handler + db 'ldarb',0xf0 + dw ARM_instruction_ldarb-instruction_handler + db 'ldarh',0xf0 + dw ARM_instruction_ldarh-instruction_handler + db 'ldaxp',0xf0 + dw ARM_instruction_ldaxp-instruction_handler + db 'ldaxr',0xf0 + dw ARM_instruction_ldaxr-instruction_handler + db 'lda~~',0x00 + dw ARM_instruction_lda-instruction_handler + db 'ldc2l',0xe0 + dw ARM_instruction_ldc2l-instruction_handler + db 'ldc~~',0x00 + dw ARM_instruction_ldc-instruction_handler + db 'ldm.n',0xe4 + dw ARM_instruction_ldm-instruction_handler + db 'ldm.w',0xe2 + dw ARM_instruction_ldm-instruction_handler + db 'ldmda',0xe0 + dw ARM_instruction_ldmda-instruction_handler + db 'ldmdb',0xe0 + dw ARM_instruction_ldmdb-instruction_handler + db 'ldmea',0xe0 + dw ARM_instruction_ldmea-instruction_handler + db 'ldmed',0xe0 + dw ARM_instruction_ldmed-instruction_handler + db 'ldmfa',0xe0 + dw ARM_instruction_ldmfa-instruction_handler + db 'ldmfd',0xe0 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmia',0xe0 + dw ARM_instruction_ldmia-instruction_handler + db 'ldmib',0xe0 + dw ARM_instruction_ldmib-instruction_handler + db 'ldm~~',0x00 + dw ARM_instruction_ldm-instruction_handler + db 'ldpsw',0xf0 + dw ARM_instruction_ldpsw-instruction_handler + db 'ldr.n',0xe4 + dw ARM_instruction_ldr-instruction_handler + db 'ldr.w',0xe2 + dw ARM_instruction_ldr-instruction_handler + db 'ldrbt',0xe0 + dw ARM_instruction_ldrbt-instruction_handler + db 'ldrex',0xe0 + dw ARM_instruction_ldrex-instruction_handler + db 'ldrht',0xe0 + dw ARM_instruction_ldrht-instruction_handler + db 'ldrsb',0xe0 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsh',0xe0 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldrsw',0xf0 + dw ARM_instruction_ldrsw-instruction_handler + db 'ldr~~',0x00 + dw ARM_instruction_ldr-instruction_handler + db 'ldtrb',0xf0 + dw ARM_instruction_ldtrb-instruction_handler + db 'ldtrh',0xf0 + dw ARM_instruction_ldtrh-instruction_handler + db 'ldurb',0xf0 + dw ARM_instruction_ldurb-instruction_handler + db 'ldurh',0xf0 + dw ARM_instruction_ldurh-instruction_handler + db 'ldxrb',0xf0 + dw ARM_instruction_ldxrb-instruction_handler + db 'ldxrh',0xf0 + dw ARM_instruction_ldxrh-instruction_handler + db 'lfmea',0xe0 + dw ARM_instruction_lfmea-instruction_handler + db 'lfmfd',0xe0 + dw ARM_instruction_lfmfd-instruction_handler + db 'lfm~~',0x00 + dw ARM_instruction_lfm-instruction_handler + db 'lgndm',0xe0 + dw ARM_instruction_lgndm-instruction_handler + db 'lgndp',0xe0 + dw ARM_instruction_lgndp-instruction_handler + db 'lgndz',0xe0 + dw ARM_instruction_lgndz-instruction_handler + db 'lgnem',0xe0 + dw ARM_instruction_lgnem-instruction_handler + db 'lgnep',0xe0 + dw ARM_instruction_lgnep-instruction_handler + db 'lgnez',0xe0 + dw ARM_instruction_lgnez-instruction_handler + db 'lgnsm',0xe0 + dw ARM_instruction_lgnsm-instruction_handler + db 'lgnsp',0xe0 + dw ARM_instruction_lgnsp-instruction_handler + db 'lgnsz',0xe0 + dw ARM_instruction_lgnsz-instruction_handler + db 'logdm',0xe0 + dw ARM_instruction_logdm-instruction_handler + db 'logdp',0xe0 + dw ARM_instruction_logdp-instruction_handler + db 'logdz',0xe0 + dw ARM_instruction_logdz-instruction_handler + db 'logem',0xe0 + dw ARM_instruction_logem-instruction_handler + db 'logep',0xe0 + dw ARM_instruction_logep-instruction_handler + db 'logez',0xe0 + dw ARM_instruction_logez-instruction_handler + db 'logsm',0xe0 + dw ARM_instruction_logsm-instruction_handler + db 'logsp',0xe0 + dw ARM_instruction_logsp-instruction_handler + db 'logsz',0xe0 + dw ARM_instruction_logsz-instruction_handler + db 'lsl.n',0xe4 + dw ARM_instruction_lsl-instruction_handler + db 'lsl.w',0xe2 + dw ARM_instruction_lsl-instruction_handler + db 'lsl~~',0x00 + dw ARM_instruction_lsl-instruction_handler + db 'lsr.n',0xe4 + dw ARM_instruction_lsr-instruction_handler + db 'lsr.w',0xe2 + dw ARM_instruction_lsr-instruction_handler + db 'lsr~~',0x00 + dw ARM_instruction_lsr-instruction_handler + db 'mar~~',0x00 + dw ARM_instruction_mar-instruction_handler + db 'mcrr2',0xe0 + dw ARM_instruction_mcrr2-instruction_handler + db 'mcr~~',0x00 + dw ARM_instruction_mcr-instruction_handler + db 'miabb',0xe0 + dw ARM_instruction_miabb-instruction_handler + db 'miabt',0xe0 + dw ARM_instruction_miabt-instruction_handler + db 'miaph',0xe0 + dw ARM_instruction_miaph-instruction_handler + db 'miatb',0xe0 + dw ARM_instruction_miatb-instruction_handler + db 'miatt',0xe0 + dw ARM_instruction_miatt-instruction_handler + db 'mia~~',0x00 + dw ARM_instruction_mia-instruction_handler + db 'mla~~',0x00 + dw ARM_instruction_mla-instruction_handler + db 'mls~~',0x00 + dw ARM_instruction_mls-instruction_handler + db 'mnfdm',0xe0 + dw ARM_instruction_mnfdm-instruction_handler + db 'mnfdp',0xe0 + dw ARM_instruction_mnfdp-instruction_handler + db 'mnfdz',0xe0 + dw ARM_instruction_mnfdz-instruction_handler + db 'mnfem',0xe0 + dw ARM_instruction_mnfem-instruction_handler + db 'mnfep',0xe0 + dw ARM_instruction_mnfep-instruction_handler + db 'mnfez',0xe0 + dw ARM_instruction_mnfez-instruction_handler + db 'mnfsm',0xe0 + dw ARM_instruction_mnfsm-instruction_handler + db 'mnfsp',0xe0 + dw ARM_instruction_mnfsp-instruction_handler + db 'mnfsz',0xe0 + dw ARM_instruction_mnfsz-instruction_handler + db 'mov.n',0xe4 + dw ARM_instruction_mov-instruction_handler + db 'mov.w',0xe2 + dw ARM_instruction_mov-instruction_handler + db 'mov~~',0x00 + dw ARM_instruction_mov-instruction_handler + db 'mra~~',0x00 + dw ARM_instruction_mra-instruction_handler + db 'mrc~~',0x00 + dw ARM_instruction_mrc-instruction_handler + db 'mrrc2',0xe0 + dw ARM_instruction_mrrc2-instruction_handler + db 'mrs~~',0x00 + dw ARM_instruction_mrs-instruction_handler + db 'msr~~',0x00 + dw ARM_instruction_msr-instruction_handler + db 'mufdm',0xe0 + dw ARM_instruction_mufdm-instruction_handler + db 'mufdp',0xe0 + dw ARM_instruction_mufdp-instruction_handler + db 'mufdz',0xe0 + dw ARM_instruction_mufdz-instruction_handler + db 'mufem',0xe0 + dw ARM_instruction_mufem-instruction_handler + db 'mufep',0xe0 + dw ARM_instruction_mufep-instruction_handler + db 'mufez',0xe0 + dw ARM_instruction_mufez-instruction_handler + db 'mufsm',0xe0 + dw ARM_instruction_mufsm-instruction_handler + db 'mufsp',0xe0 + dw ARM_instruction_mufsp-instruction_handler + db 'mufsz',0xe0 + dw ARM_instruction_mufsz-instruction_handler + db 'mul.n',0xe4 + dw ARM_instruction_mul-instruction_handler + db 'mul.w',0xe2 + dw ARM_instruction_mul-instruction_handler + db 'mul~~',0x00 + dw ARM_instruction_mul-instruction_handler + db 'mvfdm',0xe0 + dw ARM_instruction_mvfdm-instruction_handler + db 'mvfdp',0xe0 + dw ARM_instruction_mvfdp-instruction_handler + db 'mvfdz',0xe0 + dw ARM_instruction_mvfdz-instruction_handler + db 'mvfem',0xe0 + dw ARM_instruction_mvfem-instruction_handler + db 'mvfep',0xe0 + dw ARM_instruction_mvfep-instruction_handler + db 'mvfez',0xe0 + dw ARM_instruction_mvfez-instruction_handler + db 'mvfsm',0xe0 + dw ARM_instruction_mvfsm-instruction_handler + db 'mvfsp',0xe0 + dw ARM_instruction_mvfsp-instruction_handler + db 'mvfsz',0xe0 + dw ARM_instruction_mvfsz-instruction_handler + db 'mvn.n',0xe4 + dw ARM_instruction_mvn-instruction_handler + db 'mvn.w',0xe2 + dw ARM_instruction_mvn-instruction_handler + db 'mvn~~',0x00 + dw ARM_instruction_mvn-instruction_handler + db 'neg.n',0xe4 + dw ARM_instruction_neg-instruction_handler + db 'neg.w',0xe2 + dw ARM_instruction_neg-instruction_handler + db 'neg~~',0x00 + dw ARM_instruction_neg-instruction_handler + db 'nop.n',0xe4 + dw ARM_instruction_nop-instruction_handler + db 'nop.w',0xe2 + dw ARM_instruction_nop-instruction_handler + db 'nop~~',0x00 + dw ARM_instruction_nop-instruction_handler + db 'nrmdm',0xe0 + dw ARM_instruction_nrmdm-instruction_handler + db 'nrmdp',0xe0 + dw ARM_instruction_nrmdp-instruction_handler + db 'nrmdz',0xe0 + dw ARM_instruction_nrmdz-instruction_handler + db 'nrmem',0xe0 + dw ARM_instruction_nrmem-instruction_handler + db 'nrmep',0xe0 + dw ARM_instruction_nrmep-instruction_handler + db 'nrmez',0xe0 + dw ARM_instruction_nrmez-instruction_handler + db 'nrmsm',0xe0 + dw ARM_instruction_nrmsm-instruction_handler + db 'nrmsp',0xe0 + dw ARM_instruction_nrmsp-instruction_handler + db 'nrmsz',0xe0 + dw ARM_instruction_nrmsz-instruction_handler + db 'orn~~',0x00 + dw ARM_instruction_orn-instruction_handler + db 'orr.n',0xe4 + dw ARM_instruction_orr-instruction_handler + db 'orr.w',0xe2 + dw ARM_instruction_orr-instruction_handler + db 'orr~~',0x00 + dw ARM_instruction_orr-instruction_handler + db 'pkhbt',0xe0 + dw ARM_instruction_pkhbt-instruction_handler + db 'pkhtb',0xe0 + dw ARM_instruction_pkhtb-instruction_handler + db 'pld~~',0x00 + dw ARM_instruction_pld-instruction_handler + db 'pli~~',0x00 + dw ARM_instruction_pli-instruction_handler + db 'pmull',0xf0 + dw ARM_instruction_pmull-instruction_handler + db 'poldm',0xe0 + dw ARM_instruction_poldm-instruction_handler + db 'poldp',0xe0 + dw ARM_instruction_poldp-instruction_handler + db 'poldz',0xe0 + dw ARM_instruction_poldz-instruction_handler + db 'polem',0xe0 + dw ARM_instruction_polem-instruction_handler + db 'polep',0xe0 + dw ARM_instruction_polep-instruction_handler + db 'polez',0xe0 + dw ARM_instruction_polez-instruction_handler + db 'polsm',0xe0 + dw ARM_instruction_polsm-instruction_handler + db 'polsp',0xe0 + dw ARM_instruction_polsp-instruction_handler + db 'polsz',0xe0 + dw ARM_instruction_polsz-instruction_handler + db 'pop.n',0xe4 + dw ARM_instruction_pop-instruction_handler + db 'pop.w',0xe2 + dw ARM_instruction_pop-instruction_handler + db 'pop~~',0x00 + dw ARM_instruction_pop-instruction_handler + db 'powdm',0xe0 + dw ARM_instruction_powdm-instruction_handler + db 'powdp',0xe0 + dw ARM_instruction_powdp-instruction_handler + db 'powdz',0xe0 + dw ARM_instruction_powdz-instruction_handler + db 'powem',0xe0 + dw ARM_instruction_powem-instruction_handler + db 'powep',0xe0 + dw ARM_instruction_powep-instruction_handler + db 'powez',0xe0 + dw ARM_instruction_powez-instruction_handler + db 'powsm',0xe0 + dw ARM_instruction_powsm-instruction_handler + db 'powsp',0xe0 + dw ARM_instruction_powsp-instruction_handler + db 'powsz',0xe0 + dw ARM_instruction_powsz-instruction_handler + db 'qadd8',0xe0 + dw ARM_instruction_qadd8-instruction_handler + db 'qdadd',0xe0 + dw ARM_instruction_qdadd-instruction_handler + db 'qdsub',0xe0 + dw ARM_instruction_qdsub-instruction_handler + db 'qsub8',0xe0 + dw ARM_instruction_qsub8-instruction_handler + db 'rdfdm',0xe0 + dw ARM_instruction_rdfdm-instruction_handler + db 'rdfdp',0xe0 + dw ARM_instruction_rdfdp-instruction_handler + db 'rdfdz',0xe0 + dw ARM_instruction_rdfdz-instruction_handler + db 'rdfem',0xe0 + dw ARM_instruction_rdfem-instruction_handler + db 'rdfep',0xe0 + dw ARM_instruction_rdfep-instruction_handler + db 'rdfez',0xe0 + dw ARM_instruction_rdfez-instruction_handler + db 'rdfsm',0xe0 + dw ARM_instruction_rdfsm-instruction_handler + db 'rdfsp',0xe0 + dw ARM_instruction_rdfsp-instruction_handler + db 'rdfsz',0xe0 + dw ARM_instruction_rdfsz-instruction_handler + db 'rev.n',0xe4 + dw ARM_instruction_rev-instruction_handler + db 'rev.w',0xe2 + dw ARM_instruction_rev-instruction_handler + db 'rev16',0xe0 + dw ARM_instruction_rev16-instruction_handler + db 'rev32',0xf0 + dw ARM_instruction_rev32-instruction_handler + db 'rev64',0xf0 + dw ARM_instruction_rev64-instruction_handler + db 'revsh',0xe0 + dw ARM_instruction_revsh-instruction_handler + db 'rev~~',0x00 + dw ARM_instruction_rev-instruction_handler + db 'rfc~~',0x00 + dw ARM_instruction_rfc-instruction_handler + db 'rfeda',0xf0 + dw ARM_instruction_rfeda-instruction_handler + db 'rfedb',0xf0 + dw ARM_instruction_rfedb-instruction_handler + db 'rfeea',0xf0 + dw ARM_instruction_rfeea-instruction_handler + db 'rfeed',0xf0 + dw ARM_instruction_rfeed-instruction_handler + db 'rfefa',0xf0 + dw ARM_instruction_rfefa-instruction_handler + db 'rfefd',0xf0 + dw ARM_instruction_rfefd-instruction_handler + db 'rfeia',0xf0 + dw ARM_instruction_rfeia-instruction_handler + db 'rfeib',0xf0 + dw ARM_instruction_rfeib-instruction_handler + db 'rfs~~',0x00 + dw ARM_instruction_rfs-instruction_handler + db 'rmfdm',0xe0 + dw ARM_instruction_rmfdm-instruction_handler + db 'rmfdp',0xe0 + dw ARM_instruction_rmfdp-instruction_handler + db 'rmfdz',0xe0 + dw ARM_instruction_rmfdz-instruction_handler + db 'rmfem',0xe0 + dw ARM_instruction_rmfem-instruction_handler + db 'rmfep',0xe0 + dw ARM_instruction_rmfep-instruction_handler + db 'rmfez',0xe0 + dw ARM_instruction_rmfez-instruction_handler + db 'rmfsm',0xe0 + dw ARM_instruction_rmfsm-instruction_handler + db 'rmfsp',0xe0 + dw ARM_instruction_rmfsp-instruction_handler + db 'rmfsz',0xe0 + dw ARM_instruction_rmfsz-instruction_handler + db 'rnddm',0xe0 + dw ARM_instruction_rnddm-instruction_handler + db 'rnddp',0xe0 + dw ARM_instruction_rnddp-instruction_handler + db 'rnddz',0xe0 + dw ARM_instruction_rnddz-instruction_handler + db 'rndem',0xe0 + dw ARM_instruction_rndem-instruction_handler + db 'rndep',0xe0 + dw ARM_instruction_rndep-instruction_handler + db 'rndez',0xe0 + dw ARM_instruction_rndez-instruction_handler + db 'rndsm',0xe0 + dw ARM_instruction_rndsm-instruction_handler + db 'rndsp',0xe0 + dw ARM_instruction_rndsp-instruction_handler + db 'rndsz',0xe0 + dw ARM_instruction_rndsz-instruction_handler + db 'ror.n',0xe4 + dw ARM_instruction_ror-instruction_handler + db 'ror.w',0xe2 + dw ARM_instruction_ror-instruction_handler + db 'ror~~',0x00 + dw ARM_instruction_ror-instruction_handler + db 'rpwdm',0xe0 + dw ARM_instruction_rpwdm-instruction_handler + db 'rpwdp',0xe0 + dw ARM_instruction_rpwdp-instruction_handler + db 'rpwdz',0xe0 + dw ARM_instruction_rpwdz-instruction_handler + db 'rpwem',0xe0 + dw ARM_instruction_rpwem-instruction_handler + db 'rpwep',0xe0 + dw ARM_instruction_rpwep-instruction_handler + db 'rpwez',0xe0 + dw ARM_instruction_rpwez-instruction_handler + db 'rpwsm',0xe0 + dw ARM_instruction_rpwsm-instruction_handler + db 'rpwsp',0xe0 + dw ARM_instruction_rpwsp-instruction_handler + db 'rpwsz',0xe0 + dw ARM_instruction_rpwsz-instruction_handler + db 'rrx~~',0x00 + dw ARM_instruction_rrx-instruction_handler + db 'rsb.n',0xe4 + dw ARM_instruction_rsb-instruction_handler + db 'rsb.w',0xe2 + dw ARM_instruction_rsb-instruction_handler + db 'rsb~~',0x00 + dw ARM_instruction_rsb-instruction_handler + db 'rsc~~',0x00 + dw ARM_instruction_rsc-instruction_handler + db 'rsfdm',0xe0 + dw ARM_instruction_rsfdm-instruction_handler + db 'rsfdp',0xe0 + dw ARM_instruction_rsfdp-instruction_handler + db 'rsfdz',0xe0 + dw ARM_instruction_rsfdz-instruction_handler + db 'rsfem',0xe0 + dw ARM_instruction_rsfem-instruction_handler + db 'rsfep',0xe0 + dw ARM_instruction_rsfep-instruction_handler + db 'rsfez',0xe0 + dw ARM_instruction_rsfez-instruction_handler + db 'rsfsm',0xe0 + dw ARM_instruction_rsfsm-instruction_handler + db 'rsfsp',0xe0 + dw ARM_instruction_rsfsp-instruction_handler + db 'rsfsz',0xe0 + dw ARM_instruction_rsfsz-instruction_handler + db 'rshrn',0xf0 + dw ARM_instruction_rshrn-instruction_handler + db 'sabal',0xf0 + dw ARM_instruction_sabal-instruction_handler + db 'sabdl',0xf0 + dw ARM_instruction_sabdl-instruction_handler + db 'sadd8',0xe0 + dw ARM_instruction_sadd8-instruction_handler + db 'saddl',0xf0 + dw ARM_instruction_saddl-instruction_handler + db 'saddw',0xf0 + dw ARM_instruction_saddw-instruction_handler + db 'sbc.n',0xe4 + dw ARM_instruction_sbc-instruction_handler + db 'sbc.w',0xe2 + dw ARM_instruction_sbc-instruction_handler + db 'sbc~~',0x00 + dw ARM_instruction_sbc-instruction_handler + db 'sbfiz',0xf0 + dw ARM_instruction_sbfiz-instruction_handler + db 'scvtf',0xf0 + dw ARM_instruction_scvtf-instruction_handler + db 'sel~~',0x00 + dw ARM_instruction_sel-instruction_handler + db 'sev.n',0xe4 + dw ARM_instruction_sev-instruction_handler + db 'sev.w',0xe2 + dw ARM_instruction_sev-instruction_handler + db 'sev~~',0x00 + dw ARM_instruction_sev-instruction_handler + db 'sfmea',0xe0 + dw ARM_instruction_sfmea-instruction_handler + db 'sfmfd',0xe0 + dw ARM_instruction_sfmfd-instruction_handler + db 'sfm~~',0x00 + dw ARM_instruction_sfm-instruction_handler + db 'sha1c',0xf0 + dw ARM_instruction_sha1c-instruction_handler + db 'sha1h',0xf0 + dw ARM_instruction_sha1h-instruction_handler + db 'sha1m',0xf0 + dw ARM_instruction_sha1m-instruction_handler + db 'sha1p',0xf0 + dw ARM_instruction_sha1p-instruction_handler + db 'shadd',0xf0 + dw ARM_instruction_shadd-instruction_handler + db 'shasx',0xe0 + dw ARM_instruction_shasx-instruction_handler + db 'shll2',0xf0 + dw ARM_instruction_shll2-instruction_handler + db 'shrn2',0xf0 + dw ARM_instruction_shrn2-instruction_handler + db 'shsax',0xe0 + dw ARM_instruction_shsax-instruction_handler + db 'shsub',0xf0 + dw ARM_instruction_shsub-instruction_handler + db 'sindm',0xe0 + dw ARM_instruction_sindm-instruction_handler + db 'sindp',0xe0 + dw ARM_instruction_sindp-instruction_handler + db 'sindz',0xe0 + dw ARM_instruction_sindz-instruction_handler + db 'sinem',0xe0 + dw ARM_instruction_sinem-instruction_handler + db 'sinep',0xe0 + dw ARM_instruction_sinep-instruction_handler + db 'sinez',0xe0 + dw ARM_instruction_sinez-instruction_handler + db 'sinsm',0xe0 + dw ARM_instruction_sinsm-instruction_handler + db 'sinsp',0xe0 + dw ARM_instruction_sinsp-instruction_handler + db 'sinsz',0xe0 + dw ARM_instruction_sinsz-instruction_handler + db 'smaxp',0xf0 + dw ARM_instruction_smaxp-instruction_handler + db 'smaxv',0xf0 + dw ARM_instruction_smaxv-instruction_handler + db 'smc~~',0x00 + dw ARM_instruction_smc-instruction_handler + db 'sminp',0xf0 + dw ARM_instruction_sminp-instruction_handler + db 'sminv',0xf0 + dw ARM_instruction_sminv-instruction_handler + db 'smi~~',0x00 + dw ARM_instruction_smi-instruction_handler + db 'smlad',0xe0 + dw ARM_instruction_smlad-instruction_handler + db 'smlal',0xe0 + dw ARM_instruction_smlal-instruction_handler + db 'smlsd',0xe0 + dw ARM_instruction_smlsd-instruction_handler + db 'smlsl',0xf0 + dw ARM_instruction_smlsl-instruction_handler + db 'smmla',0xe0 + dw ARM_instruction_smmla-instruction_handler + db 'smmls',0xe0 + dw ARM_instruction_smmls-instruction_handler + db 'smmul',0xe0 + dw ARM_instruction_smmul-instruction_handler + db 'smuad',0xe0 + dw ARM_instruction_smuad-instruction_handler + db 'smulh',0xf0 + dw ARM_instruction_smulh-instruction_handler + db 'smull',0xe0 + dw ARM_instruction_smull-instruction_handler + db 'smusd',0xe0 + dw ARM_instruction_smusd-instruction_handler + db 'sqabs',0xf0 + dw ARM_instruction_sqabs-instruction_handler + db 'sqadd',0xf0 + dw ARM_instruction_sqadd-instruction_handler + db 'sqneg',0xf0 + dw ARM_instruction_sqneg-instruction_handler + db 'sqshl',0xf0 + dw ARM_instruction_sqshl-instruction_handler + db 'sqsub',0xf0 + dw ARM_instruction_sqsub-instruction_handler + db 'sqtdm',0xe0 + dw ARM_instruction_sqtdm-instruction_handler + db 'sqtdp',0xe0 + dw ARM_instruction_sqtdp-instruction_handler + db 'sqtdz',0xe0 + dw ARM_instruction_sqtdz-instruction_handler + db 'sqtem',0xe0 + dw ARM_instruction_sqtem-instruction_handler + db 'sqtep',0xe0 + dw ARM_instruction_sqtep-instruction_handler + db 'sqtez',0xe0 + dw ARM_instruction_sqtez-instruction_handler + db 'sqtsm',0xe0 + dw ARM_instruction_sqtsm-instruction_handler + db 'sqtsp',0xe0 + dw ARM_instruction_sqtsp-instruction_handler + db 'sqtsz',0xe0 + dw ARM_instruction_sqtsz-instruction_handler + db 'sqxtn',0xf0 + dw ARM_instruction_sqxtn-instruction_handler + db 'srsda',0xf0 + dw ARM_instruction_srsda-instruction_handler + db 'srsdb',0xf0 + dw ARM_instruction_srsdb-instruction_handler + db 'srsea',0xf0 + dw ARM_instruction_srsea-instruction_handler + db 'srsed',0xf0 + dw ARM_instruction_srsed-instruction_handler + db 'srsfa',0xf0 + dw ARM_instruction_srsfa-instruction_handler + db 'srsfd',0xf0 + dw ARM_instruction_srsfd-instruction_handler + db 'srshl',0xf0 + dw ARM_instruction_srshl-instruction_handler + db 'srshr',0xf0 + dw ARM_instruction_srshr-instruction_handler + db 'srsia',0xf0 + dw ARM_instruction_srsia-instruction_handler + db 'srsib',0xf0 + dw ARM_instruction_srsib-instruction_handler + db 'srsra',0xf0 + dw ARM_instruction_srsra-instruction_handler + db 'sshll',0xf0 + dw ARM_instruction_sshll-instruction_handler + db 'ssub8',0xe0 + dw ARM_instruction_ssub8-instruction_handler + db 'ssubl',0xf0 + dw ARM_instruction_ssubl-instruction_handler + db 'ssubw',0xf0 + dw ARM_instruction_ssubw-instruction_handler + db 'stack',0x00 + dw stack_directive-instruction_handler + db 'stc2l',0xe0 + dw ARM_instruction_stc2l-instruction_handler + db 'stc~~',0x00 + dw ARM_instruction_stc-instruction_handler + db 'stlex',0xe0 + dw ARM_instruction_stlex-instruction_handler + db 'stlrb',0xf0 + dw ARM_instruction_stlrb-instruction_handler + db 'stlrh',0xf0 + dw ARM_instruction_stlrh-instruction_handler + db 'stlxp',0xf0 + dw ARM_instruction_stlxp-instruction_handler + db 'stlxr',0xf0 + dw ARM_instruction_stlxr-instruction_handler + db 'stl~~',0x00 + dw ARM_instruction_stl-instruction_handler + db 'stm.n',0xe4 + dw ARM_instruction_stm-instruction_handler + db 'stm.w',0xe2 + dw ARM_instruction_stm-instruction_handler + db 'stmda',0xe0 + dw ARM_instruction_stmda-instruction_handler + db 'stmdb',0xe0 + dw ARM_instruction_stmdb-instruction_handler + db 'stmea',0xe0 + dw ARM_instruction_stmea-instruction_handler + db 'stmed',0xe0 + dw ARM_instruction_stmed-instruction_handler + db 'stmfa',0xe0 + dw ARM_instruction_stmfa-instruction_handler + db 'stmfd',0xe0 + dw ARM_instruction_stmfd-instruction_handler + db 'stmia',0xe0 + dw ARM_instruction_stmia-instruction_handler + db 'stmib',0xe0 + dw ARM_instruction_stmib-instruction_handler + db 'stm~~',0x00 + dw ARM_instruction_stm-instruction_handler + db 'store',0x00 + dw store_directive-instruction_handler + db 'str.n',0xe4 + dw ARM_instruction_str-instruction_handler + db 'str.w',0xe2 + dw ARM_instruction_str-instruction_handler + db 'strbt',0xe0 + dw ARM_instruction_strbt-instruction_handler + db 'strex',0xe0 + dw ARM_instruction_strex-instruction_handler + db 'strht',0xe0 + dw ARM_instruction_strht-instruction_handler + db 'str~~',0x00 + dw ARM_instruction_str-instruction_handler + db 'sttrb',0xf0 + dw ARM_instruction_sttrb-instruction_handler + db 'sttrh',0xf0 + dw ARM_instruction_sttrh-instruction_handler + db 'sturb',0xf0 + dw ARM_instruction_sturb-instruction_handler + db 'sturh',0xf0 + dw ARM_instruction_sturh-instruction_handler + db 'stxrb',0xf0 + dw ARM_instruction_stxrb-instruction_handler + db 'stxrh',0xf0 + dw ARM_instruction_stxrh-instruction_handler + db 'sub.n',0xe4 + dw ARM_instruction_sub-instruction_handler + db 'sub.w',0xe2 + dw ARM_instruction_sub-instruction_handler + db 'subhn',0xf0 + dw ARM_instruction_subhn-instruction_handler + db 'sub~~',0x00 + dw ARM_instruction_sub-instruction_handler + db 'sufdm',0xe0 + dw ARM_instruction_sufdm-instruction_handler + db 'sufdp',0xe0 + dw ARM_instruction_sufdp-instruction_handler + db 'sufdz',0xe0 + dw ARM_instruction_sufdz-instruction_handler + db 'sufem',0xe0 + dw ARM_instruction_sufem-instruction_handler + db 'sufep',0xe0 + dw ARM_instruction_sufep-instruction_handler + db 'sufez',0xe0 + dw ARM_instruction_sufez-instruction_handler + db 'sufsm',0xe0 + dw ARM_instruction_sufsm-instruction_handler + db 'sufsp',0xe0 + dw ARM_instruction_sufsp-instruction_handler + db 'sufsz',0xe0 + dw ARM_instruction_sufsz-instruction_handler + db 'svc.n',0xe4 + dw ARM_instruction_svc-instruction_handler + db 'svc.w',0xe2 + dw ARM_instruction_svc-instruction_handler + db 'svc~~',0x00 + dw ARM_instruction_svc-instruction_handler + db 'swi.n',0xe4 + dw ARM_instruction_swi-instruction_handler + db 'swi.w',0xe2 + dw ARM_instruction_swi-instruction_handler + db 'swi~~',0x00 + dw ARM_instruction_swi-instruction_handler + db 'swp~~',0x00 + dw ARM_instruction_swp-instruction_handler + db 'sxtab',0xe0 + dw ARM_instruction_sxtab-instruction_handler + db 'sxtah',0xe0 + dw ARM_instruction_sxtah-instruction_handler + db 'sxtl2',0xf0 + dw ARM_instruction_sxtl2-instruction_handler + db 'tandm',0xe0 + dw ARM_instruction_tandm-instruction_handler + db 'tandp',0xe0 + dw ARM_instruction_tandp-instruction_handler + db 'tandz',0xe0 + dw ARM_instruction_tandz-instruction_handler + db 'tanem',0xe0 + dw ARM_instruction_tanem-instruction_handler + db 'tanep',0xe0 + dw ARM_instruction_tanep-instruction_handler + db 'tanez',0xe0 + dw ARM_instruction_tanez-instruction_handler + db 'tansm',0xe0 + dw ARM_instruction_tansm-instruction_handler + db 'tansp',0xe0 + dw ARM_instruction_tansp-instruction_handler + db 'tansz',0xe0 + dw ARM_instruction_tansz-instruction_handler + db 'tbb~~',0x00 + dw ARM_instruction_tbb-instruction_handler + db 'tbh~~',0x00 + dw ARM_instruction_tbh-instruction_handler + db 'teq~~',0x00 + dw ARM_instruction_teq-instruction_handler + db 'thumb',0x00 + dw ARM_thumb_directive-instruction_handler + db 'times',0x00 + dw times_directive-instruction_handler + db 'tmcrr',0xe0 + dw ARM_instruction_tmcrr-instruction_handler + db 'tmrrc',0xe0 + dw ARM_instruction_tmrrc-instruction_handler + db 'torcb',0xe0 + dw ARM_instruction_torcb-instruction_handler + db 'torch',0xe0 + dw ARM_instruction_torch-instruction_handler + db 'torcw',0xe0 + dw ARM_instruction_torcw-instruction_handler + db 'tst.n',0xe4 + dw ARM_instruction_tst-instruction_handler + db 'tst.w',0xe2 + dw ARM_instruction_tst-instruction_handler + db 'tst~~',0x00 + dw ARM_instruction_tst-instruction_handler + db 'uabal',0xf0 + dw ARM_instruction_uabal-instruction_handler + db 'uabdl',0xf0 + dw ARM_instruction_uabdl-instruction_handler + db 'uadd8',0xe0 + dw ARM_instruction_uadd8-instruction_handler + db 'uaddl',0xf0 + dw ARM_instruction_uaddl-instruction_handler + db 'uaddw',0xf0 + dw ARM_instruction_uaddw-instruction_handler + db 'ubfiz',0xf0 + dw ARM_instruction_ubfiz-instruction_handler + db 'ucvtf',0xf0 + dw ARM_instruction_ucvtf-instruction_handler + db 'uhadd',0xf0 + dw ARM_instruction_uhadd-instruction_handler + db 'uhasx',0xe0 + dw ARM_instruction_uhasx-instruction_handler + db 'uhsax',0xe0 + dw ARM_instruction_uhsax-instruction_handler + db 'uhsub',0xf0 + dw ARM_instruction_uhsub-instruction_handler + db 'umaal',0xe0 + dw ARM_instruction_umaal-instruction_handler + db 'umaxp',0xf0 + dw ARM_instruction_umaxp-instruction_handler + db 'umaxv',0xf0 + dw ARM_instruction_umaxv-instruction_handler + db 'uminp',0xf0 + dw ARM_instruction_uminp-instruction_handler + db 'uminv',0xf0 + dw ARM_instruction_uminv-instruction_handler + db 'umlal',0xe0 + dw ARM_instruction_umlal-instruction_handler + db 'umlsl',0xf0 + dw ARM_instruction_umlsl-instruction_handler + db 'umulh',0xf0 + dw ARM_instruction_umulh-instruction_handler + db 'umull',0xe0 + dw ARM_instruction_umull-instruction_handler + db 'und.n',0xe4 + dw ARM_instruction_und-instruction_handler + db 'und.w',0xe2 + dw ARM_instruction_und-instruction_handler + db 'und~~',0x00 + dw ARM_instruction_und-instruction_handler + db 'uqadd',0xf0 + dw ARM_instruction_uqadd-instruction_handler + db 'uqasx',0xe0 + dw ARM_instruction_uqasx-instruction_handler + db 'uqsax',0xe0 + dw ARM_instruction_uqsax-instruction_handler + db 'uqshl',0xf0 + dw ARM_instruction_uqshl-instruction_handler + db 'uqsub',0xf0 + dw ARM_instruction_uqsub-instruction_handler + db 'uqxtn',0xf0 + dw ARM_instruction_uqxtn-instruction_handler + db 'urddm',0xe0 + dw ARM_instruction_urddm-instruction_handler + db 'urddp',0xe0 + dw ARM_instruction_urddp-instruction_handler + db 'urddz',0xe0 + dw ARM_instruction_urddz-instruction_handler + db 'urdem',0xe0 + dw ARM_instruction_urdem-instruction_handler + db 'urdep',0xe0 + dw ARM_instruction_urdep-instruction_handler + db 'urdez',0xe0 + dw ARM_instruction_urdez-instruction_handler + db 'urdsm',0xe0 + dw ARM_instruction_urdsm-instruction_handler + db 'urdsp',0xe0 + dw ARM_instruction_urdsp-instruction_handler + db 'urdsz',0xe0 + dw ARM_instruction_urdsz-instruction_handler + db 'urshl',0xf0 + dw ARM_instruction_urshl-instruction_handler + db 'urshr',0xf0 + dw ARM_instruction_urshr-instruction_handler + db 'ursra',0xf0 + dw ARM_instruction_ursra-instruction_handler + db 'usad8',0xe0 + dw ARM_instruction_usad8-instruction_handler + db 'use16',0x00 + dw ARM_code16_directive-instruction_handler + db 'use32',0x00 + dw ARM_code32_directive-instruction_handler + db 'use64',0x00 + dw ARM_code64_directive-instruction_handler + db 'ushll',0xf0 + dw ARM_instruction_ushll-instruction_handler + db 'usub8',0xe0 + dw ARM_instruction_usub8-instruction_handler + db 'usubl',0xf0 + dw ARM_instruction_usubl-instruction_handler + db 'usubw',0xf0 + dw ARM_instruction_usubw-instruction_handler + db 'uxtab',0xe0 + dw ARM_instruction_uxtab-instruction_handler + db 'uxtah',0xe0 + dw ARM_instruction_uxtah-instruction_handler + db 'uxtl2',0xf0 + dw ARM_instruction_uxtl2-instruction_handler + db 'vpush',0xe0 + dw ARM_instruction_vpush-instruction_handler + db 'wabsb',0xe0 + dw ARM_instruction_wabsb-instruction_handler + db 'wabsh',0xe0 + dw ARM_instruction_wabsh-instruction_handler + db 'wabsw',0xe0 + dw ARM_instruction_wabsw-instruction_handler + db 'waccb',0xe0 + dw ARM_instruction_waccb-instruction_handler + db 'wacch',0xe0 + dw ARM_instruction_wacch-instruction_handler + db 'waccw',0xe0 + dw ARM_instruction_waccw-instruction_handler + db 'waddb',0xe0 + dw ARM_instruction_waddb-instruction_handler + db 'waddh',0xe0 + dw ARM_instruction_waddh-instruction_handler + db 'waddw',0xe0 + dw ARM_instruction_waddw-instruction_handler + db 'wandn',0xe0 + dw ARM_instruction_wandn-instruction_handler + db 'wavg4',0xe0 + dw ARM_instruction_wavg4-instruction_handler + db 'wfc~~',0x00 + dw ARM_instruction_wfc-instruction_handler + db 'wfe.n',0xe4 + dw ARM_instruction_wfe-instruction_handler + db 'wfe.w',0xe2 + dw ARM_instruction_wfe-instruction_handler + db 'wfe~~',0x00 + dw ARM_instruction_wfe-instruction_handler + db 'wfi.n',0xe4 + dw ARM_instruction_wfi-instruction_handler + db 'wfi.w',0xe2 + dw ARM_instruction_wfi-instruction_handler + db 'wfi~~',0x00 + dw ARM_instruction_wfi-instruction_handler + db 'wfs~~',0x00 + dw ARM_instruction_wfs-instruction_handler + db 'while',0x00 + dw while_directive-instruction_handler + db 'wldrb',0xe0 + dw ARM_instruction_wldrb-instruction_handler + db 'wldrd',0xe0 + dw ARM_instruction_wldrd-instruction_handler + db 'wldrh',0xe0 + dw ARM_instruction_wldrh-instruction_handler + db 'wldrw',0xe0 + dw ARM_instruction_wldrw-instruction_handler + db 'wmacs',0xe0 + dw ARM_instruction_wmacs-instruction_handler + db 'wmacu',0xe0 + dw ARM_instruction_wmacu-instruction_handler + db 'wor~~',0x00 + dw ARM_instruction_wor-instruction_handler + db 'wrord',0xe0 + dw ARM_instruction_wrord-instruction_handler + db 'wrorh',0xe0 + dw ARM_instruction_wrorh-instruction_handler + db 'wrorw',0xe0 + dw ARM_instruction_wrorw-instruction_handler + db 'wsadb',0xe0 + dw ARM_instruction_wsadb-instruction_handler + db 'wsadh',0xe0 + dw ARM_instruction_wsadh-instruction_handler + db 'wslld',0xe0 + dw ARM_instruction_wslld-instruction_handler + db 'wsllh',0xe0 + dw ARM_instruction_wsllh-instruction_handler + db 'wsllw',0xe0 + dw ARM_instruction_wsllw-instruction_handler + db 'wsrad',0xe0 + dw ARM_instruction_wsrad-instruction_handler + db 'wsrah',0xe0 + dw ARM_instruction_wsrah-instruction_handler + db 'wsraw',0xe0 + dw ARM_instruction_wsraw-instruction_handler + db 'wsrld',0xe0 + dw ARM_instruction_wsrld-instruction_handler + db 'wsrlh',0xe0 + dw ARM_instruction_wsrlh-instruction_handler + db 'wsrlw',0xe0 + dw ARM_instruction_wsrlw-instruction_handler + db 'wstrb',0xe0 + dw ARM_instruction_wstrb-instruction_handler + db 'wstrd',0xe0 + dw ARM_instruction_wstrd-instruction_handler + db 'wstrh',0xe0 + dw ARM_instruction_wstrh-instruction_handler + db 'wstrw',0xe0 + dw ARM_instruction_wstrw-instruction_handler + db 'wsubb',0xe0 + dw ARM_instruction_wsubb-instruction_handler + db 'wsubh',0xe0 + dw ARM_instruction_wsubh-instruction_handler + db 'wsubw',0xe0 + dw ARM_instruction_wsubw-instruction_handler + db 'wzero',0xe0 + dw ARM_instruction_wzero-instruction_handler + db 'yield',0xe0 + dw ARM_instruction_yield-instruction_handler + db 0 +instructions_6: + db 'abs~~d',0x00 + dw ARM_instruction_absd-instruction_handler + db 'abs~~e',0x00 + dw ARM_instruction_abse-instruction_handler + db 'abs~~s',0x00 + dw ARM_instruction_abss-instruction_handler + db 'acs~~d',0x00 + dw ARM_instruction_acsd-instruction_handler + db 'acs~~e',0x00 + dw ARM_instruction_acse-instruction_handler + db 'acs~~s',0x00 + dw ARM_instruction_acss-instruction_handler + db 'adcs.n',0xe5 + dw ARM_instruction_adc-instruction_handler + db 'adcs.w',0xe3 + dw ARM_instruction_adc-instruction_handler + db 'adcs~~',0x01 + dw ARM_instruction_adc-instruction_handler + db 'adc~~s',0x01 + dw ARM_instruction_adc-instruction_handler + db 'addhn2',0xf0 + dw ARM_instruction_addhn2-instruction_handler + db 'adds.n',0xe5 + dw ARM_instruction_add-instruction_handler + db 'adds.w',0xe3 + dw ARM_instruction_add-instruction_handler + db 'adds~~',0x01 + dw ARM_instruction_add-instruction_handler + db 'addw~~',0x00 + dw ARM_instruction_addw-instruction_handler + db 'add~~s',0x01 + dw ARM_instruction_add-instruction_handler + db 'adf~~d',0x00 + dw ARM_instruction_adfd-instruction_handler + db 'adf~~e',0x00 + dw ARM_instruction_adfe-instruction_handler + db 'adf~~s',0x00 + dw ARM_instruction_adfs-instruction_handler + db 'aesd.8',0xf0 + dw ARM_instruction_aesd.8-instruction_handler + db 'aese.8',0xf0 + dw ARM_instruction_aese.8-instruction_handler + db 'aesimc',0xf0 + dw ARM_instruction_aesimc-instruction_handler + db 'ands.n',0xe5 + dw ARM_instruction_and-instruction_handler + db 'ands.w',0xe3 + dw ARM_instruction_and-instruction_handler + db 'ands~~',0x01 + dw ARM_instruction_and-instruction_handler + db 'and~~s',0x01 + dw ARM_instruction_and-instruction_handler + db 'asn~~d',0x00 + dw ARM_instruction_asnd-instruction_handler + db 'asn~~e',0x00 + dw ARM_instruction_asne-instruction_handler + db 'asn~~s',0x00 + dw ARM_instruction_asns-instruction_handler + db 'asrs.n',0xe5 + dw ARM_instruction_asr-instruction_handler + db 'asrs.w',0xe3 + dw ARM_instruction_asr-instruction_handler + db 'asrs~~',0x01 + dw ARM_instruction_asr-instruction_handler + db 'asr~~s',0x01 + dw ARM_instruction_asr-instruction_handler + db 'assert',0x00 + dw assert_directive-instruction_handler + db 'atn~~d',0x00 + dw ARM_instruction_atnd-instruction_handler + db 'atn~~e',0x00 + dw ARM_instruction_atne-instruction_handler + db 'atn~~s',0x00 + dw ARM_instruction_atns-instruction_handler + db 'bics.n',0xe5 + dw ARM_instruction_bic-instruction_handler + db 'bics.w',0xe3 + dw ARM_instruction_bic-instruction_handler + db 'bics~~',0x01 + dw ARM_instruction_bic-instruction_handler + db 'bic~~s',0x01 + dw ARM_instruction_bic-instruction_handler + db 'bx~~.n',0x04 + dw ARM_instruction_bx-instruction_handler + db 'bx~~.w',0x02 + dw ARM_instruction_bx-instruction_handler + db 'cbnz.n',0xf4 + dw ARM_instruction_cbnz-instruction_handler + db 'cbnz.w',0xf2 + dw ARM_instruction_cbnz-instruction_handler + db 'cdp2~~',0x00 + dw ARM_instruction_cdp2-instruction_handler + db 'cfabsd',0xe0 + dw ARM_instruction_cfabsd-instruction_handler + db 'cfabss',0xe0 + dw ARM_instruction_cfabss-instruction_handler + db 'cfaddd',0xe0 + dw ARM_instruction_cfaddd-instruction_handler + db 'cfadds',0xe0 + dw ARM_instruction_cfadds-instruction_handler + db 'cfcmpd',0xe0 + dw ARM_instruction_cfcmpd-instruction_handler + db 'cfcmps',0xe0 + dw ARM_instruction_cfcmps-instruction_handler + db 'cfcpyd',0xe0 + dw ARM_instruction_cfcpyd-instruction_handler + db 'cfcpys',0xe0 + dw ARM_instruction_cfcpys-instruction_handler + db 'cfldrd',0xe0 + dw ARM_instruction_cfldrd-instruction_handler + db 'cfldrs',0xe0 + dw ARM_instruction_cfldrs-instruction_handler + db 'cfmuld',0xe0 + dw ARM_instruction_cfmuld-instruction_handler + db 'cfmuls',0xe0 + dw ARM_instruction_cfmuls-instruction_handler + db 'cfmvrs',0xe0 + dw ARM_instruction_cfmvrs-instruction_handler + db 'cfmvsr',0xe0 + dw ARM_instruction_cfmvsr-instruction_handler + db 'cfnegd',0xe0 + dw ARM_instruction_cfnegd-instruction_handler + db 'cfnegs',0xe0 + dw ARM_instruction_cfnegs-instruction_handler + db 'cfsh32',0xe0 + dw ARM_instruction_cfsh32-instruction_handler + db 'cfsh64',0xe0 + dw ARM_instruction_cfsh64-instruction_handler + db 'cfstrd',0xe0 + dw ARM_instruction_cfstrd-instruction_handler + db 'cfstrs',0xe0 + dw ARM_instruction_cfstrs-instruction_handler + db 'cfsubd',0xe0 + dw ARM_instruction_cfsubd-instruction_handler + db 'cfsubs',0xe0 + dw ARM_instruction_cfsubs-instruction_handler + db 'chka~~',0x00 + dw ARM_instruction_chka-instruction_handler + db 'cmfe~~',0x00 + dw ARM_instruction_cmfe-instruction_handler + db 'cmnp~~',0x00 + dw ARM_instruction_cmnp-instruction_handler + db 'cmn~~p',0x00 + dw ARM_instruction_cmnp-instruction_handler + db 'cmpp~~',0x00 + dw ARM_instruction_cmpp-instruction_handler + db 'cmp~~p',0x00 + dw ARM_instruction_cmpp-instruction_handler + db 'cnfe~~',0x00 + dw ARM_instruction_cnfe-instruction_handler + db 'code16',0x00 + dw ARM_code16_directive-instruction_handler + db 'code32',0x00 + dw ARM_code32_directive-instruction_handler + db 'code64',0x00 + dw ARM_code64_directive-instruction_handler + db 'cos~~d',0x00 + dw ARM_instruction_cosd-instruction_handler + db 'cos~~e',0x00 + dw ARM_instruction_cose-instruction_handler + db 'cos~~s',0x00 + dw ARM_instruction_coss-instruction_handler + db 'crc32b',0xf0 + dw ARM_instruction_crc32b-instruction_handler + db 'crc32h',0xf0 + dw ARM_instruction_crc32h-instruction_handler + db 'crc32w',0xf0 + dw ARM_instruction_crc32w-instruction_handler + db 'crc32x',0xf0 + dw ARM_instruction_crc32x-instruction_handler + db 'dvf~~d',0x00 + dw ARM_instruction_dvfd-instruction_handler + db 'dvf~~e',0x00 + dw ARM_instruction_dvfe-instruction_handler + db 'dvf~~s',0x00 + dw ARM_instruction_dvfs-instruction_handler + db 'enterx',0xf0 + dw ARM_instruction_enterx-instruction_handler + db 'eors.n',0xe5 + dw ARM_instruction_eor-instruction_handler + db 'eors.w',0xe3 + dw ARM_instruction_eor-instruction_handler + db 'eors~~',0x01 + dw ARM_instruction_eor-instruction_handler + db 'eor~~s',0x01 + dw ARM_instruction_eor-instruction_handler + db 'eret~~',0x00 + dw ARM_instruction_eret-instruction_handler + db 'exp~~d',0x00 + dw ARM_instruction_expd-instruction_handler + db 'exp~~e',0x00 + dw ARM_instruction_expe-instruction_handler + db 'exp~~s',0x00 + dw ARM_instruction_exps-instruction_handler + db 'fccmpe',0xf0 + dw ARM_instruction_fccmpe-instruction_handler + db 'fcmped',0xe0 + dw ARM_instruction_fcmped-instruction_handler + db 'fcmpes',0xe0 + dw ARM_instruction_fcmpes-instruction_handler + db 'fcmpzd',0xe0 + dw ARM_instruction_fcmpzd-instruction_handler + db 'fcmpzs',0xe0 + dw ARM_instruction_fcmpzs-instruction_handler + db 'fcvtas',0xf0 + dw ARM_instruction_fcvtas-instruction_handler + db 'fcvtau',0xf0 + dw ARM_instruction_fcvtau-instruction_handler + db 'fcvtds',0xe0 + dw ARM_instruction_fcvtds-instruction_handler + db 'fcvtl2',0xf0 + dw ARM_instruction_fcvtl2-instruction_handler + db 'fcvtms',0xf0 + dw ARM_instruction_fcvtms-instruction_handler + db 'fcvtmu',0xf0 + dw ARM_instruction_fcvtmu-instruction_handler + db 'fcvtn2',0xf0 + dw ARM_instruction_fcvtn2-instruction_handler + db 'fcvtns',0xf0 + dw ARM_instruction_fcvtns-instruction_handler + db 'fcvtnu',0xf0 + dw ARM_instruction_fcvtnu-instruction_handler + db 'fcvtps',0xf0 + dw ARM_instruction_fcvtps-instruction_handler + db 'fcvtpu',0xf0 + dw ARM_instruction_fcvtpu-instruction_handler + db 'fcvtsd',0xe0 + dw ARM_instruction_fcvtsd-instruction_handler + db 'fcvtxn',0xf0 + dw ARM_instruction_fcvtxn-instruction_handler + db 'fcvtzs',0xf0 + dw ARM_instruction_fcvtzs-instruction_handler + db 'fcvtzu',0xf0 + dw ARM_instruction_fcvtzu-instruction_handler + db 'fdv~~d',0x00 + dw ARM_instruction_fdvd-instruction_handler + db 'fdv~~e',0x00 + dw ARM_instruction_fdve-instruction_handler + db 'fdv~~s',0x00 + dw ARM_instruction_fdvs-instruction_handler + db 'fix~~m',0x00 + dw ARM_instruction_fixm-instruction_handler + db 'fix~~p',0x00 + dw ARM_instruction_fixp-instruction_handler + db 'fix~~z',0x00 + dw ARM_instruction_fixz-instruction_handler + db 'fldd~~',0x00 + dw ARM_instruction_fldd-instruction_handler + db 'flds~~',0x00 + dw ARM_instruction_flds-instruction_handler + db 'flt~~d',0x00 + dw ARM_instruction_fltd-instruction_handler + db 'flt~~e',0x00 + dw ARM_instruction_flte-instruction_handler + db 'flt~~s',0x00 + dw ARM_instruction_flts-instruction_handler + db 'fmaxnm',0xf0 + dw ARM_instruction_fmaxnm-instruction_handler + db 'fminnm',0xf0 + dw ARM_instruction_fminnm-instruction_handler + db 'fml~~d',0x00 + dw ARM_instruction_fmld-instruction_handler + db 'fml~~e',0x00 + dw ARM_instruction_fmle-instruction_handler + db 'fml~~s',0x00 + dw ARM_instruction_fmls-instruction_handler + db 'fmrs~~',0x00 + dw ARM_instruction_fmrs-instruction_handler + db 'fmrx~~',0x00 + dw ARM_instruction_fmrx-instruction_handler + db 'fmsr~~',0x00 + dw ARM_instruction_fmsr-instruction_handler + db 'fmstat',0xe0 + dw ARM_instruction_fmstat-instruction_handler + db 'fmxr~~',0x00 + dw ARM_instruction_fmxr-instruction_handler + db 'fnmacd',0xe0 + dw ARM_instruction_fnmacd-instruction_handler + db 'fnmacs',0xe0 + dw ARM_instruction_fnmacs-instruction_handler + db 'fnmadd',0xf0 + dw ARM_instruction_fnmadd-instruction_handler + db 'fnmscd',0xe0 + dw ARM_instruction_fnmscd-instruction_handler + db 'fnmscs',0xe0 + dw ARM_instruction_fnmscs-instruction_handler + db 'fnmsub',0xf0 + dw ARM_instruction_fnmsub-instruction_handler + db 'fnmuld',0xe0 + dw ARM_instruction_fnmuld-instruction_handler + db 'fnmuls',0xe0 + dw ARM_instruction_fnmuls-instruction_handler + db 'format',0x00 + dw ARM_format_directive-instruction_handler + db 'frd~~d',0x00 + dw ARM_instruction_frdd-instruction_handler + db 'frd~~e',0x00 + dw ARM_instruction_frde-instruction_handler + db 'frd~~s',0x00 + dw ARM_instruction_frds-instruction_handler + db 'frecpe',0xf0 + dw ARM_instruction_frecpe-instruction_handler + db 'frecps',0xf0 + dw ARM_instruction_frecps-instruction_handler + db 'frecpx',0xf0 + dw ARM_instruction_frecpx-instruction_handler + db 'frinta',0xf0 + dw ARM_instruction_frinta-instruction_handler + db 'frinti',0xf0 + dw ARM_instruction_frinti-instruction_handler + db 'frintm',0xf0 + dw ARM_instruction_frintm-instruction_handler + db 'frintn',0xf0 + dw ARM_instruction_frintn-instruction_handler + db 'frintp',0xf0 + dw ARM_instruction_frintp-instruction_handler + db 'frintx',0xf0 + dw ARM_instruction_frintx-instruction_handler + db 'frintz',0xf0 + dw ARM_instruction_frintz-instruction_handler + db 'fshtod',0xe0 + dw ARM_instruction_fshtod-instruction_handler + db 'fshtos',0xe0 + dw ARM_instruction_fshtos-instruction_handler + db 'fsitod',0xe0 + dw ARM_instruction_fsitod-instruction_handler + db 'fsitos',0xe0 + dw ARM_instruction_fsitos-instruction_handler + db 'fsltod',0xe0 + dw ARM_instruction_fsltod-instruction_handler + db 'fsltos',0xe0 + dw ARM_instruction_fsltos-instruction_handler + db 'fsqrtd',0xe0 + dw ARM_instruction_fsqrtd-instruction_handler + db 'fsqrts',0xe0 + dw ARM_instruction_fsqrts-instruction_handler + db 'fstd~~',0x00 + dw ARM_instruction_fstd-instruction_handler + db 'fsts~~',0x00 + dw ARM_instruction_fsts-instruction_handler + db 'ftoshd',0xe0 + dw ARM_instruction_ftoshd-instruction_handler + db 'ftoshs',0xe0 + dw ARM_instruction_ftoshs-instruction_handler + db 'ftosid',0xe0 + dw ARM_instruction_ftosid-instruction_handler + db 'ftosis',0xe0 + dw ARM_instruction_ftosis-instruction_handler + db 'ftosld',0xe0 + dw ARM_instruction_ftosld-instruction_handler + db 'ftosls',0xe0 + dw ARM_instruction_ftosls-instruction_handler + db 'ftouhd',0xe0 + dw ARM_instruction_ftouhd-instruction_handler + db 'ftouhs',0xe0 + dw ARM_instruction_ftouhs-instruction_handler + db 'ftouid',0xe0 + dw ARM_instruction_ftouid-instruction_handler + db 'ftouis',0xe0 + dw ARM_instruction_ftouis-instruction_handler + db 'ftould',0xe0 + dw ARM_instruction_ftould-instruction_handler + db 'ftouls',0xe0 + dw ARM_instruction_ftouls-instruction_handler + db 'fuhtod',0xe0 + dw ARM_instruction_fuhtod-instruction_handler + db 'fuhtos',0xe0 + dw ARM_instruction_fuhtos-instruction_handler + db 'fuitod',0xe0 + dw ARM_instruction_fuitod-instruction_handler + db 'fuitos',0xe0 + dw ARM_instruction_fuitos-instruction_handler + db 'fultod',0xe0 + dw ARM_instruction_fultod-instruction_handler + db 'fultos',0xe0 + dw ARM_instruction_fultos-instruction_handler + db 'hblp~~',0x00 + dw ARM_instruction_hblp-instruction_handler + db 'itauto',0x00 + dw ARM_itauto_directive-instruction_handler + db 'ldab~~',0x00 + dw ARM_instruction_ldab-instruction_handler + db 'ldaexb',0xe0 + dw ARM_instruction_ldaexb-instruction_handler + db 'ldaexd',0xe0 + dw ARM_instruction_ldaexd-instruction_handler + db 'ldaexh',0xe0 + dw ARM_instruction_ldaexh-instruction_handler + db 'ldah~~',0x00 + dw ARM_instruction_ldah-instruction_handler + db 'ldaxrb',0xf0 + dw ARM_instruction_ldaxrb-instruction_handler + db 'ldaxrh',0xf0 + dw ARM_instruction_ldaxrh-instruction_handler + db 'lda~~b',0x00 + dw ARM_instruction_ldab-instruction_handler + db 'lda~~h',0x00 + dw ARM_instruction_ldah-instruction_handler + db 'ldc2~~',0x00 + dw ARM_instruction_ldc2-instruction_handler + db 'ldcl~~',0x00 + dw ARM_instruction_ldcl-instruction_handler + db 'ldc~~l',0x00 + dw ARM_instruction_ldcl-instruction_handler + db 'ldf~~d',0x00 + dw ARM_instruction_ldfd-instruction_handler + db 'ldf~~e',0x00 + dw ARM_instruction_ldfe-instruction_handler + db 'ldf~~p',0x00 + dw ARM_instruction_ldfp-instruction_handler + db 'ldf~~s',0x00 + dw ARM_instruction_ldfs-instruction_handler + db 'ldrb.n',0xe4 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrb.w',0xe2 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrb~~',0x00 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrd~~',0x00 + dw ARM_instruction_ldrd-instruction_handler + db 'ldrexb',0xe0 + dw ARM_instruction_ldrexb-instruction_handler + db 'ldrexd',0xe0 + dw ARM_instruction_ldrexd-instruction_handler + db 'ldrexh',0xe0 + dw ARM_instruction_ldrexh-instruction_handler + db 'ldrh.n',0xe4 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrh.w',0xe2 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrh~~',0x00 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrsbt',0xe0 + dw ARM_instruction_ldrsbt-instruction_handler + db 'ldrsht',0xe0 + dw ARM_instruction_ldrsht-instruction_handler + db 'ldrt~~',0x00 + dw ARM_instruction_ldrt-instruction_handler + db 'ldr~~b',0x00 + dw ARM_instruction_ldrb-instruction_handler + db 'ldr~~d',0x00 + dw ARM_instruction_ldrd-instruction_handler + db 'ldr~~h',0x00 + dw ARM_instruction_ldrh-instruction_handler + db 'ldr~~t',0x00 + dw ARM_instruction_ldrt-instruction_handler + db 'ldtrsb',0xf0 + dw ARM_instruction_ldtrsb-instruction_handler + db 'ldtrsh',0xf0 + dw ARM_instruction_ldtrsh-instruction_handler + db 'ldtrsw',0xf0 + dw ARM_instruction_ldtrsw-instruction_handler + db 'ldursb',0xf0 + dw ARM_instruction_ldursb-instruction_handler + db 'ldursh',0xf0 + dw ARM_instruction_ldursh-instruction_handler + db 'ldursw',0xf0 + dw ARM_instruction_ldursw-instruction_handler + db 'leavex',0xf0 + dw ARM_instruction_leavex-instruction_handler + db 'lgn~~d',0x00 + dw ARM_instruction_lgnd-instruction_handler + db 'lgn~~e',0x00 + dw ARM_instruction_lgne-instruction_handler + db 'lgn~~s',0x00 + dw ARM_instruction_lgns-instruction_handler + db 'log~~d',0x00 + dw ARM_instruction_logd-instruction_handler + db 'log~~e',0x00 + dw ARM_instruction_loge-instruction_handler + db 'log~~s',0x00 + dw ARM_instruction_logs-instruction_handler + db 'lsls.n',0xe5 + dw ARM_instruction_lsl-instruction_handler + db 'lsls.w',0xe3 + dw ARM_instruction_lsl-instruction_handler + db 'lsls~~',0x01 + dw ARM_instruction_lsl-instruction_handler + db 'lsl~~s',0x01 + dw ARM_instruction_lsl-instruction_handler + db 'lsrs.n',0xe5 + dw ARM_instruction_lsr-instruction_handler + db 'lsrs.w',0xe3 + dw ARM_instruction_lsr-instruction_handler + db 'lsrs~~',0x01 + dw ARM_instruction_lsr-instruction_handler + db 'lsr~~s',0x01 + dw ARM_instruction_lsr-instruction_handler + db 'mcr2~~',0x00 + dw ARM_instruction_mcr2-instruction_handler + db 'mcrr~~',0x00 + dw ARM_instruction_mcrr-instruction_handler + db 'mlas~~',0x01 + dw ARM_instruction_mla-instruction_handler + db 'mla~~s',0x01 + dw ARM_instruction_mla-instruction_handler + db 'mnf~~d',0x00 + dw ARM_instruction_mnfd-instruction_handler + db 'mnf~~e',0x00 + dw ARM_instruction_mnfe-instruction_handler + db 'mnf~~s',0x00 + dw ARM_instruction_mnfs-instruction_handler + db 'movs.n',0xe5 + dw ARM_instruction_mov-instruction_handler + db 'movs.w',0xe3 + dw ARM_instruction_mov-instruction_handler + db 'movs~~',0x01 + dw ARM_instruction_mov-instruction_handler + db 'movt~~',0x00 + dw ARM_instruction_movt-instruction_handler + db 'movw~~',0x00 + dw ARM_instruction_movw-instruction_handler + db 'mov~~s',0x01 + dw ARM_instruction_mov-instruction_handler + db 'mrc2~~',0x00 + dw ARM_instruction_mrc2-instruction_handler + db 'mrrc~~',0x00 + dw ARM_instruction_mrrc-instruction_handler + db 'muf~~d',0x00 + dw ARM_instruction_mufd-instruction_handler + db 'muf~~e',0x00 + dw ARM_instruction_mufe-instruction_handler + db 'muf~~s',0x00 + dw ARM_instruction_mufs-instruction_handler + db 'muls.n',0xe5 + dw ARM_instruction_mul-instruction_handler + db 'muls.w',0xe3 + dw ARM_instruction_mul-instruction_handler + db 'muls~~',0x01 + dw ARM_instruction_mul-instruction_handler + db 'mul~~s',0x01 + dw ARM_instruction_mul-instruction_handler + db 'mvf~~d',0x00 + dw ARM_instruction_mvfd-instruction_handler + db 'mvf~~e',0x00 + dw ARM_instruction_mvfe-instruction_handler + db 'mvf~~s',0x00 + dw ARM_instruction_mvfs-instruction_handler + db 'mvns.n',0xe5 + dw ARM_instruction_mvn-instruction_handler + db 'mvns.w',0xe3 + dw ARM_instruction_mvn-instruction_handler + db 'mvns~~',0x01 + dw ARM_instruction_mvn-instruction_handler + db 'mvn~~s',0x01 + dw ARM_instruction_mvn-instruction_handler + db 'negs.n',0xe5 + dw ARM_instruction_neg-instruction_handler + db 'negs.w',0xe3 + dw ARM_instruction_neg-instruction_handler + db 'negs~~',0x01 + dw ARM_instruction_neg-instruction_handler + db 'neg~~s',0x01 + dw ARM_instruction_neg-instruction_handler + db 'nrm~~d',0x00 + dw ARM_instruction_nrmd-instruction_handler + db 'nrm~~e',0x00 + dw ARM_instruction_nrme-instruction_handler + db 'nrm~~s',0x00 + dw ARM_instruction_nrms-instruction_handler + db 'orns~~',0x01 + dw ARM_instruction_orn-instruction_handler + db 'orn~~s',0x01 + dw ARM_instruction_orn-instruction_handler + db 'orrs.n',0xe5 + dw ARM_instruction_orr-instruction_handler + db 'orrs.w',0xe3 + dw ARM_instruction_orr-instruction_handler + db 'orrs~~',0x01 + dw ARM_instruction_orr-instruction_handler + db 'orr~~s',0x01 + dw ARM_instruction_orr-instruction_handler + db 'pldw~~',0x00 + dw ARM_instruction_pldw-instruction_handler + db 'pmull2',0xf0 + dw ARM_instruction_pmull2-instruction_handler + db 'pol~~d',0x00 + dw ARM_instruction_pold-instruction_handler + db 'pol~~e',0x00 + dw ARM_instruction_pole-instruction_handler + db 'pol~~s',0x00 + dw ARM_instruction_pols-instruction_handler + db 'pow~~d',0x00 + dw ARM_instruction_powd-instruction_handler + db 'pow~~e',0x00 + dw ARM_instruction_powe-instruction_handler + db 'pow~~s',0x00 + dw ARM_instruction_pows-instruction_handler + db 'public',0x00 + dw public_directive-instruction_handler + db 'push.n',0xe4 + dw ARM_instruction_push-instruction_handler + db 'push.w',0xe2 + dw ARM_instruction_push-instruction_handler + db 'push~~',0x00 + dw ARM_instruction_push-instruction_handler + db 'qadd16',0xe0 + dw ARM_instruction_qadd16-instruction_handler + db 'qadd~~',0x00 + dw ARM_instruction_qadd-instruction_handler + db 'qasx~~',0x00 + dw ARM_instruction_qasx-instruction_handler + db 'qsax~~',0x00 + dw ARM_instruction_qsax-instruction_handler + db 'qsub16',0xe0 + dw ARM_instruction_qsub16-instruction_handler + db 'qsub~~',0x00 + dw ARM_instruction_qsub-instruction_handler + db 'raddhn',0xf0 + dw ARM_instruction_raddhn-instruction_handler + db 'rbit~~',0x00 + dw ARM_instruction_rbit-instruction_handler + db 'rdf~~d',0x00 + dw ARM_instruction_rdfd-instruction_handler + db 'rdf~~e',0x00 + dw ARM_instruction_rdfe-instruction_handler + db 'rdf~~s',0x00 + dw ARM_instruction_rdfs-instruction_handler + db 'repeat',0x00 + dw repeat_directive-instruction_handler + db 'rmf~~d',0x00 + dw ARM_instruction_rmfd-instruction_handler + db 'rmf~~e',0x00 + dw ARM_instruction_rmfe-instruction_handler + db 'rmf~~s',0x00 + dw ARM_instruction_rmfs-instruction_handler + db 'rnd~~d',0x00 + dw ARM_instruction_rndd-instruction_handler + db 'rnd~~e',0x00 + dw ARM_instruction_rnde-instruction_handler + db 'rnd~~s',0x00 + dw ARM_instruction_rnds-instruction_handler + db 'rors.n',0xe5 + dw ARM_instruction_ror-instruction_handler + db 'rors.w',0xe3 + dw ARM_instruction_ror-instruction_handler + db 'rors~~',0x01 + dw ARM_instruction_ror-instruction_handler + db 'ror~~s',0x01 + dw ARM_instruction_ror-instruction_handler + db 'rpw~~d',0x00 + dw ARM_instruction_rpwd-instruction_handler + db 'rpw~~e',0x00 + dw ARM_instruction_rpwe-instruction_handler + db 'rpw~~s',0x00 + dw ARM_instruction_rpws-instruction_handler + db 'rrxs~~',0x01 + dw ARM_instruction_rrx-instruction_handler + db 'rrx~~s',0x01 + dw ARM_instruction_rrx-instruction_handler + db 'rsbs.n',0xe5 + dw ARM_instruction_rsb-instruction_handler + db 'rsbs.w',0xe3 + dw ARM_instruction_rsb-instruction_handler + db 'rsbs~~',0x01 + dw ARM_instruction_rsb-instruction_handler + db 'rsb~~s',0x01 + dw ARM_instruction_rsb-instruction_handler + db 'rscs~~',0x01 + dw ARM_instruction_rsc-instruction_handler + db 'rsc~~s',0x01 + dw ARM_instruction_rsc-instruction_handler + db 'rsf~~d',0x00 + dw ARM_instruction_rsfd-instruction_handler + db 'rsf~~e',0x00 + dw ARM_instruction_rsfe-instruction_handler + db 'rsf~~s',0x00 + dw ARM_instruction_rsfs-instruction_handler + db 'rshrn2',0xf0 + dw ARM_instruction_rshrn2-instruction_handler + db 'rsubhn',0xf0 + dw ARM_instruction_rsubhn-instruction_handler + db 'sabal2',0xf0 + dw ARM_instruction_sabal2-instruction_handler + db 'sabdl2',0xf0 + dw ARM_instruction_sabdl2-instruction_handler + db 'sadalp',0xf0 + dw ARM_instruction_sadalp-instruction_handler + db 'sadd16',0xe0 + dw ARM_instruction_sadd16-instruction_handler + db 'saddl2',0xf0 + dw ARM_instruction_saddl2-instruction_handler + db 'saddlp',0xf0 + dw ARM_instruction_saddlp-instruction_handler + db 'saddlv',0xf0 + dw ARM_instruction_saddlv-instruction_handler + db 'saddw2',0xf0 + dw ARM_instruction_saddw2-instruction_handler + db 'sasx~~',0x00 + dw ARM_instruction_sasx-instruction_handler + db 'sbcs.n',0xe5 + dw ARM_instruction_sbc-instruction_handler + db 'sbcs.w',0xe3 + dw ARM_instruction_sbc-instruction_handler + db 'sbcs~~',0x01 + dw ARM_instruction_sbc-instruction_handler + db 'sbc~~s',0x01 + dw ARM_instruction_sbc-instruction_handler + db 'sbfx~~',0x00 + dw ARM_instruction_sbfx-instruction_handler + db 'sdiv~~',0x00 + dw ARM_instruction_sdiv-instruction_handler + db 'setend',0xf0 + dw ARM_instruction_setend-instruction_handler + db 'sevl.n',0xe4 + dw ARM_instruction_sevl-instruction_handler + db 'sevl.w',0xe2 + dw ARM_instruction_sevl-instruction_handler + db 'sevl~~',0x00 + dw ARM_instruction_sevl-instruction_handler + db 'shadd8',0xe0 + dw ARM_instruction_shadd8-instruction_handler + db 'shsub8',0xe0 + dw ARM_instruction_shsub8-instruction_handler + db 'sin~~d',0x00 + dw ARM_instruction_sind-instruction_handler + db 'sin~~e',0x00 + dw ARM_instruction_sine-instruction_handler + db 'sin~~s',0x00 + dw ARM_instruction_sins-instruction_handler + db 'smaddl',0xf0 + dw ARM_instruction_smaddl-instruction_handler + db 'smlabb',0xe0 + dw ARM_instruction_smlabb-instruction_handler + db 'smlabt',0xe0 + dw ARM_instruction_smlabt-instruction_handler + db 'smladx',0xe0 + dw ARM_instruction_smladx-instruction_handler + db 'smlal2',0xf0 + dw ARM_instruction_smlal2-instruction_handler + db 'smlald',0xe0 + dw ARM_instruction_smlald-instruction_handler + db 'smlals',0xe1 + dw ARM_instruction_smlal-instruction_handler + db 'smlatb',0xe0 + dw ARM_instruction_smlatb-instruction_handler + db 'smlatt',0xe0 + dw ARM_instruction_smlatt-instruction_handler + db 'smlawb',0xe0 + dw ARM_instruction_smlawb-instruction_handler + db 'smlawt',0xe0 + dw ARM_instruction_smlawt-instruction_handler + db 'smlsdx',0xe0 + dw ARM_instruction_smlsdx-instruction_handler + db 'smlsl2',0xf0 + dw ARM_instruction_smlsl2-instruction_handler + db 'smlsld',0xe0 + dw ARM_instruction_smlsld-instruction_handler + db 'smmlar',0xe0 + dw ARM_instruction_smmlar-instruction_handler + db 'smmlsr',0xe0 + dw ARM_instruction_smmlsr-instruction_handler + db 'smmulr',0xe0 + dw ARM_instruction_smmulr-instruction_handler + db 'smnegl',0xf0 + dw ARM_instruction_smnegl-instruction_handler + db 'smsubl',0xf0 + dw ARM_instruction_smsubl-instruction_handler + db 'smuadx',0xe0 + dw ARM_instruction_smuadx-instruction_handler + db 'smulbb',0xe0 + dw ARM_instruction_smulbb-instruction_handler + db 'smulbt',0xe0 + dw ARM_instruction_smulbt-instruction_handler + db 'smull2',0xf0 + dw ARM_instruction_smull2-instruction_handler + db 'smulls',0xe1 + dw ARM_instruction_smull-instruction_handler + db 'smultb',0xe0 + dw ARM_instruction_smultb-instruction_handler + db 'smultt',0xe0 + dw ARM_instruction_smultt-instruction_handler + db 'smulwb',0xe0 + dw ARM_instruction_smulwb-instruction_handler + db 'smulwt',0xe0 + dw ARM_instruction_smulwt-instruction_handler + db 'smusdx',0xe0 + dw ARM_instruction_smusdx-instruction_handler + db 'sqrshl',0xf0 + dw ARM_instruction_sqrshl-instruction_handler + db 'sqshlu',0xf0 + dw ARM_instruction_sqshlu-instruction_handler + db 'sqshrn',0xf0 + dw ARM_instruction_sqshrn-instruction_handler + db 'sqt~~d',0x00 + dw ARM_instruction_sqtd-instruction_handler + db 'sqt~~e',0x00 + dw ARM_instruction_sqte-instruction_handler + db 'sqt~~s',0x00 + dw ARM_instruction_sqts-instruction_handler + db 'sqxtn2',0xf0 + dw ARM_instruction_sqxtn2-instruction_handler + db 'sqxtun',0xf0 + dw ARM_instruction_sqxtun-instruction_handler + db 'srhadd',0xf0 + dw ARM_instruction_srhadd-instruction_handler + db 'ssat16',0xe0 + dw ARM_instruction_ssat16-instruction_handler + db 'ssat~~',0x00 + dw ARM_instruction_ssat-instruction_handler + db 'ssax~~',0x00 + dw ARM_instruction_ssax-instruction_handler + db 'sshll2',0xf0 + dw ARM_instruction_sshll2-instruction_handler + db 'ssub16',0xe0 + dw ARM_instruction_ssub16-instruction_handler + db 'ssubl2',0xf0 + dw ARM_instruction_ssubl2-instruction_handler + db 'ssubw2',0xf0 + dw ARM_instruction_ssubw2-instruction_handler + db 'stc2~~',0x00 + dw ARM_instruction_stc2-instruction_handler + db 'stcl~~',0x00 + dw ARM_instruction_stcl-instruction_handler + db 'stc~~l',0x00 + dw ARM_instruction_stcl-instruction_handler + db 'stf~~d',0x00 + dw ARM_instruction_stfd-instruction_handler + db 'stf~~e',0x00 + dw ARM_instruction_stfe-instruction_handler + db 'stf~~p',0x00 + dw ARM_instruction_stfp-instruction_handler + db 'stf~~s',0x00 + dw ARM_instruction_stfs-instruction_handler + db 'stlb~~',0x00 + dw ARM_instruction_stlb-instruction_handler + db 'stlexb',0xe0 + dw ARM_instruction_stlexb-instruction_handler + db 'stlexd',0xe0 + dw ARM_instruction_stlexd-instruction_handler + db 'stlexh',0xe0 + dw ARM_instruction_stlexh-instruction_handler + db 'stlh~~',0x00 + dw ARM_instruction_stlh-instruction_handler + db 'stlxrb',0xf0 + dw ARM_instruction_stlxrb-instruction_handler + db 'stlxrh',0xf0 + dw ARM_instruction_stlxrh-instruction_handler + db 'stl~~b',0x00 + dw ARM_instruction_stlb-instruction_handler + db 'stl~~h',0x00 + dw ARM_instruction_stlh-instruction_handler + db 'strb.n',0xe4 + dw ARM_instruction_strb-instruction_handler + db 'strb.w',0xe2 + dw ARM_instruction_strb-instruction_handler + db 'strb~~',0x00 + dw ARM_instruction_strb-instruction_handler + db 'strd~~',0x00 + dw ARM_instruction_strd-instruction_handler + db 'strexb',0xe0 + dw ARM_instruction_strexb-instruction_handler + db 'strexd',0xe0 + dw ARM_instruction_strexd-instruction_handler + db 'strexh',0xe0 + dw ARM_instruction_strexh-instruction_handler + db 'strh.n',0xe4 + dw ARM_instruction_strh-instruction_handler + db 'strh.w',0xe2 + dw ARM_instruction_strh-instruction_handler + db 'strh~~',0x00 + dw ARM_instruction_strh-instruction_handler + db 'strt~~',0x00 + dw ARM_instruction_strt-instruction_handler + db 'str~~b',0x00 + dw ARM_instruction_strb-instruction_handler + db 'str~~d',0x00 + dw ARM_instruction_strd-instruction_handler + db 'str~~h',0x00 + dw ARM_instruction_strh-instruction_handler + db 'str~~t',0x00 + dw ARM_instruction_strt-instruction_handler + db 'subhn2',0xf0 + dw ARM_instruction_subhn2-instruction_handler + db 'subs.n',0xe5 + dw ARM_instruction_sub-instruction_handler + db 'subs.w',0xe3 + dw ARM_instruction_sub-instruction_handler + db 'subs~~',0x01 + dw ARM_instruction_sub-instruction_handler + db 'subw~~',0x00 + dw ARM_instruction_subw-instruction_handler + db 'sub~~s',0x01 + dw ARM_instruction_sub-instruction_handler + db 'suf~~d',0x00 + dw ARM_instruction_sufd-instruction_handler + db 'suf~~e',0x00 + dw ARM_instruction_sufe-instruction_handler + db 'suf~~s',0x00 + dw ARM_instruction_sufs-instruction_handler + db 'suqadd',0xf0 + dw ARM_instruction_suqadd-instruction_handler + db 'swpb~~',0x00 + dw ARM_instruction_swpb-instruction_handler + db 'swp~~b',0x00 + dw ARM_instruction_swpb-instruction_handler + db 'sxtb.n',0xe4 + dw ARM_instruction_sxtb-instruction_handler + db 'sxtb.w',0xe2 + dw ARM_instruction_sxtb-instruction_handler + db 'sxtb16',0xe0 + dw ARM_instruction_sxtb16-instruction_handler + db 'sxtb~~',0x00 + dw ARM_instruction_sxtb-instruction_handler + db 'sxth.n',0xe4 + dw ARM_instruction_sxth-instruction_handler + db 'sxth.w',0xe2 + dw ARM_instruction_sxth-instruction_handler + db 'sxth~~',0x00 + dw ARM_instruction_sxth-instruction_handler + db 'tandcb',0xe0 + dw ARM_instruction_tandcb-instruction_handler + db 'tandch',0xe0 + dw ARM_instruction_tandch-instruction_handler + db 'tandcw',0xe0 + dw ARM_instruction_tandcw-instruction_handler + db 'tan~~d',0x00 + dw ARM_instruction_tand-instruction_handler + db 'tan~~e',0x00 + dw ARM_instruction_tane-instruction_handler + db 'tan~~s',0x00 + dw ARM_instruction_tans-instruction_handler + db 'tbcstb',0xe0 + dw ARM_instruction_tbcstb-instruction_handler + db 'tbcsth',0xe0 + dw ARM_instruction_tbcsth-instruction_handler + db 'tbcstw',0xe0 + dw ARM_instruction_tbcstw-instruction_handler + db 'teqp~~',0x00 + dw ARM_instruction_teqp-instruction_handler + db 'teq~~p',0x00 + dw ARM_instruction_teqp-instruction_handler + db 'tinsrb',0xe0 + dw ARM_instruction_tinsrb-instruction_handler + db 'tinsrh',0xe0 + dw ARM_instruction_tinsrh-instruction_handler + db 'tinsrw',0xe0 + dw ARM_instruction_tinsrw-instruction_handler + db 'tmcr~~',0x00 + dw ARM_instruction_tmcr-instruction_handler + db 'tmiabb',0xe0 + dw ARM_instruction_tmiabb-instruction_handler + db 'tmiabt',0xe0 + dw ARM_instruction_tmiabt-instruction_handler + db 'tmiaph',0xe0 + dw ARM_instruction_tmiaph-instruction_handler + db 'tmiatb',0xe0 + dw ARM_instruction_tmiatb-instruction_handler + db 'tmiatt',0xe0 + dw ARM_instruction_tmiatt-instruction_handler + db 'tmia~~',0x00 + dw ARM_instruction_tmia-instruction_handler + db 'tmrc~~',0x00 + dw ARM_instruction_tmrc-instruction_handler + db 'tstp~~',0x00 + dw ARM_instruction_tstp-instruction_handler + db 'tst~~p',0x00 + dw ARM_instruction_tstp-instruction_handler + db 'uabal2',0xf0 + dw ARM_instruction_uabal2-instruction_handler + db 'uabdl2',0xf0 + dw ARM_instruction_uabdl2-instruction_handler + db 'uadalp',0xf0 + dw ARM_instruction_uadalp-instruction_handler + db 'uadd16',0xe0 + dw ARM_instruction_uadd16-instruction_handler + db 'uaddl2',0xf0 + dw ARM_instruction_uaddl2-instruction_handler + db 'uaddlp',0xf0 + dw ARM_instruction_uaddlp-instruction_handler + db 'uaddlv',0xf0 + dw ARM_instruction_uaddlv-instruction_handler + db 'uaddw2',0xf0 + dw ARM_instruction_uaddw2-instruction_handler + db 'uasx~~',0x00 + dw ARM_instruction_uasx-instruction_handler + db 'ubfx~~',0x00 + dw ARM_instruction_ubfx-instruction_handler + db 'udiv~~',0x00 + dw ARM_instruction_udiv-instruction_handler + db 'uhadd8',0xe0 + dw ARM_instruction_uhadd8-instruction_handler + db 'uhsub8',0xe0 + dw ARM_instruction_uhsub8-instruction_handler + db 'umaddl',0xf0 + dw ARM_instruction_umaddl-instruction_handler + db 'umlal2',0xf0 + dw ARM_instruction_umlal2-instruction_handler + db 'umlals',0xe1 + dw ARM_instruction_umlal-instruction_handler + db 'umlsl2',0xf0 + dw ARM_instruction_umlsl2-instruction_handler + db 'umnegl',0xf0 + dw ARM_instruction_umnegl-instruction_handler + db 'umsubl',0xf0 + dw ARM_instruction_umsubl-instruction_handler + db 'umull2',0xf0 + dw ARM_instruction_umull2-instruction_handler + db 'umulls',0xe1 + dw ARM_instruction_umull-instruction_handler + db 'uqadd8',0xe0 + dw ARM_instruction_uqadd8-instruction_handler + db 'uqrshl',0xf0 + dw ARM_instruction_uqrshl-instruction_handler + db 'uqshrn',0xf0 + dw ARM_instruction_uqshrn-instruction_handler + db 'uqsub8',0xe0 + dw ARM_instruction_uqsub8-instruction_handler + db 'uqxtn2',0xf0 + dw ARM_instruction_uqxtn2-instruction_handler + db 'urd~~d',0x00 + dw ARM_instruction_urdd-instruction_handler + db 'urd~~e',0x00 + dw ARM_instruction_urde-instruction_handler + db 'urd~~s',0x00 + dw ARM_instruction_urds-instruction_handler + db 'urecpe',0xf0 + dw ARM_instruction_urecpe-instruction_handler + db 'urhadd',0xf0 + dw ARM_instruction_urhadd-instruction_handler + db 'usada8',0xe0 + dw ARM_instruction_usada8-instruction_handler + db 'usat16',0xe0 + dw ARM_instruction_usat16-instruction_handler + db 'usat~~',0x00 + dw ARM_instruction_usat-instruction_handler + db 'usax~~',0x00 + dw ARM_instruction_usax-instruction_handler + db 'ushll2',0xf0 + dw ARM_instruction_ushll2-instruction_handler + db 'usqadd',0xf0 + dw ARM_instruction_usqadd-instruction_handler + db 'usub16',0xe0 + dw ARM_instruction_usub16-instruction_handler + db 'usubl2',0xf0 + dw ARM_instruction_usubl2-instruction_handler + db 'usubw2',0xf0 + dw ARM_instruction_usubw2-instruction_handler + db 'uxtb.n',0xe4 + dw ARM_instruction_uxtb-instruction_handler + db 'uxtb.w',0xe2 + dw ARM_instruction_uxtb-instruction_handler + db 'uxtb16',0xe0 + dw ARM_instruction_uxtb16-instruction_handler + db 'uxtb~~',0x00 + dw ARM_instruction_uxtb-instruction_handler + db 'uxth.n',0xe4 + dw ARM_instruction_uxth-instruction_handler + db 'uxth.w',0xe2 + dw ARM_instruction_uxth-instruction_handler + db 'uxth~~',0x00 + dw ARM_instruction_uxth-instruction_handler + db 'vand~~',0x00 + dw ARM_instruction_vand-instruction_handler + db 'vbic~~',0x00 + dw ARM_instruction_vbic-instruction_handler + db 'vbif~~',0x00 + dw ARM_instruction_vbif-instruction_handler + db 'vbit~~',0x00 + dw ARM_instruction_vbit-instruction_handler + db 'vbsl~~',0x00 + dw ARM_instruction_vbsl-instruction_handler + db 'vcnt.8',0xe0 + dw ARM_instruction_vcnt.8-instruction_handler + db 'vdup.8',0xe0 + dw ARM_instruction_vdup.8-instruction_handler + db 'veor~~',0x00 + dw ARM_instruction_veor-instruction_handler + db 'vext.8',0xe0 + dw ARM_instruction_vext.8-instruction_handler + db 'vld1.8',0xe0 + dw ARM_instruction_vld1.8-instruction_handler + db 'vld2.8',0xe0 + dw ARM_instruction_vld2.8-instruction_handler + db 'vld3.8',0xe0 + dw ARM_instruction_vld3.8-instruction_handler + db 'vld4.8',0xe0 + dw ARM_instruction_vld4.8-instruction_handler + db 'vldmdb',0xe0 + dw ARM_instruction_vldmdb-instruction_handler + db 'vldmea',0xe0 + dw ARM_instruction_vldmea-instruction_handler + db 'vldmfd',0xe0 + dw ARM_instruction_vldmfd-instruction_handler + db 'vldmia',0xe0 + dw ARM_instruction_vldmia-instruction_handler + db 'vldm~~',0x00 + dw ARM_instruction_vldm-instruction_handler + db 'vldr~~',0x00 + dw ARM_instruction_vldr-instruction_handler + db 'vmov.8',0xe0 + dw ARM_instruction_vmov.8-instruction_handler + db 'vmov~~',0x00 + dw ARM_instruction_vmov-instruction_handler + db 'vmrs~~',0x00 + dw ARM_instruction_vmrs-instruction_handler + db 'vmsr~~',0x00 + dw ARM_instruction_vmsr-instruction_handler + db 'vmvn~~',0x00 + dw ARM_instruction_vmvn-instruction_handler + db 'vorn~~',0x00 + dw ARM_instruction_vorn-instruction_handler + db 'vorr~~',0x00 + dw ARM_instruction_vorr-instruction_handler + db 'vpop~~',0x00 + dw ARM_instruction_vpop-instruction_handler + db 'vsli.8',0xe0 + dw ARM_instruction_vsli.8-instruction_handler + db 'vsri.8',0xe0 + dw ARM_instruction_vsri.8-instruction_handler + db 'vst1.8',0xe0 + dw ARM_instruction_vst1.8-instruction_handler + db 'vst2.8',0xe0 + dw ARM_instruction_vst2.8-instruction_handler + db 'vst3.8',0xe0 + dw ARM_instruction_vst3.8-instruction_handler + db 'vst4.8',0xe0 + dw ARM_instruction_vst4.8-instruction_handler + db 'vstmdb',0xe0 + dw ARM_instruction_vstmdb-instruction_handler + db 'vstmea',0xe0 + dw ARM_instruction_vstmea-instruction_handler + db 'vstmfd',0xe0 + dw ARM_instruction_vstmfd-instruction_handler + db 'vstmia',0xe0 + dw ARM_instruction_vstmia-instruction_handler + db 'vstm~~',0x00 + dw ARM_instruction_vstm-instruction_handler + db 'vstr~~',0x00 + dw ARM_instruction_vstr-instruction_handler + db 'vswp~~',0x00 + dw ARM_instruction_vswp-instruction_handler + db 'vtbl.8',0xe0 + dw ARM_instruction_vtbl.8-instruction_handler + db 'vtbx.8',0xe0 + dw ARM_instruction_vtbx.8-instruction_handler + db 'vtrn.8',0xe0 + dw ARM_instruction_vtrn.8-instruction_handler + db 'vtst.8',0xe0 + dw ARM_instruction_vtst.8-instruction_handler + db 'vuzp.8',0xe0 + dw ARM_instruction_vuzp.8-instruction_handler + db 'vzip.8',0xe0 + dw ARM_instruction_vzip.8-instruction_handler + db 'waddhc',0xe0 + dw ARM_instruction_waddhc-instruction_handler + db 'waddwc',0xe0 + dw ARM_instruction_waddwc-instruction_handler + db 'wand~~',0x00 + dw ARM_instruction_wand-instruction_handler + db 'wavg2b',0xe0 + dw ARM_instruction_wavg2b-instruction_handler + db 'wavg2h',0xe0 + dw ARM_instruction_wavg2h-instruction_handler + db 'wavg4r',0xe0 + dw ARM_instruction_wavg4r-instruction_handler + db 'wmacsz',0xe0 + dw ARM_instruction_wmacsz-instruction_handler + db 'wmacuz',0xe0 + dw ARM_instruction_wmacuz-instruction_handler + db 'wmadds',0xe0 + dw ARM_instruction_wmadds-instruction_handler + db 'wmaddu',0xe0 + dw ARM_instruction_wmaddu-instruction_handler + db 'wmaxsb',0xe0 + dw ARM_instruction_wmaxsb-instruction_handler + db 'wmaxsh',0xe0 + dw ARM_instruction_wmaxsh-instruction_handler + db 'wmaxsw',0xe0 + dw ARM_instruction_wmaxsw-instruction_handler + db 'wmaxub',0xe0 + dw ARM_instruction_wmaxub-instruction_handler + db 'wmaxuh',0xe0 + dw ARM_instruction_wmaxuh-instruction_handler + db 'wmaxuw',0xe0 + dw ARM_instruction_wmaxuw-instruction_handler + db 'wmerge',0xe0 + dw ARM_instruction_wmerge-instruction_handler + db 'wmiabb',0xe0 + dw ARM_instruction_wmiabb-instruction_handler + db 'wmiabt',0xe0 + dw ARM_instruction_wmiabt-instruction_handler + db 'wmiatb',0xe0 + dw ARM_instruction_wmiatb-instruction_handler + db 'wmiatt',0xe0 + dw ARM_instruction_wmiatt-instruction_handler + db 'wminsb',0xe0 + dw ARM_instruction_wminsb-instruction_handler + db 'wminsh',0xe0 + dw ARM_instruction_wminsh-instruction_handler + db 'wminsw',0xe0 + dw ARM_instruction_wminsw-instruction_handler + db 'wminub',0xe0 + dw ARM_instruction_wminub-instruction_handler + db 'wminuh',0xe0 + dw ARM_instruction_wminuh-instruction_handler + db 'wminuw',0xe0 + dw ARM_instruction_wminuw-instruction_handler + db 'wmov~~',0x00 + dw ARM_instruction_wmov-instruction_handler + db 'wmulsl',0xe0 + dw ARM_instruction_wmulsl-instruction_handler + db 'wmulsm',0xe0 + dw ARM_instruction_wmulsm-instruction_handler + db 'wmulul',0xe0 + dw ARM_instruction_wmulul-instruction_handler + db 'wmulum',0xe0 + dw ARM_instruction_wmulum-instruction_handler + db 'wmulwl',0xe0 + dw ARM_instruction_wmulwl-instruction_handler + db 'wqmulm',0xe0 + dw ARM_instruction_wqmulm-instruction_handler + db 'wrordg',0xe0 + dw ARM_instruction_wrordg-instruction_handler + db 'wrorhg',0xe0 + dw ARM_instruction_wrorhg-instruction_handler + db 'wrorwg',0xe0 + dw ARM_instruction_wrorwg-instruction_handler + db 'wsadbz',0xe0 + dw ARM_instruction_wsadbz-instruction_handler + db 'wsadhz',0xe0 + dw ARM_instruction_wsadhz-instruction_handler + db 'wshufh',0xe0 + dw ARM_instruction_wshufh-instruction_handler + db 'wslldg',0xe0 + dw ARM_instruction_wslldg-instruction_handler + db 'wsllhg',0xe0 + dw ARM_instruction_wsllhg-instruction_handler + db 'wsllwg',0xe0 + dw ARM_instruction_wsllwg-instruction_handler + db 'wsradg',0xe0 + dw ARM_instruction_wsradg-instruction_handler + db 'wsrahg',0xe0 + dw ARM_instruction_wsrahg-instruction_handler + db 'wsrawg',0xe0 + dw ARM_instruction_wsrawg-instruction_handler + db 'wsrldg',0xe0 + dw ARM_instruction_wsrldg-instruction_handler + db 'wsrlhg',0xe0 + dw ARM_instruction_wsrlhg-instruction_handler + db 'wsrlwg',0xe0 + dw ARM_instruction_wsrlwg-instruction_handler + db 'wxor~~',0x00 + dw ARM_instruction_wxor-instruction_handler + db 0 +instructions_7: + db 'abs~~dm',0x00 + dw ARM_instruction_absdm-instruction_handler + db 'abs~~dp',0x00 + dw ARM_instruction_absdp-instruction_handler + db 'abs~~dz',0x00 + dw ARM_instruction_absdz-instruction_handler + db 'abs~~em',0x00 + dw ARM_instruction_absem-instruction_handler + db 'abs~~ep',0x00 + dw ARM_instruction_absep-instruction_handler + db 'abs~~ez',0x00 + dw ARM_instruction_absez-instruction_handler + db 'abs~~sm',0x00 + dw ARM_instruction_abssm-instruction_handler + db 'abs~~sp',0x00 + dw ARM_instruction_abssp-instruction_handler + db 'abs~~sz',0x00 + dw ARM_instruction_abssz-instruction_handler + db 'acs~~dm',0x00 + dw ARM_instruction_acsdm-instruction_handler + db 'acs~~dp',0x00 + dw ARM_instruction_acsdp-instruction_handler + db 'acs~~dz',0x00 + dw ARM_instruction_acsdz-instruction_handler + db 'acs~~em',0x00 + dw ARM_instruction_acsem-instruction_handler + db 'acs~~ep',0x00 + dw ARM_instruction_acsep-instruction_handler + db 'acs~~ez',0x00 + dw ARM_instruction_acsez-instruction_handler + db 'acs~~sm',0x00 + dw ARM_instruction_acssm-instruction_handler + db 'acs~~sp',0x00 + dw ARM_instruction_acssp-instruction_handler + db 'acs~~sz',0x00 + dw ARM_instruction_acssz-instruction_handler + db 'adc~~.n',0x04 + dw ARM_instruction_adc-instruction_handler + db 'adc~~.w',0x02 + dw ARM_instruction_adc-instruction_handler + db 'add~~.n',0x04 + dw ARM_instruction_add-instruction_handler + db 'add~~.w',0x02 + dw ARM_instruction_add-instruction_handler + db 'adf~~dm',0x00 + dw ARM_instruction_adfdm-instruction_handler + db 'adf~~dp',0x00 + dw ARM_instruction_adfdp-instruction_handler + db 'adf~~dz',0x00 + dw ARM_instruction_adfdz-instruction_handler + db 'adf~~em',0x00 + dw ARM_instruction_adfem-instruction_handler + db 'adf~~ep',0x00 + dw ARM_instruction_adfep-instruction_handler + db 'adf~~ez',0x00 + dw ARM_instruction_adfez-instruction_handler + db 'adf~~sm',0x00 + dw ARM_instruction_adfsm-instruction_handler + db 'adf~~sp',0x00 + dw ARM_instruction_adfsp-instruction_handler + db 'adf~~sz',0x00 + dw ARM_instruction_adfsz-instruction_handler + db 'adr~~.n',0x04 + dw ARM_instruction_adr-instruction_handler + db 'adr~~.w',0x02 + dw ARM_instruction_adr-instruction_handler + db 'aesmc.8',0xf0 + dw ARM_instruction_aesmc.8-instruction_handler + db 'and~~.n',0x04 + dw ARM_instruction_and-instruction_handler + db 'and~~.w',0x02 + dw ARM_instruction_and-instruction_handler + db 'asn~~dm',0x00 + dw ARM_instruction_asndm-instruction_handler + db 'asn~~dp',0x00 + dw ARM_instruction_asndp-instruction_handler + db 'asn~~dz',0x00 + dw ARM_instruction_asndz-instruction_handler + db 'asn~~em',0x00 + dw ARM_instruction_asnem-instruction_handler + db 'asn~~ep',0x00 + dw ARM_instruction_asnep-instruction_handler + db 'asn~~ez',0x00 + dw ARM_instruction_asnez-instruction_handler + db 'asn~~sm',0x00 + dw ARM_instruction_asnsm-instruction_handler + db 'asn~~sp',0x00 + dw ARM_instruction_asnsp-instruction_handler + db 'asn~~sz',0x00 + dw ARM_instruction_asnsz-instruction_handler + db 'asr~~.n',0x04 + dw ARM_instruction_asr-instruction_handler + db 'asr~~.w',0x02 + dw ARM_instruction_asr-instruction_handler + db 'atn~~dm',0x00 + dw ARM_instruction_atndm-instruction_handler + db 'atn~~dp',0x00 + dw ARM_instruction_atndp-instruction_handler + db 'atn~~dz',0x00 + dw ARM_instruction_atndz-instruction_handler + db 'atn~~em',0x00 + dw ARM_instruction_atnem-instruction_handler + db 'atn~~ep',0x00 + dw ARM_instruction_atnep-instruction_handler + db 'atn~~ez',0x00 + dw ARM_instruction_atnez-instruction_handler + db 'atn~~sm',0x00 + dw ARM_instruction_atnsm-instruction_handler + db 'atn~~sp',0x00 + dw ARM_instruction_atnsp-instruction_handler + db 'atn~~sz',0x00 + dw ARM_instruction_atnsz-instruction_handler + db 'bic~~.n',0x04 + dw ARM_instruction_bic-instruction_handler + db 'bic~~.w',0x02 + dw ARM_instruction_bic-instruction_handler + db 'blx~~.n',0x04 + dw ARM_instruction_blx-instruction_handler + db 'blx~~.w',0x02 + dw ARM_instruction_blx-instruction_handler + db 'cfabs32',0xe0 + dw ARM_instruction_cfabs32-instruction_handler + db 'cfabs64',0xe0 + dw ARM_instruction_cfabs64-instruction_handler + db 'cfadd32',0xe0 + dw ARM_instruction_cfadd32-instruction_handler + db 'cfadd64',0xe0 + dw ARM_instruction_cfadd64-instruction_handler + db 'cfcmp32',0xe0 + dw ARM_instruction_cfcmp32-instruction_handler + db 'cfcmp64',0xe0 + dw ARM_instruction_cfcmp64-instruction_handler + db 'cfcvtds',0xe0 + dw ARM_instruction_cfcvtds-instruction_handler + db 'cfcvtsd',0xe0 + dw ARM_instruction_cfcvtsd-instruction_handler + db 'cfldr32',0xe0 + dw ARM_instruction_cfldr32-instruction_handler + db 'cfldr64',0xe0 + dw ARM_instruction_cfldr64-instruction_handler + db 'cfmac32',0xe0 + dw ARM_instruction_cfmac32-instruction_handler + db 'cfmsc32',0xe0 + dw ARM_instruction_cfmsc32-instruction_handler + db 'cfmul32',0xe0 + dw ARM_instruction_cfmul32-instruction_handler + db 'cfmul64',0xe0 + dw ARM_instruction_cfmul64-instruction_handler + db 'cfmv32a',0xe0 + dw ARM_instruction_cfmv32a-instruction_handler + db 'cfmv64a',0xe0 + dw ARM_instruction_cfmv64a-instruction_handler + db 'cfmva32',0xe0 + dw ARM_instruction_cfmva32-instruction_handler + db 'cfmva64',0xe0 + dw ARM_instruction_cfmva64-instruction_handler + db 'cfmvdhr',0xe0 + dw ARM_instruction_cfmvdhr-instruction_handler + db 'cfmvdlr',0xe0 + dw ARM_instruction_cfmvdlr-instruction_handler + db 'cfmvrdh',0xe0 + dw ARM_instruction_cfmvrdh-instruction_handler + db 'cfmvrdl',0xe0 + dw ARM_instruction_cfmvrdl-instruction_handler + db 'cfneg32',0xe0 + dw ARM_instruction_cfneg32-instruction_handler + db 'cfneg64',0xe0 + dw ARM_instruction_cfneg64-instruction_handler + db 'cfstr32',0xe0 + dw ARM_instruction_cfstr32-instruction_handler + db 'cfstr64',0xe0 + dw ARM_instruction_cfstr64-instruction_handler + db 'cfsub32',0xe0 + dw ARM_instruction_cfsub32-instruction_handler + db 'cfsub64',0xe0 + dw ARM_instruction_cfsub64-instruction_handler + db 'clrex~~',0x00 + dw ARM_instruction_clrex-instruction_handler + db 'cmn~~.n',0x04 + dw ARM_instruction_cmn-instruction_handler + db 'cmn~~.w',0x02 + dw ARM_instruction_cmn-instruction_handler + db 'cmp~~.n',0x04 + dw ARM_instruction_cmp-instruction_handler + db 'cmp~~.w',0x02 + dw ARM_instruction_cmp-instruction_handler + db 'cos~~dm',0x00 + dw ARM_instruction_cosdm-instruction_handler + db 'cos~~dp',0x00 + dw ARM_instruction_cosdp-instruction_handler + db 'cos~~dz',0x00 + dw ARM_instruction_cosdz-instruction_handler + db 'cos~~em',0x00 + dw ARM_instruction_cosem-instruction_handler + db 'cos~~ep',0x00 + dw ARM_instruction_cosep-instruction_handler + db 'cos~~ez',0x00 + dw ARM_instruction_cosez-instruction_handler + db 'cos~~sm',0x00 + dw ARM_instruction_cossm-instruction_handler + db 'cos~~sp',0x00 + dw ARM_instruction_cossp-instruction_handler + db 'cos~~sz',0x00 + dw ARM_instruction_cossz-instruction_handler + db 'cpsid.n',0xf4 + dw ARM_instruction_cpsid-instruction_handler + db 'cpsid.w',0xf2 + dw ARM_instruction_cpsid-instruction_handler + db 'cpsie.n',0xf4 + dw ARM_instruction_cpsie-instruction_handler + db 'cpsie.w',0xf2 + dw ARM_instruction_cpsie-instruction_handler + db 'cpy~~.n',0x04 + dw ARM_instruction_cpy-instruction_handler + db 'cpy~~.w',0x02 + dw ARM_instruction_cpy-instruction_handler + db 'crc32cb',0xf0 + dw ARM_instruction_crc32cb-instruction_handler + db 'crc32ch',0xf0 + dw ARM_instruction_crc32ch-instruction_handler + db 'crc32cw',0xf0 + dw ARM_instruction_crc32cw-instruction_handler + db 'crc32cx',0xf0 + dw ARM_instruction_crc32cx-instruction_handler + db 'display',0x00 + dw display_directive-instruction_handler + db 'dvf~~dm',0x00 + dw ARM_instruction_dvfdm-instruction_handler + db 'dvf~~dp',0x00 + dw ARM_instruction_dvfdp-instruction_handler + db 'dvf~~dz',0x00 + dw ARM_instruction_dvfdz-instruction_handler + db 'dvf~~em',0x00 + dw ARM_instruction_dvfem-instruction_handler + db 'dvf~~ep',0x00 + dw ARM_instruction_dvfep-instruction_handler + db 'dvf~~ez',0x00 + dw ARM_instruction_dvfez-instruction_handler + db 'dvf~~sm',0x00 + dw ARM_instruction_dvfsm-instruction_handler + db 'dvf~~sp',0x00 + dw ARM_instruction_dvfsp-instruction_handler + db 'dvf~~sz',0x00 + dw ARM_instruction_dvfsz-instruction_handler + db 'eor~~.n',0x04 + dw ARM_instruction_eor-instruction_handler + db 'eor~~.w',0x02 + dw ARM_instruction_eor-instruction_handler + db 'exp~~dm',0x00 + dw ARM_instruction_expdm-instruction_handler + db 'exp~~dp',0x00 + dw ARM_instruction_expdp-instruction_handler + db 'exp~~dz',0x00 + dw ARM_instruction_expdz-instruction_handler + db 'exp~~em',0x00 + dw ARM_instruction_expem-instruction_handler + db 'exp~~ep',0x00 + dw ARM_instruction_expep-instruction_handler + db 'exp~~ez',0x00 + dw ARM_instruction_expez-instruction_handler + db 'exp~~sm',0x00 + dw ARM_instruction_expsm-instruction_handler + db 'exp~~sp',0x00 + dw ARM_instruction_expsp-instruction_handler + db 'exp~~sz',0x00 + dw ARM_instruction_expsz-instruction_handler + db 'fabsd~~',0x00 + dw ARM_instruction_fabsd-instruction_handler + db 'fabss~~',0x00 + dw ARM_instruction_fabss-instruction_handler + db 'faddd~~',0x00 + dw ARM_instruction_faddd-instruction_handler + db 'fadds~~',0x00 + dw ARM_instruction_fadds-instruction_handler + db 'fcmpd~~',0x00 + dw ARM_instruction_fcmpd-instruction_handler + db 'fcmpezd',0xe0 + dw ARM_instruction_fcmpezd-instruction_handler + db 'fcmpezs',0xe0 + dw ARM_instruction_fcmpezs-instruction_handler + db 'fcmps~~',0x00 + dw ARM_instruction_fcmps-instruction_handler + db 'fconstd',0xe0 + dw ARM_instruction_fconstd-instruction_handler + db 'fconsts',0xe0 + dw ARM_instruction_fconsts-instruction_handler + db 'fcpyd~~',0x00 + dw ARM_instruction_fcpyd-instruction_handler + db 'fcpys~~',0x00 + dw ARM_instruction_fcpys-instruction_handler + db 'fcvtxn2',0xf0 + dw ARM_instruction_fcvtxn2-instruction_handler + db 'fdivd~~',0x00 + dw ARM_instruction_fdivd-instruction_handler + db 'fdivs~~',0x00 + dw ARM_instruction_fdivs-instruction_handler + db 'fdv~~dm',0x00 + dw ARM_instruction_fdvdm-instruction_handler + db 'fdv~~dp',0x00 + dw ARM_instruction_fdvdp-instruction_handler + db 'fdv~~dz',0x00 + dw ARM_instruction_fdvdz-instruction_handler + db 'fdv~~em',0x00 + dw ARM_instruction_fdvem-instruction_handler + db 'fdv~~ep',0x00 + dw ARM_instruction_fdvep-instruction_handler + db 'fdv~~ez',0x00 + dw ARM_instruction_fdvez-instruction_handler + db 'fdv~~sm',0x00 + dw ARM_instruction_fdvsm-instruction_handler + db 'fdv~~sp',0x00 + dw ARM_instruction_fdvsp-instruction_handler + db 'fdv~~sz',0x00 + dw ARM_instruction_fdvsz-instruction_handler + db 'fldmdbd',0xe0 + dw ARM_instruction_fldmdbd-instruction_handler + db 'fldmdbs',0xe0 + dw ARM_instruction_fldmdbs-instruction_handler + db 'fldmdbx',0xe0 + dw ARM_instruction_fldmdbx-instruction_handler + db 'fldmd~~',0x00 + dw ARM_instruction_fldmd-instruction_handler + db 'fldmead',0xe0 + dw ARM_instruction_fldmead-instruction_handler + db 'fldmeas',0xe0 + dw ARM_instruction_fldmeas-instruction_handler + db 'fldmeax',0xe0 + dw ARM_instruction_fldmeax-instruction_handler + db 'fldmfdd',0xe0 + dw ARM_instruction_fldmfdd-instruction_handler + db 'fldmfds',0xe0 + dw ARM_instruction_fldmfds-instruction_handler + db 'fldmfdx',0xe0 + dw ARM_instruction_fldmfdx-instruction_handler + db 'fldmiad',0xe0 + dw ARM_instruction_fldmiad-instruction_handler + db 'fldmias',0xe0 + dw ARM_instruction_fldmias-instruction_handler + db 'fldmiax',0xe0 + dw ARM_instruction_fldmiax-instruction_handler + db 'fldms~~',0x00 + dw ARM_instruction_fldms-instruction_handler + db 'fldmx~~',0x00 + dw ARM_instruction_fldmx-instruction_handler + db 'flt~~dm',0x00 + dw ARM_instruction_fltdm-instruction_handler + db 'flt~~dp',0x00 + dw ARM_instruction_fltdp-instruction_handler + db 'flt~~dz',0x00 + dw ARM_instruction_fltdz-instruction_handler + db 'flt~~em',0x00 + dw ARM_instruction_fltem-instruction_handler + db 'flt~~ep',0x00 + dw ARM_instruction_fltep-instruction_handler + db 'flt~~ez',0x00 + dw ARM_instruction_fltez-instruction_handler + db 'flt~~sm',0x00 + dw ARM_instruction_fltsm-instruction_handler + db 'flt~~sp',0x00 + dw ARM_instruction_fltsp-instruction_handler + db 'flt~~sz',0x00 + dw ARM_instruction_fltsz-instruction_handler + db 'fmacd~~',0x00 + dw ARM_instruction_fmacd-instruction_handler + db 'fmacs~~',0x00 + dw ARM_instruction_fmacs-instruction_handler + db 'fmaxnmp',0xf0 + dw ARM_instruction_fmaxnmp-instruction_handler + db 'fmaxnmv',0xf0 + dw ARM_instruction_fmaxnmv-instruction_handler + db 'fmdhr~~',0x00 + dw ARM_instruction_fmdhr-instruction_handler + db 'fmdlr~~',0x00 + dw ARM_instruction_fmdlr-instruction_handler + db 'fmdrr~~',0x00 + dw ARM_instruction_fmdrr-instruction_handler + db 'fminnmp',0xf0 + dw ARM_instruction_fminnmp-instruction_handler + db 'fminnmv',0xf0 + dw ARM_instruction_fminnmv-instruction_handler + db 'fml~~dm',0x00 + dw ARM_instruction_fmldm-instruction_handler + db 'fml~~dp',0x00 + dw ARM_instruction_fmldp-instruction_handler + db 'fml~~dz',0x00 + dw ARM_instruction_fmldz-instruction_handler + db 'fml~~em',0x00 + dw ARM_instruction_fmlem-instruction_handler + db 'fml~~ep',0x00 + dw ARM_instruction_fmlep-instruction_handler + db 'fml~~ez',0x00 + dw ARM_instruction_fmlez-instruction_handler + db 'fml~~sm',0x00 + dw ARM_instruction_fmlsm-instruction_handler + db 'fml~~sp',0x00 + dw ARM_instruction_fmlsp-instruction_handler + db 'fml~~sz',0x00 + dw ARM_instruction_fmlsz-instruction_handler + db 'fmrdh~~',0x00 + dw ARM_instruction_fmrdh-instruction_handler + db 'fmrdl~~',0x00 + dw ARM_instruction_fmrdl-instruction_handler + db 'fmrrd~~',0x00 + dw ARM_instruction_fmrrd-instruction_handler + db 'fmrrs~~',0x00 + dw ARM_instruction_fmrrs-instruction_handler + db 'fmscd~~',0x00 + dw ARM_instruction_fmscd-instruction_handler + db 'fmscs~~',0x00 + dw ARM_instruction_fmscs-instruction_handler + db 'fmsrr~~',0x00 + dw ARM_instruction_fmsrr-instruction_handler + db 'fmuld~~',0x00 + dw ARM_instruction_fmuld-instruction_handler + db 'fmuls~~',0x00 + dw ARM_instruction_fmuls-instruction_handler + db 'fnegd~~',0x00 + dw ARM_instruction_fnegd-instruction_handler + db 'fnegs~~',0x00 + dw ARM_instruction_fnegs-instruction_handler + db 'frd~~dm',0x00 + dw ARM_instruction_frddm-instruction_handler + db 'frd~~dp',0x00 + dw ARM_instruction_frddp-instruction_handler + db 'frd~~dz',0x00 + dw ARM_instruction_frddz-instruction_handler + db 'frd~~em',0x00 + dw ARM_instruction_frdem-instruction_handler + db 'frd~~ep',0x00 + dw ARM_instruction_frdep-instruction_handler + db 'frd~~ez',0x00 + dw ARM_instruction_frdez-instruction_handler + db 'frd~~sm',0x00 + dw ARM_instruction_frdsm-instruction_handler + db 'frd~~sp',0x00 + dw ARM_instruction_frdsp-instruction_handler + db 'frd~~sz',0x00 + dw ARM_instruction_frdsz-instruction_handler + db 'frsqrte',0xf0 + dw ARM_instruction_frsqrte-instruction_handler + db 'frsqrts',0xf0 + dw ARM_instruction_frsqrts-instruction_handler + db 'fstmdbd',0xe0 + dw ARM_instruction_fstmdbd-instruction_handler + db 'fstmdbs',0xe0 + dw ARM_instruction_fstmdbs-instruction_handler + db 'fstmdbx',0xe0 + dw ARM_instruction_fstmdbx-instruction_handler + db 'fstmd~~',0x00 + dw ARM_instruction_fstmd-instruction_handler + db 'fstmead',0xe0 + dw ARM_instruction_fstmead-instruction_handler + db 'fstmeas',0xe0 + dw ARM_instruction_fstmeas-instruction_handler + db 'fstmeax',0xe0 + dw ARM_instruction_fstmeax-instruction_handler + db 'fstmfdd',0xe0 + dw ARM_instruction_fstmfdd-instruction_handler + db 'fstmfds',0xe0 + dw ARM_instruction_fstmfds-instruction_handler + db 'fstmfdx',0xe0 + dw ARM_instruction_fstmfdx-instruction_handler + db 'fstmiad',0xe0 + dw ARM_instruction_fstmiad-instruction_handler + db 'fstmias',0xe0 + dw ARM_instruction_fstmias-instruction_handler + db 'fstmiax',0xe0 + dw ARM_instruction_fstmiax-instruction_handler + db 'fstms~~',0x00 + dw ARM_instruction_fstms-instruction_handler + db 'fstmx~~',0x00 + dw ARM_instruction_fstmx-instruction_handler + db 'fsubd~~',0x00 + dw ARM_instruction_fsubd-instruction_handler + db 'fsubs~~',0x00 + dw ARM_instruction_fsubs-instruction_handler + db 'ftosizd',0xe0 + dw ARM_instruction_ftosizd-instruction_handler + db 'ftosizs',0xe0 + dw ARM_instruction_ftosizs-instruction_handler + db 'ftouizd',0xe0 + dw ARM_instruction_ftouizd-instruction_handler + db 'ftouizs',0xe0 + dw ARM_instruction_ftouizs-instruction_handler + db 'ldaex~~',0x00 + dw ARM_instruction_ldaex-instruction_handler + db 'ldc2l~~',0x00 + dw ARM_instruction_ldc2l-instruction_handler + db 'ldmda~~',0x00 + dw ARM_instruction_ldmda-instruction_handler + db 'ldmdb~~',0x00 + dw ARM_instruction_ldmdb-instruction_handler + db 'ldmea~~',0x00 + dw ARM_instruction_ldmea-instruction_handler + db 'ldmed~~',0x00 + dw ARM_instruction_ldmed-instruction_handler + db 'ldmfa~~',0x00 + dw ARM_instruction_ldmfa-instruction_handler + db 'ldmfd.n',0xe4 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmfd.w',0xe2 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmfd~~',0x00 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmia.n',0xe4 + dw ARM_instruction_ldmia-instruction_handler + db 'ldmia.w',0xe2 + dw ARM_instruction_ldmia-instruction_handler + db 'ldmia~~',0x00 + dw ARM_instruction_ldmia-instruction_handler + db 'ldmib~~',0x00 + dw ARM_instruction_ldmib-instruction_handler + db 'ldm~~.n',0x04 + dw ARM_instruction_ldm-instruction_handler + db 'ldm~~.w',0x02 + dw ARM_instruction_ldm-instruction_handler + db 'ldm~~da',0x00 + dw ARM_instruction_ldmda-instruction_handler + db 'ldm~~db',0x00 + dw ARM_instruction_ldmdb-instruction_handler + db 'ldm~~ea',0x00 + dw ARM_instruction_ldmea-instruction_handler + db 'ldm~~ed',0x00 + dw ARM_instruction_ldmed-instruction_handler + db 'ldm~~fa',0x00 + dw ARM_instruction_ldmfa-instruction_handler + db 'ldm~~fd',0x00 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldm~~ia',0x00 + dw ARM_instruction_ldmia-instruction_handler + db 'ldm~~ib',0x00 + dw ARM_instruction_ldmib-instruction_handler + db 'ldrbt~~',0x00 + dw ARM_instruction_ldrbt-instruction_handler + db 'ldrex~~',0x00 + dw ARM_instruction_ldrex-instruction_handler + db 'ldrht~~',0x00 + dw ARM_instruction_ldrht-instruction_handler + db 'ldrsb.n',0xe4 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsb.w',0xe2 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsb~~',0x00 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsh.n',0xe4 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldrsh.w',0xe2 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldrsh~~',0x00 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldr~~.n',0x04 + dw ARM_instruction_ldr-instruction_handler + db 'ldr~~.w',0x02 + dw ARM_instruction_ldr-instruction_handler + db 'ldr~~bt',0x00 + dw ARM_instruction_ldrbt-instruction_handler + db 'ldr~~ht',0x00 + dw ARM_instruction_ldrht-instruction_handler + db 'ldr~~sb',0x00 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldr~~sh',0x00 + dw ARM_instruction_ldrsh-instruction_handler + db 'lfm~~ea',0x00 + dw ARM_instruction_lfmea-instruction_handler + db 'lfm~~fd',0x00 + dw ARM_instruction_lfmfd-instruction_handler + db 'lgn~~dm',0x00 + dw ARM_instruction_lgndm-instruction_handler + db 'lgn~~dp',0x00 + dw ARM_instruction_lgndp-instruction_handler + db 'lgn~~dz',0x00 + dw ARM_instruction_lgndz-instruction_handler + db 'lgn~~em',0x00 + dw ARM_instruction_lgnem-instruction_handler + db 'lgn~~ep',0x00 + dw ARM_instruction_lgnep-instruction_handler + db 'lgn~~ez',0x00 + dw ARM_instruction_lgnez-instruction_handler + db 'lgn~~sm',0x00 + dw ARM_instruction_lgnsm-instruction_handler + db 'lgn~~sp',0x00 + dw ARM_instruction_lgnsp-instruction_handler + db 'lgn~~sz',0x00 + dw ARM_instruction_lgnsz-instruction_handler + db 'log~~dm',0x00 + dw ARM_instruction_logdm-instruction_handler + db 'log~~dp',0x00 + dw ARM_instruction_logdp-instruction_handler + db 'log~~dz',0x00 + dw ARM_instruction_logdz-instruction_handler + db 'log~~em',0x00 + dw ARM_instruction_logem-instruction_handler + db 'log~~ep',0x00 + dw ARM_instruction_logep-instruction_handler + db 'log~~ez',0x00 + dw ARM_instruction_logez-instruction_handler + db 'log~~sm',0x00 + dw ARM_instruction_logsm-instruction_handler + db 'log~~sp',0x00 + dw ARM_instruction_logsp-instruction_handler + db 'log~~sz',0x00 + dw ARM_instruction_logsz-instruction_handler + db 'lsl~~.n',0x04 + dw ARM_instruction_lsl-instruction_handler + db 'lsl~~.w',0x02 + dw ARM_instruction_lsl-instruction_handler + db 'lsr~~.n',0x04 + dw ARM_instruction_lsr-instruction_handler + db 'lsr~~.w',0x02 + dw ARM_instruction_lsr-instruction_handler + db 'mcrr2~~',0x00 + dw ARM_instruction_mcrr2-instruction_handler + db 'miabb~~',0x00 + dw ARM_instruction_miabb-instruction_handler + db 'miabt~~',0x00 + dw ARM_instruction_miabt-instruction_handler + db 'miaph~~',0x00 + dw ARM_instruction_miaph-instruction_handler + db 'miatb~~',0x00 + dw ARM_instruction_miatb-instruction_handler + db 'miatt~~',0x00 + dw ARM_instruction_miatt-instruction_handler + db 'mnf~~dm',0x00 + dw ARM_instruction_mnfdm-instruction_handler + db 'mnf~~dp',0x00 + dw ARM_instruction_mnfdp-instruction_handler + db 'mnf~~dz',0x00 + dw ARM_instruction_mnfdz-instruction_handler + db 'mnf~~em',0x00 + dw ARM_instruction_mnfem-instruction_handler + db 'mnf~~ep',0x00 + dw ARM_instruction_mnfep-instruction_handler + db 'mnf~~ez',0x00 + dw ARM_instruction_mnfez-instruction_handler + db 'mnf~~sm',0x00 + dw ARM_instruction_mnfsm-instruction_handler + db 'mnf~~sp',0x00 + dw ARM_instruction_mnfsp-instruction_handler + db 'mnf~~sz',0x00 + dw ARM_instruction_mnfsz-instruction_handler + db 'mov~~.n',0x04 + dw ARM_instruction_mov-instruction_handler + db 'mov~~.w',0x02 + dw ARM_instruction_mov-instruction_handler + db 'mrrc2~~',0x00 + dw ARM_instruction_mrrc2-instruction_handler + db 'muf~~dm',0x00 + dw ARM_instruction_mufdm-instruction_handler + db 'muf~~dp',0x00 + dw ARM_instruction_mufdp-instruction_handler + db 'muf~~dz',0x00 + dw ARM_instruction_mufdz-instruction_handler + db 'muf~~em',0x00 + dw ARM_instruction_mufem-instruction_handler + db 'muf~~ep',0x00 + dw ARM_instruction_mufep-instruction_handler + db 'muf~~ez',0x00 + dw ARM_instruction_mufez-instruction_handler + db 'muf~~sm',0x00 + dw ARM_instruction_mufsm-instruction_handler + db 'muf~~sp',0x00 + dw ARM_instruction_mufsp-instruction_handler + db 'muf~~sz',0x00 + dw ARM_instruction_mufsz-instruction_handler + db 'mul~~.n',0x04 + dw ARM_instruction_mul-instruction_handler + db 'mul~~.w',0x02 + dw ARM_instruction_mul-instruction_handler + db 'mvf~~dm',0x00 + dw ARM_instruction_mvfdm-instruction_handler + db 'mvf~~dp',0x00 + dw ARM_instruction_mvfdp-instruction_handler + db 'mvf~~dz',0x00 + dw ARM_instruction_mvfdz-instruction_handler + db 'mvf~~em',0x00 + dw ARM_instruction_mvfem-instruction_handler + db 'mvf~~ep',0x00 + dw ARM_instruction_mvfep-instruction_handler + db 'mvf~~ez',0x00 + dw ARM_instruction_mvfez-instruction_handler + db 'mvf~~sm',0x00 + dw ARM_instruction_mvfsm-instruction_handler + db 'mvf~~sp',0x00 + dw ARM_instruction_mvfsp-instruction_handler + db 'mvf~~sz',0x00 + dw ARM_instruction_mvfsz-instruction_handler + db 'mvn~~.n',0x04 + dw ARM_instruction_mvn-instruction_handler + db 'mvn~~.w',0x02 + dw ARM_instruction_mvn-instruction_handler + db 'neg~~.n',0x04 + dw ARM_instruction_neg-instruction_handler + db 'neg~~.w',0x02 + dw ARM_instruction_neg-instruction_handler + db 'nop~~.n',0x04 + dw ARM_instruction_nop-instruction_handler + db 'nop~~.w',0x02 + dw ARM_instruction_nop-instruction_handler + db 'nrm~~dm',0x00 + dw ARM_instruction_nrmdm-instruction_handler + db 'nrm~~dp',0x00 + dw ARM_instruction_nrmdp-instruction_handler + db 'nrm~~dz',0x00 + dw ARM_instruction_nrmdz-instruction_handler + db 'nrm~~em',0x00 + dw ARM_instruction_nrmem-instruction_handler + db 'nrm~~ep',0x00 + dw ARM_instruction_nrmep-instruction_handler + db 'nrm~~ez',0x00 + dw ARM_instruction_nrmez-instruction_handler + db 'nrm~~sm',0x00 + dw ARM_instruction_nrmsm-instruction_handler + db 'nrm~~sp',0x00 + dw ARM_instruction_nrmsp-instruction_handler + db 'nrm~~sz',0x00 + dw ARM_instruction_nrmsz-instruction_handler + db 'orr~~.n',0x04 + dw ARM_instruction_orr-instruction_handler + db 'orr~~.w',0x02 + dw ARM_instruction_orr-instruction_handler + db 'pkhbt~~',0x00 + dw ARM_instruction_pkhbt-instruction_handler + db 'pkhtb~~',0x00 + dw ARM_instruction_pkhtb-instruction_handler + db 'pol~~dm',0x00 + dw ARM_instruction_poldm-instruction_handler + db 'pol~~dp',0x00 + dw ARM_instruction_poldp-instruction_handler + db 'pol~~dz',0x00 + dw ARM_instruction_poldz-instruction_handler + db 'pol~~em',0x00 + dw ARM_instruction_polem-instruction_handler + db 'pol~~ep',0x00 + dw ARM_instruction_polep-instruction_handler + db 'pol~~ez',0x00 + dw ARM_instruction_polez-instruction_handler + db 'pol~~sm',0x00 + dw ARM_instruction_polsm-instruction_handler + db 'pol~~sp',0x00 + dw ARM_instruction_polsp-instruction_handler + db 'pol~~sz',0x00 + dw ARM_instruction_polsz-instruction_handler + db 'pop~~.n',0x04 + dw ARM_instruction_pop-instruction_handler + db 'pop~~.w',0x02 + dw ARM_instruction_pop-instruction_handler + db 'pow~~dm',0x00 + dw ARM_instruction_powdm-instruction_handler + db 'pow~~dp',0x00 + dw ARM_instruction_powdp-instruction_handler + db 'pow~~dz',0x00 + dw ARM_instruction_powdz-instruction_handler + db 'pow~~em',0x00 + dw ARM_instruction_powem-instruction_handler + db 'pow~~ep',0x00 + dw ARM_instruction_powep-instruction_handler + db 'pow~~ez',0x00 + dw ARM_instruction_powez-instruction_handler + db 'pow~~sm',0x00 + dw ARM_instruction_powsm-instruction_handler + db 'pow~~sp',0x00 + dw ARM_instruction_powsp-instruction_handler + db 'pow~~sz',0x00 + dw ARM_instruction_powsz-instruction_handler + db 'qadd8~~',0x00 + dw ARM_instruction_qadd8-instruction_handler + db 'qdadd~~',0x00 + dw ARM_instruction_qdadd-instruction_handler + db 'qdsub~~',0x00 + dw ARM_instruction_qdsub-instruction_handler + db 'qsub8~~',0x00 + dw ARM_instruction_qsub8-instruction_handler + db 'raddhn2',0xf0 + dw ARM_instruction_raddhn2-instruction_handler + db 'rdf~~dm',0x00 + dw ARM_instruction_rdfdm-instruction_handler + db 'rdf~~dp',0x00 + dw ARM_instruction_rdfdp-instruction_handler + db 'rdf~~dz',0x00 + dw ARM_instruction_rdfdz-instruction_handler + db 'rdf~~em',0x00 + dw ARM_instruction_rdfem-instruction_handler + db 'rdf~~ep',0x00 + dw ARM_instruction_rdfep-instruction_handler + db 'rdf~~ez',0x00 + dw ARM_instruction_rdfez-instruction_handler + db 'rdf~~sm',0x00 + dw ARM_instruction_rdfsm-instruction_handler + db 'rdf~~sp',0x00 + dw ARM_instruction_rdfsp-instruction_handler + db 'rdf~~sz',0x00 + dw ARM_instruction_rdfsz-instruction_handler + db 'rev16.n',0xe4 + dw ARM_instruction_rev16-instruction_handler + db 'rev16.w',0xe2 + dw ARM_instruction_rev16-instruction_handler + db 'rev16~~',0x00 + dw ARM_instruction_rev16-instruction_handler + db 'revsh.n',0xe4 + dw ARM_instruction_revsh-instruction_handler + db 'revsh.w',0xe2 + dw ARM_instruction_revsh-instruction_handler + db 'revsh~~',0x00 + dw ARM_instruction_revsh-instruction_handler + db 'rev~~.n',0x04 + dw ARM_instruction_rev-instruction_handler + db 'rev~~.w',0x02 + dw ARM_instruction_rev-instruction_handler + db 'rmf~~dm',0x00 + dw ARM_instruction_rmfdm-instruction_handler + db 'rmf~~dp',0x00 + dw ARM_instruction_rmfdp-instruction_handler + db 'rmf~~dz',0x00 + dw ARM_instruction_rmfdz-instruction_handler + db 'rmf~~em',0x00 + dw ARM_instruction_rmfem-instruction_handler + db 'rmf~~ep',0x00 + dw ARM_instruction_rmfep-instruction_handler + db 'rmf~~ez',0x00 + dw ARM_instruction_rmfez-instruction_handler + db 'rmf~~sm',0x00 + dw ARM_instruction_rmfsm-instruction_handler + db 'rmf~~sp',0x00 + dw ARM_instruction_rmfsp-instruction_handler + db 'rmf~~sz',0x00 + dw ARM_instruction_rmfsz-instruction_handler + db 'rnd~~dm',0x00 + dw ARM_instruction_rnddm-instruction_handler + db 'rnd~~dp',0x00 + dw ARM_instruction_rnddp-instruction_handler + db 'rnd~~dz',0x00 + dw ARM_instruction_rnddz-instruction_handler + db 'rnd~~em',0x00 + dw ARM_instruction_rndem-instruction_handler + db 'rnd~~ep',0x00 + dw ARM_instruction_rndep-instruction_handler + db 'rnd~~ez',0x00 + dw ARM_instruction_rndez-instruction_handler + db 'rnd~~sm',0x00 + dw ARM_instruction_rndsm-instruction_handler + db 'rnd~~sp',0x00 + dw ARM_instruction_rndsp-instruction_handler + db 'rnd~~sz',0x00 + dw ARM_instruction_rndsz-instruction_handler + db 'ror~~.n',0x04 + dw ARM_instruction_ror-instruction_handler + db 'ror~~.w',0x02 + dw ARM_instruction_ror-instruction_handler + db 'rpw~~dm',0x00 + dw ARM_instruction_rpwdm-instruction_handler + db 'rpw~~dp',0x00 + dw ARM_instruction_rpwdp-instruction_handler + db 'rpw~~dz',0x00 + dw ARM_instruction_rpwdz-instruction_handler + db 'rpw~~em',0x00 + dw ARM_instruction_rpwem-instruction_handler + db 'rpw~~ep',0x00 + dw ARM_instruction_rpwep-instruction_handler + db 'rpw~~ez',0x00 + dw ARM_instruction_rpwez-instruction_handler + db 'rpw~~sm',0x00 + dw ARM_instruction_rpwsm-instruction_handler + db 'rpw~~sp',0x00 + dw ARM_instruction_rpwsp-instruction_handler + db 'rpw~~sz',0x00 + dw ARM_instruction_rpwsz-instruction_handler + db 'rsb~~.n',0x04 + dw ARM_instruction_rsb-instruction_handler + db 'rsb~~.w',0x02 + dw ARM_instruction_rsb-instruction_handler + db 'rsf~~dm',0x00 + dw ARM_instruction_rsfdm-instruction_handler + db 'rsf~~dp',0x00 + dw ARM_instruction_rsfdp-instruction_handler + db 'rsf~~dz',0x00 + dw ARM_instruction_rsfdz-instruction_handler + db 'rsf~~em',0x00 + dw ARM_instruction_rsfem-instruction_handler + db 'rsf~~ep',0x00 + dw ARM_instruction_rsfep-instruction_handler + db 'rsf~~ez',0x00 + dw ARM_instruction_rsfez-instruction_handler + db 'rsf~~sm',0x00 + dw ARM_instruction_rsfsm-instruction_handler + db 'rsf~~sp',0x00 + dw ARM_instruction_rsfsp-instruction_handler + db 'rsf~~sz',0x00 + dw ARM_instruction_rsfsz-instruction_handler + db 'rsubhn2',0xf0 + dw ARM_instruction_rsubhn2-instruction_handler + db 'sadd8~~',0x00 + dw ARM_instruction_sadd8-instruction_handler + db 'sbc~~.n',0x04 + dw ARM_instruction_sbc-instruction_handler + db 'sbc~~.w',0x02 + dw ARM_instruction_sbc-instruction_handler + db 'section',0x00 + dw ARM_section_directive-instruction_handler + db 'segment',0x00 + dw segment_directive-instruction_handler + db 'sev~~.n',0x04 + dw ARM_instruction_sev-instruction_handler + db 'sev~~.w',0x02 + dw ARM_instruction_sev-instruction_handler + db 'sfm~~ea',0x00 + dw ARM_instruction_sfmea-instruction_handler + db 'sfm~~fd',0x00 + dw ARM_instruction_sfmfd-instruction_handler + db 'sha1su0',0xf0 + dw ARM_instruction_sha1su0-instruction_handler + db 'sha1su1',0xf0 + dw ARM_instruction_sha1su1-instruction_handler + db 'sha256h',0xf0 + dw ARM_instruction_sha256h-instruction_handler + db 'shadd16',0xe0 + dw ARM_instruction_shadd16-instruction_handler + db 'shasx~~',0x00 + dw ARM_instruction_shasx-instruction_handler + db 'shsax~~',0x00 + dw ARM_instruction_shsax-instruction_handler + db 'shsub16',0xe0 + dw ARM_instruction_shsub16-instruction_handler + db 'sin~~dm',0x00 + dw ARM_instruction_sindm-instruction_handler + db 'sin~~dp',0x00 + dw ARM_instruction_sindp-instruction_handler + db 'sin~~dz',0x00 + dw ARM_instruction_sindz-instruction_handler + db 'sin~~em',0x00 + dw ARM_instruction_sinem-instruction_handler + db 'sin~~ep',0x00 + dw ARM_instruction_sinep-instruction_handler + db 'sin~~ez',0x00 + dw ARM_instruction_sinez-instruction_handler + db 'sin~~sm',0x00 + dw ARM_instruction_sinsm-instruction_handler + db 'sin~~sp',0x00 + dw ARM_instruction_sinsp-instruction_handler + db 'sin~~sz',0x00 + dw ARM_instruction_sinsz-instruction_handler + db 'smlad~~',0x00 + dw ARM_instruction_smlad-instruction_handler + db 'smlalbb',0xe0 + dw ARM_instruction_smlalbb-instruction_handler + db 'smlalbt',0xe0 + dw ARM_instruction_smlalbt-instruction_handler + db 'smlaldx',0xe0 + dw ARM_instruction_smlaldx-instruction_handler + db 'smlaltb',0xe0 + dw ARM_instruction_smlaltb-instruction_handler + db 'smlaltt',0xe0 + dw ARM_instruction_smlaltt-instruction_handler + db 'smlal~~',0x00 + dw ARM_instruction_smlal-instruction_handler + db 'smlsd~~',0x00 + dw ARM_instruction_smlsd-instruction_handler + db 'smlsldx',0xe0 + dw ARM_instruction_smlsldx-instruction_handler + db 'smmla~~',0x00 + dw ARM_instruction_smmla-instruction_handler + db 'smmls~~',0x00 + dw ARM_instruction_smmls-instruction_handler + db 'smmul~~',0x00 + dw ARM_instruction_smmul-instruction_handler + db 'smuad~~',0x00 + dw ARM_instruction_smuad-instruction_handler + db 'smull~~',0x00 + dw ARM_instruction_smull-instruction_handler + db 'smusd~~',0x00 + dw ARM_instruction_smusd-instruction_handler + db 'sqdmlal',0xf0 + dw ARM_instruction_sqdmlal-instruction_handler + db 'sqdmlsl',0xf0 + dw ARM_instruction_sqdmlsl-instruction_handler + db 'sqdmulh',0xf0 + dw ARM_instruction_sqdmulh-instruction_handler + db 'sqdmull',0xf0 + dw ARM_instruction_sqdmull-instruction_handler + db 'sqrshrn',0xf0 + dw ARM_instruction_sqrshrn-instruction_handler + db 'sqshrn2',0xf0 + dw ARM_instruction_sqshrn2-instruction_handler + db 'sqshrun',0xf0 + dw ARM_instruction_sqshrun-instruction_handler + db 'sqt~~dm',0x00 + dw ARM_instruction_sqtdm-instruction_handler + db 'sqt~~dp',0x00 + dw ARM_instruction_sqtdp-instruction_handler + db 'sqt~~dz',0x00 + dw ARM_instruction_sqtdz-instruction_handler + db 'sqt~~em',0x00 + dw ARM_instruction_sqtem-instruction_handler + db 'sqt~~ep',0x00 + dw ARM_instruction_sqtep-instruction_handler + db 'sqt~~ez',0x00 + dw ARM_instruction_sqtez-instruction_handler + db 'sqt~~sm',0x00 + dw ARM_instruction_sqtsm-instruction_handler + db 'sqt~~sp',0x00 + dw ARM_instruction_sqtsp-instruction_handler + db 'sqt~~sz',0x00 + dw ARM_instruction_sqtsz-instruction_handler + db 'sqxtun2',0xf0 + dw ARM_instruction_sqxtun2-instruction_handler + db 'ssub8~~',0x00 + dw ARM_instruction_ssub8-instruction_handler + db 'stc2l~~',0x00 + dw ARM_instruction_stc2l-instruction_handler + db 'stlex~~',0x00 + dw ARM_instruction_stlex-instruction_handler + db 'stmda~~',0x00 + dw ARM_instruction_stmda-instruction_handler + db 'stmdb.n',0xe4 + dw ARM_instruction_stmdb-instruction_handler + db 'stmdb.w',0xe2 + dw ARM_instruction_stmdb-instruction_handler + db 'stmdb~~',0x00 + dw ARM_instruction_stmdb-instruction_handler + db 'stmea~~',0x00 + dw ARM_instruction_stmea-instruction_handler + db 'stmed~~',0x00 + dw ARM_instruction_stmed-instruction_handler + db 'stmfa~~',0x00 + dw ARM_instruction_stmfa-instruction_handler + db 'stmfd.n',0xe4 + dw ARM_instruction_stmfd-instruction_handler + db 'stmfd.w',0xe2 + dw ARM_instruction_stmfd-instruction_handler + db 'stmfd~~',0x00 + dw ARM_instruction_stmfd-instruction_handler + db 'stmia.n',0xe4 + dw ARM_instruction_stmia-instruction_handler + db 'stmia.w',0xe2 + dw ARM_instruction_stmia-instruction_handler + db 'stmia~~',0x00 + dw ARM_instruction_stmia-instruction_handler + db 'stmib~~',0x00 + dw ARM_instruction_stmib-instruction_handler + db 'stm~~.n',0x04 + dw ARM_instruction_stm-instruction_handler + db 'stm~~.w',0x02 + dw ARM_instruction_stm-instruction_handler + db 'stm~~da',0x00 + dw ARM_instruction_stmda-instruction_handler + db 'stm~~db',0x00 + dw ARM_instruction_stmdb-instruction_handler + db 'stm~~ea',0x00 + dw ARM_instruction_stmea-instruction_handler + db 'stm~~ed',0x00 + dw ARM_instruction_stmed-instruction_handler + db 'stm~~fa',0x00 + dw ARM_instruction_stmfa-instruction_handler + db 'stm~~fd',0x00 + dw ARM_instruction_stmfd-instruction_handler + db 'stm~~ia',0x00 + dw ARM_instruction_stmia-instruction_handler + db 'stm~~ib',0x00 + dw ARM_instruction_stmib-instruction_handler + db 'strbt~~',0x00 + dw ARM_instruction_strbt-instruction_handler + db 'strex~~',0x00 + dw ARM_instruction_strex-instruction_handler + db 'strht~~',0x00 + dw ARM_instruction_strht-instruction_handler + db 'str~~.n',0x04 + dw ARM_instruction_str-instruction_handler + db 'str~~.w',0x02 + dw ARM_instruction_str-instruction_handler + db 'str~~bt',0x00 + dw ARM_instruction_strbt-instruction_handler + db 'str~~ht',0x00 + dw ARM_instruction_strht-instruction_handler + db 'sub~~.n',0x04 + dw ARM_instruction_sub-instruction_handler + db 'sub~~.w',0x02 + dw ARM_instruction_sub-instruction_handler + db 'suf~~dm',0x00 + dw ARM_instruction_sufdm-instruction_handler + db 'suf~~dp',0x00 + dw ARM_instruction_sufdp-instruction_handler + db 'suf~~dz',0x00 + dw ARM_instruction_sufdz-instruction_handler + db 'suf~~em',0x00 + dw ARM_instruction_sufem-instruction_handler + db 'suf~~ep',0x00 + dw ARM_instruction_sufep-instruction_handler + db 'suf~~ez',0x00 + dw ARM_instruction_sufez-instruction_handler + db 'suf~~sm',0x00 + dw ARM_instruction_sufsm-instruction_handler + db 'suf~~sp',0x00 + dw ARM_instruction_sufsp-instruction_handler + db 'suf~~sz',0x00 + dw ARM_instruction_sufsz-instruction_handler + db 'svc~~.n',0x04 + dw ARM_instruction_svc-instruction_handler + db 'svc~~.w',0x02 + dw ARM_instruction_svc-instruction_handler + db 'swi~~.n',0x04 + dw ARM_instruction_swi-instruction_handler + db 'swi~~.w',0x02 + dw ARM_instruction_swi-instruction_handler + db 'sxtab16',0xe0 + dw ARM_instruction_sxtab16-instruction_handler + db 'sxtab~~',0x00 + dw ARM_instruction_sxtab-instruction_handler + db 'sxtah~~',0x00 + dw ARM_instruction_sxtah-instruction_handler + db 'tan~~dm',0x00 + dw ARM_instruction_tandm-instruction_handler + db 'tan~~dp',0x00 + dw ARM_instruction_tandp-instruction_handler + db 'tan~~dz',0x00 + dw ARM_instruction_tandz-instruction_handler + db 'tan~~em',0x00 + dw ARM_instruction_tanem-instruction_handler + db 'tan~~ep',0x00 + dw ARM_instruction_tanep-instruction_handler + db 'tan~~ez',0x00 + dw ARM_instruction_tanez-instruction_handler + db 'tan~~sm',0x00 + dw ARM_instruction_tansm-instruction_handler + db 'tan~~sp',0x00 + dw ARM_instruction_tansp-instruction_handler + db 'tan~~sz',0x00 + dw ARM_instruction_tansz-instruction_handler + db 'textrcb',0xe0 + dw ARM_instruction_textrcb-instruction_handler + db 'textrch',0xe0 + dw ARM_instruction_textrch-instruction_handler + db 'textrcw',0xe0 + dw ARM_instruction_textrcw-instruction_handler + db 'thumbee',0x00 + dw ARM_thumbee_directive-instruction_handler + db 'tmcrr~~',0x00 + dw ARM_instruction_tmcrr-instruction_handler + db 'tmrrc~~',0x00 + dw ARM_instruction_tmrrc-instruction_handler + db 'torcb~~',0x00 + dw ARM_instruction_torcb-instruction_handler + db 'torch~~',0x00 + dw ARM_instruction_torch-instruction_handler + db 'torcw~~',0x00 + dw ARM_instruction_torcw-instruction_handler + db 'torvscb',0xe0 + dw ARM_instruction_torvscb-instruction_handler + db 'torvsch',0xe0 + dw ARM_instruction_torvsch-instruction_handler + db 'torvscw',0xe0 + dw ARM_instruction_torvscw-instruction_handler + db 'tst~~.n',0x04 + dw ARM_instruction_tst-instruction_handler + db 'tst~~.w',0x02 + dw ARM_instruction_tst-instruction_handler + db 'uadd8~~',0x00 + dw ARM_instruction_uadd8-instruction_handler + db 'uhadd16',0xe0 + dw ARM_instruction_uhadd16-instruction_handler + db 'uhasx~~',0x00 + dw ARM_instruction_uhasx-instruction_handler + db 'uhsax~~',0x00 + dw ARM_instruction_uhsax-instruction_handler + db 'uhsub16',0xe0 + dw ARM_instruction_uhsub16-instruction_handler + db 'umaal~~',0x00 + dw ARM_instruction_umaal-instruction_handler + db 'umlal~~',0x00 + dw ARM_instruction_umlal-instruction_handler + db 'umull~~',0x00 + dw ARM_instruction_umull-instruction_handler + db 'und~~.n',0x04 + dw ARM_instruction_und-instruction_handler + db 'und~~.w',0x02 + dw ARM_instruction_und-instruction_handler + db 'uqadd16',0xe0 + dw ARM_instruction_uqadd16-instruction_handler + db 'uqasx~~',0x00 + dw ARM_instruction_uqasx-instruction_handler + db 'uqrshrn',0xf0 + dw ARM_instruction_uqrshrn-instruction_handler + db 'uqsax~~',0x00 + dw ARM_instruction_uqsax-instruction_handler + db 'uqshrn2',0xf0 + dw ARM_instruction_uqshrn2-instruction_handler + db 'uqsub16',0xe0 + dw ARM_instruction_uqsub16-instruction_handler + db 'urd~~dm',0x00 + dw ARM_instruction_urddm-instruction_handler + db 'urd~~dp',0x00 + dw ARM_instruction_urddp-instruction_handler + db 'urd~~dz',0x00 + dw ARM_instruction_urddz-instruction_handler + db 'urd~~em',0x00 + dw ARM_instruction_urdem-instruction_handler + db 'urd~~ep',0x00 + dw ARM_instruction_urdep-instruction_handler + db 'urd~~ez',0x00 + dw ARM_instruction_urdez-instruction_handler + db 'urd~~sm',0x00 + dw ARM_instruction_urdsm-instruction_handler + db 'urd~~sp',0x00 + dw ARM_instruction_urdsp-instruction_handler + db 'urd~~sz',0x00 + dw ARM_instruction_urdsz-instruction_handler + db 'ursqrte',0xf0 + dw ARM_instruction_ursqrte-instruction_handler + db 'usad8~~',0x00 + dw ARM_instruction_usad8-instruction_handler + db 'usub8~~',0x00 + dw ARM_instruction_usub8-instruction_handler + db 'uxtab16',0xe0 + dw ARM_instruction_uxtab16-instruction_handler + db 'uxtab~~',0x00 + dw ARM_instruction_uxtab-instruction_handler + db 'uxtah~~',0x00 + dw ARM_instruction_uxtah-instruction_handler + db 'vaba.s8',0xe0 + dw ARM_instruction_vaba.s8-instruction_handler + db 'vaba.u8',0xe0 + dw ARM_instruction_vaba.u8-instruction_handler + db 'vabd.s8',0xe0 + dw ARM_instruction_vabd.s8-instruction_handler + db 'vabd.u8',0xe0 + dw ARM_instruction_vabd.u8-instruction_handler + db 'vabs.s8',0xe0 + dw ARM_instruction_vabs.s8-instruction_handler + db 'vadd.i8',0xe0 + dw ARM_instruction_vadd.i8-instruction_handler + db 'vceq.i8',0xe0 + dw ARM_instruction_vceq.i8-instruction_handler + db 'vcge.s8',0xe0 + dw ARM_instruction_vcge.s8-instruction_handler + db 'vcge.u8',0xe0 + dw ARM_instruction_vcge.u8-instruction_handler + db 'vcgt.s8',0xe0 + dw ARM_instruction_vcgt.s8-instruction_handler + db 'vcgt.u8',0xe0 + dw ARM_instruction_vcgt.u8-instruction_handler + db 'vcle.s8',0xe0 + dw ARM_instruction_vcle.s8-instruction_handler + db 'vcle.u8',0xe0 + dw ARM_instruction_vcle.u8-instruction_handler + db 'vcls.s8',0xe0 + dw ARM_instruction_vcls.s8-instruction_handler + db 'vclt.s8',0xe0 + dw ARM_instruction_vclt.s8-instruction_handler + db 'vclt.u8',0xe0 + dw ARM_instruction_vclt.u8-instruction_handler + db 'vclz.i8',0xe0 + dw ARM_instruction_vclz.i8-instruction_handler + db 'vdup.16',0xe0 + dw ARM_instruction_vdup.16-instruction_handler + db 'vdup.32',0xe0 + dw ARM_instruction_vdup.32-instruction_handler + db 'vext.16',0xe0 + dw ARM_instruction_vext.16-instruction_handler + db 'vext.32',0xe0 + dw ARM_instruction_vext.32-instruction_handler + db 'vext.64',0xe0 + dw ARM_instruction_vext.64-instruction_handler + db 'virtual',0x00 + dw virtual_directive-instruction_handler + db 'vld1.16',0xe0 + dw ARM_instruction_vld1.16-instruction_handler + db 'vld1.32',0xe0 + dw ARM_instruction_vld1.32-instruction_handler + db 'vld1.64',0xe0 + dw ARM_instruction_vld1.64-instruction_handler + db 'vld2.16',0xe0 + dw ARM_instruction_vld2.16-instruction_handler + db 'vld2.32',0xe0 + dw ARM_instruction_vld2.32-instruction_handler + db 'vld3.16',0xe0 + dw ARM_instruction_vld3.16-instruction_handler + db 'vld3.32',0xe0 + dw ARM_instruction_vld3.32-instruction_handler + db 'vld4.16',0xe0 + dw ARM_instruction_vld4.16-instruction_handler + db 'vld4.32',0xe0 + dw ARM_instruction_vld4.32-instruction_handler + db 'vldm.32',0xe0 + dw ARM_instruction_vldm.32-instruction_handler + db 'vldm.64',0xe0 + dw ARM_instruction_vldm.64-instruction_handler + db 'vldr.32',0xe0 + dw ARM_instruction_vldr.32-instruction_handler + db 'vldr.64',0xe0 + dw ARM_instruction_vldr.64-instruction_handler + db 'vmax.s8',0xe0 + dw ARM_instruction_vmax.s8-instruction_handler + db 'vmax.u8',0xe0 + dw ARM_instruction_vmax.u8-instruction_handler + db 'vmin.s8',0xe0 + dw ARM_instruction_vmin.s8-instruction_handler + db 'vmin.u8',0xe0 + dw ARM_instruction_vmin.u8-instruction_handler + db 'vmla.i8',0xe0 + dw ARM_instruction_vmla.i8-instruction_handler + db 'vmla.s8',0xe0 + dw ARM_instruction_vmla.s8-instruction_handler + db 'vmla.u8',0xe0 + dw ARM_instruction_vmla.u8-instruction_handler + db 'vmls.i8',0xe0 + dw ARM_instruction_vmls.i8-instruction_handler + db 'vmls.s8',0xe0 + dw ARM_instruction_vmls.s8-instruction_handler + db 'vmls.u8',0xe0 + dw ARM_instruction_vmls.u8-instruction_handler + db 'vmov.16',0xe0 + dw ARM_instruction_vmov.16-instruction_handler + db 'vmov.32',0xe0 + dw ARM_instruction_vmov.32-instruction_handler + db 'vmov.i8',0xe0 + dw ARM_instruction_vmov.i8-instruction_handler + db 'vmov.s8',0xe0 + dw ARM_instruction_vmov.s8-instruction_handler + db 'vmov.u8',0xe0 + dw ARM_instruction_vmov.u8-instruction_handler + db 'vmul.i8',0xe0 + dw ARM_instruction_vmul.i8-instruction_handler + db 'vmul.p8',0xe0 + dw ARM_instruction_vmul.p8-instruction_handler + db 'vmul.s8',0xe0 + dw ARM_instruction_vmul.s8-instruction_handler + db 'vmul.u8',0xe0 + dw ARM_instruction_vmul.u8-instruction_handler + db 'vneg.s8',0xe0 + dw ARM_instruction_vneg.s8-instruction_handler + db 'vpop.32',0xe0 + dw ARM_instruction_vpop.32-instruction_handler + db 'vpop.64',0xe0 + dw ARM_instruction_vpop.64-instruction_handler + db 'vpush~~',0x00 + dw ARM_instruction_vpush-instruction_handler + db 'vshl.i8',0xe0 + dw ARM_instruction_vshl.i8-instruction_handler + db 'vshl.s8',0xe0 + dw ARM_instruction_vshl.s8-instruction_handler + db 'vshl.u8',0xe0 + dw ARM_instruction_vshl.u8-instruction_handler + db 'vshr.s8',0xe0 + dw ARM_instruction_vshr.s8-instruction_handler + db 'vshr.u8',0xe0 + dw ARM_instruction_vshr.u8-instruction_handler + db 'vsli.16',0xe0 + dw ARM_instruction_vsli.16-instruction_handler + db 'vsli.32',0xe0 + dw ARM_instruction_vsli.32-instruction_handler + db 'vsli.64',0xe0 + dw ARM_instruction_vsli.64-instruction_handler + db 'vsra.s8',0xe0 + dw ARM_instruction_vsra.s8-instruction_handler + db 'vsra.u8',0xe0 + dw ARM_instruction_vsra.u8-instruction_handler + db 'vsri.16',0xe0 + dw ARM_instruction_vsri.16-instruction_handler + db 'vsri.32',0xe0 + dw ARM_instruction_vsri.32-instruction_handler + db 'vsri.64',0xe0 + dw ARM_instruction_vsri.64-instruction_handler + db 'vst1.16',0xe0 + dw ARM_instruction_vst1.16-instruction_handler + db 'vst1.32',0xe0 + dw ARM_instruction_vst1.32-instruction_handler + db 'vst1.64',0xe0 + dw ARM_instruction_vst1.64-instruction_handler + db 'vst2.16',0xe0 + dw ARM_instruction_vst2.16-instruction_handler + db 'vst2.32',0xe0 + dw ARM_instruction_vst2.32-instruction_handler + db 'vst3.16',0xe0 + dw ARM_instruction_vst3.16-instruction_handler + db 'vst3.32',0xe0 + dw ARM_instruction_vst3.32-instruction_handler + db 'vst4.16',0xe0 + dw ARM_instruction_vst4.16-instruction_handler + db 'vst4.32',0xe0 + dw ARM_instruction_vst4.32-instruction_handler + db 'vstm.32',0xe0 + dw ARM_instruction_vstm.32-instruction_handler + db 'vstm.64',0xe0 + dw ARM_instruction_vstm.64-instruction_handler + db 'vstr.32',0xe0 + dw ARM_instruction_vstr.32-instruction_handler + db 'vstr.64',0xe0 + dw ARM_instruction_vstr.64-instruction_handler + db 'vsub.i8',0xe0 + dw ARM_instruction_vsub.i8-instruction_handler + db 'vtrn.16',0xe0 + dw ARM_instruction_vtrn.16-instruction_handler + db 'vtrn.32',0xe0 + dw ARM_instruction_vtrn.32-instruction_handler + db 'vtst.16',0xe0 + dw ARM_instruction_vtst.16-instruction_handler + db 'vtst.32',0xe0 + dw ARM_instruction_vtst.32-instruction_handler + db 'vuzp.16',0xe0 + dw ARM_instruction_vuzp.16-instruction_handler + db 'vuzp.32',0xe0 + dw ARM_instruction_vuzp.32-instruction_handler + db 'vzip.16',0xe0 + dw ARM_instruction_vzip.16-instruction_handler + db 'vzip.32',0xe0 + dw ARM_instruction_vzip.32-instruction_handler + db 'wabsb~~',0x00 + dw ARM_instruction_wabsb-instruction_handler + db 'wabsh~~',0x00 + dw ARM_instruction_wabsh-instruction_handler + db 'wabsw~~',0x00 + dw ARM_instruction_wabsw-instruction_handler + db 'waccb~~',0x00 + dw ARM_instruction_waccb-instruction_handler + db 'wacch~~',0x00 + dw ARM_instruction_wacch-instruction_handler + db 'waccw~~',0x00 + dw ARM_instruction_waccw-instruction_handler + db 'waddbss',0xe0 + dw ARM_instruction_waddbss-instruction_handler + db 'waddbus',0xe0 + dw ARM_instruction_waddbus-instruction_handler + db 'waddb~~',0x00 + dw ARM_instruction_waddb-instruction_handler + db 'waddhss',0xe0 + dw ARM_instruction_waddhss-instruction_handler + db 'waddhus',0xe0 + dw ARM_instruction_waddhus-instruction_handler + db 'waddh~~',0x00 + dw ARM_instruction_waddh-instruction_handler + db 'waddwss',0xe0 + dw ARM_instruction_waddwss-instruction_handler + db 'waddwus',0xe0 + dw ARM_instruction_waddwus-instruction_handler + db 'waddw~~',0x00 + dw ARM_instruction_waddw-instruction_handler + db 'waligni',0xe0 + dw ARM_instruction_waligni-instruction_handler + db 'wandn~~',0x00 + dw ARM_instruction_wandn-instruction_handler + db 'wavg2br',0xe0 + dw ARM_instruction_wavg2br-instruction_handler + db 'wavg2hr',0xe0 + dw ARM_instruction_wavg2hr-instruction_handler + db 'wavg4~~',0x00 + dw ARM_instruction_wavg4-instruction_handler + db 'wcmpeqb',0xe0 + dw ARM_instruction_wcmpeqb-instruction_handler + db 'wcmpeqh',0xe0 + dw ARM_instruction_wcmpeqh-instruction_handler + db 'wcmpeqw',0xe0 + dw ARM_instruction_wcmpeqw-instruction_handler + db 'wfe~~.n',0x04 + dw ARM_instruction_wfe-instruction_handler + db 'wfe~~.w',0x02 + dw ARM_instruction_wfe-instruction_handler + db 'wfi~~.n',0x04 + dw ARM_instruction_wfi-instruction_handler + db 'wfi~~.w',0x02 + dw ARM_instruction_wfi-instruction_handler + db 'wldrb~~',0x00 + dw ARM_instruction_wldrb-instruction_handler + db 'wldrd~~',0x00 + dw ARM_instruction_wldrd-instruction_handler + db 'wldrh~~',0x00 + dw ARM_instruction_wldrh-instruction_handler + db 'wldrw~~',0x00 + dw ARM_instruction_wldrw-instruction_handler + db 'wmacs~~',0x00 + dw ARM_instruction_wmacs-instruction_handler + db 'wmacu~~',0x00 + dw ARM_instruction_wmacu-instruction_handler + db 'wmaddsn',0xe0 + dw ARM_instruction_wmaddsn-instruction_handler + db 'wmaddsx',0xe0 + dw ARM_instruction_wmaddsx-instruction_handler + db 'wmaddun',0xe0 + dw ARM_instruction_wmaddun-instruction_handler + db 'wmaddux',0xe0 + dw ARM_instruction_wmaddux-instruction_handler + db 'wmiabbn',0xe0 + dw ARM_instruction_wmiabbn-instruction_handler + db 'wmiabtn',0xe0 + dw ARM_instruction_wmiabtn-instruction_handler + db 'wmiatbn',0xe0 + dw ARM_instruction_wmiatbn-instruction_handler + db 'wmiattn',0xe0 + dw ARM_instruction_wmiattn-instruction_handler + db 'wmiawbb',0xe0 + dw ARM_instruction_wmiawbb-instruction_handler + db 'wmiawbt',0xe0 + dw ARM_instruction_wmiawbt-instruction_handler + db 'wmiawtb',0xe0 + dw ARM_instruction_wmiawtb-instruction_handler + db 'wmiawtt',0xe0 + dw ARM_instruction_wmiawtt-instruction_handler + db 'wmulsmr',0xe0 + dw ARM_instruction_wmulsmr-instruction_handler + db 'wmulumr',0xe0 + dw ARM_instruction_wmulumr-instruction_handler + db 'wmulwsm',0xe0 + dw ARM_instruction_wmulwsm-instruction_handler + db 'wmulwum',0xe0 + dw ARM_instruction_wmulwum-instruction_handler + db 'wqmiabb',0xe0 + dw ARM_instruction_wqmiabb-instruction_handler + db 'wqmiabt',0xe0 + dw ARM_instruction_wqmiabt-instruction_handler + db 'wqmiatb',0xe0 + dw ARM_instruction_wqmiatb-instruction_handler + db 'wqmiatt',0xe0 + dw ARM_instruction_wqmiatt-instruction_handler + db 'wqmulmr',0xe0 + dw ARM_instruction_wqmulmr-instruction_handler + db 'wqmulwm',0xe0 + dw ARM_instruction_wqmulwm-instruction_handler + db 'wrord~~',0x00 + dw ARM_instruction_wrord-instruction_handler + db 'wrorh~~',0x00 + dw ARM_instruction_wrorh-instruction_handler + db 'wrorw~~',0x00 + dw ARM_instruction_wrorw-instruction_handler + db 'wsadb~~',0x00 + dw ARM_instruction_wsadb-instruction_handler + db 'wsadh~~',0x00 + dw ARM_instruction_wsadh-instruction_handler + db 'wslld~~',0x00 + dw ARM_instruction_wslld-instruction_handler + db 'wsllh~~',0x00 + dw ARM_instruction_wsllh-instruction_handler + db 'wsllw~~',0x00 + dw ARM_instruction_wsllw-instruction_handler + db 'wsrad~~',0x00 + dw ARM_instruction_wsrad-instruction_handler + db 'wsrah~~',0x00 + dw ARM_instruction_wsrah-instruction_handler + db 'wsraw~~',0x00 + dw ARM_instruction_wsraw-instruction_handler + db 'wsrld~~',0x00 + dw ARM_instruction_wsrld-instruction_handler + db 'wsrlh~~',0x00 + dw ARM_instruction_wsrlh-instruction_handler + db 'wsrlw~~',0x00 + dw ARM_instruction_wsrlw-instruction_handler + db 'wstrb~~',0x00 + dw ARM_instruction_wstrb-instruction_handler + db 'wstrd~~',0x00 + dw ARM_instruction_wstrd-instruction_handler + db 'wstrh~~',0x00 + dw ARM_instruction_wstrh-instruction_handler + db 'wstrw~~',0x00 + dw ARM_instruction_wstrw-instruction_handler + db 'wsubbss',0xe0 + dw ARM_instruction_wsubbss-instruction_handler + db 'wsubbus',0xe0 + dw ARM_instruction_wsubbus-instruction_handler + db 'wsubb~~',0x00 + dw ARM_instruction_wsubb-instruction_handler + db 'wsubhss',0xe0 + dw ARM_instruction_wsubhss-instruction_handler + db 'wsubhus',0xe0 + dw ARM_instruction_wsubhus-instruction_handler + db 'wsubh~~',0x00 + dw ARM_instruction_wsubh-instruction_handler + db 'wsubwss',0xe0 + dw ARM_instruction_wsubwss-instruction_handler + db 'wsubwus',0xe0 + dw ARM_instruction_wsubwus-instruction_handler + db 'wsubw~~',0x00 + dw ARM_instruction_wsubw-instruction_handler + db 'wzero~~',0x00 + dw ARM_instruction_wzero-instruction_handler + db 'yield.n',0xe4 + dw ARM_instruction_yield-instruction_handler + db 'yield.w',0xe2 + dw ARM_instruction_yield-instruction_handler + db 'yield~~',0x00 + dw ARM_instruction_yield-instruction_handler + db 0 +instructions_8: + db 'adcs~~.n',0x05 + dw ARM_instruction_adc-instruction_handler + db 'adcs~~.w',0x03 + dw ARM_instruction_adc-instruction_handler + db 'adc~~s.n',0x05 + dw ARM_instruction_adc-instruction_handler + db 'adc~~s.w',0x03 + dw ARM_instruction_adc-instruction_handler + db 'adds~~.n',0x05 + dw ARM_instruction_add-instruction_handler + db 'adds~~.w',0x03 + dw ARM_instruction_add-instruction_handler + db 'add~~s.n',0x05 + dw ARM_instruction_add-instruction_handler + db 'add~~s.w',0x03 + dw ARM_instruction_add-instruction_handler + db 'aesimc.8',0xf0 + dw ARM_instruction_aesimc.8-instruction_handler + db 'ands~~.n',0x05 + dw ARM_instruction_and-instruction_handler + db 'ands~~.w',0x03 + dw ARM_instruction_and-instruction_handler + db 'and~~s.n',0x05 + dw ARM_instruction_and-instruction_handler + db 'and~~s.w',0x03 + dw ARM_instruction_and-instruction_handler + db 'asrs~~.n',0x05 + dw ARM_instruction_asr-instruction_handler + db 'asrs~~.w',0x03 + dw ARM_instruction_asr-instruction_handler + db 'asr~~s.n',0x05 + dw ARM_instruction_asr-instruction_handler + db 'asr~~s.w',0x03 + dw ARM_instruction_asr-instruction_handler + db 'bics~~.n',0x05 + dw ARM_instruction_bic-instruction_handler + db 'bics~~.w',0x03 + dw ARM_instruction_bic-instruction_handler + db 'bic~~s.n',0x05 + dw ARM_instruction_bic-instruction_handler + db 'bic~~s.w',0x03 + dw ARM_instruction_bic-instruction_handler + db 'cfabsd~~',0x00 + dw ARM_instruction_cfabsd-instruction_handler + db 'cfabss~~',0x00 + dw ARM_instruction_cfabss-instruction_handler + db 'cfaddd~~',0x00 + dw ARM_instruction_cfaddd-instruction_handler + db 'cfadds~~',0x00 + dw ARM_instruction_cfadds-instruction_handler + db 'cfcmpd~~',0x00 + dw ARM_instruction_cfcmpd-instruction_handler + db 'cfcmps~~',0x00 + dw ARM_instruction_cfcmps-instruction_handler + db 'cfcpyd~~',0x00 + dw ARM_instruction_cfcpyd-instruction_handler + db 'cfcpys~~',0x00 + dw ARM_instruction_cfcpys-instruction_handler + db 'cfcvt32d',0xe0 + dw ARM_instruction_cfcvt32d-instruction_handler + db 'cfcvt32s',0xe0 + dw ARM_instruction_cfcvt32s-instruction_handler + db 'cfcvt64d',0xe0 + dw ARM_instruction_cfcvt64d-instruction_handler + db 'cfcvt64s',0xe0 + dw ARM_instruction_cfcvt64s-instruction_handler + db 'cfcvtd32',0xe0 + dw ARM_instruction_cfcvtd32-instruction_handler + db 'cfcvts32',0xe0 + dw ARM_instruction_cfcvts32-instruction_handler + db 'cfldrd~~',0x00 + dw ARM_instruction_cfldrd-instruction_handler + db 'cfldrs~~',0x00 + dw ARM_instruction_cfldrs-instruction_handler + db 'cfmadd32',0xe0 + dw ARM_instruction_cfmadd32-instruction_handler + db 'cfmsub32',0xe0 + dw ARM_instruction_cfmsub32-instruction_handler + db 'cfmuld~~',0x00 + dw ARM_instruction_cfmuld-instruction_handler + db 'cfmuls~~',0x00 + dw ARM_instruction_cfmuls-instruction_handler + db 'cfmv32ah',0xe0 + dw ARM_instruction_cfmv32ah-instruction_handler + db 'cfmv32al',0xe0 + dw ARM_instruction_cfmv32al-instruction_handler + db 'cfmv32am',0xe0 + dw ARM_instruction_cfmv32am-instruction_handler + db 'cfmv32sc',0xe0 + dw ARM_instruction_cfmv32sc-instruction_handler + db 'cfmv64hr',0xe0 + dw ARM_instruction_cfmv64hr-instruction_handler + db 'cfmv64lr',0xe0 + dw ARM_instruction_cfmv64lr-instruction_handler + db 'cfmvah32',0xe0 + dw ARM_instruction_cfmvah32-instruction_handler + db 'cfmval32',0xe0 + dw ARM_instruction_cfmval32-instruction_handler + db 'cfmvam32',0xe0 + dw ARM_instruction_cfmvam32-instruction_handler + db 'cfmvr64h',0xe0 + dw ARM_instruction_cfmvr64h-instruction_handler + db 'cfmvr64l',0xe0 + dw ARM_instruction_cfmvr64l-instruction_handler + db 'cfmvrs~~',0x00 + dw ARM_instruction_cfmvrs-instruction_handler + db 'cfmvsc32',0xe0 + dw ARM_instruction_cfmvsc32-instruction_handler + db 'cfmvsr~~',0x00 + dw ARM_instruction_cfmvsr-instruction_handler + db 'cfnegd~~',0x00 + dw ARM_instruction_cfnegd-instruction_handler + db 'cfnegs~~',0x00 + dw ARM_instruction_cfnegs-instruction_handler + db 'cfrshl32',0xe0 + dw ARM_instruction_cfrshl32-instruction_handler + db 'cfrshl64',0xe0 + dw ARM_instruction_cfrshl64-instruction_handler + db 'cfsh32~~',0x00 + dw ARM_instruction_cfsh32-instruction_handler + db 'cfsh64~~',0x00 + dw ARM_instruction_cfsh64-instruction_handler + db 'cfstrd~~',0x00 + dw ARM_instruction_cfstrd-instruction_handler + db 'cfstrs~~',0x00 + dw ARM_instruction_cfstrs-instruction_handler + db 'cfsubd~~',0x00 + dw ARM_instruction_cfsubd-instruction_handler + db 'cfsubs~~',0x00 + dw ARM_instruction_cfsubs-instruction_handler + db 'eors~~.n',0x05 + dw ARM_instruction_eor-instruction_handler + db 'eors~~.w',0x03 + dw ARM_instruction_eor-instruction_handler + db 'eor~~s.n',0x05 + dw ARM_instruction_eor-instruction_handler + db 'eor~~s.w',0x03 + dw ARM_instruction_eor-instruction_handler + db 'fcmped~~',0x00 + dw ARM_instruction_fcmped-instruction_handler + db 'fcmpes~~',0x00 + dw ARM_instruction_fcmpes-instruction_handler + db 'fcmpzd~~',0x00 + dw ARM_instruction_fcmpzd-instruction_handler + db 'fcmpzs~~',0x00 + dw ARM_instruction_fcmpzs-instruction_handler + db 'fcvtds~~',0x00 + dw ARM_instruction_fcvtds-instruction_handler + db 'fcvtsd~~',0x00 + dw ARM_instruction_fcvtsd-instruction_handler + db 'fmstat~~',0x00 + dw ARM_instruction_fmstat-instruction_handler + db 'fnmacd~~',0x00 + dw ARM_instruction_fnmacd-instruction_handler + db 'fnmacs~~',0x00 + dw ARM_instruction_fnmacs-instruction_handler + db 'fnmscd~~',0x00 + dw ARM_instruction_fnmscd-instruction_handler + db 'fnmscs~~',0x00 + dw ARM_instruction_fnmscs-instruction_handler + db 'fnmuld~~',0x00 + dw ARM_instruction_fnmuld-instruction_handler + db 'fnmuls~~',0x00 + dw ARM_instruction_fnmuls-instruction_handler + db 'fshtod~~',0x00 + dw ARM_instruction_fshtod-instruction_handler + db 'fshtos~~',0x00 + dw ARM_instruction_fshtos-instruction_handler + db 'fsitod~~',0x00 + dw ARM_instruction_fsitod-instruction_handler + db 'fsitos~~',0x00 + dw ARM_instruction_fsitos-instruction_handler + db 'fsltod~~',0x00 + dw ARM_instruction_fsltod-instruction_handler + db 'fsltos~~',0x00 + dw ARM_instruction_fsltos-instruction_handler + db 'fsqrtd~~',0x00 + dw ARM_instruction_fsqrtd-instruction_handler + db 'fsqrts~~',0x00 + dw ARM_instruction_fsqrts-instruction_handler + db 'ftoshd~~',0x00 + dw ARM_instruction_ftoshd-instruction_handler + db 'ftoshs~~',0x00 + dw ARM_instruction_ftoshs-instruction_handler + db 'ftosid~~',0x00 + dw ARM_instruction_ftosid-instruction_handler + db 'ftosis~~',0x00 + dw ARM_instruction_ftosis-instruction_handler + db 'ftosld~~',0x00 + dw ARM_instruction_ftosld-instruction_handler + db 'ftosls~~',0x00 + dw ARM_instruction_ftosls-instruction_handler + db 'ftouhd~~',0x00 + dw ARM_instruction_ftouhd-instruction_handler + db 'ftouhs~~',0x00 + dw ARM_instruction_ftouhs-instruction_handler + db 'ftouid~~',0x00 + dw ARM_instruction_ftouid-instruction_handler + db 'ftouis~~',0x00 + dw ARM_instruction_ftouis-instruction_handler + db 'ftould~~',0x00 + dw ARM_instruction_ftould-instruction_handler + db 'ftouls~~',0x00 + dw ARM_instruction_ftouls-instruction_handler + db 'fuhtod~~',0x00 + dw ARM_instruction_fuhtod-instruction_handler + db 'fuhtos~~',0x00 + dw ARM_instruction_fuhtos-instruction_handler + db 'fuitod~~',0x00 + dw ARM_instruction_fuitod-instruction_handler + db 'fuitos~~',0x00 + dw ARM_instruction_fuitos-instruction_handler + db 'fultod~~',0x00 + dw ARM_instruction_fultod-instruction_handler + db 'fultos~~',0x00 + dw ARM_instruction_fultos-instruction_handler + db 'itnoauto',0x00 + dw ARM_itnoauto_directive-instruction_handler + db 'ldaexb~~',0x00 + dw ARM_instruction_ldaexb-instruction_handler + db 'ldaexd~~',0x00 + dw ARM_instruction_ldaexd-instruction_handler + db 'ldaexh~~',0x00 + dw ARM_instruction_ldaexh-instruction_handler + db 'ldaex~~b',0x00 + dw ARM_instruction_ldaexb-instruction_handler + db 'ldaex~~d',0x00 + dw ARM_instruction_ldaexd-instruction_handler + db 'ldaex~~h',0x00 + dw ARM_instruction_ldaexh-instruction_handler + db 'ldrb~~.n',0x04 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrb~~.w',0x02 + dw ARM_instruction_ldrb-instruction_handler + db 'ldrexb~~',0x00 + dw ARM_instruction_ldrexb-instruction_handler + db 'ldrexd~~',0x00 + dw ARM_instruction_ldrexd-instruction_handler + db 'ldrexh~~',0x00 + dw ARM_instruction_ldrexh-instruction_handler + db 'ldrh~~.n',0x04 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrh~~.w',0x02 + dw ARM_instruction_ldrh-instruction_handler + db 'ldrsbt~~',0x00 + dw ARM_instruction_ldrsbt-instruction_handler + db 'ldrsht~~',0x00 + dw ARM_instruction_ldrsht-instruction_handler + db 'ldr~~b.n',0x04 + dw ARM_instruction_ldrb-instruction_handler + db 'ldr~~b.w',0x02 + dw ARM_instruction_ldrb-instruction_handler + db 'ldr~~h.n',0x04 + dw ARM_instruction_ldrh-instruction_handler + db 'ldr~~h.w',0x02 + dw ARM_instruction_ldrh-instruction_handler + db 'ldr~~sbt',0x00 + dw ARM_instruction_ldrsbt-instruction_handler + db 'ldr~~sht',0x00 + dw ARM_instruction_ldrsht-instruction_handler + db 'lsls~~.n',0x05 + dw ARM_instruction_lsl-instruction_handler + db 'lsls~~.w',0x03 + dw ARM_instruction_lsl-instruction_handler + db 'lsl~~s.n',0x05 + dw ARM_instruction_lsl-instruction_handler + db 'lsl~~s.w',0x03 + dw ARM_instruction_lsl-instruction_handler + db 'lsrs~~.n',0x05 + dw ARM_instruction_lsr-instruction_handler + db 'lsrs~~.w',0x03 + dw ARM_instruction_lsr-instruction_handler + db 'lsr~~s.n',0x05 + dw ARM_instruction_lsr-instruction_handler + db 'lsr~~s.w',0x03 + dw ARM_instruction_lsr-instruction_handler + db 'movs~~.n',0x05 + dw ARM_instruction_mov-instruction_handler + db 'movs~~.w',0x03 + dw ARM_instruction_mov-instruction_handler + db 'mov~~s.n',0x05 + dw ARM_instruction_mov-instruction_handler + db 'mov~~s.w',0x03 + dw ARM_instruction_mov-instruction_handler + db 'muls~~.n',0x05 + dw ARM_instruction_mul-instruction_handler + db 'muls~~.w',0x03 + dw ARM_instruction_mul-instruction_handler + db 'mul~~s.n',0x05 + dw ARM_instruction_mul-instruction_handler + db 'mul~~s.w',0x03 + dw ARM_instruction_mul-instruction_handler + db 'mvns~~.n',0x05 + dw ARM_instruction_mvn-instruction_handler + db 'mvns~~.w',0x03 + dw ARM_instruction_mvn-instruction_handler + db 'mvn~~s.n',0x05 + dw ARM_instruction_mvn-instruction_handler + db 'mvn~~s.w',0x03 + dw ARM_instruction_mvn-instruction_handler + db 'negs~~.n',0x05 + dw ARM_instruction_neg-instruction_handler + db 'negs~~.w',0x03 + dw ARM_instruction_neg-instruction_handler + db 'neg~~s.n',0x05 + dw ARM_instruction_neg-instruction_handler + db 'neg~~s.w',0x03 + dw ARM_instruction_neg-instruction_handler + db 'orrs~~.n',0x05 + dw ARM_instruction_orr-instruction_handler + db 'orrs~~.w',0x03 + dw ARM_instruction_orr-instruction_handler + db 'orr~~s.n',0x05 + dw ARM_instruction_orr-instruction_handler + db 'orr~~s.w',0x03 + dw ARM_instruction_orr-instruction_handler + db 'push~~.n',0x04 + dw ARM_instruction_push-instruction_handler + db 'push~~.w',0x02 + dw ARM_instruction_push-instruction_handler + db 'qadd16~~',0x00 + dw ARM_instruction_qadd16-instruction_handler + db 'qaddsubx',0xe0 + dw ARM_instruction_qaddsubx-instruction_handler + db 'qsub16~~',0x00 + dw ARM_instruction_qsub16-instruction_handler + db 'qsubaddx',0xe0 + dw ARM_instruction_qsubaddx-instruction_handler + db 'rors~~.n',0x05 + dw ARM_instruction_ror-instruction_handler + db 'rors~~.w',0x03 + dw ARM_instruction_ror-instruction_handler + db 'ror~~s.n',0x05 + dw ARM_instruction_ror-instruction_handler + db 'ror~~s.w',0x03 + dw ARM_instruction_ror-instruction_handler + db 'rsbs~~.n',0x05 + dw ARM_instruction_rsb-instruction_handler + db 'rsbs~~.w',0x03 + dw ARM_instruction_rsb-instruction_handler + db 'rsb~~s.n',0x05 + dw ARM_instruction_rsb-instruction_handler + db 'rsb~~s.w',0x03 + dw ARM_instruction_rsb-instruction_handler + db 'sadd16~~',0x00 + dw ARM_instruction_sadd16-instruction_handler + db 'saddsubx',0xe0 + dw ARM_instruction_saddsubx-instruction_handler + db 'sbcs~~.n',0x05 + dw ARM_instruction_sbc-instruction_handler + db 'sbcs~~.w',0x03 + dw ARM_instruction_sbc-instruction_handler + db 'sbc~~s.n',0x05 + dw ARM_instruction_sbc-instruction_handler + db 'sbc~~s.w',0x03 + dw ARM_instruction_sbc-instruction_handler + db 'sevl~~.n',0x04 + dw ARM_instruction_sevl-instruction_handler + db 'sevl~~.w',0x02 + dw ARM_instruction_sevl-instruction_handler + db 'sha1c.32',0xf0 + dw ARM_instruction_sha1c.32-instruction_handler + db 'sha1h.32',0xf0 + dw ARM_instruction_sha1h.32-instruction_handler + db 'sha1m.32',0xf0 + dw ARM_instruction_sha1m.32-instruction_handler + db 'sha1p.32',0xf0 + dw ARM_instruction_sha1p.32-instruction_handler + db 'sha256h2',0xf0 + dw ARM_instruction_sha256h2-instruction_handler + db 'shadd8~~',0x00 + dw ARM_instruction_shadd8-instruction_handler + db 'shsub8~~',0x00 + dw ARM_instruction_shsub8-instruction_handler + db 'smlabb~~',0x00 + dw ARM_instruction_smlabb-instruction_handler + db 'smlabt~~',0x00 + dw ARM_instruction_smlabt-instruction_handler + db 'smladx~~',0x00 + dw ARM_instruction_smladx-instruction_handler + db 'smlald~~',0x00 + dw ARM_instruction_smlald-instruction_handler + db 'smlals~~',0x01 + dw ARM_instruction_smlal-instruction_handler + db 'smlal~~s',0x01 + dw ARM_instruction_smlal-instruction_handler + db 'smlatb~~',0x00 + dw ARM_instruction_smlatb-instruction_handler + db 'smlatt~~',0x00 + dw ARM_instruction_smlatt-instruction_handler + db 'smlawb~~',0x00 + dw ARM_instruction_smlawb-instruction_handler + db 'smlawt~~',0x00 + dw ARM_instruction_smlawt-instruction_handler + db 'smlsdx~~',0x00 + dw ARM_instruction_smlsdx-instruction_handler + db 'smlsld~~',0x00 + dw ARM_instruction_smlsld-instruction_handler + db 'smmlar~~',0x00 + dw ARM_instruction_smmlar-instruction_handler + db 'smmlsr~~',0x00 + dw ARM_instruction_smmlsr-instruction_handler + db 'smmulr~~',0x00 + dw ARM_instruction_smmulr-instruction_handler + db 'smuadx~~',0x00 + dw ARM_instruction_smuadx-instruction_handler + db 'smulbb~~',0x00 + dw ARM_instruction_smulbb-instruction_handler + db 'smulbt~~',0x00 + dw ARM_instruction_smulbt-instruction_handler + db 'smulls~~',0x01 + dw ARM_instruction_smull-instruction_handler + db 'smull~~s',0x01 + dw ARM_instruction_smull-instruction_handler + db 'smultb~~',0x00 + dw ARM_instruction_smultb-instruction_handler + db 'smultt~~',0x00 + dw ARM_instruction_smultt-instruction_handler + db 'smulwb~~',0x00 + dw ARM_instruction_smulwb-instruction_handler + db 'smulwt~~',0x00 + dw ARM_instruction_smulwt-instruction_handler + db 'smusdx~~',0x00 + dw ARM_instruction_smusdx-instruction_handler + db 'sqdmlal2',0xf0 + dw ARM_instruction_sqdmlal2-instruction_handler + db 'sqdmlsl2',0xf0 + dw ARM_instruction_sqdmlsl2-instruction_handler + db 'sqdmull2',0xf0 + dw ARM_instruction_sqdmull2-instruction_handler + db 'sqrdmulh',0xf0 + dw ARM_instruction_sqrdmulh-instruction_handler + db 'sqrshrn2',0xf0 + dw ARM_instruction_sqrshrn2-instruction_handler + db 'sqrshrun',0xf0 + dw ARM_instruction_sqrshrun-instruction_handler + db 'sqshrun2',0xf0 + dw ARM_instruction_sqshrun2-instruction_handler + db 'ssat16~~',0x00 + dw ARM_instruction_ssat16-instruction_handler + db 'ssub16~~',0x00 + dw ARM_instruction_ssub16-instruction_handler + db 'ssubaddx',0xe0 + dw ARM_instruction_ssubaddx-instruction_handler + db 'stlexb~~',0x00 + dw ARM_instruction_stlexb-instruction_handler + db 'stlexd~~',0x00 + dw ARM_instruction_stlexd-instruction_handler + db 'stlexh~~',0x00 + dw ARM_instruction_stlexh-instruction_handler + db 'stlex~~b',0x00 + dw ARM_instruction_stlexb-instruction_handler + db 'stlex~~d',0x00 + dw ARM_instruction_stlexd-instruction_handler + db 'stlex~~h',0x00 + dw ARM_instruction_stlexh-instruction_handler + db 'strb~~.n',0x04 + dw ARM_instruction_strb-instruction_handler + db 'strb~~.w',0x02 + dw ARM_instruction_strb-instruction_handler + db 'strexb~~',0x00 + dw ARM_instruction_strexb-instruction_handler + db 'strexd~~',0x00 + dw ARM_instruction_strexd-instruction_handler + db 'strexh~~',0x00 + dw ARM_instruction_strexh-instruction_handler + db 'strh~~.n',0x04 + dw ARM_instruction_strh-instruction_handler + db 'strh~~.w',0x02 + dw ARM_instruction_strh-instruction_handler + db 'str~~b.n',0x04 + dw ARM_instruction_strb-instruction_handler + db 'str~~b.w',0x02 + dw ARM_instruction_strb-instruction_handler + db 'str~~h.n',0x04 + dw ARM_instruction_strh-instruction_handler + db 'str~~h.w',0x02 + dw ARM_instruction_strh-instruction_handler + db 'subs~~.n',0x05 + dw ARM_instruction_sub-instruction_handler + db 'subs~~.w',0x03 + dw ARM_instruction_sub-instruction_handler + db 'sub~~s.n',0x05 + dw ARM_instruction_sub-instruction_handler + db 'sub~~s.w',0x03 + dw ARM_instruction_sub-instruction_handler + db 'sxtb16~~',0x00 + dw ARM_instruction_sxtb16-instruction_handler + db 'sxtb~~.n',0x04 + dw ARM_instruction_sxtb-instruction_handler + db 'sxtb~~.w',0x02 + dw ARM_instruction_sxtb-instruction_handler + db 'sxth~~.n',0x04 + dw ARM_instruction_sxth-instruction_handler + db 'sxth~~.w',0x02 + dw ARM_instruction_sxth-instruction_handler + db 'tandcb~~',0x00 + dw ARM_instruction_tandcb-instruction_handler + db 'tandch~~',0x00 + dw ARM_instruction_tandch-instruction_handler + db 'tandcw~~',0x00 + dw ARM_instruction_tandcw-instruction_handler + db 'tbcstb~~',0x00 + dw ARM_instruction_tbcstb-instruction_handler + db 'tbcsth~~',0x00 + dw ARM_instruction_tbcsth-instruction_handler + db 'tbcstw~~',0x00 + dw ARM_instruction_tbcstw-instruction_handler + db 'textrmsb',0xe0 + dw ARM_instruction_textrmsb-instruction_handler + db 'textrmsh',0xe0 + dw ARM_instruction_textrmsh-instruction_handler + db 'textrmsw',0xe0 + dw ARM_instruction_textrmsw-instruction_handler + db 'textrmub',0xe0 + dw ARM_instruction_textrmub-instruction_handler + db 'textrmuh',0xe0 + dw ARM_instruction_textrmuh-instruction_handler + db 'textrmuw',0xe0 + dw ARM_instruction_textrmuw-instruction_handler + db 'tinsrb~~',0x00 + dw ARM_instruction_tinsrb-instruction_handler + db 'tinsrh~~',0x00 + dw ARM_instruction_tinsrh-instruction_handler + db 'tinsrw~~',0x00 + dw ARM_instruction_tinsrw-instruction_handler + db 'tmiabb~~',0x00 + dw ARM_instruction_tmiabb-instruction_handler + db 'tmiabt~~',0x00 + dw ARM_instruction_tmiabt-instruction_handler + db 'tmiaph~~',0x00 + dw ARM_instruction_tmiaph-instruction_handler + db 'tmiatb~~',0x00 + dw ARM_instruction_tmiatb-instruction_handler + db 'tmiatt~~',0x00 + dw ARM_instruction_tmiatt-instruction_handler + db 'tmovmskb',0xe0 + dw ARM_instruction_tmovmskb-instruction_handler + db 'tmovmskh',0xe0 + dw ARM_instruction_tmovmskh-instruction_handler + db 'tmovmskw',0xe0 + dw ARM_instruction_tmovmskw-instruction_handler + db 'uadd16~~',0x00 + dw ARM_instruction_uadd16-instruction_handler + db 'uaddsubx',0xe0 + dw ARM_instruction_uaddsubx-instruction_handler + db 'uhadd8~~',0x00 + dw ARM_instruction_uhadd8-instruction_handler + db 'uhsub8~~',0x00 + dw ARM_instruction_uhsub8-instruction_handler + db 'umlals~~',0x01 + dw ARM_instruction_umlal-instruction_handler + db 'umlal~~s',0x01 + dw ARM_instruction_umlal-instruction_handler + db 'umulls~~',0x01 + dw ARM_instruction_umull-instruction_handler + db 'umull~~s',0x01 + dw ARM_instruction_umull-instruction_handler + db 'uqadd8~~',0x00 + dw ARM_instruction_uqadd8-instruction_handler + db 'uqrshrn2',0xf0 + dw ARM_instruction_uqrshrn2-instruction_handler + db 'uqsub8~~',0x00 + dw ARM_instruction_uqsub8-instruction_handler + db 'usada8~~',0x00 + dw ARM_instruction_usada8-instruction_handler + db 'usat16~~',0x00 + dw ARM_instruction_usat16-instruction_handler + db 'usub16~~',0x00 + dw ARM_instruction_usub16-instruction_handler + db 'usubaddx',0xe0 + dw ARM_instruction_usubaddx-instruction_handler + db 'uxtb16~~',0x00 + dw ARM_instruction_uxtb16-instruction_handler + db 'uxtb~~.n',0x04 + dw ARM_instruction_uxtb-instruction_handler + db 'uxtb~~.w',0x02 + dw ARM_instruction_uxtb-instruction_handler + db 'uxth~~.n',0x04 + dw ARM_instruction_uxth-instruction_handler + db 'uxth~~.w',0x02 + dw ARM_instruction_uxth-instruction_handler + db 'vaba.s16',0xe0 + dw ARM_instruction_vaba.s16-instruction_handler + db 'vaba.s32',0xe0 + dw ARM_instruction_vaba.s32-instruction_handler + db 'vaba.u16',0xe0 + dw ARM_instruction_vaba.u16-instruction_handler + db 'vaba.u32',0xe0 + dw ARM_instruction_vaba.u32-instruction_handler + db 'vabal.s8',0xe0 + dw ARM_instruction_vabal.s8-instruction_handler + db 'vabal.u8',0xe0 + dw ARM_instruction_vabal.u8-instruction_handler + db 'vabd.f32',0xe0 + dw ARM_instruction_vabd.f32-instruction_handler + db 'vabd.s16',0xe0 + dw ARM_instruction_vabd.s16-instruction_handler + db 'vabd.s32',0xe0 + dw ARM_instruction_vabd.s32-instruction_handler + db 'vabd.u16',0xe0 + dw ARM_instruction_vabd.u16-instruction_handler + db 'vabd.u32',0xe0 + dw ARM_instruction_vabd.u32-instruction_handler + db 'vabdl.s8',0xe0 + dw ARM_instruction_vabdl.s8-instruction_handler + db 'vabdl.u8',0xe0 + dw ARM_instruction_vabdl.u8-instruction_handler + db 'vabs.f32',0xe0 + dw ARM_instruction_vabs.f32-instruction_handler + db 'vabs.f64',0xe0 + dw ARM_instruction_vabs.f64-instruction_handler + db 'vabs.s16',0xe0 + dw ARM_instruction_vabs.s16-instruction_handler + db 'vabs.s32',0xe0 + dw ARM_instruction_vabs.s32-instruction_handler + db 'vadd.f32',0xe0 + dw ARM_instruction_vadd.f32-instruction_handler + db 'vadd.f64',0xe0 + dw ARM_instruction_vadd.f64-instruction_handler + db 'vadd.i16',0xe0 + dw ARM_instruction_vadd.i16-instruction_handler + db 'vadd.i32',0xe0 + dw ARM_instruction_vadd.i32-instruction_handler + db 'vadd.i64',0xe0 + dw ARM_instruction_vadd.i64-instruction_handler + db 'vaddl.s8',0xe0 + dw ARM_instruction_vaddl.s8-instruction_handler + db 'vaddl.u8',0xe0 + dw ARM_instruction_vaddl.u8-instruction_handler + db 'vaddw.s8',0xe0 + dw ARM_instruction_vaddw.s8-instruction_handler + db 'vaddw.u8',0xe0 + dw ARM_instruction_vaddw.u8-instruction_handler + db 'vand.i16',0xe0 + dw ARM_instruction_vand.i16-instruction_handler + db 'vand.i32',0xe0 + dw ARM_instruction_vand.i32-instruction_handler + db 'vbic.i16',0xe0 + dw ARM_instruction_vbic.i16-instruction_handler + db 'vbic.i32',0xe0 + dw ARM_instruction_vbic.i32-instruction_handler + db 'vceq.f32',0xe0 + dw ARM_instruction_vceq.f32-instruction_handler + db 'vceq.i16',0xe0 + dw ARM_instruction_vceq.i16-instruction_handler + db 'vceq.i32',0xe0 + dw ARM_instruction_vceq.i32-instruction_handler + db 'vcge.f32',0xe0 + dw ARM_instruction_vcge.f32-instruction_handler + db 'vcge.s16',0xe0 + dw ARM_instruction_vcge.s16-instruction_handler + db 'vcge.s32',0xe0 + dw ARM_instruction_vcge.s32-instruction_handler + db 'vcge.u16',0xe0 + dw ARM_instruction_vcge.u16-instruction_handler + db 'vcge.u32',0xe0 + dw ARM_instruction_vcge.u32-instruction_handler + db 'vcgt.f32',0xe0 + dw ARM_instruction_vcgt.f32-instruction_handler + db 'vcgt.s16',0xe0 + dw ARM_instruction_vcgt.s16-instruction_handler + db 'vcgt.s32',0xe0 + dw ARM_instruction_vcgt.s32-instruction_handler + db 'vcgt.u16',0xe0 + dw ARM_instruction_vcgt.u16-instruction_handler + db 'vcgt.u32',0xe0 + dw ARM_instruction_vcgt.u32-instruction_handler + db 'vcle.f32',0xe0 + dw ARM_instruction_vcle.f32-instruction_handler + db 'vcle.s16',0xe0 + dw ARM_instruction_vcle.s16-instruction_handler + db 'vcle.s32',0xe0 + dw ARM_instruction_vcle.s32-instruction_handler + db 'vcle.u16',0xe0 + dw ARM_instruction_vcle.u16-instruction_handler + db 'vcle.u32',0xe0 + dw ARM_instruction_vcle.u32-instruction_handler + db 'vcls.s16',0xe0 + dw ARM_instruction_vcls.s16-instruction_handler + db 'vcls.s32',0xe0 + dw ARM_instruction_vcls.s32-instruction_handler + db 'vclt.f32',0xe0 + dw ARM_instruction_vclt.f32-instruction_handler + db 'vclt.s16',0xe0 + dw ARM_instruction_vclt.s16-instruction_handler + db 'vclt.s32',0xe0 + dw ARM_instruction_vclt.s32-instruction_handler + db 'vclt.u16',0xe0 + dw ARM_instruction_vclt.u16-instruction_handler + db 'vclt.u32',0xe0 + dw ARM_instruction_vclt.u32-instruction_handler + db 'vclz.i16',0xe0 + dw ARM_instruction_vclz.i16-instruction_handler + db 'vclz.i32',0xe0 + dw ARM_instruction_vclz.i32-instruction_handler + db 'vcmp.f32',0xe0 + dw ARM_instruction_vcmp.f32-instruction_handler + db 'vcmp.f64',0xe0 + dw ARM_instruction_vcmp.f64-instruction_handler + db 'vcnt~~.8',0x00 + dw ARM_instruction_vcnt.8-instruction_handler + db 'vdiv.f32',0xe0 + dw ARM_instruction_vdiv.f32-instruction_handler + db 'vdiv.f64',0xe0 + dw ARM_instruction_vdiv.f64-instruction_handler + db 'vdup~~.8',0x00 + dw ARM_instruction_vdup.8-instruction_handler + db 'vext~~.8',0x00 + dw ARM_instruction_vext.8-instruction_handler + db 'vfma.f32',0xe0 + dw ARM_instruction_vfma.f32-instruction_handler + db 'vfma.f64',0xe0 + dw ARM_instruction_vfma.f64-instruction_handler + db 'vfms.f32',0xe0 + dw ARM_instruction_vfms.f32-instruction_handler + db 'vfms.f64',0xe0 + dw ARM_instruction_vfms.f64-instruction_handler + db 'vhadd.s8',0xe0 + dw ARM_instruction_vhadd.s8-instruction_handler + db 'vhadd.u8',0xe0 + dw ARM_instruction_vhadd.u8-instruction_handler + db 'vhsub.s8',0xe0 + dw ARM_instruction_vhsub.s8-instruction_handler + db 'vhsub.u8',0xe0 + dw ARM_instruction_vhsub.u8-instruction_handler + db 'vld1~~.8',0x00 + dw ARM_instruction_vld1.8-instruction_handler + db 'vld2~~.8',0x00 + dw ARM_instruction_vld2.8-instruction_handler + db 'vld3~~.8',0x00 + dw ARM_instruction_vld3.8-instruction_handler + db 'vld4~~.8',0x00 + dw ARM_instruction_vld4.8-instruction_handler + db 'vldmdb~~',0x00 + dw ARM_instruction_vldmdb-instruction_handler + db 'vldmea~~',0x00 + dw ARM_instruction_vldmea-instruction_handler + db 'vldmfd~~',0x00 + dw ARM_instruction_vldmfd-instruction_handler + db 'vldmia~~',0x00 + dw ARM_instruction_vldmia-instruction_handler + db 'vmax.f32',0xe0 + dw ARM_instruction_vmax.f32-instruction_handler + db 'vmax.s16',0xe0 + dw ARM_instruction_vmax.s16-instruction_handler + db 'vmax.s32',0xe0 + dw ARM_instruction_vmax.s32-instruction_handler + db 'vmax.u16',0xe0 + dw ARM_instruction_vmax.u16-instruction_handler + db 'vmax.u32',0xe0 + dw ARM_instruction_vmax.u32-instruction_handler + db 'vmin.f32',0xe0 + dw ARM_instruction_vmin.f32-instruction_handler + db 'vmin.s16',0xe0 + dw ARM_instruction_vmin.s16-instruction_handler + db 'vmin.s32',0xe0 + dw ARM_instruction_vmin.s32-instruction_handler + db 'vmin.u16',0xe0 + dw ARM_instruction_vmin.u16-instruction_handler + db 'vmin.u32',0xe0 + dw ARM_instruction_vmin.u32-instruction_handler + db 'vmla.f32',0xe0 + dw ARM_instruction_vmla.f32-instruction_handler + db 'vmla.f64',0xe0 + dw ARM_instruction_vmla.f64-instruction_handler + db 'vmla.i16',0xe0 + dw ARM_instruction_vmla.i16-instruction_handler + db 'vmla.i32',0xe0 + dw ARM_instruction_vmla.i32-instruction_handler + db 'vmla.s16',0xe0 + dw ARM_instruction_vmla.s16-instruction_handler + db 'vmla.s32',0xe0 + dw ARM_instruction_vmla.s32-instruction_handler + db 'vmla.u16',0xe0 + dw ARM_instruction_vmla.u16-instruction_handler + db 'vmla.u32',0xe0 + dw ARM_instruction_vmla.u32-instruction_handler + db 'vmlal.s8',0xe0 + dw ARM_instruction_vmlal.s8-instruction_handler + db 'vmlal.u8',0xe0 + dw ARM_instruction_vmlal.u8-instruction_handler + db 'vmls.f32',0xe0 + dw ARM_instruction_vmls.f32-instruction_handler + db 'vmls.f64',0xe0 + dw ARM_instruction_vmls.f64-instruction_handler + db 'vmls.i16',0xe0 + dw ARM_instruction_vmls.i16-instruction_handler + db 'vmls.i32',0xe0 + dw ARM_instruction_vmls.i32-instruction_handler + db 'vmls.s16',0xe0 + dw ARM_instruction_vmls.s16-instruction_handler + db 'vmls.s32',0xe0 + dw ARM_instruction_vmls.s32-instruction_handler + db 'vmls.u16',0xe0 + dw ARM_instruction_vmls.u16-instruction_handler + db 'vmls.u32',0xe0 + dw ARM_instruction_vmls.u32-instruction_handler + db 'vmlsl.s8',0xe0 + dw ARM_instruction_vmlsl.s8-instruction_handler + db 'vmlsl.u8',0xe0 + dw ARM_instruction_vmlsl.u8-instruction_handler + db 'vmov.f32',0xe0 + dw ARM_instruction_vmov.f32-instruction_handler + db 'vmov.f64',0xe0 + dw ARM_instruction_vmov.f64-instruction_handler + db 'vmov.i16',0xe0 + dw ARM_instruction_vmov.i16-instruction_handler + db 'vmov.i32',0xe0 + dw ARM_instruction_vmov.i32-instruction_handler + db 'vmov.i64',0xe0 + dw ARM_instruction_vmov.i64-instruction_handler + db 'vmov.s16',0xe0 + dw ARM_instruction_vmov.s16-instruction_handler + db 'vmov.u16',0xe0 + dw ARM_instruction_vmov.u16-instruction_handler + db 'vmovl.s8',0xe0 + dw ARM_instruction_vmovl.s8-instruction_handler + db 'vmovl.u8',0xe0 + dw ARM_instruction_vmovl.u8-instruction_handler + db 'vmovn.i8',0xe0 + dw ARM_instruction_vmovn.i8-instruction_handler + db 'vmov~~.8',0x00 + dw ARM_instruction_vmov.8-instruction_handler + db 'vmul.f32',0xe0 + dw ARM_instruction_vmul.f32-instruction_handler + db 'vmul.f64',0xe0 + dw ARM_instruction_vmul.f64-instruction_handler + db 'vmul.i16',0xe0 + dw ARM_instruction_vmul.i16-instruction_handler + db 'vmul.i32',0xe0 + dw ARM_instruction_vmul.i32-instruction_handler + db 'vmul.s16',0xe0 + dw ARM_instruction_vmul.s16-instruction_handler + db 'vmul.s32',0xe0 + dw ARM_instruction_vmul.s32-instruction_handler + db 'vmul.u16',0xe0 + dw ARM_instruction_vmul.u16-instruction_handler + db 'vmul.u32',0xe0 + dw ARM_instruction_vmul.u32-instruction_handler + db 'vmull.p8',0xe0 + dw ARM_instruction_vmull.p8-instruction_handler + db 'vmull.s8',0xe0 + dw ARM_instruction_vmull.s8-instruction_handler + db 'vmull.u8',0xe0 + dw ARM_instruction_vmull.u8-instruction_handler + db 'vmvn.i16',0xe0 + dw ARM_instruction_vmvn.i16-instruction_handler + db 'vmvn.i32',0xe0 + dw ARM_instruction_vmvn.i32-instruction_handler + db 'vneg.f32',0xe0 + dw ARM_instruction_vneg.f32-instruction_handler + db 'vneg.f64',0xe0 + dw ARM_instruction_vneg.f64-instruction_handler + db 'vneg.s16',0xe0 + dw ARM_instruction_vneg.s16-instruction_handler + db 'vneg.s32',0xe0 + dw ARM_instruction_vneg.s32-instruction_handler + db 'vorn.i16',0xe0 + dw ARM_instruction_vorn.i16-instruction_handler + db 'vorn.i32',0xe0 + dw ARM_instruction_vorn.i32-instruction_handler + db 'vorr.i16',0xe0 + dw ARM_instruction_vorr.i16-instruction_handler + db 'vorr.i32',0xe0 + dw ARM_instruction_vorr.i32-instruction_handler + db 'vpadd.i8',0xe0 + dw ARM_instruction_vpadd.i8-instruction_handler + db 'vpmax.s8',0xe0 + dw ARM_instruction_vpmax.s8-instruction_handler + db 'vpmax.u8',0xe0 + dw ARM_instruction_vpmax.u8-instruction_handler + db 'vpmin.s8',0xe0 + dw ARM_instruction_vpmin.s8-instruction_handler + db 'vpmin.u8',0xe0 + dw ARM_instruction_vpmin.u8-instruction_handler + db 'vpush.32',0xe0 + dw ARM_instruction_vpush.32-instruction_handler + db 'vpush.64',0xe0 + dw ARM_instruction_vpush.64-instruction_handler + db 'vqabs.s8',0xe0 + dw ARM_instruction_vqabs.s8-instruction_handler + db 'vqadd.s8',0xe0 + dw ARM_instruction_vqadd.s8-instruction_handler + db 'vqadd.u8',0xe0 + dw ARM_instruction_vqadd.u8-instruction_handler + db 'vqneg.s8',0xe0 + dw ARM_instruction_vqneg.s8-instruction_handler + db 'vqshl.s8',0xe0 + dw ARM_instruction_vqshl.s8-instruction_handler + db 'vqshl.u8',0xe0 + dw ARM_instruction_vqshl.u8-instruction_handler + db 'vqsub.s8',0xe0 + dw ARM_instruction_vqsub.s8-instruction_handler + db 'vqsub.u8',0xe0 + dw ARM_instruction_vqsub.u8-instruction_handler + db 'vrev16.8',0xe0 + dw ARM_instruction_vrev16.8-instruction_handler + db 'vrev32.8',0xe0 + dw ARM_instruction_vrev32.8-instruction_handler + db 'vrev64.8',0xe0 + dw ARM_instruction_vrev64.8-instruction_handler + db 'vrshl.s8',0xe0 + dw ARM_instruction_vrshl.s8-instruction_handler + db 'vrshl.u8',0xe0 + dw ARM_instruction_vrshl.u8-instruction_handler + db 'vrshr.s8',0xe0 + dw ARM_instruction_vrshr.s8-instruction_handler + db 'vrshr.u8',0xe0 + dw ARM_instruction_vrshr.u8-instruction_handler + db 'vrsra.s8',0xe0 + dw ARM_instruction_vrsra.s8-instruction_handler + db 'vrsra.u8',0xe0 + dw ARM_instruction_vrsra.u8-instruction_handler + db 'vshl.i16',0xe0 + dw ARM_instruction_vshl.i16-instruction_handler + db 'vshl.i32',0xe0 + dw ARM_instruction_vshl.i32-instruction_handler + db 'vshl.i64',0xe0 + dw ARM_instruction_vshl.i64-instruction_handler + db 'vshl.s16',0xe0 + dw ARM_instruction_vshl.s16-instruction_handler + db 'vshl.s32',0xe0 + dw ARM_instruction_vshl.s32-instruction_handler + db 'vshl.s64',0xe0 + dw ARM_instruction_vshl.s64-instruction_handler + db 'vshl.u16',0xe0 + dw ARM_instruction_vshl.u16-instruction_handler + db 'vshl.u32',0xe0 + dw ARM_instruction_vshl.u32-instruction_handler + db 'vshl.u64',0xe0 + dw ARM_instruction_vshl.u64-instruction_handler + db 'vshll.i8',0xe0 + dw ARM_instruction_vshll.i8-instruction_handler + db 'vshll.s8',0xe0 + dw ARM_instruction_vshll.s8-instruction_handler + db 'vshll.u8',0xe0 + dw ARM_instruction_vshll.u8-instruction_handler + db 'vshr.s16',0xe0 + dw ARM_instruction_vshr.s16-instruction_handler + db 'vshr.s32',0xe0 + dw ARM_instruction_vshr.s32-instruction_handler + db 'vshr.s64',0xe0 + dw ARM_instruction_vshr.s64-instruction_handler + db 'vshr.u16',0xe0 + dw ARM_instruction_vshr.u16-instruction_handler + db 'vshr.u32',0xe0 + dw ARM_instruction_vshr.u32-instruction_handler + db 'vshr.u64',0xe0 + dw ARM_instruction_vshr.u64-instruction_handler + db 'vsli~~.8',0x00 + dw ARM_instruction_vsli.8-instruction_handler + db 'vsra.s16',0xe0 + dw ARM_instruction_vsra.s16-instruction_handler + db 'vsra.s32',0xe0 + dw ARM_instruction_vsra.s32-instruction_handler + db 'vsra.s64',0xe0 + dw ARM_instruction_vsra.s64-instruction_handler + db 'vsra.u16',0xe0 + dw ARM_instruction_vsra.u16-instruction_handler + db 'vsra.u32',0xe0 + dw ARM_instruction_vsra.u32-instruction_handler + db 'vsra.u64',0xe0 + dw ARM_instruction_vsra.u64-instruction_handler + db 'vsri~~.8',0x00 + dw ARM_instruction_vsri.8-instruction_handler + db 'vst1~~.8',0x00 + dw ARM_instruction_vst1.8-instruction_handler + db 'vst2~~.8',0x00 + dw ARM_instruction_vst2.8-instruction_handler + db 'vst3~~.8',0x00 + dw ARM_instruction_vst3.8-instruction_handler + db 'vst4~~.8',0x00 + dw ARM_instruction_vst4.8-instruction_handler + db 'vstmdb~~',0x00 + dw ARM_instruction_vstmdb-instruction_handler + db 'vstmea~~',0x00 + dw ARM_instruction_vstmea-instruction_handler + db 'vstmfd~~',0x00 + dw ARM_instruction_vstmfd-instruction_handler + db 'vstmia~~',0x00 + dw ARM_instruction_vstmia-instruction_handler + db 'vsub.f32',0xe0 + dw ARM_instruction_vsub.f32-instruction_handler + db 'vsub.f64',0xe0 + dw ARM_instruction_vsub.f64-instruction_handler + db 'vsub.i16',0xe0 + dw ARM_instruction_vsub.i16-instruction_handler + db 'vsub.i32',0xe0 + dw ARM_instruction_vsub.i32-instruction_handler + db 'vsub.i64',0xe0 + dw ARM_instruction_vsub.i64-instruction_handler + db 'vsubl.s8',0xe0 + dw ARM_instruction_vsubl.s8-instruction_handler + db 'vsubl.u8',0xe0 + dw ARM_instruction_vsubl.u8-instruction_handler + db 'vsubw.s8',0xe0 + dw ARM_instruction_vsubw.s8-instruction_handler + db 'vsubw.u8',0xe0 + dw ARM_instruction_vsubw.u8-instruction_handler + db 'vtbl~~.8',0x00 + dw ARM_instruction_vtbl.8-instruction_handler + db 'vtbx~~.8',0x00 + dw ARM_instruction_vtbx.8-instruction_handler + db 'vtrn~~.8',0x00 + dw ARM_instruction_vtrn.8-instruction_handler + db 'vtst~~.8',0x00 + dw ARM_instruction_vtst.8-instruction_handler + db 'vuzp~~.8',0x00 + dw ARM_instruction_vuzp.8-instruction_handler + db 'vzip~~.8',0x00 + dw ARM_instruction_vzip.8-instruction_handler + db 'waddhc~~',0x00 + dw ARM_instruction_waddhc-instruction_handler + db 'waddwc~~',0x00 + dw ARM_instruction_waddwc-instruction_handler + db 'walignr0',0xe0 + dw ARM_instruction_walignr0-instruction_handler + db 'walignr1',0xe0 + dw ARM_instruction_walignr1-instruction_handler + db 'walignr2',0xe0 + dw ARM_instruction_walignr2-instruction_handler + db 'walignr3',0xe0 + dw ARM_instruction_walignr3-instruction_handler + db 'wavg2b~~',0x00 + dw ARM_instruction_wavg2b-instruction_handler + db 'wavg2h~~',0x00 + dw ARM_instruction_wavg2h-instruction_handler + db 'wavg4r~~',0x00 + dw ARM_instruction_wavg4r-instruction_handler + db 'wcmpgtsb',0xe0 + dw ARM_instruction_wcmpgtsb-instruction_handler + db 'wcmpgtsh',0xe0 + dw ARM_instruction_wcmpgtsh-instruction_handler + db 'wcmpgtsw',0xe0 + dw ARM_instruction_wcmpgtsw-instruction_handler + db 'wcmpgtub',0xe0 + dw ARM_instruction_wcmpgtub-instruction_handler + db 'wcmpgtuh',0xe0 + dw ARM_instruction_wcmpgtuh-instruction_handler + db 'wcmpgtuw',0xe0 + dw ARM_instruction_wcmpgtuw-instruction_handler + db 'wmacsz~~',0x00 + dw ARM_instruction_wmacsz-instruction_handler + db 'wmacuz~~',0x00 + dw ARM_instruction_wmacuz-instruction_handler + db 'wmadds~~',0x00 + dw ARM_instruction_wmadds-instruction_handler + db 'wmaddu~~',0x00 + dw ARM_instruction_wmaddu-instruction_handler + db 'wmaxsb~~',0x00 + dw ARM_instruction_wmaxsb-instruction_handler + db 'wmaxsh~~',0x00 + dw ARM_instruction_wmaxsh-instruction_handler + db 'wmaxsw~~',0x00 + dw ARM_instruction_wmaxsw-instruction_handler + db 'wmaxub~~',0x00 + dw ARM_instruction_wmaxub-instruction_handler + db 'wmaxuh~~',0x00 + dw ARM_instruction_wmaxuh-instruction_handler + db 'wmaxuw~~',0x00 + dw ARM_instruction_wmaxuw-instruction_handler + db 'wmerge~~',0x00 + dw ARM_instruction_wmerge-instruction_handler + db 'wmiabb~~',0x00 + dw ARM_instruction_wmiabb-instruction_handler + db 'wmiabt~~',0x00 + dw ARM_instruction_wmiabt-instruction_handler + db 'wmiatb~~',0x00 + dw ARM_instruction_wmiatb-instruction_handler + db 'wmiatt~~',0x00 + dw ARM_instruction_wmiatt-instruction_handler + db 'wmiawbbn',0xe0 + dw ARM_instruction_wmiawbbn-instruction_handler + db 'wmiawbtn',0xe0 + dw ARM_instruction_wmiawbtn-instruction_handler + db 'wmiawtbn',0xe0 + dw ARM_instruction_wmiawtbn-instruction_handler + db 'wmiawttn',0xe0 + dw ARM_instruction_wmiawttn-instruction_handler + db 'wminsb~~',0x00 + dw ARM_instruction_wminsb-instruction_handler + db 'wminsh~~',0x00 + dw ARM_instruction_wminsh-instruction_handler + db 'wminsw~~',0x00 + dw ARM_instruction_wminsw-instruction_handler + db 'wminub~~',0x00 + dw ARM_instruction_wminub-instruction_handler + db 'wminuh~~',0x00 + dw ARM_instruction_wminuh-instruction_handler + db 'wminuw~~',0x00 + dw ARM_instruction_wminuw-instruction_handler + db 'wmulsl~~',0x00 + dw ARM_instruction_wmulsl-instruction_handler + db 'wmulsm~~',0x00 + dw ARM_instruction_wmulsm-instruction_handler + db 'wmulul~~',0x00 + dw ARM_instruction_wmulul-instruction_handler + db 'wmulum~~',0x00 + dw ARM_instruction_wmulum-instruction_handler + db 'wmulwl~~',0x00 + dw ARM_instruction_wmulwl-instruction_handler + db 'wmulwsmr',0xe0 + dw ARM_instruction_wmulwsmr-instruction_handler + db 'wmulwumr',0xe0 + dw ARM_instruction_wmulwumr-instruction_handler + db 'wpackdss',0xe0 + dw ARM_instruction_wpackdss-instruction_handler + db 'wpackdus',0xe0 + dw ARM_instruction_wpackdus-instruction_handler + db 'wpackhss',0xe0 + dw ARM_instruction_wpackhss-instruction_handler + db 'wpackhus',0xe0 + dw ARM_instruction_wpackhus-instruction_handler + db 'wpackwss',0xe0 + dw ARM_instruction_wpackwss-instruction_handler + db 'wpackwus',0xe0 + dw ARM_instruction_wpackwus-instruction_handler + db 'wqmiabbn',0xe0 + dw ARM_instruction_wqmiabbn-instruction_handler + db 'wqmiabtn',0xe0 + dw ARM_instruction_wqmiabtn-instruction_handler + db 'wqmiatbn',0xe0 + dw ARM_instruction_wqmiatbn-instruction_handler + db 'wqmiattn',0xe0 + dw ARM_instruction_wqmiattn-instruction_handler + db 'wqmulm~~',0x00 + dw ARM_instruction_wqmulm-instruction_handler + db 'wqmulwmr',0xe0 + dw ARM_instruction_wqmulwmr-instruction_handler + db 'wrordg~~',0x00 + dw ARM_instruction_wrordg-instruction_handler + db 'wrorhg~~',0x00 + dw ARM_instruction_wrorhg-instruction_handler + db 'wrorwg~~',0x00 + dw ARM_instruction_wrorwg-instruction_handler + db 'wsadbz~~',0x00 + dw ARM_instruction_wsadbz-instruction_handler + db 'wsadhz~~',0x00 + dw ARM_instruction_wsadhz-instruction_handler + db 'wshufh~~',0x00 + dw ARM_instruction_wshufh-instruction_handler + db 'wslldg~~',0x00 + dw ARM_instruction_wslldg-instruction_handler + db 'wsllhg~~',0x00 + dw ARM_instruction_wsllhg-instruction_handler + db 'wsllwg~~',0x00 + dw ARM_instruction_wsllwg-instruction_handler + db 'wsradg~~',0x00 + dw ARM_instruction_wsradg-instruction_handler + db 'wsrahg~~',0x00 + dw ARM_instruction_wsrahg-instruction_handler + db 'wsrawg~~',0x00 + dw ARM_instruction_wsrawg-instruction_handler + db 'wsrldg~~',0x00 + dw ARM_instruction_wsrldg-instruction_handler + db 'wsrlhg~~',0x00 + dw ARM_instruction_wsrlhg-instruction_handler + db 'wsrlwg~~',0x00 + dw ARM_instruction_wsrlwg-instruction_handler + db 0 +instructions_9: + db 'cfabs32~~',0x00 + dw ARM_instruction_cfabs32-instruction_handler + db 'cfabs64~~',0x00 + dw ARM_instruction_cfabs64-instruction_handler + db 'cfadd32~~',0x00 + dw ARM_instruction_cfadd32-instruction_handler + db 'cfadd64~~',0x00 + dw ARM_instruction_cfadd64-instruction_handler + db 'cfcmp32~~',0x00 + dw ARM_instruction_cfcmp32-instruction_handler + db 'cfcmp64~~',0x00 + dw ARM_instruction_cfcmp64-instruction_handler + db 'cfcvtds~~',0x00 + dw ARM_instruction_cfcvtds-instruction_handler + db 'cfcvtsd~~',0x00 + dw ARM_instruction_cfcvtsd-instruction_handler + db 'cfldr32~~',0x00 + dw ARM_instruction_cfldr32-instruction_handler + db 'cfldr64~~',0x00 + dw ARM_instruction_cfldr64-instruction_handler + db 'cfmac32~~',0x00 + dw ARM_instruction_cfmac32-instruction_handler + db 'cfmadda32',0xe0 + dw ARM_instruction_cfmadda32-instruction_handler + db 'cfmsc32~~',0x00 + dw ARM_instruction_cfmsc32-instruction_handler + db 'cfmsuba32',0xe0 + dw ARM_instruction_cfmsuba32-instruction_handler + db 'cfmul32~~',0x00 + dw ARM_instruction_cfmul32-instruction_handler + db 'cfmul64~~',0x00 + dw ARM_instruction_cfmul64-instruction_handler + db 'cfmv32a~~',0x00 + dw ARM_instruction_cfmv32a-instruction_handler + db 'cfmv64a~~',0x00 + dw ARM_instruction_cfmv64a-instruction_handler + db 'cfmva32~~',0x00 + dw ARM_instruction_cfmva32-instruction_handler + db 'cfmva64~~',0x00 + dw ARM_instruction_cfmva64-instruction_handler + db 'cfmvdhr~~',0x00 + dw ARM_instruction_cfmvdhr-instruction_handler + db 'cfmvdlr~~',0x00 + dw ARM_instruction_cfmvdlr-instruction_handler + db 'cfmvrdh~~',0x00 + dw ARM_instruction_cfmvrdh-instruction_handler + db 'cfmvrdl~~',0x00 + dw ARM_instruction_cfmvrdl-instruction_handler + db 'cfneg32~~',0x00 + dw ARM_instruction_cfneg32-instruction_handler + db 'cfneg64~~',0x00 + dw ARM_instruction_cfneg64-instruction_handler + db 'cfstr32~~',0x00 + dw ARM_instruction_cfstr32-instruction_handler + db 'cfstr64~~',0x00 + dw ARM_instruction_cfstr64-instruction_handler + db 'cfsub32~~',0x00 + dw ARM_instruction_cfsub32-instruction_handler + db 'cfsub64~~',0x00 + dw ARM_instruction_cfsub64-instruction_handler + db 'fcmpezd~~',0x00 + dw ARM_instruction_fcmpezd-instruction_handler + db 'fcmpezs~~',0x00 + dw ARM_instruction_fcmpezs-instruction_handler + db 'fconstd~~',0x00 + dw ARM_instruction_fconstd-instruction_handler + db 'fconsts~~',0x00 + dw ARM_instruction_fconsts-instruction_handler + db 'fldmdbd~~',0x00 + dw ARM_instruction_fldmdbd-instruction_handler + db 'fldmdbs~~',0x00 + dw ARM_instruction_fldmdbs-instruction_handler + db 'fldmdbx~~',0x00 + dw ARM_instruction_fldmdbx-instruction_handler + db 'fldmead~~',0x00 + dw ARM_instruction_fldmead-instruction_handler + db 'fldmeas~~',0x00 + dw ARM_instruction_fldmeas-instruction_handler + db 'fldmeax~~',0x00 + dw ARM_instruction_fldmeax-instruction_handler + db 'fldmfdd~~',0x00 + dw ARM_instruction_fldmfdd-instruction_handler + db 'fldmfds~~',0x00 + dw ARM_instruction_fldmfds-instruction_handler + db 'fldmfdx~~',0x00 + dw ARM_instruction_fldmfdx-instruction_handler + db 'fldmiad~~',0x00 + dw ARM_instruction_fldmiad-instruction_handler + db 'fldmias~~',0x00 + dw ARM_instruction_fldmias-instruction_handler + db 'fldmiax~~',0x00 + dw ARM_instruction_fldmiax-instruction_handler + db 'fstmdbd~~',0x00 + dw ARM_instruction_fstmdbd-instruction_handler + db 'fstmdbs~~',0x00 + dw ARM_instruction_fstmdbs-instruction_handler + db 'fstmdbx~~',0x00 + dw ARM_instruction_fstmdbx-instruction_handler + db 'fstmead~~',0x00 + dw ARM_instruction_fstmead-instruction_handler + db 'fstmeas~~',0x00 + dw ARM_instruction_fstmeas-instruction_handler + db 'fstmeax~~',0x00 + dw ARM_instruction_fstmeax-instruction_handler + db 'fstmfdd~~',0x00 + dw ARM_instruction_fstmfdd-instruction_handler + db 'fstmfds~~',0x00 + dw ARM_instruction_fstmfds-instruction_handler + db 'fstmfdx~~',0x00 + dw ARM_instruction_fstmfdx-instruction_handler + db 'fstmiad~~',0x00 + dw ARM_instruction_fstmiad-instruction_handler + db 'fstmias~~',0x00 + dw ARM_instruction_fstmias-instruction_handler + db 'fstmiax~~',0x00 + dw ARM_instruction_fstmiax-instruction_handler + db 'ftosizd~~',0x00 + dw ARM_instruction_ftosizd-instruction_handler + db 'ftosizs~~',0x00 + dw ARM_instruction_ftosizs-instruction_handler + db 'ftouizd~~',0x00 + dw ARM_instruction_ftouizd-instruction_handler + db 'ftouizs~~',0x00 + dw ARM_instruction_ftouizs-instruction_handler + db 'ldmfd~~.n',0x04 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmfd~~.w',0x02 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldmia~~.n',0x04 + dw ARM_instruction_ldmia-instruction_handler + db 'ldmia~~.w',0x02 + dw ARM_instruction_ldmia-instruction_handler + db 'ldm~~fd.n',0x04 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldm~~fd.w',0x02 + dw ARM_instruction_ldmfd-instruction_handler + db 'ldm~~ia.n',0x04 + dw ARM_instruction_ldmia-instruction_handler + db 'ldm~~ia.w',0x02 + dw ARM_instruction_ldmia-instruction_handler + db 'ldrsb~~.n',0x04 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsb~~.w',0x02 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldrsh~~.n',0x04 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldrsh~~.w',0x02 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldr~~sb.n',0x04 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldr~~sb.w',0x02 + dw ARM_instruction_ldrsb-instruction_handler + db 'ldr~~sh.n',0x04 + dw ARM_instruction_ldrsh-instruction_handler + db 'ldr~~sh.w',0x02 + dw ARM_instruction_ldrsh-instruction_handler + db 'processor',0x00 + dw ARM_processor_directive-instruction_handler + db 'rev16~~.n',0x04 + dw ARM_instruction_rev16-instruction_handler + db 'rev16~~.w',0x02 + dw ARM_instruction_rev16-instruction_handler + db 'revsh~~.n',0x04 + dw ARM_instruction_revsh-instruction_handler + db 'revsh~~.w',0x02 + dw ARM_instruction_revsh-instruction_handler + db 'sha256su0',0xf0 + dw ARM_instruction_sha256su0-instruction_handler + db 'sha256su1',0xf0 + dw ARM_instruction_sha256su1-instruction_handler + db 'shadd16~~',0x00 + dw ARM_instruction_shadd16-instruction_handler + db 'shaddsubx',0xe0 + dw ARM_instruction_shaddsubx-instruction_handler + db 'shsub16~~',0x00 + dw ARM_instruction_shsub16-instruction_handler + db 'shsubaddx',0xe0 + dw ARM_instruction_shsubaddx-instruction_handler + db 'smlalbb~~',0x00 + dw ARM_instruction_smlalbb-instruction_handler + db 'smlalbt~~',0x00 + dw ARM_instruction_smlalbt-instruction_handler + db 'smlaldx~~',0x00 + dw ARM_instruction_smlaldx-instruction_handler + db 'smlaltb~~',0x00 + dw ARM_instruction_smlaltb-instruction_handler + db 'smlaltt~~',0x00 + dw ARM_instruction_smlaltt-instruction_handler + db 'smlsldx~~',0x00 + dw ARM_instruction_smlsldx-instruction_handler + db 'sqrshrun2',0xf0 + dw ARM_instruction_sqrshrun2-instruction_handler + db 'stmdb~~.n',0x04 + dw ARM_instruction_stmdb-instruction_handler + db 'stmdb~~.w',0x02 + dw ARM_instruction_stmdb-instruction_handler + db 'stmfd~~.n',0x04 + dw ARM_instruction_stmfd-instruction_handler + db 'stmfd~~.w',0x02 + dw ARM_instruction_stmfd-instruction_handler + db 'stmia~~.n',0x04 + dw ARM_instruction_stmia-instruction_handler + db 'stmia~~.w',0x02 + dw ARM_instruction_stmia-instruction_handler + db 'stm~~db.n',0x04 + dw ARM_instruction_stmdb-instruction_handler + db 'stm~~db.w',0x02 + dw ARM_instruction_stmdb-instruction_handler + db 'stm~~fd.n',0x04 + dw ARM_instruction_stmfd-instruction_handler + db 'stm~~fd.w',0x02 + dw ARM_instruction_stmfd-instruction_handler + db 'stm~~ia.n',0x04 + dw ARM_instruction_stmia-instruction_handler + db 'stm~~ia.w',0x02 + dw ARM_instruction_stmia-instruction_handler + db 'sxtab16~~',0x00 + dw ARM_instruction_sxtab16-instruction_handler + db 'textrcb~~',0x00 + dw ARM_instruction_textrcb-instruction_handler + db 'textrch~~',0x00 + dw ARM_instruction_textrch-instruction_handler + db 'textrcw~~',0x00 + dw ARM_instruction_textrcw-instruction_handler + db 'torvscb~~',0x00 + dw ARM_instruction_torvscb-instruction_handler + db 'torvsch~~',0x00 + dw ARM_instruction_torvsch-instruction_handler + db 'torvscw~~',0x00 + dw ARM_instruction_torvscw-instruction_handler + db 'uhadd16~~',0x00 + dw ARM_instruction_uhadd16-instruction_handler + db 'uhaddsubx',0xe0 + dw ARM_instruction_uhaddsubx-instruction_handler + db 'uhsub16~~',0x00 + dw ARM_instruction_uhsub16-instruction_handler + db 'uhsubaddx',0xe0 + dw ARM_instruction_uhsubaddx-instruction_handler + db 'uqadd16~~',0x00 + dw ARM_instruction_uqadd16-instruction_handler + db 'uqaddsubx',0xe0 + dw ARM_instruction_uqaddsubx-instruction_handler + db 'uqsub16~~',0x00 + dw ARM_instruction_uqsub16-instruction_handler + db 'uqsubaddx',0xe0 + dw ARM_instruction_uqsubaddx-instruction_handler + db 'uxtab16~~',0x00 + dw ARM_instruction_uxtab16-instruction_handler + db 'vabal.s16',0xe0 + dw ARM_instruction_vabal.s16-instruction_handler + db 'vabal.s32',0xe0 + dw ARM_instruction_vabal.s32-instruction_handler + db 'vabal.u16',0xe0 + dw ARM_instruction_vabal.u16-instruction_handler + db 'vabal.u32',0xe0 + dw ARM_instruction_vabal.u32-instruction_handler + db 'vaba~~.s8',0x00 + dw ARM_instruction_vaba.s8-instruction_handler + db 'vaba~~.u8',0x00 + dw ARM_instruction_vaba.u8-instruction_handler + db 'vabdl.s16',0xe0 + dw ARM_instruction_vabdl.s16-instruction_handler + db 'vabdl.s32',0xe0 + dw ARM_instruction_vabdl.s32-instruction_handler + db 'vabdl.u16',0xe0 + dw ARM_instruction_vabdl.u16-instruction_handler + db 'vabdl.u32',0xe0 + dw ARM_instruction_vabdl.u32-instruction_handler + db 'vabd~~.s8',0x00 + dw ARM_instruction_vabd.s8-instruction_handler + db 'vabd~~.u8',0x00 + dw ARM_instruction_vabd.u8-instruction_handler + db 'vabs~~.s8',0x00 + dw ARM_instruction_vabs.s8-instruction_handler + db 'vacge.f32',0xe0 + dw ARM_instruction_vacge.f32-instruction_handler + db 'vacgt.f32',0xe0 + dw ARM_instruction_vacgt.f32-instruction_handler + db 'vacle.f32',0xe0 + dw ARM_instruction_vacle.f32-instruction_handler + db 'vaclt.f32',0xe0 + dw ARM_instruction_vaclt.f32-instruction_handler + db 'vaddl.s16',0xe0 + dw ARM_instruction_vaddl.s16-instruction_handler + db 'vaddl.s32',0xe0 + dw ARM_instruction_vaddl.s32-instruction_handler + db 'vaddl.u16',0xe0 + dw ARM_instruction_vaddl.u16-instruction_handler + db 'vaddl.u32',0xe0 + dw ARM_instruction_vaddl.u32-instruction_handler + db 'vaddw.s16',0xe0 + dw ARM_instruction_vaddw.s16-instruction_handler + db 'vaddw.s32',0xe0 + dw ARM_instruction_vaddw.s32-instruction_handler + db 'vaddw.u16',0xe0 + dw ARM_instruction_vaddw.u16-instruction_handler + db 'vaddw.u32',0xe0 + dw ARM_instruction_vaddw.u32-instruction_handler + db 'vadd~~.i8',0x00 + dw ARM_instruction_vadd.i8-instruction_handler + db 'vceq~~.i8',0x00 + dw ARM_instruction_vceq.i8-instruction_handler + db 'vcge~~.s8',0x00 + dw ARM_instruction_vcge.s8-instruction_handler + db 'vcge~~.u8',0x00 + dw ARM_instruction_vcge.u8-instruction_handler + db 'vcgt~~.s8',0x00 + dw ARM_instruction_vcgt.s8-instruction_handler + db 'vcgt~~.u8',0x00 + dw ARM_instruction_vcgt.u8-instruction_handler + db 'vcle~~.s8',0x00 + dw ARM_instruction_vcle.s8-instruction_handler + db 'vcle~~.u8',0x00 + dw ARM_instruction_vcle.u8-instruction_handler + db 'vcls~~.s8',0x00 + dw ARM_instruction_vcls.s8-instruction_handler + db 'vclt~~.s8',0x00 + dw ARM_instruction_vclt.s8-instruction_handler + db 'vclt~~.u8',0x00 + dw ARM_instruction_vclt.u8-instruction_handler + db 'vclz~~.i8',0x00 + dw ARM_instruction_vclz.i8-instruction_handler + db 'vcmpe.f32',0xe0 + dw ARM_instruction_vcmpe.f32-instruction_handler + db 'vcmpe.f64',0xe0 + dw ARM_instruction_vcmpe.f64-instruction_handler + db 'vdup~~.16',0x00 + dw ARM_instruction_vdup.16-instruction_handler + db 'vdup~~.32',0x00 + dw ARM_instruction_vdup.32-instruction_handler + db 'vext~~.16',0x00 + dw ARM_instruction_vext.16-instruction_handler + db 'vext~~.32',0x00 + dw ARM_instruction_vext.32-instruction_handler + db 'vext~~.64',0x00 + dw ARM_instruction_vext.64-instruction_handler + db 'vfnma.f32',0xe0 + dw ARM_instruction_vfnma.f32-instruction_handler + db 'vfnma.f64',0xe0 + dw ARM_instruction_vfnma.f64-instruction_handler + db 'vfnms.f32',0xe0 + dw ARM_instruction_vfnms.f32-instruction_handler + db 'vfnms.f64',0xe0 + dw ARM_instruction_vfnms.f64-instruction_handler + db 'vhadd.s16',0xe0 + dw ARM_instruction_vhadd.s16-instruction_handler + db 'vhadd.s32',0xe0 + dw ARM_instruction_vhadd.s32-instruction_handler + db 'vhadd.u16',0xe0 + dw ARM_instruction_vhadd.u16-instruction_handler + db 'vhadd.u32',0xe0 + dw ARM_instruction_vhadd.u32-instruction_handler + db 'vhsub.s16',0xe0 + dw ARM_instruction_vhsub.s16-instruction_handler + db 'vhsub.s32',0xe0 + dw ARM_instruction_vhsub.s32-instruction_handler + db 'vhsub.u16',0xe0 + dw ARM_instruction_vhsub.u16-instruction_handler + db 'vhsub.u32',0xe0 + dw ARM_instruction_vhsub.u32-instruction_handler + db 'vld1~~.16',0x00 + dw ARM_instruction_vld1.16-instruction_handler + db 'vld1~~.32',0x00 + dw ARM_instruction_vld1.32-instruction_handler + db 'vld1~~.64',0x00 + dw ARM_instruction_vld1.64-instruction_handler + db 'vld2~~.16',0x00 + dw ARM_instruction_vld2.16-instruction_handler + db 'vld2~~.32',0x00 + dw ARM_instruction_vld2.32-instruction_handler + db 'vld3~~.16',0x00 + dw ARM_instruction_vld3.16-instruction_handler + db 'vld3~~.32',0x00 + dw ARM_instruction_vld3.32-instruction_handler + db 'vld4~~.16',0x00 + dw ARM_instruction_vld4.16-instruction_handler + db 'vld4~~.32',0x00 + dw ARM_instruction_vld4.32-instruction_handler + db 'vldmdb.32',0xe0 + dw ARM_instruction_vldmdb.32-instruction_handler + db 'vldmdb.64',0xe0 + dw ARM_instruction_vldmdb.64-instruction_handler + db 'vldmea.32',0xe0 + dw ARM_instruction_vldmea.32-instruction_handler + db 'vldmea.64',0xe0 + dw ARM_instruction_vldmea.64-instruction_handler + db 'vldmfd.32',0xe0 + dw ARM_instruction_vldmfd.32-instruction_handler + db 'vldmfd.64',0xe0 + dw ARM_instruction_vldmfd.64-instruction_handler + db 'vldmia.32',0xe0 + dw ARM_instruction_vldmia.32-instruction_handler + db 'vldmia.64',0xe0 + dw ARM_instruction_vldmia.64-instruction_handler + db 'vldm~~.32',0x00 + dw ARM_instruction_vldm.32-instruction_handler + db 'vldm~~.64',0x00 + dw ARM_instruction_vldm.64-instruction_handler + db 'vldr~~.32',0x00 + dw ARM_instruction_vldr.32-instruction_handler + db 'vldr~~.64',0x00 + dw ARM_instruction_vldr.64-instruction_handler + db 'vmax~~.s8',0x00 + dw ARM_instruction_vmax.s8-instruction_handler + db 'vmax~~.u8',0x00 + dw ARM_instruction_vmax.u8-instruction_handler + db 'vmin~~.s8',0x00 + dw ARM_instruction_vmin.s8-instruction_handler + db 'vmin~~.u8',0x00 + dw ARM_instruction_vmin.u8-instruction_handler + db 'vmlal.s16',0xe0 + dw ARM_instruction_vmlal.s16-instruction_handler + db 'vmlal.s32',0xe0 + dw ARM_instruction_vmlal.s32-instruction_handler + db 'vmlal.u16',0xe0 + dw ARM_instruction_vmlal.u16-instruction_handler + db 'vmlal.u32',0xe0 + dw ARM_instruction_vmlal.u32-instruction_handler + db 'vmla~~.i8',0x00 + dw ARM_instruction_vmla.i8-instruction_handler + db 'vmla~~.s8',0x00 + dw ARM_instruction_vmla.s8-instruction_handler + db 'vmla~~.u8',0x00 + dw ARM_instruction_vmla.u8-instruction_handler + db 'vmlsl.s16',0xe0 + dw ARM_instruction_vmlsl.s16-instruction_handler + db 'vmlsl.s32',0xe0 + dw ARM_instruction_vmlsl.s32-instruction_handler + db 'vmlsl.u16',0xe0 + dw ARM_instruction_vmlsl.u16-instruction_handler + db 'vmlsl.u32',0xe0 + dw ARM_instruction_vmlsl.u32-instruction_handler + db 'vmls~~.i8',0x00 + dw ARM_instruction_vmls.i8-instruction_handler + db 'vmls~~.s8',0x00 + dw ARM_instruction_vmls.s8-instruction_handler + db 'vmls~~.u8',0x00 + dw ARM_instruction_vmls.u8-instruction_handler + db 'vmovl.s16',0xe0 + dw ARM_instruction_vmovl.s16-instruction_handler + db 'vmovl.s32',0xe0 + dw ARM_instruction_vmovl.s32-instruction_handler + db 'vmovl.u16',0xe0 + dw ARM_instruction_vmovl.u16-instruction_handler + db 'vmovl.u32',0xe0 + dw ARM_instruction_vmovl.u32-instruction_handler + db 'vmovn.i16',0xe0 + dw ARM_instruction_vmovn.i16-instruction_handler + db 'vmovn.i32',0xe0 + dw ARM_instruction_vmovn.i32-instruction_handler + db 'vmov~~.16',0x00 + dw ARM_instruction_vmov.16-instruction_handler + db 'vmov~~.32',0x00 + dw ARM_instruction_vmov.32-instruction_handler + db 'vmov~~.i8',0x00 + dw ARM_instruction_vmov.i8-instruction_handler + db 'vmov~~.s8',0x00 + dw ARM_instruction_vmov.s8-instruction_handler + db 'vmov~~.u8',0x00 + dw ARM_instruction_vmov.u8-instruction_handler + db 'vmull.p64',0xf0 + dw ARM_instruction_vmull.p64-instruction_handler + db 'vmull.s16',0xe0 + dw ARM_instruction_vmull.s16-instruction_handler + db 'vmull.s32',0xe0 + dw ARM_instruction_vmull.s32-instruction_handler + db 'vmull.u16',0xe0 + dw ARM_instruction_vmull.u16-instruction_handler + db 'vmull.u32',0xe0 + dw ARM_instruction_vmull.u32-instruction_handler + db 'vmul~~.i8',0x00 + dw ARM_instruction_vmul.i8-instruction_handler + db 'vmul~~.p8',0x00 + dw ARM_instruction_vmul.p8-instruction_handler + db 'vmul~~.s8',0x00 + dw ARM_instruction_vmul.s8-instruction_handler + db 'vmul~~.u8',0x00 + dw ARM_instruction_vmul.u8-instruction_handler + db 'vneg~~.s8',0x00 + dw ARM_instruction_vneg.s8-instruction_handler + db 'vnmla.f32',0xe0 + dw ARM_instruction_vnmla.f32-instruction_handler + db 'vnmla.f64',0xe0 + dw ARM_instruction_vnmla.f64-instruction_handler + db 'vnmls.f32',0xe0 + dw ARM_instruction_vnmls.f32-instruction_handler + db 'vnmls.f64',0xe0 + dw ARM_instruction_vnmls.f64-instruction_handler + db 'vnmul.f32',0xe0 + dw ARM_instruction_vnmul.f32-instruction_handler + db 'vnmul.f64',0xe0 + dw ARM_instruction_vnmul.f64-instruction_handler + db 'vpadal.s8',0xe0 + dw ARM_instruction_vpadal.s8-instruction_handler + db 'vpadal.u8',0xe0 + dw ARM_instruction_vpadal.u8-instruction_handler + db 'vpadd.f32',0xe0 + dw ARM_instruction_vpadd.f32-instruction_handler + db 'vpadd.i16',0xe0 + dw ARM_instruction_vpadd.i16-instruction_handler + db 'vpadd.i32',0xe0 + dw ARM_instruction_vpadd.i32-instruction_handler + db 'vpaddl.s8',0xe0 + dw ARM_instruction_vpaddl.s8-instruction_handler + db 'vpaddl.u8',0xe0 + dw ARM_instruction_vpaddl.u8-instruction_handler + db 'vpmax.f32',0xe0 + dw ARM_instruction_vpmax.f32-instruction_handler + db 'vpmax.s16',0xe0 + dw ARM_instruction_vpmax.s16-instruction_handler + db 'vpmax.s32',0xe0 + dw ARM_instruction_vpmax.s32-instruction_handler + db 'vpmax.u16',0xe0 + dw ARM_instruction_vpmax.u16-instruction_handler + db 'vpmax.u32',0xe0 + dw ARM_instruction_vpmax.u32-instruction_handler + db 'vpmin.f32',0xe0 + dw ARM_instruction_vpmin.f32-instruction_handler + db 'vpmin.s16',0xe0 + dw ARM_instruction_vpmin.s16-instruction_handler + db 'vpmin.s32',0xe0 + dw ARM_instruction_vpmin.s32-instruction_handler + db 'vpmin.u16',0xe0 + dw ARM_instruction_vpmin.u16-instruction_handler + db 'vpmin.u32',0xe0 + dw ARM_instruction_vpmin.u32-instruction_handler + db 'vpop~~.32',0x00 + dw ARM_instruction_vpop.32-instruction_handler + db 'vpop~~.64',0x00 + dw ARM_instruction_vpop.64-instruction_handler + db 'vqabs.s16',0xe0 + dw ARM_instruction_vqabs.s16-instruction_handler + db 'vqabs.s32',0xe0 + dw ARM_instruction_vqabs.s32-instruction_handler + db 'vqadd.s16',0xe0 + dw ARM_instruction_vqadd.s16-instruction_handler + db 'vqadd.s32',0xe0 + dw ARM_instruction_vqadd.s32-instruction_handler + db 'vqadd.s64',0xe0 + dw ARM_instruction_vqadd.s64-instruction_handler + db 'vqadd.u16',0xe0 + dw ARM_instruction_vqadd.u16-instruction_handler + db 'vqadd.u32',0xe0 + dw ARM_instruction_vqadd.u32-instruction_handler + db 'vqadd.u64',0xe0 + dw ARM_instruction_vqadd.u64-instruction_handler + db 'vqneg.s16',0xe0 + dw ARM_instruction_vqneg.s16-instruction_handler + db 'vqneg.s32',0xe0 + dw ARM_instruction_vqneg.s32-instruction_handler + db 'vqrshl.s8',0xe0 + dw ARM_instruction_vqrshl.s8-instruction_handler + db 'vqrshl.u8',0xe0 + dw ARM_instruction_vqrshl.u8-instruction_handler + db 'vqshl.s16',0xe0 + dw ARM_instruction_vqshl.s16-instruction_handler + db 'vqshl.s32',0xe0 + dw ARM_instruction_vqshl.s32-instruction_handler + db 'vqshl.s64',0xe0 + dw ARM_instruction_vqshl.s64-instruction_handler + db 'vqshl.u16',0xe0 + dw ARM_instruction_vqshl.u16-instruction_handler + db 'vqshl.u32',0xe0 + dw ARM_instruction_vqshl.u32-instruction_handler + db 'vqshl.u64',0xe0 + dw ARM_instruction_vqshl.u64-instruction_handler + db 'vqshlu.s8',0xe0 + dw ARM_instruction_vqshlu.s8-instruction_handler + db 'vqsub.s16',0xe0 + dw ARM_instruction_vqsub.s16-instruction_handler + db 'vqsub.s32',0xe0 + dw ARM_instruction_vqsub.s32-instruction_handler + db 'vqsub.s64',0xe0 + dw ARM_instruction_vqsub.s64-instruction_handler + db 'vqsub.u16',0xe0 + dw ARM_instruction_vqsub.u16-instruction_handler + db 'vqsub.u32',0xe0 + dw ARM_instruction_vqsub.u32-instruction_handler + db 'vqsub.u64',0xe0 + dw ARM_instruction_vqsub.u64-instruction_handler + db 'vrev32.16',0xe0 + dw ARM_instruction_vrev32.16-instruction_handler + db 'vrev64.16',0xe0 + dw ARM_instruction_vrev64.16-instruction_handler + db 'vrev64.32',0xe0 + dw ARM_instruction_vrev64.32-instruction_handler + db 'vrhadd.s8',0xe0 + dw ARM_instruction_vrhadd.s8-instruction_handler + db 'vrhadd.u8',0xe0 + dw ARM_instruction_vrhadd.u8-instruction_handler + db 'vrshl.s16',0xe0 + dw ARM_instruction_vrshl.s16-instruction_handler + db 'vrshl.s32',0xe0 + dw ARM_instruction_vrshl.s32-instruction_handler + db 'vrshl.s64',0xe0 + dw ARM_instruction_vrshl.s64-instruction_handler + db 'vrshl.u16',0xe0 + dw ARM_instruction_vrshl.u16-instruction_handler + db 'vrshl.u32',0xe0 + dw ARM_instruction_vrshl.u32-instruction_handler + db 'vrshl.u64',0xe0 + dw ARM_instruction_vrshl.u64-instruction_handler + db 'vrshr.s16',0xe0 + dw ARM_instruction_vrshr.s16-instruction_handler + db 'vrshr.s32',0xe0 + dw ARM_instruction_vrshr.s32-instruction_handler + db 'vrshr.s64',0xe0 + dw ARM_instruction_vrshr.s64-instruction_handler + db 'vrshr.u16',0xe0 + dw ARM_instruction_vrshr.u16-instruction_handler + db 'vrshr.u32',0xe0 + dw ARM_instruction_vrshr.u32-instruction_handler + db 'vrshr.u64',0xe0 + dw ARM_instruction_vrshr.u64-instruction_handler + db 'vrsra.s16',0xe0 + dw ARM_instruction_vrsra.s16-instruction_handler + db 'vrsra.s32',0xe0 + dw ARM_instruction_vrsra.s32-instruction_handler + db 'vrsra.s64',0xe0 + dw ARM_instruction_vrsra.s64-instruction_handler + db 'vrsra.u16',0xe0 + dw ARM_instruction_vrsra.u16-instruction_handler + db 'vrsra.u32',0xe0 + dw ARM_instruction_vrsra.u32-instruction_handler + db 'vrsra.u64',0xe0 + dw ARM_instruction_vrsra.u64-instruction_handler + db 'vshll.i16',0xe0 + dw ARM_instruction_vshll.i16-instruction_handler + db 'vshll.i32',0xe0 + dw ARM_instruction_vshll.i32-instruction_handler + db 'vshll.s16',0xe0 + dw ARM_instruction_vshll.s16-instruction_handler + db 'vshll.s32',0xe0 + dw ARM_instruction_vshll.s32-instruction_handler + db 'vshll.u16',0xe0 + dw ARM_instruction_vshll.u16-instruction_handler + db 'vshll.u32',0xe0 + dw ARM_instruction_vshll.u32-instruction_handler + db 'vshl~~.i8',0x00 + dw ARM_instruction_vshl.i8-instruction_handler + db 'vshl~~.s8',0x00 + dw ARM_instruction_vshl.s8-instruction_handler + db 'vshl~~.u8',0x00 + dw ARM_instruction_vshl.u8-instruction_handler + db 'vshrn.i16',0xe0 + dw ARM_instruction_vshrn.i16-instruction_handler + db 'vshrn.i32',0xe0 + dw ARM_instruction_vshrn.i32-instruction_handler + db 'vshrn.i64',0xe0 + dw ARM_instruction_vshrn.i64-instruction_handler + db 'vshr~~.s8',0x00 + dw ARM_instruction_vshr.s8-instruction_handler + db 'vshr~~.u8',0x00 + dw ARM_instruction_vshr.u8-instruction_handler + db 'vsli~~.16',0x00 + dw ARM_instruction_vsli.16-instruction_handler + db 'vsli~~.32',0x00 + dw ARM_instruction_vsli.32-instruction_handler + db 'vsli~~.64',0x00 + dw ARM_instruction_vsli.64-instruction_handler + db 'vsqrt.f32',0xe0 + dw ARM_instruction_vsqrt.f32-instruction_handler + db 'vsqrt.f64',0xe0 + dw ARM_instruction_vsqrt.f64-instruction_handler + db 'vsra~~.s8',0x00 + dw ARM_instruction_vsra.s8-instruction_handler + db 'vsra~~.u8',0x00 + dw ARM_instruction_vsra.u8-instruction_handler + db 'vsri~~.16',0x00 + dw ARM_instruction_vsri.16-instruction_handler + db 'vsri~~.32',0x00 + dw ARM_instruction_vsri.32-instruction_handler + db 'vsri~~.64',0x00 + dw ARM_instruction_vsri.64-instruction_handler + db 'vst1~~.16',0x00 + dw ARM_instruction_vst1.16-instruction_handler + db 'vst1~~.32',0x00 + dw ARM_instruction_vst1.32-instruction_handler + db 'vst1~~.64',0x00 + dw ARM_instruction_vst1.64-instruction_handler + db 'vst2~~.16',0x00 + dw ARM_instruction_vst2.16-instruction_handler + db 'vst2~~.32',0x00 + dw ARM_instruction_vst2.32-instruction_handler + db 'vst3~~.16',0x00 + dw ARM_instruction_vst3.16-instruction_handler + db 'vst3~~.32',0x00 + dw ARM_instruction_vst3.32-instruction_handler + db 'vst4~~.16',0x00 + dw ARM_instruction_vst4.16-instruction_handler + db 'vst4~~.32',0x00 + dw ARM_instruction_vst4.32-instruction_handler + db 'vstmdb.32',0xe0 + dw ARM_instruction_vstmdb.32-instruction_handler + db 'vstmdb.64',0xe0 + dw ARM_instruction_vstmdb.64-instruction_handler + db 'vstmea.32',0xe0 + dw ARM_instruction_vstmea.32-instruction_handler + db 'vstmea.64',0xe0 + dw ARM_instruction_vstmea.64-instruction_handler + db 'vstmfd.32',0xe0 + dw ARM_instruction_vstmfd.32-instruction_handler + db 'vstmfd.64',0xe0 + dw ARM_instruction_vstmfd.64-instruction_handler + db 'vstmia.32',0xe0 + dw ARM_instruction_vstmia.32-instruction_handler + db 'vstmia.64',0xe0 + dw ARM_instruction_vstmia.64-instruction_handler + db 'vstm~~.32',0x00 + dw ARM_instruction_vstm.32-instruction_handler + db 'vstm~~.64',0x00 + dw ARM_instruction_vstm.64-instruction_handler + db 'vstr~~.32',0x00 + dw ARM_instruction_vstr.32-instruction_handler + db 'vstr~~.64',0x00 + dw ARM_instruction_vstr.64-instruction_handler + db 'vsubl.s16',0xe0 + dw ARM_instruction_vsubl.s16-instruction_handler + db 'vsubl.s32',0xe0 + dw ARM_instruction_vsubl.s32-instruction_handler + db 'vsubl.u16',0xe0 + dw ARM_instruction_vsubl.u16-instruction_handler + db 'vsubl.u32',0xe0 + dw ARM_instruction_vsubl.u32-instruction_handler + db 'vsubw.s16',0xe0 + dw ARM_instruction_vsubw.s16-instruction_handler + db 'vsubw.s32',0xe0 + dw ARM_instruction_vsubw.s32-instruction_handler + db 'vsubw.u16',0xe0 + dw ARM_instruction_vsubw.u16-instruction_handler + db 'vsubw.u32',0xe0 + dw ARM_instruction_vsubw.u32-instruction_handler + db 'vsub~~.i8',0x00 + dw ARM_instruction_vsub.i8-instruction_handler + db 'vtrn~~.16',0x00 + dw ARM_instruction_vtrn.16-instruction_handler + db 'vtrn~~.32',0x00 + dw ARM_instruction_vtrn.32-instruction_handler + db 'vtst~~.16',0x00 + dw ARM_instruction_vtst.16-instruction_handler + db 'vtst~~.32',0x00 + dw ARM_instruction_vtst.32-instruction_handler + db 'vuzp~~.16',0x00 + dw ARM_instruction_vuzp.16-instruction_handler + db 'vuzp~~.32',0x00 + dw ARM_instruction_vuzp.32-instruction_handler + db 'vzip~~.16',0x00 + dw ARM_instruction_vzip.16-instruction_handler + db 'vzip~~.32',0x00 + dw ARM_instruction_vzip.32-instruction_handler + db 'wabsdiffb',0xe0 + dw ARM_instruction_wabsdiffb-instruction_handler + db 'wabsdiffh',0xe0 + dw ARM_instruction_wabsdiffh-instruction_handler + db 'wabsdiffw',0xe0 + dw ARM_instruction_wabsdiffw-instruction_handler + db 'waddbss~~',0x00 + dw ARM_instruction_waddbss-instruction_handler + db 'waddbus~~',0x00 + dw ARM_instruction_waddbus-instruction_handler + db 'waddhss~~',0x00 + dw ARM_instruction_waddhss-instruction_handler + db 'waddhus~~',0x00 + dw ARM_instruction_waddhus-instruction_handler + db 'waddsubhx',0xe0 + dw ARM_instruction_waddsubhx-instruction_handler + db 'waddwss~~',0x00 + dw ARM_instruction_waddwss-instruction_handler + db 'waddwus~~',0x00 + dw ARM_instruction_waddwus-instruction_handler + db 'waligni~~',0x00 + dw ARM_instruction_waligni-instruction_handler + db 'wavg2br~~',0x00 + dw ARM_instruction_wavg2br-instruction_handler + db 'wavg2hr~~',0x00 + dw ARM_instruction_wavg2hr-instruction_handler + db 'wcmpeqb~~',0x00 + dw ARM_instruction_wcmpeqb-instruction_handler + db 'wcmpeqh~~',0x00 + dw ARM_instruction_wcmpeqh-instruction_handler + db 'wcmpeqw~~',0x00 + dw ARM_instruction_wcmpeqw-instruction_handler + db 'wmaddsn~~',0x00 + dw ARM_instruction_wmaddsn-instruction_handler + db 'wmaddsx~~',0x00 + dw ARM_instruction_wmaddsx-instruction_handler + db 'wmaddun~~',0x00 + dw ARM_instruction_wmaddun-instruction_handler + db 'wmaddux~~',0x00 + dw ARM_instruction_wmaddux-instruction_handler + db 'wmiabbn~~',0x00 + dw ARM_instruction_wmiabbn-instruction_handler + db 'wmiabtn~~',0x00 + dw ARM_instruction_wmiabtn-instruction_handler + db 'wmiatbn~~',0x00 + dw ARM_instruction_wmiatbn-instruction_handler + db 'wmiattn~~',0x00 + dw ARM_instruction_wmiattn-instruction_handler + db 'wmiawbb~~',0x00 + dw ARM_instruction_wmiawbb-instruction_handler + db 'wmiawbt~~',0x00 + dw ARM_instruction_wmiawbt-instruction_handler + db 'wmiawtb~~',0x00 + dw ARM_instruction_wmiawtb-instruction_handler + db 'wmiawtt~~',0x00 + dw ARM_instruction_wmiawtt-instruction_handler + db 'wmulsmr~~',0x00 + dw ARM_instruction_wmulsmr-instruction_handler + db 'wmulumr~~',0x00 + dw ARM_instruction_wmulumr-instruction_handler + db 'wmulwsm~~',0x00 + dw ARM_instruction_wmulwsm-instruction_handler + db 'wmulwum~~',0x00 + dw ARM_instruction_wmulwum-instruction_handler + db 'wqmiabb~~',0x00 + dw ARM_instruction_wqmiabb-instruction_handler + db 'wqmiabt~~',0x00 + dw ARM_instruction_wqmiabt-instruction_handler + db 'wqmiatb~~',0x00 + dw ARM_instruction_wqmiatb-instruction_handler + db 'wqmiatt~~',0x00 + dw ARM_instruction_wqmiatt-instruction_handler + db 'wqmulmr~~',0x00 + dw ARM_instruction_wqmulmr-instruction_handler + db 'wqmulwm~~',0x00 + dw ARM_instruction_wqmulwm-instruction_handler + db 'wsubaddhx',0xe0 + dw ARM_instruction_wsubaddhx-instruction_handler + db 'wsubbss~~',0x00 + dw ARM_instruction_wsubbss-instruction_handler + db 'wsubbus~~',0x00 + dw ARM_instruction_wsubbus-instruction_handler + db 'wsubhss~~',0x00 + dw ARM_instruction_wsubhss-instruction_handler + db 'wsubhus~~',0x00 + dw ARM_instruction_wsubhus-instruction_handler + db 'wsubwss~~',0x00 + dw ARM_instruction_wsubwss-instruction_handler + db 'wsubwus~~',0x00 + dw ARM_instruction_wsubwus-instruction_handler + db 'wunpckihb',0xe0 + dw ARM_instruction_wunpckihb-instruction_handler + db 'wunpckihh',0xe0 + dw ARM_instruction_wunpckihh-instruction_handler + db 'wunpckihw',0xe0 + dw ARM_instruction_wunpckihw-instruction_handler + db 'wunpckilb',0xe0 + dw ARM_instruction_wunpckilb-instruction_handler + db 'wunpckilh',0xe0 + dw ARM_instruction_wunpckilh-instruction_handler + db 'wunpckilw',0xe0 + dw ARM_instruction_wunpckilw-instruction_handler + db 'yield~~.n',0x04 + dw ARM_instruction_yield-instruction_handler + db 'yield~~.w',0x02 + dw ARM_instruction_yield-instruction_handler + db 0 +instructions_10: + db 'cfcvt32d~~',0x00 + dw ARM_instruction_cfcvt32d-instruction_handler + db 'cfcvt32s~~',0x00 + dw ARM_instruction_cfcvt32s-instruction_handler + db 'cfcvt64d~~',0x00 + dw ARM_instruction_cfcvt64d-instruction_handler + db 'cfcvt64s~~',0x00 + dw ARM_instruction_cfcvt64s-instruction_handler + db 'cfcvtd32~~',0x00 + dw ARM_instruction_cfcvtd32-instruction_handler + db 'cfcvts32~~',0x00 + dw ARM_instruction_cfcvts32-instruction_handler + db 'cfmadd32~~',0x00 + dw ARM_instruction_cfmadd32-instruction_handler + db 'cfmsub32~~',0x00 + dw ARM_instruction_cfmsub32-instruction_handler + db 'cfmv32ah~~',0x00 + dw ARM_instruction_cfmv32ah-instruction_handler + db 'cfmv32al~~',0x00 + dw ARM_instruction_cfmv32al-instruction_handler + db 'cfmv32am~~',0x00 + dw ARM_instruction_cfmv32am-instruction_handler + db 'cfmv32sc~~',0x00 + dw ARM_instruction_cfmv32sc-instruction_handler + db 'cfmv64hr~~',0x00 + dw ARM_instruction_cfmv64hr-instruction_handler + db 'cfmv64lr~~',0x00 + dw ARM_instruction_cfmv64lr-instruction_handler + db 'cfmvah32~~',0x00 + dw ARM_instruction_cfmvah32-instruction_handler + db 'cfmval32~~',0x00 + dw ARM_instruction_cfmval32-instruction_handler + db 'cfmvam32~~',0x00 + dw ARM_instruction_cfmvam32-instruction_handler + db 'cfmvr64h~~',0x00 + dw ARM_instruction_cfmvr64h-instruction_handler + db 'cfmvr64l~~',0x00 + dw ARM_instruction_cfmvr64l-instruction_handler + db 'cfmvsc32~~',0x00 + dw ARM_instruction_cfmvsc32-instruction_handler + db 'cfrshl32~~',0x00 + dw ARM_instruction_cfrshl32-instruction_handler + db 'cfrshl64~~',0x00 + dw ARM_instruction_cfrshl64-instruction_handler + db 'cftruncd32',0xe0 + dw ARM_instruction_cftruncd32-instruction_handler + db 'cftruncs32',0xe0 + dw ARM_instruction_cftruncs32-instruction_handler + db 'qaddsubx~~',0x00 + dw ARM_instruction_qaddsubx-instruction_handler + db 'qsubaddx~~',0x00 + dw ARM_instruction_qsubaddx-instruction_handler + db 'saddsubx~~',0x00 + dw ARM_instruction_saddsubx-instruction_handler + db 'sha1su0.32',0xf0 + dw ARM_instruction_sha1su0.32-instruction_handler + db 'sha1su1.32',0xf0 + dw ARM_instruction_sha1su1.32-instruction_handler + db 'sha256h.32',0xf0 + dw ARM_instruction_sha256h.32-instruction_handler + db 'ssubaddx~~',0x00 + dw ARM_instruction_ssubaddx-instruction_handler + db 'textrmsb~~',0x00 + dw ARM_instruction_textrmsb-instruction_handler + db 'textrmsh~~',0x00 + dw ARM_instruction_textrmsh-instruction_handler + db 'textrmsw~~',0x00 + dw ARM_instruction_textrmsw-instruction_handler + db 'textrmub~~',0x00 + dw ARM_instruction_textrmub-instruction_handler + db 'textrmuh~~',0x00 + dw ARM_instruction_textrmuh-instruction_handler + db 'textrmuw~~',0x00 + dw ARM_instruction_textrmuw-instruction_handler + db 'tmovmskb~~',0x00 + dw ARM_instruction_tmovmskb-instruction_handler + db 'tmovmskh~~',0x00 + dw ARM_instruction_tmovmskh-instruction_handler + db 'tmovmskw~~',0x00 + dw ARM_instruction_tmovmskw-instruction_handler + db 'uaddsubx~~',0x00 + dw ARM_instruction_uaddsubx-instruction_handler + db 'usubaddx~~',0x00 + dw ARM_instruction_usubaddx-instruction_handler + db 'vabal~~.s8',0x00 + dw ARM_instruction_vabal.s8-instruction_handler + db 'vabal~~.u8',0x00 + dw ARM_instruction_vabal.u8-instruction_handler + db 'vaba~~.s16',0x00 + dw ARM_instruction_vaba.s16-instruction_handler + db 'vaba~~.s32',0x00 + dw ARM_instruction_vaba.s32-instruction_handler + db 'vaba~~.u16',0x00 + dw ARM_instruction_vaba.u16-instruction_handler + db 'vaba~~.u32',0x00 + dw ARM_instruction_vaba.u32-instruction_handler + db 'vabdl~~.s8',0x00 + dw ARM_instruction_vabdl.s8-instruction_handler + db 'vabdl~~.u8',0x00 + dw ARM_instruction_vabdl.u8-instruction_handler + db 'vabd~~.f32',0x00 + dw ARM_instruction_vabd.f32-instruction_handler + db 'vabd~~.s16',0x00 + dw ARM_instruction_vabd.s16-instruction_handler + db 'vabd~~.s32',0x00 + dw ARM_instruction_vabd.s32-instruction_handler + db 'vabd~~.u16',0x00 + dw ARM_instruction_vabd.u16-instruction_handler + db 'vabd~~.u32',0x00 + dw ARM_instruction_vabd.u32-instruction_handler + db 'vabs~~.f32',0x00 + dw ARM_instruction_vabs.f32-instruction_handler + db 'vabs~~.f64',0x00 + dw ARM_instruction_vabs.f64-instruction_handler + db 'vabs~~.s16',0x00 + dw ARM_instruction_vabs.s16-instruction_handler + db 'vabs~~.s32',0x00 + dw ARM_instruction_vabs.s32-instruction_handler + db 'vaddhn.i16',0xe0 + dw ARM_instruction_vaddhn.i16-instruction_handler + db 'vaddhn.i32',0xe0 + dw ARM_instruction_vaddhn.i32-instruction_handler + db 'vaddhn.i64',0xe0 + dw ARM_instruction_vaddhn.i64-instruction_handler + db 'vaddl~~.s8',0x00 + dw ARM_instruction_vaddl.s8-instruction_handler + db 'vaddl~~.u8',0x00 + dw ARM_instruction_vaddl.u8-instruction_handler + db 'vaddw~~.s8',0x00 + dw ARM_instruction_vaddw.s8-instruction_handler + db 'vaddw~~.u8',0x00 + dw ARM_instruction_vaddw.u8-instruction_handler + db 'vadd~~.f32',0x00 + dw ARM_instruction_vadd.f32-instruction_handler + db 'vadd~~.f64',0x00 + dw ARM_instruction_vadd.f64-instruction_handler + db 'vadd~~.i16',0x00 + dw ARM_instruction_vadd.i16-instruction_handler + db 'vadd~~.i32',0x00 + dw ARM_instruction_vadd.i32-instruction_handler + db 'vadd~~.i64',0x00 + dw ARM_instruction_vadd.i64-instruction_handler + db 'vand~~.i16',0x00 + dw ARM_instruction_vand.i16-instruction_handler + db 'vand~~.i32',0x00 + dw ARM_instruction_vand.i32-instruction_handler + db 'vbic~~.i16',0x00 + dw ARM_instruction_vbic.i16-instruction_handler + db 'vbic~~.i32',0x00 + dw ARM_instruction_vbic.i32-instruction_handler + db 'vceq~~.f32',0x00 + dw ARM_instruction_vceq.f32-instruction_handler + db 'vceq~~.i16',0x00 + dw ARM_instruction_vceq.i16-instruction_handler + db 'vceq~~.i32',0x00 + dw ARM_instruction_vceq.i32-instruction_handler + db 'vcge~~.f32',0x00 + dw ARM_instruction_vcge.f32-instruction_handler + db 'vcge~~.s16',0x00 + dw ARM_instruction_vcge.s16-instruction_handler + db 'vcge~~.s32',0x00 + dw ARM_instruction_vcge.s32-instruction_handler + db 'vcge~~.u16',0x00 + dw ARM_instruction_vcge.u16-instruction_handler + db 'vcge~~.u32',0x00 + dw ARM_instruction_vcge.u32-instruction_handler + db 'vcgt~~.f32',0x00 + dw ARM_instruction_vcgt.f32-instruction_handler + db 'vcgt~~.s16',0x00 + dw ARM_instruction_vcgt.s16-instruction_handler + db 'vcgt~~.s32',0x00 + dw ARM_instruction_vcgt.s32-instruction_handler + db 'vcgt~~.u16',0x00 + dw ARM_instruction_vcgt.u16-instruction_handler + db 'vcgt~~.u32',0x00 + dw ARM_instruction_vcgt.u32-instruction_handler + db 'vcle~~.f32',0x00 + dw ARM_instruction_vcle.f32-instruction_handler + db 'vcle~~.s16',0x00 + dw ARM_instruction_vcle.s16-instruction_handler + db 'vcle~~.s32',0x00 + dw ARM_instruction_vcle.s32-instruction_handler + db 'vcle~~.u16',0x00 + dw ARM_instruction_vcle.u16-instruction_handler + db 'vcle~~.u32',0x00 + dw ARM_instruction_vcle.u32-instruction_handler + db 'vcls~~.s16',0x00 + dw ARM_instruction_vcls.s16-instruction_handler + db 'vcls~~.s32',0x00 + dw ARM_instruction_vcls.s32-instruction_handler + db 'vclt~~.f32',0x00 + dw ARM_instruction_vclt.f32-instruction_handler + db 'vclt~~.s16',0x00 + dw ARM_instruction_vclt.s16-instruction_handler + db 'vclt~~.s32',0x00 + dw ARM_instruction_vclt.s32-instruction_handler + db 'vclt~~.u16',0x00 + dw ARM_instruction_vclt.u16-instruction_handler + db 'vclt~~.u32',0x00 + dw ARM_instruction_vclt.u32-instruction_handler + db 'vclz~~.i16',0x00 + dw ARM_instruction_vclz.i16-instruction_handler + db 'vclz~~.i32',0x00 + dw ARM_instruction_vclz.i32-instruction_handler + db 'vcmp~~.f32',0x00 + dw ARM_instruction_vcmp.f32-instruction_handler + db 'vcmp~~.f64',0x00 + dw ARM_instruction_vcmp.f64-instruction_handler + db 'vdiv~~.f32',0x00 + dw ARM_instruction_vdiv.f32-instruction_handler + db 'vdiv~~.f64',0x00 + dw ARM_instruction_vdiv.f64-instruction_handler + db 'vfma~~.f32',0x00 + dw ARM_instruction_vfma.f32-instruction_handler + db 'vfma~~.f64',0x00 + dw ARM_instruction_vfma.f64-instruction_handler + db 'vfms~~.f32',0x00 + dw ARM_instruction_vfms.f32-instruction_handler + db 'vfms~~.f64',0x00 + dw ARM_instruction_vfms.f64-instruction_handler + db 'vhadd~~.s8',0x00 + dw ARM_instruction_vhadd.s8-instruction_handler + db 'vhadd~~.u8',0x00 + dw ARM_instruction_vhadd.u8-instruction_handler + db 'vhsub~~.s8',0x00 + dw ARM_instruction_vhsub.s8-instruction_handler + db 'vhsub~~.u8',0x00 + dw ARM_instruction_vhsub.u8-instruction_handler + db 'vmaxnm.f32',0xf0 + dw ARM_instruction_vmaxnm.f32-instruction_handler + db 'vmaxnm.f64',0xf0 + dw ARM_instruction_vmaxnm.f64-instruction_handler + db 'vmax~~.f32',0x00 + dw ARM_instruction_vmax.f32-instruction_handler + db 'vmax~~.s16',0x00 + dw ARM_instruction_vmax.s16-instruction_handler + db 'vmax~~.s32',0x00 + dw ARM_instruction_vmax.s32-instruction_handler + db 'vmax~~.u16',0x00 + dw ARM_instruction_vmax.u16-instruction_handler + db 'vmax~~.u32',0x00 + dw ARM_instruction_vmax.u32-instruction_handler + db 'vminnm.f32',0xf0 + dw ARM_instruction_vminnm.f32-instruction_handler + db 'vminnm.f64',0xf0 + dw ARM_instruction_vminnm.f64-instruction_handler + db 'vmin~~.f32',0x00 + dw ARM_instruction_vmin.f32-instruction_handler + db 'vmin~~.s16',0x00 + dw ARM_instruction_vmin.s16-instruction_handler + db 'vmin~~.s32',0x00 + dw ARM_instruction_vmin.s32-instruction_handler + db 'vmin~~.u16',0x00 + dw ARM_instruction_vmin.u16-instruction_handler + db 'vmin~~.u32',0x00 + dw ARM_instruction_vmin.u32-instruction_handler + db 'vmlal~~.s8',0x00 + dw ARM_instruction_vmlal.s8-instruction_handler + db 'vmlal~~.u8',0x00 + dw ARM_instruction_vmlal.u8-instruction_handler + db 'vmla~~.f32',0x00 + dw ARM_instruction_vmla.f32-instruction_handler + db 'vmla~~.f64',0x00 + dw ARM_instruction_vmla.f64-instruction_handler + db 'vmla~~.i16',0x00 + dw ARM_instruction_vmla.i16-instruction_handler + db 'vmla~~.i32',0x00 + dw ARM_instruction_vmla.i32-instruction_handler + db 'vmla~~.s16',0x00 + dw ARM_instruction_vmla.s16-instruction_handler + db 'vmla~~.s32',0x00 + dw ARM_instruction_vmla.s32-instruction_handler + db 'vmla~~.u16',0x00 + dw ARM_instruction_vmla.u16-instruction_handler + db 'vmla~~.u32',0x00 + dw ARM_instruction_vmla.u32-instruction_handler + db 'vmlsl~~.s8',0x00 + dw ARM_instruction_vmlsl.s8-instruction_handler + db 'vmlsl~~.u8',0x00 + dw ARM_instruction_vmlsl.u8-instruction_handler + db 'vmls~~.f32',0x00 + dw ARM_instruction_vmls.f32-instruction_handler + db 'vmls~~.f64',0x00 + dw ARM_instruction_vmls.f64-instruction_handler + db 'vmls~~.i16',0x00 + dw ARM_instruction_vmls.i16-instruction_handler + db 'vmls~~.i32',0x00 + dw ARM_instruction_vmls.i32-instruction_handler + db 'vmls~~.s16',0x00 + dw ARM_instruction_vmls.s16-instruction_handler + db 'vmls~~.s32',0x00 + dw ARM_instruction_vmls.s32-instruction_handler + db 'vmls~~.u16',0x00 + dw ARM_instruction_vmls.u16-instruction_handler + db 'vmls~~.u32',0x00 + dw ARM_instruction_vmls.u32-instruction_handler + db 'vmovl~~.s8',0x00 + dw ARM_instruction_vmovl.s8-instruction_handler + db 'vmovl~~.u8',0x00 + dw ARM_instruction_vmovl.u8-instruction_handler + db 'vmovn~~.i8',0x00 + dw ARM_instruction_vmovn.i8-instruction_handler + db 'vmov~~.f32',0x00 + dw ARM_instruction_vmov.f32-instruction_handler + db 'vmov~~.f64',0x00 + dw ARM_instruction_vmov.f64-instruction_handler + db 'vmov~~.i16',0x00 + dw ARM_instruction_vmov.i16-instruction_handler + db 'vmov~~.i32',0x00 + dw ARM_instruction_vmov.i32-instruction_handler + db 'vmov~~.i64',0x00 + dw ARM_instruction_vmov.i64-instruction_handler + db 'vmov~~.s16',0x00 + dw ARM_instruction_vmov.s16-instruction_handler + db 'vmov~~.u16',0x00 + dw ARM_instruction_vmov.u16-instruction_handler + db 'vmull~~.p8',0x00 + dw ARM_instruction_vmull.p8-instruction_handler + db 'vmull~~.s8',0x00 + dw ARM_instruction_vmull.s8-instruction_handler + db 'vmull~~.u8',0x00 + dw ARM_instruction_vmull.u8-instruction_handler + db 'vmul~~.f32',0x00 + dw ARM_instruction_vmul.f32-instruction_handler + db 'vmul~~.f64',0x00 + dw ARM_instruction_vmul.f64-instruction_handler + db 'vmul~~.i16',0x00 + dw ARM_instruction_vmul.i16-instruction_handler + db 'vmul~~.i32',0x00 + dw ARM_instruction_vmul.i32-instruction_handler + db 'vmul~~.s16',0x00 + dw ARM_instruction_vmul.s16-instruction_handler + db 'vmul~~.s32',0x00 + dw ARM_instruction_vmul.s32-instruction_handler + db 'vmul~~.u16',0x00 + dw ARM_instruction_vmul.u16-instruction_handler + db 'vmul~~.u32',0x00 + dw ARM_instruction_vmul.u32-instruction_handler + db 'vmvn~~.i16',0x00 + dw ARM_instruction_vmvn.i16-instruction_handler + db 'vmvn~~.i32',0x00 + dw ARM_instruction_vmvn.i32-instruction_handler + db 'vneg~~.f32',0x00 + dw ARM_instruction_vneg.f32-instruction_handler + db 'vneg~~.f64',0x00 + dw ARM_instruction_vneg.f64-instruction_handler + db 'vneg~~.s16',0x00 + dw ARM_instruction_vneg.s16-instruction_handler + db 'vneg~~.s32',0x00 + dw ARM_instruction_vneg.s32-instruction_handler + db 'vorn~~.i16',0x00 + dw ARM_instruction_vorn.i16-instruction_handler + db 'vorn~~.i32',0x00 + dw ARM_instruction_vorn.i32-instruction_handler + db 'vorr~~.i16',0x00 + dw ARM_instruction_vorr.i16-instruction_handler + db 'vorr~~.i32',0x00 + dw ARM_instruction_vorr.i32-instruction_handler + db 'vpadal.s16',0xe0 + dw ARM_instruction_vpadal.s16-instruction_handler + db 'vpadal.s32',0xe0 + dw ARM_instruction_vpadal.s32-instruction_handler + db 'vpadal.u16',0xe0 + dw ARM_instruction_vpadal.u16-instruction_handler + db 'vpadal.u32',0xe0 + dw ARM_instruction_vpadal.u32-instruction_handler + db 'vpaddl.s16',0xe0 + dw ARM_instruction_vpaddl.s16-instruction_handler + db 'vpaddl.s32',0xe0 + dw ARM_instruction_vpaddl.s32-instruction_handler + db 'vpaddl.u16',0xe0 + dw ARM_instruction_vpaddl.u16-instruction_handler + db 'vpaddl.u32',0xe0 + dw ARM_instruction_vpaddl.u32-instruction_handler + db 'vpadd~~.i8',0x00 + dw ARM_instruction_vpadd.i8-instruction_handler + db 'vpmax~~.s8',0x00 + dw ARM_instruction_vpmax.s8-instruction_handler + db 'vpmax~~.u8',0x00 + dw ARM_instruction_vpmax.u8-instruction_handler + db 'vpmin~~.s8',0x00 + dw ARM_instruction_vpmin.s8-instruction_handler + db 'vpmin~~.u8',0x00 + dw ARM_instruction_vpmin.u8-instruction_handler + db 'vpush~~.32',0x00 + dw ARM_instruction_vpush.32-instruction_handler + db 'vpush~~.64',0x00 + dw ARM_instruction_vpush.64-instruction_handler + db 'vqabs~~.s8',0x00 + dw ARM_instruction_vqabs.s8-instruction_handler + db 'vqadd~~.s8',0x00 + dw ARM_instruction_vqadd.s8-instruction_handler + db 'vqadd~~.u8',0x00 + dw ARM_instruction_vqadd.u8-instruction_handler + db 'vqmovn.s16',0xe0 + dw ARM_instruction_vqmovn.s16-instruction_handler + db 'vqmovn.s32',0xe0 + dw ARM_instruction_vqmovn.s32-instruction_handler + db 'vqmovn.s64',0xe0 + dw ARM_instruction_vqmovn.s64-instruction_handler + db 'vqmovn.u16',0xe0 + dw ARM_instruction_vqmovn.u16-instruction_handler + db 'vqmovn.u32',0xe0 + dw ARM_instruction_vqmovn.u32-instruction_handler + db 'vqmovn.u64',0xe0 + dw ARM_instruction_vqmovn.u64-instruction_handler + db 'vqneg~~.s8',0x00 + dw ARM_instruction_vqneg.s8-instruction_handler + db 'vqrshl.s16',0xe0 + dw ARM_instruction_vqrshl.s16-instruction_handler + db 'vqrshl.s32',0xe0 + dw ARM_instruction_vqrshl.s32-instruction_handler + db 'vqrshl.s64',0xe0 + dw ARM_instruction_vqrshl.s64-instruction_handler + db 'vqrshl.u16',0xe0 + dw ARM_instruction_vqrshl.u16-instruction_handler + db 'vqrshl.u32',0xe0 + dw ARM_instruction_vqrshl.u32-instruction_handler + db 'vqrshl.u64',0xe0 + dw ARM_instruction_vqrshl.u64-instruction_handler + db 'vqshlu.s16',0xe0 + dw ARM_instruction_vqshlu.s16-instruction_handler + db 'vqshlu.s32',0xe0 + dw ARM_instruction_vqshlu.s32-instruction_handler + db 'vqshlu.s64',0xe0 + dw ARM_instruction_vqshlu.s64-instruction_handler + db 'vqshl~~.s8',0x00 + dw ARM_instruction_vqshl.s8-instruction_handler + db 'vqshl~~.u8',0x00 + dw ARM_instruction_vqshl.u8-instruction_handler + db 'vqshrn.s16',0xe0 + dw ARM_instruction_vqshrn.s16-instruction_handler + db 'vqshrn.s32',0xe0 + dw ARM_instruction_vqshrn.s32-instruction_handler + db 'vqshrn.s64',0xe0 + dw ARM_instruction_vqshrn.s64-instruction_handler + db 'vqshrn.u16',0xe0 + dw ARM_instruction_vqshrn.u16-instruction_handler + db 'vqshrn.u32',0xe0 + dw ARM_instruction_vqshrn.u32-instruction_handler + db 'vqshrn.u64',0xe0 + dw ARM_instruction_vqshrn.u64-instruction_handler + db 'vqsub~~.s8',0x00 + dw ARM_instruction_vqsub.s8-instruction_handler + db 'vqsub~~.u8',0x00 + dw ARM_instruction_vqsub.u8-instruction_handler + db 'vrecpe.f32',0xe0 + dw ARM_instruction_vrecpe.f32-instruction_handler + db 'vrecpe.u32',0xe0 + dw ARM_instruction_vrecpe.u32-instruction_handler + db 'vrecps.f32',0xe0 + dw ARM_instruction_vrecps.f32-instruction_handler + db 'vrev16~~.8',0x00 + dw ARM_instruction_vrev16.8-instruction_handler + db 'vrev32~~.8',0x00 + dw ARM_instruction_vrev32.8-instruction_handler + db 'vrev64~~.8',0x00 + dw ARM_instruction_vrev64.8-instruction_handler + db 'vrhadd.s16',0xe0 + dw ARM_instruction_vrhadd.s16-instruction_handler + db 'vrhadd.s32',0xe0 + dw ARM_instruction_vrhadd.s32-instruction_handler + db 'vrhadd.u16',0xe0 + dw ARM_instruction_vrhadd.u16-instruction_handler + db 'vrhadd.u32',0xe0 + dw ARM_instruction_vrhadd.u32-instruction_handler + db 'vrshl~~.s8',0x00 + dw ARM_instruction_vrshl.s8-instruction_handler + db 'vrshl~~.u8',0x00 + dw ARM_instruction_vrshl.u8-instruction_handler + db 'vrshrn.i16',0xe0 + dw ARM_instruction_vrshrn.i16-instruction_handler + db 'vrshrn.i32',0xe0 + dw ARM_instruction_vrshrn.i32-instruction_handler + db 'vrshrn.i64',0xe0 + dw ARM_instruction_vrshrn.i64-instruction_handler + db 'vrshr~~.s8',0x00 + dw ARM_instruction_vrshr.s8-instruction_handler + db 'vrshr~~.u8',0x00 + dw ARM_instruction_vrshr.u8-instruction_handler + db 'vrsra~~.s8',0x00 + dw ARM_instruction_vrsra.s8-instruction_handler + db 'vrsra~~.u8',0x00 + dw ARM_instruction_vrsra.u8-instruction_handler + db 'vseleq.f32',0xf0 + dw ARM_instruction_vseleq.f32-instruction_handler + db 'vseleq.f64',0xf0 + dw ARM_instruction_vseleq.f64-instruction_handler + db 'vselge.f32',0xf0 + dw ARM_instruction_vselge.f32-instruction_handler + db 'vselge.f64',0xf0 + dw ARM_instruction_vselge.f64-instruction_handler + db 'vselgt.f32',0xf0 + dw ARM_instruction_vselgt.f32-instruction_handler + db 'vselgt.f64',0xf0 + dw ARM_instruction_vselgt.f64-instruction_handler + db 'vselvs.f32',0xf0 + dw ARM_instruction_vselvs.f32-instruction_handler + db 'vselvs.f64',0xf0 + dw ARM_instruction_vselvs.f64-instruction_handler + db 'vshll~~.i8',0x00 + dw ARM_instruction_vshll.i8-instruction_handler + db 'vshll~~.s8',0x00 + dw ARM_instruction_vshll.s8-instruction_handler + db 'vshll~~.u8',0x00 + dw ARM_instruction_vshll.u8-instruction_handler + db 'vshl~~.i16',0x00 + dw ARM_instruction_vshl.i16-instruction_handler + db 'vshl~~.i32',0x00 + dw ARM_instruction_vshl.i32-instruction_handler + db 'vshl~~.i64',0x00 + dw ARM_instruction_vshl.i64-instruction_handler + db 'vshl~~.s16',0x00 + dw ARM_instruction_vshl.s16-instruction_handler + db 'vshl~~.s32',0x00 + dw ARM_instruction_vshl.s32-instruction_handler + db 'vshl~~.s64',0x00 + dw ARM_instruction_vshl.s64-instruction_handler + db 'vshl~~.u16',0x00 + dw ARM_instruction_vshl.u16-instruction_handler + db 'vshl~~.u32',0x00 + dw ARM_instruction_vshl.u32-instruction_handler + db 'vshl~~.u64',0x00 + dw ARM_instruction_vshl.u64-instruction_handler + db 'vshr~~.s16',0x00 + dw ARM_instruction_vshr.s16-instruction_handler + db 'vshr~~.s32',0x00 + dw ARM_instruction_vshr.s32-instruction_handler + db 'vshr~~.s64',0x00 + dw ARM_instruction_vshr.s64-instruction_handler + db 'vshr~~.u16',0x00 + dw ARM_instruction_vshr.u16-instruction_handler + db 'vshr~~.u32',0x00 + dw ARM_instruction_vshr.u32-instruction_handler + db 'vshr~~.u64',0x00 + dw ARM_instruction_vshr.u64-instruction_handler + db 'vsra~~.s16',0x00 + dw ARM_instruction_vsra.s16-instruction_handler + db 'vsra~~.s32',0x00 + dw ARM_instruction_vsra.s32-instruction_handler + db 'vsra~~.s64',0x00 + dw ARM_instruction_vsra.s64-instruction_handler + db 'vsra~~.u16',0x00 + dw ARM_instruction_vsra.u16-instruction_handler + db 'vsra~~.u32',0x00 + dw ARM_instruction_vsra.u32-instruction_handler + db 'vsra~~.u64',0x00 + dw ARM_instruction_vsra.u64-instruction_handler + db 'vsubhn.i16',0xe0 + dw ARM_instruction_vsubhn.i16-instruction_handler + db 'vsubhn.i32',0xe0 + dw ARM_instruction_vsubhn.i32-instruction_handler + db 'vsubhn.i64',0xe0 + dw ARM_instruction_vsubhn.i64-instruction_handler + db 'vsubl~~.s8',0x00 + dw ARM_instruction_vsubl.s8-instruction_handler + db 'vsubl~~.u8',0x00 + dw ARM_instruction_vsubl.u8-instruction_handler + db 'vsubw~~.s8',0x00 + dw ARM_instruction_vsubw.s8-instruction_handler + db 'vsubw~~.u8',0x00 + dw ARM_instruction_vsubw.u8-instruction_handler + db 'vsub~~.f32',0x00 + dw ARM_instruction_vsub.f32-instruction_handler + db 'vsub~~.f64',0x00 + dw ARM_instruction_vsub.f64-instruction_handler + db 'vsub~~.i16',0x00 + dw ARM_instruction_vsub.i16-instruction_handler + db 'vsub~~.i32',0x00 + dw ARM_instruction_vsub.i32-instruction_handler + db 'vsub~~.i64',0x00 + dw ARM_instruction_vsub.i64-instruction_handler + db 'walignr0~~',0x00 + dw ARM_instruction_walignr0-instruction_handler + db 'walignr1~~',0x00 + dw ARM_instruction_walignr1-instruction_handler + db 'walignr2~~',0x00 + dw ARM_instruction_walignr2-instruction_handler + db 'walignr3~~',0x00 + dw ARM_instruction_walignr3-instruction_handler + db 'wcmpgtsb~~',0x00 + dw ARM_instruction_wcmpgtsb-instruction_handler + db 'wcmpgtsh~~',0x00 + dw ARM_instruction_wcmpgtsh-instruction_handler + db 'wcmpgtsw~~',0x00 + dw ARM_instruction_wcmpgtsw-instruction_handler + db 'wcmpgtub~~',0x00 + dw ARM_instruction_wcmpgtub-instruction_handler + db 'wcmpgtuh~~',0x00 + dw ARM_instruction_wcmpgtuh-instruction_handler + db 'wcmpgtuw~~',0x00 + dw ARM_instruction_wcmpgtuw-instruction_handler + db 'wmiawbbn~~',0x00 + dw ARM_instruction_wmiawbbn-instruction_handler + db 'wmiawbtn~~',0x00 + dw ARM_instruction_wmiawbtn-instruction_handler + db 'wmiawtbn~~',0x00 + dw ARM_instruction_wmiawtbn-instruction_handler + db 'wmiawttn~~',0x00 + dw ARM_instruction_wmiawttn-instruction_handler + db 'wmulwsmr~~',0x00 + dw ARM_instruction_wmulwsmr-instruction_handler + db 'wmulwumr~~',0x00 + dw ARM_instruction_wmulwumr-instruction_handler + db 'wpackdss~~',0x00 + dw ARM_instruction_wpackdss-instruction_handler + db 'wpackdus~~',0x00 + dw ARM_instruction_wpackdus-instruction_handler + db 'wpackhss~~',0x00 + dw ARM_instruction_wpackhss-instruction_handler + db 'wpackhus~~',0x00 + dw ARM_instruction_wpackhus-instruction_handler + db 'wpackwss~~',0x00 + dw ARM_instruction_wpackwss-instruction_handler + db 'wpackwus~~',0x00 + dw ARM_instruction_wpackwus-instruction_handler + db 'wqmiabbn~~',0x00 + dw ARM_instruction_wqmiabbn-instruction_handler + db 'wqmiabtn~~',0x00 + dw ARM_instruction_wqmiabtn-instruction_handler + db 'wqmiatbn~~',0x00 + dw ARM_instruction_wqmiatbn-instruction_handler + db 'wqmiattn~~',0x00 + dw ARM_instruction_wqmiattn-instruction_handler + db 'wqmulwmr~~',0x00 + dw ARM_instruction_wqmulwmr-instruction_handler + db 'wunpckehsb',0xe0 + dw ARM_instruction_wunpckehsb-instruction_handler + db 'wunpckehsh',0xe0 + dw ARM_instruction_wunpckehsh-instruction_handler + db 'wunpckehsw',0xe0 + dw ARM_instruction_wunpckehsw-instruction_handler + db 'wunpckehub',0xe0 + dw ARM_instruction_wunpckehub-instruction_handler + db 'wunpckehuh',0xe0 + dw ARM_instruction_wunpckehuh-instruction_handler + db 'wunpckehuw',0xe0 + dw ARM_instruction_wunpckehuw-instruction_handler + db 'wunpckelsb',0xe0 + dw ARM_instruction_wunpckelsb-instruction_handler + db 'wunpckelsh',0xe0 + dw ARM_instruction_wunpckelsh-instruction_handler + db 'wunpckelsw',0xe0 + dw ARM_instruction_wunpckelsw-instruction_handler + db 'wunpckelub',0xe0 + dw ARM_instruction_wunpckelub-instruction_handler + db 'wunpckeluh',0xe0 + dw ARM_instruction_wunpckeluh-instruction_handler + db 'wunpckeluw',0xe0 + dw ARM_instruction_wunpckeluw-instruction_handler + db 0 +instructions_11: + db 'cfmadda32~~',0x00 + dw ARM_instruction_cfmadda32-instruction_handler + db 'cfmsuba32~~',0x00 + dw ARM_instruction_cfmsuba32-instruction_handler + db 'coprocessor',0x00 + dw ARM_coprocessor_directive-instruction_handler + db 'sha256h2.32',0xf0 + dw ARM_instruction_sha256h2.32-instruction_handler + db 'shaddsubx~~',0x00 + dw ARM_instruction_shaddsubx-instruction_handler + db 'shsubaddx~~',0x00 + dw ARM_instruction_shsubaddx-instruction_handler + db 'uhaddsubx~~',0x00 + dw ARM_instruction_uhaddsubx-instruction_handler + db 'uhsubaddx~~',0x00 + dw ARM_instruction_uhsubaddx-instruction_handler + db 'uqaddsubx~~',0x00 + dw ARM_instruction_uqaddsubx-instruction_handler + db 'uqsubaddx~~',0x00 + dw ARM_instruction_uqsubaddx-instruction_handler + db 'vabal~~.s16',0x00 + dw ARM_instruction_vabal.s16-instruction_handler + db 'vabal~~.s32',0x00 + dw ARM_instruction_vabal.s32-instruction_handler + db 'vabal~~.u16',0x00 + dw ARM_instruction_vabal.u16-instruction_handler + db 'vabal~~.u32',0x00 + dw ARM_instruction_vabal.u32-instruction_handler + db 'vabdl~~.s16',0x00 + dw ARM_instruction_vabdl.s16-instruction_handler + db 'vabdl~~.s32',0x00 + dw ARM_instruction_vabdl.s32-instruction_handler + db 'vabdl~~.u16',0x00 + dw ARM_instruction_vabdl.u16-instruction_handler + db 'vabdl~~.u32',0x00 + dw ARM_instruction_vabdl.u32-instruction_handler + db 'vacge~~.f32',0x00 + dw ARM_instruction_vacge.f32-instruction_handler + db 'vacgt~~.f32',0x00 + dw ARM_instruction_vacgt.f32-instruction_handler + db 'vacle~~.f32',0x00 + dw ARM_instruction_vacle.f32-instruction_handler + db 'vaclt~~.f32',0x00 + dw ARM_instruction_vaclt.f32-instruction_handler + db 'vaddl~~.s16',0x00 + dw ARM_instruction_vaddl.s16-instruction_handler + db 'vaddl~~.s32',0x00 + dw ARM_instruction_vaddl.s32-instruction_handler + db 'vaddl~~.u16',0x00 + dw ARM_instruction_vaddl.u16-instruction_handler + db 'vaddl~~.u32',0x00 + dw ARM_instruction_vaddl.u32-instruction_handler + db 'vaddw~~.s16',0x00 + dw ARM_instruction_vaddw.s16-instruction_handler + db 'vaddw~~.s32',0x00 + dw ARM_instruction_vaddw.s32-instruction_handler + db 'vaddw~~.u16',0x00 + dw ARM_instruction_vaddw.u16-instruction_handler + db 'vaddw~~.u32',0x00 + dw ARM_instruction_vaddw.u32-instruction_handler + db 'vcmpe~~.f32',0x00 + dw ARM_instruction_vcmpe.f32-instruction_handler + db 'vcmpe~~.f64',0x00 + dw ARM_instruction_vcmpe.f64-instruction_handler + db 'vfnma~~.f32',0x00 + dw ARM_instruction_vfnma.f32-instruction_handler + db 'vfnma~~.f64',0x00 + dw ARM_instruction_vfnma.f64-instruction_handler + db 'vfnms~~.f32',0x00 + dw ARM_instruction_vfnms.f32-instruction_handler + db 'vfnms~~.f64',0x00 + dw ARM_instruction_vfnms.f64-instruction_handler + db 'vhadd~~.s16',0x00 + dw ARM_instruction_vhadd.s16-instruction_handler + db 'vhadd~~.s32',0x00 + dw ARM_instruction_vhadd.s32-instruction_handler + db 'vhadd~~.u16',0x00 + dw ARM_instruction_vhadd.u16-instruction_handler + db 'vhadd~~.u32',0x00 + dw ARM_instruction_vhadd.u32-instruction_handler + db 'vhsub~~.s16',0x00 + dw ARM_instruction_vhsub.s16-instruction_handler + db 'vhsub~~.s32',0x00 + dw ARM_instruction_vhsub.s32-instruction_handler + db 'vhsub~~.u16',0x00 + dw ARM_instruction_vhsub.u16-instruction_handler + db 'vhsub~~.u32',0x00 + dw ARM_instruction_vhsub.u32-instruction_handler + db 'vldmdb~~.32',0x00 + dw ARM_instruction_vldmdb.32-instruction_handler + db 'vldmdb~~.64',0x00 + dw ARM_instruction_vldmdb.64-instruction_handler + db 'vldmea~~.32',0x00 + dw ARM_instruction_vldmea.32-instruction_handler + db 'vldmea~~.64',0x00 + dw ARM_instruction_vldmea.64-instruction_handler + db 'vldmfd~~.32',0x00 + dw ARM_instruction_vldmfd.32-instruction_handler + db 'vldmfd~~.64',0x00 + dw ARM_instruction_vldmfd.64-instruction_handler + db 'vldmia~~.32',0x00 + dw ARM_instruction_vldmia.32-instruction_handler + db 'vldmia~~.64',0x00 + dw ARM_instruction_vldmia.64-instruction_handler + db 'vmlal~~.s16',0x00 + dw ARM_instruction_vmlal.s16-instruction_handler + db 'vmlal~~.s32',0x00 + dw ARM_instruction_vmlal.s32-instruction_handler + db 'vmlal~~.u16',0x00 + dw ARM_instruction_vmlal.u16-instruction_handler + db 'vmlal~~.u32',0x00 + dw ARM_instruction_vmlal.u32-instruction_handler + db 'vmlsl~~.s16',0x00 + dw ARM_instruction_vmlsl.s16-instruction_handler + db 'vmlsl~~.s32',0x00 + dw ARM_instruction_vmlsl.s32-instruction_handler + db 'vmlsl~~.u16',0x00 + dw ARM_instruction_vmlsl.u16-instruction_handler + db 'vmlsl~~.u32',0x00 + dw ARM_instruction_vmlsl.u32-instruction_handler + db 'vmovl~~.s16',0x00 + dw ARM_instruction_vmovl.s16-instruction_handler + db 'vmovl~~.s32',0x00 + dw ARM_instruction_vmovl.s32-instruction_handler + db 'vmovl~~.u16',0x00 + dw ARM_instruction_vmovl.u16-instruction_handler + db 'vmovl~~.u32',0x00 + dw ARM_instruction_vmovl.u32-instruction_handler + db 'vmovn~~.i16',0x00 + dw ARM_instruction_vmovn.i16-instruction_handler + db 'vmovn~~.i32',0x00 + dw ARM_instruction_vmovn.i32-instruction_handler + db 'vmull~~.s16',0x00 + dw ARM_instruction_vmull.s16-instruction_handler + db 'vmull~~.s32',0x00 + dw ARM_instruction_vmull.s32-instruction_handler + db 'vmull~~.u16',0x00 + dw ARM_instruction_vmull.u16-instruction_handler + db 'vmull~~.u32',0x00 + dw ARM_instruction_vmull.u32-instruction_handler + db 'vnmla~~.f32',0x00 + dw ARM_instruction_vnmla.f32-instruction_handler + db 'vnmla~~.f64',0x00 + dw ARM_instruction_vnmla.f64-instruction_handler + db 'vnmls~~.f32',0x00 + dw ARM_instruction_vnmls.f32-instruction_handler + db 'vnmls~~.f64',0x00 + dw ARM_instruction_vnmls.f64-instruction_handler + db 'vnmul~~.f32',0x00 + dw ARM_instruction_vnmul.f32-instruction_handler + db 'vnmul~~.f64',0x00 + dw ARM_instruction_vnmul.f64-instruction_handler + db 'vpadal~~.s8',0x00 + dw ARM_instruction_vpadal.s8-instruction_handler + db 'vpadal~~.u8',0x00 + dw ARM_instruction_vpadal.u8-instruction_handler + db 'vpaddl~~.s8',0x00 + dw ARM_instruction_vpaddl.s8-instruction_handler + db 'vpaddl~~.u8',0x00 + dw ARM_instruction_vpaddl.u8-instruction_handler + db 'vpadd~~.f32',0x00 + dw ARM_instruction_vpadd.f32-instruction_handler + db 'vpadd~~.i16',0x00 + dw ARM_instruction_vpadd.i16-instruction_handler + db 'vpadd~~.i32',0x00 + dw ARM_instruction_vpadd.i32-instruction_handler + db 'vpmax~~.f32',0x00 + dw ARM_instruction_vpmax.f32-instruction_handler + db 'vpmax~~.s16',0x00 + dw ARM_instruction_vpmax.s16-instruction_handler + db 'vpmax~~.s32',0x00 + dw ARM_instruction_vpmax.s32-instruction_handler + db 'vpmax~~.u16',0x00 + dw ARM_instruction_vpmax.u16-instruction_handler + db 'vpmax~~.u32',0x00 + dw ARM_instruction_vpmax.u32-instruction_handler + db 'vpmin~~.f32',0x00 + dw ARM_instruction_vpmin.f32-instruction_handler + db 'vpmin~~.s16',0x00 + dw ARM_instruction_vpmin.s16-instruction_handler + db 'vpmin~~.s32',0x00 + dw ARM_instruction_vpmin.s32-instruction_handler + db 'vpmin~~.u16',0x00 + dw ARM_instruction_vpmin.u16-instruction_handler + db 'vpmin~~.u32',0x00 + dw ARM_instruction_vpmin.u32-instruction_handler + db 'vqabs~~.s16',0x00 + dw ARM_instruction_vqabs.s16-instruction_handler + db 'vqabs~~.s32',0x00 + dw ARM_instruction_vqabs.s32-instruction_handler + db 'vqadd~~.s16',0x00 + dw ARM_instruction_vqadd.s16-instruction_handler + db 'vqadd~~.s32',0x00 + dw ARM_instruction_vqadd.s32-instruction_handler + db 'vqadd~~.s64',0x00 + dw ARM_instruction_vqadd.s64-instruction_handler + db 'vqadd~~.u16',0x00 + dw ARM_instruction_vqadd.u16-instruction_handler + db 'vqadd~~.u32',0x00 + dw ARM_instruction_vqadd.u32-instruction_handler + db 'vqadd~~.u64',0x00 + dw ARM_instruction_vqadd.u64-instruction_handler + db 'vqdmlal.s16',0xe0 + dw ARM_instruction_vqdmlal.s16-instruction_handler + db 'vqdmlal.s32',0xe0 + dw ARM_instruction_vqdmlal.s32-instruction_handler + db 'vqdmlsl.s16',0xe0 + dw ARM_instruction_vqdmlsl.s16-instruction_handler + db 'vqdmlsl.s32',0xe0 + dw ARM_instruction_vqdmlsl.s32-instruction_handler + db 'vqdmulh.s16',0xe0 + dw ARM_instruction_vqdmulh.s16-instruction_handler + db 'vqdmulh.s32',0xe0 + dw ARM_instruction_vqdmulh.s32-instruction_handler + db 'vqdmull.s16',0xe0 + dw ARM_instruction_vqdmull.s16-instruction_handler + db 'vqdmull.s32',0xe0 + dw ARM_instruction_vqdmull.s32-instruction_handler + db 'vqmovun.s16',0xe0 + dw ARM_instruction_vqmovun.s16-instruction_handler + db 'vqmovun.s32',0xe0 + dw ARM_instruction_vqmovun.s32-instruction_handler + db 'vqmovun.s64',0xe0 + dw ARM_instruction_vqmovun.s64-instruction_handler + db 'vqneg~~.s16',0x00 + dw ARM_instruction_vqneg.s16-instruction_handler + db 'vqneg~~.s32',0x00 + dw ARM_instruction_vqneg.s32-instruction_handler + db 'vqrshl~~.s8',0x00 + dw ARM_instruction_vqrshl.s8-instruction_handler + db 'vqrshl~~.u8',0x00 + dw ARM_instruction_vqrshl.u8-instruction_handler + db 'vqrshrn.s16',0xe0 + dw ARM_instruction_vqrshrn.s16-instruction_handler + db 'vqrshrn.s32',0xe0 + dw ARM_instruction_vqrshrn.s32-instruction_handler + db 'vqrshrn.s64',0xe0 + dw ARM_instruction_vqrshrn.s64-instruction_handler + db 'vqrshrn.u16',0xe0 + dw ARM_instruction_vqrshrn.u16-instruction_handler + db 'vqrshrn.u32',0xe0 + dw ARM_instruction_vqrshrn.u32-instruction_handler + db 'vqrshrn.u64',0xe0 + dw ARM_instruction_vqrshrn.u64-instruction_handler + db 'vqshlu~~.s8',0x00 + dw ARM_instruction_vqshlu.s8-instruction_handler + db 'vqshl~~.s16',0x00 + dw ARM_instruction_vqshl.s16-instruction_handler + db 'vqshl~~.s32',0x00 + dw ARM_instruction_vqshl.s32-instruction_handler + db 'vqshl~~.s64',0x00 + dw ARM_instruction_vqshl.s64-instruction_handler + db 'vqshl~~.u16',0x00 + dw ARM_instruction_vqshl.u16-instruction_handler + db 'vqshl~~.u32',0x00 + dw ARM_instruction_vqshl.u32-instruction_handler + db 'vqshl~~.u64',0x00 + dw ARM_instruction_vqshl.u64-instruction_handler + db 'vqshrun.s16',0xe0 + dw ARM_instruction_vqshrun.s16-instruction_handler + db 'vqshrun.s32',0xe0 + dw ARM_instruction_vqshrun.s32-instruction_handler + db 'vqshrun.s64',0xe0 + dw ARM_instruction_vqshrun.s64-instruction_handler + db 'vqsub~~.s16',0x00 + dw ARM_instruction_vqsub.s16-instruction_handler + db 'vqsub~~.s32',0x00 + dw ARM_instruction_vqsub.s32-instruction_handler + db 'vqsub~~.s64',0x00 + dw ARM_instruction_vqsub.s64-instruction_handler + db 'vqsub~~.u16',0x00 + dw ARM_instruction_vqsub.u16-instruction_handler + db 'vqsub~~.u32',0x00 + dw ARM_instruction_vqsub.u32-instruction_handler + db 'vqsub~~.u64',0x00 + dw ARM_instruction_vqsub.u64-instruction_handler + db 'vraddhn.i16',0xe0 + dw ARM_instruction_vraddhn.i16-instruction_handler + db 'vraddhn.i32',0xe0 + dw ARM_instruction_vraddhn.i32-instruction_handler + db 'vraddhn.i64',0xe0 + dw ARM_instruction_vraddhn.i64-instruction_handler + db 'vrev32~~.16',0x00 + dw ARM_instruction_vrev32.16-instruction_handler + db 'vrev64~~.16',0x00 + dw ARM_instruction_vrev64.16-instruction_handler + db 'vrev64~~.32',0x00 + dw ARM_instruction_vrev64.32-instruction_handler + db 'vrhadd~~.s8',0x00 + dw ARM_instruction_vrhadd.s8-instruction_handler + db 'vrhadd~~.u8',0x00 + dw ARM_instruction_vrhadd.u8-instruction_handler + db 'vrshl~~.s16',0x00 + dw ARM_instruction_vrshl.s16-instruction_handler + db 'vrshl~~.s32',0x00 + dw ARM_instruction_vrshl.s32-instruction_handler + db 'vrshl~~.s64',0x00 + dw ARM_instruction_vrshl.s64-instruction_handler + db 'vrshl~~.u16',0x00 + dw ARM_instruction_vrshl.u16-instruction_handler + db 'vrshl~~.u32',0x00 + dw ARM_instruction_vrshl.u32-instruction_handler + db 'vrshl~~.u64',0x00 + dw ARM_instruction_vrshl.u64-instruction_handler + db 'vrshr~~.s16',0x00 + dw ARM_instruction_vrshr.s16-instruction_handler + db 'vrshr~~.s32',0x00 + dw ARM_instruction_vrshr.s32-instruction_handler + db 'vrshr~~.s64',0x00 + dw ARM_instruction_vrshr.s64-instruction_handler + db 'vrshr~~.u16',0x00 + dw ARM_instruction_vrshr.u16-instruction_handler + db 'vrshr~~.u32',0x00 + dw ARM_instruction_vrshr.u32-instruction_handler + db 'vrshr~~.u64',0x00 + dw ARM_instruction_vrshr.u64-instruction_handler + db 'vrsqrte.f32',0xe0 + dw ARM_instruction_vrsqrte.f32-instruction_handler + db 'vrsqrte.u32',0xe0 + dw ARM_instruction_vrsqrte.u32-instruction_handler + db 'vrsqrts.f32',0xe0 + dw ARM_instruction_vrsqrts.f32-instruction_handler + db 'vrsra~~.s16',0x00 + dw ARM_instruction_vrsra.s16-instruction_handler + db 'vrsra~~.s32',0x00 + dw ARM_instruction_vrsra.s32-instruction_handler + db 'vrsra~~.s64',0x00 + dw ARM_instruction_vrsra.s64-instruction_handler + db 'vrsra~~.u16',0x00 + dw ARM_instruction_vrsra.u16-instruction_handler + db 'vrsra~~.u32',0x00 + dw ARM_instruction_vrsra.u32-instruction_handler + db 'vrsra~~.u64',0x00 + dw ARM_instruction_vrsra.u64-instruction_handler + db 'vrsubhn.i16',0xe0 + dw ARM_instruction_vrsubhn.i16-instruction_handler + db 'vrsubhn.i32',0xe0 + dw ARM_instruction_vrsubhn.i32-instruction_handler + db 'vrsubhn.i64',0xe0 + dw ARM_instruction_vrsubhn.i64-instruction_handler + db 'vshll~~.i16',0x00 + dw ARM_instruction_vshll.i16-instruction_handler + db 'vshll~~.i32',0x00 + dw ARM_instruction_vshll.i32-instruction_handler + db 'vshll~~.s16',0x00 + dw ARM_instruction_vshll.s16-instruction_handler + db 'vshll~~.s32',0x00 + dw ARM_instruction_vshll.s32-instruction_handler + db 'vshll~~.u16',0x00 + dw ARM_instruction_vshll.u16-instruction_handler + db 'vshll~~.u32',0x00 + dw ARM_instruction_vshll.u32-instruction_handler + db 'vshrn~~.i16',0x00 + dw ARM_instruction_vshrn.i16-instruction_handler + db 'vshrn~~.i32',0x00 + dw ARM_instruction_vshrn.i32-instruction_handler + db 'vshrn~~.i64',0x00 + dw ARM_instruction_vshrn.i64-instruction_handler + db 'vsqrt~~.f32',0x00 + dw ARM_instruction_vsqrt.f32-instruction_handler + db 'vsqrt~~.f64',0x00 + dw ARM_instruction_vsqrt.f64-instruction_handler + db 'vstmdb~~.32',0x00 + dw ARM_instruction_vstmdb.32-instruction_handler + db 'vstmdb~~.64',0x00 + dw ARM_instruction_vstmdb.64-instruction_handler + db 'vstmea~~.32',0x00 + dw ARM_instruction_vstmea.32-instruction_handler + db 'vstmea~~.64',0x00 + dw ARM_instruction_vstmea.64-instruction_handler + db 'vstmfd~~.32',0x00 + dw ARM_instruction_vstmfd.32-instruction_handler + db 'vstmfd~~.64',0x00 + dw ARM_instruction_vstmfd.64-instruction_handler + db 'vstmia~~.32',0x00 + dw ARM_instruction_vstmia.32-instruction_handler + db 'vstmia~~.64',0x00 + dw ARM_instruction_vstmia.64-instruction_handler + db 'vsubl~~.s16',0x00 + dw ARM_instruction_vsubl.s16-instruction_handler + db 'vsubl~~.s32',0x00 + dw ARM_instruction_vsubl.s32-instruction_handler + db 'vsubl~~.u16',0x00 + dw ARM_instruction_vsubl.u16-instruction_handler + db 'vsubl~~.u32',0x00 + dw ARM_instruction_vsubl.u32-instruction_handler + db 'vsubw~~.s16',0x00 + dw ARM_instruction_vsubw.s16-instruction_handler + db 'vsubw~~.s32',0x00 + dw ARM_instruction_vsubw.s32-instruction_handler + db 'vsubw~~.u16',0x00 + dw ARM_instruction_vsubw.u16-instruction_handler + db 'vsubw~~.u32',0x00 + dw ARM_instruction_vsubw.u32-instruction_handler + db 'wabsdiffb~~',0x00 + dw ARM_instruction_wabsdiffb-instruction_handler + db 'wabsdiffh~~',0x00 + dw ARM_instruction_wabsdiffh-instruction_handler + db 'wabsdiffw~~',0x00 + dw ARM_instruction_wabsdiffw-instruction_handler + db 'waddsubhx~~',0x00 + dw ARM_instruction_waddsubhx-instruction_handler + db 'wsubaddhx~~',0x00 + dw ARM_instruction_wsubaddhx-instruction_handler + db 'wunpckihb~~',0x00 + dw ARM_instruction_wunpckihb-instruction_handler + db 'wunpckihh~~',0x00 + dw ARM_instruction_wunpckihh-instruction_handler + db 'wunpckihw~~',0x00 + dw ARM_instruction_wunpckihw-instruction_handler + db 'wunpckilb~~',0x00 + dw ARM_instruction_wunpckilb-instruction_handler + db 'wunpckilh~~',0x00 + dw ARM_instruction_wunpckilh-instruction_handler + db 'wunpckilw~~',0x00 + dw ARM_instruction_wunpckilw-instruction_handler + db 0 +instructions_12: + db 'cftruncd32~~',0x00 + dw ARM_instruction_cftruncd32-instruction_handler + db 'cftruncs32~~',0x00 + dw ARM_instruction_cftruncs32-instruction_handler + db 'sha256su0.32',0xf0 + dw ARM_instruction_sha256su0.32-instruction_handler + db 'sha256su1.32',0xf0 + dw ARM_instruction_sha256su1.32-instruction_handler + db 'vaddhn~~.i16',0x00 + dw ARM_instruction_vaddhn.i16-instruction_handler + db 'vaddhn~~.i32',0x00 + dw ARM_instruction_vaddhn.i32-instruction_handler + db 'vaddhn~~.i64',0x00 + dw ARM_instruction_vaddhn.i64-instruction_handler + db 'vcvt.f16.f32',0xe0 + dw ARM_instruction_vcvt.f16.f32-instruction_handler + db 'vcvt.f32.f16',0xe0 + dw ARM_instruction_vcvt.f32.f16-instruction_handler + db 'vcvt.f32.f64',0xe0 + dw ARM_instruction_vcvt.f32.f64-instruction_handler + db 'vcvt.f32.s16',0xe0 + dw ARM_instruction_vcvt.f32.s16-instruction_handler + db 'vcvt.f32.s32',0xe0 + dw ARM_instruction_vcvt.f32.s32-instruction_handler + db 'vcvt.f32.u16',0xe0 + dw ARM_instruction_vcvt.f32.u16-instruction_handler + db 'vcvt.f32.u32',0xe0 + dw ARM_instruction_vcvt.f32.u32-instruction_handler + db 'vcvt.f64.f32',0xe0 + dw ARM_instruction_vcvt.f64.f32-instruction_handler + db 'vcvt.f64.s16',0xe0 + dw ARM_instruction_vcvt.f64.s16-instruction_handler + db 'vcvt.f64.s32',0xe0 + dw ARM_instruction_vcvt.f64.s32-instruction_handler + db 'vcvt.f64.u16',0xe0 + dw ARM_instruction_vcvt.f64.u16-instruction_handler + db 'vcvt.f64.u32',0xe0 + dw ARM_instruction_vcvt.f64.u32-instruction_handler + db 'vcvt.s16.f32',0xe0 + dw ARM_instruction_vcvt.s16.f32-instruction_handler + db 'vcvt.s16.f64',0xe0 + dw ARM_instruction_vcvt.s16.f64-instruction_handler + db 'vcvt.s32.f32',0xe0 + dw ARM_instruction_vcvt.s32.f32-instruction_handler + db 'vcvt.s32.f64',0xe0 + dw ARM_instruction_vcvt.s32.f64-instruction_handler + db 'vcvt.u16.f32',0xe0 + dw ARM_instruction_vcvt.u16.f32-instruction_handler + db 'vcvt.u16.f64',0xe0 + dw ARM_instruction_vcvt.u16.f64-instruction_handler + db 'vcvt.u32.f32',0xe0 + dw ARM_instruction_vcvt.u32.f32-instruction_handler + db 'vcvt.u32.f64',0xe0 + dw ARM_instruction_vcvt.u32.f64-instruction_handler + db 'vpadal~~.s16',0x00 + dw ARM_instruction_vpadal.s16-instruction_handler + db 'vpadal~~.s32',0x00 + dw ARM_instruction_vpadal.s32-instruction_handler + db 'vpadal~~.u16',0x00 + dw ARM_instruction_vpadal.u16-instruction_handler + db 'vpadal~~.u32',0x00 + dw ARM_instruction_vpadal.u32-instruction_handler + db 'vpaddl~~.s16',0x00 + dw ARM_instruction_vpaddl.s16-instruction_handler + db 'vpaddl~~.s32',0x00 + dw ARM_instruction_vpaddl.s32-instruction_handler + db 'vpaddl~~.u16',0x00 + dw ARM_instruction_vpaddl.u16-instruction_handler + db 'vpaddl~~.u32',0x00 + dw ARM_instruction_vpaddl.u32-instruction_handler + db 'vqmovn~~.s16',0x00 + dw ARM_instruction_vqmovn.s16-instruction_handler + db 'vqmovn~~.s32',0x00 + dw ARM_instruction_vqmovn.s32-instruction_handler + db 'vqmovn~~.s64',0x00 + dw ARM_instruction_vqmovn.s64-instruction_handler + db 'vqmovn~~.u16',0x00 + dw ARM_instruction_vqmovn.u16-instruction_handler + db 'vqmovn~~.u32',0x00 + dw ARM_instruction_vqmovn.u32-instruction_handler + db 'vqmovn~~.u64',0x00 + dw ARM_instruction_vqmovn.u64-instruction_handler + db 'vqrdmulh.s16',0xe0 + dw ARM_instruction_vqrdmulh.s16-instruction_handler + db 'vqrdmulh.s32',0xe0 + dw ARM_instruction_vqrdmulh.s32-instruction_handler + db 'vqrshl~~.s16',0x00 + dw ARM_instruction_vqrshl.s16-instruction_handler + db 'vqrshl~~.s32',0x00 + dw ARM_instruction_vqrshl.s32-instruction_handler + db 'vqrshl~~.s64',0x00 + dw ARM_instruction_vqrshl.s64-instruction_handler + db 'vqrshl~~.u16',0x00 + dw ARM_instruction_vqrshl.u16-instruction_handler + db 'vqrshl~~.u32',0x00 + dw ARM_instruction_vqrshl.u32-instruction_handler + db 'vqrshl~~.u64',0x00 + dw ARM_instruction_vqrshl.u64-instruction_handler + db 'vqrshrun.s16',0xe0 + dw ARM_instruction_vqrshrun.s16-instruction_handler + db 'vqrshrun.s32',0xe0 + dw ARM_instruction_vqrshrun.s32-instruction_handler + db 'vqrshrun.s64',0xe0 + dw ARM_instruction_vqrshrun.s64-instruction_handler + db 'vqshlu~~.s16',0x00 + dw ARM_instruction_vqshlu.s16-instruction_handler + db 'vqshlu~~.s32',0x00 + dw ARM_instruction_vqshlu.s32-instruction_handler + db 'vqshlu~~.s64',0x00 + dw ARM_instruction_vqshlu.s64-instruction_handler + db 'vqshrn~~.s16',0x00 + dw ARM_instruction_vqshrn.s16-instruction_handler + db 'vqshrn~~.s32',0x00 + dw ARM_instruction_vqshrn.s32-instruction_handler + db 'vqshrn~~.s64',0x00 + dw ARM_instruction_vqshrn.s64-instruction_handler + db 'vqshrn~~.u16',0x00 + dw ARM_instruction_vqshrn.u16-instruction_handler + db 'vqshrn~~.u32',0x00 + dw ARM_instruction_vqshrn.u32-instruction_handler + db 'vqshrn~~.u64',0x00 + dw ARM_instruction_vqshrn.u64-instruction_handler + db 'vrecpe~~.f32',0x00 + dw ARM_instruction_vrecpe.f32-instruction_handler + db 'vrecpe~~.u32',0x00 + dw ARM_instruction_vrecpe.u32-instruction_handler + db 'vrecps~~.f32',0x00 + dw ARM_instruction_vrecps.f32-instruction_handler + db 'vrhadd~~.s16',0x00 + dw ARM_instruction_vrhadd.s16-instruction_handler + db 'vrhadd~~.s32',0x00 + dw ARM_instruction_vrhadd.s32-instruction_handler + db 'vrhadd~~.u16',0x00 + dw ARM_instruction_vrhadd.u16-instruction_handler + db 'vrhadd~~.u32',0x00 + dw ARM_instruction_vrhadd.u32-instruction_handler + db 'vrshrn~~.i16',0x00 + dw ARM_instruction_vrshrn.i16-instruction_handler + db 'vrshrn~~.i32',0x00 + dw ARM_instruction_vrshrn.i32-instruction_handler + db 'vrshrn~~.i64',0x00 + dw ARM_instruction_vrshrn.i64-instruction_handler + db 'vsubhn~~.i16',0x00 + dw ARM_instruction_vsubhn.i16-instruction_handler + db 'vsubhn~~.i32',0x00 + dw ARM_instruction_vsubhn.i32-instruction_handler + db 'vsubhn~~.i64',0x00 + dw ARM_instruction_vsubhn.i64-instruction_handler + db 'wunpckehsb~~',0x00 + dw ARM_instruction_wunpckehsb-instruction_handler + db 'wunpckehsh~~',0x00 + dw ARM_instruction_wunpckehsh-instruction_handler + db 'wunpckehsw~~',0x00 + dw ARM_instruction_wunpckehsw-instruction_handler + db 'wunpckehub~~',0x00 + dw ARM_instruction_wunpckehub-instruction_handler + db 'wunpckehuh~~',0x00 + dw ARM_instruction_wunpckehuh-instruction_handler + db 'wunpckehuw~~',0x00 + dw ARM_instruction_wunpckehuw-instruction_handler + db 'wunpckelsb~~',0x00 + dw ARM_instruction_wunpckelsb-instruction_handler + db 'wunpckelsh~~',0x00 + dw ARM_instruction_wunpckelsh-instruction_handler + db 'wunpckelsw~~',0x00 + dw ARM_instruction_wunpckelsw-instruction_handler + db 'wunpckelub~~',0x00 + dw ARM_instruction_wunpckelub-instruction_handler + db 'wunpckeluh~~',0x00 + dw ARM_instruction_wunpckeluh-instruction_handler + db 'wunpckeluw~~',0x00 + dw ARM_instruction_wunpckeluw-instruction_handler + db 0 +instructions_13: + db 'vcvta.s32.f32',0xf0 + dw ARM_instruction_vcvta.s32.f32-instruction_handler + db 'vcvta.s32.f64',0xf0 + dw ARM_instruction_vcvta.s32.f64-instruction_handler + db 'vcvta.u32.f32',0xf0 + dw ARM_instruction_vcvta.u32.f32-instruction_handler + db 'vcvta.u32.f64',0xf0 + dw ARM_instruction_vcvta.u32.f64-instruction_handler + db 'vcvtb.f16.f32',0xe0 + dw ARM_instruction_vcvtb.f16.f32-instruction_handler + db 'vcvtb.f16.f64',0xe0 + dw ARM_instruction_vcvtb.f16.f64-instruction_handler + db 'vcvtb.f32.f16',0xe0 + dw ARM_instruction_vcvtb.f32.f16-instruction_handler + db 'vcvtb.f64.f16',0xe0 + dw ARM_instruction_vcvtb.f64.f16-instruction_handler + db 'vcvtm.s32.f32',0xf0 + dw ARM_instruction_vcvtm.s32.f32-instruction_handler + db 'vcvtm.s32.f64',0xf0 + dw ARM_instruction_vcvtm.s32.f64-instruction_handler + db 'vcvtm.u32.f32',0xf0 + dw ARM_instruction_vcvtm.u32.f32-instruction_handler + db 'vcvtm.u32.f64',0xf0 + dw ARM_instruction_vcvtm.u32.f64-instruction_handler + db 'vcvtn.s32.f32',0xf0 + dw ARM_instruction_vcvtn.s32.f32-instruction_handler + db 'vcvtn.s32.f64',0xf0 + dw ARM_instruction_vcvtn.s32.f64-instruction_handler + db 'vcvtn.u32.f32',0xf0 + dw ARM_instruction_vcvtn.u32.f32-instruction_handler + db 'vcvtn.u32.f64',0xf0 + dw ARM_instruction_vcvtn.u32.f64-instruction_handler + db 'vcvtp.s32.f32',0xf0 + dw ARM_instruction_vcvtp.s32.f32-instruction_handler + db 'vcvtp.s32.f64',0xf0 + dw ARM_instruction_vcvtp.s32.f64-instruction_handler + db 'vcvtp.u32.f32',0xf0 + dw ARM_instruction_vcvtp.u32.f32-instruction_handler + db 'vcvtp.u32.f64',0xf0 + dw ARM_instruction_vcvtp.u32.f64-instruction_handler + db 'vcvtr.s32.f32',0xe0 + dw ARM_instruction_vcvtr.s32.f32-instruction_handler + db 'vcvtr.s32.f64',0xe0 + dw ARM_instruction_vcvtr.s32.f64-instruction_handler + db 'vcvtr.u32.f32',0xe0 + dw ARM_instruction_vcvtr.u32.f32-instruction_handler + db 'vcvtr.u32.f64',0xe0 + dw ARM_instruction_vcvtr.u32.f64-instruction_handler + db 'vcvtt.f16.f32',0xe0 + dw ARM_instruction_vcvtt.f16.f32-instruction_handler + db 'vcvtt.f16.f64',0xe0 + dw ARM_instruction_vcvtt.f16.f64-instruction_handler + db 'vcvtt.f32.f16',0xe0 + dw ARM_instruction_vcvtt.f32.f16-instruction_handler + db 'vcvtt.f64.f16',0xe0 + dw ARM_instruction_vcvtt.f64.f16-instruction_handler + db 'vqdmlal~~.s16',0x00 + dw ARM_instruction_vqdmlal.s16-instruction_handler + db 'vqdmlal~~.s32',0x00 + dw ARM_instruction_vqdmlal.s32-instruction_handler + db 'vqdmlsl~~.s16',0x00 + dw ARM_instruction_vqdmlsl.s16-instruction_handler + db 'vqdmlsl~~.s32',0x00 + dw ARM_instruction_vqdmlsl.s32-instruction_handler + db 'vqdmulh~~.s16',0x00 + dw ARM_instruction_vqdmulh.s16-instruction_handler + db 'vqdmulh~~.s32',0x00 + dw ARM_instruction_vqdmulh.s32-instruction_handler + db 'vqdmull~~.s16',0x00 + dw ARM_instruction_vqdmull.s16-instruction_handler + db 'vqdmull~~.s32',0x00 + dw ARM_instruction_vqdmull.s32-instruction_handler + db 'vqmovun~~.s16',0x00 + dw ARM_instruction_vqmovun.s16-instruction_handler + db 'vqmovun~~.s32',0x00 + dw ARM_instruction_vqmovun.s32-instruction_handler + db 'vqmovun~~.s64',0x00 + dw ARM_instruction_vqmovun.s64-instruction_handler + db 'vqrshrn~~.s16',0x00 + dw ARM_instruction_vqrshrn.s16-instruction_handler + db 'vqrshrn~~.s32',0x00 + dw ARM_instruction_vqrshrn.s32-instruction_handler + db 'vqrshrn~~.s64',0x00 + dw ARM_instruction_vqrshrn.s64-instruction_handler + db 'vqrshrn~~.u16',0x00 + dw ARM_instruction_vqrshrn.u16-instruction_handler + db 'vqrshrn~~.u32',0x00 + dw ARM_instruction_vqrshrn.u32-instruction_handler + db 'vqrshrn~~.u64',0x00 + dw ARM_instruction_vqrshrn.u64-instruction_handler + db 'vqshrun~~.s16',0x00 + dw ARM_instruction_vqshrun.s16-instruction_handler + db 'vqshrun~~.s32',0x00 + dw ARM_instruction_vqshrun.s32-instruction_handler + db 'vqshrun~~.s64',0x00 + dw ARM_instruction_vqshrun.s64-instruction_handler + db 'vraddhn~~.i16',0x00 + dw ARM_instruction_vraddhn.i16-instruction_handler + db 'vraddhn~~.i32',0x00 + dw ARM_instruction_vraddhn.i32-instruction_handler + db 'vraddhn~~.i64',0x00 + dw ARM_instruction_vraddhn.i64-instruction_handler + db 'vrsqrte~~.f32',0x00 + dw ARM_instruction_vrsqrte.f32-instruction_handler + db 'vrsqrte~~.u32',0x00 + dw ARM_instruction_vrsqrte.u32-instruction_handler + db 'vrsqrts~~.f32',0x00 + dw ARM_instruction_vrsqrts.f32-instruction_handler + db 'vrsubhn~~.i16',0x00 + dw ARM_instruction_vrsubhn.i16-instruction_handler + db 'vrsubhn~~.i32',0x00 + dw ARM_instruction_vrsubhn.i32-instruction_handler + db 'vrsubhn~~.i64',0x00 + dw ARM_instruction_vrsubhn.i64-instruction_handler + db 0 +instructions_14: + db 'vcvt~~.f16.f32',0x00 + dw ARM_instruction_vcvt.f16.f32-instruction_handler + db 'vcvt~~.f32.f16',0x00 + dw ARM_instruction_vcvt.f32.f16-instruction_handler + db 'vcvt~~.f32.f64',0x00 + dw ARM_instruction_vcvt.f32.f64-instruction_handler + db 'vcvt~~.f32.s16',0x00 + dw ARM_instruction_vcvt.f32.s16-instruction_handler + db 'vcvt~~.f32.s32',0x00 + dw ARM_instruction_vcvt.f32.s32-instruction_handler + db 'vcvt~~.f32.u16',0x00 + dw ARM_instruction_vcvt.f32.u16-instruction_handler + db 'vcvt~~.f32.u32',0x00 + dw ARM_instruction_vcvt.f32.u32-instruction_handler + db 'vcvt~~.f64.f32',0x00 + dw ARM_instruction_vcvt.f64.f32-instruction_handler + db 'vcvt~~.f64.s16',0x00 + dw ARM_instruction_vcvt.f64.s16-instruction_handler + db 'vcvt~~.f64.s32',0x00 + dw ARM_instruction_vcvt.f64.s32-instruction_handler + db 'vcvt~~.f64.u16',0x00 + dw ARM_instruction_vcvt.f64.u16-instruction_handler + db 'vcvt~~.f64.u32',0x00 + dw ARM_instruction_vcvt.f64.u32-instruction_handler + db 'vcvt~~.s16.f32',0x00 + dw ARM_instruction_vcvt.s16.f32-instruction_handler + db 'vcvt~~.s16.f64',0x00 + dw ARM_instruction_vcvt.s16.f64-instruction_handler + db 'vcvt~~.s32.f32',0x00 + dw ARM_instruction_vcvt.s32.f32-instruction_handler + db 'vcvt~~.s32.f64',0x00 + dw ARM_instruction_vcvt.s32.f64-instruction_handler + db 'vcvt~~.u16.f32',0x00 + dw ARM_instruction_vcvt.u16.f32-instruction_handler + db 'vcvt~~.u16.f64',0x00 + dw ARM_instruction_vcvt.u16.f64-instruction_handler + db 'vcvt~~.u32.f32',0x00 + dw ARM_instruction_vcvt.u32.f32-instruction_handler + db 'vcvt~~.u32.f64',0x00 + dw ARM_instruction_vcvt.u32.f64-instruction_handler + db 'vqrdmulh~~.s16',0x00 + dw ARM_instruction_vqrdmulh.s16-instruction_handler + db 'vqrdmulh~~.s32',0x00 + dw ARM_instruction_vqrdmulh.s32-instruction_handler + db 'vqrshrun~~.s16',0x00 + dw ARM_instruction_vqrshrun.s16-instruction_handler + db 'vqrshrun~~.s32',0x00 + dw ARM_instruction_vqrshrun.s32-instruction_handler + db 'vqrshrun~~.s64',0x00 + dw ARM_instruction_vqrshrun.s64-instruction_handler + db 'vrinta.f32.f32',0xf0 + dw ARM_instruction_vrinta.f32.f32-instruction_handler + db 'vrinta.f64.f64',0xf0 + dw ARM_instruction_vrinta.f64.f64-instruction_handler + db 'vrintm.f32.f32',0xf0 + dw ARM_instruction_vrintm.f32.f32-instruction_handler + db 'vrintm.f64.f64',0xf0 + dw ARM_instruction_vrintm.f64.f64-instruction_handler + db 'vrintn.f32.f32',0xf0 + dw ARM_instruction_vrintn.f32.f32-instruction_handler + db 'vrintn.f64.f64',0xf0 + dw ARM_instruction_vrintn.f64.f64-instruction_handler + db 'vrintp.f32.f32',0xf0 + dw ARM_instruction_vrintp.f32.f32-instruction_handler + db 'vrintp.f64.f64',0xf0 + dw ARM_instruction_vrintp.f64.f64-instruction_handler + db 'vrintr.f32.f32',0xe0 + dw ARM_instruction_vrintr.f32.f32-instruction_handler + db 'vrintr.f64.f64',0xe0 + dw ARM_instruction_vrintr.f64.f64-instruction_handler + db 'vrintx.f32.f32',0xe0 + dw ARM_instruction_vrintx.f32.f32-instruction_handler + db 'vrintx.f64.f64',0xe0 + dw ARM_instruction_vrintx.f64.f64-instruction_handler + db 'vrintz.f32.f32',0xe0 + dw ARM_instruction_vrintz.f32.f32-instruction_handler + db 'vrintz.f64.f64',0xe0 + dw ARM_instruction_vrintz.f64.f64-instruction_handler + db 0 +instructions_15: + db 'vcvtb~~.f16.f32',0x00 + dw ARM_instruction_vcvtb.f16.f32-instruction_handler + db 'vcvtb~~.f16.f64',0x00 + dw ARM_instruction_vcvtb.f16.f64-instruction_handler + db 'vcvtb~~.f32.f16',0x00 + dw ARM_instruction_vcvtb.f32.f16-instruction_handler + db 'vcvtb~~.f64.f16',0x00 + dw ARM_instruction_vcvtb.f64.f16-instruction_handler + db 'vcvtr~~.s32.f32',0x00 + dw ARM_instruction_vcvtr.s32.f32-instruction_handler + db 'vcvtr~~.s32.f64',0x00 + dw ARM_instruction_vcvtr.s32.f64-instruction_handler + db 'vcvtr~~.u32.f32',0x00 + dw ARM_instruction_vcvtr.u32.f32-instruction_handler + db 'vcvtr~~.u32.f64',0x00 + dw ARM_instruction_vcvtr.u32.f64-instruction_handler + db 'vcvtt~~.f16.f32',0x00 + dw ARM_instruction_vcvtt.f16.f32-instruction_handler + db 'vcvtt~~.f16.f64',0x00 + dw ARM_instruction_vcvtt.f16.f64-instruction_handler + db 'vcvtt~~.f32.f16',0x00 + dw ARM_instruction_vcvtt.f32.f16-instruction_handler + db 'vcvtt~~.f64.f16',0x00 + dw ARM_instruction_vcvtt.f64.f16-instruction_handler + db 0 +instructions_16: + db 'vrintr~~.f32.f32',0x00 + dw ARM_instruction_vrintr.f32.f32-instruction_handler + db 'vrintr~~.f64.f64',0x00 + dw ARM_instruction_vrintr.f64.f64-instruction_handler + db 'vrintx~~.f32.f32',0x00 + dw ARM_instruction_vrintx.f32.f32-instruction_handler + db 'vrintx~~.f64.f64',0x00 + dw ARM_instruction_vrintx.f64.f64-instruction_handler + db 'vrintz~~.f32.f32',0x00 + dw ARM_instruction_vrintz.f32.f32-instruction_handler + db 'vrintz~~.f64.f64',0x00 + dw ARM_instruction_vrintz.f64.f64-instruction_handler + db 0 +instructions_end: +purge dw diff --git a/source/armv8.inc b/source/armv8.inc new file mode 100644 index 0000000..5dda0b6 --- /dev/null +++ b/source/armv8.inc @@ -0,0 +1,30304 @@ +; NOTE: This software is under the same copyright as FASM with only the +; copyright holder name changed. + +; ARMv8 assembler core module v1.44 for flat assembler, +; Copyright (c) 2005-2023, revolution. +; All rights reserved. + +; This program is free for commercial and non-commercial use as long as +; the following conditions are adhered to. + +; Copyright remains revolution, and as such any Copyright notices +; in the code are not to be removed. + +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are +; met: + +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. + +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR +; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +; The licence and distribution terms for any publically available +; version or derivative of this code cannot be changed. i.e. this code +; cannot simply be copied and put under another distribution licence +; (including the GNU Public Licence). + +; For best viewing pleasure use a tab stop of 8 characters and fixed +; spacing font + +; Not everything matches the ARM ADS assembly style, where possible the +; original style is used but there are some differences +; 1) label names cannot begin with a digit +; 2) CPSIE and CPSID formats are changed, use "iflags_aif" form instead of +; "aif" (eg. "CPSIE iflags_i" instead of "CPSID i") +; 3) SRS with writeback must have a separating space after the mode number +; and before "!" (eg. "SRSDB 16 !" instead of "SRSDB 16!") +; 4) macro, rept, irp, format, if, virtual etc. are all significant changes +; from the ARM ADS, so you will need to re-write those sections of +; existing code + +ARM_VERSION_STRING equ "1.44" +ARM_VERSION_MAJOR = 1 +ARM_VERSION_MINOR = 44 + +;outline of [code_type] bits + +CPU_ACTIVITY_THUMB_NON_UAL = 1 shl 1 ;1 for THUMB_NON_UAL mode, 0 for ARM or THUMB_UAL mode +CPU_ACTIVITY_THUMB_UAL = 1 shl 2 ;1 for THUMB_UAL mode, 0 for ARM or THUMB_NON_UAL mode +CPU_ACTIVITY_ARM = 1 shl 3 ;1 for ARM mode, 0 for THUMB_NON_UAL or THUMB_UAL mode +CPU_ACTIVITY_UNKNOWN = 1 shl 4 ;this the default at startup +CPU_ACTIVITY_THUMBEE = 1 shl 5 ;1 for THUMBEE mode when CPU_ACTIVITY_THUMB_UAL is active +CPU_ACTIVITY_ARM64 = 1 shl 6 ;1 for ARM64 code + +CPU32_CAPABILITY_26BIT = 0 +CPU32_CAPABILITY_V1 = 1 +CPU32_CAPABILITY_V2 = 2 +CPU32_CAPABILITY_A = 3 +CPU32_CAPABILITY_V3 = 4 +CPU32_CAPABILITY_M = 5 +CPU32_CAPABILITY_V4 = 6 +CPU32_CAPABILITY_V4T = 7 +CPU32_CAPABILITY_V5 = 8 +CPU32_CAPABILITY_V5T = 9 +CPU32_CAPABILITY_E = 10 +CPU32_CAPABILITY_P = 11 +CPU32_CAPABILITY_J = 12 +CPU32_CAPABILITY_X = 13 +CPU32_CAPABILITY_V6 = 14 +CPU32_CAPABILITY_V6T = 15 +CPU32_CAPABILITY_ALIGN = 16 +CPU32_CAPABILITY_K = 17 +CPU32_CAPABILITY_Z = 18 +CPU32_CAPABILITY_6M = 19 +CPU32_CAPABILITY_7M = 20 +CPU32_CAPABILITY_T2 = 21 +CPU32_CAPABILITY_V7 = 22 +CPU32_CAPABILITY_SYNC = 23 +CPU32_CAPABILITY_DIV = 24 +CPU32_CAPABILITY_T2EE = 25 +CPU32_CAPABILITY_MP = 26 +CPU32_CAPABILITY_VE = 27 +CPU32_CAPABILITY_V8 = 28 ;v8 instructions in ARM32 and THUMB modes +CPU32_CAPABILITY_CRC = 29 ;CRC instructions in ARM32 and THUMB modes + +COPRO_CAPABILITY_FPA_V1 = 0 +COPRO_CAPABILITY_FPA_V2 = 1 +COPRO_CAPABILITY_MAVERICK = 2 +COPRO_CAPABILITY_VFP_V1xD = 3 +COPRO_CAPABILITY_VFP_V1 = 4 +COPRO_CAPABILITY_VFP_V2 = 5 +COPRO_CAPABILITY_VFP_V3 = 6 +COPRO_CAPABILITY_VFP_D32 = 7 +COPRO_CAPABILITY_VFP_HP = 8 +COPRO_CAPABILITY_XSCALE = 9 +COPRO_CAPABILITY_IWMMXT_V1 = 10 +COPRO_CAPABILITY_IWMMXT_V2 = 11 +COPRO_CAPABILITY_SIMD_INT = 12 +COPRO_CAPABILITY_SIMD_FLOAT = 13 +COPRO_CAPABILITY_SIMD_HP = 14 +COPRO_CAPABILITY_VFP_V4 = 15 +COPRO_CAPABILITY_SIMD_V2 = 16 +COPRO_CAPABILITY_SIMD_V8 = 17 +COPRO_CAPABILITY_SIMD_CRYPTO = 18 + +CPU_CAPABILITY_DEFAULT =\ + 1 shl CPU32_CAPABILITY_26BIT +\ + 1 shl CPU32_CAPABILITY_V1 +\ + 1 shl CPU32_CAPABILITY_V2 +\ + 1 shl CPU32_CAPABILITY_A +\ + 1 shl CPU32_CAPABILITY_V3 +\ + 1 shl CPU32_CAPABILITY_M +\ + 1 shl CPU32_CAPABILITY_V4 +\ + 1 shl CPU32_CAPABILITY_V4T +\ + 1 shl CPU32_CAPABILITY_V5 +\ + 1 shl CPU32_CAPABILITY_V5T +\ + 1 shl CPU32_CAPABILITY_E +\ + 1 shl CPU32_CAPABILITY_P +\ + 1 shl CPU32_CAPABILITY_J +\ + 1 shl CPU32_CAPABILITY_X +\ + 1 shl CPU32_CAPABILITY_V6 +\ + 1 shl CPU32_CAPABILITY_V6T +\ + 1 shl CPU32_CAPABILITY_ALIGN +\ + 1 shl CPU32_CAPABILITY_K +\ + 1 shl CPU32_CAPABILITY_Z +\ + 1 shl CPU32_CAPABILITY_6M +\ + 1 shl CPU32_CAPABILITY_7M +\ + 1 shl CPU32_CAPABILITY_T2 +\ + 1 shl CPU32_CAPABILITY_V7 +\ + 1 shl CPU32_CAPABILITY_SYNC +\ + 1 shl CPU32_CAPABILITY_DIV +\ + 1 shl CPU32_CAPABILITY_T2EE +\ + 1 shl CPU32_CAPABILITY_MP +\ + 1 shl CPU32_CAPABILITY_VE +\ + 1 shl CPU32_CAPABILITY_V8 +\ + 1 shl CPU32_CAPABILITY_CRC + +COPRO_CAPABILITY_DEFAULT =\ + 1 shl COPRO_CAPABILITY_FPA_V1 +\ + 1 shl COPRO_CAPABILITY_FPA_V2 +\ + 1 shl COPRO_CAPABILITY_MAVERICK +\ + 1 shl COPRO_CAPABILITY_VFP_V1xD +\ + 1 shl COPRO_CAPABILITY_VFP_V1 +\ + 1 shl COPRO_CAPABILITY_VFP_V2 +\ + 1 shl COPRO_CAPABILITY_VFP_V3 +\ + 1 shl COPRO_CAPABILITY_VFP_D32 +\ + 1 shl COPRO_CAPABILITY_VFP_HP +\ + 1 shl COPRO_CAPABILITY_XSCALE +\ + 1 shl COPRO_CAPABILITY_IWMMXT_V1 +\ + 1 shl COPRO_CAPABILITY_IWMMXT_V2 +\ + 1 shl COPRO_CAPABILITY_SIMD_INT +\ + 1 shl COPRO_CAPABILITY_SIMD_FLOAT +\ + 1 shl COPRO_CAPABILITY_SIMD_HP +\ + 1 shl COPRO_CAPABILITY_VFP_V4 +\ + 1 shl COPRO_CAPABILITY_SIMD_V2 +\ + 1 shl COPRO_CAPABILITY_SIMD_V8 +\ + 1 shl COPRO_CAPABILITY_SIMD_CRYPTO + +CPU64_CAPABILITY_V8 = 32 ;v8 instructions in ARM64 mode +CPU64_CAPABILITY_FP = CPU64_CAPABILITY_V8 + 1 ;floating point instructions in ARM64 mode +CPU64_CAPABILITY_SIMD = CPU64_CAPABILITY_FP + 1 ;SIMD instructions in ARM64 mode +CPU64_CAPABILITY_CRC = CPU64_CAPABILITY_SIMD + 1 ;CRC instructions in ARM64 mode +CPU64_CAPABILITY_CRYPTO = CPU64_CAPABILITY_CRC + 1 ;cryptography instructions in ARM64 mode + +CPU32_CAPABILITY_ALL = CPU_CAPABILITY_DEFAULT +COPRO_CAPABILITY_ALL = COPRO_CAPABILITY_DEFAULT +CPU64_CAPABILITY_ALL =\ + 1 shl CPU64_CAPABILITY_V8 +\ + 1 shl CPU64_CAPABILITY_FP +\ + 1 shl CPU64_CAPABILITY_SIMD +\ + 1 shl CPU64_CAPABILITY_CRC +\ + 1 shl CPU64_CAPABILITY_CRYPTO + +ARM_code = CPU_ACTIVITY_ARM + +FLAG_BIT_CONDITION_SET = 0 +FLAG_BIT_FORCE_WIDE = 1 +FLAG_BIT_FORCE_NARROW = 2 +FLAG_BIT_FORCE_AUTO_WIDE = 3 + +FLAG_CONDITION_SET = 1 shl FLAG_BIT_CONDITION_SET +FLAG_FORCE_WIDE = 1 shl FLAG_BIT_FORCE_WIDE +FLAG_FORCE_NARROW = 1 shl FLAG_BIT_FORCE_NARROW +FLAG_FORCE_AUTO_WIDE = 1 shl FLAG_BIT_FORCE_AUTO_WIDE + +CONDITION_SEARCH_CHARACTER = '~' + +;undefined instruction space, we use this for triggering unencodable instructions +;xxxx_0111_1111_xxxx_xxxx_xxxx_1111_xxxx x7fxxxfx arm + +UNENCODEABLE_INSTRUCTION_ARM = 0xf7ffffff + +THUMB_FLAG_NOT_INSIDE_IT = 1 shl 0 ;not allowable inside an IT block +THUMB_FLAG_ONLY_INSIDE_IT = 1 shl 1 ;only allowable inside an IT block +THUMB_FLAG_ONLY_LAST_IT = 1 shl 2 ;only allowable as last instruction of an IT block +THUMB_FLAG_IS_BCC = 1 shl 3 ;special Bcc opcodes are conditional but exist outside an IT block + +ARM_INSTRUCTION_OPCODE_AND = 0000b +ARM_INSTRUCTION_OPCODE_EOR = 0001b +ARM_INSTRUCTION_OPCODE_SUB = 0010b +ARM_INSTRUCTION_OPCODE_RSB = 0011b +ARM_INSTRUCTION_OPCODE_ADD = 0100b +ARM_INSTRUCTION_OPCODE_ADC = 0101b +ARM_INSTRUCTION_OPCODE_SBC = 0110b +ARM_INSTRUCTION_OPCODE_RSC = 0111b +ARM_INSTRUCTION_OPCODE_TST = 1000b +ARM_INSTRUCTION_OPCODE_TEQ = 1001b +ARM_INSTRUCTION_OPCODE_CMP = 1010b +ARM_INSTRUCTION_OPCODE_CMN = 1011b +ARM_INSTRUCTION_OPCODE_ORR = 1100b +ARM_INSTRUCTION_OPCODE_MOV = 1101b +ARM_INSTRUCTION_OPCODE_BIC = 1110b +ARM_INSTRUCTION_OPCODE_MVN = 1111b + +ARM_SHIFT_OPCODE_LSL = 0 +ARM_SHIFT_OPCODE_LSR = 1 +ARM_SHIFT_OPCODE_ASR = 2 +ARM_SHIFT_OPCODE_ROR = 3 + +THUMB_INSTRUCTION_OPCODE_AND = 0000b +THUMB_INSTRUCTION_OPCODE_EOR = 0001b +THUMB_INSTRUCTION_OPCODE_LSL = 0010b +THUMB_INSTRUCTION_OPCODE_LSR = 0011b +THUMB_INSTRUCTION_OPCODE_ASR = 0100b +THUMB_INSTRUCTION_OPCODE_ADC = 0101b +THUMB_INSTRUCTION_OPCODE_SBC = 0110b +THUMB_INSTRUCTION_OPCODE_ROR = 0111b +THUMB_INSTRUCTION_OPCODE_TST = 1000b +THUMB_INSTRUCTION_OPCODE_NEG = 1001b +THUMB_INSTRUCTION_OPCODE_CMP = 1010b +THUMB_INSTRUCTION_OPCODE_CMN = 1011b +THUMB_INSTRUCTION_OPCODE_ORR = 1100b +THUMB_INSTRUCTION_OPCODE_MUL = 1101b +THUMB_INSTRUCTION_OPCODE_BIC = 1110b +THUMB_INSTRUCTION_OPCODE_MVN = 1111b + +SIMD_REG_LIST_TYPE_REGISTER = 0 ;dy +SIMD_REG_LIST_TYPE_ELEMENT = 1 ;dy[x] +SIMD_REG_LIST_TYPE_VECTOR = 2 ;dy[] + +IT_MODE_AUTO = 1 + +;conditions for choosing 16 bit thumb when two options are available: +; OPs reg,... - always encoded as short unless forced by a condition or explicit IT block +; OP reg,... - default encoded as long. If the preceeding instruction was the same type, +; then if the preceeding instruction was encoded as long we recode it as +; short+short (IT + movs reg1,reg2 i.e. to begin the IT block), or if there +; are still remaining slots available in a previous IT block, then we encode +; this instruction as short (movs reg1,reg2) and extend the previous IT block. + + ;renamed variables in X86_64 +label force_wide_flag dword at address_high +label IT_anchor_distance byte at segment_register + ;renamed variables in preprocessor for our use +label potential_IT_anchor dword at macro_line +label explicit_IT_state dword at macro_block +label current_IT_block dword at macro_block_line +label thumb32_error dword at macro_block_line_number +label thumb16_error dword at macro_symbols +label thumb32_instruction dword at struc_name + arm64_instruction equ thumb32_instruction +label thumb16_instruction word at struc_label +label anchor_instruction word at struc_label+2 +label arm_instruction dword at instant_macro_start + arm64_instruction2 equ arm_instruction +label reg_list_bitmap dword at parameters_end + label simd_reg_list_first byte at parameters_end+0 + label simd_reg_list_count byte at parameters_end+1 + label simd_reg_list_x byte at parameters_end+2 + label simd_reg_list_type byte at parameters_end+3 +label operand_registers dword at locals_counter + label operand_register0 byte at locals_counter+0 + label operand_register1 byte at locals_counter+1 + label operand_register2 byte at locals_counter+2 + label operand_register3 byte at locals_counter+3 + label instruction_condition byte at locals_counter+4 + label instruction_shift_op byte at locals_counter+5 + label copro_opcode1 byte at locals_counter+6 + label copro_opcode2 byte at locals_counter+7 +label cpu_capability_flags2 dword at default_argument_value +label immediate_value_high dword at initial_definitions +label it_control byte at macro_status + ;renamed variables in parser for our use +label immediate_value dword at current_locals_prefix +label immediate_value2 dword at anonymous_reverse + label current_reg_number byte at anonymous_forward+0 + label current_parameter byte at anonymous_forward+1 + label thumb_flags_16 byte at anonymous_forward+2 + label thumb_flags_32 byte at anonymous_forward+3 +label cpu_capability_flags dword at label_hash +label copro_capability_flags dword at label_leaf +label ARM_error_line dword at parsed_lines + ;renamed variables in AVX for our use +label first_global_symbol dword at uncompressed_displacement + ;renamed variables in x64 for our use +label can_swap_rm_rn byte at rex_prefix + +irpv any, esp { + irp reg,ax,bx,cx,dx,si,di,sp,bp \{ v\#reg equ r\#reg \} + __is_64 = 1 +rept 0 {} rept 1 { + irp reg,ax,bx,cx,dx,si,di,sp,bp \{ v\#reg equ e\#reg \} + __is_64 = 0 + ;remove this macro if you want to drop support for processors that don't have CMOVcc + irp cc,a,ae,b,be,c,e,g,ge,l,le,na,nae,nb,nbe,nc,ne,ng,nge,nl,nle,no,np,ns,nz,o,p,pe,po,s,z \{ + local i + macro cmov#cc [args] \\{ + \\common + \\local .x + j#cc .x + load i from $-2 + store (i xor 1) at $-2 + mov args + .x: + \\} + \} +} + +patch_error_displayed = 0 +macro patch labl,instr_search,instr_replace,offset { + local expecting, length, new, a, b + macro display_nibble value \{ + local nibble + nibble=(value) and 0fh + '0' + if nibble > '9' + nibble=nibble - '9' - 1 + 'a' + end if + display nibble + \} + macro display_hex prefix, address, length \{ + display prefix + while % <= length + load a byte from address + % - 1 + display_nibble a shr 4 + display_nibble a + display ' ' + end while + display 13, 10 + \} + virtual at labl + offset + expecting:: + irp i,instr_search\{i\} + length = $ - $$ + end virtual + virtual at labl + offset + new:: + irp i,instr_replace\{i\} + if $ - $$ <= length + times (length + $$ - $) nop + else + if ~ patch_error_displayed + display $ - $$ - length + '0', " too many bytes", 13, 10 + patch_error_displayed = 1 + rb -1 ; "Instruction patch is too long" + end if + end if + end virtual + while % <= length + load a byte from labl + offset + % - 1 + load b byte from expecting:labl + offset + % - 1 + if a <> b + if ~ patch_error_displayed + display_hex '-16: ', labl + offset - 16, 16 + display_hex '+00: ', labl + offset + 00, 16 + display_hex '+16: ', labl + offset + 16, 16 + display_hex 'this ', expecting:labl + offset, length + patch_error_displayed = 1 + rb -1 ; "Mismatched instructions for patch" + end if + end if + end while + while % <= length + load a byte from new:labl + offset + % - 1 + store byte a at labl + offset + % - 1 + end while + purge display_nibble, display_hex +} + +macro override labl, instr { + local new, length, a + virtual at labl + new:: + irp i,instr{i\} + length = $ - $$ + end virtual + while % <= length + load a byte from new:labl + % - 1 + store byte a at labl + % - 1 + end while +} + +;All patches are done here + +;patch to add FIT operator + + patch calculation_loop, , , 123 + __is_64 * 2 + +;patches to add PROCESSOR operator + + patch parse_instruction_arguments,\ + <,je allow_embedded_instruction>,\ + , 0 + patch parse_argument, <,je separator>, , 160 + __is_64 * 2 + patch operator_argument,, , 58 + __is_64 * 8 + patch negation_ok, , , 37 + __is_64 * 8 + +;patches to save IT data inside virtual blocks + + patch addressing_space_extension_ok, , , 60 + __is_64 * 24 + patch continue_virtual_area, , , 182 + __is_64 * 46 + patch end_virtual, , , 0 + +;patch to inhibit IT block generation across labels + + patch assemble_line, , , 35 + __is_64 * 2 + +;two patches to catch the format arguments + + patch parse_instruction_arguments,<>,<>,88 + patch parse_instruction_arguments,<>,<>,95 + +;three patches for ELF format + + patch format_elf, \ + <, \ + , \ + , \ + , \ + , \ + , \ + >, \ + <, \ + , \ + , \ + >, \ + 48 + __is_64 * 3 + patch format_elf, <>, <>, 74 + __is_64 * 10 ;CODE32 + patch format_elf64, \ + <, \ + , \ + , \ + , \ + , \ + , \ + >, \ + <, \ + , \ + , \ + >, \ + 32 + __is_64 * 3 + patch elf_exe_brand_ok, <>, <>, 0 + +;nine patches for PE format + + patch format_pe, <>, <>, 2 ;ARM + patch format_pe, <>, <>, 11 ;WinCE + patch format_pe, <>, <>, 20 ;3.0 + patch format_pe, <>, <>, 30 + patch pe_settings, <>, <>, -19 + patch init_peplus_specific,<>, <>, 4 + __is_64 + patch pe_org_ok, <>, <>, 14 ;CODE32 + patch new_section, <>, <>, 83 + __is_64 * 31 ;CODE32 + patch pe_alignment_ok, <>,\ + <>, 0 + +;three patches to allow {} around register lists and custom address formats + + patch parse_argument, <,je address_argument>, <,je ARM_square_parser>, 99 + __is_64 * 2 + patch parse_argument, <,je open_decorator>, <,je ARM_curly_parser>, 115 + __is_64 * 2 + patch parse_argument, <,je unallowed_character>, <,je separator>, 131 + __is_64 * 2 + +;a patch for setting the alignment bytes to 0xff + + patch nops, <>, <>, 0 + +;patch to give us control when the code stream has finished being assembled + + macro finish_elf_exe_patch_code { mov ebx,[number_of_sections] } + patch finish_elf_segment, finish_elf_exe_patch_code, jmp ARM_finish_elf_segment, 0 + +;patch the reset state at beginning of assembly passes + + patch pass_loop, , , 0 + +;patch to allow alternative half-precision number range + + patch fp_word_ok, , , 8 + +;patch to use a custom instruction searcher to convert '~~' to conditionals + + override get_instruction, jmp ARM_get_instruction + +;patch to allow skipping of commas inside address expressions + + override skip_address, jmp skip_done + +;patch to allow %p and %c predefined variables + + override get_predefined_id, jmp ARM_get_predefined_id ;in PARSER.INC + override predefined_label, jmp ARM_predefined_label ;in EXPRCALC.INC + +;patch to use a custom instruction handler to store address of line start + + override instruction_handler, jmp ARM_instruction_handler + +;patch to disable use of 0x13 as code type setting (this is now a directive) + + patch assemble_line, , , 61 + __is_64 * 2 + +;patches to recognise base address registers in virtual + + patch symbol_value, <>, , 46 + __is_64 * 12 + patch address_size_ok, <,>, , 52 + __is_64 * 5 + +;patch to allow for 17 character symbols + + patch get_symbol, <>,<>,10 + __is_64 * 7 + +;seven patches for the IDE caption + + if defined _caption + + patch convert_table, ,,256 + patch loading_error, ,,26 + patch not_enough_mem, ,,23 + patch move_file_name, ,,76 + patch open_single_file, ,,52 + patch run_object, ,,2 + patch drop_files, ,,102 + + ARM_push_caption: + mov eax,_logo + xchg eax,[esp] + jmp vax + + end if + +;patch the error_summary_dialog to show the full error message by wrapping the text + +macro dialogitem class,title,id,x,y,cx,cy,style,exstyle { + if (style) and SS_LEFTNOWORDWRAP = SS_LEFTNOWORDWRAP ;check for error_summary_dialog message item + dialogitem class,,id,x,y-5,cx,cy+16,(style) and (not SS_LEFTNOWORDWRAP),exstyle + else + dialogitem class,<title>,id,x,y,cx,cy,style,exstyle + end if +} + +;ARM, ARM64, THUMB and THUMB_T2 encodings are sufficiently different that we use separate decoding code for each. +;The basic premise is that we decode all three together as much a possible using the templates. +;We decode the parameters and then split into each separate encoder once basic syntax checks are passed. +;Once split off, specific invalid encodings are checked by each encoder. +; +;In T2 mode, the IT instruction is checked by a common handler function and it is possible that previous +;instructions will be recoded if IT prediction was sub-optimal or invalid. + +;decoder template definitions: + +align 4 + +struc make_template_entry [name] { + common + local counter + counter = 0 + forward + dd decode_template.#name + name = counter + counter = counter + 1 +} + +template_decode_table make_template_entry \ + TMPL_modifier_exclaim ,\;'!' + TMPL_modifier_translate ,\;'^' + TMPL_cpu_sel ,\;cpu32_*, cpu64_* + TMPL_copro_sel ,\;copro32_ + TMPL_copro_opcode1 ,\;imm + TMPL_copro_opcode2 ,\;imm + TMPL_EOL ,\;0xf + TMPL_base_reg ,\;r0-r15 + TMPL_base_reg! ,\;r0!-r15! + TMPL_cpro_sel ,\;p0-p15 + TMPL_cpro_reg ,\;c0-c15 + TMPL_endian ,\;le,be + TMPL_shift_op ,\;lsl,lsr,asr,ror + TMPL_shift_op3 ,\;lsl,lsr,asr + TMPL_rrx_op ,\;rrx + TMPL_lsl ,\;lsl + TMPL_msl ,\;msl + TMPL_vfps_reg ,\;s0-s31 + TMPL_vfpd_reg ,\;d0-d31 + TMPL_acc_40bt ,\;acc0-acc7 + TMPL_vfp_syst ,\;vfp_syst + TMPL_iflags ,\;iflags_* + TMPL_psr ,\;cpsr_*,spsr_* + TMPL_imm ,\;'(' + TMPL_imm2 ,\;'(' + TMPL_imm64 ,\;64-bit immediates + TMPL_bracket_left ,\;'[' + TMPL_bracket_right ,\;']' + TMPL_reg_list ,\;'{..}' + TMPL_vfp_reg_list_s ,\;'{..}' + TMPL_vfp_reg_list_d ,\;'{..}' + TMPL_add_sub_reg ,\;-rm, +rm + TMPL_expression ,\;implicit or explicit reg + offset + TMPL_address ,\;code address immediate + TMPL_address64 ,\;64-bit code address immediate + TMPL_option ,\;{imm} + TMPL_comma ,\;, + TMPL_iwmmx_wreg ,\;wr0-wr15 + TMPL_iwmmx_creg ,\;iwmmx_creg + TMPL_mvrk_areg ,\;a0-a3 + TMPL_mvrk_psc ,\;dspsc + TMPL_fpa_freg ,\;f0-f7 + TMPL_imm_float ,\;float + TMPL_barrier ,\;barrier + TMPL_condition ,\;conditions + TMPL_condition_nv ,\;conditions with nv + TMPL_simd_qreg ,\;q0-q15 + TMPL_vfpdx_reg ,\;d0[x]-d31[x] x=0-7 + TMPL_simd_reg_list ,\;{d0,d1,...}, {d0,d2,...}, {d0[x],d1[x],...}, {d0[x],d2[x],...}, {d0[],d1[],...}, {d0[],d2[],...} + TMPL_address_reg@ ,\;r0@x-r15@x + TMPL_sysm_reg ,\;apsr, iapsr, eapsr, xpsr, ipsr, epsr, iepsr, msp, psp, primask, basepri, basepri_max, faultmask, control + TMPL_banked_reg ,\;banked registers for MSR/MRS access + TMPL_word_z_reg ,\;32-bit w0-w30,wzr + TMPL_word_s_reg ,\;32-bit w0-w30,wsp + TMPL_dword_z_reg ,\;64-bit x0-x30,xzr + TMPL_dword_s_reg ,\;64-bit x0-x30,sp + TMPL_word_gen_reg ,\;32-bit w0-w30 + TMPL_word_zr_reg ,\;32-bit wzr + TMPL_word_sp_reg ,\;32-bit wsp + TMPL_dword_gen_reg ,\;64-bit x0-x30 + TMPL_dword_zr_reg ,\;64-bit xzr + TMPL_dword_sp_reg ,\;64-bit sp + TMPL_vect_breg ,\;b0-b31 + TMPL_vect_hreg ,\;h0-h31 + TMPL_vect_sreg ,\;s0-s31 + TMPL_vect_dreg ,\;d0-d31 + TMPL_vect_qreg ,\;q0-q31 + TMPL_vect_v8b ,\;v0.8b-v31.8b + TMPL_vect_v16b ,\;v0.16b-v31.16b + TMPL_vect_v4h ,\;v0.4h-v31.4h + TMPL_vect_v8h ,\;v0.8h-v31.8h + TMPL_vect_v2s ,\;v0.2s-v31.2s + TMPL_vect_v4s ,\;v0.4s-v31.4s + TMPL_vect_v1d ,\;v0.1d-v31.1d + TMPL_vect_v2d ,\;v0.2d-v31.2d + TMPL_vect_v1q ,\;v0.1q-v31.1q + TMPL_extend ,\;[su]xt[]bhwx] + TMPL_always ,\;always match everything + TMPL_never ,\;never match anything + TMPL_at_op ,\;at ops + TMPL_dc_op ,\;dc ops + TMPL_ic_op ,\;ic ops + TMPL_tlbi_op ,\;tlbi ops + TMPL_prf_op ,\;pldl1keep-pstl3strm + TMPL_msr_reg ,\;msr registers + TMPL_pstate_reg ,\;pstate registers + TMPL_sysreg_dynamic ,\;s<op0>_<op1>_<Cn>_<Cm>_<op2> registers + TMPL_vect_element_b ,\;v0.b[imm]-v31.b[imm] + TMPL_vect_element_h ,\;v0.h[imm]-v31.h[imm] + TMPL_vect_element_s ,\;v0.s[imm]-v31.s[imm] + TMPL_vect_element_d ,\;v0.d[imm]-v31.d[imm] + TMPL_vect_list_8b ,\;{v.8b,...} + TMPL_vect_list_16b ,\;{v.16b,...} + TMPL_vect_list_4h ,\;{v.4h,...} + TMPL_vect_list_8h ,\;{v.8h,...} + TMPL_vect_list_2s ,\;{v.2s,...} + TMPL_vect_list_4s ,\;{v.4s,...} + TMPL_vect_list_1d ,\;{v.1d,...} + TMPL_vect_list_2d ,\;{v.2d,...} + TMPL_vect_list_vb ,\;{v0.b}[imm]-{v31.b}[imm] + TMPL_vect_list_vh ,\;{v0.b}[imm]-{v31.b}[imm] + TMPL_vect_list_vs ,\;{v0.b}[imm]-{v31.b}[imm] + TMPL_vect_list_vd ,\;{v0.b}[imm]-{v31.b}[imm] + TMPL_size_1 ,\;set operand_size to byte + TMPL_size_2 ,\;set operand_size to hword + TMPL_size_4 ,\;set operand_size to word + TMPL_size_8 ,\;set operand_size to dword + TMPL_size_16 ,\;set operand_size to qword + TMPL_size_32 ;set operand_size to dqword + +restruc make_template_entry + +TEMPLATE_maximum_operand= 9 +TEMPLATE_length = TEMPLATE_maximum_operand + +macro TEMPLATE [arg] { + common + local .x,.y + db 0 ;index number of the last template + .x: + forward + .y = $ + irp val,arg \{ + db val + \} + db TMPL_EOL + assert ($-.y) <= TEMPLATE_maximum_operand + while ($-.y) < TEMPLATE_length + db -1 + end while + common + store byte (($-.x)/TEMPLATE_length)-1 at .x-1 +} + +decode_template: + mov [instruction_condition],al + mov [arm_instruction],edx + mov [thumb32_instruction],ecx + call ARM_generic_mode_checks + xor eax,eax + mov [immediate_value_high],eax + mov [instruction_shift_op],al + mov [current_reg_number],al + mov [operand_registers],eax + mov [current_parameter],al + mov [immediate_value2],eax + mov [immediate_value],eax + mov [thumb_flags_16],al + mov [thumb_flags_32],al + mov [copro_opcode1],al + mov [copro_opcode2],al + mov eax,[esp] ;get template definitions + mov ebx,0 ;ebx=current template definition + mov ah,[eax] ;ah=highest constraint + mov al,0 ;al=lowest constriant + .refine_constraint: + .refine_lower_constraint: + movzx ecx,al + imul ecx,ecx,TEMPLATE_length + add ecx,[esp] + lea ecx,[ecx+ebx+1] + movzx ecx,byte[ecx] ;ecx=template value + movzx eax,ax ;clear the multi-match mask + push ebx ecx esi eax + call near dword[template_decode_table+ecx*4] + pop eax edx ecx ebx + jnc .lower_constraint_found + mov esi,edx + .try_next_constraint: + inc al + cmp al,ah + ja .failed + movzx edx,al + imul edx,edx,TEMPLATE_length + add edx,[esp] + lea edx,[edx+ebx+1] + cmp cl,[edx] + jz .try_next_constraint + jmp .refine_lower_constraint + .lower_constraint_found: + test eax,0xffff0000 + setnz ch + or cl,ch ;mask off similar matches + .refine_higher_constraint: + movzx edx,ah + imul edx,edx,TEMPLATE_length + add edx,[esp] + lea edx,[edx+ebx+1] + mov ch,[edx] + test eax,0xffff0000 + setnz dl + or ch,dl ;mask off similar matches + cmp cl,ch + jz .higher_constraint_found + dec ah + cmp ah,al + jb .failed + jmp .refine_higher_constraint + .higher_constraint_found: + .next_parameter: + cmp cl,TMPL_EOL + jz .end_of_line + inc bl + cmp bl,TEMPLATE_maximum_operand + jb .refine_constraint + cmp byte[esi],0xf ;end of line? + jne .extra_characters_on_line + .end_of_line: + cmp ah,al + jnz .amibguous_definition + .finish: + ;return al=matched template ordinal + mov ecx,[esp] ;get template definitions + movzx ebx,byte[ecx] + imul ebx,ebx,TEMPLATE_length + lea ebx,[ebx+ecx+1+TEMPLATE_length] + mov [esp],ebx + test [code_type],CPU_ACTIVITY_ARM64 + jnz .ret + ;create a default instruction for ARM + mov ebp,[arm_instruction] + mov cl,[instruction_condition] + and cl,0xf0 + shl ecx,24 + or ebp,ecx + mov ecx,ebp + or ecx,1 shl 20 ;set the S bit + test [instruction_condition],FLAG_CONDITION_SET + cmovnz ebp,ecx + mov [arm_instruction],ebp + .ret: + ret + .unexpected_end_of_line: + jmp ERROR_unexpected_end_of_line + .extra_characters_on_line: + jmp extra_characters_on_line + .amibguous_definition: + .failed: + cmp [current_parameter],0 + jz ERROR_parameter_n_not_valid.first + cmp [current_parameter],1 + jz ERROR_parameter_n_not_valid.second + cmp [current_parameter],2 + jz ERROR_parameter_n_not_valid.third + cmp [current_parameter],3 + jz ERROR_parameter_n_not_valid.fourth + cmp [current_parameter],4 + jz ERROR_parameter_n_not_valid.fifth + cmp [current_parameter],5 + jz ERROR_parameter_n_not_valid.sixth + jmp ERROR_parameter_n_not_valid.all + .skip_comma: + mov al,[esi] + cmp al,0xf ;end of line? + jz .TMPL_okay + cmp al,0x0 ;end of source? + jz .TMPL_okay + cmp al,']' + jz .TMPL_okay + inc esi + cmp al,',' + jnz .expecting_comma + cmp byte[esi],0xf ;end of line? + jz .unexpected_end_of_line + cmp byte[esi],0x0 ;end of source? + jz .unexpected_end_of_line + .TMPL_always: + .TMPL_okay: + clc + retn + .expecting_comma: + .TMPL_never: + .TMPL_not_matched: + stc + retn + .TMPL_modifier_exclaim: + cmp word[esi],(modifier + 0) shr 8 + ((modifier + 0) and 0xff) shl 8 + jnz .TMPL_not_matched + add esi,2 + jmp .TMPL_okay + .TMPL_modifier_translate: + cmp word[esi],(modifier + 1) shr 8 + ((modifier + 1) and 0xff) shl 8 + jnz .TMPL_not_matched + add esi,2 + jmp .TMPL_okay + .TMPL_copro_opcode1: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [copro_opcode1],al + inc [current_parameter] + cmp eax,0xf + ja .TMPL_out_of_range + test edx,edx + jnz .TMPL_out_of_range + test byte[edi+13],1 ;check sign + jz .skip_comma + .TMPL_out_of_range: + mov ecx,ERROR_value_out_of_range + call ARM_defer_error + jmp .skip_comma + .TMPL_copro_opcode2: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [copro_opcode2],al + inc [current_parameter] + cmp eax,0x7 + ja .TMPL_out_of_range + test edx,edx + jnz .TMPL_out_of_range + test byte[edi+13],1 ;check sign + jz .skip_comma + jmp .TMPL_out_of_range + .TMPL_EOL: + cmp byte[esi],0xf ;end of line? + jz .TMPL_okay + cmp byte[esi],0x0 ;end of source? + jz .TMPL_okay + jmp .TMPL_not_matched + .TMPL_reg_decoder: + lodsw + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + shr edx,16 + cmp ax,dx + jae .TMPL_not_matched + cmp byte[esi],'(' + jz .TMPL_not_matched + .TMPL_put_reg: + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],al + inc [current_reg_number] + inc [current_parameter] + jmp .skip_comma + .TMPL_base_reg: + mov edx,base_reg + base_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_base_reg!: + mov edx,base_reg! + base_reg!.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_cpro_sel: + mov edx,cpro_sel + cpro_sel.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_cpro_reg: + mov edx,cpro_reg + cpro_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_fpa_freg: + mov edx,fpa_freg + fpa_freg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_barrier: + mov edx,barrier + barrier.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_condition_nv: + mov edx,condition + condition.size shl 16 + jmp .TMPL_condition.do + .TMPL_condition: + mov edx,condition + (condition.size-1) shl 16 ;exclude NV + .TMPL_condition.do: + cmp word[esi],(endian + 0) shr 8 + ((endian + 0) and 0xff) shl 8 ;special value for overlap with LE + mov al,0xd + jz .TMPL_condition.found2 + cmp byte[esi],0xf0 ;special value for overlap with EQ + mov al,0x0 + jz .TMPL_condition.found1 + jmp .TMPL_reg_decoder + .TMPL_condition.found2: + inc esi + .TMPL_condition.found1: + inc esi + jmp .TMPL_put_reg + .TMPL_shift_op: + lodsw + xchg ah,al + sub ax,shift_op + jb .TMPL_not_matched + cmp ax,shift_op.size + jae .TMPL_not_matched + mov [instruction_shift_op],al + jmp .TMPL_okay + .TMPL_shift_op3: + lodsw + xchg ah,al + sub ax,shift_op + jb .TMPL_not_matched + cmp ax,shift_op.size-1 ;ror not allowed + jae .TMPL_not_matched + mov [instruction_shift_op],al + jmp .TMPL_okay + .TMPL_vfpdx_reg: + cmp word[esi+2],'[(' + jnz .TMPL_not_matched + lodsd + xchg ah,al + sub ax,vfpd_reg + jb .TMPL_not_matched + cmp ax,vfpd_reg.size + jae .TMPL_not_matched + push eax + call ARM_calculate_expression + pop eax + cmp byte[esi],']' + jnz .TMPL_not_matched + cmp word[edi+10],0 ;mult2, mult1 + jnz .TMPL_not_matched + ;double and shift high bit to LSb + add al,al + mov ah,al + shr al,5 + and ax,0x1e01 + or ah,al + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],ah + inc [current_reg_number] + inc esi + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + inc [current_parameter] + cmp eax,0x7 + ja .TMPL_out_of_range + test edx,edx + jnz .TMPL_out_of_range + test byte[edi+13],1 ;check sign + jnz .TMPL_out_of_range + jmp .skip_comma + .TMPL_vfps_reg: + mov edx,vfps_reg + vfps_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vfpd_reg: + lodsw + xchg ah,al + sub ax,vfpd_reg + jb .TMPL_not_matched + cmp ax,vfpd_reg.size + jae .TMPL_not_matched + .TMPL_vfpd_reg.do: + ;double and shift high bit to LSb + add al,al + mov ah,al + shr al,5 + and ax,0x1e01 + or ah,al + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],ah + inc [current_reg_number] + inc [current_parameter] + jmp .skip_comma + .TMPL_simd_qreg: + lodsw + xchg ah,al + sub ax,simd_qreg + jb .TMPL_not_matched + cmp ax,simd_qreg.size + jae .TMPL_not_matched + add al,al + jmp .TMPL_vfpd_reg.do + .TMPL_vect_breg: + mov edx,vect_breg + vect_breg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_hreg: + mov edx,vect_hreg + vect_hreg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_sreg: + mov edx,vect_sreg + vect_sreg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_dreg: + mov edx,vect_dreg + vect_dreg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_qreg: + mov edx,vect_qreg + vect_qreg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v8b: + mov edx,vect_v8b + vect_v8b.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v16b: + mov edx,vect_v16b + vect_v16b.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v4h: + mov edx,vect_v4h + vect_v4h.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v8h: + mov edx,vect_v8h + vect_v8h.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v2s: + mov edx,vect_v2s + vect_v2s.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v4s: + mov edx,vect_v4s + vect_v4s.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v1d: + mov edx,vect_v1d + vect_v1d.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v2d: + mov edx,vect_v2d + vect_v2d.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vect_v1q: + mov edx,vect_v1q + vect_v1q.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_vfp_syst: + mov edx,vfp_syst + vfp_syst.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_acc_40bt: + mov edx,acc_40bt + acc_40bt.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_endian: + mov edx,endian + endian.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_iflags: + mov edx,iflags + iflags.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_psr: + mov edx,psr_reg + psr_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_iwmmx_wreg: + mov edx,iwmmx_wreg + iwmmx_wreg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_iwmmx_creg: + mov edx,iwmmx_creg + iwmmx_creg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_address: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + cmp byte[edx+1],'.' ;float? + jz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + inc [current_parameter] + movzx ecx,byte[edi+13] ;sign bit + and ecx,1 + or ecx,edx + jz .TMPL_okay + cdq + cmp edx,[edi+4] + jnz .TMPL_address.out_of_range + xor dl,[edi+13] ;check sign + test dl,1 + jz .TMPL_okay + jmp .TMPL_address.out_of_range + .TMPL_address64: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + cmp byte[edx+1],'.' ;float? + jz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + mov [immediate_value_high],edx + inc [current_parameter] + movzx ecx,byte[edi+13] ;sign bit + and ecx,1 + jz .TMPL_okay + test edx,edx + js .TMPL_okay + .TMPL_address.out_of_range: + mov ecx,ERROR_value_out_of_range + call ARM_defer_error + jmp .TMPL_okay + .TMPL_imm_float: + mov eax,[esi] + cmp ax,'(.' + jz .TMPL_imm + and eax,0x00ffffff + cmp eax,'#(.' + jz .TMPL_imm + jmp .TMPL_not_matched + .TMPL_imm2: + mov ecx,immediate_value2 + jmp .TMPL_imm.do + .TMPL_imm: + mov ecx,immediate_value + .TMPL_imm.do: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + push esi ecx + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop ecx esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [ecx],eax + inc [current_parameter] + movzx ecx,byte[edi+13] ;sign bit + and ecx,1 + or ecx,edx + jz .TMPL_okay + cdq + cmp edx,[edi+4] + jnz .TMPL_imm.out_of_range + xor dl,[edi+13] ;check sign + test dl,1 + jz .TMPL_okay + jmp .TMPL_imm.out_of_range + .TMPL_imm64: + cmp byte[esi],'#' + setz dl + movzx edx,dl + add edx,esi + cmp byte[edx],'(' + jnz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + mov [immediate_value_high],edx + inc [current_parameter] + movzx ecx,byte[edi+13] ;sign bit + and ecx,1 + jz .TMPL_okay + test edx,edx + js .TMPL_okay + .TMPL_imm.out_of_range: + mov ecx,ERROR_value_out_of_range + call ARM_defer_error + jmp .TMPL_okay + .TMPL_bracket_left: + mov [operand_flags],0 + mov edx,esi + mov cx,[edx] + xchg ch,cl + sub cx,size_opr + jb .no_size_operator + cmp cx,size_opr.size + jae .no_size_operator + cmp cl,[operand_size] + jnz ERROR_operand_sizes_do_not_match + add edx,2 + mov [operand_flags],1 + .no_size_operator: + cmp byte[edx],'[' + jnz .TMPL_not_matched + inc edx + mov esi,edx + jmp .TMPL_okay + .TMPL_bracket_right: + cmp byte[esi],']' + jnz .TMPL_not_matched + inc esi + cmp word[esi],(modifier + 0) shr 8 + ((modifier + 0) and 0xff) shl 8 + jnz .skip_comma + jmp .TMPL_okay + .TMPL_simd_reg_list: + cmp byte[esi],0x91 + jnz .TMPL_not_matched + inc esi + lodsw + xchg ah,al + sub ax,vfpd_reg + jb .TMPL_not_matched + cmp ax,vfpd_reg.size + jae .TMPL_not_matched + mov [simd_reg_list_first],al + mov [simd_reg_list_count],1 + mov [simd_reg_list_x],0 + mov [simd_reg_list_type],SIMD_REG_LIST_TYPE_REGISTER + cmp byte[esi],0x92 + jz .TMPL_simd_reg_list.done + cmp word[esi],'[]' + jz .TMPL_simd_reg_list.vector + cmp word[esi],'[(' + jz .TMPL_simd_reg_list.element + .TMPL_simd_reg_list.check_next: + cmp byte[esi],0x92 + jz .TMPL_simd_reg_list.done + cmp byte[esi],',' + jnz .TMPL_not_matched + inc esi + lodsw + xchg ah,al + sub ax,vfpd_reg + jb .TMPL_not_matched + cmp ax,vfpd_reg.size + jae .TMPL_not_matched + inc [simd_reg_list_count] + cmp [simd_reg_list_count],2 ;second reg sets the separation + jnz .TMPL_simd_reg_list.check_separation + sub al,[simd_reg_list_first] + dec al + test al,not 1 + jnz .TMPL_not_matched + and al,1 + ror al,1 + or [simd_reg_list_count],al + jmp .TMPL_simd_reg_list.separation_okay + .TMPL_simd_reg_list.check_separation: + mov ah,[simd_reg_list_first] + mov cl,[simd_reg_list_count] + mov ch,cl + and ch,0x7f + sub al,ah + rol cl,1 + and cl,1 + shr al,cl + jc .TMPL_not_matched + inc al + cmp al,ch + jnz .TMPL_not_matched + .TMPL_simd_reg_list.separation_okay: + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + jz .TMPL_simd_reg_list.check_vector + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + jz .TMPL_simd_reg_list.check_element + jmp .TMPL_simd_reg_list.check_next + .TMPL_simd_reg_list.check_vector: + cmp word[esi],'[]' + jnz .TMPL_not_matched + add esi,2 + jmp .TMPL_simd_reg_list.check_next + .TMPL_simd_reg_list.check_element: + cmp word[esi],'[(' + jnz .TMPL_not_matched + add esi,2 + call ARM_calculate_expression + cmp word[edi+10],0 ;mult2, mult1 + jnz .TMPL_not_matched + mov eax,[edi] + mov edx,[edi+4] + test edx,edx + jnz .TMPL_not_matched + test byte[edi+13],1 ;check sign + jnz .TMPL_not_matched + cmp eax,7 + ja .TMPL_not_matched + cmp [simd_reg_list_x],al + jnz .TMPL_not_matched + lodsb + cmp al,']' + jnz .TMPL_not_matched + jmp .TMPL_simd_reg_list.check_next + .TMPL_simd_reg_list.vector: + mov [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + add esi,2 + jmp .TMPL_simd_reg_list.check_next + .TMPL_simd_reg_list.element: + mov [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + add esi,2 + call ARM_calculate_expression + cmp word[edi+8],0 ;reg2, reg1 + jnz .TMPL_not_matched + mov eax,[edi] + mov edx,[edi+4] + test edx,edx + jnz .TMPL_not_matched + test byte[edi+13],1 ;check sign + jnz .TMPL_not_matched + cmp eax,7 + ja .TMPL_not_matched + mov [simd_reg_list_x],al + lodsb + cmp al,']' + jnz .TMPL_not_matched + jmp .TMPL_simd_reg_list.check_next + .TMPL_simd_reg_list.done: + inc esi + inc [current_parameter] + jmp .skip_comma + .TMPL_vfp_reg_list_s: + mov edx,vfps_reg + vfps_reg.size shl 16 + jmp .TMPL_reg_list.decode + .TMPL_vfp_reg_list_d: + mov edx,vfpd_reg + vfpd_reg.size shl 16 + jmp .TMPL_reg_list.decode + .TMPL_reg_list: + mov edx,base_reg + base_reg.size shl 16 + .TMPL_reg_list.decode: + cmp byte[esi],0x91 + jnz .TMPL_not_matched + mov [reg_list_bitmap],0 + .TMPL_reg_list.next: + inc esi + cmp byte[esi],0x92 + jz .TMPL_reg_list.done + lodsw + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + cmp ax,dx + jae .TMPL_not_matched + ror edx,16 + movzx ecx,al + bts [reg_list_bitmap],ecx + jc ERROR_repeated_register_in_list + cmp byte[esi],0x92 + jz .TMPL_reg_list.done + cmp byte[esi],',' + jz .TMPL_reg_list.next + cmp byte[esi],'-' + jnz .TMPL_not_matched + inc esi + lodsw + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + cmp ax,dx + jae .TMPL_not_matched + ror edx,16 + movzx ebx,al + btr [reg_list_bitmap],ecx + cmp ecx,ebx + je ERROR_repeated_register_in_list + jg .TMPL_reg_list.range_next + xchg ecx,ebx + .TMPL_reg_list.range_next: + bts [reg_list_bitmap],ecx + jc ERROR_repeated_register_in_list + dec ecx + cmp ecx,ebx + jge .TMPL_reg_list.range_next + cmp byte[esi],',' + jz .TMPL_reg_list.next + cmp byte[esi],0x92 + jnz .TMPL_not_matched + .TMPL_reg_list.done: + inc esi + cmp [reg_list_bitmap],0 + jz ERROR_empty_set + inc [current_parameter] + jmp .TMPL_okay + .TMPL_rrx_op: + cmp word[esi],rrx_op shr 8 + (rrx_op and 0xff) shl 8 + jnz .TMPL_not_matched + add esi,2 + inc [current_parameter] + jmp .TMPL_okay + .TMPL_sysm_reg: + mov ax,word[esi] + xchg ah,al + cmp ax,psr_reg+34 + jz .TMPL_sysm_reg.apsr + mov edx,sysm_reg + sysm_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_sysm_reg.apsr: + mov al,0 + add esi,2 + jmp .TMPL_put_reg + .TMPL_banked_reg: + mov edx,banked_reg + banked_reg.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_mvrk_areg: + mov ax,word[esi] + xchg ah,al + cmp ax,mvrk_areg + jnz .TMPL_mvrk_areg_a1_a3 + sub ax,mvrk_areg + jz .TMPL_mvrk_areg_a0 + .TMPL_mvrk_areg_a1_a3: + sub ax,base_reg + jb .TMPL_not_matched + cmp ax,2 + ja .TMPL_not_matched + inc al + .TMPL_mvrk_areg_a0: + add esi,2 + jmp .TMPL_put_reg + .TMPL_mvrk_psc: + cmp word[esi],mvrk_psc shr 8 + (mvrk_psc and 0xff) shl 8 + jnz .TMPL_not_matched + add esi,2 + inc [current_parameter] + jmp .skip_comma + .TMPL_add_sub_reg: + mov cl,0 + cmp byte[esi],'-' + jnz .TMPL_add_reg + mov cl,0x80 + inc esi + .TMPL_add_reg: + mov ax,[esi] + xchg ah,al + sub ax,base_reg + jb .TMPL_reg_in_expression + cmp ax,base_reg.size + jae .TMPL_reg_in_expression + add esi,2 + or al,cl + jmp .TMPL_put_reg + .TMPL_reg_in_expression: + lodsb + cmp al,'(' + jnz .TMPL_not_matched + lodsw + xchg ah,al + sub ax,base_reg + jb .TMPL_not_matched + cmp ax,base_reg.size + jae .TMPL_not_matched + cmp byte[esi],')' + jz .TMPL_reg_in_expression.add_reg + cmp word[esi],')' shl 8 + 0x83 ;unary minus? + jnz .TMPL_not_matched + or al,0x80 + inc esi + .TMPL_reg_in_expression.add_reg: + inc esi + jmp .TMPL_put_reg + .TMPL_address_reg@: + lodsw + xchg ah,al + mov edx,base_reg + (0*16) shl 16 + cmp ax,base_reg + jb @f + cmp ax,base_reg + base_reg.size + jb .TMPL_address_reg@.make + @@: mov edx,base_@16 + (1*16) shl 16 + cmp ax,base_@16 + jb @f + cmp ax,base_@16 + base_@16.size + jb .TMPL_address_reg@.make + @@: mov edx,base_@32 + (2*16) shl 16 + cmp ax,base_@32 + jb @f + cmp ax,base_@32 + base_@32.size + jb .TMPL_address_reg@.make + @@: mov edx,base_@64 + (3*16) shl 16 + cmp ax,base_@64 + jb @f + cmp ax,base_@64 + base_@64.size + jb .TMPL_address_reg@.make + @@: mov edx,base_@128 + (4*16) shl 16 + cmp ax,base_@128 + jb @f + cmp ax,base_@128 + base_@128.size + jb .TMPL_address_reg@.make + @@: mov edx,base_@256 + (5*16) shl 16 + cmp ax,base_@256 + jb .TMPL_not_matched + cmp ax,base_@256 + base_@256.size + jae .TMPL_not_matched + .TMPL_address_reg@.make: + sub ax,dx + shr edx,16 + add al,dl + jmp .TMPL_put_reg + .TMPL_expression: + xor edx,edx + cmp byte[esi],'(' + jz .TMPL_expression.start_okay + cmp byte[esi],0x10 + jnz .TMPL_not_matched + cmp byte[esi+2],'(' + jnz .TMPL_not_matched + lodsw + mov dl,ah + add edx,0x10000 + .TMPL_expression.start_okay: + push esi edx + inc esi + call ARM_calculate_expression + pop eax edx + xchg esi,edx + mov ecx,[edi+8] ;mult2, mult1, reg2, reg1 + add ecx,eax + cmp ecx,0xffff + jbe .TMPL_not_matched + xor ecx,0x00010000 + cmp ecx,0xff + ja .TMPL_invalid_expression.too_complex + test [code_type],CPU_ACTIVITY_ARM64 + jnz .TMPL_expression.64 + sub cl,base_reg - 0x1000 + jb .TMPL_invalid_expression.not_base + cmp cl,base_reg.size + jae .TMPL_invalid_expression.not_base + jmp .TMPL_expression.set_reg + .TMPL_expression.64: + cmp cl,dword_reg + 31 - 0x1000 ;xzr not allowed + je .TMPL_invalid_expression.not_base64 + mov al,dword_reg + 31 - 0x1000 + cmp cl,base_reg + 13 - 0x1000 ;sp? + cmovz ecx,eax + sub cl,dword_reg - 0x1000 + jb .TMPL_invalid_expression.not_base64 + cmp cl,dword_reg.size + jae .TMPL_invalid_expression.not_base64 + .TMPL_expression.set_reg: + xchg esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + movzx ebx,[current_reg_number] + mov [operand_register0+ebx],cl + inc [current_reg_number] + inc [current_parameter] + movzx ecx,byte[edi+13] ;sign bit + and ecx,1 + or ecx,edx + jz .TMPL_okay + cdq + cmp edx,[edi+4] + jnz .TMPL_expression.out_of_range + xor dl,[edi+13] ;check sign + test dl,1 + jz .TMPL_okay + .TMPL_expression.out_of_range: + mov ecx,ERROR_value_out_of_range + call ARM_defer_error + jmp .TMPL_okay + .TMPL_invalid_expression.too_complex: + jmp ERROR_register_out_of_range.too_complex + .TMPL_invalid_expression.not_base: + jmp ERROR_register_out_of_range.only_base + .TMPL_invalid_expression.not_base64: + jmp ERROR_register_out_of_range.only_base64 + .TMPL_option: + cmp byte[esi],0x91 + jnz .TMPL_not_matched + cmp byte[esi+1],'#' + setz dl + movzx edx,dl + lea edx,[esi+edx+1] + cmp byte[edx],'(' + jnz .TMPL_not_matched + push esi + lea esi,[edx+1] + call ARM_calculate_expression + mov edx,esi + pop esi + cmp word[edi+10],0 ;mult2, mult1 + jnz .TMPL_not_matched + inc edx + cmp byte[edx-1],0x92 + jnz .TMPL_not_matched + mov esi,edx + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + inc [current_parameter] + test edx,edx + jnz .TMPL_option.out_of_range + test byte[edi+13],1 ;check sign + jz .TMPL_okay + .TMPL_option.out_of_range: + mov ecx,ERROR_value_out_of_range + call ARM_defer_error + jmp .TMPL_okay + .TMPL_comma: + cmp byte[esi],',' + jnz .TMPL_not_matched + inc esi + jmp .TMPL_okay + .TMPL_word_z_reg: + assert TMPL_word_z_reg and not 1 = TMPL_word_s_reg and not 1 + lodsw + xchg ah,al + sub ax,word_reg + jb .TMPL_not_matched + cmp ax,word_reg.size - 2 + ja .TMPL_not_matched ;wsp not allowed + setnz cl ;wzr? + or [esp+6 + __is_64 * 4],cl + jmp .TMPL_put_reg + .TMPL_word_s_reg: + assert TMPL_word_z_reg and not 1 = TMPL_word_s_reg and not 1 + lodsw + xchg ah,al + sub ax,word_reg + jb .TMPL_not_matched + cmp ax,word_reg.size + jae .TMPL_not_matched + cmp al,word_reg.size - 2 + jz .TMPL_not_matched ;wzr not allowed + seta cl ;wsp? + sub al,cl + or [esp+6 + __is_64 * 4],cl + jmp .TMPL_put_reg + .TMPL_dword_z_reg: + assert TMPL_dword_z_reg and not 1 = TMPL_dword_s_reg and not 1 + lodsw + xchg ah,al + sub ax,dword_reg + jb .TMPL_not_matched + cmp ax,dword_reg.size - 1 + ja .TMPL_not_matched + setnz cl ;wzr? + or [esp+6 + __is_64 * 4],cl + jmp .TMPL_put_reg + .TMPL_dword_s_reg: + assert TMPL_dword_z_reg and not 1 = TMPL_dword_s_reg and not 1 + lodsw + xchg ah,al + cmp ax,base_reg + 13 ;sp? + jz .TMPL_dword_s_reg.sp + sub ax,dword_reg + jb .TMPL_not_matched + cmp ax,dword_reg.size - 1 + jae .TMPL_not_matched ;xzr not allowed + jmp .TMPL_put_reg + .TMPL_dword_s_reg.sp: + or byte[esp+6 + __is_64 * 4],1 + mov al,0x1f + jmp .TMPL_put_reg + .TMPL_word_gen_reg: + mov edx,word_reg + (word_reg.size - 2) shl 16 + jmp .TMPL_reg_decoder + .TMPL_word_zr_reg: + lodsw + cmp ax,(word_reg + word_reg.size - 2) shr 8 + ((word_reg + word_reg.size - 2) and 0xff) shl 8 + jnz .TMPL_not_matched + mov al,0x1f + jmp .TMPL_put_reg + .TMPL_word_sp_reg: + lodsw + cmp ax,(word_reg + word_reg.size - 1) shr 8 + ((word_reg + word_reg.size - 1) and 0xff) shl 8 + jnz .TMPL_not_matched + mov al,0x1f + jmp .TMPL_put_reg + .TMPL_dword_gen_reg: + mov edx,dword_reg + (dword_reg.size - 1) shl 16 + jmp .TMPL_reg_decoder + .TMPL_prf_op: + mov edx,prf_op + prf_op.size shl 16 + jmp .TMPL_reg_decoder + .TMPL_dword_zr_reg: + lodsw + cmp ax,(dword_reg + dword_reg.size - 1) shr 8 + ((dword_reg + dword_reg.size - 1) and 0xff) shl 8 + jnz .TMPL_not_matched + mov al,0x1f + jmp .TMPL_put_reg + .TMPL_dword_sp_reg: + lodsw + cmp ax,(base_reg+13) shr 8 + ((base_reg+13) and 0xff) shl 8 + jnz .TMPL_not_matched + mov al,0x1f + jmp .TMPL_put_reg + .TMPL_extend: + lodsw + xchg ah,al + sub ax,xtnd_op + jb .TMPL_not_matched + cmp ax,xtnd_op.size + jae .TMPL_not_matched + mov [instruction_shift_op],al + jmp .TMPL_okay + .TMPL_lsl: + lodsw + cmp ax,(shift_op+0) shr 8 + ((shift_op+0) and 0xff) shl 8 + jnz .TMPL_not_matched + mov [instruction_shift_op],0 + jmp .TMPL_okay + .TMPL_at_op: + lodsw + xchg ah,al + sub ax,sys_at + jb .TMPL_not_matched + cmp ax,sys_at.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_dc_op: + lodsw + xchg ah,al + sub ax,sys_dc + jb .TMPL_not_matched + cmp ax,sys_dc.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_ic_op: + lodsw + xchg ah,al + sub ax,sys_ic + jb .TMPL_not_matched + cmp ax,sys_ic.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_tlbi_op: + lodsw + xchg ah,al + sub ax,sys_tlbi + jb .TMPL_not_matched + cmp ax,sys_tlbi.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_msr_reg: + lodsw + xchg ah,al + cmp ax,banked_reg+32+20 ;spsr_abt? + mov cx,sys_msr+(sys_encode_spsr_abt-sys_encode_table_msr) shr 1 + cmovz eax,ecx + cmp ax,banked_reg+32+14 ;spsr_fiq? + mov cx,sys_msr+(sys_encode_spsr_fiq-sys_encode_table_msr) shr 1 + cmovz eax,ecx + cmp ax,banked_reg+32+16 ;spsr_irq? + mov cx,sys_msr+(sys_encode_spsr_irq-sys_encode_table_msr) shr 1 + cmovz eax,ecx + cmp ax,banked_reg+32+22 ;spsr_und? + mov cx,sys_msr+(sys_encode_spsr_und-sys_encode_table_msr) shr 1 + cmovz eax,ecx + sub ax,sys_msr + jb .TMPL_not_matched + cmp ax,sys_msr.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_pstate_reg: + lodsw + xchg ah,al + sub ax,sys_pstate + jb .TMPL_not_matched + cmp ax,sys_pstate.size + jae .TMPL_not_matched + movzx eax,ax + mov [immediate_value],eax + inc [current_parameter] + jmp .skip_comma + .TMPL_sysreg_dynamic: + lodsw + cmp ax,'(' + 0x11 shl 8 + jnz .TMPL_not_matched + lodsd + cmp byte[esi],')' + jnz .TMPL_not_matched + inc esi + xor edx,edx + mov ebx,[eax+0x18] + ;S<op0>_<op1>_<Cn>_<Cm>_<op2> + mov cl,[ebx] + inc ebx + cmp cl,'s' + jz .TMPL_sysreg_dynamic.start_okay + cmp cl,'S' + jnz .TMPL_not_matched + .TMPL_sysreg_dynamic.start_okay: + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,3 + ja .TMPL_not_matched + cmp cl,2 + jb .TMPL_not_matched + or edx,ecx + cmp byte[ebx],'_' + jnz .TMPL_not_matched + inc ebx + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,7 + ja .TMPL_not_matched + shl edx,3 + or edx,ecx + cmp word[ebx],'_c' + jz .TMPL_sysreg_dynamic.first_reg_okay + cmp word[ebx],'_C' + jnz .TMPL_not_matched + .TMPL_sysreg_dynamic.first_reg_okay: + inc ebx + inc ebx + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,9 + ja .TMPL_not_matched + cmp byte[ebx],'_' + jz .TMPL_sysreg_dynamic.place_first_reg + cmp cl,1 + jnz .TMPL_not_matched + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,5 + ja .TMPL_not_matched + add cl,10 + .TMPL_sysreg_dynamic.place_first_reg: + shl edx,4 + or edx,ecx + cmp word[ebx],'_c' + jz .TMPL_sysreg_dynamic.second_reg_okay + cmp word[ebx],'_C' + jnz .TMPL_not_matched + .TMPL_sysreg_dynamic.second_reg_okay: + inc ebx + inc ebx + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,9 + ja .TMPL_not_matched + cmp byte[ebx],'_' + jz .TMPL_sysreg_dynamic.place_second_reg + cmp cl,1 + jnz .TMPL_not_matched + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,5 + ja .TMPL_not_matched + add cl,10 + .TMPL_sysreg_dynamic.place_second_reg: + shl edx,4 + or edx,ecx + cmp byte[ebx],'_' + jnz .TMPL_not_matched + inc ebx + movzx ecx,byte[ebx] + inc ebx + sub cl,'0' + jb .TMPL_not_matched + cmp cl,7 + ja .TMPL_not_matched + shl edx,3 + or edx,ecx + cmp byte[ebx],',' + jz .TMPL_sysreg_dynamic.create + cmp byte[ebx],0 + jnz .TMPL_not_matched + .TMPL_sysreg_dynamic.create: + mov [immediate_value],edx + mov cx,[current_pass] + xchg [eax+16],cx + mov edx,[current_line] + mov [eax+28],edx + or byte[eax+8],1+2 + jmp .skip_comma + .TMPL_vect_element_b: + mov edx,vect_vb + vect_vb.size shl 16 + 15 shl 24 + jmp .TMPL_vect_element + .TMPL_vect_element_h: + mov edx,vect_vh + vect_vh.size shl 16 + 7 shl 24 + jmp .TMPL_vect_element + .TMPL_vect_element_s: + mov edx,vect_vs + vect_vs.size shl 16 + 3 shl 24 + jmp .TMPL_vect_element + .TMPL_vect_element_d: + mov edx,vect_vd + vect_vd.size shl 16 + 1 shl 24 + .TMPL_vect_element: + cmp word[esi+2],'[(' + jnz .TMPL_not_matched + lodsd + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + movzx cx,dl + cmp ax,cx + jae .TMPL_not_matched + push eax edx + call ARM_calculate_expression + pop ebx eax + cmp byte[esi],']' + jnz .TMPL_not_matched + cmp word[edi+10],0 ;mult2, mult1 + jnz .TMPL_not_matched + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],al + inc [current_reg_number] + inc esi + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,immediate_value + mov edx,immediate_value2 + test ecx,ecx + cmovnz eax,edx + mov ecx,[edi] + mov edx,[edi+4] + mov [eax],ecx + inc [current_parameter] + movzx ebx,bh + cmp ecx,ebx + ja .TMPL_out_of_range + test edx,edx + jnz .TMPL_out_of_range + test byte[edi+13],1 ;check sign + jnz .TMPL_out_of_range + jmp .skip_comma + .TMPL_vect_list_8b: + mov edx,vect_v8b + vect_v8b.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_16b: + mov edx,vect_v16b + vect_v16b.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_4h: + mov edx,vect_v4h + vect_v4h.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_8h: + mov edx,vect_v8h + vect_v8h.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_2s: + mov edx,vect_v2s + vect_v2s.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_4s: + mov edx,vect_v4s + vect_v4s.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_1d: + mov edx,vect_v1d + vect_v1d.size shl 16 + jmp .TMPL_vect_list + .TMPL_vect_list_2d: + mov edx,vect_v2d + vect_v2d.size shl 16 + .TMPL_vect_list: + lodsb + cmp al,0x91 + jnz .TMPL_not_matched + mov [simd_reg_list_count],0 + .TMPL_vect_list.next: + cmp byte[esi],0x92 + jz .TMPL_vect_list.done + lodsw + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + cmp ax,dx + jae .TMPL_not_matched + ror edx,16 + movzx eax,al + movzx ecx,[simd_reg_list_count] + test ecx,ecx + jnz .TMPL_vect_list.check_increment + mov [simd_reg_list_first],al + jmp .TMPL_vect_list.advance + .TMPL_vect_list.check_increment: + mov ebx,ecx + add bl,[simd_reg_list_first] + and bl,0x1f + cmp bl,al + jnz .TMPL_not_matched + .TMPL_vect_list.advance: + inc cl + mov [simd_reg_list_count],cl + lodsb + cmp al,',' + jz .TMPL_vect_list.next + cmp al,0x92 + jnz .TMPL_not_matched + .TMPL_vect_list.done: + cmp [simd_reg_list_count],0 + jz ERROR_empty_set + cmp [simd_reg_list_count],4 + ja .TMPL_not_matched + mov bl,[simd_reg_list_first] + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],bl + inc [current_reg_number] + inc [current_parameter] + jmp .skip_comma + .TMPL_vect_list_vb: + mov edx,vect_vb + vect_vb.size shl 16 + 15 shl 24 + jmp .TMPL_vect_list_v + .TMPL_vect_list_vh: + mov edx,vect_vh + vect_vh.size shl 16 + 7 shl 24 + jmp .TMPL_vect_list_v + .TMPL_vect_list_vs: + mov edx,vect_vs + vect_vs.size shl 16 + 3 shl 24 + jmp .TMPL_vect_list_v + .TMPL_vect_list_vd: + mov edx,vect_vd + vect_vd.size shl 16 + 1 shl 24 + .TMPL_vect_list_v: + lodsb + cmp al,0x91 + jnz .TMPL_not_matched + mov [simd_reg_list_count],0 + .TMPL_vect_list_v.next: + cmp byte[esi],0x92 + jz .TMPL_vect_list_v.done + lodsw + xchg ah,al + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + movzx cx,dl + cmp ax,cx + jae .TMPL_not_matched + ror edx,16 + movzx eax,al + movzx ecx,[simd_reg_list_count] + test ecx,ecx + jnz .TMPL_vect_list_v.check_increment + mov [simd_reg_list_first],al + jmp .TMPL_vect_list_v.advance + .TMPL_vect_list_v.check_increment: + mov ebx,ecx + add bl,[simd_reg_list_first] + and bl,0x1f + cmp bl,al + jnz .TMPL_not_matched + .TMPL_vect_list_v.advance: + inc cl + mov [simd_reg_list_count],cl + lodsb + cmp al,',' + jz .TMPL_vect_list_v.next + cmp al,0x92 + jnz .TMPL_not_matched + .TMPL_vect_list_v.done: + cmp [simd_reg_list_count],0 + jz ERROR_empty_set + cmp [simd_reg_list_count],4 + ja .TMPL_not_matched + lodsw + cmp ax,'[(' + jnz .TMPL_not_matched + push edx + call ARM_calculate_expression + pop ebx + lodsb + cmp al,']' + jnz .TMPL_not_matched + cmp word[edi+10],0 ;mult2, mult1 + jnz .TMPL_not_matched + mov bl,[simd_reg_list_first] + movzx ecx,[current_reg_number] + mov [operand_register0+ecx],bl + inc [current_reg_number] + mov eax,[edi+16] + mov [symbol_identifier],eax + mov al,[edi+12] + mov [value_type],al + mov eax,immediate_value + mov edx,immediate_value2 + test ecx,ecx + cmovnz eax,edx + mov ecx,[edi] + mov edx,[edi+4] + mov [eax],ecx + inc [current_parameter] + shr ebx,24 + cmp ecx,ebx + ja .TMPL_out_of_range + test edx,edx + jnz .TMPL_out_of_range + test byte[edi+13],1 ;check sign + jnz .TMPL_out_of_range + jmp .skip_comma + .TMPL_msl: + cmp word[esi],msl_op shr 8 + (msl_op and 0xff) shl 8 + jnz .TMPL_not_matched + add esi,2 + inc [current_parameter] + jmp .TMPL_okay + .TMPL_cpu_sel: + mov ecx,[cpu_capability_flags] + mov ebx,[cpu_capability_flags2] + mov edx,cpu_sel + cpu_sel.size shl 16 + jmp .TMPL_processor_selection + .TMPL_copro_sel: + mov ecx,[copro_capability_flags] + xor ebx,ebx + mov edx,copro_sel + copro_sel.size shl 16 + .TMPL_processor_selection: + cmp byte[esi],'-' + jz .TMPL_processor_selection.accumulate + cmp byte[esi],'+' + jz .TMPL_processor_selection.accumulate + ;start from scratch + xor ecx,ecx + xor ebx,ebx + .TMPL_processor_selection.accumulate: + xor eax,eax + cmp byte[esi],'+' + jz .TMPL_processor_selection.increment + cmp byte[esi],'-' + jnz .TMPL_processor_selection.next + or eax,-1 + .TMPL_processor_selection.increment: + inc esi + .TMPL_processor_selection.next: + lodsw + xchg ah,al + cmp ax,cpu_sel.all32 + jz .TMPL_processor_selection.cpu_sel.all32 + cmp ax,cpu_sel.all64 + jz .TMPL_processor_selection.cpu_sel.all64 + cmp ax,copro_sel.all + jz .TMPL_processor_selection.copro_sel.all + sub ax,dx + jb .TMPL_not_matched + ror edx,16 + cmp ax,dx + jae .TMPL_not_matched + ror edx,16 + cmp al,32 + jb @f + xchg ecx,ebx + @@: bts ecx,eax + test eax,eax + jns @f + btr ecx,eax + @@: cmp al,32 + jb .TMPL_processor_selection.advance + xchg ecx,ebx + .TMPL_processor_selection.advance: + mov al,[esi] + cmp al,'+' + jz .TMPL_processor_selection.accumulate + cmp al,'-' + jz .TMPL_processor_selection.accumulate + mov [immediate_value],ecx + mov [immediate_value_high],ebx + inc [current_parameter] + jmp .TMPL_okay + .TMPL_processor_selection.cpu_sel.all32: + cmp dx,cpu_sel + jnz .TMPL_not_matched + or ecx,CPU32_CAPABILITY_ALL and (1 shl 32 - 1) + or ebx,CPU32_CAPABILITY_ALL shr 32 + test eax,eax + jns .TMPL_processor_selection.advance + and ecx,not (CPU32_CAPABILITY_ALL and (1 shl 32 - 1)) + and ebx,not (CPU32_CAPABILITY_ALL shr 32) + jmp .TMPL_processor_selection.advance + .TMPL_processor_selection.cpu_sel.all64: + cmp dx,cpu_sel + jnz .TMPL_not_matched + or ecx,CPU64_CAPABILITY_ALL and (1 shl 32 - 1) + or ebx,CPU64_CAPABILITY_ALL shr 32 + test eax,eax + jns .TMPL_processor_selection.advance + and ecx,not (CPU64_CAPABILITY_ALL and (1 shl 32 - 1)) + and ebx,not (CPU64_CAPABILITY_ALL shr 32) + jmp .TMPL_processor_selection.advance + .TMPL_processor_selection.copro_sel.all: + cmp dx,copro_sel + jnz .TMPL_not_matched + or ecx,COPRO_CAPABILITY_ALL + test eax,eax + jns .TMPL_processor_selection.advance + and ecx,not COPRO_CAPABILITY_ALL + jmp .TMPL_processor_selection.advance + .TMPL_size_1: + mov [operand_size],1 + jmp .TMPL_okay + .TMPL_size_2: + mov [operand_size],2 + jmp .TMPL_okay + .TMPL_size_4: + mov [operand_size],4 + jmp .TMPL_okay + .TMPL_size_8: + mov [operand_size],8 + jmp .TMPL_okay + .TMPL_size_16: + mov [operand_size],16 + jmp .TMPL_okay + .TMPL_size_32: + mov [operand_size],32 + jmp .TMPL_okay + +ARM_code16_directive: + call ARM_generic_mode_checks + cmp [explicit_IT_state],0 + jnz ERROR_mode_change_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + mov [code_type],CPU_ACTIVITY_THUMB_NON_UAL + jmp instruction_assembled + +ARM_thumb_directive: + call ARM_generic_mode_checks + cmp [explicit_IT_state],0 + jnz ERROR_mode_change_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + mov [code_type],CPU_ACTIVITY_THUMB_UAL + jmp instruction_assembled + +ARM_itauto_directive: + or [it_control],IT_MODE_AUTO + xor eax,eax + mov [current_IT_block],eax + mov [potential_IT_anchor],eax + jmp instruction_assembled +ARM_itnoauto_directive: + and [it_control],not IT_MODE_AUTO + xor eax,eax + mov [current_IT_block],eax + jmp instruction_assembled + +ARM_thumbee_directive: + call ARM_generic_mode_checks + cmp [explicit_IT_state],0 + jnz ERROR_mode_change_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + mov [code_type],CPU_ACTIVITY_THUMB_UAL + CPU_ACTIVITY_THUMBEE + jmp instruction_assembled + +ARM_code32_directive: + call ARM_generic_mode_checks + cmp [explicit_IT_state],0 + jnz ERROR_mode_change_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + mov [code_type],CPU_ACTIVITY_ARM + jmp instruction_assembled + +ARM_code64_directive: + call ARM_generic_mode_checks + cmp [explicit_IT_state],0 + jnz ERROR_mode_change_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + mov [code_type],CPU_ACTIVITY_ARM64 + jmp instruction_assembled + +ARM_coprocessor_directive: + call decode_template + TEMPLATE \ + <TMPL_imm>,\ ;0=imm + <TMPL_copro_sel> ;1=imm + mov ecx,[immediate_value] + cmp al,1 + je .selected + and ecx,COPRO_CAPABILITY_DEFAULT + .selected: + mov [copro_capability_flags],ecx + jmp instruction_assembled + +ARM_processor_directive: + call decode_template + TEMPLATE \ + <TMPL_imm>,\ ;0=imm + <TMPL_cpu_sel> ;1=imm + mov ecx,[immediate_value] + mov edx,[immediate_value_high] + cmp al,1 + je .selected + and ecx,CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1) + and edx,CPU_CAPABILITY_DEFAULT shr 32 + .selected: + mov [cpu_capability_flags],ecx + mov [cpu_capability_flags2],edx + jmp instruction_assembled + +ARM_format_directive: + cmp dword[esi],05018h + 0c019h shl 16 ;"elf dwarf" + jnz format_directive + cmp word[esi+4],01d19h ;"executable" + jnz format_directive + cmp edi,[code_start] + jne unexpected_instruction + mov edx,[addressing_space] + test byte [edx+0Ah],1 + jne unexpected_instruction + cmp [output_format],0 + jne unexpected_instruction + mov [format_flags],5 ;set to DWARF(4) + executable(1) + mov [output_format],5 ;set to ELF + mov edx,edi + mov ecx,34h shr 2 + lea eax,[edi+ecx*4] + cmp eax,[tagged_blocks] + jae out_of_memory + xor eax,eax + rep stosd + mov dword[edx],7fh + 'ELF' shl 8 + mov al,1 + mov [edx+4],al + mov [edx+5],al + mov [edx+6],al + mov byte[edx+10h],2 ;e_type + mov byte[edx+12h],40 ;machine type ARM + mov [edx+14h],al ;e_version + mov dword[edx+024h],02000016h ;e_flags + mov byte[edx+28h],34h ;e_ehsize + mov byte[edx+2ah],20h ;e_phentsize + mov byte[edx+2eh],28h ;e_shentsize + mov [code_type],ARM_code + add esi,6 + mov [image_base],0 + cmp byte[esi],80h + jne .base_ok + lodsw + cmp ah,'(' + jne invalid_argument + cmp byte[esi],'.' + je invalid_value + push edx + call get_dword_value + cmp [value_type],0 + jne invalid_use_of_symbol + mov [image_base],eax + pop edx + .base_ok: + mov ebx,edi + mov ecx,20h shr 2 + cmp [current_pass],0 + je .init_sections + imul ecx,[number_of_sections] + .init_sections: + xor eax,eax + rep stosd + mov [number_of_sections],0 + mov ecx,edi + sub ecx,[code_start] + mov eax,[image_base] + mov byte[ebx],1 ;p_type + mov [ebx+4],ecx ;file offset + mov [ebx+8],eax ;p_vaddr + mov [ebx+0ch],eax ;p_paddr + mov byte[ebx+18h],7 ;p_flags + mov word[ebx+1ch],20h ;p_align + mov [edx+18h],eax ;e_entry + or edx,-1 + mov cl,-1 + not eax + add eax,1 + adc edx,0 + adc cl,0 + add eax,edi + adc edx,0 + mov ebx,[addressing_space] + movzx ecx,cl + mov [ebx+0x00],eax + mov [ebx+0x04],edx + mov [ebx+0x08],ecx + mov dword[ebx+0x10],0 + mov dword[ebx+0x14],0 + mov [ebx+0x18],edi + mov dword[ebx+0x1c],0 + mov [symbols_stream],edi + jmp instruction_assembled + +ARM_section_directive: + cmp [output_format],5 + jnz section_directive + test [format_flags],4 + jz section_directive + mov eax,[addressing_space] + test byte[eax+0x0a],1 + jne illegal_instruction + ;first we close the current section + cmp [number_of_sections],0 + jz .first_section + call ARM_finish_elf_segment + jmp .next_section + .first_section: + cmp edi,[symbols_stream] ;has some code already been emitted? + jnz ERROR_code_is_not_in_a_section + mov eax,[image_base] + .next_section: + push eax + mov ebx,[number_of_sections] + shl ebx,5 + add ebx,[code_start] + add ebx,34h + cmp ebx,[symbols_stream] + jb .new_section_okay + mov ebx,[symbols_stream] + sub ebx,20h + mov [next_pass_needed],-1 + .new_section_okay: + push edi + mov edi,ebx + mov ecx,20h shr 2 + xor eax,eax + rep stosd + pop edi + pop ecx + mov eax,edi + sub eax,[code_start] + mov [ebx+04h],eax ;p_offset + mov [ebx+08h],ecx ;p_vaddr + mov dword[ebx+0ch],0 ;p_paddr + lodsw + cmp ax,'(' + jne ERROR_expecting_section_name + mov [ebx],esi ;we use p_type to temporarily store the string offset + mov ecx,[esi] + lea esi,[esi+4+ecx+1] + .next_attribute: + cmp byte[esi],8Ch + jz .section_alignment + cmp byte[esi],80h + jz .section_at + cmp byte[esi],19h + jnz .section_attributes_done + lodsw + sub ah,28 + jbe invalid_argument + cmp ah,1 + je .set_flag + cmp ah,3 + ja invalid_argument + xor ah,1 + cmp ah,2 + je .set_flag + inc ah + .set_flag: ;at least one flag required + test [ebx+18h],ah + jnz ERROR_duplicate_flag_setting + or [ebx+18h],ah + jmp .next_attribute + .section_alignment: ;required + inc esi + lodsb + cmp al,'(' + jne invalid_argument + cmp byte[esi],'.' + je invalid_value + push ebx + call get_dword_value + pop ebx + cmp [value_type],0 + jne ERROR_invalid_use_of_symbol_in_align + mov edx,eax + dec edx + test eax,edx + jnz invalid_value + test eax,eax + jz invalid_value + xchg [ebx+1ch],eax ;p_align + test eax,eax + jnz ERROR_duplicate_align_setting + jmp .next_attribute + .section_at: ;optional + lodsw + cmp ah,'(' + jne invalid_argument + cmp byte[esi],'.' + je invalid_value + push ebx + call get_dword_value + pop ebx + cmp [value_type],0 + jne ERROR_invalid_use_of_symbol_in_at + mov [ebx+0ch],eax ;p_paddr + or dword[ebx+018h],1 shl 31 + jmp .next_attribute + .section_attributes_done: + test byte[ebx+018h],-1 ;p_flags + jz ERROR_section_flags_zero + mov ecx,[ebx+01ch] ;p_align + sub ecx,1 + js ERROR_section_align_zero + test dword[ebx+018h],1 shl 31 + jz .no_at_specified + and dword[ebx+018h],not (1 shl 31) + mov eax,[ebx+0ch] ;p_paddr + test eax,ecx + jnz ERROR_section_at_not_aligned + jmp .finish + .no_at_specified: + mov eax,[ebx+08h] ;p_vaddr + add eax,ecx + not ecx + and eax,ecx + mov [ebx+0ch],eax ;p_paddr + .finish: + mov [ebx+08h],eax ;p_vaddr + or edx,-1 + mov cl,-1 + neg eax + cmc + adc edx,0 + adc cl,0 + add eax,edi + adc edx,0 + adc cl,0 + push eax ecx edx + call create_addressing_space + pop edx ecx eax + mov ebx,[addressing_space] + mov [ebx+0x00],eax + mov [ebx+0x04],edx + mov [ebx+0x08],cl + inc [number_of_sections] + jmp instruction_assembled + +ARM_finish_elf_segment: + ;called by close_elf after the last line is assembled + ;we must patch it to properly close the last section + cmp [output_format],5 + jnz .not_my_format + test [format_flags],4 + jz .not_my_format + mov eax,[code_start] + mov ecx,[eax] + cmp ecx,7fh + 'ELF' shl 8 + jnz .done + mov ebx,[number_of_sections] + dec ebx + shl ebx,5 + lea ebx,[ebx+eax+0x34] + cmp ebx,[symbols_stream] + jb .exe_section_ok + mov ebx,[symbols_stream] + sub ebx,20h + .exe_section_ok: + mov edx,edi ;edx=the original data end + mov eax,edi + mov ecx,[addressing_space] + sub eax,[ecx+0x18] ;length of code in this section + mov ecx,[ebx+01ch] ;align + sub ecx,1 + jc .align_done + and eax,ecx + jz .align_done + not eax + lea eax,[eax+ecx+2] + add eax,edi + cmp eax,[tagged_blocks] + jae out_of_memory + xor ecx,ecx + .align: + mov dword[edi],ecx + add edi,4 + cmp edi,eax + jb .align + mov edi,eax ;edi=the aligned data end + .align_done: + mov eax,edi + sub eax,[code_start] ;offset into file position of emitted code on disk + sub eax,[ebx+4] ;length code in this section + cmp edx,[undefined_data_end] + jne .size_ok + mov edi,[undefined_data_start] + mov dword[edi],0 + mov ecx,[addressing_space] + sub edi,[ecx+0x00] ;length of initialised code in this section + add edi,3 + and edi,not 3 + add edi,[ecx+0x00] + .size_ok: + mov [ebx+14h],eax ;p_memsz + mov eax,edi + sub eax,[code_start] ;offset into file position of emitted code on disk + sub eax,[ebx+4] ;length code in this section + mov [ebx+10h],eax ;p_filesz + mov eax,[ebx+8] ;p_vaddr + add eax,[ebx+14h] ;p_memsz + ;return eax = desired p_vaddr for next section + .done: + ret + .not_my_format: + mov ebx,[code_start] + mov dword[ebx+024h],0202h ;e_flags + .patch_start: + finish_elf_exe_patch_code + jmp finish_elf_segment+($-.patch_start) + +ARM_sections_added=7 + +ARM_close_dwarf: +;this is called after the assembler has finished + cmp [output_format],3 ;pe + jz ARM_close_pe + cmp [output_format],5 ;elf + jnz .ret + test [format_flags],4 + jz .ret + mov ebx,[code_start] + mov eax,edi + sub eax,ebx + mov [ebx+020h],eax ;e_shoff + movzx eax,word[ebx+02ch] ;e_phmnum + add eax,ARM_sections_added ;we add some sections + mov [ebx+30h],ax ;e_shnum + lea ecx,[eax*8] + sub vsp,vcx + mov vbp,vsp + ;build the .shstrtab table + mov edx,edi + sub edx,[code_start] + mov [vbp+vax*8+4-ARM_sections_added*8],edx + xor al,al + stosb + xor ecx,ecx + .next_code_section: + cmp cx,[ebx+02ch] ;e_phmnum + jae .code_section_names_done + mov edx,ecx + shl edx,5 + add edx,[ebx+01ch] ;e_phoff + add edx,[code_start] + mov eax,1 + xchg eax,[edx] ;p_type + cmp eax,1 + jnz .code_section_name_found + mov eax,ARM_string_noname_section + .code_section_name_found: + mov edx,[edx+04h] ;p_offset + mov [vbp+vcx*8+4],edx + call .add_string_to_shstrtab + add ecx,1 + jmp .next_code_section + .code_section_names_done: + lea eax,[ecx+1] + mov word[ebx+032h],ax ;e_shstrndx + mov eax,ARM_string_shstrtab + call .add_string_to_shstrtab + add ecx,1 + mov eax,ARM_string_debug_abbrev + call .add_string_to_shstrtab + add ecx,1 + mov eax,ARM_string_debug_info + call .add_string_to_shstrtab + add ecx,1 + mov eax,ARM_string_debug_line + call .add_string_to_shstrtab + add ecx,1 + mov eax,ARM_string_symtab + call .add_string_to_shstrtab + add ecx,1 + mov eax,ARM_string_strtab + call .add_string_to_shstrtab + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + add edi,[code_start] + sub ecx,ARM_sections_added-3 + ;build the .debug_abbrev table + mov edx,edi + sub edx,[code_start] + mov [vbp+vcx*8+4],edx + mov esi,ARM_data_debug_abbrev + mov edx,ecx + mov ecx,ARM_data_debug_abbrev_len + lea eax,[edi+ecx+010h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + add edi,[code_start] + lea ecx,[edx+1] + ;build the .debug_info table + mov edx,edi + sub edx,[code_start] + mov [vbp+vcx*8+4],edx + mov esi,ARM_data_debug_info + mov edx,ecx + mov ecx,ARM_data_debug_info_len + lea eax,[edi+ecx+010h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + call .get_top_level_file_name + mov ecx,esi + test byte[esi],-1 + jz .top_level_file_done + .top_level_file_loop: + add esi,1 + test byte[esi],-1 + jnz .top_level_file_loop + .top_level_file_done: + sub esi,ecx + xchg esi,ecx + lea eax,[edi+ecx+010h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + xor al,al + stosb + mov esi,ARM_data_debug_producer + mov ecx,ARM_data_debug_producer_len + lea eax,[edi+ecx+020h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + mov eax,[image_base] + stosd ;low_pc + mov eax,-1 + stosd ;high_pc + xor eax,eax + stosd ;stmt_list + stosb + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + mov eax,edi + lea ecx,[edx+1] + sub eax,[vbp+vcx*8+4-8] + add edi,[code_start] + lea edx,[eax-4] + neg eax + mov [edi+eax],edx + ;build the .debug_line table + mov edx,edi + sub edx,[code_start] + mov [vbp+vcx*8+4],edx + push ecx + mov esi,ARM_data_debug_line_prologue + mov ecx,ARM_data_debug_line_prologue_len + lea eax,[edi+ecx+010h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + PUSH vbp + call ARM_debug_add_file_names + POP vbp + mov eax,[esp] + mov eax,[vbp+vax*8+4] + add eax,[code_start] + mov ebx,edi + sub ebx,eax + sub ebx,10 + mov [eax+6],ebx + PUSH vbp + call ARM_debug_add_line_info + POP vbp + pop ecx + sub edi,[code_start] + mov eax,edi + add ecx,1 + sub eax,[vbp+vcx*8+4-8] + add edi,[code_start] + lea edx,[eax-4] + neg eax + mov [edi+eax],edx + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + add edi,[code_start] + ;build the .symtab table + mov edx,edi + sub edx,[code_start] + mov [vbp+vcx*8+4],edx + push ecx + PUSH vbp + lea eax,[edi+20h] + cmp eax,[tagged_blocks] + jae out_of_memory + xor eax,eax + stosd + stosd + stosd + stosd + call ARM_make_code_identifier_table + mov edx,edi + sub edx,[code_start] + mov [first_global_symbol],edx + call ARM_make_symbol_symtab + POP vbp + pop ecx + mov edx,[first_global_symbol] + sub edx,[vbp+vcx*8+4] + mov [first_global_symbol],edx + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + add edi,[code_start] + add ecx,1 + ;build the .strtab table + mov edx,edi + sub edx,[code_start] + mov [vbp+vcx*8+4],edx + push ecx + call ARM_make_symbol_strtab + pop ecx + mov dword[edi],0 + sub edi,[code_start] + add edi,3 + and edi,not 3 + add edi,[code_start] + add ecx,1 + mov ebx,[code_start] + mov edx,edi + sub edx,ebx + mov [vbp+vcx*8+4],edx + mov [ebx+020h],edx ;e_shoff + ;zero the new section headers + movzx ecx,word[ebx+30h] ;e_shnum + imul ecx,28h shr 2 + lea edx,[ecx*4-28h] ;skip the null section header + lea eax,[edi+ecx+10h] + cmp eax,[tagged_blocks] + jae out_of_memory + xor eax,eax + rep stosd + sub edi,edx + ;place_the code section headers + xor ecx,ecx + .next_code_placement: + cmp cx,[ebx+02ch] ;e_phmnum + jae .code_section_placement_done + mov edx,ecx + shl edx,5 + add edx,[ebx+01ch] ;e_phoff + add edx,[code_start] + mov eax,[vbp+vcx*8] + mov [edi+00h],eax ;sh_name + mov byte[edi+04h],1 ;sh_type + mov eax,[edx+018h] ;p_flags + test al,2 ;test write flag + setnz ah + and al,1 + shl al,2 + or al,ah + or al,2 + movzx eax,al + mov [edi+08h],eax ;sh_flags + mov eax,[edx+08h] ;p_vaddr + mov [edi+0ch],eax ;sh_addr + mov eax,[edx+04h] ;p_offset + mov [edi+010h],eax ;sh_offset + mov eax,[edx+010h] ;p_filesz + mov [edi+014h],eax ;sh_size + mov eax,[edx+01ch] ;p_align + mov [edi+020h],eax ;sh_addralign + add edi,028h + add ecx,1 + jmp .next_code_placement + .code_section_placement_done: + ;place the .shstrtab section header + mov dl,3 + call .make_section_header + ;place the .debug_abbrev section header + mov dl,1 + call .make_section_header + ;place the .debug_info section header + mov dl,1 + call .make_section_header + ;place the .debug_line section header + mov dl,1 + call .make_section_header + ;place the .symtab section header + mov dl,2 + call .make_section_header + mov edx,[first_global_symbol] + lea eax,[ecx+1] ;index to the next section (.strtab) + mov [edi-28h+018h],eax ;sh_link + shr edx,4 + mov [edi-28h+01ch],edx ;sh_info + mov byte[edi-28h+020h],04h ;sh_addralign + mov byte[edi-28h+024h],10h ;sh_size + ;place the .strtab section header + mov dl,3 + call .make_section_header + .done: + movzx eax,word[ebx+02ch] ;e_phmnum + add eax,ARM_sections_added + lea vsp,[vbp+vax*8] + .ret: + ret + .add_string_to_shstrtab: + ;ecx=section number + ;eax=pointer to string + push ecx + mov edx,edi + sub edx,[code_start] + sub edx,[ebx+020h] ;s_shoff + mov [vbp+vcx*8],edx ;store the string offset + mov ecx,[eax] + lea esi,[edi+ecx+010h] + cmp esi,[tagged_blocks] + jae out_of_memory + lea esi,[eax+4] + rep movsb + xor al,al + stosb + pop ecx + ret + .make_section_header: + mov eax,[vbp+vcx*8] + mov [edi+00h],eax ;sh_name + mov [edi+04h],dl ;sh_type + mov eax,[vbp+vcx*8+4] + mov dword[edi+010h],eax ;sh_offset + sub eax,[vbp+vcx*8+4+8] + neg eax + mov [edi+014h],eax ;sh_size + add edi,028h + add ecx,1 + ret + .get_top_level_file_name: + mov esi,[source_start] + mov esi,[esi+1] + mov esi,[esi] + ret + +ARM_close_pe: + mov ebx,[code_start] ;ebx points to PE header + ;calculate size of code + movzx eax,word[ebx+0x14] + lea edx,[ebx+eax+0x18] ;edx points to section headers + xor eax,eax + xor ecx,ecx + cmp cx,[ebx+6] + jae .code_size_known + .code_size_loop: + test dword[edx+0x24],0x20 + jz .next_code_section + add eax,[edx+0x10] + cmp dword[ebx+0x18+20],0 + jnz .next_code_section + mov esi,[edx+0xc] ;get virtual address + mov [ebx+0x18+20],esi ;update base of code + .next_code_section: + add edx,0x28 + inc ecx + cmp cx,[ebx+6] + jb .code_size_loop + .code_size_known: + mov [ebx+0x18+4],eax ;update the size of code + ;calculate size of initialised data + movzx eax,word[ebx+0x14] + lea edx,[ebx+eax+0x18] ;edx points to section headers + xor eax,eax + xor ecx,ecx + cmp cx,[ebx+6] + jae .initialised_size_known + .initialised_size_loop: + test dword[edx+0x24],0x40 + jz .next_initialised_section + add eax,[edx+0x10] + cmp dword[ebx+0x18+24],0 + jnz .next_initialised_section + mov esi,[edx+0xc] ;get virtual address + mov [ebx+0x18+24],esi ;update base of data + .next_initialised_section: + add edx,0x28 + inc ecx + cmp cx,[ebx+6] + jb .initialised_size_loop + .initialised_size_known: + mov [ebx+0x18+8],eax ;update the size of initialised data + ;calculate size of uninitialised data + movzx eax,word[ebx+0x14] + lea edx,[ebx+eax+0x18] ;edx points to section headers + xor eax,eax + xor ecx,ecx + cmp cx,[ebx+6] + jae .uninitialised_size_known + .uninitialised_size_loop: + test dword[edx+0x24],0x80 + jz .next_uninitialised_section + add eax,[edx+0x8] + sub eax,[edx+0x10] + .next_uninitialised_section: + add edx,0x28 + inc ecx + cmp cx,[ebx+6] + jb .uninitialised_size_loop + .uninitialised_size_known: + mov [ebx+0x18+12],eax ;update the size of uninitialised data + ;update relocs stripped flag + cmp dword[ebx+0x78+5*8+4],0 + jz .checksum + and word[ebx+0x16],not 1 + .checksum: + mov ecx,0x10 + mov dword[ebx+0x58],0 + jmp directory_ok ;recompute checksum and return + +ARM_start_line_processing: + add edi,0fh + and edi,not 0fh + cmp edi,[tagged_blocks] + jae out_of_memory + mov eax,[labels_list] + mov [tagged_blocks],eax + mov eax,[additional_memory] + mov [free_additional_memory],eax + mov eax,[additional_memory_end] + mov [structures_buffer],eax + mov esi,[source_start] + mov [code_start],edi + xor eax,eax + mov dword [adjustment],eax + mov dword [adjustment+4],eax + mov [addressing_space],eax + mov [error_line],eax + mov [counter],eax + mov [format_flags],eax + mov [number_of_relocations],eax + mov [undefined_data_end],eax + mov [file_extension],eax + mov [next_pass_needed],al + mov [output_format],al + mov [adjustment_sign],al + mov [code_type],ARM_code + call init_addressing_space + inc [current_pass] + mov ax,[current_pass] + cmp ax,[passes_limit] + je code_cannot_be_generated + ret + +ARM_debug_add_file_names: + ;file names are compared by string and not address, + ;this is because it is possible to include a file more than once, + ;then we would have duplicated entries in the table + push [code_start] + push edi + call ARM_start_line_processing + mov vbp,vsp + .neg1 = -1 + push .neg1 ;-4 total files + push [input_file] + .line_loop: + cmp byte[esi],0Fh + jne .next_line + call .find_source_line + mov eax,[eax] + mov ebx,[vbp-4] + test ebx,ebx + jz .add_file + .file_loop: + if __is_64 + movsxd rbx,ebx + end if + mov ecx,[vbp-4+vbx*4] + cmp eax,ecx + jz .next_line + .char_loop: + mov dl,[eax] + mov dh,[ecx] + add eax,1 + add ecx,1 + cmp dh,dl + jnz .next_file + test dl,dl + jnz .char_loop + jmp .next_line + .next_file: + call .find_source_line + mov eax,[eax] + add ebx,1 + jnz .file_loop + .add_file: + mov ebx,[vbp-4] + sub ebx,1 + mov [vbp-4],ebx + call .find_source_line + mov eax,[eax] + push eax + .next_line: + PUSH vbp + call assemble_line + POP vbp + jnc .line_loop + mov edi,[vbp] + xor edx,edx + cmp edx,[vbp-4] + jle .done + .copy_loop: + mov esi,[vbp-8+vdx*4] + mov ecx,[input_file] + cmp ecx,esi + jnz .not_top_level_source + test byte[esi],-1 + jz .top_level_file_done + .top_level_file_loop: + add esi,1 + test byte[esi],-1 + jnz .top_level_file_loop + .top_level_file_done: + sub esi,ecx + xchg esi,ecx + jmp .copy + .not_top_level_source: + movzx ecx,byte[esi-1] + sub ecx,1 + jns .copy + mov ecx,dword[esi-4] + .copy: + lea eax,[edi+ecx+010h] + cmp eax,[tagged_blocks] + jae out_of_memory + rep movsb + xor eax,eax + stosd + sub edx,1 + cmp edx,[vbp-4] + jg .copy_loop + .done: + xor al,al + stosb + mov [vbp],edi + mov vsp,vbp + cmp [number_of_sections],0 + jnz .section_count_okay + inc [number_of_sections] + .section_count_okay: + pop edi + pop [code_start] + .ret: + ret + .find_source_line: + mov eax,[esi+1] + .next_source_link: + test byte[eax+7],0x80 + jz .ret + mov eax,[eax+12] + jmp .next_source_link + +ARM_debug_add_line_info: + mov ecx,[code_start] + mov ecx,[ecx+0x38] + .16k = 16 shl 10 + push .16k ;+20 initial buffer size + push edi ;+16 start of line data + push ecx ;+12 offset to first program byte + push [code_start] ;+8 real generated code + push edi ;+4 current output position for line data + add eax,ARM_data_debug_line_prologue_len + push eax ;+0 file name buffer + mov vbp,vsp + .restart: + add edi,[vbp+20] + lea eax,[edi+0x20] + cmp eax,[tagged_blocks] + jae out_of_memory + call ARM_start_line_processing + push 1 ;-4 state machine file number + push 1 ;-8 state machine line number + push 0 ;-12 state machine address offset + push 0 ;-16 address before assembly + push 0 ;-20 address after assembly + push 0 ;-24 source line before assembly + .line_loop: + cmp byte[esi],0x0f + jne .skip_line + mov ecx,[addressing_space] + test byte[ecx+0x0a],1 + jnz .skip_line + mov ecx,[ecx+0x00] + sub ecx,edi + neg ecx + mov [vbp-16],ecx + mov [vbp-24],esi + PUSH vbp + call assemble_line + POP vbp + jc .close + mov ecx,[addressing_space] + test byte[ecx+0x0a],1 + jnz .line_loop + mov ecx,[ecx+0x00] + sub ecx,edi + neg ecx + mov [vbp-20],ecx + call .emit_line_data + jmp .line_loop + .skip_line: + PUSH vbp + call assemble_line + POP vbp + jnc .line_loop + .close: + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + sub eax,[vbp-12] ;current + call .pc_far + mov al,0 ;extended opcode + call .write_line_code + mov al,1 ;one byte + call .write_line_code + mov al,1 ;end sequence + call .write_line_code + mov eax,[vbp+4] + cmp eax,[code_start] + jbe .close_okay + mov edi,[vbp+16] + sub eax,edi + mov [vbp+4],edi + add eax,0x100 + mov [vbp+20],eax ;adjust the buffer size + mov vsp,vbp + jmp .restart + .close_okay: + lea vsp,[vbp+4] + cmp [number_of_sections],0 + jnz .section_count_okay + inc [number_of_sections] + .section_count_okay: + pop edi + pop [code_start] + add esp,12 + ret + .emit_line_data: + mov eax,[vbp+4] + lea eax,[eax+20h] + cmp eax,[tagged_blocks] + jae out_of_memory + mov eax,edi + sub eax,[code_start] + cmp eax,[vbp+12] ;any output yet? + jb .ret + mov eax,[vbp-20] + cmp eax,[vbp-16] + je .ret + call .update_file + call .update_address + jmp .update_line + .update_file: + mov edx,1 shl 16 ;start at file number 1 + mov ecx,[vbp] + .file_loop: + call .find_source_line + mov eax,[eax+0] ;file name + .char_loop: + mov dl,[eax] + mov dh,[ecx] + add eax,1 + add ecx,1 + cmp dh,dl + jnz .next_file + test dl,dl + jnz .char_loop + jmp .found_file + .next_file: + add edx,1 shl 16 ;bump to next file + test dh,dh + jz .skip_null + .skip_loop: + add ecx,1 + mov dh,[ecx] + test dh,dh + jnz .skip_loop + .skip_null: + add ecx,4 + cmp byte[ecx],0 + jnz .file_loop + jmp ERROR_line_processing_error + .found_file: + shr edx,16 + cmp edx,[vbp-4] + jz .ret + ;set a new file + mov [vbp-4],edx + mov al,4 ;opcode 4: set file + call .write_line_code + jmp .emit_leb128 + .update_address: + mov eax,[vbp-16] ;before + sub eax,[vbp-12] ;current + cmp eax,40 + jbe .ret + cmp eax,80 + ja .pc_far + add dword[vbp-12],40 + push eax + mov al,8 ;opcode 8: const add pc + call .write_line_code + pop eax + sub eax,40 + ret + .pc_far: + add [vbp-12],eax + test eax,eax + js .pc_negative + mov edx,eax + mov al,2 ;opcode 2: advance pc + call .write_line_code + call .emit_leb128 + xor eax,eax + ret + .pc_negative: + mov al,0 ;extended opcode + call .write_line_code + mov al,5 ;5 bytes + call .write_line_code + mov al,2 ;set address + call .write_line_code + mov eax,[vbp-12] ;LSB + call .write_line_code + shr eax,8 + call .write_line_code + shr eax,8 + call .write_line_code + shr eax,8 ;MSB + call .write_line_code + xor eax,eax + ret + .update_line: + ;eax=address advance value + push eax + call .find_source_line + mov edx,[eax+4] + sub edx,[vbp-8] + add [vbp-8],edx + pop eax + cmp edx,6 + jb .send_special_code + .send_line_advance: + push eax + mov al,3 ;opcode 3: advance line + call .write_line_code + call .emit_signed_leb + xor edx,edx + pop eax + test eax,eax + jnz .send_special_code + .copy: + mov al,1 ;opcode 1: copy + jmp .write_line_code + .send_special_code: + add [vbp-12],eax + imul eax,6 + add eax,edx + jz .copy + add eax,10 ;special opcode + jmp .write_line_code + .find_source_line: + mov eax,[vbp-24] + mov eax,[eax+1] + .next_source_link: + test byte[eax+7],0x80 + jz .ret + mov eax,[eax+12] + jmp .next_source_link + .emit_leb128: + bsr ecx,edx + jnz .leb_calcu + or ecx,-1 + .leb_calcu: + add ecx,1 + jmp .next_leb128 + .emit_signed_leb: + ;edx is the value to emit + test edx,edx + jns .leb_pos + not edx + bsr ecx,edx + not edx + jmp .leb_bits + .leb_pos: + bsr ecx,edx + .leb_bits: + jnz .leb_calc + or ecx,-1 + .leb_calc: + add ecx,2 + .next_leb128: + mov eax,edx + and eax,0x7f + shr edx,7 + sub ecx,7 + jle .write_line_code + or al,0x80 ;set continuation bit + call .write_line_code + jmp .next_leb128 + .write_line_code: + mov ebx,[vbp+4] + cmp ebx,[code_start] + jae .skip_overwrite + mov [ebx],al + .skip_overwrite: + inc ebx + mov [vbp+4],ebx + .ret: + ret + +ARM_string_arm_code_offset = 1 +ARM_string_thumb_code_offset = 1+ARM_string_arm_code_offset+ARM_string_arm_code_identifier_len +ARM_string_data_offset = 1+ARM_string_thumb_code_offset+ARM_string_thumb_code_identifier_len +ARM_string_thumbee_code_offset = 1+ARM_string_data_offset+ARM_string_data_identifier_len + +ARM_make_symbol_strtab: + mov ebx,[code_start] + xor al,al + stosb + mov esi,ARM_string_arm_code_identifier + mov ecx,ARM_string_arm_code_identifier_len + rep movsb + stosb + mov esi,ARM_string_thumb_code_identifier + mov ecx,ARM_string_thumb_code_identifier_len + rep movsb + stosb + mov esi,ARM_string_data_identifier + mov ecx,ARM_string_data_identifier_len + rep movsb + stosb + mov esi,ARM_string_thumbee_code_identifier + mov ecx,ARM_string_thumbee_code_identifier_len + rep movsb + stosb + mov esi,[ebx-4] ;esi=source of label data + mov ebx,[ebx-8] ;ebx=last address+1 + cmp esi,ebx + jae .ret + .loop: + movzx ecx,byte[esi] + lea eax,[esi+1] + mov edx,[esi+ecx+1] + lea esi,[esi+ecx+5] + test dword[edx+8],0100h + jz .skip + xchg esi,eax + lea edx,[edi+ecx+10h] + cmp edx,[tagged_blocks] + jae out_of_memory + rep movsb + xchg esi,eax + xor al,al + stosb + .skip: + cmp esi,ebx + jb .loop + .ret: + ret + +ARM_make_symbol_symtab: + mov ebx,[code_start] + mov esi,[ebx-4] ;esi=source of label data + mov ebx,[ebx-8] ;ebx=last address+1 + cmp esi,ebx + jae .ret + push ebp + mov ebp,1+ARM_string_arm_code_identifier_len+\ + 1+ARM_string_thumb_code_identifier_len+\ + 1+ARM_string_data_identifier_len+\ + 1+ARM_string_thumbee_code_identifier_len+\ + 1 + .loop: + movzx ecx,byte[esi] + mov edx,[esi+ecx+1] + lea esi,[esi+ecx+5] + test dword[edx+8],0100h + jz .skip + lea eax,[edi+20h] + cmp eax,[tagged_blocks] + jae out_of_memory + mov [edi],ebp ;name + lea ebp,[ebp+ecx+1] + mov eax,[edx] + mov [edi+4],eax ;value + movzx eax,byte[edx+10] + mov [edi+8],eax ;size + test eax,eax + setz al + movzx eax,al + add eax,1 + 1 shl 4 ;object = 1, function = 2 + binding global + mov [edi+12],ax ;binding type + mov eax,[edx] + ;find the section associated with this label + mov ecx,[code_start] + movzx edx,word[ecx+02ch] ;e_phnum + add edx,1 + .next_section: + sub edx,1 + je .no_section + lea ecx,[edx-1] + shl ecx,5 + add ecx,[code_start] + cmp eax,[ecx+034h+8] ;p_vaddr + jb .next_section + sub eax,[ecx+034h+8] ;p_vaddr + cmp eax,[ecx+034h+14h] ;p_memsz + jb .section_found + add eax,[ecx+034h+8] ;p_vaddr + jmp .next_section + .no_section: + xor edx,edx + .section_found: + mov word[edi+14],dx ;section + add edi,16 + .skip: + cmp esi,ebx + jb .loop + pop ebp + .ret: + ret + +ARM_make_code_identifier_table: + mov ecx,[code_start] + mov ecx,[ecx+38h] + .16k = 16 shl 10 + push .16k ;+16 initial buffer size + push edi ;+12 start of data + push ecx ;+8 offset to first program byte + push [code_start] + push edi ;+0 current output position + mov vbp,vsp + .restart: + add edi,[vbp+16] + lea ebx,[edi+0x20] + cmp ebx,[tagged_blocks] + jae out_of_memory + call ARM_start_line_processing + .neg1 = -1 + push .neg1 ;-4 last code type + push .neg1 ;-8 this code type + push .neg1 ;-12 this code address + .line_loop: + mov edx,esi + cmp byte[edx],0Fh + jnz .check_data + add edx,5 + .check_data: + ;any data yet? + mov eax,edi + sub eax,[code_start] + cmp eax,[vbp+8] + jb .skip_line + .find_line: + mov al,[edx] + cmp al,1 + jz .do_line + cmp al,2 + jz .do_value + cmp al,3 + jnz .skip_line + .do_value: + add edx,6 + jmp .find_line + .do_line: + mov ecx,[addressing_space] + test byte[ecx+0x0a],1 + jnz .skip_line + movzx eax,word[edx+1] + mov ecx,080h ;data code type + cmp eax,ARM_code_generator_start-instruction_handler + jb .found_generator + movzx ecx,[code_type] + .found_generator: + mov [vbp-8],ecx + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + mov [vbp-12],eax + PUSH vbp + call assemble_line + POP vbp + lahf + mov ecx,[vbp-8] + cmp ecx,[vbp-4] + jz .next_line + mov edx,[addressing_space] + test byte[edx+0x0a],1 + jnz .next_line + push eax + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + cmp eax,[vbp-12] + jz .non_code_line + xchg edi,[vbp] + lea ebx,[edi+16] + cmp ebx,[code_start] + jae .skip_overwrite1 + mov [vbp-4],ecx + lea edx,[edi+20h] + cmp edx,[tagged_blocks] + jae out_of_memory + mov edx,ARM_string_data_offset + test cl,cl + js .found_generator2 + mov edx,ARM_string_arm_code_offset + test ecx,CPU_ACTIVITY_ARM + jnz .found_generator2 + mov edx,ARM_string_thumb_code_offset + test ecx,CPU_ACTIVITY_THUMBEE + jz .found_generator2 + mov edx,ARM_string_thumbee_code_offset + .found_generator2: + mov eax,[vbp-12] + mov [edi],edx ;name + mov [edi+4],eax ;address + mov dword[edi+8],0 ;length + mov ecx,2 + cmp edx,ARM_string_data_offset + jnz @f + mov ecx,1 + @@: mov [edi+12],cx ;binding type + ;find the section associated with this address + mov ecx,[vbp+4] + movzx edx,word[ecx+02ch] ;e_phnum + add edx,1 + .next_section: + sub edx,1 + je .no_section + lea ecx,[edx-1] + shl ecx,5 + add ecx,[vbp+4] + cmp eax,[ecx+034h+8] ;p_vaddr + jb .next_section + sub eax,[ecx+034h+8] ;p_vaddr + cmp eax,[ecx+034h+14h] ;p_memsz + jb .section_found + add eax,[ecx+034h+8] ;p_vaddr + jmp .next_section + .no_section: + xor edx,edx + .section_found: + mov word[edi+14],dx ;section + .skip_overwrite1: + add edi,16 + xchg edi,[vbp] + .non_code_line: + pop eax + .next_line: + sahf + jmp .finish_line + .skip_line: + PUSH vbp + call assemble_line + POP vbp + .finish_line: + jnc .line_loop + mov ecx,[vbp-8] + test cl,cl + js .done + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + xchg edi,[vbp] + lea ebx,[edi+16] + cmp ebx,[code_start] + jae .skip_overwrite2 + mov edx,ARM_string_data_offset + mov [edi],edx ;name + mov [edi+4],eax ;address + mov dword[edi+8],0 ;length + mov word[edi+12],1 ;binding type + mov word[edi+14],0 ;section + .skip_overwrite2: + add edi,16 + xchg edi,[vbp] + .done: + mov eax,[vbp] + cmp eax,[code_start] + jb .done_okay + mov edi,[vbp+12] + mov eax,[vbp] + sub eax,edi + mov [vbp],edi + add eax,0x100 + mov [vbp+16],eax ;adjust the buffer size + mov vsp,vbp + jmp .restart + .done_okay: + mov vsp,vbp + cmp [number_of_sections],0 + jnz .section_count_okay + inc [number_of_sections] + .section_count_okay: + pop edi + pop [code_start] + add esp,12 + ret + +ARM_label_walker: + mov edi,[code_start] + add edi,4 + push edi + call .walk + pop esi + mov ebx,edi + add edi,0fh+8 + and edi,not 0fh + mov [code_start],edi + mov [edi-4],esi + mov [edi-8],ebx + mov [esi-4],eax + ret + .walk: + mov edx,32+1 + mov ebx,hash_tree + xor eax,eax + test dword[ebx],-1 + jz .done + .recur: + mov ebx,[ebx] + sub edx,1 + jz .store + test dword[ebx],-1 + jz .right + push ebx + call .recur + pop ebx + .right: + add ebx,4 + test dword[ebx],-1 + jz .done + call .recur + .done: + add edx,1 + ret + .store: + add eax,1 ;bump the label count + mov esi,[ebx+4] + mov esi,[esi+18h] ;string text name + movzx ecx,byte[esi-1] ;name length + mov [edi],cl + add edi,1 + lea esi,[edi+ecx+20h] + cmp esi,[labels_list] + jae out_of_memory + mov esi,[ebx+4] + mov esi,[esi+18h] ;string text name + rep movsb + lea esi,[ebx+4] ;offset to 24 byte data field + movsd + mov ebx,[ebx] ;next link? + test ebx,ebx + jnz .store + jmp .done + +ARM_org_directive: + cmp [output_format],5 + jnz org_directive + test [format_flags],4 + jz org_directive + jmp ERROR_org_not_allowed + +;we must supply this label for parser.inc to assemble + +prefix_instruction: ;not used in ARM + +ARM_data_debug_abbrev: + ;this is the debug_abbrev table, it is the minimum requirement to make a complete table for AXD + db 1 ;abbrev code + db 11h ;tag_compile_unit + db 1 ;has children + db 3,8 ;name,string + db 25h,8 ;producer,string + db 11h,1 ;low_pc,address + db 12h,1 ;high_pc,address + db 10h,6 ;stmt_list,data4 + db 0 ;terminate child + db 0 ;no siblings +ARM_data_debug_abbrev_len=$-ARM_data_debug_abbrev + +ARM_data_debug_producer: + db 'ARMv8 assembler core v',ARM_VERSION_STRING,' for flat assembler v',VERSION_STRING,' by revolution',0 +ARM_data_debug_producer_len=$-ARM_data_debug_producer + +ARM_data_debug_info: + dd 0 ;length + dw 2 ;version + dd 0 ;offset to abbrev table + db 4 ;address size + db 1 ;abbrev code +ARM_data_debug_info_len=$-ARM_data_debug_info + +ARM_data_debug_line_prologue: + ;this defines the layout of the line numbers table + dd 0 ;total length + dw 2 ;version + dd 0 ;prologue length + db 1 ;minimum instruction length + db 1 ;default is statment + db 0 ;line base + db 6 ;line range + db 10 ;opcode base + db 0,1,1,1,1,0,0,0,0 ;standard opcode lengths + db 0 ;no include directories +ARM_data_debug_line_prologue_len=$-ARM_data_debug_line_prologue + +ARM_string_arm_code_identifier: + db '$a' + ARM_string_arm_code_identifier_len=$-ARM_string_arm_code_identifier +ARM_string_thumb_code_identifier: + db '$t' + ARM_string_thumb_code_identifier_len=$-ARM_string_thumb_code_identifier +ARM_string_data_identifier: + db '$d' + ARM_string_data_identifier_len=$-ARM_string_data_identifier +ARM_string_thumbee_code_identifier: + db '$t.x' + ARM_string_thumbee_code_identifier_len=$-ARM_string_thumbee_code_identifier +ARM_string_shstrtab: + dd ARM_string_shstrtab_len + db '.shstrtab' + ARM_string_shstrtab_len=$-ARM_string_shstrtab-4 +ARM_string_debug_abbrev: + dd ARM_string_debug_abbrev_len + db '.debug_abbrev' + ARM_string_debug_abbrev_len=$-ARM_string_debug_abbrev-4 +ARM_string_debug_info: + dd ARM_string_debug_info_len + db '.debug_info' + ARM_string_debug_info_len=$-ARM_string_debug_info-4 +ARM_string_debug_line: + dd ARM_string_debug_line_len + db '.debug_line' + ARM_string_debug_line_len=$-ARM_string_debug_line-4 +ARM_string_symtab: + dd ARM_string_symtab_len + db '.symtab' + ARM_string_symtab_len=$-ARM_string_symtab-4 +ARM_string_strtab: + dd ARM_string_strtab_len + db '.strtab' + ARM_string_strtab_len=$-ARM_string_strtab-4 +ARM_string_noname_section: + dd ARM_string_noname_section_len + db '.flat' + ARM_string_noname_section_len=$-ARM_string_noname_section-4 + +ARM_code_generator_start: + +;ARM/THUMB jump table + +INST_ARM64 equ es +INST_ARM64S equ fs +INST_ARM64V equ gs + +ARM_instruction_adc: + INST_ARM64S + dd 0x1a000000 + dd ARM64_dz_nz_mz + mov edx,ARM_INSTRUCTION_OPCODE_ADC shl 21 + mov ecx,0xe shl 28 + 0xa shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_add: + INST_ARM64S + dd 0x00000000 + dd ARM64_arithmetic1 + mov edx,ARM_INSTRUCTION_OPCODE_ADD shl 21 + mov ecx,0xe shl 28 + 0x8 shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_addw: + mov edx,ARM_INSTRUCTION_OPCODE_ADD shl 21 + mov ecx,0xf2000000 + jmp THUMB_rd_rn_imm12 +ARM_instruction_adr: + INST_ARM64 + dd 0x10000000 + dd ARM64_adr + mov edx,ARM_INSTRUCTION_OPCODE_ADD shl 21 + jmp ARM_rd_target +ARM_instruction_and: + INST_ARM64S + dd 0x00000000 + dd ARM64_arithmetic2 + mov edx,ARM_INSTRUCTION_OPCODE_AND shl 21 + mov ecx,0xe shl 28 + 0x0 shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_asr: + INST_ARM64 + dd 0x1ac02800 + dd ARM64_arithmetic3 + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ASR shl 5 + jmp ARM_rd_rn_shift +ARM_instruction_b: + INST_ARM64 + dd 0x14000000 + dd ARM64_b + mov edx,0x0a000000 + jmp ARM_target +ARM_instruction_bfc: + mov edx,0x07c0001f + mov ecx,0xf36f0000 + jmp ARM_rd_imm_imm +ARM_instruction_bfi: + INST_ARM64 + dd 0x33000000 + dd ARM64_bfi + mov edx,0x07c00010 + mov ecx,0xf3600000 + jmp ARM_rd_rn_imm_imm +ARM_instruction_bic: + INST_ARM64S + dd 0x00200000 + dd ARM64_arithmetic2 + mov edx,ARM_INSTRUCTION_OPCODE_BIC shl 21 + mov ecx,0xe shl 28 + 0x1 shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_bkpt: + mov edx,0x01200070 + jmp ARM_immediate16 +ARM_instruction_bl: + INST_ARM64 + dd 0x94000000 + dd ARM64_b + mov edx,0x0b000000 + jmp ARM_target +ARM_instruction_blx: + mov edx,0 ;instruction varies depending upon parameters + jmp ARM_Xtarget +ARM_instruction_bx: + mov edx,0x012fff10 + jmp ARM_rm +ARM_instruction_bxj: + mov edx,0x012fff20 + mov ecx,0xf3c08f00 + jmp ARM_rm_J +ARM_instruction_cbnz: + INST_ARM64 + dd 0x35000000 + dd ARM64_b_reg + mov ecx,0xb900 + jmp THUMB_reg_address +ARM_instruction_cbz: + INST_ARM64 + dd 0x34000000 + dd ARM64_b_reg + mov ecx,0xb100 + jmp THUMB_reg_address +ARM_instruction_cdp: + mov edx,0x0e000000 + jmp ARM_copro_op1_crd_crn_crm_op2 +ARM_instruction_cdp2: + mov edx,0xfe000000 + jmp ARM_copro_op1_crd_crn_crm_op2 +ARM_instruction_chka: + jmp THUMBEE_rn_rm +ARM_instruction_clrex: + INST_ARM64 + dd 0xd503305f + dd ARM64_clrex + mov edx,0xf57ff01f + mov ecx,0xf3bf8f2f + jmp ARM_clrex +ARM_instruction_clz: + INST_ARM64 + dd 0x5ac01000 + dd ARM64_arithmetic4 + mov edx,0x016f0f10 + mov ecx,0xfab0f080 + jmp ARM_rd_rm_CLZ +ARM_instruction_cmn: + INST_ARM64 + dd 0x20000000 + dd ARM64_arithmetic1_zr + mov edx,ARM_INSTRUCTION_OPCODE_CMN shl 21 + 1 shl 20 + mov ecx,0xe shl 28 + 0x8 shl 21 + 1 shl 20 + 0xf shl 8 + jmp ARM_rn_shifter +ARM_instruction_cmnp: + mov edx,ARM_INSTRUCTION_OPCODE_CMN shl 21 + 1 shl 20 + 0xf shl 12 + jmp ARM_rn_shifter_26bit +ARM_instruction_cmp: + INST_ARM64 + dd 0x60000000 + dd ARM64_arithmetic1_zr + mov edx,ARM_INSTRUCTION_OPCODE_CMP shl 21 + 1 shl 20 + mov ecx,0xe shl 28 + 0xd shl 21 + 1 shl 20 + 0xf shl 8 + jmp ARM_rn_shifter +ARM_instruction_cmpp: + mov edx,ARM_INSTRUCTION_OPCODE_CMP shl 21 + 1 shl 20 + 0xf shl 12 + jmp ARM_rn_shifter_26bit +ARM_instruction_cps: + mov edx,0xf1020000 + mov ecx,0xf3af8100 + jmp ARM_mode +ARM_instruction_cpsid: + mov edx,0xf10c0000 + mov ecx,0xf3af8600 + jmp ARM_iflags_mode +ARM_instruction_cpsie: + mov edx,0xf1080000 + mov ecx,0xf3af8400 + jmp ARM_iflags_mode +ARM_instruction_cpy: + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + mov ecx,0xe shl 28 + 0x2 shl 21 + 0xf shl 16 + jmp ARM_rd_rm_CPY +ARM_instruction_dbg: + mov edx,0x0320f0f0 + mov ecx,0xf3af80f0 + jmp ARM_imm4 +ARM_instruction_dmb: + INST_ARM64 + dd 0xd50330bf + dd ARM64_data_barrier + mov edx,0xf57ff050 + mov ecx,0xf3bf8f50 + jmp ARM_barrier +ARM_instruction_dsb: + INST_ARM64 + dd 0xd503309f + dd ARM64_data_barrier + mov edx,0xf57ff040 + mov ecx,0xf3bf8f40 + jmp ARM_barrier +ARM_instruction_enterx: + mov ecx,0xf3bf8f1f + jmp THUMBEE_enterx +ARM_instruction_eor: + INST_ARM64 + dd 0x40000000 + dd ARM64_arithmetic2 + mov edx,ARM_INSTRUCTION_OPCODE_EOR shl 21 + mov ecx,0xe shl 28 + 0x4 shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_hb: + mov edx,0x0000c200 + jmp THUMBEE_imm +ARM_instruction_hbl: + mov edx,0x0000c300 + jmp THUMBEE_imm +ARM_instruction_hblp: + mov edx,0x0000c400 + jmp THUMBEE_imm5_imm5 +ARM_instruction_hbp: + mov edx,0x0000c000 + jmp THUMBEE_imm3_imm5 +ARM_instruction_isb: + INST_ARM64 + dd 0xd50330df + dd ARM64_instruction_barrier + mov edx,0xf57ff060 + mov ecx,0xf3bf8f60 + jmp ARM_barrier +ARM_instruction_it: + mov ecx,0xbf08 + jmp THUMB_condition +ARM_instruction_ite: + mov ecx,0xbf0c + jmp THUMB_condition +ARM_instruction_itee: + mov ecx,0xbf0e + jmp THUMB_condition +ARM_instruction_iteee: + mov ecx,0xbf0f + jmp THUMB_condition +ARM_instruction_iteet: + mov ecx,0xbf0d + jmp THUMB_condition +ARM_instruction_itet: + mov ecx,0xbf0a + jmp THUMB_condition +ARM_instruction_itete: + mov ecx,0xbf0b + jmp THUMB_condition +ARM_instruction_itett: + mov ecx,0xbf09 + jmp THUMB_condition +ARM_instruction_itt: + mov ecx,0xbf04 + jmp THUMB_condition +ARM_instruction_itte: + mov ecx,0xbf06 + jmp THUMB_condition +ARM_instruction_ittee: + mov ecx,0xbf07 + jmp THUMB_condition +ARM_instruction_ittet: + mov ecx,0xbf05 + jmp THUMB_condition +ARM_instruction_ittt: + mov ecx,0xbf02 + jmp THUMB_condition +ARM_instruction_ittte: + mov ecx,0xbf03 + jmp THUMB_condition +ARM_instruction_itttt: + mov ecx,0xbf01 + jmp THUMB_condition +ARM_instruction_ldc: + mov edx,0x0c100000 + jmp ARM_copro_crd_address5 +ARM_instruction_ldc2: + mov edx,0xfc100000 + jmp ARM_copro_crd_address5 +ARM_instruction_ldc2l: + mov edx,0xfc500000 + jmp ARM_copro_crd_address5 +ARM_instruction_ldcl: + mov edx,0x0c500000 + jmp ARM_copro_crd_address5 +ARM_instruction_ldm: +ARM_instruction_ldmia: +ARM_instruction_ldmfd: + mov edx,0x08900000 + mov ecx,0xe8900000 + jmp ARM_rn_address4 +ARM_instruction_ldmda: +ARM_instruction_ldmfa: + mov edx,0x08100000 + jmp ARM_rn_address4 +ARM_instruction_ldmdb: +ARM_instruction_ldmea: + mov edx,0x09100000 + mov ecx,0xe9100000 + jmp ARM_rn_address4 +ARM_instruction_ldmed: +ARM_instruction_ldmib: + mov edx,0x09900000 + jmp ARM_rn_address4 +ARM_instruction_ldr: + INST_ARM64 + dd 0x38400000 + dd ARM64_memory + mov [operand_size],4 + mov edx,0x04100000 + mov ecx,0xf8500000 + jmp ARM_rd_address2 +ARM_instruction_ldrb: + INST_ARM64 + dd 0x38400000 + dd ARM64_memory_byte_hword + mov [operand_size],1 + mov edx,0x04500000 + mov ecx,0xf8100000 + jmp ARM_rd_address2 +ARM_instruction_ldrbt: + mov [operand_size],1 + mov edx,0x04700000 + mov ecx,0xf8100e00 + jmp ARM_rd_address2_post +ARM_instruction_ldrd: + mov [operand_size],8 + mov edx,0x000000d0 + mov ecx,0xe8500000 + jmp ARM_rd_address3D +ARM_instruction_ldrex: + mov [operand_size],4 + mov edx,0x01900f9f + mov ecx,0xe8500f00 + jmp ARM_rd_q_rn_p +ARM_instruction_ldrexb: + mov [operand_size],1 + mov edx,0x01d00f9f + mov ecx,0xe8d00f4f + jmp ARM_rd_q_rn_p +ARM_instruction_ldrexd: + mov [operand_size],8 + mov edx,0x01b00f9f + mov ecx,0xe8d0007f + jmp ARM_rt_rt2_q_rn_p +ARM_instruction_ldrexh: + mov [operand_size],2 + mov edx,0x01f00f9f + mov ecx,0xe8d00f5f + jmp ARM_rd_q_rn_p +ARM_instruction_ldrh: + INST_ARM64 + dd 0x38400001 + dd ARM64_memory_byte_hword + mov [operand_size],2 + mov edx,0x001000b0 + mov ecx,0xf8300000 + jmp ARM_rd_address3 +ARM_instruction_ldrht: + mov [operand_size],2 + mov edx,0x003000b0 + mov ecx,0xf8300e00 + jmp ARM_rd_address3T +ARM_instruction_ldrsb: + INST_ARM64 + dd 0x38800000 + dd ARM64_memory_signed_byte_hword + mov [operand_size],1 + mov edx,0x001000d0 + mov ecx,0xf9100000 + jmp ARM_rd_address3 +ARM_instruction_ldrsbt: + mov [operand_size],1 + mov edx,0x003000d0 + mov ecx,0xf9100e00 + jmp ARM_rd_address3T +ARM_instruction_ldrsh: + INST_ARM64 + dd 0x38800001 + dd ARM64_memory_signed_byte_hword + mov [operand_size],2 + mov edx,0x001000f0 + mov ecx,0xf9300000 + jmp ARM_rd_address3 +ARM_instruction_ldrsht: + mov [operand_size],2 + mov edx,0x003000f0 + mov ecx,0xf9300e00 + jmp ARM_rd_address3T +ARM_instruction_ldrt: + mov [operand_size],4 + mov edx,0x04300000 + mov ecx,0xf8500e00 + jmp ARM_rd_address2_post +ARM_instruction_leavex: + mov ecx,0xf3bf8f0f + jmp THUMBEE_enterx +ARM_instruction_lsl: + INST_ARM64 + dd 0x1ac02000 + dd ARM64_arithmetic3 + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_LSL shl 5 + jmp ARM_rd_rn_shift +ARM_instruction_lsr: + INST_ARM64 + dd 0x1ac02400 + dd ARM64_arithmetic3 + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_LSR shl 5 + jmp ARM_rd_rn_shift +ARM_instruction_mcr: + mov edx,0x0e000010 + jmp ARM_copro_op1_rd_crn_crm_op2 +ARM_instruction_mcr2: + mov edx,0xfe000010 + jmp ARM_copro_op1_rd_crn_crm_op2 +ARM_instruction_mcrr: + mov edx,0x0c400000 + jmp ARM_copro_op1_rd_rn_crm +ARM_instruction_mcrr2: + mov edx,0xfc400000 + jmp ARM_copro_op1_rd_rn_crm +ARM_instruction_mla: + INST_ARM64V + dd 0x0e209400 ;vector + dd 0x2f000000 ;element + dd ARM64_arithmetic17 + mov edx,0x00200090 + mov ecx,0xfb000000 + jmp ARM_rd_rm_rs_rn +ARM_instruction_mls: + INST_ARM64V + dd 0x2e209400 ;vector + dd 0x2f004000 ;element + dd ARM64_arithmetic17 + mov edx,0x00600090 + mov ecx,0xfb000010 + jmp ARM_rd_rm_rs_rn +ARM_instruction_mov: + INST_ARM64 + dd 0x00000000 + dd ARM64_mov_aliases + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + mov ecx,0xe shl 28 + 0x2 shl 21 + 0xf shl 16 + jmp ARM_rd_shifter_exp +ARM_instruction_movt: + mov edx,0x03400000 + mov ecx,0xf2c00000 + jmp ARM_rd_imm16 +ARM_instruction_movw: + mov edx,0x03000000 + mov ecx,0xf2400000 + jmp ARM_rd_imm16 +ARM_instruction_mrc: + mov edx,0x0e100010 + jmp ARM_copro_op1_rd_crn_crm_op2 +ARM_instruction_mrc2: + mov edx,0xfe100010 + jmp ARM_copro_op1_rd_crn_crm_op2 +ARM_instruction_mrrc: + mov edx,0x0c500000 + jmp ARM_copro_op1_rd_rn_crm +ARM_instruction_mrrc2: + mov edx,0xfc500000 + jmp ARM_copro_op1_rd_rn_crm +ARM_instruction_mrs: + INST_ARM64 + dd 0xd5200000 + dd ARM64_sys_predefined_mrs + mov edx,0x010f0000 + mov ecx,0xf3ef8000 + jmp ARM_rd_psr +ARM_instruction_msr: + INST_ARM64 + dd 0xd5000000 + dd ARM64_sys_predefined_msr + mov edx,0x0120f000 + mov ecx,0xf3808000 + jmp ARM_psr_value +ARM_instruction_mul: + INST_ARM64 + dd 0x00000000 + dd ARM64_arithmetic6 + mov edx,0x00000090 + mov ecx,0xfb00f000 + jmp ARM_rd_rm_rs +ARM_instruction_mvn: + INST_ARM64 + dd 0x00000000 + dd ARM64_arithmetic7 + mov edx,ARM_INSTRUCTION_OPCODE_MVN shl 21 + mov ecx,0xe shl 28 + 0x3 shl 21 + 0xf shl 16 + jmp ARM_rd_shifter +ARM_instruction_neg: + INST_ARM64S + dd 0x4b0003e0 + dd ARM64_arithmetic8 + mov edx,ARM_INSTRUCTION_OPCODE_RSB shl 21 + mov ecx,0xe shl 28 + 0xe shl 21 + jmp ARM_rd_rm +ARM_instruction_nop: + INST_ARM64 + dd 0xd503201f + dd ARM64_debug3 + mov edx,0x0320f000 + jmp ARM_nop +ARM_instruction_orn: + INST_ARM64 + dd 0x20200000 + dd ARM64_arithmetic2 + mov ecx,0xe shl 28 + 0x3 shl 21 + jmp THUMB_rd_rn_shifter_ORN +ARM_instruction_orr: + INST_ARM64 + dd 0x20000000 + dd ARM64_arithmetic2 + mov edx,ARM_INSTRUCTION_OPCODE_ORR shl 21 + mov ecx,0xe shl 28 + 0x2 shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_pkhbt: + mov edx,0x06800010 + mov ecx,0xeac00000 + jmp ARM_rd_rn_rm_shift_imm +ARM_instruction_pkhtb: + mov edx,0x06800050 + mov ecx,0xeac00020 + jmp ARM_rd_rn_rm_shift_imm +ARM_instruction_pld: + mov [operand_size],1 + mov edx,0x04500000 + mov ecx,0xf810f000 + jmp ARM_address2 +ARM_instruction_pldw: + mov [operand_size],1 + mov edx,0x04100000 + mov ecx,0xf830f000 + jmp ARM_address2 +ARM_instruction_pli: + mov [operand_size],1 + mov edx,0x05500000 + mov ecx,0xf910f000 + jmp ARM_address2 +ARM_instruction_pop: + mov edx,0x08900000 + mov ecx,0xe8900000 + jmp ARM_address4 +ARM_instruction_push: + mov edx,0x09000000 + mov ecx,0xe9000000 + jmp ARM_address4 +ARM_instruction_qadd: + mov edx,0x01000050 + mov ecx,0xfa80f080 + jmp ARM_rd_rm_rn +ARM_instruction_qadd16: + mov edx,0x06200f10 + mov ecx,0xfa90f010 + jmp ARM_rd_rn_rm +ARM_instruction_qadd8: + mov edx,0x06200f90 + mov ecx,0xfa80f010 + jmp ARM_rd_rn_rm +ARM_instruction_qaddsubx: +ARM_instruction_qasx: + mov edx,0x06200f30 + mov ecx,0xfaa0f010 + jmp ARM_rd_rn_rm +ARM_instruction_qdadd: + mov edx,0x01400050 + mov ecx,0xfa80f090 + jmp ARM_rd_rm_rn +ARM_instruction_qdsub: + mov edx,0x01600050 + mov ecx,0xfa80f0b0 + jmp ARM_rd_rm_rn +ARM_instruction_qsub: + mov edx,0x01200050 + mov ecx,0xfa80f0a0 + jmp ARM_rd_rm_rn +ARM_instruction_qsub16: + mov edx,0x06200f70 + mov ecx,0xfad0f010 + jmp ARM_rd_rn_rm +ARM_instruction_qsub8: + mov edx,0x06200ff0 + mov ecx,0xfac0f010 + jmp ARM_rd_rn_rm +ARM_instruction_qsubaddx: +ARM_instruction_qsax: + mov edx,0x06200f50 + mov ecx,0xfae0f010 + jmp ARM_rd_rn_rm +ARM_instruction_rbit: + INST_ARM64 + dd 0x5ac00000 + dd ARM64_arithmetic10 + mov edx,0x06ff0f30 + mov ecx,0xfa90f0a0 + jmp ARM_rd_rm_REV +ARM_instruction_rev: + INST_ARM64 + dd 0x5ac00800 + dd ARM64_arithmetic11 + mov edx,0x06bf0f30 + mov ecx,0xfa90f080 + jmp ARM_rd_rm_REV +ARM_instruction_rev16: + INST_ARM64 + dd 0x5ac00400 + dd ARM64_arithmetic12 + mov edx,0x06bf0fb0 + mov ecx,0xfa90f090 + jmp ARM_rd_rm_REV +ARM_instruction_revsh: + mov edx,0x06ff0fb0 + mov ecx,0xfa90f0b0 + jmp ARM_rd_rm_REV +ARM_instruction_rfe: +ARM_instruction_rfeia: +ARM_instruction_rfefd: + mov edx,0xf8900a00 + mov ecx,0xe990c000 + jmp ARM_rn +ARM_instruction_rfeda: +ARM_instruction_rfefa: + mov edx,0xf8100a00 + jmp ARM_rn +ARM_instruction_rfedb: +ARM_instruction_rfeea: + mov edx,0xf9100a00 + mov ecx,0xe810c000 + jmp ARM_rn +ARM_instruction_rfeib: +ARM_instruction_rfeed: + mov edx,0xf9900a00 + jmp ARM_rn +ARM_instruction_ror: + INST_ARM64 + dd 0x1ac02c00 + dd ARM64_arithmetic3 + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ROR shl 5 + jmp ARM_rd_rn_shift +ARM_instruction_rrx: + mov edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ROR shl 5 + mov ecx,0xea4f0000 + jmp ARM_rd_shift +ARM_instruction_rsb: + mov edx,ARM_INSTRUCTION_OPCODE_RSB shl 21 + mov ecx,0xe shl 28 + 0xe shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_rsc: + mov edx,ARM_INSTRUCTION_OPCODE_RSC shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_sadd16: + mov edx,0x06100f10 + mov ecx,0xfa90f000 + jmp ARM_rd_rn_rm +ARM_instruction_sadd8: + mov edx,0x06100f90 + mov ecx,0xfa80f000 + jmp ARM_rd_rn_rm +ARM_instruction_saddsubx: +ARM_instruction_sasx: + mov edx,0x06100f30 + mov ecx,0xfaa0f000 + jmp ARM_rd_rn_rm +ARM_instruction_sbc: + INST_ARM64S + dd 0x5a000000 + dd ARM64_dz_nz_mz + mov edx,ARM_INSTRUCTION_OPCODE_SBC shl 21 + mov ecx,0xe shl 28 + 0xb shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_sbfx: + INST_ARM64 + dd 0x13000000 + dd ARM64_bfxil + mov edx,0x07a00050 + mov ecx,0xf3400000 + jmp ARM_rd_rn_imm_imm_X +ARM_instruction_sdiv: + INST_ARM64 + dd 0x1ac00c00 + dd ARM64_dz_nz_mz + mov edx,0x0710f010 + mov ecx,0xfb90f0f0 + jmp ARM_rd_rn_rm_DIV +ARM_instruction_sel: + mov edx,0x06800fb0 + mov ecx,0xfaa0f080 + jmp ARM_rd_rn_rm +ARM_instruction_setend: + mov edx,0xf1010000 + jmp ARM_endian +ARM_instruction_sev: + INST_ARM64 + dd 0xd503209f + dd ARM64_debug3 + mov edx,0x0320f004 + mov ecx,0xf3af8004 + jmp ARM_nops +ARM_instruction_shadd16: + mov edx,0x06300f10 + mov ecx,0xfa90f020 + jmp ARM_rd_rn_rm +ARM_instruction_shadd8: + mov edx,0x06300f90 + mov ecx,0xfa80f020 + jmp ARM_rd_rn_rm +ARM_instruction_shaddsubx: +ARM_instruction_shasx: + mov edx,0x06300f30 + mov ecx,0xfaa0f020 + jmp ARM_rd_rn_rm +ARM_instruction_shsub16: + mov edx,0x06300f70 + mov ecx,0xfad0f020 + jmp ARM_rd_rn_rm +ARM_instruction_shsub8: + mov edx,0x06300ff0 + mov ecx,0xfac0f020 + jmp ARM_rd_rn_rm +ARM_instruction_shsubaddx: +ARM_instruction_shsax: + mov edx,0x06300f50 + mov ecx,0xfae0f020 + jmp ARM_rd_rn_rm +ARM_instruction_smc: + INST_ARM64 + dd 0xd4000003 + dd ARM64_debug +ARM_instruction_smi: + mov edx,0x01600070 + mov ecx,0xf7f08000 + jmp ARM_immediate4 +ARM_instruction_smlabb: + mov edx,0x01000080 + mov ecx,0xfb100000 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlabt: + mov edx,0x010000c0 + mov ecx,0xfb100010 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlad: + mov edx,0x07000010 + mov ecx,0xfb200000 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smladx: + mov edx,0x07000030 + mov ecx,0xfb200010 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smlal: + INST_ARM64V + dd 0x0e208000 ;vector + dd 0x0f002000 ;element + dd ARM64_arithmetic18_long + mov edx,0x00e00090 + mov ecx,0xfbc00000 + jmp ARM_rdlo_rdhi_rm_rs +ARM_instruction_smlalbb: + mov edx,0x01400080 + mov ecx,0xfbc00080 + jmp ARM_rdlo_rdhi_rm_rs_E +ARM_instruction_smlalbt: + mov edx,0x014000c0 + mov ecx,0xfbc00090 + jmp ARM_rdlo_rdhi_rm_rs_E +ARM_instruction_smlald: + mov edx,0x07400010 + mov ecx,0xfbc000c0 + jmp ARM_rdlo_rdhi_rm_rs_D +ARM_instruction_smlaldx: + mov edx,0x07400030 + mov ecx,0xfbc000d0 + jmp ARM_rdlo_rdhi_rm_rs_D +ARM_instruction_smlaltb: + mov edx,0x014000a0 + mov ecx,0xfbc000a0 + jmp ARM_rdlo_rdhi_rm_rs_E +ARM_instruction_smlaltt: + mov edx,0x014000e0 + mov ecx,0xfbc000b0 + jmp ARM_rdlo_rdhi_rm_rs_E +ARM_instruction_smlatb: + mov edx,0x010000a0 + mov ecx,0xfb100020 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlatt: + mov edx,0x010000e0 + mov ecx,0xfb100030 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlawb: + mov edx,0x01200080 + mov ecx,0xfb300000 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlawt: + mov edx,0x012000c0 + mov ecx,0xfb300010 + jmp ARM_rd_rm_rs_rn_E +ARM_instruction_smlsd: + mov edx,0x07000050 + mov ecx,0xfb400000 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smlsdx: + mov edx,0x07000070 + mov ecx,0xfb400010 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smlsld: + mov edx,0x07400050 + mov ecx,0xfbd000c0 + jmp ARM_rdlo_rdhi_rm_rs_D +ARM_instruction_smlsldx: + mov edx,0x07400070 + mov ecx,0xfbd000d0 + jmp ARM_rdlo_rdhi_rm_rs_D +ARM_instruction_smmla: + mov edx,0x07500010 + mov ecx,0xfb500000 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smmlar: + mov edx,0x07500030 + mov ecx,0xfb500010 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smmls: + mov edx,0x075000d0 + mov ecx,0xfb600000 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smmlsr: + mov edx,0x075000f0 + mov ecx,0xfb600010 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_smmul: + mov edx,0x0750f010 + mov ecx,0xfb50f000 + jmp ARM_rd_rm_rs_M +ARM_instruction_smmulr: + mov edx,0x0750f030 + mov ecx,0xfb50f010 + jmp ARM_rd_rm_rs_M +ARM_instruction_smuad: + mov edx,0x0700f010 + mov ecx,0xfb20f000 + jmp ARM_rd_rm_rs_M +ARM_instruction_smuadx: + mov edx,0x0700f030 + mov ecx,0xfb20f010 + jmp ARM_rd_rm_rs_M +ARM_instruction_smulbb: + mov edx,0x01600080 + mov ecx,0xfb10f000 + jmp ARM_rd_rm_rs_E +ARM_instruction_smulbt: + mov edx,0x016000c0 + mov ecx,0xfb10f010 + jmp ARM_rd_rm_rs_E +ARM_instruction_smull: + INST_ARM64 + dd 0x9b207c00 + dd ARM64_arithmetic15 + mov edx,0x00c00090 + mov ecx,0xfb800000 + jmp ARM_rdlo_rdhi_rm_rs +ARM_instruction_smultb: + mov edx,0x016000a0 + mov ecx,0xfb10f020 + jmp ARM_rd_rm_rs_E +ARM_instruction_smultt: + mov edx,0x016000e0 + mov ecx,0xfb10f030 + jmp ARM_rd_rm_rs_E +ARM_instruction_smulwb: + mov edx,0x012000a0 + mov ecx,0xfb30f000 + jmp ARM_rd_rm_rs_E +ARM_instruction_smulwt: + mov edx,0x012000e0 + mov ecx,0xfb30f010 + jmp ARM_rd_rm_rs_E +ARM_instruction_smusd: + mov edx,0x0700f050 + mov ecx,0xfb40f000 + jmp ARM_rd_rm_rs_M +ARM_instruction_smusdx: + mov edx,0x0700f070 + mov ecx,0xfb40f010 + jmp ARM_rd_rm_rs_M +ARM_instruction_srs: +ARM_instruction_srsia: +ARM_instruction_srsea: + mov edx,0xf8cd0500 + mov ecx,0xe98dc000 + jmp ARM_reg_mode +ARM_instruction_srsda: +ARM_instruction_srsfa: + mov edx,0xf84d0500 + jmp ARM_reg_mode +ARM_instruction_srsdb: +ARM_instruction_srsfd: + mov edx,0xf94d0500 + mov ecx,0xe80dc000 + jmp ARM_reg_mode +ARM_instruction_srsib: +ARM_instruction_srsed: + mov edx,0xf9cd0500 + jmp ARM_reg_mode +ARM_instruction_ssat: + mov edx,0x06a00010 + mov ecx,0xf3000000 + jmp ARM_rd_imm_rm_shift +ARM_instruction_ssat16: + mov edx,0x06a00f30 + mov ecx,0xf3200000 + jmp ARM_rd_imm_rm +ARM_instruction_ssub16: + mov edx,0x06100f70 + mov ecx,0xfad0f000 + jmp ARM_rd_rn_rm +ARM_instruction_ssub8: + mov edx,0x06100ff0 + mov ecx,0xfac0f000 + jmp ARM_rd_rn_rm +ARM_instruction_ssubaddx: +ARM_instruction_ssax: + mov edx,0x06100f50 + mov ecx,0xfae0f000 + jmp ARM_rd_rn_rm +ARM_instruction_stc: + mov edx,0x0c000000 + jmp ARM_copro_crd_address5 +ARM_instruction_stc2: + mov edx,0xfc000000 + jmp ARM_copro_crd_address5 +ARM_instruction_stc2l: + mov edx,0xfc400000 + jmp ARM_copro_crd_address5 +ARM_instruction_stcl: + mov edx,0x0c400000 + jmp ARM_copro_crd_address5 +ARM_instruction_stm: +ARM_instruction_stmia: +ARM_instruction_stmea: + mov edx,0x08800000 + mov ecx,0xe8800000 + jmp ARM_rn_address4 +ARM_instruction_stmda: +ARM_instruction_stmed: + mov edx,0x08000000 + jmp ARM_rn_address4 +ARM_instruction_stmdb: +ARM_instruction_stmfd: + mov edx,0x09000000 + mov ecx,0xe9000000 + jmp ARM_rn_address4 +ARM_instruction_stmib: +ARM_instruction_stmfa: + mov edx,0x09800000 + jmp ARM_rn_address4 +ARM_instruction_str: + INST_ARM64 + dd 0x38000000 + dd ARM64_memory + mov [operand_size],4 + mov edx,0x04000000 + mov ecx,0xf8400000 + jmp ARM_rd_address2 +ARM_instruction_strb: + INST_ARM64 + dd 0x38000000 + dd ARM64_memory_byte_hword + mov [operand_size],1 + mov edx,0x04400000 + mov ecx,0xf8000000 + jmp ARM_rd_address2 +ARM_instruction_strbt: + mov [operand_size],1 + mov edx,0x04600000 + mov ecx,0xf8000e00 + jmp ARM_rd_address2_post +ARM_instruction_strd: + mov [operand_size],8 + mov edx,0x000000f0 + mov ecx,0xe8400000 + jmp ARM_rd_address3D +ARM_instruction_strex: + mov [operand_size],4 + mov edx,0x01800f90 + mov ecx,0xe8400000 + jmp ARM_rd_rm_q_rn_p_STREX +ARM_instruction_strexb: + mov [operand_size],1 + mov edx,0x01c00f90 + mov ecx,0xe8c00f40 + jmp ARM_rd_rm_q_rn_p_STREX +ARM_instruction_strexd: + mov [operand_size],8 + mov edx,0x01a00f90 + mov ecx,0xe8c00070 + jmp ARM_rd_rt_rt2_q_rn_p +ARM_instruction_strexh: + mov [operand_size],2 + mov edx,0x01e00f90 + mov ecx,0xe8c00f50 + jmp ARM_rd_rm_q_rn_p_STREX +ARM_instruction_strh: + INST_ARM64 + dd 0x38000001 + dd ARM64_memory_byte_hword + mov [operand_size],2 + mov edx,0x000000b0 + mov ecx,0xf8200000 + jmp ARM_rd_address3 +ARM_instruction_strht: + mov [operand_size],2 + mov edx,0x002000b0 + mov ecx,0xf8200e00 + jmp ARM_rd_address3T +ARM_instruction_strt: + mov [operand_size],4 + mov edx,0x04200000 + mov ecx,0xf8400e00 + jmp ARM_rd_address2_post +ARM_instruction_sub: + INST_ARM64S + dd 0x40000000 + dd ARM64_arithmetic1 + mov edx,ARM_INSTRUCTION_OPCODE_SUB shl 21 + mov ecx,0xe shl 28 + 0xd shl 21 + jmp ARM_rd_rn_shifter +ARM_instruction_subw: + mov edx,ARM_INSTRUCTION_OPCODE_SUB shl 21 + mov ecx,0xf2000000 + 5 shl 21 + jmp THUMB_rd_rn_imm12 +ARM_instruction_svc: + INST_ARM64 + dd 0xd4000001 + dd ARM64_debug +ARM_instruction_swi: + mov edx,0x0f000000 + jmp ARM_immediate24 +ARM_instruction_swp: + mov edx,0x01000090 + jmp ARM_rd_rm_q_rn_p +ARM_instruction_swpb: + mov edx,0x01400090 + jmp ARM_rd_rm_q_rn_p +ARM_instruction_sxtab: + mov edx,0x06a00070 + mov ecx,0xfa40f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_sxtab16: + mov edx,0x06800070 + mov ecx,0xfa20f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_sxtah: + mov edx,0x06b00070 + mov ecx,0xfa00f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_sxtb: + INST_ARM64 + dd 0x13001c00 + dd ARM64_dz_nw + mov edx,0x06af0070 + mov ecx,0xfa4ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_sxtb16: + mov edx,0x068f0070 + mov ecx,0xfa2ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_sxth: + INST_ARM64 + dd 0x13003c00 + dd ARM64_dz_nw + mov edx,0x06bf0070 + mov ecx,0xfa0ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_tbb: + mov ecx,0xe8d0f000 + jmp THUMB_q_rn_rm_p +ARM_instruction_tbh: + mov ecx,0xe8d0f010 + jmp THUMB_q_rn_rm_lsl_1_p +ARM_instruction_teq: + mov edx,ARM_INSTRUCTION_OPCODE_TEQ shl 21 + 1 shl 20 + mov ecx,0xe shl 28 + 0x4 shl 21 + 1 shl 20 + 0xf shl 8 + jmp ARM_rn_shifter +ARM_instruction_teqp: + mov edx,ARM_INSTRUCTION_OPCODE_TEQ shl 21 + 1 shl 20 + 0xf shl 12 + jmp ARM_rn_shifter_26bit +ARM_instruction_tst: + INST_ARM64 + dd 0x60000000 + dd ARM64_arithmetic16 + mov edx,ARM_INSTRUCTION_OPCODE_TST shl 21 + 1 shl 20 + mov ecx,0xe shl 28 + 0x0 shl 21 + 1 shl 20 + 0xf shl 8 + jmp ARM_rn_shifter +ARM_instruction_tstp: + mov edx,ARM_INSTRUCTION_OPCODE_TST shl 21 + 1 shl 20 + 0xf shl 12 + jmp ARM_rn_shifter_26bit +ARM_instruction_uadd16: + mov edx,0x06500f10 + mov ecx,0xfa90f040 + jmp ARM_rd_rn_rm +ARM_instruction_uadd8: + mov edx,0x06500f90 + mov ecx,0xfa80f040 + jmp ARM_rd_rn_rm +ARM_instruction_uaddsubx: +ARM_instruction_uasx: + mov edx,0x06500f30 + mov ecx,0xfaa0f040 + jmp ARM_rd_rn_rm +ARM_instruction_ubfx: + INST_ARM64 + dd 0x53000000 + dd ARM64_bfxil + mov edx,0x07e00050 + mov ecx,0xf3c00000 + jmp ARM_rd_rn_imm_imm_X +ARM_instruction_udiv: + INST_ARM64 + dd 0x1ac00800 + dd ARM64_dz_nz_mz + mov edx,0x0730f010 + mov ecx,0xfbb0f0f0 + jmp ARM_rd_rn_rm_DIV +ARM_instruction_uhadd16: + mov edx,0x06700f10 + mov ecx,0xfa90f060 + jmp ARM_rd_rn_rm +ARM_instruction_uhadd8: + mov edx,0x06700f90 + mov ecx,0xfa80f060 + jmp ARM_rd_rn_rm +ARM_instruction_uhaddsubx: +ARM_instruction_uhasx: + mov edx,0x06700f30 + mov ecx,0xfaa0f060 + jmp ARM_rd_rn_rm +ARM_instruction_uhsub16: + mov edx,0x06700f70 + mov ecx,0xfad0f060 + jmp ARM_rd_rn_rm +ARM_instruction_uhsub8: + mov edx,0x06700ff0 + mov ecx,0xfac0f060 + jmp ARM_rd_rn_rm +ARM_instruction_uhsubaddx: +ARM_instruction_uhsax: + mov edx,0x06700f50 + mov ecx,0xfae0f060 + jmp ARM_rd_rn_rm +ARM_instruction_umaal: + mov edx,0x00400090 + mov ecx,0xfbe00060 + jmp ARM_rdlo_rdhi_rm_rs +ARM_instruction_umlal: + INST_ARM64V + dd 0x2e208000 ;vector + dd 0x2f002000 ;element + dd ARM64_arithmetic18_long + mov edx,0x00a00090 + mov ecx,0xfbe00000 + jmp ARM_rdlo_rdhi_rm_rs +ARM_instruction_umull: + INST_ARM64 + dd 0x9ba07c00 + dd ARM64_arithmetic15 + mov edx,0x00800090 + mov ecx,0xfba00000 + jmp ARM_rdlo_rdhi_rm_rs +ARM_instruction_und: + mov edx,0x07f000f0 + mov ecx,0xf7f0a0f0 + jmp ARM_und +ARM_instruction_uqadd16: + mov edx,0x06600f10 + mov ecx,0xfa90f050 + jmp ARM_rd_rn_rm +ARM_instruction_uqadd8: + mov edx,0x06600f90 + mov ecx,0xfa80f050 + jmp ARM_rd_rn_rm +ARM_instruction_uqaddsubx: +ARM_instruction_uqasx: + mov edx,0x06600f30 + mov ecx,0xfaa0f050 + jmp ARM_rd_rn_rm +ARM_instruction_uqsub16: + mov edx,0x06600f70 + mov ecx,0xfad0f050 + jmp ARM_rd_rn_rm +ARM_instruction_uqsub8: + mov edx,0x06600ff0 + mov ecx,0xfac0f050 + jmp ARM_rd_rn_rm +ARM_instruction_uqsubaddx: +ARM_instruction_uqsax: + mov edx,0x06600f50 + mov ecx,0xfae0f050 + jmp ARM_rd_rn_rm +ARM_instruction_usad8: + mov edx,0x0780f010 + mov ecx,0xfb70f000 + jmp ARM_rd_rm_rs_SAD +ARM_instruction_usada8: + mov edx,0x07800010 + mov ecx,0xfb700000 + jmp ARM_rd_rm_rs_rn_D +ARM_instruction_usat: + mov edx,0x06e00010 + mov ecx,0xf3800000 + jmp ARM_rd_imm_rm_shift +ARM_instruction_usat16: + mov edx,0x06e00f30 + mov ecx,0xf3a00000 + jmp ARM_rd_imm_rm +ARM_instruction_usub16: + mov edx,0x06500f70 + mov ecx,0xfad0f040 + jmp ARM_rd_rn_rm +ARM_instruction_usub8: + mov edx,0x06500ff0 + mov ecx,0xfac0f040 + jmp ARM_rd_rn_rm +ARM_instruction_usubaddx: +ARM_instruction_usax: + mov edx,0x06500f50 + mov ecx,0xfae0f040 + jmp ARM_rd_rn_rm +ARM_instruction_uxtab: + mov edx,0x06e00070 + mov ecx,0xfa50f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_uxtab16: + mov edx,0x06c00070 + mov ecx,0xfa30f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_uxtah: + mov edx,0x06f00070 + mov ecx,0xfa10f080 + jmp ARM_rd_rn_rm_rotation +ARM_instruction_uxtb: + INST_ARM64 + dd 0x53001c00 + dd ARM64_dw_nw + mov edx,0x06ef0070 + mov ecx,0xfa5ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_uxtb16: + mov edx,0x06cf0070 + mov ecx,0xfa3ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_uxth: + INST_ARM64 + dd 0x53003c00 + dd ARM64_dw_nw + mov edx,0x06ff0070 + mov ecx,0xfa1ff080 + jmp ARM_rd_rm_rotation +ARM_instruction_wfe: + INST_ARM64 + dd 0xd503205f + dd ARM64_debug3 + mov edx,0x0320f002 + mov ecx,0xf3af8002 + jmp ARM_nops +ARM_instruction_wfi: + INST_ARM64 + dd 0xd503207f + dd ARM64_debug3 + mov edx,0x0320f003 + mov ecx,0xf3af8003 + jmp ARM_nops +ARM_instruction_yield: + INST_ARM64 + dd 0xd503203f + dd ARM64_debug3 + mov edx,0x0320f001 + mov ecx,0xf3af8001 + jmp ARM_nops + +;FPA jump table + +ARM_instruction_absd: + mov edx,0x0e208180 + jmp FPA_fd_fm +ARM_instruction_absdm: + mov edx,0x0e2081c0 + jmp FPA_fd_fm +ARM_instruction_absdp: + mov edx,0x0e2081a0 + jmp FPA_fd_fm +ARM_instruction_absdz: + mov edx,0x0e2081e0 + jmp FPA_fd_fm +ARM_instruction_abse: + mov edx,0x0e288100 + jmp FPA_fd_fm +ARM_instruction_absem: + mov edx,0x0e288140 + jmp FPA_fd_fm +ARM_instruction_absep: + mov edx,0x0e288120 + jmp FPA_fd_fm +ARM_instruction_absez: + mov edx,0x0e288160 + jmp FPA_fd_fm +ARM_instruction_abss: + mov edx,0x0e208100 + jmp FPA_fd_fm +ARM_instruction_abssm: + mov edx,0x0e208140 + jmp FPA_fd_fm +ARM_instruction_abssp: + mov edx,0x0e208120 + jmp FPA_fd_fm +ARM_instruction_abssz: + mov edx,0x0e208160 + jmp FPA_fd_fm +ARM_instruction_acsd: + mov edx,0x0ec08180 + jmp FPA_fd_fm +ARM_instruction_acsdm: + mov edx,0x0ec081c0 + jmp FPA_fd_fm +ARM_instruction_acsdp: + mov edx,0x0ec081a0 + jmp FPA_fd_fm +ARM_instruction_acsdz: + mov edx,0x0ec081e0 + jmp FPA_fd_fm +ARM_instruction_acse: + mov edx,0x0ec88100 + jmp FPA_fd_fm +ARM_instruction_acsem: + mov edx,0x0ec88140 + jmp FPA_fd_fm +ARM_instruction_acsep: + mov edx,0x0ec88120 + jmp FPA_fd_fm +ARM_instruction_acsez: + mov edx,0x0ec88160 + jmp FPA_fd_fm +ARM_instruction_acss: + mov edx,0x0ec08100 + jmp FPA_fd_fm +ARM_instruction_acssm: + mov edx,0x0ec08140 + jmp FPA_fd_fm +ARM_instruction_acssp: + mov edx,0x0ec08120 + jmp FPA_fd_fm +ARM_instruction_acssz: + mov edx,0x0ec08160 + jmp FPA_fd_fm +ARM_instruction_adfd: + mov edx,0x0e000180 + jmp FPA_fd_fn_fm +ARM_instruction_adfdm: + mov edx,0x0e0001c0 + jmp FPA_fd_fn_fm +ARM_instruction_adfdp: + mov edx,0x0e0001a0 + jmp FPA_fd_fn_fm +ARM_instruction_adfdz: + mov edx,0x0e0001e0 + jmp FPA_fd_fn_fm +ARM_instruction_adfe: + mov edx,0x0e080100 + jmp FPA_fd_fn_fm +ARM_instruction_adfem: + mov edx,0x0e080140 + jmp FPA_fd_fn_fm +ARM_instruction_adfep: + mov edx,0x0e080120 + jmp FPA_fd_fn_fm +ARM_instruction_adfez: + mov edx,0x0e080160 + jmp FPA_fd_fn_fm +ARM_instruction_adfs: + mov edx,0x0e000100 + jmp FPA_fd_fn_fm +ARM_instruction_adfsm: + mov edx,0x0e000140 + jmp FPA_fd_fn_fm +ARM_instruction_adfsp: + mov edx,0x0e000120 + jmp FPA_fd_fn_fm +ARM_instruction_adfsz: + mov edx,0x0e000160 + jmp FPA_fd_fn_fm +ARM_instruction_asnd: + mov edx,0x0eb08180 + jmp FPA_fd_fm +ARM_instruction_asndm: + mov edx,0x0eb081c0 + jmp FPA_fd_fm +ARM_instruction_asndp: + mov edx,0x0eb081a0 + jmp FPA_fd_fm +ARM_instruction_asndz: + mov edx,0x0eb081e0 + jmp FPA_fd_fm +ARM_instruction_asne: + mov edx,0x0eb88100 + jmp FPA_fd_fm +ARM_instruction_asnem: + mov edx,0x0eb88140 + jmp FPA_fd_fm +ARM_instruction_asnep: + mov edx,0x0eb88120 + jmp FPA_fd_fm +ARM_instruction_asnez: + mov edx,0x0eb88160 + jmp FPA_fd_fm +ARM_instruction_asns: + mov edx,0x0eb08100 + jmp FPA_fd_fm +ARM_instruction_asnsm: + mov edx,0x0eb08140 + jmp FPA_fd_fm +ARM_instruction_asnsp: + mov edx,0x0eb08120 + jmp FPA_fd_fm +ARM_instruction_asnsz: + mov edx,0x0eb08160 + jmp FPA_fd_fm +ARM_instruction_atnd: + mov edx,0x0ed08180 + jmp FPA_fd_fm +ARM_instruction_atndm: + mov edx,0x0ed081c0 + jmp FPA_fd_fm +ARM_instruction_atndp: + mov edx,0x0ed081a0 + jmp FPA_fd_fm +ARM_instruction_atndz: + mov edx,0x0ed081e0 + jmp FPA_fd_fm +ARM_instruction_atne: + mov edx,0x0ed88100 + jmp FPA_fd_fm +ARM_instruction_atnem: + mov edx,0x0ed88140 + jmp FPA_fd_fm +ARM_instruction_atnep: + mov edx,0x0ed88120 + jmp FPA_fd_fm +ARM_instruction_atnez: + mov edx,0x0ed88160 + jmp FPA_fd_fm +ARM_instruction_atns: + mov edx,0x0ed08100 + jmp FPA_fd_fm +ARM_instruction_atnsm: + mov edx,0x0ed08140 + jmp FPA_fd_fm +ARM_instruction_atnsp: + mov edx,0x0ed08120 + jmp FPA_fd_fm +ARM_instruction_atnsz: + mov edx,0x0ed08160 + jmp FPA_fd_fm +ARM_instruction_cmf: + mov edx,0x0e90f110 + jmp FPA_fn_fm +ARM_instruction_cmfe: + mov edx,0x0ed0f110 + jmp FPA_fn_fm +ARM_instruction_cnf: + mov edx,0x0eb0f110 + jmp FPA_fn_fm +ARM_instruction_cnfe: + mov edx,0x0ef0f110 + jmp FPA_fn_fm +ARM_instruction_cosd: + mov edx,0x0e908180 + jmp FPA_fd_fm +ARM_instruction_cosdm: + mov edx,0x0e9081c0 + jmp FPA_fd_fm +ARM_instruction_cosdp: + mov edx,0x0e9081a0 + jmp FPA_fd_fm +ARM_instruction_cosdz: + mov edx,0x0e9081e0 + jmp FPA_fd_fm +ARM_instruction_cose: + mov edx,0x0e988100 + jmp FPA_fd_fm +ARM_instruction_cosem: + mov edx,0x0e988140 + jmp FPA_fd_fm +ARM_instruction_cosep: + mov edx,0x0e988120 + jmp FPA_fd_fm +ARM_instruction_cosez: + mov edx,0x0e988160 + jmp FPA_fd_fm +ARM_instruction_coss: + mov edx,0x0e908100 + jmp FPA_fd_fm +ARM_instruction_cossm: + mov edx,0x0e908140 + jmp FPA_fd_fm +ARM_instruction_cossp: + mov edx,0x0e908120 + jmp FPA_fd_fm +ARM_instruction_cossz: + mov edx,0x0e908160 + jmp FPA_fd_fm +ARM_instruction_dvfd: + mov edx,0x0e400180 + jmp FPA_fd_fn_fm +ARM_instruction_dvfdm: + mov edx,0x0e4001c0 + jmp FPA_fd_fn_fm +ARM_instruction_dvfdp: + mov edx,0x0e4001a0 + jmp FPA_fd_fn_fm +ARM_instruction_dvfdz: + mov edx,0x0e4001e0 + jmp FPA_fd_fn_fm +ARM_instruction_dvfe: + mov edx,0x0e480100 + jmp FPA_fd_fn_fm +ARM_instruction_dvfem: + mov edx,0x0e480140 + jmp FPA_fd_fn_fm +ARM_instruction_dvfep: + mov edx,0x0e480120 + jmp FPA_fd_fn_fm +ARM_instruction_dvfez: + mov edx,0x0e480160 + jmp FPA_fd_fn_fm +ARM_instruction_dvfs: + mov edx,0x0e400100 + jmp FPA_fd_fn_fm +ARM_instruction_dvfsm: + mov edx,0x0e400140 + jmp FPA_fd_fn_fm +ARM_instruction_dvfsp: + mov edx,0x0e400120 + jmp FPA_fd_fn_fm +ARM_instruction_dvfsz: + mov edx,0x0e400160 + jmp FPA_fd_fn_fm +ARM_instruction_expd: + mov edx,0x0e708180 + jmp FPA_fd_fm +ARM_instruction_expdm: + mov edx,0x0e7081c0 + jmp FPA_fd_fm +ARM_instruction_expdp: + mov edx,0x0e7081a0 + jmp FPA_fd_fm +ARM_instruction_expdz: + mov edx,0x0e7081e0 + jmp FPA_fd_fm +ARM_instruction_expe: + mov edx,0x0e788100 + jmp FPA_fd_fm +ARM_instruction_expem: + mov edx,0x0e788140 + jmp FPA_fd_fm +ARM_instruction_expep: + mov edx,0x0e788120 + jmp FPA_fd_fm +ARM_instruction_expez: + mov edx,0x0e788160 + jmp FPA_fd_fm +ARM_instruction_exps: + mov edx,0x0e708100 + jmp FPA_fd_fm +ARM_instruction_expsm: + mov edx,0x0e708140 + jmp FPA_fd_fm +ARM_instruction_expsp: + mov edx,0x0e708120 + jmp FPA_fd_fm +ARM_instruction_expsz: + mov edx,0x0e708160 + jmp FPA_fd_fm +ARM_instruction_fdvd: + mov edx,0x0ea00180 + jmp FPA_fd_fn_fm +ARM_instruction_fdvdm: + mov edx,0x0ea001c0 + jmp FPA_fd_fn_fm +ARM_instruction_fdvdp: + mov edx,0x0ea001a0 + jmp FPA_fd_fn_fm +ARM_instruction_fdvdz: + mov edx,0x0ea001e0 + jmp FPA_fd_fn_fm +ARM_instruction_fdve: + mov edx,0x0ea80100 + jmp FPA_fd_fn_fm +ARM_instruction_fdvem: + mov edx,0x0ea80140 + jmp FPA_fd_fn_fm +ARM_instruction_fdvep: + mov edx,0x0ea80120 + jmp FPA_fd_fn_fm +ARM_instruction_fdvez: + mov edx,0x0ea80160 + jmp FPA_fd_fn_fm +ARM_instruction_fdvs: + mov edx,0x0ea00100 + jmp FPA_fd_fn_fm +ARM_instruction_fdvsm: + mov edx,0x0ea00140 + jmp FPA_fd_fn_fm +ARM_instruction_fdvsp: + mov edx,0x0ea00120 + jmp FPA_fd_fn_fm +ARM_instruction_fdvsz: + mov edx,0x0ea00160 + jmp FPA_fd_fn_fm +ARM_instruction_fix: + mov edx,0x0e100110 + jmp FPA_rd_fm +ARM_instruction_fixm: + mov edx,0x0e100150 + jmp FPA_rd_fm +ARM_instruction_fixp: + mov edx,0x0e100130 + jmp FPA_rd_fm +ARM_instruction_fixz: + mov edx,0x0e100170 + jmp FPA_rd_fm +ARM_instruction_fltd: + mov edx,0x0e000190 + jmp FPA_fn_rd +ARM_instruction_fltdm: + mov edx,0x0e0001d0 + jmp FPA_fn_rd +ARM_instruction_fltdp: + mov edx,0x0e0001b0 + jmp FPA_fn_rd +ARM_instruction_fltdz: + mov edx,0x0e0001f0 + jmp FPA_fn_rd +ARM_instruction_flte: + mov edx,0x0e080110 + jmp FPA_fn_rd +ARM_instruction_fltem: + mov edx,0x0e080150 + jmp FPA_fn_rd +ARM_instruction_fltep: + mov edx,0x0e080130 + jmp FPA_fn_rd +ARM_instruction_fltez: + mov edx,0x0e080170 + jmp FPA_fn_rd +ARM_instruction_flts: + mov edx,0x0e000110 + jmp FPA_fn_rd +ARM_instruction_fltsm: + mov edx,0x0e000150 + jmp FPA_fn_rd +ARM_instruction_fltsp: + mov edx,0x0e000130 + jmp FPA_fn_rd +ARM_instruction_fltsz: + mov edx,0x0e000170 + jmp FPA_fn_rd +ARM_instruction_fmld: + mov edx,0x0e900180 + jmp FPA_fd_fn_fm +ARM_instruction_fmldm: + mov edx,0x0e9001c0 + jmp FPA_fd_fn_fm +ARM_instruction_fmldp: + mov edx,0x0e9001a0 + jmp FPA_fd_fn_fm +ARM_instruction_fmldz: + mov edx,0x0e9001e0 + jmp FPA_fd_fn_fm +ARM_instruction_fmle: + mov edx,0x0e980100 + jmp FPA_fd_fn_fm +ARM_instruction_fmlem: + mov edx,0x0e980140 + jmp FPA_fd_fn_fm +ARM_instruction_fmlep: + mov edx,0x0e980120 + jmp FPA_fd_fn_fm +ARM_instruction_fmlez: + mov edx,0x0e980160 + jmp FPA_fd_fn_fm +ARM_instruction_fmls: + INST_ARM64V + dd 0x5f805000 ;scalar + dd 0x0f805000 ;vector + dd ARM64_vector_scalar_sd_two_reg_element_sub + mov edx,0x0e900100 + jmp FPA_fd_fn_fm +ARM_instruction_fmlsm: + mov edx,0x0e900140 + jmp FPA_fd_fn_fm +ARM_instruction_fmlsp: + mov edx,0x0e900120 + jmp FPA_fd_fn_fm +ARM_instruction_fmlsz: + mov edx,0x0e900160 + jmp FPA_fd_fn_fm +ARM_instruction_frdd: + mov edx,0x0eb00180 + jmp FPA_fd_fn_fm +ARM_instruction_frddm: + mov edx,0x0eb001c0 + jmp FPA_fd_fn_fm +ARM_instruction_frddp: + mov edx,0x0eb001a0 + jmp FPA_fd_fn_fm +ARM_instruction_frddz: + mov edx,0x0eb001e0 + jmp FPA_fd_fn_fm +ARM_instruction_frde: + mov edx,0x0eb80100 + jmp FPA_fd_fn_fm +ARM_instruction_frdem: + mov edx,0x0eb80140 + jmp FPA_fd_fn_fm +ARM_instruction_frdep: + mov edx,0x0eb80120 + jmp FPA_fd_fn_fm +ARM_instruction_frdez: + mov edx,0x0eb80160 + jmp FPA_fd_fn_fm +ARM_instruction_frds: + mov edx,0x0eb00100 + jmp FPA_fd_fn_fm +ARM_instruction_frdsm: + mov edx,0x0eb00140 + jmp FPA_fd_fn_fm +ARM_instruction_frdsp: + mov edx,0x0eb00120 + jmp FPA_fd_fn_fm +ARM_instruction_frdsz: + mov edx,0x0eb00160 + jmp FPA_fd_fn_fm +ARM_instruction_ldfd: + mov edx,0x0c108100 + jmp FPA_fd_address5 +ARM_instruction_ldfe: + mov edx,0x0c500100 + jmp FPA_fd_address5 +ARM_instruction_ldfp: + mov edx,0x0c508100 + jmp FPA_fd_address5 +ARM_instruction_ldfs: + mov edx,0x0c100100 + jmp FPA_fd_address5 +ARM_instruction_lfm: + mov edx,0x0c100200 + jmp FPA_fd_imm_address5 +ARM_instruction_lfmea: + mov edx,0x0d100200 + jmp FPA_fd_imm_rn +ARM_instruction_lfmfd: + mov edx,0x0c900200 + jmp FPA_fd_imm_rn +ARM_instruction_lgnd: + mov edx,0x0e608180 + jmp FPA_fd_fm +ARM_instruction_lgndm: + mov edx,0x0e6081c0 + jmp FPA_fd_fm +ARM_instruction_lgndp: + mov edx,0x0e6081a0 + jmp FPA_fd_fm +ARM_instruction_lgndz: + mov edx,0x0e6081e0 + jmp FPA_fd_fm +ARM_instruction_lgne: + mov edx,0x0e688100 + jmp FPA_fd_fm +ARM_instruction_lgnem: + mov edx,0x0e688140 + jmp FPA_fd_fm +ARM_instruction_lgnep: + mov edx,0x0e688120 + jmp FPA_fd_fm +ARM_instruction_lgnez: + mov edx,0x0e688160 + jmp FPA_fd_fm +ARM_instruction_lgns: + mov edx,0x0e608100 + jmp FPA_fd_fm +ARM_instruction_lgnsm: + mov edx,0x0e608140 + jmp FPA_fd_fm +ARM_instruction_lgnsp: + mov edx,0x0e608120 + jmp FPA_fd_fm +ARM_instruction_lgnsz: + mov edx,0x0e608160 + jmp FPA_fd_fm +ARM_instruction_logd: + mov edx,0x0e508180 + jmp FPA_fd_fm +ARM_instruction_logdm: + mov edx,0x0e5081c0 + jmp FPA_fd_fm +ARM_instruction_logdp: + mov edx,0x0e5081a0 + jmp FPA_fd_fm +ARM_instruction_logdz: + mov edx,0x0e5081e0 + jmp FPA_fd_fm +ARM_instruction_loge: + mov edx,0x0e588100 + jmp FPA_fd_fm +ARM_instruction_logem: + mov edx,0x0e588140 + jmp FPA_fd_fm +ARM_instruction_logep: + mov edx,0x0e588120 + jmp FPA_fd_fm +ARM_instruction_logez: + mov edx,0x0e588160 + jmp FPA_fd_fm +ARM_instruction_logs: + mov edx,0x0e508100 + jmp FPA_fd_fm +ARM_instruction_logsm: + mov edx,0x0e508140 + jmp FPA_fd_fm +ARM_instruction_logsp: + mov edx,0x0e508120 + jmp FPA_fd_fm +ARM_instruction_logsz: + mov edx,0x0e508160 + jmp FPA_fd_fm +ARM_instruction_mnfd: + mov edx,0x0e108180 + jmp FPA_fd_fm +ARM_instruction_mnfdm: + mov edx,0x0e1081c0 + jmp FPA_fd_fm +ARM_instruction_mnfdp: + mov edx,0x0e1081a0 + jmp FPA_fd_fm +ARM_instruction_mnfdz: + mov edx,0x0e1081e0 + jmp FPA_fd_fm +ARM_instruction_mnfe: + mov edx,0x0e188100 + jmp FPA_fd_fm +ARM_instruction_mnfem: + mov edx,0x0e188140 + jmp FPA_fd_fm +ARM_instruction_mnfep: + mov edx,0x0e188120 + jmp FPA_fd_fm +ARM_instruction_mnfez: + mov edx,0x0e188160 + jmp FPA_fd_fm +ARM_instruction_mnfs: + mov edx,0x0e108100 + jmp FPA_fd_fm +ARM_instruction_mnfsm: + mov edx,0x0e108140 + jmp FPA_fd_fm +ARM_instruction_mnfsp: + mov edx,0x0e108120 + jmp FPA_fd_fm +ARM_instruction_mnfsz: + mov edx,0x0e108160 + jmp FPA_fd_fm +ARM_instruction_mufd: + mov edx,0x0e100180 + jmp FPA_fd_fn_fm +ARM_instruction_mufdm: + mov edx,0x0e1001c0 + jmp FPA_fd_fn_fm +ARM_instruction_mufdp: + mov edx,0x0e1001a0 + jmp FPA_fd_fn_fm +ARM_instruction_mufdz: + mov edx,0x0e1001e0 + jmp FPA_fd_fn_fm +ARM_instruction_mufe: + mov edx,0x0e180100 + jmp FPA_fd_fn_fm +ARM_instruction_mufem: + mov edx,0x0e180140 + jmp FPA_fd_fn_fm +ARM_instruction_mufep: + mov edx,0x0e180120 + jmp FPA_fd_fn_fm +ARM_instruction_mufez: + mov edx,0x0e180160 + jmp FPA_fd_fn_fm +ARM_instruction_mufs: + mov edx,0x0e100100 + jmp FPA_fd_fn_fm +ARM_instruction_mufsm: + mov edx,0x0e100140 + jmp FPA_fd_fn_fm +ARM_instruction_mufsp: + mov edx,0x0e100120 + jmp FPA_fd_fn_fm +ARM_instruction_mufsz: + mov edx,0x0e100160 + jmp FPA_fd_fn_fm +ARM_instruction_mvfd: + mov edx,0x0e008180 + jmp FPA_fd_fm +ARM_instruction_mvfdm: + mov edx,0x0e0081c0 + jmp FPA_fd_fm +ARM_instruction_mvfdp: + mov edx,0x0e0081a0 + jmp FPA_fd_fm +ARM_instruction_mvfdz: + mov edx,0x0e0081e0 + jmp FPA_fd_fm +ARM_instruction_mvfe: + mov edx,0x0e088100 + jmp FPA_fd_fm +ARM_instruction_mvfem: + mov edx,0x0e088140 + jmp FPA_fd_fm +ARM_instruction_mvfep: + mov edx,0x0e088120 + jmp FPA_fd_fm +ARM_instruction_mvfez: + mov edx,0x0e088160 + jmp FPA_fd_fm +ARM_instruction_mvfs: + mov edx,0x0e008100 + jmp FPA_fd_fm +ARM_instruction_mvfsm: + mov edx,0x0e008140 + jmp FPA_fd_fm +ARM_instruction_mvfsp: + mov edx,0x0e008120 + jmp FPA_fd_fm +ARM_instruction_mvfsz: + mov edx,0x0e008160 + jmp FPA_fd_fm +ARM_instruction_nrmd: + mov edx,0x0ef08180 + jmp FPA_fd_fm +ARM_instruction_nrmdm: + mov edx,0x0ef081c0 + jmp FPA_fd_fm +ARM_instruction_nrmdp: + mov edx,0x0ef081a0 + jmp FPA_fd_fm +ARM_instruction_nrmdz: + mov edx,0x0ef081e0 + jmp FPA_fd_fm +ARM_instruction_nrme: + mov edx,0x0ef88100 + jmp FPA_fd_fm +ARM_instruction_nrmem: + mov edx,0x0ef88140 + jmp FPA_fd_fm +ARM_instruction_nrmep: + mov edx,0x0ef88120 + jmp FPA_fd_fm +ARM_instruction_nrmez: + mov edx,0x0ef88160 + jmp FPA_fd_fm +ARM_instruction_nrms: + mov edx,0x0ef08100 + jmp FPA_fd_fm +ARM_instruction_nrmsm: + mov edx,0x0ef08140 + jmp FPA_fd_fm +ARM_instruction_nrmsp: + mov edx,0x0ef08120 + jmp FPA_fd_fm +ARM_instruction_nrmsz: + mov edx,0x0ef08160 + jmp FPA_fd_fm +ARM_instruction_pold: + mov edx,0x0ec00180 + jmp FPA_fd_fn_fm +ARM_instruction_poldm: + mov edx,0x0ec001c0 + jmp FPA_fd_fn_fm +ARM_instruction_poldp: + mov edx,0x0ec001a0 + jmp FPA_fd_fn_fm +ARM_instruction_poldz: + mov edx,0x0ec001e0 + jmp FPA_fd_fn_fm +ARM_instruction_pole: + mov edx,0x0ec80100 + jmp FPA_fd_fn_fm +ARM_instruction_polem: + mov edx,0x0ec80140 + jmp FPA_fd_fn_fm +ARM_instruction_polep: + mov edx,0x0ec80120 + jmp FPA_fd_fn_fm +ARM_instruction_polez: + mov edx,0x0ec80160 + jmp FPA_fd_fn_fm +ARM_instruction_pols: + mov edx,0x0ec00100 + jmp FPA_fd_fn_fm +ARM_instruction_polsm: + mov edx,0x0ec00140 + jmp FPA_fd_fn_fm +ARM_instruction_polsp: + mov edx,0x0ec00120 + jmp FPA_fd_fn_fm +ARM_instruction_polsz: + mov edx,0x0ec00160 + jmp FPA_fd_fn_fm +ARM_instruction_powd: + mov edx,0x0e600180 + jmp FPA_fd_fn_fm +ARM_instruction_powdm: + mov edx,0x0e6001c0 + jmp FPA_fd_fn_fm +ARM_instruction_powdp: + mov edx,0x0e6001a0 + jmp FPA_fd_fn_fm +ARM_instruction_powdz: + mov edx,0x0e6001e0 + jmp FPA_fd_fn_fm +ARM_instruction_powe: + mov edx,0x0e680100 + jmp FPA_fd_fn_fm +ARM_instruction_powem: + mov edx,0x0e680140 + jmp FPA_fd_fn_fm +ARM_instruction_powep: + mov edx,0x0e680120 + jmp FPA_fd_fn_fm +ARM_instruction_powez: + mov edx,0x0e680160 + jmp FPA_fd_fn_fm +ARM_instruction_pows: + mov edx,0x0e600100 + jmp FPA_fd_fn_fm +ARM_instruction_powsm: + mov edx,0x0e600140 + jmp FPA_fd_fn_fm +ARM_instruction_powsp: + mov edx,0x0e600120 + jmp FPA_fd_fn_fm +ARM_instruction_powsz: + mov edx,0x0e600160 + jmp FPA_fd_fn_fm +ARM_instruction_rdfd: + mov edx,0x0e500180 + jmp FPA_fd_fn_fm +ARM_instruction_rdfdm: + mov edx,0x0e5001c0 + jmp FPA_fd_fn_fm +ARM_instruction_rdfdp: + mov edx,0x0e5001a0 + jmp FPA_fd_fn_fm +ARM_instruction_rdfdz: + mov edx,0x0e5001e0 + jmp FPA_fd_fn_fm +ARM_instruction_rdfe: + mov edx,0x0e580100 + jmp FPA_fd_fn_fm +ARM_instruction_rdfem: + mov edx,0x0e580140 + jmp FPA_fd_fn_fm +ARM_instruction_rdfep: + mov edx,0x0e580120 + jmp FPA_fd_fn_fm +ARM_instruction_rdfez: + mov edx,0x0e580160 + jmp FPA_fd_fn_fm +ARM_instruction_rdfs: + mov edx,0x0e500100 + jmp FPA_fd_fn_fm +ARM_instruction_rdfsm: + mov edx,0x0e500140 + jmp FPA_fd_fn_fm +ARM_instruction_rdfsp: + mov edx,0x0e500120 + jmp FPA_fd_fn_fm +ARM_instruction_rdfsz: + mov edx,0x0e500160 + jmp FPA_fd_fn_fm +ARM_instruction_rfc: + mov edx,0x0e500110 + jmp FPA_rd +ARM_instruction_rfs: + mov edx,0x0e300110 + jmp FPA_rd +ARM_instruction_rmfd: + mov edx,0x0e800180 + jmp FPA_fd_fn_fm +ARM_instruction_rmfdm: + mov edx,0x0e8001c0 + jmp FPA_fd_fn_fm +ARM_instruction_rmfdp: + mov edx,0x0e8001a0 + jmp FPA_fd_fn_fm +ARM_instruction_rmfdz: + mov edx,0x0e8001e0 + jmp FPA_fd_fn_fm +ARM_instruction_rmfe: + mov edx,0x0e880100 + jmp FPA_fd_fn_fm +ARM_instruction_rmfem: + mov edx,0x0e880140 + jmp FPA_fd_fn_fm +ARM_instruction_rmfep: + mov edx,0x0e880120 + jmp FPA_fd_fn_fm +ARM_instruction_rmfez: + mov edx,0x0e880160 + jmp FPA_fd_fn_fm +ARM_instruction_rmfs: + mov edx,0x0e800100 + jmp FPA_fd_fn_fm +ARM_instruction_rmfsm: + mov edx,0x0e800140 + jmp FPA_fd_fn_fm +ARM_instruction_rmfsp: + mov edx,0x0e800120 + jmp FPA_fd_fn_fm +ARM_instruction_rmfsz: + mov edx,0x0e800160 + jmp FPA_fd_fn_fm +ARM_instruction_rndd: + mov edx,0x0e308180 + jmp FPA_fd_fm +ARM_instruction_rnddm: + mov edx,0x0e3081c0 + jmp FPA_fd_fm +ARM_instruction_rnddp: + mov edx,0x0e3081a0 + jmp FPA_fd_fm +ARM_instruction_rnddz: + mov edx,0x0e3081e0 + jmp FPA_fd_fm +ARM_instruction_rnde: + mov edx,0x0e388100 + jmp FPA_fd_fm +ARM_instruction_rndem: + mov edx,0x0e388140 + jmp FPA_fd_fm +ARM_instruction_rndep: + mov edx,0x0e388120 + jmp FPA_fd_fm +ARM_instruction_rndez: + mov edx,0x0e388160 + jmp FPA_fd_fm +ARM_instruction_rnds: + mov edx,0x0e308100 + jmp FPA_fd_fm +ARM_instruction_rndsm: + mov edx,0x0e308140 + jmp FPA_fd_fm +ARM_instruction_rndsp: + mov edx,0x0e308120 + jmp FPA_fd_fm +ARM_instruction_rndsz: + mov edx,0x0e308160 + jmp FPA_fd_fm +ARM_instruction_rpwd: + mov edx,0x0e700180 + jmp FPA_fd_fn_fm +ARM_instruction_rpwdm: + mov edx,0x0e7001c0 + jmp FPA_fd_fn_fm +ARM_instruction_rpwdp: + mov edx,0x0e7001a0 + jmp FPA_fd_fn_fm +ARM_instruction_rpwdz: + mov edx,0x0e7001e0 + jmp FPA_fd_fn_fm +ARM_instruction_rpwe: + mov edx,0x0e780100 + jmp FPA_fd_fn_fm +ARM_instruction_rpwem: + mov edx,0x0e780140 + jmp FPA_fd_fn_fm +ARM_instruction_rpwep: + mov edx,0x0e780120 + jmp FPA_fd_fn_fm +ARM_instruction_rpwez: + mov edx,0x0e780160 + jmp FPA_fd_fn_fm +ARM_instruction_rpws: + mov edx,0x0e700100 + jmp FPA_fd_fn_fm +ARM_instruction_rpwsm: + mov edx,0x0e700140 + jmp FPA_fd_fn_fm +ARM_instruction_rpwsp: + mov edx,0x0e700120 + jmp FPA_fd_fn_fm +ARM_instruction_rpwsz: + mov edx,0x0e700160 + jmp FPA_fd_fn_fm +ARM_instruction_rsfd: + mov edx,0x0e300180 + jmp FPA_fd_fn_fm +ARM_instruction_rsfdm: + mov edx,0x0e3001c0 + jmp FPA_fd_fn_fm +ARM_instruction_rsfdp: + mov edx,0x0e3001a0 + jmp FPA_fd_fn_fm +ARM_instruction_rsfdz: + mov edx,0x0e3001e0 + jmp FPA_fd_fn_fm +ARM_instruction_rsfe: + mov edx,0x0e380100 + jmp FPA_fd_fn_fm +ARM_instruction_rsfem: + mov edx,0x0e380140 + jmp FPA_fd_fn_fm +ARM_instruction_rsfep: + mov edx,0x0e380120 + jmp FPA_fd_fn_fm +ARM_instruction_rsfez: + mov edx,0x0e380160 + jmp FPA_fd_fn_fm +ARM_instruction_rsfs: + mov edx,0x0e300100 + jmp FPA_fd_fn_fm +ARM_instruction_rsfsm: + mov edx,0x0e300140 + jmp FPA_fd_fn_fm +ARM_instruction_rsfsp: + mov edx,0x0e300120 + jmp FPA_fd_fn_fm +ARM_instruction_rsfsz: + mov edx,0x0e300160 + jmp FPA_fd_fn_fm +ARM_instruction_sfm: + mov edx,0x0c000200 + jmp FPA_fd_imm_address5 +ARM_instruction_sfmea: + mov edx,0x0c800200 + jmp FPA_fd_imm_rn +ARM_instruction_sfmfd: + mov edx,0x0d000200 + jmp FPA_fd_imm_rn +ARM_instruction_sind: + mov edx,0x0e808180 + jmp FPA_fd_fm +ARM_instruction_sindm: + mov edx,0x0e8081c0 + jmp FPA_fd_fm +ARM_instruction_sindp: + mov edx,0x0e8081a0 + jmp FPA_fd_fm +ARM_instruction_sindz: + mov edx,0x0e8081e0 + jmp FPA_fd_fm +ARM_instruction_sine: + mov edx,0x0e888100 + jmp FPA_fd_fm +ARM_instruction_sinem: + mov edx,0x0e888140 + jmp FPA_fd_fm +ARM_instruction_sinep: + mov edx,0x0e888120 + jmp FPA_fd_fm +ARM_instruction_sinez: + mov edx,0x0e888160 + jmp FPA_fd_fm +ARM_instruction_sins: + mov edx,0x0e808100 + jmp FPA_fd_fm +ARM_instruction_sinsm: + mov edx,0x0e808140 + jmp FPA_fd_fm +ARM_instruction_sinsp: + mov edx,0x0e808120 + jmp FPA_fd_fm +ARM_instruction_sinsz: + mov edx,0x0e808160 + jmp FPA_fd_fm +ARM_instruction_sqtd: + mov edx,0x0e408180 + jmp FPA_fd_fm +ARM_instruction_sqtdm: + mov edx,0x0e4081c0 + jmp FPA_fd_fm +ARM_instruction_sqtdp: + mov edx,0x0e4081a0 + jmp FPA_fd_fm +ARM_instruction_sqtdz: + mov edx,0x0e4081e0 + jmp FPA_fd_fm +ARM_instruction_sqte: + mov edx,0x0e488100 + jmp FPA_fd_fm +ARM_instruction_sqtem: + mov edx,0x0e488140 + jmp FPA_fd_fm +ARM_instruction_sqtep: + mov edx,0x0e488120 + jmp FPA_fd_fm +ARM_instruction_sqtez: + mov edx,0x0e488160 + jmp FPA_fd_fm +ARM_instruction_sqts: + mov edx,0x0e408100 + jmp FPA_fd_fm +ARM_instruction_sqtsm: + mov edx,0x0e408140 + jmp FPA_fd_fm +ARM_instruction_sqtsp: + mov edx,0x0e408120 + jmp FPA_fd_fm +ARM_instruction_sqtsz: + mov edx,0x0e408160 + jmp FPA_fd_fm +ARM_instruction_stfd: + mov edx,0x0c008100 + jmp FPA_fd_address5 +ARM_instruction_stfe: + mov edx,0x0c400100 + jmp FPA_fd_address5 +ARM_instruction_stfp: + mov edx,0x0c408100 + jmp FPA_fd_address5 +ARM_instruction_stfs: + mov edx,0x0c000100 + jmp FPA_fd_address5 +ARM_instruction_sufd: + mov edx,0x0e200180 + jmp FPA_fd_fn_fm +ARM_instruction_sufdm: + mov edx,0x0e2001c0 + jmp FPA_fd_fn_fm +ARM_instruction_sufdp: + mov edx,0x0e2001a0 + jmp FPA_fd_fn_fm +ARM_instruction_sufdz: + mov edx,0x0e2001e0 + jmp FPA_fd_fn_fm +ARM_instruction_sufe: + mov edx,0x0e280100 + jmp FPA_fd_fn_fm +ARM_instruction_sufem: + mov edx,0x0e280140 + jmp FPA_fd_fn_fm +ARM_instruction_sufep: + mov edx,0x0e280120 + jmp FPA_fd_fn_fm +ARM_instruction_sufez: + mov edx,0x0e280160 + jmp FPA_fd_fn_fm +ARM_instruction_sufs: + mov edx,0x0e200100 + jmp FPA_fd_fn_fm +ARM_instruction_sufsm: + mov edx,0x0e200140 + jmp FPA_fd_fn_fm +ARM_instruction_sufsp: + mov edx,0x0e200120 + jmp FPA_fd_fn_fm +ARM_instruction_sufsz: + mov edx,0x0e200160 + jmp FPA_fd_fn_fm +ARM_instruction_tand: + mov edx,0x0ea08180 + jmp FPA_fd_fm +ARM_instruction_tandm: + mov edx,0x0ea081c0 + jmp FPA_fd_fm +ARM_instruction_tandp: + mov edx,0x0ea081a0 + jmp FPA_fd_fm +ARM_instruction_tandz: + mov edx,0x0ea081e0 + jmp FPA_fd_fm +ARM_instruction_tane: + mov edx,0x0ea88100 + jmp FPA_fd_fm +ARM_instruction_tanem: + mov edx,0x0ea88140 + jmp FPA_fd_fm +ARM_instruction_tanep: + mov edx,0x0ea88120 + jmp FPA_fd_fm +ARM_instruction_tanez: + mov edx,0x0ea88160 + jmp FPA_fd_fm +ARM_instruction_tans: + mov edx,0x0ea08100 + jmp FPA_fd_fm +ARM_instruction_tansm: + mov edx,0x0ea08140 + jmp FPA_fd_fm +ARM_instruction_tansp: + mov edx,0x0ea08120 + jmp FPA_fd_fm +ARM_instruction_tansz: + mov edx,0x0ea08160 + jmp FPA_fd_fm +ARM_instruction_urdd: + mov edx,0x0ee08180 + jmp FPA_fd_fm +ARM_instruction_urddm: + mov edx,0x0ee081c0 + jmp FPA_fd_fm +ARM_instruction_urddp: + mov edx,0x0ee081a0 + jmp FPA_fd_fm +ARM_instruction_urddz: + mov edx,0x0ee081e0 + jmp FPA_fd_fm +ARM_instruction_urde: + mov edx,0x0ee88100 + jmp FPA_fd_fm +ARM_instruction_urdem: + mov edx,0x0ee88140 + jmp FPA_fd_fm +ARM_instruction_urdep: + mov edx,0x0ee88120 + jmp FPA_fd_fm +ARM_instruction_urdez: + mov edx,0x0ee88160 + jmp FPA_fd_fm +ARM_instruction_urds: + mov edx,0x0ee08100 + jmp FPA_fd_fm +ARM_instruction_urdsm: + mov edx,0x0ee08140 + jmp FPA_fd_fm +ARM_instruction_urdsp: + mov edx,0x0ee08120 + jmp FPA_fd_fm +ARM_instruction_urdsz: + mov edx,0x0ee08160 + jmp FPA_fd_fm +ARM_instruction_wfc: + mov edx,0x0e400110 + jmp FPA_rd +ARM_instruction_wfs: + mov edx,0x0e200110 + jmp FPA_rd + +;Maverick jump table + +ARM_instruction_cfabs32: + mov edx,0x0e300500 + jmp MAVERICK_crd_crn +ARM_instruction_cfabs64: + mov edx,0x0e300520 + jmp MAVERICK_crd_crn +ARM_instruction_cfabsd: + mov edx,0x0e300420 + jmp MAVERICK_crd_crn +ARM_instruction_cfabss: + mov edx,0x0e300400 + jmp MAVERICK_crd_crn +ARM_instruction_cfadd32: + mov edx,0x0e300580 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfadd64: + mov edx,0x0e3005a0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfaddd: + mov edx,0x0e3004a0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfadds: + mov edx,0x0e300480 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfcmp32: + mov edx,0x0e100590 + jmp MAVERICK_rd_crn_crm +ARM_instruction_cfcmp64: + mov edx,0x0e1005b0 + jmp MAVERICK_rd_crn_crm +ARM_instruction_cfcmpd: + mov edx,0x0e1004b0 + jmp MAVERICK_rd_crn_crm +ARM_instruction_cfcmps: + mov edx,0x0e100490 + jmp MAVERICK_rd_crn_crm +ARM_instruction_cfcpyd: + mov edx,0x0e000420 + jmp MAVERICK_crd_crn +ARM_instruction_cfcpys: + mov edx,0x0e000400 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvt32d: + mov edx,0x0e0004a0 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvt32s: + mov edx,0x0e000480 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvt64d: + mov edx,0x0e0004e0 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvt64s: + mov edx,0x0e0004c0 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvtd32: + mov edx,0x0e1005a0 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvtds: + mov edx,0x0e000440 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvts32: + mov edx,0x0e100580 + jmp MAVERICK_crd_crn +ARM_instruction_cfcvtsd: + mov edx,0x0e000460 + jmp MAVERICK_crd_crn +ARM_instruction_cfldr32: + mov edx,0x0c100500 + jmp MAVERICK_crd_address5 +ARM_instruction_cfldr64: + mov edx,0x0c500500 + jmp MAVERICK_crd_address5 +ARM_instruction_cfldrd: + mov edx,0x0c500400 + jmp MAVERICK_crd_address5 +ARM_instruction_cfldrs: + mov edx,0x0c100400 + jmp MAVERICK_crd_address5 +ARM_instruction_cfmac32: + mov edx,0x0e100540 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmadd32: + mov edx,0x0e000600 + jmp MAVERICK_aa_crd_crn_crm +ARM_instruction_cfmadda32: + mov edx,0x0e200600 + jmp MAVERICK_aa_ad_crn_crm +ARM_instruction_cfmsc32: + mov edx,0x0e100560 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmsub32: + mov edx,0x0e100600 + jmp MAVERICK_aa_crd_crn_crm +ARM_instruction_cfmsuba32: + mov edx,0x0e300600 + jmp MAVERICK_aa_ad_crn_crm +ARM_instruction_cfmul32: + mov edx,0x0e100500 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmul64: + mov edx,0x0e100520 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmuld: + mov edx,0x0e100420 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmuls: + mov edx,0x0e100400 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfmv32a: + mov edx,0x0e1004a0 + jmp MAVERICK_crd_an +ARM_instruction_cfmv32ah: + mov edx,0x0e100480 + jmp MAVERICK_crd_an +ARM_instruction_cfmv32al: + mov edx,0x0e100440 + jmp MAVERICK_crd_an +ARM_instruction_cfmv32am: + mov edx,0x0e100460 + jmp MAVERICK_crd_an +ARM_instruction_cfmv32sc: + mov edx,0x0e1004e0 + jmp MAVERICK_crd_psc +ARM_instruction_cfmv64a: + mov edx,0x0e1004c0 + jmp MAVERICK_crd_an +ARM_instruction_cfmv64hr: + mov edx,0x0e000530 + jmp MAVERICK_crn_rd +ARM_instruction_cfmv64lr: + mov edx,0x0e000510 + jmp MAVERICK_crn_rd +ARM_instruction_cfmva32: + mov edx,0x0e2004a0 + jmp MAVERICK_ad_crn +ARM_instruction_cfmva64: + mov edx,0x0e2004c0 + jmp MAVERICK_ad_crn +ARM_instruction_cfmvah32: + mov edx,0x0e200480 + jmp MAVERICK_ad_crn +ARM_instruction_cfmval32: + mov edx,0x0e200440 + jmp MAVERICK_ad_crn +ARM_instruction_cfmvam32: + mov edx,0x0e200460 + jmp MAVERICK_ad_crn +ARM_instruction_cfmvdhr: + mov edx,0x0e000430 + jmp MAVERICK_crn_rd +ARM_instruction_cfmvdlr: + mov edx,0x0e000410 + jmp MAVERICK_crn_rd +ARM_instruction_cfmvr64h: + mov edx,0x0e100530 + jmp MAVERICK_rd_crn +ARM_instruction_cfmvr64l: + mov edx,0x0e100510 + jmp MAVERICK_rd_crn +ARM_instruction_cfmvrdh: + mov edx,0x0e100430 + jmp MAVERICK_rd_crn +ARM_instruction_cfmvrdl: + mov edx,0x0e100410 + jmp MAVERICK_rd_crn +ARM_instruction_cfmvrs: + mov edx,0x0e100450 + jmp MAVERICK_rd_crn +ARM_instruction_cfmvsc32: + mov edx,0x0e2004e0 + jmp MAVERICK_psc_crd +ARM_instruction_cfmvsr: + mov edx,0x0e000450 + jmp MAVERICK_crn_rd +ARM_instruction_cfneg32: + mov edx,0x0e300540 + jmp MAVERICK_crd_crn +ARM_instruction_cfneg64: + mov edx,0x0e300560 + jmp MAVERICK_crd_crn +ARM_instruction_cfnegd: + mov edx,0x0e300460 + jmp MAVERICK_crd_crn +ARM_instruction_cfnegs: + mov edx,0x0e300440 + jmp MAVERICK_crd_crn +ARM_instruction_cfrshl32: + mov edx,0x0e000550 + jmp MAVERICK_crm_crn_rd +ARM_instruction_cfrshl64: + mov edx,0x0e000570 + jmp MAVERICK_crm_crn_rd +ARM_instruction_cfsh32: + mov edx,0x0e000500 + jmp MAVERICK_crd_crn_imm +ARM_instruction_cfsh64: + mov edx,0x0e200500 + jmp MAVERICK_crd_crn_imm +ARM_instruction_cfstr32: + mov edx,0x0c000500 + jmp MAVERICK_crd_address5 +ARM_instruction_cfstr64: + mov edx,0x0c400500 + jmp MAVERICK_crd_address5 +ARM_instruction_cfstrd: + mov edx,0x0c400400 + jmp MAVERICK_crd_address5 +ARM_instruction_cfstrs: + mov edx,0x0c000400 + jmp MAVERICK_crd_address5 +ARM_instruction_cfsub32: + mov edx,0x0e3005c0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfsub64: + mov edx,0x0e3005e0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfsubd: + mov edx,0x0e3004e0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cfsubs: + mov edx,0x0e3004c0 + jmp MAVERICK_crd_crn_crm +ARM_instruction_cftruncd32: + mov edx,0x0e1005e0 + jmp MAVERICK_crd_crn +ARM_instruction_cftruncs32: + mov edx,0x0e1005c0 + jmp MAVERICK_crd_crn + +;VFP jump table + +ARM_instruction_fabsd: + mov edx,0x0eb00bc0 + jmp VFP_dd_dm +ARM_instruction_fabss: + mov edx,0x0eb00ac0 + jmp VFP_sd_sm +ARM_instruction_faddd: + mov edx,0x0e300b00 + jmp VFP_dd_dn_dm +ARM_instruction_fadds: + mov edx,0x0e300a00 + jmp VFP_sd_sn_sm +ARM_instruction_fcmpd: + mov edx,0x0eb40b40 + jmp VFP_dd_dm_zero +ARM_instruction_fcmped: + mov edx,0x0eb40bc0 + jmp VFP_dd_dm_zero +ARM_instruction_fcmpes: + mov edx,0x0eb40ac0 + jmp VFP_sd_sm_zero +ARM_instruction_fcmpezd: + mov edx,0x0eb50bc0 + jmp VFP_dd +ARM_instruction_fcmpezs: + mov edx,0x0eb50ac0 + jmp VFP_sd +ARM_instruction_fcmps: + mov edx,0x0eb40a40 + jmp VFP_sd_sm_zero +ARM_instruction_fcmpzd: + mov edx,0x0eb50b40 + jmp VFP_dd +ARM_instruction_fcmpzs: + mov edx,0x0eb50a40 + jmp VFP_sd +ARM_instruction_fconstd: + mov edx,0x0eb00b00 + jmp VFP_dm_imm +ARM_instruction_fconsts: + mov edx,0x0eb00a00 + jmp VFP_sm_imm +ARM_instruction_fcpyd: + mov edx,0x0eb00b40 + jmp VFP_dd_dm +ARM_instruction_fcpys: + mov edx,0x0eb00a40 + jmp VFP_sd_sm +ARM_instruction_fcvtds: + mov edx,0x0eb70ac0 + jmp VFP_dd_sm +ARM_instruction_fcvtsd: + mov edx,0x0eb70bc0 + jmp VFP_sd_dm +ARM_instruction_fdivd: + mov edx,0x0e800b00 + jmp VFP_dd_dn_dm +ARM_instruction_fdivs: + mov edx,0x0e800a00 + jmp VFP_sd_sn_sm +ARM_instruction_fldd: + mov edx,0x0d100b00 + jmp VFP_dd_rn_offset +ARM_instruction_fldmdbd: +ARM_instruction_fldmead: + mov edx,0xd100b00 + jmp VFP_rn_list_d +ARM_instruction_fldmdbx: +ARM_instruction_fldmeax: + mov edx,0xd100b01 + jmp VFP_rn_list_d +ARM_instruction_fldmdbs: +ARM_instruction_fldmeas: + mov edx,0xd100a00 + jmp VFP_rn_list_s +ARM_instruction_fldmd: +ARM_instruction_fldmiad: +ARM_instruction_fldmfdd: + mov edx,0xc900b00 + jmp VFP_rn_list_d +ARM_instruction_fldmx: +ARM_instruction_fldmiax: +ARM_instruction_fldmfdx: + mov edx,0xc900b01 + jmp VFP_rn_list_d +ARM_instruction_fldms: +ARM_instruction_fldmias: +ARM_instruction_fldmfds: + mov edx,0xc900a00 + jmp VFP_rn_list_s +ARM_instruction_flds: + mov edx,0x0d100a00 + jmp VFP_sd_rn_offset +ARM_instruction_fmacd: + mov edx,0x0e000b00 + jmp VFP_FLOAT_dd_dn_dm +ARM_instruction_fmacs: + mov edx,0x0e000a00 + jmp VFP_FLOAT_sd_sn_sm +ARM_instruction_fmdhr: + mov edx,0xe200b10 + jmp VFP_dn_rd +ARM_instruction_fmdlr: + mov edx,0xe000b10 + jmp VFP_dn_rd +ARM_instruction_fmdrr: + mov edx,0x0c400b10 + jmp VFP_dm_rd_rn +ARM_instruction_fmrdh: + mov edx,0x0e300b10 + jmp VFP_rd_dn +ARM_instruction_fmrdl: + mov edx,0x0e100b10 + jmp VFP_rd_dn +ARM_instruction_fmrrd: + mov edx,0x0c500b10 + jmp VFP_rd_rn_dm +ARM_instruction_fmrrs: + mov edx,0x0c500a10 + jmp VFP_rd_rn_sm +ARM_instruction_fmrs: + mov edx,0x0e100a10 + jmp VFP_rd_sn +ARM_instruction_fmrx: + mov edx,0x0ef00a10 + jmp VFP_rd_sysreg +ARM_instruction_fmscd: + mov edx,0x0e100b00 + jmp VFP_FLOAT_dd_dn_dm +ARM_instruction_fmscs: + mov edx,0x0e100a00 + jmp VFP_FLOAT_sd_sn_sm +ARM_instruction_fmsr: + mov edx,0x0e000a10 + jmp VFP_sn_rd +ARM_instruction_fmsrr: + mov edx,0x0c400a10 + jmp VFP_sm_rd_rn +ARM_instruction_fmstat: + mov edx,0x0ef1fa10 + jmp VFP_fmstat +ARM_instruction_fmuld: + mov edx,0x0e200b00 + jmp VFP_dd_dn_dm +ARM_instruction_fmuls: + mov edx,0x0e200a00 + jmp VFP_sd_sn_sm +ARM_instruction_fmxr: + mov edx,0x0ee00a10 + jmp VFP_sysreg_rd +ARM_instruction_fnegd: + mov edx,0x0eb10b40 + jmp VFP_dd_dm +ARM_instruction_fnegs: + mov edx,0x0eb10a40 + jmp VFP_sd_sm +ARM_instruction_fnmacd: + mov edx,0x0e000b40 + jmp VFP_FLOAT_dd_dn_dm +ARM_instruction_fnmacs: + mov edx,0x0e000a40 + jmp VFP_FLOAT_sd_sn_sm +ARM_instruction_fnmscd: + mov edx,0x0e100b40 + jmp VFP_FLOAT_dd_dn_dm +ARM_instruction_fnmscs: + mov edx,0x0e100a40 + jmp VFP_FLOAT_sd_sn_sm +ARM_instruction_fnmuld: + mov edx,0x0e200b40 + jmp VFP_dd_dn_dm +ARM_instruction_fnmuls: + mov edx,0x0e200a40 + jmp VFP_sd_sn_sm +ARM_instruction_fshtod: + mov edx,0x0eba0b40 + jmp VFP_dd_dd_imm +ARM_instruction_fshtos: + mov edx,0x0eba0a40 + jmp VFP_sd_sd_imm +ARM_instruction_fsitod: + mov edx,0x0eb80bc0 + jmp VFP_dd_sm +ARM_instruction_fsitos: + mov edx,0x0eb80ac0 + jmp VFP_sd_sm +ARM_instruction_fsltod: + mov edx,0x0eba0bc0 + jmp VFP_dd_dd_imm +ARM_instruction_fsltos: + mov edx,0x0eba0ac0 + jmp VFP_sd_sd_imm +ARM_instruction_fsqrtd: + mov edx,0x0eb10bc0 + jmp VFP_dd_dm +ARM_instruction_fsqrts: + mov edx,0x0eb10ac0 + jmp VFP_sd_sm +ARM_instruction_fstd: + mov edx,0x0d000b00 + jmp VFP_dd_rn_offset +ARM_instruction_fstmdbd: +ARM_instruction_fstmfdd: + mov edx,0xd000b00 + jmp VFP_rn_list_d +ARM_instruction_fstmdbx: +ARM_instruction_fstmfdx: + mov edx,0xd000b01 + jmp VFP_rn_list_d +ARM_instruction_fstmdbs: +ARM_instruction_fstmfds: + mov edx,0xd000a00 + jmp VFP_rn_list_s +ARM_instruction_fstmd: +ARM_instruction_fstmiad: +ARM_instruction_fstmead: + mov edx,0xc800b00 + jmp VFP_rn_list_d +ARM_instruction_fstmx: +ARM_instruction_fstmiax: +ARM_instruction_fstmeax: + mov edx,0xc800b01 + jmp VFP_rn_list_d +ARM_instruction_fstms: +ARM_instruction_fstmias: +ARM_instruction_fstmeas: + mov edx,0xc800a00 + jmp VFP_rn_list_s +ARM_instruction_fsts: + mov edx,0x0d000a00 + jmp VFP_sd_rn_offset +ARM_instruction_fsubd: + mov edx,0x0e300b40 + jmp VFP_dd_dn_dm +ARM_instruction_fsubs: + mov edx,0x0e300a40 + jmp VFP_sd_sn_sm +ARM_instruction_ftoshd: + mov edx,0x0ebe0b40 + jmp VFP_dd_dd_imm +ARM_instruction_ftoshs: + mov edx,0x0ebe0a40 + jmp VFP_sd_sd_imm +ARM_instruction_ftosid: + mov edx,0x0ebd0b40 + jmp VFP_sd_dm +ARM_instruction_ftosis: + mov edx,0x0ebd0a40 + jmp VFP_sd_sm +ARM_instruction_ftosizd: + mov edx,0x0ebd0bc0 + jmp VFP_sd_dm +ARM_instruction_ftosizs: + mov edx,0x0ebd0ac0 + jmp VFP_sd_sm +ARM_instruction_ftosld: + mov edx,0x0ebe0bc0 + jmp VFP_dd_dd_imm +ARM_instruction_ftosls: + mov edx,0x0ebe0ac0 + jmp VFP_sd_sd_imm +ARM_instruction_ftouhd: + mov edx,0x0ebf0b40 + jmp VFP_dd_dd_imm +ARM_instruction_ftouhs: + mov edx,0x0ebf0a40 + jmp VFP_sd_sd_imm +ARM_instruction_ftouid: + mov edx,0x0ebc0b40 + jmp VFP_sd_dm +ARM_instruction_ftouis: + mov edx,0x0ebc0a40 + jmp VFP_sd_sm +ARM_instruction_ftouizd: + mov edx,0x0ebc0bc0 + jmp VFP_sd_dm +ARM_instruction_ftouizs: + mov edx,0x0ebc0ac0 + jmp VFP_sd_sm +ARM_instruction_ftould: + mov edx,0x0ebf0bc0 + jmp VFP_dd_dd_imm +ARM_instruction_ftouls: + mov edx,0x0ebf0ac0 + jmp VFP_sd_sd_imm +ARM_instruction_fuhtod: + mov edx,0x0ebb0b40 + jmp VFP_dd_dd_imm +ARM_instruction_fuhtos: + mov edx,0x0ebb0a40 + jmp VFP_sd_sd_imm +ARM_instruction_fuitod: + mov edx,0x0eb80b40 + jmp VFP_dd_sm +ARM_instruction_fuitos: + mov edx,0x0eb80a40 + jmp VFP_sd_sm +ARM_instruction_fultod: + mov edx,0x0ebb0bc0 + jmp VFP_dd_dd_imm +ARM_instruction_fultos: + mov edx,0x0ebb0ac0 + jmp VFP_sd_sd_imm +ARM_instruction_vcvtb.f16.f32: + mov edx,0x0eb30a40 + jmp VFP_sd_sm_HP +ARM_instruction_vcvtb.f32.f16: + mov edx,0x0eb20a40 + jmp VFP_sd_sm_HP +ARM_instruction_vcvtt.f16.f32: + mov edx,0x0eb30ac0 + jmp VFP_sd_sm_HP +ARM_instruction_vcvtt.f32.f16: + mov edx,0x0eb20ac0 + jmp VFP_sd_sm_HP + +;xScale jump table + +ARM_instruction_mar: + mov edx,0x0c400000 + jmp XSCALE_acc_rdlo_rdhi +ARM_instruction_mia: + mov edx,0x0e200010 + jmp XSCALE_acc_rm_rs +ARM_instruction_miabb: + mov edx,0x0e2c0010 + jmp XSCALE_acc_rm_rs +ARM_instruction_miabt: + mov edx,0x0e2d0010 + jmp XSCALE_acc_rm_rs +ARM_instruction_miaph: + mov edx,0x0e280010 + jmp XSCALE_acc_rm_rs +ARM_instruction_miatb: + mov edx,0x0e2e0010 + jmp XSCALE_acc_rm_rs +ARM_instruction_miatt: + mov edx,0x0e2f0010 + jmp XSCALE_acc_rm_rs +ARM_instruction_mra: + mov edx,0x0c500000 + jmp XSCALE_rdlo_rdhi_acc + +;IWMMXT v1 jump table + +ARM_instruction_tandcb: + mov edx,0x0e13f130 + jmp IWMMXT_r15 +ARM_instruction_tandch: + mov edx,0x0e53f130 + jmp IWMMXT_r15 +ARM_instruction_tandcw: + mov edx,0x0e93f130 + jmp IWMMXT_r15 +ARM_instruction_tbcstb: + mov edx,0x0e400010 + jmp IWMMXT_wrd_rn +ARM_instruction_tbcsth: + mov edx,0x0e400050 + jmp IWMMXT_wrd_rn +ARM_instruction_tbcstw: + mov edx,0x0e400090 + jmp IWMMXT_wrd_rn +ARM_instruction_textrcb: + mov edx,0x0e13f170 + jmp IWMMXT_r15_imm +ARM_instruction_textrch: + mov edx,0x0e53f170 + jmp IWMMXT_r15_imm +ARM_instruction_textrcw: + mov edx,0x0e93f170 + jmp IWMMXT_r15_imm +ARM_instruction_textrmsb: + mov edx,0x0e100078 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_textrmsh: + mov edx,0x0e500078 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_textrmsw: + mov edx,0x0e900078 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_textrmub: + mov edx,0x0e100070 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_textrmuh: + mov edx,0x0e500070 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_textrmuw: + mov edx,0x0e900070 + jmp IWMMXT_rd_wrn_imm +ARM_instruction_tinsrb: + mov edx,0x0e600010 + jmp IWMMXT_wrd_rn_imm +ARM_instruction_tinsrh: + mov edx,0x0e600050 + jmp IWMMXT_wrd_rn_imm +ARM_instruction_tinsrw: + mov edx,0x0e600090 + jmp IWMMXT_wrd_rn_imm +ARM_instruction_tmcr: + mov edx,0x0e000110 + jmp IWMMXT_wcd_rn +ARM_instruction_tmcrr: + mov edx,0x0c400000 + jmp IWMMXT_wrd_rdlo_rdhi +ARM_instruction_tmia: + mov edx,0x0e200010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmiabb: + mov edx,0x0e2c0010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmiabt: + mov edx,0x0e2d0010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmiaph: + mov edx,0x0e280010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmiatb: + mov edx,0x0e2e0010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmiatt: + mov edx,0x0e2f0010 + jmp IWMMXT_wrd_rm_rs +ARM_instruction_tmovmskb: + mov edx,0x0e100030 + jmp IWMMXT_rd_wrn +ARM_instruction_tmovmskh: + mov edx,0x0e500030 + jmp IWMMXT_rd_wrn +ARM_instruction_tmovmskw: + mov edx,0x0e900030 + jmp IWMMXT_rd_wrn +ARM_instruction_tmrc: + mov edx,0x0e100110 + jmp IWMMXT_rd_wcn +ARM_instruction_tmrrc: + mov edx,0x0c500000 + jmp IWMMXT_rdlo_rdhi_wrn +ARM_instruction_torcb: + mov edx,0x0e13f150 + jmp IWMMXT_r15 +ARM_instruction_torch: + mov edx,0x0e53f150 + jmp IWMMXT_r15 +ARM_instruction_torcw: + mov edx,0x0e93f150 + jmp IWMMXT_r15 +ARM_instruction_waccb: + mov edx,0x0e0001c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wacch: + mov edx,0x0e4001c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_waccw: + mov edx,0x0e8001c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_waddb: + mov edx,0x0e000180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddbss: + mov edx,0x0e300180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddbus: + mov edx,0x0e100180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddh: + mov edx,0x0e400180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddhss: + mov edx,0x0e700180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddhus: + mov edx,0x0e500180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddw: + mov edx,0x0e800180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddwss: + mov edx,0x0eb00180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waddwus: + mov edx,0x0e900180 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_waligni: + mov edx,0x0e000020 + jmp IWMMXT_wrd_wrn_wrm_imm +ARM_instruction_walignr0: + mov edx,0x0e800020 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_walignr1: + mov edx,0x0e900020 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_walignr2: + mov edx,0x0ea00020 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_walignr3: + mov edx,0x0eb00020 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wand: + mov edx,0x0e200000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wandn: + mov edx,0x0e300000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wavg2b: + mov edx,0x0e800000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wavg2br: + mov edx,0x0e900000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wavg2h: + mov edx,0x0ec00000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wavg2hr: + mov edx,0x0ed00000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpeqb: + mov edx,0x0e000060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpeqh: + mov edx,0x0e400060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpeqw: + mov edx,0x0e800060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtsb: + mov edx,0x0e300060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtsh: + mov edx,0x0e700060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtsw: + mov edx,0x0eb00060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtub: + mov edx,0x0e100060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtuh: + mov edx,0x0e500060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wcmpgtuw: + mov edx,0x0e900060 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wldrb: + mov edx,0x0c100000 + jmp IWMMXT_wrd_address5 +ARM_instruction_wldrd: + mov edx,0x0c500100 + jmp IWMMXT_wrd_address5_reg_offset +ARM_instruction_wldrh: + mov edx,0x0c500000 + jmp IWMMXT_wrd_address5 +ARM_instruction_wldrw: + mov edx,0x0c100100 + jmp IWMMXT_wrd_address5 +ARM_instruction_wmacs: + mov edx,0x0e600100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmacsz: + mov edx,0x0e700100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmacu: + mov edx,0x0e400100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmacuz: + mov edx,0x0e500100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmadds: + mov edx,0x0ea00100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaddu: + mov edx,0x0e800100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxsb: + mov edx,0x0e200160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxsh: + mov edx,0x0e600160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxsw: + mov edx,0x0ea00160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxub: + mov edx,0x0e000160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxuh: + mov edx,0x0e400160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmaxuw: + mov edx,0x0e800160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminsb: + mov edx,0x0e300160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminsh: + mov edx,0x0e700160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminsw: + mov edx,0x0eb00160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminub: + mov edx,0x0e100160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminuh: + mov edx,0x0e500160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wminuw: + mov edx,0x0e900160 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmov: + mov edx,0x0e000000 + jmp IWMMXT_wrd_wrn_WMOV +ARM_instruction_wmulsl: + mov edx,0x0e200100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmulsm: + mov edx,0x0e300100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmulul: + mov edx,0x0e000100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wmulum: + mov edx,0x0e100100 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wor: + mov edx,0x0e000000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackdss: + mov edx,0x0ef00080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackdus: + mov edx,0x0ed00080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackhss: + mov edx,0x0e700080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackhus: + mov edx,0x0e500080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackwss: + mov edx,0x0eb00080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wpackwus: + mov edx,0x0e900080 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wrord: + mov edx,0x0ef00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wrordg: + mov edx,0x0ef00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wrorh: + mov edx,0x0e700040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wrorhg: + mov edx,0x0e700140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wrorw: + mov edx,0x0eb00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wrorwg: + mov edx,0x0eb00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsadb: + mov edx,0x0e000120 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsadbz: + mov edx,0x0e100120 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsadh: + mov edx,0x0e400120 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsadhz: + mov edx,0x0e500120 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wshufh: + mov edx,0x0e0001e0 + jmp IWMMXT_wrd_wrn_imm +ARM_instruction_wslld: + mov edx,0x0ed00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wslldg: + mov edx,0x0ed00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsllh: + mov edx,0x0e500040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsllhg: + mov edx,0x0e500140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsllw: + mov edx,0x0e900040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsllwg: + mov edx,0x0e900140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsrad: + mov edx,0x0ec00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsradg: + mov edx,0x0ec00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsrah: + mov edx,0x0e400040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsrahg: + mov edx,0x0e400140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsraw: + mov edx,0x0e800040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsrawg: + mov edx,0x0e800140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsrld: + mov edx,0x0ee00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsrldg: + mov edx,0x0ee00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsrlh: + mov edx,0x0e600040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsrlhg: + mov edx,0x0e600140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wsrlw: + mov edx,0x0ea00040 + jmp IWMMXT_wrd_wrn_param +ARM_instruction_wsrlwg: + mov edx,0x0ea00140 + jmp IWMMXT_wrd_wrn_wcm +ARM_instruction_wstrb: + mov edx,0x0c000000 + jmp IWMMXT_wrd_address5 +ARM_instruction_wstrd: + mov edx,0x0c400100 + jmp IWMMXT_wrd_address5_reg_offset +ARM_instruction_wstrh: + mov edx,0x0c400000 + jmp IWMMXT_wrd_address5 +ARM_instruction_wstrw: + mov edx,0x0c000100 + jmp IWMMXT_wrd_address5 +ARM_instruction_wsubb: + mov edx,0x0e0001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubbss: + mov edx,0x0e3001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubbus: + mov edx,0x0e1001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubh: + mov edx,0x0e4001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubhss: + mov edx,0x0e7001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubhus: + mov edx,0x0e5001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubw: + mov edx,0x0e8001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubwss: + mov edx,0x0eb001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wsubwus: + mov edx,0x0e9001a0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckehsb: + mov edx,0x0e2000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckehsh: + mov edx,0x0e6000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckehsw: + mov edx,0x0ea000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckehub: + mov edx,0x0e0000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckehuh: + mov edx,0x0e4000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckehuw: + mov edx,0x0e8000c0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckelsb: + mov edx,0x0e2000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckelsh: + mov edx,0x0e6000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckelsw: + mov edx,0x0ea000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckelub: + mov edx,0x0e0000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckeluh: + mov edx,0x0e4000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckeluw: + mov edx,0x0e8000e0 + jmp IWMMXT_wrd_wrn +ARM_instruction_wunpckihb: + mov edx,0x0e1000c0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckihh: + mov edx,0x0e5000c0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckihw: + mov edx,0x0e9000c0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckilb: + mov edx,0x0e1000e0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckilh: + mov edx,0x0e5000e0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wunpckilw: + mov edx,0x0e9000e0 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wxor: + mov edx,0x0e100000 + jmp IWMMXT_wrd_wrn_wrm +ARM_instruction_wzero: + mov edx,0x0e300000 + jmp IWMMXT_wrd +;IWMMXT V2 jump table +ARM_instruction_torvscb: + mov edx,0x0e12f190 + jmp IWMMXT_r15_v2 +ARM_instruction_torvsch: + mov edx,0x0e52f190 + jmp IWMMXT_r15_v2 +ARM_instruction_torvscw: + mov edx,0x0e92f190 + jmp IWMMXT_r15_v2 +ARM_instruction_wabsb: + mov edx,0x0e2001c0 + jmp IWMMXT_rd_rn_v2 +ARM_instruction_wabsh: + mov edx,0x0e6001c0 + jmp IWMMXT_rd_rn_v2 +ARM_instruction_wabsw: + mov edx,0x0ea001c0 + jmp IWMMXT_rd_rn_v2 +ARM_instruction_wabsdiffb: + mov edx,0x0e1001c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wabsdiffh: + mov edx,0x0e5001c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wabsdiffw: + mov edx,0x0e9001c0 + jmp IWMMXT_rd_rn_rm_v2 +;;ARM_instruction_waddbhusl: +;; mov edx,0x0e2001a0 +;; jmp IWMMXT_rd_rn_rm_v2 +;;ARM_instruction_waddbhusm: +;; mov edx,0x0e6001a0 +;; jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_waddhc: + mov edx,0x0e600180 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_waddwc: + mov edx,0x0ea00180 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_waddsubhx: + mov edx,0x0ea001a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wavg4: + mov edx,0x0e400000 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wavg4r: + mov edx,0x0e500000 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmaddsn: + mov edx,0x0ee00100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmaddsx: + mov edx,0x0eb00100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmaddun: + mov edx,0x0ec00100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmaddux: + mov edx,0x0e900100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmerge: + mov edx,0x0e000080 + jmp IWMMXT_rd_rn_rm_imm +ARM_instruction_wmiabb: + mov edx,0x0e0000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiabt: + mov edx,0x0e1000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiatb: + mov edx,0x0e2000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiatt: + mov edx,0x0e3000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiabbn: + mov edx,0x0e4000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiabtn: + mov edx,0x0e5000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiatbn: + mov edx,0x0e6000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiattn: + mov edx,0x0e7000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawbb: + mov edx,0x0e800120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawbt: + mov edx,0x0e900120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawtb: + mov edx,0x0ea00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawtt: + mov edx,0x0eb00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawbbn: + mov edx,0x0ec00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawbtn: + mov edx,0x0ed00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawtbn: + mov edx,0x0ee00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmiawttn: + mov edx,0x0ef00120 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulsmr: + mov edx,0x0ef00100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulumr: + mov edx,0x0ed00100 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulwumr: + mov edx,0x0ec000c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulwsmr: + mov edx,0x0ee000c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulwum: + mov edx,0x0ed000c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulwsm: + mov edx,0x0ef000c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wmulwl: + mov edx,0x0eb000c0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiabb: + mov edx,0x0e8000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiabt: + mov edx,0x0e9000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiatb: + mov edx,0x0ea000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiatt: + mov edx,0x0eb000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiabbn: + mov edx,0x0ec000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiabtn: + mov edx,0x0ed000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiatbn: + mov edx,0x0ee000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmiattn: + mov edx,0x0ef000a0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmulm: + mov edx,0x0e100080 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmulmr: + mov edx,0x0e300080 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmulwm: + mov edx,0x0ec000e0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wqmulwmr: + mov edx,0x0ee000e0 + jmp IWMMXT_rd_rn_rm_v2 +ARM_instruction_wsubaddhx: + mov edx,0x0ed001c0 + jmp IWMMXT_rd_rn_rm_v2 + +;SIMD int & float jump table, with some aliases to VFP opcodes + +ARM_instruction_vaba.s16: + mov edx,0xf2100710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vaba.s32: + mov edx,0xf2200710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vaba.s8: + mov edx,0xf2000710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vaba.u16: + mov edx,0xf3100710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vaba.u32: + mov edx,0xf3200710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vaba.u8: + mov edx,0xf3000710 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vabal.s16: + mov edx,0xf2900500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabal.s32: + mov edx,0xf2a00500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabal.s8: + mov edx,0xf2800500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabal.u16: + mov edx,0xf3900500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabal.u32: + mov edx,0xf3a00500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabal.u8: + mov edx,0xf3800500 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabd.f32: + mov edx,0xf3200d00 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vabd.s16: + mov edx,0xf2100700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabd.s32: + mov edx,0xf2200700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabd.s8: + mov edx,0xf2000700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabd.u16: + mov edx,0xf3100700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabd.u32: + mov edx,0xf3200700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabd.u8: + mov edx,0xf3000700 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vabdl.s16: + mov edx,0xf2900700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabdl.s32: + mov edx,0xf2a00700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabdl.s8: + mov edx,0xf2800700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabdl.u16: + mov edx,0xf3900700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabdl.u32: + mov edx,0xf3a00700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabdl.u8: + mov edx,0xf3800700 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vabs.f32: + mov edx,0xf3b90700 + mov ecx,0x0eb00ac0 + jmp SIMD_FLOAT_vd_vm_f32 +ARM_instruction_vabs.f64 = ARM_instruction_fabsd +ARM_instruction_vabs.s16: + mov edx,0xf3b50300 + jmp SIMD_INT_vd_vm +ARM_instruction_vabs.s32: + mov edx,0xf3b90300 + jmp SIMD_INT_vd_vm +ARM_instruction_vabs.s8: + mov edx,0xf3b10300 + jmp SIMD_INT_vd_vm +ARM_instruction_vacge.f32: + mov edx,0xf3000e10 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vacgt.f32: + mov edx,0xf3200e10 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vacle.f32: + mov edx,0xf3000e10 + jmp SIMD_FLOAT_vd_vm_vn_alt +ARM_instruction_vaclt.f32: + mov edx,0xf3200e10 + jmp SIMD_FLOAT_vd_vm_vn_alt +ARM_instruction_vadd.f32: + mov edx,0xf2000d00 + mov ecx,0x0e300a00 + jmp SIMD_FLOAT_vd_vn_vm_f32 +ARM_instruction_vadd.f64 = ARM_instruction_faddd +ARM_instruction_vadd.i16: + mov edx,0xf2100800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vadd.i32: + mov edx,0xf2200800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vadd.i64: + mov edx,0xf2300800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vadd.i8: + mov edx,0xf2000800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vaddhn.i16: + mov edx,0xf2800400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vaddhn.i32: + mov edx,0xf2900400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vaddhn.i64: + mov edx,0xf2a00400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vaddl.s16: + mov edx,0xf2900000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddl.s32: + mov edx,0xf2a00000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddl.s8: + mov edx,0xf2800000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddl.u16: + mov edx,0xf3900000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddl.u32: + mov edx,0xf3a00000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddl.u8: + mov edx,0xf3800000 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vaddw.s16: + mov edx,0xf2900100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vaddw.s32: + mov edx,0xf2a00100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vaddw.s8: + mov edx,0xf2800100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vaddw.u16: + mov edx,0xf3900100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vaddw.u32: + mov edx,0xf3a00100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vaddw.u8: + mov edx,0xf3800100 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vand.i16: + mov edx,0xf2800931 + jmp SIMD_INT_vd_imm +ARM_instruction_vand.i32: + mov edx,0xf2800131 + jmp SIMD_INT_vd_imm +ARM_instruction_vand: + mov edx,0xf2000110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vbic.i16: + mov edx,0xf2800930 + jmp SIMD_INT_vd_imm +ARM_instruction_vbic.i32: + mov edx,0xf2800130 + jmp SIMD_INT_vd_imm +ARM_instruction_vbic: + mov edx,0xf2100110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vbif: + mov edx,0xf3300110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vbit: + mov edx,0xf3200110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vbsl: + mov edx,0xf3100110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vceq.f32: + mov edx,0xf2000e00 + mov ecx,0xf3b90500 + jmp SIMD_FLOAT_vd_vn_vm_alt_zero +ARM_instruction_vceq.i16: + mov edx,0xf3100810 + mov ecx,0xf3b50100 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vceq.i32: + mov edx,0xf3200810 + mov ecx,0xf3b90100 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vceq.i8: + mov edx,0xf3000810 + mov ecx,0xf3b10100 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcge.f32: + mov edx,0xf3000e00 + mov ecx,0xf3b90480 + jmp SIMD_FLOAT_vd_vn_vm_alt_zero +ARM_instruction_vcge.s16: + mov edx,0xf2100310 + mov ecx,0xf3b50080 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcge.s32: + mov edx,0xf2200310 + mov ecx,0xf3b90080 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcge.s8: + mov edx,0xf2000310 + mov ecx,0xf3b10080 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcge.u16: + mov edx,0xf3100310 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcge.u32: + mov edx,0xf3200310 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcge.u8: + mov edx,0xf3000310 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcgt.f32: + mov edx,0xf3200e00 + mov ecx,0xf3b90400 + jmp SIMD_FLOAT_vd_vn_vm_alt_zero +ARM_instruction_vcgt.s16: + mov edx,0xf2100300 + mov ecx,0xf3b50000 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcgt.s32: + mov edx,0xf2200300 + mov ecx,0xf3b90000 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcgt.s8: + mov edx,0xf2000300 + mov ecx,0xf3b10000 + jmp SIMD_INT_vd_vn_vm_alt_zero +ARM_instruction_vcgt.u16: + mov edx,0xf3100300 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcgt.u32: + mov edx,0xf3200300 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcgt.u8: + mov edx,0xf3000300 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vcle.f32: + mov edx,0xf3000e00 + mov ecx,0xf3b90580 + jmp SIMD_FLOAT_vd_vn_vm_alt_zero_swap +ARM_instruction_vcle.s16: + mov edx,0xf2100310 + mov ecx,0xf3b50180 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vcle.s32: + mov edx,0xf2200310 + mov ecx,0xf3b90180 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vcle.s8: + mov edx,0xf2000310 + mov ecx,0xf3b10180 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vcle.u16: + mov edx,0xf3100310 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vcle.u32: + mov edx,0xf3200310 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vcle.u8: + mov edx,0xf3000310 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vcls.s16: + mov edx,0xf3b40400 + jmp SIMD_INT_vd_vm +ARM_instruction_vcls.s32: + mov edx,0xf3b80400 + jmp SIMD_INT_vd_vm +ARM_instruction_vcls.s8: + mov edx,0xf3b00400 + jmp SIMD_INT_vd_vm +ARM_instruction_vclt.f32: + mov edx,0xf3200e00 + mov ecx,0xf3b90600 + jmp SIMD_FLOAT_vd_vn_vm_alt_zero_swap +ARM_instruction_vclt.s16: + mov edx,0xf2100300 + mov ecx,0xf3b50200 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vclt.s32: + mov edx,0xf2200300 + mov ecx,0xf3b90200 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vclt.s8: + mov edx,0xf2000300 + mov ecx,0xf3b10200 + jmp SIMD_INT_vd_vn_vm_alt_zero_swap +ARM_instruction_vclt.u16: + mov edx,0xf3100300 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vclt.u32: + mov edx,0xf3200300 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vclt.u8: + mov edx,0xf3000300 + jmp SIMD_INT_vd_vn_vm_alt_swap +ARM_instruction_vclz.i16: + mov edx,0xf3b40480 + jmp SIMD_INT_vd_vm +ARM_instruction_vclz.i32: + mov edx,0xf3b80480 + jmp SIMD_INT_vd_vm +ARM_instruction_vclz.i8: + mov edx,0xf3b00480 + jmp SIMD_INT_vd_vm +ARM_instruction_vcmp.f32 = ARM_instruction_fcmps +ARM_instruction_vcmp.f64 = ARM_instruction_fcmpd +ARM_instruction_vcmpe.f32 = ARM_instruction_fcmpes +ARM_instruction_vcmpe.f64 = ARM_instruction_fcmped +ARM_instruction_vcnt.8: + mov edx,0xf3b00500 + jmp SIMD_INT_vd_vm +ARM_instruction_vcvt.f16.f32: + mov edx,0xf3b60600 + jmp SIMD_FLOAT_dd_qm +ARM_instruction_vcvt.f32.f16: + mov edx,0xf3b60700 + jmp SIMD_FLOAT_qd_dm +ARM_instruction_vcvt.f32.f64 = ARM_instruction_fcvtsd +ARM_instruction_vcvt.f32.s16 = ARM_instruction_fshtos +ARM_instruction_vcvt.f32.s32: + mov edx,0xf3bb0600 + mov ecx,0x0eb80ac0 ;FSITOS + jmp SIMD_FLOAT_vd_vm_imm +ARM_instruction_vcvt.f32.u16 = ARM_instruction_fuhtos +ARM_instruction_vcvt.f32.u32: + mov edx,0xf3bb0680 + mov ecx,0x0eb80a40 ;FUITOS + jmp SIMD_FLOAT_vd_vm_imm +ARM_instruction_vcvt.f64.f32 = ARM_instruction_fcvtds +ARM_instruction_vcvt.f64.s16 = ARM_instruction_fshtod +ARM_instruction_vcvt.f64.s32: + mov edx,0x0eb80bc0 ;FSITOD + mov ecx,0x0eba0bc0 ;FSLTOD + jmp SIMD_FLOAT_dd_sm_CVT +ARM_instruction_vcvt.f64.u16 = ARM_instruction_fuhtod +ARM_instruction_vcvt.f64.u32: + mov edx,0x0eb80b40 ;FUITOD + mov ecx,0x0ebb0bc0 ;FULTOD + jmp SIMD_FLOAT_dd_sm_CVT +ARM_instruction_vcvt.s16.f32 = ARM_instruction_ftoshs +ARM_instruction_vcvt.s16.f64 = ARM_instruction_ftoshd +ARM_instruction_vcvt.s32.f32: + mov edx,0xf3bb0700 + mov ecx,0x0ebd0ac0 ;FTOSIZS + jmp SIMD_FLOAT_vd_vm_imm +ARM_instruction_vcvt.s32.f64: + mov edx,0x0ebd0bc0 ;FTOSIZD + mov ecx,0x0ebe0bc0 ;FTOSLD + jmp SIMD_FLOAT_sd_dm_CVT +ARM_instruction_vcvt.u16.f32 = ARM_instruction_ftouhs +ARM_instruction_vcvt.u16.f64 = ARM_instruction_ftouhd +ARM_instruction_vcvt.u32.f32: + mov edx,0xf3bb0780 + mov ecx,0x0ebc0ac0 ;FTOUIZS + jmp SIMD_FLOAT_vd_vm_imm +ARM_instruction_vcvt.u32.f64: + mov edx,0x0ebc0bc0 ;FTOUIZD + mov ecx,0x0ebf0bc0 ;FTOULD + jmp SIMD_FLOAT_sd_dm_CVT +ARM_instruction_vcvtr.s32.f32 = ARM_instruction_ftosis +ARM_instruction_vcvtr.s32.f64 = ARM_instruction_ftosid +ARM_instruction_vcvtr.u32.f32 = ARM_instruction_ftouis +ARM_instruction_vcvtr.u32.f64 = ARM_instruction_ftouid +ARM_instruction_vdiv.f32 = ARM_instruction_fdivs +ARM_instruction_vdiv.f64 = ARM_instruction_fdivd +ARM_instruction_vdup.16: + mov edx,0xf3b20c00 + mov ecx,0x0e800b30 + jmp SIMD_INT_qd_dmx +ARM_instruction_vdup.32: + mov edx,0xf3b30c00 + mov ecx,0x0e800b10 + jmp SIMD_INT_qd_dmx +ARM_instruction_vdup.8: + mov edx,0xf3b10c00 + mov ecx,0x0ec00b10 + jmp SIMD_INT_qd_dmx +ARM_instruction_veor: + mov edx,0xf3000110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vext.16: + mov edx,0xf2b00200 + jmp SIMD_INT_vd_vn_vm_imm +ARM_instruction_vext.32: + mov edx,0xf2b00400 + jmp SIMD_INT_vd_vn_vm_imm +ARM_instruction_vext.64: + mov edx,0xf2b00800 + jmp SIMD_INT_vd_vn_vm_imm +ARM_instruction_vext.8: + mov edx,0xf2b00100 + jmp SIMD_INT_vd_vn_vm_imm +ARM_instruction_vhadd.s16: + mov edx,0xf2100000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhadd.s32: + mov edx,0xf2200000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhadd.s8: + mov edx,0xf2000000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhadd.u16: + mov edx,0xf3100000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhadd.u32: + mov edx,0xf3200000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhadd.u8: + mov edx,0xf3000000 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.s16: + mov edx,0xf2100200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.s32: + mov edx,0xf2200200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.s8: + mov edx,0xf2000200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.u16: + mov edx,0xf3100200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.u32: + mov edx,0xf3200200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vhsub.u8: + mov edx,0xf3000200 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vld1.16: + mov edx,0xf4200040 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vld1.32: + mov edx,0xf4200080 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vld1.64: + mov edx,0xf42000c0 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vld1.8: + mov edx,0xf4200000 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vld2.16: + mov edx,0xf4200040 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vld2.32: + mov edx,0xf4200080 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vld2.8: + mov edx,0xf4200000 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vld3.16: + mov edx,0xf4200040 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vld3.32: + mov edx,0xf4200080 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vld3.8: + mov edx,0xf4200000 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vld4.16: + mov edx,0xf4200040 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vld4.32: + mov edx,0xf4200080 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vld4.8: + mov edx,0xf4200000 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vldm.32 = ARM_instruction_fldmias +ARM_instruction_vldm.64 = ARM_instruction_fldmiad +ARM_instruction_vldmdb.32 = ARM_instruction_fldmdbs +ARM_instruction_vldmdb.64 = ARM_instruction_fldmdbd +ARM_instruction_vldmfd.32 = ARM_instruction_fldmfds +ARM_instruction_vldmfd.64 = ARM_instruction_fldmfdd +ARM_instruction_vldmea.32 = ARM_instruction_fldmeas +ARM_instruction_vldmea.64 = ARM_instruction_fldmead +ARM_instruction_vldmia.32 = ARM_instruction_fldmias +ARM_instruction_vldmia.64 = ARM_instruction_fldmiad +ARM_instruction_vldmea: +ARM_instruction_vldmdb: + mov edx,0xd100a00 + jmp SIMD_INT_rn_list +ARM_instruction_vldm: +ARM_instruction_vldmfd: +ARM_instruction_vldmia: + mov edx,0xc900a00 + jmp SIMD_INT_rn_list +ARM_instruction_vldr.32 = ARM_instruction_flds +ARM_instruction_vldr.64 = ARM_instruction_fldd +ARM_instruction_vldr: + mov edx,0x0d100a00 + jmp SIMD_INT_vd_rn_offset +ARM_instruction_vmax.f32: + mov edx,0xf2000f00 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vmax.s16: + mov edx,0xf2100600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmax.s32: + mov edx,0xf2200600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmax.s8: + mov edx,0xf2000600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmax.u16: + mov edx,0xf3100600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmax.u32: + mov edx,0xf3200600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmax.u8: + mov edx,0xf3000600 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.f32: + mov edx,0xf2200f00 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vmin.s16: + mov edx,0xf2100610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.s32: + mov edx,0xf2200610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.s8: + mov edx,0xf2000610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.u16: + mov edx,0xf3100610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.u32: + mov edx,0xf3200610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmin.u8: + mov edx,0xf3000610 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmla.f32: + mov edx,0xf2000d10 + mov ecx,0x0e000a00 + jmp SIMD_FLOAT_vd_vn_vmx_f32 +ARM_instruction_vmla.f64 = ARM_instruction_fmacd +ARM_instruction_vmla.i16: + mov edx,0xf2100900 + jmp SIMD_INT_vd_vn_vmx +ARM_instruction_vmla.i32: + mov edx,0xf2200900 + jmp SIMD_INT_vd_vn_vmx +ARM_instruction_vmla.i8: + mov edx,0xf2000900 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vmla.s16 = ARM_instruction_vmla.i16 +ARM_instruction_vmla.s32 = ARM_instruction_vmla.i32 +ARM_instruction_vmla.s8 = ARM_instruction_vmla.i8 +ARM_instruction_vmla.u16 = ARM_instruction_vmla.i16 +ARM_instruction_vmla.u32 = ARM_instruction_vmla.i32 +ARM_instruction_vmla.u8 = ARM_instruction_vmla.i8 +ARM_instruction_vmlal.s16: + mov edx,0xf2900800 + mov ecx,0xf2900240 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlal.s32: + mov edx,0xf2a00800 + mov ecx,0xf2a00240 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlal.s8: + mov edx,0xf2800800 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmlal.u16: + mov edx,0xf3900800 + mov ecx,0xf3900240 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlal.u32: + mov edx,0xf3a00800 + mov ecx,0xf3a00240 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlal.u8: + mov edx,0xf3800800 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmls.f32: + mov edx,0xf2200d10 + mov ecx,0x0e000a40 + jmp SIMD_FLOAT_vd_vn_vmx_f32 +ARM_instruction_vmls.f64 = ARM_instruction_fnmacd +ARM_instruction_vmls.i16: + mov edx,0xf3100900 + jmp SIMD_INT_vd_vn_vmx +ARM_instruction_vmls.i32: + mov edx,0xf3200900 + jmp SIMD_INT_vd_vn_vmx +ARM_instruction_vmls.i8: + mov edx,0xf3000900 + jmp SIMD_INT_vd_vn_vm +ARM_instruction_vmls.s16 = ARM_instruction_vmls.i16 +ARM_instruction_vmls.s32 = ARM_instruction_vmls.i32 +ARM_instruction_vmls.s8 = ARM_instruction_vmls.i8 +ARM_instruction_vmls.u16 = ARM_instruction_vmls.i16 +ARM_instruction_vmls.u32 = ARM_instruction_vmls.i32 +ARM_instruction_vmls.u8 = ARM_instruction_vmls.i8 +ARM_instruction_vmlsl.s16: + mov edx,0xf2900a00 + mov ecx,0xf2900640 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlsl.s32: + mov edx,0xf2a00a00 + mov ecx,0xf2a00640 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlsl.s8: + mov edx,0xf2800a00 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmlsl.u16: + mov edx,0xf3900a00 + mov ecx,0xf3900640 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlsl.u32: + mov edx,0xf3a00a00 + mov ecx,0xf3a00640 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmlsl.u8: + mov edx,0xf3800a00 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmov.16: + mov edx,0x0e000b30 + jmp SIMD_INT_ddx_rn +ARM_instruction_vmov.32: + mov edx,0x0e000b10 + jmp SIMD_INT_rdd_rdn +ARM_instruction_vmov.8: + mov edx,0x0e400b10 + jmp SIMD_INT_ddx_rn +ARM_instruction_vmov.f32: + mov edx,0x0eb00a00 ;FCONSTS + mov ecx,0xf2800f10 + jmp SIMD_FLOAT_sm_imm +ARM_instruction_vmov.f64: + mov edx,0x0eb00b00 ;FCONSTD + jmp SIMD_FLOAT_dm_imm +ARM_instruction_vmov.i16: + mov edx,0xf2800810 + jmp SIMD_INT_vd_imm_i16 +ARM_instruction_vmov.i32: + mov edx,0xf2800010 + jmp SIMD_INT_vd_imm_i32 +ARM_instruction_vmov.i64: + mov edx,0xf2800e30 + jmp SIMD_INT_vd_imm_i8 +ARM_instruction_vmov.i8: + mov edx,0xf2800e10 + jmp SIMD_INT_vd_imm_i8 +ARM_instruction_vmov.s16: + mov edx,0x0e100b30 + jmp SIMD_INT_rd_dnx +ARM_instruction_vmov.s8: + mov edx,0x0e500b10 + jmp SIMD_INT_rd_dnx +ARM_instruction_vmov.u16: + mov edx,0x0e900b30 + jmp SIMD_INT_rd_dnx +ARM_instruction_vmov.u8: + mov edx,0x0ed00b10 + jmp SIMD_INT_rd_dnx +ARM_instruction_vmov: + jmp SIMD_INT_MOV +ARM_instruction_vmovl.s16: + mov edx,0xf2900a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovl.s32: + mov edx,0xf2a00a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovl.s8: + mov edx,0xf2880a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovl.u16: + mov edx,0xf3900a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovl.u32: + mov edx,0xf3a00a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovl.u8: + mov edx,0xf3880a10 + jmp SIMD_INT_qd_dm +ARM_instruction_vmovn.i16: + mov edx,0xf3b60200 + jmp SIMD_INT_dd_qm +ARM_instruction_vmovn.i32: + mov edx,0xf3ba0200 + jmp SIMD_INT_dd_qm +ARM_instruction_vmovn.i8: + mov edx,0xf3b20200 + jmp SIMD_INT_dd_qm +ARM_instruction_vmrs = ARM_instruction_fmrx +ARM_instruction_vmsr = ARM_instruction_fmxr +ARM_instruction_vmul.f32: + mov edx,0xf3000d10 + mov ecx,0x0e200a00 + jmp SIMD_FLOAT_vd_vn_vmx_alt_f32 +ARM_instruction_vmul.f64 = ARM_instruction_fmuld +ARM_instruction_vmul.i16: + mov edx,0xf2100910 + mov ecx,0xf2900840 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vmul.i32: + mov edx,0xf2200910 + mov ecx,0xf2a00840 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vmul.i8: + mov edx,0xf2000910 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmul.p8: + mov edx,0xf3000910 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmul.s16: + mov edx,0xf2100910 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmul.s32: + mov edx,0xf2200910 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vmul.s8 = ARM_instruction_vmul.i8 +ARM_instruction_vmul.u16 = ARM_instruction_vmul.s16 +ARM_instruction_vmul.u32 = ARM_instruction_vmul.s32 +ARM_instruction_vmul.u8 = ARM_instruction_vmul.i8 +ARM_instruction_vmull.p8: + mov edx,0xf2800e00 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmull.s16: + mov edx,0xf2900c00 + mov ecx,0xf2900a40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmull.s32: + mov edx,0xf2a00c00 + mov ecx,0xf2a00a40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmull.s8: + mov edx,0xf2800c00 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmull.u16: + mov edx,0xf3900c00 + mov ecx,0xf3900a40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmull.u32: + mov edx,0xf3a00c00 + mov ecx,0xf3a00a40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vmull.u8: + mov edx,0xf3800c00 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vmvn.i16: + mov edx,0xf2800830 + jmp SIMD_INT_vd_imm_i16 +ARM_instruction_vmvn.i32: + mov edx,0xf2800030 + jmp SIMD_INT_vd_imm_i32 +ARM_instruction_vmvn: + mov edx,0xf3b00580 + jmp SIMD_INT_vd_vm +ARM_instruction_vneg.f32: + mov edx,0xf3b90780 + mov ecx,0x0eb10a40 + jmp SIMD_FLOAT_vd_vm_f32 +ARM_instruction_vneg.f64 = ARM_instruction_fnegd +ARM_instruction_vneg.s16: + mov edx,0xf3b50380 + jmp SIMD_INT_vd_vm +ARM_instruction_vneg.s32: + mov edx,0xf3b90380 + jmp SIMD_INT_vd_vm +ARM_instruction_vneg.s8: + mov edx,0xf3b10380 + jmp SIMD_INT_vd_vm +ARM_instruction_vnmla.f32 = ARM_instruction_fnmscs +ARM_instruction_vnmla.f64 = ARM_instruction_fnmscd +ARM_instruction_vnmls.f32 = ARM_instruction_fmscs +ARM_instruction_vnmls.f64 = ARM_instruction_fmscd +ARM_instruction_vnmul.f32 = ARM_instruction_fnmuls +ARM_instruction_vnmul.f64 = ARM_instruction_fnmuld +ARM_instruction_vorn.i16: + mov edx,0xf2800911 + jmp SIMD_INT_vd_imm +ARM_instruction_vorn.i32: + mov edx,0xf2800111 + jmp SIMD_INT_vd_imm +ARM_instruction_vorn: + mov edx,0xf2300110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vorr.i16: + mov edx,0xf2800910 + jmp SIMD_INT_vd_imm +ARM_instruction_vorr.i32: + mov edx,0xf2800110 + jmp SIMD_INT_vd_imm +ARM_instruction_vorr: + mov edx,0xf2200110 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vpadal.s16: + mov edx,0xf3b40600 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadal.s32: + mov edx,0xf3b80600 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadal.s8: + mov edx,0xf3b00600 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadal.u16: + mov edx,0xf3b40680 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadal.u32: + mov edx,0xf3b80680 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadal.u8: + mov edx,0xf3b00680 + jmp SIMD_INT_vd_vm +ARM_instruction_vpadd.f32: + mov edx,0xf3000d00 + jmp SIMD_FLOAT_dd_dn_dm_alt +ARM_instruction_vpadd.i16: + mov edx,0xf2100b10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpadd.i32: + mov edx,0xf2200b10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpadd.i8: + mov edx,0xf2000b10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpaddl.s16: + mov edx,0xf3b40200 + jmp SIMD_INT_vd_vm +ARM_instruction_vpaddl.s32: + mov edx,0xf3b80200 + jmp SIMD_INT_vd_vm +ARM_instruction_vpaddl.s8: + mov edx,0xf3b00200 + jmp SIMD_INT_vd_vm +ARM_instruction_vpaddl.u16: + mov edx,0xf3b40280 + jmp SIMD_INT_vd_vm +ARM_instruction_vpaddl.u32: + mov edx,0xf3b80280 + jmp SIMD_INT_vd_vm +ARM_instruction_vpaddl.u8: + mov edx,0xf3b00280 + jmp SIMD_INT_vd_vm +ARM_instruction_vpmax.f32: + mov edx,0xf3000f00 + jmp SIMD_FLOAT_dd_dn_dm_alt +ARM_instruction_vpmax.s16: + mov edx,0xf2100a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmax.s32: + mov edx,0xf2200a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmax.s8: + mov edx,0xf2000a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmax.u16: + mov edx,0xf3100a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmax.u32: + mov edx,0xf3200a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmax.u8: + mov edx,0xf3000a00 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.f32: + mov edx,0xf3200f00 + jmp SIMD_FLOAT_dd_dn_dm_alt +ARM_instruction_vpmin.s16: + mov edx,0xf2100a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.s32: + mov edx,0xf2200a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.s8: + mov edx,0xf2000a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.u16: + mov edx,0xf3100a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.u32: + mov edx,0xf3200a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpmin.u8: + mov edx,0xf3000a10 + jmp SIMD_INT_dd_dn_dm_alt +ARM_instruction_vpop: + mov edx,0x0c900a00 + jmp SIMD_INT_list +ARM_instruction_vpush: + mov edx,0x0d000a00 + jmp SIMD_INT_list +ARM_instruction_vpop.32: + mov edx,0x0c900a00 + jmp SIMD_INT_list.32 +ARM_instruction_vpush.32: + mov edx,0x0d000a00 + jmp SIMD_INT_list.32 +ARM_instruction_vpop.64: + mov edx,0x0c900b00 + jmp SIMD_INT_list.64 +ARM_instruction_vpush.64: + mov edx,0x0d000b00 + jmp SIMD_INT_list.64 +ARM_instruction_vqabs.s16: + mov edx,0xf3b40700 + jmp SIMD_INT_vd_vm +ARM_instruction_vqabs.s32: + mov edx,0xf3b80700 + jmp SIMD_INT_vd_vm +ARM_instruction_vqabs.s8: + mov edx,0xf3b00700 + jmp SIMD_INT_vd_vm +ARM_instruction_vqadd.s16: + mov edx,0xf2100010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.s32: + mov edx,0xf2200010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.s64: + mov edx,0xf2300010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.s8: + mov edx,0xf2000010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.u16: + mov edx,0xf3100010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.u32: + mov edx,0xf3200010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.u64: + mov edx,0xf3300010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqadd.u8: + mov edx,0xf3000010 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqdmlal.s16: + mov edx,0xf2900900 + mov ecx,0xf2900340 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqdmlal.s32: + mov edx,0xf2a00900 + mov ecx,0xf2a00340 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqdmlsl.s16: + mov edx,0xf2900b00 + mov ecx,0xf2900740 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqdmlsl.s32: + mov edx,0xf2a00b00 + mov ecx,0xf2a00740 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqdmulh.s16: + mov edx,0xf2100b00 + mov ecx,0xf2900c40 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vqdmulh.s32: + mov edx,0xf2200b00 + mov ecx,0xf2a00c40 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vqdmull.s16: + mov edx,0xf2900d00 + mov ecx,0xf2900b40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqdmull.s32: + mov edx,0xf2a00d00 + mov ecx,0xf2a00b40 + jmp SIMD_INT_vd_vn_vmx_long +ARM_instruction_vqmovn.s16: + mov edx,0xf3b20280 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovn.s32: + mov edx,0xf3b60280 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovn.s64: + mov edx,0xf3ba0280 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovn.u16: + mov edx,0xf3b202c0 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovn.u32: + mov edx,0xf3b602c0 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovn.u64: + mov edx,0xf3ba02c0 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovun.s16: + mov edx,0xf3b20240 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovun.s32: + mov edx,0xf3b60240 + jmp SIMD_INT_dd_qm +ARM_instruction_vqmovun.s64: + mov edx,0xf3ba0240 + jmp SIMD_INT_dd_qm +ARM_instruction_vqneg.s16: + mov edx,0xf3b40780 + jmp SIMD_INT_vd_vm +ARM_instruction_vqneg.s32: + mov edx,0xf3b80780 + jmp SIMD_INT_vd_vm +ARM_instruction_vqneg.s8: + mov edx,0xf3b00780 + jmp SIMD_INT_vd_vm +ARM_instruction_vqrdmulh.s16: + mov edx,0xf3100b00 + mov ecx,0xf2900d40 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vqrdmulh.s32: + mov edx,0xf3200b00 + mov ecx,0xf2a00d40 + jmp SIMD_INT_vd_vn_vmx_alt +ARM_instruction_vqrshl.s16: + mov edx,0xf2100510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.s32: + mov edx,0xf2200510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.s64: + mov edx,0xf2300510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.s8: + mov edx,0xf2000510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.u16: + mov edx,0xf3100510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.u32: + mov edx,0xf3200510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.u64: + mov edx,0xf3300510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshl.u8: + mov edx,0xf3000510 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqrshrn.s16: + mov edx,0xf2880950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrn.s32: + mov edx,0xf2900950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrn.s64: + mov edx,0xf2a00950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrn.u16: + mov edx,0xf3880950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrn.u32: + mov edx,0xf3900950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrn.u64: + mov edx,0xf3a00950 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrun.s16: + mov edx,0xf3880850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrun.s32: + mov edx,0xf3900850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqrshrun.s64: + mov edx,0xf3a00850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshl.s16: + mov edx,0xf2100410 + mov ecx,0xf2900710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.s32: + mov edx,0xf2200410 + mov ecx,0xf2a00710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.s64: + mov edx,0xf2300410 + mov ecx,0xf2800790 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.s8: + mov edx,0xf2000410 + mov ecx,0xf2880710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.u16: + mov edx,0xf3100410 + mov ecx,0xf3900710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.u32: + mov edx,0xf3200410 + mov ecx,0xf3a00710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.u64: + mov edx,0xf3300410 + mov ecx,0xf3800790 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshl.u8: + mov edx,0xf3000410 + mov ecx,0xf3880710 + jmp SIMD_INT_vd_vn_vm_imm_alt +ARM_instruction_vqshlu.s16: + mov edx,0xf3900610 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vqshlu.s32: + mov edx,0xf3a00610 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vqshlu.s64: + mov edx,0xf3800690 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vqshlu.s8: + mov edx,0xf3880610 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vqshrn.s16: + mov edx,0xf2880910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrn.s32: + mov edx,0xf2900910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrn.s64: + mov edx,0xf2a00910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrn.u16: + mov edx,0xf3880910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrn.u32: + mov edx,0xf3900910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrn.u64: + mov edx,0xf3a00910 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrun.s16: + mov edx,0xf3880810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrun.s32: + mov edx,0xf3900810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqshrun.s64: + mov edx,0xf3a00810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vqsub.s16: + mov edx,0xf2100210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.s32: + mov edx,0xf2200210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.s64: + mov edx,0xf2300210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.s8: + mov edx,0xf2000210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.u16: + mov edx,0xf3100210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.u32: + mov edx,0xf3200210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.u64: + mov edx,0xf3300210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vqsub.u8: + mov edx,0xf3000210 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vraddhn.i16: + mov edx,0xf3800400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vraddhn.i32: + mov edx,0xf3900400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vraddhn.i64: + mov edx,0xf3a00400 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vrecpe.f32: + mov edx,0xf3bb0500 + jmp SIMD_FLOAT_vd_vm +ARM_instruction_vrecpe.u32: + mov edx,0xf3bb0400 + jmp SIMD_INT_vd_vm +ARM_instruction_vrecps.f32: + mov edx,0xf2000f10 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vrev16.8: + mov edx,0xf3b00100 + jmp SIMD_INT_vd_vm +ARM_instruction_vrev32.16: + mov edx,0xf3b40080 + jmp SIMD_INT_vd_vm +ARM_instruction_vrev32.8: + mov edx,0xf3b00080 + jmp SIMD_INT_vd_vm +ARM_instruction_vrev64.16: + mov edx,0xf3b40000 + jmp SIMD_INT_vd_vm +ARM_instruction_vrev64.32: + mov edx,0xf3b80000 + jmp SIMD_INT_vd_vm +ARM_instruction_vrev64.8: + mov edx,0xf3b00000 + jmp SIMD_INT_vd_vm +ARM_instruction_vrhadd.s16: + mov edx,0xf2100100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrhadd.s32: + mov edx,0xf2200100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrhadd.s8: + mov edx,0xf2000100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrhadd.u16: + mov edx,0xf3100100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrhadd.u32: + mov edx,0xf3200100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrhadd.u8: + mov edx,0xf3000100 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.s16: + mov edx,0xf2100500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.s32: + mov edx,0xf2200500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.s64: + mov edx,0xf2300500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.s8: + mov edx,0xf2000500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.u16: + mov edx,0xf3100500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.u32: + mov edx,0xf3200500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.u64: + mov edx,0xf3300500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshl.u8: + mov edx,0xf3000500 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vrshr.s16: + mov edx,0xf2900210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.s32: + mov edx,0xf2a00210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.s64: + mov edx,0xf2800290 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.s8: + mov edx,0xf2880210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.u16: + mov edx,0xf3900210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.u32: + mov edx,0xf3a00210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.u64: + mov edx,0xf3800290 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshr.u8: + mov edx,0xf3880210 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrshrn.i16: + mov edx,0xf2880850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vrshrn.i32: + mov edx,0xf2900850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vrshrn.i64: + mov edx,0xf2a00850 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vrsqrte.f32: + mov edx,0xf3bb0580 + jmp SIMD_FLOAT_vd_vm +ARM_instruction_vrsqrte.u32: + mov edx,0xf3bb0480 + jmp SIMD_INT_vd_vm +ARM_instruction_vrsqrts.f32: + mov edx,0xf2200f10 + jmp SIMD_FLOAT_vd_vn_vm_alt +ARM_instruction_vrsra.s16: + mov edx,0xf2900310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.s32: + mov edx,0xf2a00310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.s64: + mov edx,0xf2800390 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.s8: + mov edx,0xf2880310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.u16: + mov edx,0xf3900310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.u32: + mov edx,0xf3a00310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.u64: + mov edx,0xf3800390 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsra.u8: + mov edx,0xf3880310 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vrsubhn.i16: + mov edx,0xf3800600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vrsubhn.i32: + mov edx,0xf3900600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vrsubhn.i64: + mov edx,0xf3a00600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vshl.i16: + mov edx,0xf2900510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vshl.i32: + mov edx,0xf2a00510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vshl.i64: + mov edx,0xf2800590 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vshl.i8: + mov edx,0xf2880510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vshl.s16: + mov edx,0xf2100400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.s32: + mov edx,0xf2200400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.s64: + mov edx,0xf2300400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.s8: + mov edx,0xf2000400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.u16: + mov edx,0xf3100400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.u32: + mov edx,0xf3200400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.u64: + mov edx,0xf3300400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshl.u8: + mov edx,0xf3000400 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vshll.i16: + mov edx,0xf3b60300 + jmp SIMD_INT_qd_dm_imm_I +ARM_instruction_vshll.i32: + mov edx,0xf3ba0300 + jmp SIMD_INT_qd_dm_imm_I +ARM_instruction_vshll.i8: + mov edx,0xf3b20300 + jmp SIMD_INT_qd_dm_imm_I +ARM_instruction_vshll.s16: + mov edx,0xf2900a10 + mov ecx,0xf3b60300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshll.s32: + mov edx,0xf2a00a10 + mov ecx,0xf3ba0300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshll.s8: + mov edx,0xf2880a10 + mov ecx,0xf3b20300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshll.u16: + mov edx,0xf3900a10 + mov ecx,0xf3b60300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshll.u32: + mov edx,0xf3a00a10 + mov ecx,0xf3ba0300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshll.u8: + mov edx,0xf3880a10 + mov ecx,0xf3b20300 + jmp SIMD_INT_qd_dm_imm +ARM_instruction_vshr.s16: + mov edx,0xf2900010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.s32: + mov edx,0xf2a00010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.s64: + mov edx,0xf2800090 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.s8: + mov edx,0xf2880010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.u16: + mov edx,0xf3900010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.u32: + mov edx,0xf3a00010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.u64: + mov edx,0xf3800090 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshr.u8: + mov edx,0xf3880010 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vshrn.i16: + mov edx,0xf2880810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vshrn.i32: + mov edx,0xf2900810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vshrn.i64: + mov edx,0xf2a00810 + jmp SIMD_INT_dd_qm_imm +ARM_instruction_vsli.16: + mov edx,0xf3900510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vsli.32: + mov edx,0xf3a00510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vsli.64: + mov edx,0xf3800590 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vsli.8: + mov edx,0xf3880510 + jmp SIMD_INT_vd_vm_imm_alt +ARM_instruction_vsqrt.f32 = ARM_instruction_fsqrts +ARM_instruction_vsqrt.f64 = ARM_instruction_fsqrtd +ARM_instruction_vsra.s16: + mov edx,0xf2900110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.s32: + mov edx,0xf2a00110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.s64: + mov edx,0xf2800190 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.s8: + mov edx,0xf2880110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.u16: + mov edx,0xf3900110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.u32: + mov edx,0xf3a00110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.u64: + mov edx,0xf3800190 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsra.u8: + mov edx,0xf3880110 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsri.16: + mov edx,0xf3900410 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsri.32: + mov edx,0xf3a00410 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsri.64: + mov edx,0xf3800490 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vsri.8: + mov edx,0xf3880410 + jmp SIMD_INT_vd_vm_imm_alt_neg +ARM_instruction_vst1.16: + mov edx,0xf4000040 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vst1.32: + mov edx,0xf4000080 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vst1.64: + mov edx,0xf40000c0 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vst1.8: + mov edx,0xf4000000 + jmp SIMD_INT_list_rn_rm_1 +ARM_instruction_vst2.16: + mov edx,0xf4000040 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vst2.32: + mov edx,0xf4000080 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vst2.8: + mov edx,0xf4000000 + jmp SIMD_INT_list_rn_rm_2 +ARM_instruction_vst3.16: + mov edx,0xf4000040 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vst3.32: + mov edx,0xf4000080 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vst3.8: + mov edx,0xf4000000 + jmp SIMD_INT_list_rn_rm_3 +ARM_instruction_vst4.16: + mov edx,0xf4000040 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vst4.32: + mov edx,0xf4000080 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vst4.8: + mov edx,0xf4000000 + jmp SIMD_INT_list_rn_rm_4 +ARM_instruction_vstm.32 = ARM_instruction_fstmias +ARM_instruction_vstm.64 = ARM_instruction_fstmiad +ARM_instruction_vstmdb.32 = ARM_instruction_fstmdbs +ARM_instruction_vstmdb.64 = ARM_instruction_fstmdbd +ARM_instruction_vstmfd.32 = ARM_instruction_fstmfds +ARM_instruction_vstmfd.64 = ARM_instruction_fstmfdd +ARM_instruction_vstmea.32 = ARM_instruction_fstmeas +ARM_instruction_vstmea.64 = ARM_instruction_fstmead +ARM_instruction_vstmia.32 = ARM_instruction_fstmias +ARM_instruction_vstmia.64 = ARM_instruction_fstmiad +ARM_instruction_vstmfd: +ARM_instruction_vstmdb: + mov edx,0xd000a00 + jmp SIMD_INT_rn_list +ARM_instruction_vstm: +ARM_instruction_vstmea: +ARM_instruction_vstmia: + mov edx,0xc800a00 + jmp SIMD_INT_rn_list +ARM_instruction_vstr.32 = ARM_instruction_fsts +ARM_instruction_vstr.64 = ARM_instruction_fstd +ARM_instruction_vstr: + mov edx,0x0d000a00 + jmp SIMD_INT_vd_rn_offset +ARM_instruction_vsub.f32: + mov edx,0xf2200d00 + mov ecx,0x0e300a40 + jmp SIMD_FLOAT_vd_vn_vm_f32 +ARM_instruction_vsub.f64 = ARM_instruction_fsubd +ARM_instruction_vsub.i16: + mov edx,0xf3100800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vsub.i32: + mov edx,0xf3200800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vsub.i64: + mov edx,0xf3300800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vsub.i8: + mov edx,0xf3000800 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vsubhn.i16: + mov edx,0xf2800600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vsubhn.i32: + mov edx,0xf2900600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vsubhn.i64: + mov edx,0xf2a00600 + jmp SIMD_INT_vd_vn_vm_narrow +ARM_instruction_vsubl.s16: + mov edx,0xf2900200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubl.s32: + mov edx,0xf2a00200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubl.s8: + mov edx,0xf2800200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubl.u16: + mov edx,0xf3900200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubl.u32: + mov edx,0xf3a00200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubl.u8: + mov edx,0xf3800200 + jmp SIMD_INT_vd_vn_vm_long +ARM_instruction_vsubw.s16: + mov edx,0xf2900300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vsubw.s32: + mov edx,0xf2a00300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vsubw.s8: + mov edx,0xf2800300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vsubw.u16: + mov edx,0xf3900300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vsubw.u32: + mov edx,0xf3a00300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vsubw.u8: + mov edx,0xf3800300 + jmp SIMD_INT_vd_vn_vm_wide +ARM_instruction_vswp: + mov edx,0xf3b20000 + jmp SIMD_INT_vd_vm +ARM_instruction_vtbl.8: + mov edx,0xf3b00800 + jmp SIMD_dn_list_dm +ARM_instruction_vtbx.8: + mov edx,0xf3b00840 + jmp SIMD_dn_list_dm +ARM_instruction_vtrn.16: + mov edx,0xf3b60080 + jmp SIMD_INT_vd_vm +ARM_instruction_vtrn.32: + mov edx,0xf3ba0080 + jmp SIMD_INT_vd_vm +ARM_instruction_vtrn.8: + mov edx,0xf3b20080 + jmp SIMD_INT_vd_vm +ARM_instruction_vtst.16: + mov edx,0xf2100810 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vtst.32: + mov edx,0xf2200810 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vtst.8: + mov edx,0xf2000810 + jmp SIMD_INT_vd_vn_vm_alt +ARM_instruction_vuzp.16: + mov edx,0xf3b60100 + jmp SIMD_INT_vd_vm +ARM_instruction_vuzp.32: + mov edx,0xf3ba0100 + jmp SIMD_INT_vd_vm +ARM_instruction_vuzp.8: + mov edx,0xf3b20100 + jmp SIMD_INT_vd_vm +ARM_instruction_vzip.16: + mov edx,0xf3b60180 + jmp SIMD_INT_vd_vm +ARM_instruction_vzip.32: + mov edx,0xf3ba0180 + jmp SIMD_INT_vd_vm +ARM_instruction_vzip.8: + mov edx,0xf3b20180 + jmp SIMD_INT_vd_vm + +;VFPv4 and SIMDv2 + +ARM_instruction_vfma.f32: + mov edx,0xf2000c10 + mov ecx,0x0ea00a00 + jmp SIMD_FLOAT_vd_vn_vm +ARM_instruction_vfms.f32: + mov edx,0xf2200c10 + mov ecx,0x0ea00a40 + jmp SIMD_FLOAT_vd_vn_vm +ARM_instruction_vfma.f64: + mov ecx,0x0ea00b00 + jmp SIMD_FLOAT_dd_dn_dm +ARM_instruction_vfms.f64: + mov ecx,0x0ea00b40 + jmp SIMD_FLOAT_dd_dn_dm +ARM_instruction_vfnma.f32: + mov ecx,0x0e900a40 + jmp SIMD_FLOAT_sd_sn_sm +ARM_instruction_vfnms.f32: + mov ecx,0x0e900a00 + jmp SIMD_FLOAT_sd_sn_sm +ARM_instruction_vfnma.f64: + mov ecx,0x0e900b40 + jmp SIMD_FLOAT_dd_dn_dm +ARM_instruction_vfnms.f64: + mov ecx,0x0e900b00 + jmp SIMD_FLOAT_dd_dn_dm + +;v7VE + +ARM_instruction_eret: + INST_ARM64 + dd 0xd69f03e0 + dd ARM64_debug3 + mov edx,0x0160006e + mov ecx,0xf3de8f00 + jmp ARM_eret +ARM_instruction_hvc: + INST_ARM64 + dd 0xd4000002 + dd ARM64_debug + mov edx,0x01400070 + mov ecx,0xf7e08000 + jmp ARM_immediate16_ve + +;v8 + +ARM_instruction_hlt: + INST_ARM64 + dd 0xd4400000 + dd ARM64_debug + mov edx,0x01000070 + jmp ARM_immediate16_v8 +ARM_instruction_lda: + mov [operand_size],4 + mov edx,0x01900c9f + mov ecx,0xe8d00faf + jmp ARM_rd_q_rn_p +ARM_instruction_ldab: + mov [operand_size],1 + mov edx,0x01d00c9f + mov ecx,0xe8d00f8f + jmp ARM_rd_q_rn_p +ARM_instruction_ldah: + mov [operand_size],2 + mov edx,0x01f00c9f + mov ecx,0xe8d00f9f + jmp ARM_rd_q_rn_p +ARM_instruction_ldaex: + mov [operand_size],4 + mov edx,0x01900e9f + mov ecx,0xe8d00fef + jmp ARM_rd_q_rn_p +ARM_instruction_ldaexb: + mov [operand_size],1 + mov edx,0x01d00e9f + mov ecx,0xe8d00fcf + jmp ARM_rd_q_rn_p +ARM_instruction_ldaexh: + mov [operand_size],2 + mov edx,0x01f00e9f + mov ecx,0xe8d00fdf + jmp ARM_rd_q_rn_p +ARM_instruction_ldaexd: + mov [operand_size],8 + mov edx,0x01b00e9f + mov ecx,0xe8d000ff + jmp ARM_rt_rt2_q_rn_p +ARM_instruction_sevl: + INST_ARM64 + dd 0xd50320bf + dd ARM64_debug3 + mov edx,0x0320f005 + mov ecx,0xf3af8005 + jmp ARM_nops +ARM_instruction_stl: + mov [operand_size],4 + mov edx,0x0180fc90 + mov ecx,0xe8c00faf + jmp ARM_rt_q_rn_p +ARM_instruction_stlb: + mov [operand_size],1 + mov edx,0x01c0fc90 + mov ecx,0xe8c00f8f + jmp ARM_rt_q_rn_p +ARM_instruction_stlh: + mov [operand_size],1 + mov edx,0x01e0fc90 + mov ecx,0xe8c00f9f + jmp ARM_rt_q_rn_p +ARM_instruction_stlex: + mov [operand_size],4 + mov edx,0x01800e90 + mov ecx,0xe8c00fe0 + jmp ARM_rd_rt_q_rn_p_STLEX +ARM_instruction_stlexb: + mov [operand_size],1 + mov edx,0x01c00e90 + mov ecx,0xe8c00fc0 + jmp ARM_rd_rt_q_rn_p_STLEX +ARM_instruction_stlexh: + mov [operand_size],2 + mov edx,0x01e00e90 + mov ecx,0xe8c00fd0 + jmp ARM_rd_rt_q_rn_p_STLEX +ARM_instruction_stlexd: + mov [operand_size],8 + mov edx,0x01a00e90 + mov ecx,0xe8c000f0 + jmp ARM_rd_rt_rt2_q_rn_p_STLEXD +ARM_instruction_dcps1: + INST_ARM64 + dd 0xd4a00001 + dd ARM64_debug2 + mov ecx,0xf78f8001 + jmp THUMB_v8 +ARM_instruction_dcps2: + INST_ARM64 + dd 0xd4a00002 + dd ARM64_debug2 + mov ecx,0xf78f8002 + jmp THUMB_v8 +ARM_instruction_dcps3: + INST_ARM64 + dd 0xd4a00003 + dd ARM64_debug2 + mov ecx,0xf78f8003 + jmp THUMB_v8 + +;v8 VFP/SIMD +ARM_instruction_vcvtm.s32.f32: + mov edx,0xfebf0ac0 + mov ecx,0xf3bb0300 + jmp SIMD_sd_sm +ARM_instruction_vcvtm.u32.f32: + mov edx,0xfebf0a40 + mov ecx,0xf3bb0380 + jmp SIMD_sd_sm +ARM_instruction_vcvtm.s32.f64: + mov edx,0xfebf0bc0 + jmp SIMD_sd_dm +ARM_instruction_vcvtm.u32.f64: + mov edx,0xfebf0b40 + jmp SIMD_sd_dm +ARM_instruction_vcvtp.s32.f32: + mov edx,0xfebe0ac0 + mov ecx,0xf3bb0200 + jmp SIMD_sd_sm +ARM_instruction_vcvtp.u32.f32: + mov edx,0xfebe0a40 + mov ecx,0xf3bb0280 + jmp SIMD_sd_sm +ARM_instruction_vcvtp.s32.f64: + mov edx,0xfebe0bc0 + jmp SIMD_sd_dm +ARM_instruction_vcvtp.u32.f64: + mov edx,0xfebe0b40 + jmp SIMD_sd_dm +ARM_instruction_vcvtn.s32.f32: + mov edx,0xfebd0ac0 + mov ecx,0xf3bb0100 + jmp SIMD_sd_sm +ARM_instruction_vcvtn.u32.f32: + mov edx,0xfebd0a40 + mov ecx,0xf3bb0180 + jmp SIMD_sd_sm +ARM_instruction_vcvtn.s32.f64: + mov edx,0xfebd0bc0 + jmp SIMD_sd_dm +ARM_instruction_vcvtn.u32.f64: + mov edx,0xfebd0b40 + jmp SIMD_sd_dm +ARM_instruction_vcvta.s32.f32: + mov edx,0xfebc0ac0 + mov ecx,0xf3bb0000 + jmp SIMD_sd_sm +ARM_instruction_vcvta.u32.f32: + mov edx,0xfebc0a40 + mov ecx,0xf3bb0080 + jmp SIMD_sd_sm +ARM_instruction_vcvta.s32.f64: + mov edx,0xfebc0bc0 + jmp SIMD_sd_dm +ARM_instruction_vcvta.u32.f64: + mov edx,0xfebc0b40 + jmp SIMD_sd_dm +ARM_instruction_vcvtb.f16.f64: + mov edx,0x0eb30b40 + jmp VFP_sd_dm_HP +ARM_instruction_vcvtb.f64.f16: + mov edx,0x0eb20b40 + jmp VFP_dd_sm_HP +ARM_instruction_vcvtt.f16.f64: + mov edx,0x0eb30bc0 + jmp VFP_sd_dm_HP +ARM_instruction_vcvtt.f64.f16: + mov edx,0x0eb20bc0 + jmp VFP_dd_sm_HP +ARM_instruction_vmaxnm.f32: + mov edx,0xfe800a00 + mov ecx,0xf3000f10 + jmp SIMD_FLOAT_vd_vn_vm_v8 +ARM_instruction_vmaxnm.f64: + mov ecx,0xfe800b00 + jmp SIMD_FLOAT_dd_dn_dm_v8 +ARM_instruction_vminnm.f32: + mov edx,0xfe800a40 + mov ecx,0xf3200f10 + jmp SIMD_FLOAT_vd_vn_vm_v8 +ARM_instruction_vminnm.f64: + mov ecx,0xfe800b40 + jmp SIMD_FLOAT_dd_dn_dm_v8 +ARM_instruction_vrintm.f32.f32: + mov edx,0xfebb0a40 + mov ecx,0xf3ba0680 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrintm.f64.f64: + mov edx,0xfebb0b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrintp.f32.f32: + mov edx,0xfeba0a40 + mov ecx,0xf3ba0780 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrintp.f64.f64: + mov edx,0xfeba0b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrintn.f32.f32: + mov edx,0xfeb90a40 + mov ecx,0xf3ba0400 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrintn.f64.f64: + mov edx,0xfeb90b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrinta.f32.f32: + mov edx,0xfeb80a40 + mov ecx,0xf3ba0500 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrinta.f64.f64: + mov edx,0xfeb80b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrintx.f32.f32: + mov edx,0x0eb70a40 + mov ecx,0xf3ba0480 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrintx.f64.f64: + mov edx,0x0eb70b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrintr.f32.f32: + mov edx,0x0eb60a40 + jmp SIMD_FLOAT_sd_sn_v8 +ARM_instruction_vrintr.f64.f64: + mov edx,0x0eb60b40 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vrintz.f32.f32: + mov edx,0x0eb60ac0 + mov ecx,0xf3ba0580 + jmp SIMD_FLOAT_vd_vn_v8 +ARM_instruction_vrintz.f64.f64: + mov edx,0x0eb60bc0 + jmp SIMD_FLOAT_dd_dn_v8 +ARM_instruction_vseleq.f32: + mov ecx,0xfe000a00 + jmp SIMD_FLOAT_sd_sn_sm_v8 +ARM_instruction_vseleq.f64: + mov ecx,0xfe000b00 + jmp SIMD_FLOAT_dd_dn_dm_v8 +ARM_instruction_vselvs.f32: + mov ecx,0xfe100a00 + jmp SIMD_FLOAT_sd_sn_sm_v8 +ARM_instruction_vselvs.f64: + mov ecx,0xfe100b00 + jmp SIMD_FLOAT_dd_dn_dm_v8 +ARM_instruction_vselge.f32: + mov ecx,0xfe200a00 + jmp SIMD_FLOAT_sd_sn_sm_v8 +ARM_instruction_vselge.f64: + mov ecx,0xfe200b00 + jmp SIMD_FLOAT_dd_dn_dm_v8 +ARM_instruction_vselgt.f32: + mov ecx,0xfe300a00 + jmp SIMD_FLOAT_sd_sn_sm_v8 +ARM_instruction_vselgt.f64: + mov ecx,0xfe300b00 + jmp SIMD_FLOAT_dd_dn_dm_v8 + +;v8 CRC +ARM_instruction_crc32b: + INST_ARM64 + dd 0x1ac04000 + dd ARM64_wz_wz_wz + mov edx,0xe1000040 + mov ecx,0xfac0f080 + jmp ARM_rd_rn_rm_crc +ARM_instruction_crc32h: + INST_ARM64 + dd 0x1ac04400 + dd ARM64_wz_wz_wz + mov edx,0xe1200040 + mov ecx,0xfac0f090 + jmp ARM_rd_rn_rm_crc +ARM_instruction_crc32w: + INST_ARM64 + dd 0x1ac04800 + dd ARM64_wz_wz_wz + mov edx,0xe1400040 + mov ecx,0xfac0f0a0 + jmp ARM_rd_rn_rm_crc +ARM_instruction_crc32cb: + INST_ARM64 + dd 0x1ac05000 + dd ARM64_wz_wz_wz + mov edx,0xe1000240 + mov ecx,0xfad0f080 + jmp ARM_rd_rn_rm_crc +ARM_instruction_crc32ch: + INST_ARM64 + dd 0x1ac05400 + dd ARM64_wz_wz_wz + mov edx,0xe1200240 + mov ecx,0xfad0f090 + jmp ARM_rd_rn_rm_crc +ARM_instruction_crc32cw: + INST_ARM64 + dd 0x1ac05800 + dd ARM64_wz_wz_wz + mov edx,0xe1400240 + mov ecx,0xfad0f0a0 + jmp ARM_rd_rn_rm_crc + +;v8 crypto +ARM_instruction_aesd.8: + mov edx,0xf3b00340 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_aese.8: + mov edx,0xf3b00300 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_aesimc.8: + mov edx,0xf3b003c0 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_aesmc.8: + mov edx,0xf3b00380 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_sha1h.32: + mov edx,0xf3b902c0 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_sha1su1.32: + mov edx,0xf3ba0380 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_sha256su0.32: + mov edx,0xf3ba03c0 + jmp SIMD_CRYPTO_qd_qm +ARM_instruction_sha1c.32: + mov edx,0xf2000c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha1p.32: + mov edx,0xf2100c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha1m.32: + mov edx,0xf2200c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha1su0.32: + mov edx,0xf2300c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha256h.32: + mov edx,0xf3000c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha256h2.32: + mov edx,0xf3100c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_sha256su1.32: + mov edx,0xf3200c40 + jmp SIMD_CRYPTO_qd_qn_qm +ARM_instruction_vmull.p64: + mov edx,0xf2a00e00 + jmp SIMD_INT_qd_dn_dm + +;v8 64-bit + +ARM_instruction_adrp: + INST_ARM64 + dd 0x90000000 + dd ARM64_adr + jmp ERROR_instruction_not_32bit +ARM_instruction_asrv: + INST_ARM64 + dd 0x1ac02800 + dd ARM64_register_rotate + jmp ERROR_instruction_not_32bit +ARM_instruction_at: + INST_ARM64 + dd 0xd5000000 + dd ARM64_sys_predefined_at + jmp ERROR_instruction_not_32bit +ARM_instruction_b.eq: + INST_ARM64 + dd 0x54000000 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.ne: + INST_ARM64 + dd 0x54000001 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.cs: + INST_ARM64 + dd 0x54000002 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.cc: + INST_ARM64 + dd 0x54000003 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.mi: + INST_ARM64 + dd 0x54000004 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.pl: + INST_ARM64 + dd 0x54000005 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.vs: + INST_ARM64 + dd 0x54000006 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.vc: + INST_ARM64 + dd 0x54000007 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.hi: + INST_ARM64 + dd 0x54000008 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.ls: + INST_ARM64 + dd 0x54000009 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.ge: + INST_ARM64 + dd 0x5400000a + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.lt: + INST_ARM64 + dd 0x5400000b + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.gt: + INST_ARM64 + dd 0x5400000c + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.le: + INST_ARM64 + dd 0x5400000d + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.al: + INST_ARM64 + dd 0x5400000e + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.hs: + INST_ARM64 + dd 0x54000002 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.lo: + INST_ARM64 + dd 0x54000003 + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_b.nv: + INST_ARM64 + dd 0x5400000f + dd ARM64_b_cond + jmp ERROR_instruction_not_32bit +ARM_instruction_bfm: + INST_ARM64 + dd 0x33000000 + dd ARM64_bfm + jmp ERROR_instruction_not_32bit +ARM_instruction_bfxil: + INST_ARM64 + dd 0x33000000 + dd ARM64_bfxil + jmp ERROR_instruction_not_32bit +ARM_instruction_blr: + INST_ARM64 + dd 0xd63f0000 + dd ARM64_br + jmp ERROR_instruction_not_32bit +ARM_instruction_br: + INST_ARM64 + dd 0xd61f0000 + dd ARM64_br + jmp ERROR_instruction_not_32bit +ARM_instruction_brk: + INST_ARM64 + dd 0xd4200000 + dd ARM64_debug + jmp ERROR_instruction_not_32bit +ARM_instruction_ccmn: + INST_ARM64 + dd 0x3a400000 + dd ARM64_conditional_compare + jmp ERROR_instruction_not_32bit +ARM_instruction_ccmp: + INST_ARM64 + dd 0x7a400000 + dd ARM64_conditional_compare + jmp ERROR_instruction_not_32bit +ARM_instruction_cinc: + INST_ARM64 + dd 0x1a800400 + dd ARM64_conditional_modify + jmp ERROR_instruction_not_32bit +ARM_instruction_cinv: + INST_ARM64 + dd 0x5a800000 + dd ARM64_conditional_modify + jmp ERROR_instruction_not_32bit +ARM_instruction_cls: + INST_ARM64 + dd 0x5ac01400 + dd ARM64_arithmetic4 + jmp ERROR_instruction_not_32bit +ARM_instruction_cneg: + INST_ARM64 + dd 0x5a800400 + dd ARM64_conditional_modify_zr + jmp ERROR_instruction_not_32bit +ARM_instruction_crc32x: + INST_ARM64 + dd 0x9ac04c00 + dd ARM64_wz_wz_xz + jmp ERROR_instruction_not_32bit +ARM_instruction_crc32cx: + INST_ARM64 + dd 0x9ac05c00 + dd ARM64_wz_wz_xz + jmp ERROR_instruction_not_32bit +ARM_instruction_csel: + INST_ARM64 + dd 0x1a800000 + dd ARM64_conditional_select + jmp ERROR_instruction_not_32bit +ARM_instruction_cset: + INST_ARM64 + dd 0x1a9f07e0 + dd ARM64_conditional_set + jmp ERROR_instruction_not_32bit +ARM_instruction_csetm: + INST_ARM64 + dd 0x5a9f03e0 + dd ARM64_conditional_set + jmp ERROR_instruction_not_32bit +ARM_instruction_csinc: + INST_ARM64 + dd 0x1a800400 + dd ARM64_conditional_select + jmp ERROR_instruction_not_32bit +ARM_instruction_csinv: + INST_ARM64 + dd 0x5a800000 + dd ARM64_conditional_select + jmp ERROR_instruction_not_32bit +ARM_instruction_csneg: + INST_ARM64 + dd 0x5a800400 + dd ARM64_conditional_select + jmp ERROR_instruction_not_32bit +ARM_instruction_dc: + INST_ARM64 + dd 0xd5000000 + dd ARM64_sys_predefined_dc + jmp ERROR_instruction_not_32bit +ARM_instruction_drps: + INST_ARM64 + dd 0xd6bf03e0 + dd ARM64_debug3 + jmp ERROR_instruction_not_32bit +ARM_instruction_eon: + INST_ARM64 + dd 0x40200000 + dd ARM64_arithmetic2 + jmp ERROR_instruction_not_32bit +ARM_instruction_extr: + INST_ARM64 + dd 0x13800000 + dd ARM64_arithmetic5 + jmp ERROR_instruction_not_32bit +ARM_instruction_hint: + INST_ARM64 + dd 0xd503201f + dd ARM64_hint + jmp ERROR_instruction_not_32bit +ARM_instruction_ic: + INST_ARM64 + dd 0xd5000000 + dd ARM64_sys_predefined_ic + jmp ERROR_instruction_not_32bit +ARM_instruction_ldar: + INST_ARM64 + dd 0x88dffc00 + dd ARM64_memory_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldarb: + INST_ARM64 + dd 0x08dffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldarh: + INST_ARM64 + dd 0x48dffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldaxp: + INST_ARM64 + dd 0x887f8000 + dd ARM64_memory_double_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldaxr: + INST_ARM64 + dd 0x885ffc00 + dd ARM64_memory_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldaxrb: + INST_ARM64 + dd 0x085ffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldaxrh: + INST_ARM64 + dd 0x485ffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldnp: + INST_ARM64 + dd 0x28400000 + dd ARM64_memory_double_imm7 + jmp ERROR_instruction_not_32bit +ARM_instruction_ldp: + INST_ARM64 + dd 0x28400000 + dd ARM64_memory_double_imm7_post_pre_offset + jmp ERROR_instruction_not_32bit +ARM_instruction_ldpsw: + INST_ARM64 + dd 0x68400000 + dd ARM64_memory_double_imm7_signed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldrsw: + INST_ARM64 + dd 0x38800000 + dd ARM64_memory_signed_word + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtr: + INST_ARM64 + dd 0x38400c00 + dd ARM64_memory_unprivileged + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtrb: + INST_ARM64 + dd 0x38400c00 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtrh: + INST_ARM64 + dd 0x38400c01 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtrsb: + INST_ARM64 + dd 0x38c00c00 + dd ARM64_memory_unprivileged_signed_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtrsh: + INST_ARM64 + dd 0x38c00c01 + dd ARM64_memory_unprivileged_signed_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldtrsw: + INST_ARM64 + dd 0x38800c00 + dd ARM64_memory_unprivileged_signed_word + jmp ERROR_instruction_not_32bit +ARM_instruction_ldur: + INST_ARM64 + dd 0x38400400 + dd ARM64_memory_unscaled + jmp ERROR_instruction_not_32bit +ARM_instruction_ldurb: + INST_ARM64 + dd 0x38400400 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldurh: + INST_ARM64 + dd 0x38400401 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldursb: + INST_ARM64 + dd 0x38800400 + dd ARM64_memory_unprivileged_signed_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldursh: + INST_ARM64 + dd 0x38800401 + dd ARM64_memory_unprivileged_signed_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_ldursw: + INST_ARM64 + dd 0x38800400 + dd ARM64_memory_unprivileged_signed_word + jmp ERROR_instruction_not_32bit +ARM_instruction_ldxp: + INST_ARM64 + dd 0x887f0000 + dd ARM64_memory_double_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldxr: + INST_ARM64 + dd 0x885f7c00 + dd ARM64_memory_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldxrb: + INST_ARM64 + dd 0x085f7c00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_ldxrh: + INST_ARM64 + dd 0x485f7c00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_lslv: + INST_ARM64 + dd 0x1ac02000 + dd ARM64_register_rotate + jmp ERROR_instruction_not_32bit +ARM_instruction_lsrv: + INST_ARM64 + dd 0x1ac02400 + dd ARM64_register_rotate + jmp ERROR_instruction_not_32bit +ARM_instruction_madd: + INST_ARM64 + dd 0x1b000000 + dd ARM64_dz_nz_mz_az + jmp ERROR_instruction_not_32bit +ARM_instruction_mneg: + INST_ARM64 + dd 0x1b00fc00 + dd ARM64_dz_nz_mz + jmp ERROR_instruction_not_32bit +ARM_instruction_movk: + INST_ARM64 + dd 0x72800000 + dd ARM64_mov_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_movn: + INST_ARM64 + dd 0x12800000 + dd ARM64_mov_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_movz: + INST_ARM64 + dd 0x52800000 + dd ARM64_mov_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_msub: + INST_ARM64 + dd 0x1b008000 + dd ARM64_dz_nz_mz_az + jmp ERROR_instruction_not_32bit +ARM_instruction_ngc: + INST_ARM64S + dd 0x5a0003e0 + dd ARM64_arithmetic9 + jmp ERROR_instruction_not_32bit +ARM_instruction_prfm: + INST_ARM64 + dd 0xf8800000 + dd ARM64_prefetch + jmp ERROR_instruction_not_32bit +ARM_instruction_ret: + INST_ARM64 + dd 0xd65f0000 + dd ARM64_ret + jmp ERROR_instruction_not_32bit +ARM_instruction_rev32: + INST_ARM64 + dd 0xdac00800 + dd ARM64_arithmetic13 + jmp ERROR_instruction_not_32bit +ARM_instruction_rev64: + INST_ARM64 + dd 0xdac00c00 + dd ARM64_arithmetic14 + jmp ERROR_instruction_not_32bit +ARM_instruction_rorv: + INST_ARM64 + dd 0x1ac02c00 + dd ARM64_register_rotate + jmp ERROR_instruction_not_32bit +ARM_instruction_sbfiz: + INST_ARM64 + dd 0x13000000 + dd ARM64_bfi + jmp ERROR_instruction_not_32bit +ARM_instruction_sbfm: + INST_ARM64 + dd 0x13000000 + dd ARM64_bfm + jmp ERROR_instruction_not_32bit +ARM_instruction_smaddl: + INST_ARM64 + dd 0x9b200000 + dd ARM64_dx_nw_mw_ax + jmp ERROR_instruction_not_32bit +ARM_instruction_smnegl: + INST_ARM64 + dd 0x9b20fc00 + dd ARM64_dx_nw_mw + jmp ERROR_instruction_not_32bit +ARM_instruction_smsubl: + INST_ARM64 + dd 0x9b208000 + dd ARM64_dx_nw_mw_ax + jmp ERROR_instruction_not_32bit +ARM_instruction_smulh: + INST_ARM64 + dd 0x9b407c00 + dd ARM64_xz_xz_xz + jmp ERROR_instruction_not_32bit +ARM_instruction_stlr: + INST_ARM64 + dd 0x889ffc00 + dd ARM64_memory_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlrb: + INST_ARM64 + dd 0x089ffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlrh: + INST_ARM64 + dd 0x489ffc00 + dd ARM64_memory_word_single_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlxp: + INST_ARM64 + dd 0x88208000 + dd ARM64_memory_triple_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlxr: + INST_ARM64 + dd 0x8800fc00 + dd ARM64_memory_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlxrb: + INST_ARM64 + dd 0x0800fc00 + dd ARM64_memory_word_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stlxrh: + INST_ARM64 + dd 0x4800fc00 + dd ARM64_memory_word_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stnp: + INST_ARM64 + dd 0x28000000 + dd ARM64_memory_double_imm7 + jmp ERROR_instruction_not_32bit +ARM_instruction_stp: + INST_ARM64 + dd 0x28000000 + dd ARM64_memory_double_imm7_post_pre_offset + jmp ERROR_instruction_not_32bit +ARM_instruction_sttr: + INST_ARM64 + dd 0x38000c00 + dd ARM64_memory_unprivileged + jmp ERROR_instruction_not_32bit +ARM_instruction_sttrb: + INST_ARM64 + dd 0x38000c00 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_sttrh: + INST_ARM64 + dd 0x38000c01 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_stur: + INST_ARM64 + dd 0x38000400 + dd ARM64_memory_unscaled + jmp ERROR_instruction_not_32bit +ARM_instruction_sturb: + INST_ARM64 + dd 0x38000400 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_sturh: + INST_ARM64 + dd 0x38000401 + dd ARM64_memory_unprivileged_byte_hword + jmp ERROR_instruction_not_32bit +ARM_instruction_stxp: + INST_ARM64 + dd 0x88200000 + dd ARM64_memory_triple_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stxr: + INST_ARM64 + dd 0x88007c00 + dd ARM64_memory_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stxrb: + INST_ARM64 + dd 0x08007c00 + dd ARM64_memory_word_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_stxrh: + INST_ARM64 + dd 0x48007c00 + dd ARM64_memory_word_double_release_fixed + jmp ERROR_instruction_not_32bit +ARM_instruction_sxtw: + INST_ARM64 + dd 0x93407c00 + dd ARM64_dx_nw + jmp ERROR_instruction_not_32bit +ARM_instruction_sys: + INST_ARM64 + dd 0xd5080000 + dd ARM64_sys + jmp ERROR_instruction_not_32bit +ARM_instruction_sysl: + INST_ARM64 + dd 0xd5280000 + dd ARM64_sysl + jmp ERROR_instruction_not_32bit +ARM_instruction_tbnz: + INST_ARM64 + dd 0x37000000 + dd ARM64_tb + jmp ERROR_instruction_not_32bit +ARM_instruction_tbz: + INST_ARM64 + dd 0x36000000 + dd ARM64_tb + jmp ERROR_instruction_not_32bit +ARM_instruction_tlbi: + INST_ARM64 + dd 0xd5000000 + dd ARM64_sys_predefined_tlbi + jmp ERROR_instruction_not_32bit +ARM_instruction_ubfiz: + INST_ARM64 + dd 0x53000000 + dd ARM64_bfi + jmp ERROR_instruction_not_32bit +ARM_instruction_ubfm: + INST_ARM64 + dd 0x53000000 + dd ARM64_bfm + jmp ERROR_instruction_not_32bit +ARM_instruction_umaddl: + INST_ARM64 + dd 0x9ba00000 + dd ARM64_dx_nw_mw_ax + jmp ERROR_instruction_not_32bit +ARM_instruction_umnegl: + INST_ARM64 + dd 0x9ba0fc00 + dd ARM64_dx_nw_mw + jmp ERROR_instruction_not_32bit +ARM_instruction_umsubl: + INST_ARM64 + dd 0x9ba08000 + dd ARM64_dx_nw_mw_ax + jmp ERROR_instruction_not_32bit +ARM_instruction_umulh: + INST_ARM64 + dd 0x9bc07c00 + dd ARM64_xz_xz_xz + jmp ERROR_instruction_not_32bit +ARM_instruction_abs: + INST_ARM64 + dd 0x0e20b800 + dd ARM64_vector_scalar_bhsd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_addhn: + INST_ARM64 + dd 0x0e204000 + dd ARM64_vector_narrow_low + jmp ERROR_instruction_not_32bit +ARM_instruction_addhn2: + INST_ARM64 + dd 0x4e204000 + dd ARM64_vector_narrow_high + jmp ERROR_instruction_not_32bit +ARM_instruction_addp: + INST_ARM64 + dd 0x0e20bc00 + dd ARM64_vector_narrow_3reg_scalar_2reg + jmp ERROR_instruction_not_32bit +ARM_instruction_addv: + INST_ARM64 + dd 0x0e31b800 + dd ARM64_vector_reduce_bhs + jmp ERROR_instruction_not_32bit +ARM_instruction_aesd: + INST_ARM64 + dd 0x4e285800 + dd ARM64_crypto_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_aese: + INST_ARM64 + dd 0x4e284800 + dd ARM64_crypto_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_aesimc: + INST_ARM64 + dd 0x4e287800 + dd ARM64_crypto_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_aesmc: + INST_ARM64 + dd 0x4e286800 + dd ARM64_crypto_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_bif: + INST_ARM64 + dd 0x2ee01c00 + dd ARM64_vector_scalar_b_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_bit: + INST_ARM64 + dd 0x2ea01c00 + dd ARM64_vector_scalar_b_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_bsl: + INST_ARM64 + dd 0x2e601c00 + dd ARM64_vector_scalar_b_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_cmeq: + INST_ARM64 + dd 0x2e208c00 + dd ARM64_vector_scalar_bhsd_three_reg_zero + jmp ERROR_instruction_not_32bit +ARM_instruction_cmge: + INST_ARM64 + dd 0x0e203c00 + dd ARM64_vector_scalar_bhsd_three_reg_zero + jmp ERROR_instruction_not_32bit +ARM_instruction_cmgt: + INST_ARM64 + dd 0x0e203400 + dd ARM64_vector_scalar_bhsd_three_reg_zero + jmp ERROR_instruction_not_32bit +ARM_instruction_cmhi: + INST_ARM64 + dd 0x2e203400 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_cmhs: + INST_ARM64 + dd 0x2e203c00 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_cmle: + INST_ARM64 + dd 0x2e209800 + dd ARM64_vector_scalar_bhsd_two_reg_zero + jmp ERROR_instruction_not_32bit +ARM_instruction_cmlt: + INST_ARM64 + dd 0x0e20a800 + dd ARM64_vector_scalar_bhsd_two_reg_zero + jmp ERROR_instruction_not_32bit +ARM_instruction_cmtst: + INST_ARM64 + dd 0x0e208c00 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_cnt: + INST_ARM64 + dd 0x0e205800 + dd ARM64_vector_b_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_dup: + INST_ARM64 + dd 0x00000000 + dd ARM64_dup + jmp ERROR_instruction_not_32bit +ARM_instruction_ext: + INST_ARM64 + dd 0x2e000000 + dd ARM64_vector_b_three_reg_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_fabd: + INST_ARM64V + dd 0x7ea0d400 ;scalar + dd 0x2ea0d400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fabs: + INST_ARM64V + dd 0x1e20c000 ;scalar + dd 0x0ea0f800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_facge: + INST_ARM64V + dd 0x7e20ec00 ;scalar + dd 0x2e20ec00 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_facgt: + INST_ARM64V + dd 0x7ea0ec00 ;scalar + dd 0x2ea0ec00 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fadd: + INST_ARM64V + dd 0x1e202800 ;scalar + dd 0x0e20d400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_faddp: + INST_ARM64V + dd 0x7e30d800 ;scalar + dd 0x2e20d400 ;vector + dd ARM64_vector_scalar_sd_pairs + jmp ERROR_instruction_not_32bit +ARM_instruction_fccmp: + INST_ARM64 + dd 0x1e200400 + dd ARM64_conditional_compare_float + jmp ERROR_instruction_not_32bit +ARM_instruction_fccmpe: + INST_ARM64 + dd 0x1e200410 + dd ARM64_conditional_compare_float + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmeq: + INST_ARM64V + dd 0x5e20e400 ;scalar + dd 0x0e20e400 ;vector + dd ARM64_vector_scalar_sd_compare_mask_eq + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmge: + INST_ARM64V + dd 0x7e20e400 ;scalar + dd 0x2e20e400 ;vector + dd ARM64_vector_scalar_sd_compare_mask_ge + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmgt: + INST_ARM64V + dd 0x7ea0e400 ;scalar + dd 0x2ea0e400 ;vector + dd ARM64_vector_scalar_sd_compare_mask_gt + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmle: + INST_ARM64V + dd 0x7ea0d800 ;scalar + dd 0x2ea0d800 ;vector + dd ARM64_vector_scalar_sd_compare_mask_le + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmlt: + INST_ARM64V + dd 0x5ea0e800 ;scalar + dd 0x0ea0e800 ;vector + dd ARM64_vector_scalar_sd_compare_mask_le + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmp: + INST_ARM64 + dd 0x1e202000 + dd ARM64_scalar_sd_compare + jmp ERROR_instruction_not_32bit +ARM_instruction_fcmpe: + INST_ARM64 + dd 0x1e202010 + dd ARM64_scalar_sd_compare + jmp ERROR_instruction_not_32bit +ARM_instruction_fcsel: + INST_ARM64 + dd 0x1e200c00 + dd ARM64_scalar_conditional_select + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvt: + INST_ARM64 + dd 0x1e224000 + dd ARM64_scalar_hsd_convert + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtas: + INST_ARM64V + dd 0x5e21c800 ;scalar + dd 0x0e21c800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_as + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtau: + INST_ARM64V + dd 0x7e21c800 ;scalar + dd 0x2e21c800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_au + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtl: + INST_ARM64 + dd 0x0e217800 + dd ARM64_vector_convert_long + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtl2: + INST_ARM64 + dd 0x4e217800 + dd ARM64_vector_convert_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtms: + INST_ARM64V + dd 0x5e21b800 ;scalar + dd 0x0e21b800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_ms + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtmu: + INST_ARM64V + dd 0x7e21b800 ;scalar + dd 0x2e21b800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_mu + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtn: + INST_ARM64 + dd 0x0e216800 + dd ARM64_vector_convert_narrow + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtn2: + INST_ARM64 + dd 0x4e216800 + dd ARM64_vector_convert_narrow2 + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtns: + INST_ARM64V + dd 0x5e21a800 ;scalar + dd 0x0e21a800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_ns + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtnu: + INST_ARM64V + dd 0x7e21a800 ;scalar + dd 0x2e21a800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_nu + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtps: + INST_ARM64V + dd 0x5ea1a800 ;scalar + dd 0x0ea1a800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_ps + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtpu: + INST_ARM64V + dd 0x7ea1a800 ;scalar + dd 0x2ea1a800 ;vector + dd ARM64_vector_scalar_sdwx_two_reg_pu + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtxn: + INST_ARM64V + dd 0x7e616800 ;scalar + dd 0x2e616800 ;vector + dd ARM64_vector_convert_odd_narrow + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtxn2: + INST_ARM64 + dd 0x6e616800 + dd ARM64_vector_convert_odd_narrow2 + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtzs: + INST_ARM64V + dd 0x5ea1b800 ;scalar + dd 0x0ea1b800 ;vector + dd ARM64_vector_scalar_sd_convert_zero_s + jmp ERROR_instruction_not_32bit +ARM_instruction_fcvtzu: + INST_ARM64V + dd 0x7ea1b800 ;scalar + dd 0x2ea1b800 ;vector + dd ARM64_vector_scalar_sd_convert_zero_u + jmp ERROR_instruction_not_32bit +ARM_instruction_fdiv: + INST_ARM64V + dd 0x1e201800 ;scalar + dd 0x2e20fc00 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fmadd: + INST_ARM64 + dd 0x1f000000 + dd ARM64_scalar_sd_four_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fmax: + INST_ARM64V + dd 0x1e204800 ;scalar + dd 0x0e20f400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fmaxnm: + INST_ARM64V + dd 0x1e206800 ;scalar + dd 0x0e20c400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fmaxnmp: + INST_ARM64V + dd 0x7e30c800 ;scalar + dd 0x2e20c400 ;vector + dd ARM64_vector_scalar_sd_pairs + jmp ERROR_instruction_not_32bit +ARM_instruction_fmaxnmv: + INST_ARM64 + dd 0x6e30c800 + dd ARM64_vector_4_to_1 + jmp ERROR_instruction_not_32bit +ARM_instruction_fmaxp: + INST_ARM64V + dd 0x7e30f800 ;scalar + dd 0x2e20f400 ;vector + dd ARM64_vector_scalar_sd_pairs + jmp ERROR_instruction_not_32bit +ARM_instruction_fmaxv: + INST_ARM64 + dd 0x6e30f800 + dd ARM64_vector_4_to_1 + jmp ERROR_instruction_not_32bit +ARM_instruction_fmin: + INST_ARM64V + dd 0x1e205800 ;scalar + dd 0x0ea0f400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fminnm: + INST_ARM64V + dd 0x1e207800 ;scalar + dd 0x0ea0c400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fminnmp: + INST_ARM64V + dd 0x7eb0c800 ;scalar + dd 0x2ea0c400 ;vector + dd ARM64_vector_scalar_sd_pairs + jmp ERROR_instruction_not_32bit +ARM_instruction_fminnmv: + INST_ARM64 + dd 0x6eb0c800 + dd ARM64_vector_4_to_1 + jmp ERROR_instruction_not_32bit +ARM_instruction_fminp: + INST_ARM64V + dd 0x7eb0f800 ;scalar + dd 0x2ea0f400 ;vector + dd ARM64_vector_scalar_sd_pairs + jmp ERROR_instruction_not_32bit +ARM_instruction_fminv: + INST_ARM64 + dd 0x6eb0f800 + dd ARM64_vector_4_to_1 + jmp ERROR_instruction_not_32bit +ARM_instruction_fmla: + INST_ARM64V + dd 0x5f801000 ;scalar + dd 0x0f801000 ;vector + dd ARM64_vector_scalar_sd_two_reg_element_add + jmp ERROR_instruction_not_32bit +ARM_instruction_fmov: + INST_ARM64 + dd 0x00000000 + dd ARM64_fmov + jmp ERROR_instruction_not_32bit +ARM_instruction_fmsub: + INST_ARM64 + dd 0x1f008000 + dd ARM64_scalar_sd_four_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fmul: + INST_ARM64V + dd 0x1e200800 ;scalar + dd 0x2e20dc00 ;vector + dd ARM64_vector_scalar_sd_three_reg_element + jmp ERROR_instruction_not_32bit +ARM_instruction_fmulx: + INST_ARM64V + dd 0x5e20dc00 ;scalar + dd 0x0e20dc00 ;vector + dd ARM64_vector_scalar_sd_three_reg_element_x + jmp ERROR_instruction_not_32bit +ARM_instruction_fneg: + INST_ARM64V + dd 0x1e214000 ;scalar + dd 0x2ea0f800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fnmadd: + INST_ARM64 + dd 0x1f200000 + dd ARM64_scalar_sd_four_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fnmsub: + INST_ARM64 + dd 0x1f208000 + dd ARM64_scalar_sd_four_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fnmul: + INST_ARM64 + dd 0x1e208800 + dd ARM64_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frecpe: + INST_ARM64V + dd 0x5ea1d800 ;scalar + dd 0x0ea1d800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frecps: + INST_ARM64V + dd 0x5e20fc00 ;scalar + dd 0x0e20fc00 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frecpx: + INST_ARM64 + dd 0x5ea1f800 + dd ARM64_scalar_sd_rwo_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frinta: + INST_ARM64V + dd 0x1e264000 ;scalar + dd 0x2e218800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frinti: + INST_ARM64V + dd 0x1e27c000 ;scalar + dd 0x2ea19800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frintm: + INST_ARM64V + dd 0x1e254000 ;scalar + dd 0x0e219800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frintn: + INST_ARM64V + dd 0x1e244000 ;scalar + dd 0x0e218800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frintp: + INST_ARM64V + dd 0x1e24c000 ;scalar + dd 0x0ea18800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frintx: + INST_ARM64V + dd 0x1e274000 ;scalar + dd 0x2e219800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frintz: + INST_ARM64V + dd 0x1e25c000 ;scalar + dd 0x0ea19800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frsqrte: + INST_ARM64V + dd 0x7ea1d800 ;scalar + dd 0x2ea1d800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_frsqrts: + INST_ARM64V + dd 0x5ea0fc00 ;scalar + dd 0x0ea0fc00 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fsqrt: + INST_ARM64V + dd 0x1e21c000 ;scalar + dd 0x2ea1f800 ;vector + dd ARM64_vector_scalar_sd_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_fsub: + INST_ARM64V + dd 0x1e203800 ;scalar + dd 0x0ea0d400 ;vector + dd ARM64_vector_scalar_sd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_ins: + INST_ARM64 + dd 0x00000000 + dd ARM64_ins +ARM_instruction_ld1: + INST_ARM64V + dd 0x0dc00000 ;single + dd 0x0cc02000 ;multiple + dd ARM64_ld1 + jmp ERROR_instruction_not_32bit +ARM_instruction_ld1r: + INST_ARM64 + dd 0x0dc0c000 + dd ARM64_ld1r +ARM_instruction_ld2: + INST_ARM64V + dd 0x0de00000 ;single + dd 0x0cc00000 ;multiple + dd ARM64_ld2 + jmp ERROR_instruction_not_32bit +ARM_instruction_ld2r: + INST_ARM64 + dd 0x0de0c000 + dd ARM64_ld2r +ARM_instruction_ld3: + INST_ARM64V + dd 0x0dc02000 ;single + dd 0x0cc00000 ;multiple + dd ARM64_ld3 + jmp ERROR_instruction_not_32bit +ARM_instruction_ld3r: + INST_ARM64 + dd 0x0dc0e000 + dd ARM64_ld3r +ARM_instruction_ld4: + INST_ARM64V + dd 0x0de02000 ;single + dd 0x0cc00000 ;multiple + dd ARM64_ld4 + jmp ERROR_instruction_not_32bit +ARM_instruction_ld4r: + INST_ARM64 + dd 0x0de0e000 + dd ARM64_ld4r +ARM_instruction_movi: + INST_ARM64 + dd 0x0f000400 + dd ARM64_movi +ARM_instruction_mvni: + INST_ARM64 + dd 0x2f000400 + dd ARM64_mvni +ARM_instruction_not: + INST_ARM64 + dd 0x2e205800 + dd ARM64_vector_b_two_reg +ARM_instruction_pmul: + INST_ARM64 + dd 0x2e209c00 + dd ARM64_vector_scalar_b_three_reg +ARM_instruction_pmull: + INST_ARM64 + dd 0x0e20e000 + dd ARM64_polynomial +ARM_instruction_pmull2: + INST_ARM64 + dd 0x4e20e000 + dd ARM64_polynomial2 +ARM_instruction_raddhn: + INST_ARM64 + dd 0x2e204000 + dd ARM64_vector_narrow_low + jmp ERROR_instruction_not_32bit +ARM_instruction_raddhn2: + INST_ARM64 + dd 0x6e204000 + dd ARM64_vector_narrow_high + jmp ERROR_instruction_not_32bit +ARM_instruction_rshrn: + INST_ARM64 + dd 0x0f008c00 + dd ARM64_vector_narrow_shift_low + jmp ERROR_instruction_not_32bit +ARM_instruction_rshrn2: + INST_ARM64 + dd 0x4f008c00 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_rsubhn: + INST_ARM64 + dd 0x2e206000 + dd ARM64_vector_narrow_low + jmp ERROR_instruction_not_32bit +ARM_instruction_rsubhn2: + INST_ARM64 + dd 0x6e206000 + dd ARM64_vector_narrow_high + jmp ERROR_instruction_not_32bit +ARM_instruction_saba: + INST_ARM64 + dd 0x0e207c00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sabal: + INST_ARM64 + dd 0x0e205000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sabal2: + INST_ARM64 + dd 0x4e205000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sabd: + INST_ARM64 + dd 0x0e207400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sabdl: + INST_ARM64 + dd 0x0e207000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sabdl2: + INST_ARM64 + dd 0x4e207000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sadalp: + INST_ARM64 + dd 0x0e206800 + dd ARM64_vector_bhs_two_reg_pair + jmp ERROR_instruction_not_32bit +ARM_instruction_saddl: + INST_ARM64 + dd 0x0e200000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_saddl2: + INST_ARM64 + dd 0x4e200000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_saddlp: + INST_ARM64 + dd 0x0e202800 + dd ARM64_vector_bhs_two_reg_pair + jmp ERROR_instruction_not_32bit +ARM_instruction_saddlv: + INST_ARM64 + dd 0x0e303800 + dd ARM64_scalar_vector_bhs_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_saddw: + INST_ARM64 + dd 0x0e201000 + dd ARM64_vector_bhs_three_reg_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_saddw2: + INST_ARM64 + dd 0x4e201000 + dd ARM64_vector_bhs_three_reg_wide2 + jmp ERROR_instruction_not_32bit +ARM_instruction_scvtf: + INST_ARM64V + dd 0x5e21d800 ;scalar + dd 0x0e21d800 ;vector + dd ARM64_scalar_vector_sd_convert_zero_s + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1c: + INST_ARM64 + dd 0x5e000000 + dd ARM64_sha_qsv + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1h: + INST_ARM64 + dd 0x5e280800 + dd ARM64_sha_s_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1m: + INST_ARM64 + dd 0x5e002000 + dd ARM64_sha_qsv + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1p: + INST_ARM64 + dd 0x5e001000 + dd ARM64_sha_qsv + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1su0: + INST_ARM64 + dd 0x5e003000 + dd ARM64_sha_vs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sha1su1: + INST_ARM64 + dd 0x5e281800 + dd ARM64_sha_vs_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sha256h: + INST_ARM64 + dd 0x5e004000 + dd ARM64_sha_qqv + jmp ERROR_instruction_not_32bit +ARM_instruction_sha256h2: + INST_ARM64 + dd 0x5e005000 + dd ARM64_sha_qqv + jmp ERROR_instruction_not_32bit +ARM_instruction_sha256su0: + INST_ARM64 + dd 0x5e282800 + dd ARM64_sha_vs_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sha256su1: + INST_ARM64 + dd 0x5e006000 + dd ARM64_sha_vs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_shadd: + INST_ARM64 + dd 0x0e200400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_shl: + INST_ARM64 + dd 0x0f005400 + dd ARM64_vector_scalar_bhsd_two_reg_left_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_shll: + INST_ARM64 + dd 0x2e213800 + dd ARM64_vector_scalar_bhs_long_size + jmp ERROR_instruction_not_32bit +ARM_instruction_shll2: + INST_ARM64 + dd 0x6e213800 + dd ARM64_vector_scalar_bhs_long2_size + jmp ERROR_instruction_not_32bit +ARM_instruction_shrn: + INST_ARM64 + dd 0x0f008400 + dd ARM64_vector_narrow_shift_low + jmp ERROR_instruction_not_32bit +ARM_instruction_shrn2: + INST_ARM64 + dd 0x4f008400 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_shsub: + INST_ARM64 + dd 0x0e202400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sli: + INST_ARM64 + dd 0x2f005400 + dd ARM64_vector_scalar_bhsd_two_reg_left_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_smax: + INST_ARM64 + dd 0x0e206400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_smaxp: + INST_ARM64 + dd 0x0e20a400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_smaxv: + INST_ARM64 + dd 0x0e30a800 + dd ARM64_vector_reduce_bhs + jmp ERROR_instruction_not_32bit +ARM_instruction_smin: + INST_ARM64 + dd 0x0e206c00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sminp: + INST_ARM64 + dd 0x0e20ac00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sminv: + INST_ARM64 + dd 0x0e31a800 + dd ARM64_vector_reduce_bhs + jmp ERROR_instruction_not_32bit +ARM_instruction_smlal2: + INST_ARM64V + dd 0x4e208000 ;vector + dd 0x4f002000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_smlsl: + INST_ARM64V + dd 0x0e20a000 ;vector + dd 0x0f006000 ;element + dd ARM64_arithmetic18_long + jmp ERROR_instruction_not_32bit +ARM_instruction_smlsl2: + INST_ARM64V + dd 0x4e20a000 ;vector + dd 0x4f006000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_smov: + INST_ARM64 + dd 0x0e002c00 + dd ARM64_smov + jmp ERROR_instruction_not_32bit +ARM_instruction_smull2: + INST_ARM64V + dd 0x4e20c000 ;vector + dd 0x4f00a000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqabs: + INST_ARM64 + dd 0x0e207800 + dd ARM64_vector_scalar_bhsd_two_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sqadd: + INST_ARM64 + dd 0x0e200c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmlal: + INST_ARM64V + dd 0x0e209000 ;vector + dd 0x0f003000 ;element + dd ARM64_arithmetic19_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmlal2: + INST_ARM64V + dd 0x4e209000 ;vector + dd 0x4f003000 ;element + dd ARM64_arithmetic19_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmlsl: + INST_ARM64V + dd 0x0e20b000 ;vector + dd 0x0f007000 ;element + dd ARM64_arithmetic19_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmlsl2: + INST_ARM64V + dd 0x4e20b000 ;vector + dd 0x4f007000 ;element + dd ARM64_arithmetic19_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmulh: + INST_ARM64V + dd 0x0e20b400 ;vector + dd 0x0f00c000 ;element + dd ARM64_arithmetic20 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmull: + INST_ARM64V + dd 0x0e20d000 ;vector + dd 0x0f00b000 ;element + dd ARM64_arithmetic19_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sqdmull2: + INST_ARM64V + dd 0x4e20d000 ;vector + dd 0x4f00b000 ;element + dd ARM64_arithmetic19_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqneg: + INST_ARM64 + dd 0x2e207800 + dd ARM64_vector_scalar_bhsd_two_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrdmulh: + INST_ARM64V + dd 0x2e20b400 ;vector + dd 0x0f00d000 ;element + dd ARM64_arithmetic20 + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrshl: + INST_ARM64 + dd 0x0e205c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrshrn: + INST_ARM64 + dd 0x0f009c00 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrshrn2: + INST_ARM64 + dd 0x4f009c00 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrshrun: + INST_ARM64 + dd 0x2f008c00 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqrshrun2: + INST_ARM64 + dd 0x6f008c00 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshl: + INST_ARM64V + dd 0x0e204c00 ;register + dd 0x0f007400 ;immediate + dd ARM64_vector_scalar_bhsd_shift_reg_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshlu: + INST_ARM64 + dd 0x2f006400 + dd ARM64_vector_scalar_bhsd_shift_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshrn: + INST_ARM64 + dd 0x0f009400 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshrn2: + INST_ARM64 + dd 0x4f009400 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshrun: + INST_ARM64 + dd 0x2f008400 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqshrun2: + INST_ARM64 + dd 0x6f008400 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqsub: + INST_ARM64 + dd 0x0e202c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sqxtn: + INST_ARM64 + dd 0x0e214800 + dd ARM64_vector_scalar_narrow_extract_low + jmp ERROR_instruction_not_32bit +ARM_instruction_sqxtn2: + INST_ARM64 + dd 0x4e214800 + dd ARM64_vector_narrow_extract_high + jmp ERROR_instruction_not_32bit +ARM_instruction_sqxtun: + INST_ARM64 + dd 0x2e212800 + dd ARM64_vector_scalar_narrow_extract_low + jmp ERROR_instruction_not_32bit +ARM_instruction_sqxtun2: + INST_ARM64 + dd 0x6e212800 + dd ARM64_vector_narrow_extract_high + jmp ERROR_instruction_not_32bit +ARM_instruction_srhadd: + INST_ARM64 + dd 0x0e201400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sri: + INST_ARM64 + dd 0x2f004400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_srshl: + INST_ARM64 + dd 0x0e205400 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_srshr: + INST_ARM64 + dd 0x0f002400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_srsra: + INST_ARM64 + dd 0x0f003400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_sshl: + INST_ARM64 + dd 0x0e204400 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_sshll: + INST_ARM64 + dd 0x0f00a400 + dd ARM64_vector_scalar_bhs_long_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_sshll2: + INST_ARM64 + dd 0x4f00a400 + dd ARM64_vector_scalar_bhs_long2_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_sshr: + INST_ARM64 + dd 0x0f000400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ssra: + INST_ARM64 + dd 0x0f001400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ssubl: + INST_ARM64 + dd 0x0e202000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_ssubl2: + INST_ARM64 + dd 0x4e202000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_ssubw: + INST_ARM64 + dd 0x0e203000 + dd ARM64_vector_bhs_three_reg_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_ssubw2: + INST_ARM64 + dd 0x4e203000 + dd ARM64_vector_bhs_three_reg_wide2 + jmp ERROR_instruction_not_32bit +ARM_instruction_st1: + INST_ARM64V + dd 0x0d800000 ;single + dd 0x0c802000 ;multiple + dd ARM64_ld1 + jmp ERROR_instruction_not_32bit +ARM_instruction_st2: + INST_ARM64V + dd 0x0da00000 ;single + dd 0x0c800000 ;multiple + dd ARM64_ld2 + jmp ERROR_instruction_not_32bit +ARM_instruction_st3: + INST_ARM64V + dd 0x0d802000 ;single + dd 0x0c800000 ;multiple + dd ARM64_ld3 + jmp ERROR_instruction_not_32bit +ARM_instruction_st4: + INST_ARM64V + dd 0x0da02000 ;single + dd 0x0c800000 ;multiple + dd ARM64_ld4 + jmp ERROR_instruction_not_32bit +ARM_instruction_subhn: + INST_ARM64 + dd 0x0e206000 + dd ARM64_vector_narrow_low + jmp ERROR_instruction_not_32bit +ARM_instruction_subhn2: + INST_ARM64 + dd 0x4e206000 + dd ARM64_vector_narrow_high + jmp ERROR_instruction_not_32bit +ARM_instruction_suqadd: + INST_ARM64 + dd 0x0e203800 + dd ARM64_vector_scalar_bhsd_two_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_sxtl: + INST_ARM64 + dd 0x0f00a400 + dd ARM64_vector_scalar_bhs_long + jmp ERROR_instruction_not_32bit +ARM_instruction_sxtl2: + INST_ARM64 + dd 0x4f00a400 + dd ARM64_vector_scalar_bhs_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_tbl: + INST_ARM64 + dd 0x0e000000 + dd ARM64_tb1 + jmp ERROR_instruction_not_32bit +ARM_instruction_tbx: + INST_ARM64 + dd 0x0e001000 + dd ARM64_tb1 + jmp ERROR_instruction_not_32bit +ARM_instruction_trn1: + INST_ARM64 + dd 0x0e002800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_trn2: + INST_ARM64 + dd 0x0e006800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uaba: + INST_ARM64 + dd 0x2e207c00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uabal: + INST_ARM64 + dd 0x2e205000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_uabal2: + INST_ARM64 + dd 0x6e205000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uabd: + INST_ARM64 + dd 0x2e207400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uabdl: + INST_ARM64 + dd 0x2e207000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_uabdl2: + INST_ARM64 + dd 0x6e207000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uadalp: + INST_ARM64 + dd 0x2e206800 + dd ARM64_vector_bhs_two_reg_pair + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddl: + INST_ARM64 + dd 0x2e200000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddl2: + INST_ARM64 + dd 0x6e200000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddlp: + INST_ARM64 + dd 0x2e202800 + dd ARM64_vector_bhs_two_reg_pair + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddlv: + INST_ARM64 + dd 0x2e303800 + dd ARM64_scalar_vector_bhs_two_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddw: + INST_ARM64 + dd 0x2e201000 + dd ARM64_vector_bhs_three_reg_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_uaddw2: + INST_ARM64 + dd 0x6e201000 + dd ARM64_vector_bhs_three_reg_wide2 + jmp ERROR_instruction_not_32bit +ARM_instruction_ucvtf: + INST_ARM64V + dd 0x7e21d800 ;scalar + dd 0x2e21d800 ;vector + dd ARM64_scalar_vector_sd_convert_zero_u + jmp ERROR_instruction_not_32bit +ARM_instruction_uhadd: + INST_ARM64 + dd 0x2e200400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uhsub: + INST_ARM64 + dd 0x2e202400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_umax: + INST_ARM64 + dd 0x2e206400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_umaxp: + INST_ARM64 + dd 0x2e20a400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_umaxv: + INST_ARM64 + dd 0x2e30a800 + dd ARM64_vector_reduce_bhs + jmp ERROR_instruction_not_32bit +ARM_instruction_umin: + INST_ARM64 + dd 0x2e206c00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uminp: + INST_ARM64 + dd 0x2e20ac00 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uminv: + INST_ARM64 + dd 0x2e31a800 + dd ARM64_vector_reduce_bhs + jmp ERROR_instruction_not_32bit +ARM_instruction_umlal2: + INST_ARM64V + dd 0x6e208000 ;vector + dd 0x6f002000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_umlsl: + INST_ARM64V + dd 0x2e20a000 ;vector + dd 0x2f006000 ;element + dd ARM64_arithmetic18_long + jmp ERROR_instruction_not_32bit +ARM_instruction_umlsl2: + INST_ARM64V + dd 0x6e20a000 ;vector + dd 0x6f006000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_umov: + INST_ARM64 + dd 0x0e003c00 + dd ARM64_umov + jmp ERROR_instruction_not_32bit +ARM_instruction_umull2: + INST_ARM64V + dd 0x6e20c000 ;vector + dd 0x6f00a000 ;element + dd ARM64_arithmetic18_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uqadd: + INST_ARM64 + dd 0x2e200c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_uqrshl: + INST_ARM64 + dd 0x2e205c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_uqrshrn: + INST_ARM64 + dd 0x2f009c00 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_uqrshrn2: + INST_ARM64 + dd 0x6f009c00 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_uqshl: + INST_ARM64V + dd 0x2e204c00 ;register + dd 0x2f007400 ;immediate + dd ARM64_vector_scalar_bhsd_shift_reg_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_uqshrn: + INST_ARM64 + dd 0x2f009400 + dd ARM64_vector_scalar_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_uqshrn2: + INST_ARM64 + dd 0x6f009400 + dd ARM64_vector_narrow_shift_high + jmp ERROR_instruction_not_32bit +ARM_instruction_uqsub: + INST_ARM64 + dd 0x2e202c00 + dd ARM64_vector_scalar_bhsd_three_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_uqxtn: + INST_ARM64 + dd 0x2e214800 + dd ARM64_vector_scalar_narrow_extract_low + jmp ERROR_instruction_not_32bit +ARM_instruction_uqxtn2: + INST_ARM64 + dd 0x6e214800 + dd ARM64_vector_narrow_extract_high + jmp ERROR_instruction_not_32bit +ARM_instruction_urecpe: + INST_ARM64 + dd 0x0ea1c800 + dd ARM64_arithmetic21 + jmp ERROR_instruction_not_32bit +ARM_instruction_urhadd: + INST_ARM64 + dd 0x2e201400 + dd ARM64_vector_bhs_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_urshl: + INST_ARM64 + dd 0x2e205400 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_urshr: + INST_ARM64 + dd 0x2f002400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ursqrte: + INST_ARM64 + dd 0x2ea1c800 + dd ARM64_arithmetic21 + jmp ERROR_instruction_not_32bit +ARM_instruction_ursra: + INST_ARM64 + dd 0x2f003400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ushl: + INST_ARM64 + dd 0x2e204400 + dd ARM64_vector_scalar_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_ushll: + INST_ARM64 + dd 0x2f00a400 + dd ARM64_vector_scalar_bhs_long_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ushll2: + INST_ARM64 + dd 0x6f00a400 + dd ARM64_vector_scalar_bhs_long2_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_ushr: + INST_ARM64 + dd 0x2f000400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_usqadd: + INST_ARM64 + dd 0x2e203800 + dd ARM64_vector_scalar_bhsd_two_reg_q + jmp ERROR_instruction_not_32bit +ARM_instruction_usra: + INST_ARM64 + dd 0x2f001400 + dd ARM64_vector_scalar_bhsd_two_reg_right_imm + jmp ERROR_instruction_not_32bit +ARM_instruction_usubl: + INST_ARM64 + dd 0x2e202000 + dd ARM64_vector_bhs_three_reg_long + jmp ERROR_instruction_not_32bit +ARM_instruction_usubl2: + INST_ARM64 + dd 0x6e202000 + dd ARM64_vector_bhs_three_reg_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_usubw: + INST_ARM64 + dd 0x2e203000 + dd ARM64_vector_bhs_three_reg_wide + jmp ERROR_instruction_not_32bit +ARM_instruction_usubw2: + INST_ARM64 + dd 0x6e203000 + dd ARM64_vector_bhs_three_reg_wide2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uxtl: + INST_ARM64 + dd 0x2f00a400 + dd ARM64_vector_scalar_bhs_long + jmp ERROR_instruction_not_32bit +ARM_instruction_uxtl2: + INST_ARM64 + dd 0x6f00a400 + dd ARM64_vector_scalar_bhs_long2 + jmp ERROR_instruction_not_32bit +ARM_instruction_uzp1: + INST_ARM64 + dd 0x0e001800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_uzp2: + INST_ARM64 + dd 0x0e005800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_xtn: + INST_ARM64 + dd 0x0e212800 + dd ARM64_vector_narrow_extract_low + jmp ERROR_instruction_not_32bit +ARM_instruction_xtn2: + INST_ARM64 + dd 0x4e212800 + dd ARM64_vector_narrow_extract_high + jmp ERROR_instruction_not_32bit +ARM_instruction_zip1: + INST_ARM64 + dd 0x0e003800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit +ARM_instruction_zip2: + INST_ARM64 + dd 0x0e007800 + dd ARM64_vector_bhsd_three_reg + jmp ERROR_instruction_not_32bit + +;special + +ARM_instruction_crc32: + jmp CRC_32 + +ARM_set_virtual: + call allocate_structure_data + mov al,[IT_anchor_distance] + mov ecx,[potential_IT_anchor] + mov edx,[explicit_IT_state] + mov ebp,[current_IT_block] + mov word[ebx],ARM_set_virtual-instruction_handler + mov [ebx+2],al + mov [ebx+4],ecx + mov [ebx+8],edx + mov [ebx+12],ebp + mov ax,[anchor_instruction] + mov [ebx+16],ax + xor eax,eax + mov [IT_anchor_distance],al + mov [potential_IT_anchor],eax + mov [explicit_IT_state],eax + mov [current_IT_block],eax + mov [anchor_instruction],ax + jmp instruction_assembled + +ARM_square_parser: + mov al,'[' + stosb + .next: + lodsb + test al,al + jz .close + cmp al,']' + jz .done + cmp al,',' + jz .store + cmp al,'#' + jz .store + cmp al,01ah + jnz .expression + lodsb + movzx ecx,al + push edi + mov edi,symbols + call get_symbol + pop edi + jnc .symbol + sub esi,1 + .expression: + sub esi,1 + mov al,'(' + stosb + push edi + call convert_expression + pop eax + cmp byte[eax],'!' + jnz .converted_okay + inc esi + .converted_okay: + mov al,')' + .store: + stosb + jmp .next + .symbol: + stosw + jmp .next + .close: + dec esi + .done: + stosb + jmp argument_parsed + +ARM_curly_parser: + mov al,0x91 + stosb + .next: + lodsb + test al,al + jz .close + cmp al,'}' + jz .done + cmp al,',' + jz .store + cmp al,'[' + jz .store + cmp al,']' + jz .store + cmp al,'-' + jz .store + cmp al,'#' + jz .store + cmp al,01ah + jnz .expression + lodsb + movzx ecx,al + push edi + mov edi,symbols + call get_symbol + pop edi + jnc .symbol + sub esi,1 + .expression: + sub esi,1 + mov al,'(' + stosb + push edi + call convert_expression + pop eax + cmp byte[eax],'!' + jnz .converted_okay + inc esi + .converted_okay: + mov al,')' + .store: + stosb + jmp .next + .symbol: + stosw + jmp .next + .close: + dec esi + stosb + jmp argument_parsed + .done: + mov al,0x92 + stosb + jmp argument_parsed + +ARM_calculate_expression: + xor eax,eax + mov [edi+8],eax + mov [edi+12],eax + push [error] [error_info] [error_line] + mov [error_line],0 + mov [value_size],0 + cmp byte[esi],'.' ;float? + jnz .size_known + mov [value_size],4 + .size_known: + call calculate_expression + mov ecx,[error_line] + test ecx,ecx + jz .no_error + mov [ARM_error_line],ecx + pop ecx + test ecx,ecx + jz .new_error + mov [error_line],ecx + pop [error_info] [error] + stc + ret + .new_error: + pop ecx ecx + stc + ret + .no_error: + pop [error_line] [error_info] [error] + clc + ret + +ARM_defer_error: + mov ebp,UNENCODEABLE_INSTRUCTION_ARM + cmp [error_line],0 + jne @f + mov [error],ecx + mov ecx,[current_line] + mov [error_line],ecx + @@: mov ecx,[current_line] + mov [ARM_error_line],ecx + ret + +ARM_store_instruction_with_error: + call ARM_defer_error + jmp ARM_store_instruction.store +ARM_store_instruction: + cmp ebp,0xf shl 28 + jb .unconditional_okay + mov ah,[instruction_condition] + and ah,0xf0 + cmp ah,0xe0 + jb ERROR_instruction_not_conditional + .unconditional_okay: + cmp [explicit_IT_state],0 + jz .explicit_okay + mov cl,byte[explicit_IT_state] ;get currently specified condition + mov ch,[instruction_condition] + and cx,0xf0f0 + cmp ch,cl + mov ecx,ERROR_condition_does_not_match_IT_specifier + jnz ARM_store_instruction_with_error + .explicit_okay: + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + test eax,3 + mov ecx,ERROR_instruction_not_aligned + jnz ARM_store_instruction_with_error + .store: + shr [explicit_IT_state],8 + cmp [error_line],0 + jz .store_instruction + mov ecx,[current_line] + cmp [ARM_error_line],ecx + jnz .store_instruction + cmp [current_pass],1 + jbe .store_instruction + cmp [error],ERROR_immediate_cannot_be_encoded + jz .soft_error + cmp [error],ERROR_immediate_offset_out_of_range + jz .soft_error + cmp [error],ERROR_value_out_of_range + jne .store_instruction + .soft_error: + or ebp,-1 ;set to this value so that we can use if/else/end if to detect unencodable instructions + .store_instruction: + mov [edi],ebp + add edi,4 + jmp instruction_assembled + +ARM64_store_instruction: + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + test eax,3 + mov ecx,ERROR_instruction_not_aligned + jnz ARM_store_instruction_with_error + .store: + cmp [error_line],0 + jz .store_instruction + mov ecx,[current_line] + cmp [ARM_error_line],ecx + jnz .store_instruction + cmp [current_pass],1 + jbe .store_instruction + cmp [error],ERROR_immediate_cannot_be_encoded + jz .soft_error + cmp [error],ERROR_immediate_offset_out_of_range + jz .soft_error + cmp [error],ERROR_value_out_of_range + jne .store_instruction + .soft_error: + or ebp,-1 ;set to this value so that we can use if/else/end if to detect unencodable instructions + .store_instruction: + mov [edi],ebp + add edi,4 + jmp instruction_assembled + +;we must supply this function for expressi.inc to assemble +;called by exprcalc.inc during store +get_size_operator: + xor ah,ah + cmp al,11h + jne .no_size_operator + mov [size_declared],1 + lods word[esi] + xchg al,ah + mov [operand_flags],1 + cmp ah,[operand_size] + je .size_operator_ok + cmp [operand_size],0 + jne operand_sizes_do_not_match + mov [operand_size],ah + .size_operator_ok: + ret + .no_size_operator: + mov [size_declared],0 + cmp al,'[' + jne .size_operator_ok + mov [operand_flags],0 + ret + +;we must provide this function for assemble.inc + +segment_prefix = ERROR_illegal_instruction + +;use a custom instruction searcher to convert '~~' to conditionals + +conditional_strings: + db 'eq',0,0x00 + db 'ne',0,0x10 + db 'cs',0,0x20 + db 'cc',0,0x30 + db 'mi',0,0x40 + db 'pl',0,0x50 + db 'vs',0,0x60 + db 'vc',0,0x70 + db 'hi',0,0x80 + db 'ls',0,0x90 + db 'ge',0,0xa0 + db 'lt',0,0xb0 + db 'gt',0,0xc0 + db 'le',0,0xd0 + db 'al',0,0xe0 + db 'hs',0,0x20 + db 'lo',0,0x30 + db 0 + +ARM_get_instruction: + ;esi=pointer to string + ;ecx=length of string + push esi ecx + call ARM_find_instruction + jnc .found + lea edi,[converted+ecx-2] + .try_condition: + cmp edi,converted + jbe .not_found + mov ax,[edi] + mov esi,conditional_strings + .next_condition: + cmp ax,[esi] + jz .condition_matched + add esi,4 + cmp byte[esi],0 + jnz .next_condition + .next_position: + dec edi + jmp .try_condition + .condition_matched: + push dword[edi] + mov word[edi],CONDITION_SEARCH_CHARACTER*0x101 + movzx eax,byte[esi+3] + push eax edi + mov esi,converted + call ARM_find_instruction + pop edi edx + pop dword[edi] + jc .next_position + or al,dl + .found: + pop ecx esi + add esi,ecx + clc + ret + .not_found: + pop ecx esi + stc + ret + +ARM_find_instruction: + push esi + mov ebp,ecx + mov byte[characters+CONDITION_SEARCH_CHARACTER],CONDITION_SEARCH_CHARACTER + call lower_case + mov byte[characters+CONDITION_SEARCH_CHARACTER],0 + mov ecx,ebp + cmp cl,16 + ja .no_instruction + sub cl,1 + jc .no_instruction + mov ebx,[instructions+ecx*8] + add ebx,instructions + mov edx,[instructions+ecx*8+4] + .scan_instructions: + or edx,edx + jz .no_instruction + mov eax,edx + shr eax,1 + lea edi,[ebp+3] + imul eax,edi + lea edi,[ebx+eax] + mov esi,converted + mov ecx,ebp + repe cmps byte [esi],[edi] + ja .instructions_up + jb .instructions_down + pop esi + add esi,ebp + mov al,[edi] + mov bx,[edi+1] + clc + ret + .no_instruction: + pop esi + mov ecx,ebp + stc + ret + .instructions_down: + shr edx,1 + jmp .scan_instructions + .instructions_up: + lea ebx,[edi+ecx+3] + shr edx,1 + adc edx,-1 + jmp .scan_instructions + +;custom handler to store address of line start + +virtual + INST_ARM64 + assert $-1=$$ + load ARM64_ENCODING byte from $-1 +end virtual +virtual + INST_ARM64S + assert $-1=$$ + load ARM64S_ENCODING byte from $-1 ;for instruction that allow setting the flags +end virtual +virtual + INST_ARM64V + assert $-1=$$ + load ARM64V_ENCODING byte from $-1 ;for instruction that allow setting the flags +end virtual + +ARM_instruction_handler: + movzx ebx,word[esi] + mov al,[esi+2] + add esi,3 + mov [force_wide_flag],esi + POP vdx + add ebx,edx + cmp ebx,ARM_code_generator_start ;directives and other non-instructions + jb .execute + cmp byte[ebx],ARM64_ENCODING + jz .check_64bit + cmp byte[ebx],ARM64S_ENCODING + jz .check_64bit + cmp byte[ebx],ARM64V_ENCODING + jz .check_64bit + test [code_type],CPU_ACTIVITY_ARM64 + jnz ERROR_instruction_not_64bit + .execute: + jmp vbx + .check_64bit: + test [code_type],CPU_ACTIVITY_ARM64 + jnz .64bit + add ebx,9 + cmp byte[ebx-9],ARM64V_ENCODING + jnz .execute_ARM + add ebx,4 + .execute_ARM: + jmp vbx + .64bit: + cmp byte[ebx],ARM64S_ENCODING + jz .64bit_s + test al,FLAG_CONDITION_SET + jnz ERROR_cannot_set_flags + cmp byte[ebx],ARM64V_ENCODING + jz .64bit_v + .64bit_s: + mov ecx,[ebx+1] ;get instruction template + mov edx,ecx + or edx,1 shl 29 ;set S + test al,FLAG_CONDITION_SET + cmovnz ecx,edx + cmp al,0xe0 + jb ERROR_instruction_not_conditional + mov ebx,[ebx+5] + jmp vbx + .64bit_v: + mov ecx,[ebx+1] ;get scalar instruction template + mov edx,[ebx+5] ;get vector instruction template + cmp al,0xe0 + jb ERROR_instruction_not_conditional + mov ebx,[ebx+9] + jmp vbx + +ARM_opcode_swap_table: + db (0eh xor 00h) ;0 - and --> bic, invert + db 0 ;1 - eor + db (04h xor 02h)+0x80 ;2 - sub --> add, negate + db 0 ;3 - rsb + db (02h xor 04h)+0x80 ;4 - add --> sub, negate + db (06h xor 05h)+0x80 ;5 - adc --> sbc, negate + db (05h xor 06h)+0x80 ;6 - sbc --> adc, negate + db 0 ;7 - rsc + db 0 ;8 - tst + db 0 ;9 - teq + db (0bh xor 0ah)+0x80 ;a - cmp --> cmn, negate + db (0ah xor 0bh)+0x80 ;b - cmn --> cmp, negate + db 0 ;c - orr + db (0fh xor 0dh) ;d - mov --> mvn, invert + db (00h xor 0eh) ;e - bic --> and, invert + db (0dh xor 0fh) ;f - mvn --> mov, invert + +ARM_encode_immediate_with_opcode_swap: + call ARM_encode_immediate + jnc .done + mov eax,[arm_instruction] + shr eax,21 + and eax,0xf + mov al,[eax+ARM_opcode_swap_table] + test al,al + jz .fail + mov ecx,[immediate_value] + not ecx + test al,0x80 + jz .try + inc ecx + and eax,0xf + .try: + mov [immediate_value],ecx + shl eax,21 + xor [arm_instruction],eax + xor ebp,eax + call ARM_encode_immediate + jnc .done + .fail: + stc + .done: + ret + +ARM_encode_immediate: + mov eax,[immediate_value] + xor ecx,ecx + .try: + cmp eax,0ffh + jbe .immediate_ok + add ch,1 + rol eax,2 + cmp ch,010h + jb .try + stc + ret + .immediate_ok: + or eax,ecx + mov [immediate_value],eax + clc + ret + +THUMB_opcode_swap_table: + db (01h xor 00h) ;0 - and --> bic, invert + db (00h xor 01h) ;1 - bic --> and, invert + db (03h xor 02h) ;2 - mov --> mvn, invert, also orr --> orn, invert + db (02h xor 03h) ;3 - mvn --> mov, invert, also orn --> orr, invert + db 0 ;4 - eor, teq + db 0 ;5 - + db 0 ;6 - + db 0 ;7 - + db (0dh xor 08h)+0x80 ;8 - add --> sub, negate, also cmn --> cmp, negate + db 0 ;9 - + db (0bh xor 0ah)+0x80 ;a - adc --> sbc, negate + db (0ah xor 0bh)+0x80 ;b - sbc --> adc, negate + db 0 ;c - + db (08h xor 0dh)+0x80 ;d - sub --> add, negate, also cmp --> cmn, negate + db 0 ;e - rsb + db 0 ;f - + +THUMB_encode_immediate_with_opcode_swap: + call THUMB_encode_immediate + jnc .done + mov eax,[thumb32_instruction] + shr eax,21 + and eax,0xf + mov al,[eax+THUMB_opcode_swap_table] + test al,al + jz .fail + mov ecx,[immediate_value] + not ecx + test al,0x80 + jz .try + inc ecx + and eax,0xf + .try: + mov [immediate_value],ecx + shl eax,21 + xor [thumb32_instruction],eax + xor ebp,eax + call THUMB_encode_immediate + jnc .done + .fail: + stc + .done: + ret + +THUMB_encode_immediate: + mov eax,[immediate_value] + xor edx,edx + bsr ecx,eax + jz .immediate_ok + sub ecx,8 + jb .immediate_ok + mov edx,2 + shl edx,cl + dec edx + test eax,edx + jnz .check_special_combos + sub ecx,31 + neg ecx + mov edx,ecx + shl edx,7 + rol eax,cl + and eax,0x7f + jmp .immediate_ok + .check_special_combos: + mov ecx,eax + shr ecx,16 + cmp ax,cx + jnz .fail + mov edx,1 shl 8 + cmp ah,0 ;0X0X + jz .immediate_ok + mov edx,2 shl 8 + xchg ah,al + cmp ah,0 ;X0X0 + jz .immediate_ok + mov edx,3 shl 8 + movzx eax,al + cmp ch,cl ;XXXX + jz .immediate_ok + .fail: + stc + ret + .immediate_ok: + or eax,edx + mov [immediate_value],eax + clc + ret + +THUMB_check_12bit_immediate: + mov eax,[immediate_value] + mov ecx,eax + neg ecx + cmovns eax,ecx + test eax,not 0xfff + jnz .fail + ;check for fit into a modified immediate value + bsr ecx,eax + jz .fail + bsf edx,eax + sub ecx,edx + cmp ecx,8 + jb .fail + clc + ret + .fail: + stc + ret + +PREDEFINED_LABEL_PROCESSOR = 4 ;%p +PREDEFINED_LABEL_COPROCESSOR = 5 ;%c + +ARM_predefined_label: + or eax,eax + jz current_offset_label + cmp eax,1 + je counter_label + cmp eax,2 + je timestamp_label + cmp eax,3 + je org_origin_label + cmp eax,PREDEFINED_LABEL_PROCESSOR + je .processor_id + cmp eax,PREDEFINED_LABEL_COPROCESSOR + je .coprocessor_id + mov edx,invalid_value + jmp error_undefined + .processor_id: + mov eax,[cpu_capability_flags] + mov edx,[cpu_capability_flags2] + and eax,CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1) + and edx,CPU_CAPABILITY_DEFAULT shr 32 + jmp make_qword_label_value + .coprocessor_id: + mov eax,[copro_capability_flags] + and eax,COPRO_CAPABILITY_DEFAULT + jmp make_dword_label_value + +ARM_get_predefined_id: + cmp ecx,2 + ja find_label + inc esi + cmp cl,1 + je get_counter_id + lods byte [esi] + mov ebx,characters + xlat [ebx] + cmp al,'t' + je get_timestamp_id + cmp al,'p' + je .processor_id + cmp al,'c' + je .coprocessor_id + sub esi,2 + jmp find_label + .processor_id: + mov eax,PREDEFINED_LABEL_PROCESSOR + ret + .coprocessor_id: + mov eax,PREDEFINED_LABEL_COPROCESSOR + ret + +ARM_assemble_line: + test [code_type],CPU_ACTIVITY_UNKNOWN + jz assemble_line + jmp ARM_generic_mode_checks.default + +ARM_generic_mode_checks: + test [code_type],CPU_ACTIVITY_ARM64 + jnz .arm + test [code_type],CPU_ACTIVITY_ARM + jz .other + .arm: + test al,FLAG_FORCE_NARROW + jnz ERROR_narrow_instructions_are_not_encodable_in_arm_mode + ret + .other: + test [code_type],CPU_ACTIVITY_UNKNOWN + jnz .default + mov [thumb16_error],ERROR_instruction_not_16bit + mov [thumb32_error],ERROR_instruction_not_16bit + ret + .default: + mov [code_type],CPU_ACTIVITY_ARM + mov [cpu_capability_flags],CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1) + mov [cpu_capability_flags2],CPU_CAPABILITY_DEFAULT shr 32 + mov [copro_capability_flags],COPRO_CAPABILITY_DEFAULT + mov [it_control],IT_MODE_AUTO + mov [potential_IT_anchor],0 + mov [explicit_IT_state],0 + mov [current_IT_block],0 + jmp .arm + +ARM_check_shift_range: + mov eax,[immediate_value] + cmp eax,0 + jnz .shift_not_zero + ;force to LSL 0 + mov [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + and ebp,not (3 shl 5) + .shift_not_zero: + movzx ecx,[instruction_shift_op] + shl ecx,5 + or ebp,ecx + mov edx,0x1f00 ;lsl is 0 to 31 + cmp ecx,ARM_SHIFT_OPCODE_LSL shl 5 + je .check_range + mov edx,0x2001 ;lsr & asr are 1 to 32 + cmp ecx,ARM_SHIFT_OPCODE_LSR shl 5 + je .check_range + cmp ecx,ARM_SHIFT_OPCODE_ASR shl 5 + je .check_range + mov edx,0x1f01 ;ror is 1 to 31 + .check_range: + cmp eax,32 + ja .shift_out_of_range + cmp al,dl + jb .shift_out_of_range + cmp al,dh + ja .shift_out_of_range + and eax,0x1f + shl eax,7 + or ebp,eax + ret + .shift_out_of_range: + cmp edx,0x1f00 + mov ecx,ERROR_shift_value_out_of_range.0_31 + jz .defer_error + cmp edx,0x2001 + mov ecx,ERROR_shift_value_out_of_range.1_32 + jz .defer_error + cmp edx,0x1f01 + mov ecx,ERROR_shift_value_out_of_range.1_31 + jz .defer_error + ud2 + .defer_error: + call ARM_defer_error + ret + + align 4 +THUMB_UAL_s_table: + ;bit=1 instruction needs 's' modifier outside of IT block + ;bit=0 instruction never uses 's' modifier + ;everything after 0x4400 never uses 's' modifier + dd 0xffffffff ;0000-07ff lsl r,r,i5 + dd 0xffffffff ;0800-0fff lsr r,r,i5 + dd 0xffffffff ;1000-17ff asr r,r,i5 + dd 0xffffffff ;1800-1fff add r,r,r/sub r,r,r/add r,r,i3/sub r,r,i3 + dd 0xffffffff ;2000-27ff mov r,i8 + dd 0x00000000 ;2800-2fff cmp r,i8 + dd 0xffffffff ;3000-37ff add r,i8 + dd 0xffffffff ;3800-3fff sub r,i8 + dw 0xf2ff ;4000-43ff {and/eor/lsl/lsr/asr/adc/sbc/ror/tst/neg/cmp/cmn/orr/mul/bic/mvn} r,r + +THUMB_do_non_UAL_S_override: + ;in pre-UAL code a 'OP reg,...' and 'OPs reg,...' are the same and use the 'OPs' form + ;we can fake this by forcing the S version if the encoding is in range + cmp [thumb16_error],0 + jnz .16bit_okay + movzx eax,[thumb16_instruction] + shr eax,6 + test [code_type],CPU_ACTIVITY_THUMB_NON_UAL + jz .flag_set_override_done + cmp eax,0x4400 shr 6 + jae .flag_set_override_done + bt [THUMB_UAL_s_table],eax + jnc .flag_set_override_done + or [instruction_condition],FLAG_CONDITION_SET + ;every thumb32 equivalent instruction except MUL has the 's' in bit 20 + cmp eax,0x4340 shr 6 ;MUL? + jnz .do_thumb32_s_override + ;cannot be encoded in thumb32 + mov [thumb32_error],ERROR_instruction_not_16bit + jmp .flag_set_override_done + .do_thumb32_s_override: + or [thumb32_instruction],1 shl 20 + .flag_set_override_done: + ;now check the S flag + cmp eax,0x4400 shr 6 + jae .flag_must_be_unset + bt [THUMB_UAL_s_table],eax + jnc .flag_must_be_unset + test [instruction_condition],FLAG_CONDITION_SET + jnz .only_outside + ;only inside IT + or [thumb_flags_16],THUMB_FLAG_ONLY_INSIDE_IT + jmp .16bit_okay + .only_outside: + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + jmp .16bit_okay + .flag_must_be_unset: + test [instruction_condition],FLAG_CONDITION_SET + jz .16bit_okay + .16bit_unavailable: + mov [thumb16_error],ERROR_instruction_not_16bit + .16bit_okay: + ret + +THUMB_try_place_narrow_with_IT: + cmp [thumb16_error],ERROR_instruction_not_16bit + jz .unencodable + call THUMB_try_place_narrow_without_IT + jnc .done + test [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + jnz .fail + call THUMB_start_IT_block + .done: + ret + .unencodable: + mov ecx,ERROR_instruction_not_16bit + .fail: + stc + ret + +THUMB_try_place_wide_with_IT: + cmp [thumb32_error],ERROR_instruction_not_16bit + jz .unencodable + call THUMB_try_place_wide_without_IT + jnc .done + test [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + jnz .fail + call THUMB_start_IT_block + .done: + ret + .unencodable: + mov ecx,ERROR_instruction_not_16bit + .fail: + stc + ret + +THUMB_try_place_wide_without_IT: + cmp [thumb32_error],ERROR_instruction_not_16bit + jz .unencodable + mov ecx,thumb_flags_32 + jmp THUMB_try_place_without_IT + .unencodable: + mov ecx,ERROR_instruction_not_16bit + stc + ret + +THUMB_try_place_narrow_without_IT: + cmp [thumb16_error],ERROR_instruction_not_16bit + jz .unencodable + mov ecx,thumb_flags_16 + jmp THUMB_try_place_without_IT + .unencodable: + mov ecx,ERROR_instruction_not_16bit + stc + ret + +THUMB_try_place_without_IT: + ;ecx=flag check address + mov al,[instruction_condition] + and al,0xf0 + test byte[ecx],THUMB_FLAG_ONLY_INSIDE_IT + jnz .force_inside + test byte[ecx],THUMB_FLAG_NOT_INSIDE_IT + jnz .force_outside + ;decide based upon the condition + cmp al,0xf0 ;unconditional? + jae .success + cmp al,0xe0 + jb .force_inside + ;try inside with AL condition. We try to extend open IT blocks if possible + test byte[ecx],THUMB_FLAG_NOT_INSIDE_IT + jnz .success ;this can happen when an explicit IT block is used + call THUMB_extend_IT_block + clc ;always give success even if the extension failed + ret + .force_inside: + test byte[ecx],THUMB_FLAG_NOT_INSIDE_IT + jnz .fail ;this can happen when an explicit IT block is used + cmp [explicit_IT_state],0 + jnz .success + call THUMB_extend_IT_block + ret + .force_outside: + test [explicit_IT_state],2 + jnz .success + cmp [explicit_IT_state],0 + jnz .fail + cmp al,0xe0 ;AL condition? + jae .success + test byte[ecx],THUMB_FLAG_IS_BCC + jz .fail + .success: + mov [current_IT_block],0 ;since we are not extending the IT block we have to kill it + clc + ret + .fail: + mov ecx,ERROR_instruction_not_16bit + stc + ret + +THUMB_query_condition_pc: + mov ecx,edi + test [code_type],CPU_ACTIVITY_ARM + jnz .done + mov ah,[instruction_condition] + and ah,0xf0 + cmp ah,0xe0 + jae .done + push eax ecx + call THUMB_query_condition_match + pop ecx eax + setc dl + movzx edx,dl + lea ecx,[ecx+edx*2] ;adjust for IT block + .done: + ret + +THUMB_query_condition_match: + ;check to see if the current instruction would match or extend an existing IT block + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz .not_match + cmp [explicit_IT_state],0 + jnz .explicit + mov eax,[current_IT_block] + test eax,eax + jz .not_match + mov ch,[instruction_condition] + cmp ch,0xf0 + jae .not_match + mov cl,[eax] + mov edx,ecx + and ecx,0xe0e0 + cmp ch,cl + jnz .not_match + .okay: + clc + ret + .explicit: + mov cl,byte[explicit_IT_state] ;get currently specified condition + mov ch,[instruction_condition] + and cx,0xf0f0 + cmp ch,cl + jz .okay + .not_match: + stc + ret + +BKPT_force_condition_match: + ;used by BKPT + mov cl,[instruction_condition] + mov eax,[explicit_IT_state] + test eax,eax + jnz .explicit + mov eax,[current_IT_block] + test eax,eax + jz .done + mov al,[eax] + .explicit: + and al,0xf0 + and cl,0x0f + or al,cl + mov [instruction_condition],al + .done: + ret + +THUMB_check_condition: + mov al,[instruction_condition] + and al,0xf0 + cmp [explicit_IT_state],0 + jnz .explicit + .not_explicit: + cmp al,0xe0 ;AL condition? + jz .okay + test [thumb_flags_32],THUMB_FLAG_IS_BCC + jnz .okay + cmp al,0xf0 + jz .not_conditional + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + mov ecx,ERROR_requires_cpu_capability_arm_7m + jz .fail + .inside: + or [thumb_flags_16],THUMB_FLAG_ONLY_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_INSIDE_IT + .okay: + clc + ret + .not_conditional: + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + jmp .okay + .explicit: + mov edx,[explicit_IT_state] + test edx,2 + jnz .not_explicit + cmp al,0xf0 ;AL condition? + jz ERROR_instruction_not_conditional + test [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + jz .check_explicit_match + mov ecx,ERROR_instruction_must_be_last_in_IT_block + test edx,0xffffff00 ;must be no more conditions + jnz .fail + .check_explicit_match: + and dl,0xf0 + cmp al,dl + jz .inside + mov ecx,ERROR_condition_does_not_match_IT_specifier + .fail: + stc + ret + +THUMB_start_IT_block: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz .capability + mov al,[instruction_condition] + and eax,0xf0 + cmp al,0xf0 + jae .cannot_start + cmp al,0xe0 + jnz .make_new_IT_here + call THUMB_convert_anchor + jnc .okay + .make_new_IT_here: + mov [potential_IT_anchor],0 + or eax,0xbf08 + mov [current_IT_block],edi + mov [edi],ax + add edi,2 + .okay: + clc + ret + .cannot_start: + mov ecx,ERROR_instruction_not_conditional + stc + ret + .capability: + mov ecx,ERROR_requires_cpu_capability_arm_7m + stc + ret + +THUMB_convert_anchor: + test [it_control],IT_MODE_AUTO + jz .cannot_convert + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz .cannot_convert + mov al,[instruction_condition] + and eax,0xf0 + cmp al,0xf0 + jae .cannot_convert + cmp al,0xe0 + jnz .cannot_convert + mov cl,[IT_anchor_distance] + cmp cl,3 + ja .cannot_convert + mov eax,[potential_IT_anchor] + test eax,eax + jz .cannot_convert + mov dx,[anchor_instruction] + shl edx,16 + or edx,0xbfe0 + mov ch,0x10 + shr ch,cl + movzx ecx,ch + or edx,ecx + mov [current_IT_block],eax + mov [eax],edx + mov [potential_IT_anchor],0 + clc + ret + .cannot_convert: + stc + ret + +THUMB_extend_IT_block: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz .cannot_extend + mov eax,[current_IT_block] + test eax,eax + jz .cannot_extend + cmp [explicit_IT_state],0 + jnz .okay + mov ch,[instruction_condition] + cmp ch,0xf0 + jae .cannot_extend + mov cl,[eax] + mov edx,ecx + and ecx,0xe0e0 + cmp ch,cl + jnz .cannot_extend + bsf ecx,edx + test ecx,ecx + jz .cannot_extend + shr dh,4 + and dh,0x1 + shl dh,cl + btr edx,ecx + or dl,dh + dec ecx + bts edx,ecx + mov [eax],dl + .okay: + clc + ret + .cannot_extend: + mov [current_IT_block],0 + stc + ret + +ARM_post_process_simd_with_error: + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction_with_error + mov [thumb32_error],ecx + jmp THUMB_post_process + +ARM_post_process_simd_convert_table: + db 0x00 ;f0 ---> invalid + db 0x00 ;f1 ---> invalid + db 0xef ;f2 ---> ef + db 0xff ;f3 ---> ff + db 0xf9 ;f4 ---> f9 + db 0x00 ;f5 ---> invalid + db 0x00 ;f6 ---> invalid + db 0x00 ;f7 ---> invalid + db 0x00 ;f8 ---> invalid + db 0x00 ;f9 ---> invalid + db 0x00 ;fa ---> invalid + db 0x00 ;fb ---> invalid + db 0x00 ;fc ---> invalid + db 0x00 ;fd ---> invalid + db 0xfe ;fe ---> fe + db 0x00 ;ff ---> invalid + +ARM_post_process_simd: + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction + mov [thumb32_error],0 + mov eax,ebp + shr eax,24 + sub eax,0xf0 + jb .fatal_error + movzx eax,byte[eax+ARM_post_process_simd_convert_table] + test eax,eax + jz .fatal_error + shl eax,24 + and ebp,not 0xff000000 + or eax,ebp + mov [thumb32_instruction],eax + jmp THUMB_post_process + .fatal_error: + jmp ERROR_thumb_recode_error + +ARM_post_process_copro_with_error: + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction_with_error + jmp ARM_post_process_copro.thumb + +ARM_post_process_copro: + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + xor ecx,ecx + .thumb: + mov [thumb32_instruction],ebp + mov [thumb32_error],ecx + cmp ebp,0xf shl 28 ;is it a '2' version? + jae THUMB_post_process + and ebp,not (0xf shl 28) + or ebp,0xe shl 28 + mov [thumb32_instruction],ebp + jmp THUMB_post_process + +THUMB_post_process: + cmp [thumb16_error],0 + jz .forced_wide_done + cmp [thumb32_error],0 + jnz .forced_wide_done + mov ax,[passes_limit] + sub ax,[current_pass] + cmp ax,6 + ja .forced_wide_done + mov eax,[force_wide_flag] + mov cl,[eax-1] + and cl,FLAG_FORCE_AUTO_WIDE + shr cl,FLAG_BIT_FORCE_AUTO_WIDE - FLAG_BIT_FORCE_WIDE + or cl,FLAG_FORCE_AUTO_WIDE + or [eax-1],cl + .forced_wide_done: + call THUMB_do_non_UAL_S_override + call THUMB_check_condition + jc .fail + test [instruction_condition],FLAG_FORCE_NARROW + jz .narrow_not_forced + call THUMB_try_place_narrow_with_IT + jnc .store_narrow + jmp .fail + .narrow_not_forced: + test [instruction_condition],FLAG_FORCE_WIDE + jz .wide_not_forced + call THUMB_try_place_wide_with_IT + jnc .store_wide + jmp .fail + .wide_not_forced: + cmp [thumb16_error],0 + setz al + cmp [thumb32_error],0 + setz ah + xor al,ah + jnz .no_free_choice + test ah,ah + jnz .free_choice_without_error_copy + mov ecx,[thumb32_error] + cmp ecx,ERROR_instruction_not_16bit + jz .free_choice_without_error_copy + mov [thumb16_error],ecx + .free_choice_without_error_copy: + call THUMB_try_place_narrow_without_IT + jnc .store_narrow + call THUMB_convert_anchor + jc .not_converted + call THUMB_try_place_narrow_without_IT + jnc .store_narrow + .not_converted: + call THUMB_try_place_wide_without_IT + jnc .store_wide + call THUMB_try_place_narrow_with_IT + jnc .store_narrow + call THUMB_try_place_wide_with_IT + jnc .store_wide + cmp ecx,ERROR_instruction_not_16bit + jnz .fail + mov eax,[thumb32_error] + test eax,eax + cmovnz ecx,eax + jmp .fail + .no_free_choice: + test ah,ah + jz .not_prefer_wide + call THUMB_try_place_wide_with_IT + jnc .store_wide + jmp .fail + .not_prefer_wide: + call THUMB_try_place_narrow_with_IT + jnc .store_narrow + jmp .fail + .store_narrow: + mov ecx,[thumb16_error] + movzx ebp,[thumb16_instruction] + test ecx,ecx + jnz THUMB_store_instruction_16_with_error + jmp THUMB_store_instruction_16 + .store_wide: + mov ecx,[thumb32_error] + mov ebp,[thumb32_instruction] + test ecx,ecx + jnz THUMB_store_instruction_32_with_error + jmp THUMB_store_instruction_32 + .fail: +; jmp THUMB_store_instruction_16_with_error + +THUMB_store_instruction_16_with_error: + call ARM_defer_error + jmp THUMB_store_instruction_16.store +THUMB_store_instruction_16: + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + test eax,1 + mov ecx,ERROR_instruction_not_aligned + jnz THUMB_store_instruction_16_with_error + .store: + mov [edi],bp + mov ebp,2 + jmp THUMB_finalise_instruction + +THUMB_store_instruction_32_with_error: + call ARM_defer_error + jmp THUMB_store_instruction_32.store +THUMB_store_instruction_32: + mov eax,[addressing_space] + mov eax,[eax+0x00] + sub eax,edi + neg eax + test eax,1 + mov ecx,ERROR_instruction_not_aligned + jnz THUMB_store_instruction_32_with_error + .store: + ror ebp,16 ;swap the hword endian + mov [edi],ebp + mov ebp,4 + jmp THUMB_finalise_instruction + +THUMB_finalise_instruction: + mov al,[IT_anchor_distance] + add al,1 + sbb al,0 + mov [IT_anchor_distance],al + add edi,ebp + mov ecx,[explicit_IT_state] + btr [explicit_IT_state],1 + jc .explicit_beginning + shr [explicit_IT_state],8 + .explicit_beginning: + test ecx,ecx + jnz instruction_assembled + mov eax,[current_IT_block] + test eax,eax + jz .check_potential_IT_anchor + test [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + jnz .kill_implicit_IT_block + test byte[eax],1 ;end of condition? + jz instruction_assembled + .kill_implicit_IT_block: + mov [current_IT_block],0 + jmp instruction_assembled + .check_potential_IT_anchor: + cmp [instruction_condition],0xe0 + jb .kill_potential_anchor + cmp [instruction_condition],0xf0 + jae .kill_potential_anchor + cmp ebp,4 + jnz .check_potential_anchor_extension + cmp [thumb16_error],0 + jnz .check_potential_anchor_extension + test [instruction_condition],FLAG_CONDITION_SET + FLAG_FORCE_WIDE + jnz .check_potential_anchor_extension + lea eax,[edi-4] ;make a new anchor + mov cx,[thumb16_instruction] + mov [IT_anchor_distance],1 + mov [potential_IT_anchor],eax + mov [anchor_instruction],cx + jmp instruction_assembled + .check_potential_anchor_extension: + cmp [potential_IT_anchor],0 + jz instruction_assembled + cmp ebp,2 + jnz .check_potential_anchor_extension_32 + test [instruction_condition],FLAG_CONDITION_SET + jnz .kill_potential_anchor + .check_potential_anchor_extension_32: + test [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_ONLY_LAST_IT + THUMB_FLAG_IS_BCC + jnz .kill_potential_anchor + cmp [IT_anchor_distance],4 + jbe instruction_assembled ;anchor extention is okay + .kill_potential_anchor: + mov [potential_IT_anchor],0 + jmp instruction_assembled + +ARM_define_label: + cmp [explicit_IT_state],0 + jnz ERROR_label_inside_IT_block + mov [current_IT_block],0 + mov [potential_IT_anchor],0 + jmp define_label + +ARM_end_virtual: + call find_structure_data + jc .ret + sub ebx,0x18 + mov al,[ebx+2] + mov ecx,[ebx+4] + mov edx,[ebx+8] + mov ebp,[ebx+12] + mov [IT_anchor_distance],al + mov [potential_IT_anchor],ecx + mov [explicit_IT_state],edx + mov [current_IT_block],ebp + mov ax,[ebx+16] + mov [anchor_instruction],ax + call remove_structure_data + add ebx,0x18 + .ret: + ret + +ARM_fit_operator: + POP vdx + je calculate_not + cmp al,0D1h ;FIT? + je .calculate_fit + jmp vdx + .calculate_fit: + cmp word [edi+8],0 + jne invalid_expression + cmp byte [edi+12],0 + je .fit_ok + cmp [error_line],0 + jne .fit_ok + mov eax,[current_line] + mov [error_line],eax + mov [error],invalid_use_of_symbol + .fit_ok: + xor ebx,ebx + test [code_type],CPU_ACTIVITY_ARM64 + jnz .fit_mask_test64 + mov eax,[edi] + mov edx,[edi+4] + test edx,edx + jz .fit_test + cdq + cmp edx,[edi+4] + jnz .fit_done + .fit_test: + push [immediate_value] + mov ebp,ARM_encode_immediate + mov edx,THUMB_encode_immediate + test [code_type],CPU_ACTIVITY_ARM + cmovz ebp,edx + mov [immediate_value],eax + call vbp + setnc bl ;bit-0 = can fit normal + mov eax,1 shl CPU32_CAPABILITY_T2 + mov ecx,1 shl CPU32_CAPABILITY_7M + test [code_type],CPU_ACTIVITY_ARM + cmovz eax,ecx + test [cpu_capability_flags],eax + jz .movw_done + cmp [immediate_value],1 shl 16 + setb cl + shl cl,3 + or bl,cl ;bit-3 = can fit movw + .movw_done: + mov eax,[edi] + not eax + mov [immediate_value],eax + call vbp + setnc cl + shl cl,1 + or bl,cl ;bit-1 = can fit inverted + mov eax,[edi] + neg eax + mov [immediate_value],eax + call vbp + setnc cl + shl cl,2 + or bl,cl ;bit-2 = can fit negated + pop [immediate_value] + .fit_done: + mov [edi],ebx ;set low dword + mov dword[edi+4],0 ;set high dword + mov byte[edi+13],0 ;set sign + add edi,14h + jmp calculation_loop + .fit_mask_test64: + push [immediate_value] + push [immediate_value_high] + mov eax,[edi] + mov edx,[edi+4] + mov [immediate_value],eax + mov [immediate_value_high],edx + push ebx + call ARM64_encode_bitmask + pop ebx + setnc bl ;bit-0 = can fit in 64 bit mask + mov eax,[edi] + mov edx,[edi+4] + test edx,edx + jz .fit_mask_test32 + cdq + cmp edx,[edi+4] + jnz .fit_mask_done + .fit_mask_test32: + mov [immediate_value],eax + mov [immediate_value_high],eax + push ebx + call ARM64_encode_bitmask + pop ebx + setnc cl + shl cl,1 + or bl,cl ;bit-1 = can fit in 32 bit mask + .fit_mask_done: + pop [immediate_value_high] + pop [immediate_value] + jmp .fit_done + +ARM_processor_directives: + ;called during parsing + cmp bx,ARM_processor_directive-instruction_handler + jz .enable_cpu_selection_symbols + cmp bx,ARM_coprocessor_directive-instruction_handler + jnz .done + .enable_cpu_selection_symbols: + mov [decorator_symbols_allowed],1 + .done: + ret + +ARM_parse_processor_separators: + ;called during parsing + cmp al,'-' + je separator + cmp al,'+' + je separator + jmp not_a_separator + +ARM_check_operator: + ;called during parsing + cmp al,8Fh ;processor? + je .get_symbol + cmp al,8Eh ;coprocessor? + jne argument_parsed + .get_symbol: + mov [decorator_symbols_allowed],1 + inc esi + movzx ecx,byte [esi] + inc esi + push edi + call get_symbol + pop edi + mov [decorator_symbols_allowed],0 + lea esi,[esi-2] + jc argument_parsed + add esi,2 + stosw + jmp argument_parsed + +ARM_check_processor: + ;called during assembly + je .used + cmp al,8Fh + je .processor + cmp al,8Eh + je .coprocessor + ret + .used: + add esp,4 + __is_64 * 4 + jmp check_for_used + .processor: + add esp,4 + __is_64 * 4 + inc esi + lodsw + xchg ah,al + cmp ax,cpu_sel + jb ERROR_expecting_CPU_selection_symbol + cmp ax,cpu_sel + cpu_sel.size + jae ERROR_expecting_CPU_selection_symbol + sub ax,cpu_sel + mov ecx,[cpu_capability_flags] + mov ebx,[cpu_capability_flags2] + jmp .symbol_okay + .coprocessor: + add esp,4 + __is_64 * 4 + inc esi + lodsw + xchg ah,al + cmp ax,copro_sel + jb ERROR_expecting_COPRO_selection_symbol + cmp ax,copro_sel + copro_sel.size + jae ERROR_expecting_COPRO_selection_symbol + sub ax,copro_sel + mov ecx,[copro_capability_flags] + xor ebx,ebx + .symbol_okay: + cmp ax,32 + cmovae ecx,ebx + bt ecx,eax + jc return_true + jmp return_false + +;V1 + +ARM_rd_rn_shifter: + ;used by ADC, ADD, AND, BIC, EOR, ORR, RSB, RSC, SBC, SUB + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ; 0=reg,imm alternate for reg,reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ; 1=reg,byte,rot alternate for reg,reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ; 2=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ; 3=reg,reg,rrx alternate for reg,reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ; 4=reg,reg,shift imm alternate for reg,reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\ ; 5=reg,reg,shift reg alternate for reg,reg,reg,shift reg + <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\ ; 6=reg,reg,imm + <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ; 7=reg,reg,byte,rot + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\ ; 8=reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ; 9=reg,reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;10=reg,reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;11=reg,reg,reg,shift reg + movzx eax,al + mov ecx,eax + shl ecx,24 + or eax,ecx + cmp al,6 + jae .encode_instruction + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + or edx,ecx + mov [operand_registers],edx + .encode_shifter: + ;used by ADC, ADD, AND, BIC, EOR, ORR, RSB (NEG), RSC, SBC, SUB + ;used by MOV (LSL, LSR, ASR, ROR, RRX), MVN, CMN, CMP, TEQ, TST + add al,6 + .encode_instruction: + ;used by ADR, MOV reg,exp + cmp [operand_register0],0xf + jnz .pc_check_done + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + .pc_check_done: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_rd_rn_shifter + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + .encode: + ;used by CMNP, CMPP, TEQP, TSTP + cmp al,6 + jz .reg_reg_imm + cmp al,7 + jz .reg_reg_byte_rot + cmp al,8 + jz .reg_reg_reg + cmp al,9 + jz .reg_reg_reg_rrx + cmp al,10 + jz .reg_reg_reg_shift_imm + cmp al,11 + jz .reg_reg_reg_shift_reg + ud2 + .reg_reg_byte_rot: + cmp [immediate_value],0xff + ja .byte_out_of_range + test [immediate_value2],not (0xf shl 1) + jnz .rotation_out_of_range + mov eax,[immediate_value2] + shl eax,8-1 + or [immediate_value],eax + jmp .reg_reg_imm_make + .reg_reg_imm: + call ARM_encode_immediate_with_opcode_swap + jc .immediate_out_of_range + .reg_reg_imm_make: + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + or ebp,eax + bts ebp,25 + jmp ARM_store_instruction + .reg_reg_reg_shift_imm: + call ARM_check_shift_range + .reg_reg_reg: + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + or ebp,eax + jmp ARM_store_instruction + .reg_reg_reg_shift_reg: + movzx eax,[operand_register0] + cmp al,0xf + jz ERROR_r15_not_valid.all + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + cmp al,0xf + jz ERROR_r15_not_valid.all + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + cmp al,0xf + jz ERROR_r15_not_valid.all + or ebp,eax + movzx eax,[instruction_shift_op] + shl eax,5 + or ebp,eax + movzx eax,[operand_register3] + cmp al,0xf + jz ERROR_r15_not_valid.all + shl eax,8 + or ebp,eax + bts ebp,4 + jmp ARM_store_instruction + .reg_reg_reg_rrx: + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + or ebp,eax + or ebp,ARM_SHIFT_OPCODE_ROR shl 5 + jmp ARM_store_instruction + .immediate_out_of_range: + mov ecx,ERROR_immediate_cannot_be_encoded + jmp ARM_store_instruction_with_error + .byte_out_of_range: + mov ecx,ERROR_byte_value_out_of_range + jmp ARM_store_instruction_with_error + .rotation_out_of_range: + mov ecx,ERROR_rotation_value_out_of_range + jmp ARM_store_instruction_with_error + +ARM_rd_shifter: + ;used by MVN + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;1=reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ;2=reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ;3=reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;4=reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;5=reg,reg,shift reg + .encode: + cmp al,0 + jnz .do + mov ecx,[immediate_value] + cmp ecx,0xffff + ja .do + test ebp,1 shl 22 ;1=mvn + jnz .do + test [instruction_condition],FLAG_CONDITION_SET + jnz .do + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB + push eax ecx + call ARM_encode_immediate + pop [immediate_value] eax + jnc .do + and ebp,0xf shl 28 + or ebp,0x03000000 ;switch to movw + jmp ARM_rd_imm16.do ;do movw + .THUMB: + push eax [immediate_value] + call THUMB_encode_immediate + pop [immediate_value] eax + jnc .do + mov [thumb32_instruction],0xf2400000 ;switch to movw + jmp ARM_rd_imm16.do ;do movw + .do: + ;used by CPY + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + mov dh,0 + or edx,ecx + mov [operand_registers],edx + jmp ARM_rd_rn_shifter.encode_shifter + +ARM_rd_shifter_exp: + ;used by MOV + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;1=reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ;2=reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ;3=reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;4=reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\ ;5=reg,reg,shift reg + <TMPL_base_reg,TMPL_expression> ;6=reg,exp converted to add reg,reg,imm + cmp al,6 + jb ARM_rd_shifter.encode + xor ebp,(ARM_INSTRUCTION_OPCODE_MOV xor ARM_INSTRUCTION_OPCODE_ADD) shl 21 + xor [arm_instruction],(ARM_INSTRUCTION_OPCODE_MOV xor ARM_INSTRUCTION_OPCODE_ADD) shl 21 + xor [thumb32_instruction],(0x2 shl 21 + 0xf shl 16) xor (0x8 shl 21) + jmp ARM_rd_rn_shifter.encode_instruction + +ARM_rd_rn_shift: + ;used by LSL, LSR, ASR, ROR + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm alternate for reg,reg,imm + <TMPL_base_reg,TMPL_base_reg>,\ ;1=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\ ;2=reg,reg,imm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;3=reg,reg,reg + mov ecx,ebp + shr ecx,5 + and ecx,3 + mov [instruction_shift_op],cl + ;make the thumb32 opcode + test al,1 + jz .reg_reg_imm + ;for reg,reg,reg + shl ecx,21 + or ecx,0xfa00f000 + mov [thumb32_instruction],ecx + jmp .thumb32_done + .reg_reg_imm: + shl ecx,4 + or ecx,0xea4f0000 + mov [thumb32_instruction],ecx + .thumb32_done: + cmp al,2 + jae .registers_shifted + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + or edx,ecx + mov [operand_registers],edx + add al,2 + .registers_shifted: + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + mov dh,0 + or edx,ecx + mov [operand_registers],edx + add al,2 + jmp ARM_rd_rn_shifter.encode_shifter + +ARM_rd_shift: + ;used by RRX + call decode_template + TEMPLATE \ + <TMPL_base_reg>,\ ;0=reg alternate for reg,reg + <TMPL_base_reg,TMPL_base_reg> ;1=reg,reg + mov [instruction_shift_op],ARM_SHIFT_OPCODE_ROR + cmp al,1 + jae .registers_shifted + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + or edx,ecx + mov [operand_registers],edx + .registers_shifted: + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + mov dh,0 + or edx,ecx + mov [operand_registers],edx + mov al,3 + jmp ARM_rd_rn_shifter.encode_shifter + +ARM_rn_shifter: + ;used by CMN, CMP, TEQ, TST + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;1=reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ;2=reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ;3=reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;4=reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;5=reg,reg,shift reg + mov edx,[operand_registers] + shl edx,8 + mov [operand_registers],edx + jmp ARM_rd_rn_shifter.encode_shifter + +ARM_rn_shifter_26bit: + ;used by CMNP, CMPP, TEQP, TSTP + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;1=reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ;2=reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ;3=reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;4=reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;5=reg,reg,shift reg + test [code_type],CPU_ACTIVITY_ARM + jz ERROR_instruction_not_16bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_26BIT + jz ERROR_requires_cpu_capability_arm_26bit + mov edx,[operand_registers] + shl edx,8 + mov [operand_registers],edx + add al,6 + jmp ARM_rd_rn_shifter.encode + +ARM_rd_address2: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_rd_address + ;used by LDR, LDRB, STR, STRB, selectively: PLD, LDRT, LDRBT, STRT, STRBT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ; 1=rd,[rn],+-rm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\ ; 2=rd,[rn],+-rm,shift imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_rrx_op>,\ ; 3=rd,[rn],+-rm,rrx + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 4=rd,[rn],imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 5=rd,[rn,imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 6=rd,[rn,imm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ; 7=rd,[rn,+-rm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 8=rd,[rn,+-rm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\ ; 9=rd,[rn,+-rm,shift imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;10=rd,[rn,+-rm,shift imm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right>,\ ;11=rd,[rn,+-rm,rrx] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;12=rd,[rn,+-rm,rrx]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;13=rd,[imm] PC relative + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;14=rd,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;15=rd,[exp]! implicit reg from structure + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + ;check that rd!=15 unless LDR, STR + cmp [operand_size],4 + jnz .check_rd + ;check for LDRT + mov edx,[arm_instruction] + and edx,0xf shl 21 + cmp edx,1 shl 21 + jnz .process + .check_rd: + mov cl,[operand_register0] + cmp cl,15 + jz ERROR_r15_not_valid.first + .process: + cmp al,0 + jz .rd_q_rn_p + cmp al,1 + jz .rd_q_rn_p_PMrm + cmp al,2 + jz .rd_q_rn_p_PMrm_shift_imm + cmp al,3 + jz .rd_q_rn_p_PMrm_rrx + cmp al,4 + jz .rd_q_rn_p_imm + cmp al,5 + jz .rd_q_rn_imm_p + cmp al,6 + jz .rd_q_rn_imm_p! + cmp al,7 + jz .rd_q_rn_PMrm_p + cmp al,8 + jz .rd_q_rn_PMrm_p! + cmp al,9 + jz .rd_q_rn_PMrm_shift_imm_p + cmp al,10 + jz .rd_q_rn_PMrm_shift_imm_p! + cmp al,11 + jz .rd_q_rn_PMrm_rrx_p + cmp al,12 + jz .rd_q_rn_PMrm_rrx_p! + cmp al,13 + jz .rd_q_imm_p + cmp al,14 + jz .rd_q_exp_p + cmp al,15 + jz .rd_q_exp_p! + ud2 + .rd_q_rn_p_imm: + cmp [immediate_value],0 + jz .rd_q_rn_p + .rd_q_rn_p_imm.do: + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.post + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + jmp .rd_rn_imm + .rd_q_rn_imm_p!: + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.post + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + mov eax,[immediate_value] + test eax,eax + jz .rd_q_rn_imm_p + xor ebp,1 shl 21 + 1 shl 24 + jmp .rd_rn_imm + .rd_q_rn_p: + .rd_q_rn_imm_p: + xor ebp,1 shl 24 + .rd_rn_imm: + or ebp,1 shl 23 + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + cmp eax,0xfff + jg .immediate_offset_out_of_range + cmp eax,-0xfff + jl .immediate_offset_out_of_range + test eax,eax + jns .store_offset + neg eax + btr ebp,23 + .store_offset: + or ebp,eax + jmp ARM_store_instruction + .rd_q_rn_PMrm_p!: + mov [instruction_shift_op],0 + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + jmp .rd_q_rn_PMrm_shift_imm_p! + .rd_q_rn_p_PMrm: + mov [instruction_shift_op],0 + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + jmp .rd_q_rn_p_PMrm_shift_imm + .rd_q_rn_PMrm_p: + mov [instruction_shift_op],0 + jmp .rd_q_rn_PMrm_shift_imm_p + .rd_q_rn_PMrm_shift_imm_p!: + call ARM_check_shift_range + xor ebp,1 shl 21 + 1 shl 24 + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.post + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + jmp .check_rn_rm + .rd_q_rn_p_PMrm_shift_imm: + call ARM_check_shift_range + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.post + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + .check_rn_rm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jnz .rd_rn_PMrm_shift_imm + mov ax,word[operand_register1] + and ax,0x7f7f + cmp al,ah + jz ERROR_base_and_offset_must_differ_with_writeback + jmp .rd_rn_PMrm_shift_imm + .rd_q_rn_PMrm_shift_imm_p: + call ARM_check_shift_range + xor ebp,1 shl 24 + .rd_rn_PMrm_shift_imm: + or ebp,1 shl 23 + 1 shl 25 + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + test al,al + jns .store_reg + and eax,0xf + btr ebp,23 + .store_reg: + cmp eax,0xf + jz ERROR_r15_not_valid.third + or ebp,eax + jmp ARM_store_instruction + .rd_q_rn_PMrm_rrx_p!: + xor ebp,1 shl 21 + 1 shl 24 + 3 shl 5 + jmp .rd_q_rn_p_PMrm_rrx.do + .rd_q_rn_p_PMrm_rrx: + or ebp,3 shl 5 + .rd_q_rn_p_PMrm_rrx.do: + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.second + mov ax,word[operand_register0] + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jnz .rd_rn_PMrm_shift_imm + mov ax,word[operand_register1] + and ax,0x7f7f + cmp al,ah + jz ERROR_base_and_offset_must_differ_with_writeback + jmp .rd_rn_PMrm_shift_imm + .rd_q_rn_PMrm_rrx_p: + xor ebp,1 shl 24 + 3 shl 5 + jmp .rd_rn_PMrm_shift_imm + .rd_q_imm_p: + mov [operand_register1],0xf + mov eax,[addressing_space] + mov eax,[eax+0x00] + add eax,[immediate_value] + sub eax,edi + sub eax,8 + mov [immediate_value],eax + jmp .rd_q_rn_imm_p + .rd_q_exp_p: + jmp .rd_q_rn_imm_p + .rd_q_exp_p!: + jmp .rd_q_rn_imm_p! + .immediate_offset_out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0xfff + jmp ARM_store_instruction_with_error + +ARM_rd_address2_post: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_rd_address + ;used by LDRT, LDRBT, STRT, STRBT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ;1=rd,[rn],+-rm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\ ;2=rd,[rn],+-rm,shift imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_rrx_op>,\ ;3=rd,[rn],+-rm,rrx + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm> ;4=rd,[rn],imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + cmp [operand_register0],15 + jz ERROR_r15_not_valid.first + cmp al,0 + jz ARM_rd_address2.rd_q_rn_p_imm.do + cmp al,1 + jz ARM_rd_address2.rd_q_rn_p_PMrm + cmp al,2 + jz ARM_rd_address2.rd_q_rn_p_PMrm_shift_imm + cmp al,3 + jz ARM_rd_address2.rd_q_rn_p_PMrm_rrx + cmp al,4 + jz ARM_rd_address2.rd_q_rn_p_imm.do + ud2 + +ARM_rn_address4: + ;used by LDM, STM + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_reg_list>,\ ;0=rn,{..} + <TMPL_base_reg,TMPL_reg_list,TMPL_modifier_translate>,\ ;1=rn,{..}^ + <TMPL_base_reg!,TMPL_reg_list>,\ ;2=rn!,{..} + <TMPL_base_reg!,TMPL_reg_list,TMPL_modifier_translate> ;3=rn!,{..}^ + mov [operand_size],4 + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_rn_address4 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + test al,1 + jnz .do_multiple ;cannot change to ldr when using translate + .do: + mov ecx,[reg_list_bitmap] + dec ecx + and ecx,[reg_list_bitmap] + jz .do_single ;single registers use a different encoding + .do_multiple: + cmp al,0 + jz .rn_list + cmp al,1 + jz .rn_list_t + cmp al,2 + jz .rn!_list + cmp al,3 + jz .rn!_list_t + ud2 + .rn_list: + mov ecx,0 + jmp .make + .rn_list_t: + mov ecx,1 shl 22 + jmp .make + .rn!_list: + mov ecx,1 shl 21 + jmp .make + .rn!_list_t: + test [reg_list_bitmap],1 shl 15 ;if PC is not present then we can't use writeback + jz ERROR_register_writeback_not_allowed + mov ecx,1 shl 22 + 1 shl 21 + .make: + or ebp,ecx + or ebp,[reg_list_bitmap] + movzx ecx,[operand_register0] + bt ebp,21 + jnc .dest_okay + bt ebp,20 + jc .ldm_check + ;stm check + bt ebp,22 ;translate? + jnc .writeback_okay + bt ebp,21 ;writeback? + jc ERROR_register_writeback_not_allowed + .writeback_okay: + bsf edx,ebp + cmp edx,ecx + jz .dest_okay + .ldm_check: + bt ebp,ecx + jc ERROR_destination_register_not_allowed_in_list + .dest_okay: + cmp ecx,15 ;PC? + jz ERROR_r15_not_valid.first + shl ecx,16 + or ebp,ecx + jmp ARM_store_instruction + .do_single: + and eax,2 + shl eax,21-1 + or ebp,eax + bsf ecx,[reg_list_bitmap] + mov ch,[operand_register0] + mov [operand_registers],ecx + mov [operand_size],4 + mov ecx,ebp + and ecx,1 shl 24 + 1 shl 21 + ;IA,DA ; 0=rd,[rn] + ;IA!,DA! ; 4=rd,[rn],imm + ;IB,DB ; 5=rd,[rn,imm] + ;IB!,DB! ; 6=rd,[rn,imm]! + mov eax,0 ; 0=rd,[rn] + mov edx,4 ; 4=rd,[rn],imm + cmp ecx,0 shl 24 + 1 shl 21 + cmovz eax,edx + mov edx,5 ; 5=rd,[rn,imm] + cmp ecx,1 shl 24 + 0 shl 21 + cmovz eax,edx + mov edx,6 ; 6=rd,[rn,imm]! + cmp ecx,1 shl 24 + 1 shl 21 + cmovz eax,edx + mov ecx,eax + and ecx,4 + mov edx,ecx + neg edx + test ebp,1 shl 23 + cmovz ecx,edx + mov [immediate_value],ecx + movzx ecx,[instruction_condition] + and ecx,0xf0 + shl ecx,24 + and ebp,0x00100000 + lea ebp,[ebp+ecx+0x04000000] + jmp ARM_rd_address2.process + +ARM_address4: + ;used by PUSH, POP + call decode_template + TEMPLATE \ + <TMPL_reg_list> ;0={..} + mov [operand_size],4 + mov [operand_register0],13 ;sp + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_address4 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + mov al,2 ;2=rn!,{..} + jmp ARM_rn_address4.do + +ARM_target: + ;used by B, BL + call decode_template + TEMPLATE \ + <TMPL_address> ;0=imm PC relative + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_B_target + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + mov eax,[addressing_space] + mov eax,[eax+0x00] + add eax,[immediate_value] + sub eax,edi + sub eax,8 + test eax,3 + jnz .not_aligned + cmp eax,1 shl 25 + jge .jump_out_of_range + cmp eax,-(1 shl 25) + jl .jump_out_of_range + shr eax,2 + and eax,0x00ffffff + or ebp,eax + or ebp,1 shl 27 + 1 shl 25 + jmp ARM_store_instruction + .jump_out_of_range: + mov ecx,ERROR_relative_jump_out_of_range + jmp ARM_store_instruction_with_error + .not_aligned: + mov ecx,ERROR_relative_jump_not_aligned + jmp ARM_store_instruction_with_error + +ARM_immediate24: + ;used by SWI + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_immediate8 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + mov eax,[immediate_value] + cmp eax,0x00ffffff + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0xffffff + jmp ARM_store_instruction_with_error + +ARM_rd_target: + ;used by ADR + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_address> ;0=reg,imm + mov [operand_register1],0xf ;rn=pc + mov ecx,[addressing_space] + mov ecx,[ecx+0x00] + add ecx,[immediate_value] + sub ecx,edi + sub ecx,8 + test [code_type],CPU_ACTIVITY_ARM + jnz .offset_done + call THUMB_query_condition_pc ;adjust for THUMB + mov eax,[addressing_space] + sub ecx,[eax+0x00] + add ecx,4 + and ecx,not 3 + neg ecx + add ecx,[immediate_value] + cmp [value_undefined],0 + jz .offset_done + xor ecx,ecx + .offset_done: + mov [immediate_value],ecx + mov al,6 ;6=reg,reg,imm + jmp ARM_rd_rn_shifter.encode_instruction + +ARM_rd_rm: + ;used by NEG + call decode_template + TEMPLATE \ + <TMPL_base_reg>,\ ;0=reg + <TMPL_base_reg,TMPL_base_reg> ;1=reg,reg + cmp al,0 + jnz .registers_shifted + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + or edx,ecx + mov [operand_registers],edx + .registers_shifted: + mov al,0 ;reg,reg,imm + jmp ARM_rd_rn_shifter.encode_shifter + +;V2 + +ARM_copro_op1_crd_crn_crm_op2: + ;used by CDP, CDP2 + call decode_template + TEMPLATE \ + <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg>,\ ;0=copro,op1,crd,crn,crm + <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2> ;1=copro,op1,crd,crn,crm,op2 + test [code_type],CPU_ACTIVITY_ARM + jz .check_v7m + cmp ebp,0xf shl 28 ;CDP2? + jae .check_v5 + jmp .check_v2 + .check_v7m: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .version_check_okay + .check_v2: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2 + jz ERROR_requires_cpu_capability_arm_v2 + jmp .version_check_okay + .check_v5: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + .version_check_okay: + movzx eax,[operand_register0] ;cpnum + shl eax,8 + or ebp,eax + movzx eax,[copro_opcode1] ;op1 + shl eax,20 + or ebp,eax + movzx eax,[operand_register1] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;crm + or ebp,eax + movzx eax,[copro_opcode2] ;op2 + shl eax,5 + or ebp,eax + jmp ARM_post_process_copro + +ARM_copro_crd_address5: + ;used by LDC, LDCL, LDC2, LDC2L, STC, STCL, STC2, STC2L + call decode_template + TEMPLATE \ + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=copro,crd,[rn] + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=copro,crd,[rn],imm + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ;2=copro,crd,[rn],{imm} + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;3=copro,crd,[rn,imm] + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;4=copro,crd,[rn,imm]! + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;5=copro,crd,[imm] PC relative + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;6=copro,crd,[exp] implicit reg from structure + <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;7=copro,crd,[exp]! implicit reg from structure + test [code_type],CPU_ACTIVITY_ARM + jz .check_v7m + cmp ebp,0xf shl 28 ;LDC2/STC2? + jae .check_v5 + jmp .check_v2 + .check_v7m: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .version_check_okay + .check_v2: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2 + jz ERROR_requires_cpu_capability_arm_v2 + jmp .version_check_okay + .check_v5: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + .version_check_okay: + cmp al,0 + jz .copro_crd_q_rn_p + cmp al,1 + jz .copro_crd_q_rn_p_imm + cmp al,2 + jz .copro_crd_q_rn_p_option + cmp al,3 + jz .copro_crd_q_rn_imm_p + cmp al,4 + jz .copro_crd_q_rn_imm_p! + cmp al,5 + jz .copro_crd_q_imm_p + cmp al,6 + jz .copro_crd_q_exp_p + cmp al,7 + jz .copro_crd_q_exp_p! + ud2 + .copro_crd_q_rn_p_option: + cmp [immediate_value],0xff + ja .option_out_of_range + shl [immediate_value],2 + jmp .encode + .copro_crd_q_imm_p: + mov [operand_register2],0xf + call THUMB_query_condition_pc + mov eax,[addressing_space] + sub ecx,[eax+0x00] + and ecx,not 3 ;round down + neg ecx + add ecx,[immediate_value] + test [code_type],CPU_ACTIVITY_ARM + setnz al + movzx eax,al + shl eax,2 + add eax,4 ;offset=4 for THUMB and 8 for ARM + sub ecx,eax + mov [immediate_value],ecx + .copro_crd_q_rn_p: + .copro_crd_q_exp_p: + .copro_crd_q_rn_imm_p: + or ebp,1 shl 24 ;P bit + jmp .encode + .copro_crd_q_exp_p!: + .copro_crd_q_rn_imm_p!: + cmp [operand_register2],0xf + jz ERROR_r15_not_valid.third + or ebp,1 shl 24 ;P bit + .copro_crd_q_rn_p_imm: + cmp [immediate_value],0 + jz .copro_crd_q_rn_p + or ebp,1 shl 21 ;W bit + cmp [operand_register2],0xf + jz ERROR_r15_not_valid.third + .encode: + movzx eax,[operand_register0] ;cpnum + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + test eax,3 + jnz .out_of_range + sar eax,2 + mov ecx,1 shl 23 ;U bit + or ecx,ebp + mov edx,eax + neg edx + test eax,eax + cmovns ebp,ecx + cmovs eax,edx + cmp eax,0xff + ja .out_of_range + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0x3fc + jmp ARM_post_process_copro_with_error + .option_out_of_range: + mov ecx,ERROR_option_out_of_range + jmp ARM_post_process_copro_with_error + +ARM_copro_op1_rd_crn_crm_op2: + ;used by MCR, MCR2, MRC, MRC2 + call decode_template + TEMPLATE \ + <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg>,\ ;0=copro,op1,rd,crn,crm + <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2> ;1=copro,op1,rd,crn,crm,op2 + test [code_type],CPU_ACTIVITY_ARM + jz .check_v7m + cmp ebp,0xf shl 28 ;MCR2 or MRC2? + jae .check_v5 + jmp .check_v2 + .check_v7m: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .version_check_okay + .check_v2: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2 + jz ERROR_requires_cpu_capability_arm_v2 + jmp .version_check_okay + .check_v5: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + .version_check_okay: + movzx eax,[operand_register0] ;cpnum + shl eax,8 + or ebp,eax + movzx eax,[copro_opcode1] ;op1 + cmp eax,7 + ja .out_of_range + shl eax,21 + or ebp,eax + movzx eax,[operand_register1] ;rd + test ebp,1 shl 20 ;MCR? + jnz .rd_check_okay + cmp eax,15 + jz ERROR_r15_not_valid.third + .rd_check_okay: + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;crm + or ebp,eax + movzx eax,[copro_opcode2] ;op2 + shl eax,5 + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_opcode3_out_of_range + jmp ARM_post_process_copro_with_error + +ARM_rd_rm_rs_rn: + ;used by MLA, MLS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rd,rm,rs,rn + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm_rs_rn.7m + test ebp,1 shl 22 ;MLS? + jz .do + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + jmp .encode + .do: + ;used by MUL + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2 + jz ERROR_requires_cpu_capability_arm_v2 + .encode: + ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8 + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,8 + or ebp,eax + movzx eax,[operand_register3] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.fourth + shl eax,12 + or ebp,eax + ;version 6 and above relax the rd!=rm restriction + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jnz ARM_store_instruction + mov al,[operand_register0] ;rd + mov ah,[operand_register1] ;rm + cmp al,ah + jz ERROR_source_rm_and_dest_must_differ + jmp ARM_store_instruction + .THUMB_rd_rm_rs_rn.7m: + test [instruction_condition],FLAG_CONDITION_SET + jnz THUMB_post_process + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + jmp .THUMB_rd_rm_rs_rn.encode + .THUMB_rd_rm_rs_rn: + ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8 + mov [thumb32_error],ERROR_requires_cpu_capability_arm_t2 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz THUMB_post_process + .THUMB_rd_rm_rs_rn.encode: + mov cl,0xff + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rm + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rs + or ebp,eax + movzx eax,[operand_register3] ;rn + shl eax,12 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_rs: + ;used by MUL + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=rd,rm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=rd,rm,rs + mov [operand_register3],0 ;rn=0 + cmp al,0 + jnz .do + mov al,[operand_register0] + mov [operand_register2],al + .do: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_MUL_rd_rm_rs + jmp ARM_rd_rm_rs_rn.do + +;v2a + +ARM_rd_rm_q_rn_p: + ;used by SWP, SWPB + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right> ;0=rd,rm,[rn] + test [code_type],CPU_ACTIVITY_ARM + jz ERROR_instruction_not_16bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_A + jz ERROR_requires_cpu_capability_arm_v2a + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,16 + or ebp,eax + mov al,[operand_register0] ;rd + mov ah,[operand_register1] ;rm + mov cl,[operand_register2] ;rn + cmp cl,al + jz ERROR_memory_address_cannot_be_source_or_dest + cmp cl,ah + jz ERROR_memory_address_cannot_be_source_or_dest + jmp ARM_store_instruction + +;v3 + +ARM_rd_psr: + ;used by MRS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_sysm_reg>,\ ;0=rd,sysm + <TMPL_base_reg,TMPL_psr>,\ ;1=rd,psr + <TMPL_base_reg,TMPL_banked_reg> ;2=rd,banked_reg + cmp al,2 + jz .banked + cmp al,0 + jz .THUMB_sysm + movzx ecx,[operand_register1] ;PSR + mov edx,32 + cmp ecx,15 + cmovz ecx,edx + mov edx,33 + cmp ecx,31 + cmovz ecx,edx + cmp ecx,32 + jb ERROR_must_use_full_psr + and ecx,1 ;ecx = R bit + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_psr + .encode: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3 + jz ERROR_requires_cpu_capability_arm_v3 + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + shl ecx,22 + or ebp,ecx + jmp ARM_store_instruction + .ARM_sysm: + movzx ecx,[operand_register1] + test ecx,ecx ;APSR? + jnz ERROR_instruction_not_32bit + jmp .encode + .THUMB_sysm: + test [code_type],CPU_ACTIVITY_ARM + jnz .ARM_sysm + xor ecx,ecx + movzx edx,[operand_register1] + or [thumb32_instruction],edx + cmp edx,20 ;control is 6M + jz .THUMB_check_6M + cmp edx,17 ;17+ are 7M + jae .THUMB_check_7M + .THUMB_check_6M: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jz ERROR_requires_cpu_capability_arm_6m + jmp .THUMB_rd_psr.encode + .THUMB_check_7M: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .THUMB_rd_psr.encode + .THUMB_rd_psr: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + .THUMB_rd_psr.encode: + mov ebp,[thumb32_instruction] + mov [thumb32_error],ERROR_r13_r15_not_valid + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz THUMB_post_process + cmp eax,0xd + jz THUMB_post_process + shl eax,8 + or ebp,eax + shl ecx,20 + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .banked: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE + jz ERROR_requires_cpu_capability_arm_ve + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.second + movzx ebp,[operand_register1] + mov ecx,ebp + mov edx,ebp + and ebp,0x0f ;get m1 field + and ecx,0x10 ;get m field + and edx,0x20 ;get R field + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_banked + shl ebp,16 + shl ecx,8-4 + shl edx,22-5 + or ebp,ecx + or ebp,edx + or ebp,eax + or ebp,0x0100f200 + movzx eax,[instruction_condition] + and eax,0xf0 + shl eax,28-4 + or ebp,eax + jmp ARM_store_instruction + .THUMB_banked: + cmp eax,0xd + jz ERROR_r13_not_valid.second + shl ebp,8 + shl ecx,4-4 + shl edx,20-5 + shl eax,16 + or ebp,ecx + or ebp,edx + or ebp,eax + or ebp,0xf3e08020 + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_psr_value: + ;used by MSR + call decode_template + TEMPLATE \ + <TMPL_sysm_reg,TMPL_base_reg>,\ ;0=sysm,rn + <TMPL_psr,TMPL_base_reg>,\ ;1=psr,rn + <TMPL_psr,TMPL_imm>,\ ;2=psr,imm + <TMPL_banked_reg,TMPL_base_reg> ;3=banked_reg,rn + cmp al,3 + jz .banked + sub al,1 + jc .THUMB_sysm + movzx edx,[operand_register0] ;psr + mov ecx,0x09 ;CPSR_fc + cmp edx,32 ;CPSR? + cmovz edx,ecx + mov ecx,0x19 ;SPSR_fc + cmp edx,33 ;SPSR? + cmovz edx,ecx + mov ecx,0x0c ;APSR_nzcvqg + cmp edx,34 ;APSR? + cmovz edx,ecx + mov ecx,0x10 ;extract R bit + and ecx,edx + and edx,0xf + cmp al,1 + jz .psr_imm + .psr_rm: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_psr_rm + .encode: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3 + jz ERROR_requires_cpu_capability_arm_v3 + shl edx,16 + or ebp,edx + shl ecx,22-4 + or ebp,ecx + movzx eax,[operand_register1] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + jmp ARM_store_instruction + .psr_imm: + test [code_type],CPU_ACTIVITY_ARM + jz ERROR_instruction_not_16bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3 + jz ERROR_requires_cpu_capability_arm_v3 + shl edx,16 + or ebp,edx + shl ecx,22-4 + or ebp,ecx + or ebp,1 shl 25 + call ARM_encode_immediate + jc ERROR_immediate_cannot_be_encoded + or ebp,[immediate_value] + jmp ARM_store_instruction + .ARM_sysm: + xor ecx,ecx + movzx edx,[operand_register0] + test edx,edx ;APSR? + jnz ERROR_instruction_not_32bit + mov edx,0x0c ;APSR_nzcvqg + jmp .encode + .THUMB_sysm: + test [code_type],CPU_ACTIVITY_ARM + jnz .ARM_sysm + movzx ecx,[operand_register0] + or [thumb32_instruction],ecx + cmp ecx,20 ;control is 6M + jz .THUMB_check_6M + cmp ecx,17 ;17+ are 7M + jae .THUMB_check_7M + .THUMB_check_6M: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jz ERROR_requires_cpu_capability_arm_6m + xor ecx,ecx + mov edx,8 + jmp .THUMB_rd_psr.encode + .THUMB_check_7M: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + xor ecx,ecx + mov edx,8 + jmp .THUMB_rd_psr.encode + .THUMB_psr_rm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + .THUMB_rd_psr.encode: + mov ebp,[thumb32_instruction] + shl edx,8 + or ebp,edx + shl ecx,20-4 + or ebp,ecx + mov [thumb32_error],ERROR_r13_r15_not_valid + movzx eax,[operand_register1] ;rn + cmp eax,0xf + jz THUMB_post_process + cmp eax,0xd + jz THUMB_post_process + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .banked: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE + jz ERROR_requires_cpu_capability_arm_ve + movzx eax,[operand_register1] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.second + cmp eax,0xd + jz ERROR_r13_not_valid.second + movzx ebp,[operand_register0] + mov ecx,ebp + mov edx,ebp + and ebp,0x0f ;get m1 field + and ecx,0x10 ;get m field + and edx,0x20 ;get R field + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_banked + shl ebp,16 + shl ecx,8-4 + shl edx,22-5 + or ebp,ecx + or ebp,edx + or ebp,eax + or ebp,0x0120f200 + movzx eax,[instruction_condition] + and eax,0xf0 + shl eax,28-4 + or ebp,eax + jmp ARM_store_instruction + .THUMB_banked: + shl ebp,8 + shl ecx,4-4 + shl edx,20-5 + shl eax,16 + or ebp,ecx + or ebp,edx + or ebp,eax + or ebp,0xf3808020 + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rdlo_rdhi_rm_rs: + ;used by UMLAL, UMULL, SMLAL, SMULL, UMAAL + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rdlo,rdhi,rm,rs + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rdlo_rdhi_rn_rm.7m + mov edx,[arm_instruction] + and edx,0xf shl 21 + 0xf shl 4 + cmp edx,2 shl 21 + 9 shl 4 ;UMAAL? + jnz .check_M + ;check v6 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + jmp .encode + .check_M: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_M + jz ERROR_requires_cpu_capability_arm_m + .encode: + movzx eax,[operand_register0] ;rdlo + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rdhi + shl eax,16 + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.third + or ebp,eax + movzx eax,[operand_register3] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.fourth + shl eax,8 + or ebp,eax + mov ax,word[operand_registers+0] ;rdlo & rdhi + cmp al,ah + jz ERROR_destination_registers_must_differ + ;version 6 and above relax the rd!=rm restriction + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jnz ARM_store_instruction + mov cl,[operand_register2] ;rm + cmp cl,al + jz ERROR_source_rm_and_dest_must_differ + cmp cl,ah + jz ERROR_source_rm_and_dest_must_differ + jmp ARM_store_instruction + .THUMB_rdlo_rdhi_rn_rm.7m: + test [thumb32_instruction],0x60 ;UMAAL is T2 + jnz .THUMB_rdlo_rdhi_rn_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .THUMB_rdlo_rdhi_rn_rm.encode + .THUMB_rdlo_rdhi_rn_rm: + ;used by SMLALD, SMLALDX, SMLSLD, SMLSLDX, SMLALBB, SMLALBT, SMLALTB, SMLALTT + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + .THUMB_rdlo_rdhi_rn_rm.encode: + mov cl,0xff + call THUMB2_check_bad_regs + jc THUMB_post_process + mov [thumb32_error],ERROR_destination_registers_must_differ + mov ax,word[operand_registers+0] ;rdlo & rdhi + cmp al,ah + jz THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rdlo + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rdhi + shl eax,8 + or ebp,eax + movzx eax,[operand_register2] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;rm + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +;v4 + +ARM_rd_address3D: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_rd_address + ;used by STRD, LDRD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ; 1=rd,[rn],+-rm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 2=rd,[rn],imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 3=rd,[rn,imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 4=rd,[rn,imm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ; 5=rd,[rn,+-rm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 6=rd,[rn,+-rm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ; 7=rd,[imm] PC relative + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 8=rd,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 9=rd,[exp]! implicit reg from structure + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;10=rd,rd2,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ;11=rd,rd2,[rn],+-rm + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;12=rd,rd2,[rn],imm + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;13=rd,rd2,[rn,imm] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;14=rd,rd2,[rn,imm]! + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ;15=rd,rd2,[rn,+-rm] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;16=rd,rd2,[rn,+-rm]! + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;17=rd,rd2,[imm] PC relative + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;18=rd,rd2,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;19=rd,rd2,[exp]! implicit reg from structure + cmp al,10 + jb .dest_registers_defined + mov ecx,[operand_registers] + mov dl,cl + shr ecx,8 + dec cl + mov [operand_registers],ecx + cmp dl,cl + jnz ERROR_source_registers_must_be_consecutive + sub al,10 + .dest_registers_defined: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_P + jz ERROR_requires_cpu_capability_arm_p + mov cl,[operand_register0] + test cl,1 ;even register? + jnz ERROR_destination_register_must_be_even + cmp cl,14 + jz ERROR_r14_not_valid.first + jmp ARM_rd_address3.version_check_okay + +ARM_rd_address3: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_rd_address + ;used by LDRH, LDRSH, LDRSB, STRH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ;1=rd,[rn],+-rm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;2=rd,[rn],imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;3=rd,[rn,imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;4=rd,[rn,imm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ;5=rd,[rn,+-rm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;6=rd,[rn,+-rm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;7=rd,[imm] PC relative + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;8=rd,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;9=rd,[exp]! implicit reg from structure + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4 + jz ERROR_requires_cpu_capability_arm_v4 + .version_check_okay: + mov cl,[operand_register0] + cmp cl,15 + jz ERROR_r15_not_valid.first + cmp al,0 + jz .rd_q_rn_p + cmp al,1 + jz .rd_q_rn_p_PMrm + cmp al,2 + jz .rd_q_rn_p_imm + cmp al,3 + jz .rd_q_rn_imm_p + cmp al,4 + jz .rd_q_rn_imm_p! + cmp al,5 + jz .rd_q_rn_PMrm_p + cmp al,6 + jz .rd_q_rn_PMrm_p! + cmp al,7 + jz .rd_q_imm_p + cmp al,8 + jz .rd_q_exp_p + cmp al,9 + jz .rd_q_exp_p! + ud2 + .rd_q_imm_p: + mov [operand_register1],0xf ;rn=r15 + mov eax,[addressing_space] + mov eax,[eax+0x00] + add eax,[immediate_value] + sub eax,edi + sub eax,8 + mov [immediate_value],eax + .rd_q_exp_p: + .rd_q_rn_p: + .rd_q_rn_imm_p: + or ebp,0x2 shl 21 + test ebp,1 shl 21 ;W=1 if T specified + jnz .encode_imm + or ebp,0x8 shl 21 ;P + jmp .encode_imm + .rd_q_rn_p_imm: + cmp [immediate_value],0 + jz .rd_q_rn_p + or ebp,0x2 shl 21 + jmp .check_rn + .rd_q_exp_p!: + .rd_q_rn_imm_p!: + cmp [immediate_value],0 + jz .rd_q_rn_p + or ebp,0xb shl 21 + .check_rn: + mov ax,word[operand_register0] ;ah=rn, al=rd + cmp ah,0xf + jz ERROR_r15_not_valid.second + cmp [operand_size],8 ;LDRD or STRD? + setz cl + not cl + and al,cl + and ah,cl + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + .encode_imm: + or ebp,1 shl 23 + mov eax,[immediate_value] + test eax,eax + jns .positive_imm + and ebp,not (1 shl 23) + neg eax + .positive_imm: + cmp eax,0xff + ja .out_of_range + mov ecx,eax + and ecx,0xf shl 4 + and eax,0xf + shl ecx,4 + or eax,ecx + or ebp,eax + or ebp,1 shl 22 + .encode_rd_rn: + movzx eax,[operand_register0] ;rd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + jmp ARM_store_instruction + .rd_q_rn_PMrm_p: + or ebp,0x8 shl 21 + jmp .encode_reg + .rd_q_rn_PMrm_p!: + or ebp,0x9 shl 21 + .rd_q_rn_p_PMrm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jnz .base_offset_okay + mov ax,word[operand_register1] + and ax,0x7f7f + cmp al,ah + jz ERROR_base_and_offset_must_differ_with_writeback + .base_offset_okay: + mov al,[operand_register1] ;rn + cmp al,0xf + jz ERROR_r15_not_valid.second + cmp al,[operand_register0] ;rd + jz ERROR_base_and_dest_must_differ_with_writeback + cmp [operand_size],8 ;LDRD or STRD? + jnz .encode_reg + mov ah,[operand_register0] ;rd + and ax,0xfefe + cmp al,ah + jz ERROR_base_and_dest_must_differ_with_writeback + .encode_reg: + cmp [operand_size],8 ;LDRD or STRD? + jnz .encode_reg.do + test ebp,1 shl 20 ;STRD=0 + jz .encode_reg.do + mov ah,[operand_register0] ;rd + mov al,[operand_register2] ;rm + and ax,0x7e7e + cmp al,ah + jz ERROR_offset_and_dest_must_differ_with_LDRD + .encode_reg.do: + or ebp,1 shl 23 + movzx eax,[operand_register2] ;rm + test al,al + jns .store_reg + and eax,0xf + btr ebp,23 + .store_reg: + cmp eax,0xf + jz ERROR_r15_not_valid.third + or ebp,eax + jmp .encode_rd_rn + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0xff + jmp ARM_store_instruction_with_error + +;v4T + +THUMB2_check_bad_regs: + ;cl has the bitmap for registers to check + ;cl[3..0] check for reg[3..0] <> pc + ;cl[7..4] check for reg[3..0] <> sp + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz .sp_check_okay + and cl,0xf ;v8 instructions allow usage of SP in THUMB instructions + .sp_check_okay: + mov edx,[operand_registers] + test cl,0x01 shl 0 + jz .reg0_pc_okay + cmp dl,0xf + jz .bad_reg + .reg0_pc_okay: + test cl,0x10 shl 0 + jz .reg0_sp_okay + cmp dl,0xd + jz .bad_reg + .reg0_sp_okay: + shr cl,1 + test cl,0x01 + jz .reg1_pc_okay + cmp dh,0xf + jz .bad_reg + .reg1_pc_okay: + test cl,0x10 + jz .reg1_sp_okay + cmp dh,0xd + jz .bad_reg + .reg1_sp_okay: + shr cl,1 + shr edx,16 + test cl,0x01 + jz .reg2_pc_okay + cmp dl,0xf + jz .bad_reg + .reg2_pc_okay: + test cl,0x10 + jz .reg2_sp_okay + cmp dl,0xd + jz .bad_reg + .reg2_sp_okay: + shr cl,1 + test cl,0x01 + jz .reg3_pc_okay + cmp dh,0xf + jz .bad_reg + .reg3_pc_okay: + test cl,0x10 + jz .reg3_sp_okay + cmp dh,0xd + jz .bad_reg + .reg3_sp_okay: + clc + ret + .bad_reg: + and cl,0x11 + cmp cl,0x10 + mov [thumb32_error],ERROR_r15_not_valid + jb .fail + mov [thumb32_error],ERROR_r13_not_valid + jz .fail + mov [thumb32_error],ERROR_r13_r15_not_valid + .fail: + stc + ret + +THUMB_rd_rn_shifter: + mov edx,[arm_instruction] + and edx,0xf shl 21 + shr edx,21 + mov ah,dl + mov [can_swap_rm_rn],0 + cmp ah,ARM_INSTRUCTION_OPCODE_AND + jz THUMB_AND_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_EOR + jz THUMB_EOR_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_SUB + jz THUMB_SUB_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_RSB + jz THUMB_RSB_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_ADD + jz THUMB_ADD_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_ADC + jz THUMB_ADC_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_SBC + jz THUMB_SBC_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_RSC + jz THUMB_RSC_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_TST + jz THUMB_TST_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_TEQ + jz THUMB_TEQ_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_CMP + jz THUMB_CMP_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_CMN + jz THUMB_CMN_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_ORR + jz THUMB_ORR_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_MOV + jz THUMB_MOV_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_BIC + jz THUMB_BIC_rd_rn_shifter + cmp ah,ARM_INSTRUCTION_OPCODE_MVN + jz THUMB_MVN_rd_rn_shifter + ud2 + +THUMB_AND_rd_rn_shifter: + mov [can_swap_rm_rn],-1 + mov dx,THUMB_INSTRUCTION_OPCODE_AND + jmp THUMB_GEN_rd_rn_shifter + +THUMB_EOR_rd_rn_shifter: + mov [can_swap_rm_rn],-1 + mov dx,THUMB_INSTRUCTION_OPCODE_EOR + jmp THUMB_GEN_rd_rn_shifter + +THUMB_ADC_rd_rn_shifter: + mov [can_swap_rm_rn],-1 + mov dx,THUMB_INSTRUCTION_OPCODE_ADC + jmp THUMB_GEN_rd_rn_shifter + +THUMB_SBC_rd_rn_shifter: + mov dx,THUMB_INSTRUCTION_OPCODE_SBC + jmp THUMB_GEN_rd_rn_shifter + +THUMB_TST_rd_rn_shifter: + mov edx,[operand_registers] + mov dl,dh + mov [operand_registers],edx + mov dx,THUMB_INSTRUCTION_OPCODE_TST + jmp THUMB_GEN_rd_rn_shifter + +THUMB_CMN_rd_rn_shifter: + mov edx,[operand_registers] + movzx ecx,dh + shl ecx,16 + or [thumb32_instruction],ecx + mov cx,0x0800 + cmp dh,13 ;SP is okay here + cmove edx,ecx + mov dl,dh + mov word[operand_registers+0],dx + mov dx,THUMB_INSTRUCTION_OPCODE_CMN + jmp THUMB_GEN_rd_rn_shifter + +THUMB_ORR_rd_rn_shifter: + mov [can_swap_rm_rn],-1 + mov dx,THUMB_INSTRUCTION_OPCODE_ORR + jmp THUMB_GEN_rd_rn_shifter + +THUMB_BIC_rd_rn_shifter: + mov dx,THUMB_INSTRUCTION_OPCODE_BIC + jmp THUMB_GEN_rd_rn_shifter + +THUMB_MVN_rd_rn_shifter: + mov edx,[operand_registers] + mov dh,dl + mov [operand_registers],edx + mov dx,THUMB_INSTRUCTION_OPCODE_MVN + jmp THUMB_GEN_rd_rn_shifter + +THUMB_GEN_rd_rn_shifter: + cmp al,6 + jz .reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz .reg_reg_reg + cmp al,9 + jz .reg_reg_reg_rrx + cmp al,10 + jz .reg_reg_reg_shift_imm + cmp al,11 + jz .reg_reg_reg_shift_reg + ud2 + .reg_reg_reg: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_reg.32 + mov [thumb16_error],ERROR_dest_and_source_must_be_the_same + mov eax,[operand_registers] + test eax,0x080808 + jnz .register_swap_done + mov ecx,[force_wide_flag] + test byte[ecx-1],FLAG_FORCE_WIDE + jnz .register_swap_done + cmp [can_swap_rm_rn],-1 + jnz .register_swap_done + mov ecx,eax + shr ecx,16 + cmp cl,al + jnz .register_swap_done + xchg cl,ah + shl ecx,16 + and eax,not (0xff shl 16) + or eax,ecx + .register_swap_done: + cmp ah,al ;rd=rn? + jnz .reg_reg_reg.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + shr eax,8 + test ax,0x0808 + jnz .reg_reg_reg.32 + shl ah,3 + or al,ah + mov ah,0x40 + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_reg.32: + mov cl,0x77 + .reg_reg_reg.32.valid_regs_set: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + call THUMB2_check_bad_regs + jc THUMB_post_process + mov edx,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register1] + shl eax,16 + or edx,eax + movzx eax,[operand_register2] + or edx,eax + test [instruction_condition],FLAG_CONDITION_SET + setnz cl + movzx ecx,cl + shl ecx,20 + or edx,ecx + or edx,1 shl 27 + 1 shl 25 + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + .reg_reg_imm: + mov cl,0x33 + .reg_reg_imm.valid_regs_set: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + push ecx + call THUMB_encode_immediate_with_opcode_swap + pop ecx + mov [thumb32_error],ERROR_immediate_cannot_be_encoded + jc THUMB_post_process + .reg_reg_imm.encode: + call THUMB2_check_bad_regs + jc THUMB_post_process + mov edx,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register1] + shl eax,16 + or edx,eax + test [instruction_condition],FLAG_CONDITION_SET + setnz cl + movzx ecx,cl + shl ecx,20 + or edx,ecx + mov eax,[immediate_value] + mov ecx,eax + and ecx,7 shl 8 + shl ecx,12-8 + or edx,ecx + mov ecx,eax + and eax,0xff + and ecx,1 shl 11 + shl ecx,26-11 + or edx,eax + or edx,ecx + or edx,1 shl 28 + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + .reg_reg_reg_rrx: + mov cl,0x77 + .reg_reg_reg_rrx.valid_regs_set: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov [instruction_shift_op],ARM_SHIFT_OPCODE_ROR + jmp .reg_reg_reg_shift_imm.do + .reg_reg_reg_shift_imm: + mov cl,0x77 + .reg_reg_reg_shift_imm.valid_regs_set: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + push ecx + call ARM_check_shift_range + pop ecx + .reg_reg_reg_shift_imm.do: + call THUMB2_check_bad_regs + jc THUMB_post_process + mov edx,[thumb32_instruction] + movzx ecx,[instruction_shift_op] + mov eax,[immediate_value] + shl ecx,4 + or edx,ecx + mov ecx,eax + and eax,0x3 + and ecx,0x7 shl 2 + shl eax,6 + shl ecx,12-2 + or edx,eax + or edx,ecx + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register1] + shl eax,16 + or edx,eax + movzx eax,[operand_register2] + or edx,eax + test [instruction_condition],FLAG_CONDITION_SET + setnz cl + movzx ecx,cl + shl ecx,20 + or edx,ecx + or edx,1 shl 27 + 1 shl 25 + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + .reg_reg_reg_shift_reg: + jmp THUMB_post_process + +THUMB_CMP_rd_rn_shifter: + cmp al,6 + jz .reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz .reg_reg + cmp al,9 + jz .reg_transfer + cmp al,10 + jz .reg_transfer + cmp al,11 + jz THUMB_post_process + ud2 + .reg_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_imm.32 + mov eax,[operand_registers] + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov edx,[immediate_value] + cmp edx,0xff + ja .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp ah,7 + ja .reg_reg_imm.32 + mov al,dl + or ah,0x28 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_imm.32: + mov al,6 + .reg_transfer: + mov edx,[operand_registers] + mov dl,dh + mov word[operand_registers+0],dx + mov cl,0x02 + cmp al,6 + jz THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set + cmp al,8 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg.32.valid_regs_set + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx.valid_regs_set + cmp al,10 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm.valid_regs_set + ud2 + .reg_reg: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_transfer + mov edx,[operand_registers] + shr edx,8 + test dx,0x0808 + jnz .hreg1_hreg2 + mov dx,THUMB_INSTRUCTION_OPCODE_CMP + mov eax,[operand_registers] + shr eax,8 + shl ah,3 + or al,ah + mov ah,0x40 + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + mov al,6 + jmp .reg_transfer + .hreg1_hreg2: + mov al,dl + and al,0x8 + and dl,0x7 + shl al,4 + or al,dl + shl dh,3 + or al,dh + mov ah,0x45 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + mov al,6 + jmp .reg_transfer + +THUMB_RSB_rd_rn_shifter: + ;NEG + cmp al,6 + jz .reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg.32 + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp al,11 + jz THUMB_post_process + ud2 + .reg_reg_imm: + cmp [immediate_value],0 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov eax,[operand_registers] + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ax,0x0808 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_imm + shl ah,3 + or al,ah + mov ah,0x40 + mov dx,THUMB_INSTRUCTION_OPCODE_NEG + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_imm + +THUMB_TEQ_rd_rn_shifter: + cmp al,6 + jz THUMB_GEN_rd_rn_shifter.reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg.32 + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp al,11 + jz THUMB_post_process + ud2 + +THUMB_RSC_rd_rn_shifter: + jmp THUMB_post_process + +THUMB_SUB_rd_rn_shifter: + cmp al,6 + jz .reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz .reg_reg_reg + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz THUMB_ADD_rd_rn_shifter.reg_reg_reg.32 + cmp al,11 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_reg + ud2 + .reg_reg_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_imm.32 + mov edx,eax + mov eax,[operand_registers] + cmp ah,al ;rd=rn? + jnz .reg_reg_imm3 + cmp al,13 ;SP? + jz .sp_imm7 + shr edx,24 + jz .reg.imm8 + cmp [immediate_value],7 ;for small immediates honour two reg encoding + jbe .reg_reg_imm3 + .reg.imm8: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov ch,0x38 + mov edx,[immediate_value] + test edx,edx ;negative? + jns .reg_imm8_check_range + neg edx + mov ch,0x30 ;change to add reg,imm8 + .reg_imm8_check_range: + cmp edx,0xff + ja .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp al,7 + ja .reg_reg_imm.32 + mov al,dl + or ah,ch + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .reg_reg_imm3: + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_7 + mov edx,[immediate_value] + mov ch,0x1e + test edx,edx ;negative? + jns .reg_reg_imm3_check_range + neg edx + mov ch,0x1c ;change to add reg,reg,imm3 + .reg_reg_imm3_check_range: + cmp edx,7 + ja .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ax,0x0808 + jnz .reg_reg_imm.32 + shl ah,3 + or al,ah + mov ah,ch + shl edx,6 + or eax,edx + movzx eax,ax + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .sp_imm7: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x1fc + mov ecx,0xb080 + mov eax,[immediate_value] + test eax,eax ;negative? + jns .sp_imm7_check_range + neg eax + mov cl,0 ;change to add sp,imm7 + .sp_imm7_check_range: + cmp eax,0x7f*4 + ja .reg_reg_imm.32 + test eax,3 + jnz .reg_reg_imm.32 + shr eax,2 + or eax,ecx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_imm.32: + cmp word[operand_registers+0],0x0e0f ;sub pc,lr,imm? + jnz .reg_reg_imm.not_pc_lr + test [instruction_condition],FLAG_CONDITION_SET + jnz .subs_pc_lr + .reg_reg_imm.not_pc_lr: + mov ebp,[thumb32_instruction] + mov [thumb32_instruction],0xf2a00000 ;SUBW + call THUMB_check_12bit_immediate + jnc THUMB_rd_rn_imm12.encode + cmp [operand_register1],15 ;PC? + jz THUMB_rd_rn_imm12.encode + mov [thumb32_instruction],ebp + cmp [operand_register1],13 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov cl,0x03 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set + .subs_pc_lr: + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb32_error],ERROR_requires_cpu_capability_arm_t2 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz THUMB_post_process + mov [thumb32_error],ERROR_immediate_value_out_of_range.0_0xff + mov eax,[immediate_value] + cmp eax,0xff + ja THUMB_post_process + or eax,0xf3de8f00 + mov [thumb32_instruction],eax + mov [thumb32_error],0 + jmp THUMB_post_process + .reg_reg_reg: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_ADD_rd_rn_shifter.reg_reg_reg.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + mov eax,[operand_registers] + test eax,0x080808 + jnz THUMB_ADD_rd_rn_shifter.reg_reg_reg.32 + mov edx,eax + shr edx,16 + shl ah,3 + or al,ah + mov ah,0 + mov dh,0 + shl edx,6 + or eax,edx + or ah,0x1a + movzx eax,ax + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_ADD_rd_rn_shifter.reg_reg_reg.32 + +THUMB_ADD_rd_rn_shifter: + cmp al,6 + jz .reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz .reg_reg_reg + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz .reg_reg_reg.32 + cmp al,11 + jz THUMB_post_process + ud2 + .reg_reg_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_imm.32 + mov edx,eax + mov eax,[operand_registers] + cmp ax,13*0x100+13 ;SP,SP,imm? + jz .sp_imm7 + cmp ah,13 ;SP? + jz .rd_sp_imm8 + cmp ah,15 ;PC? + jz .rd_pc_imm8 + cmp ah,al ;rd=rn? + jnz .reg_reg_imm3 + shr edx,24 + jz .reg.imm8 + cmp [immediate_value],7 ;for small immediates honour two reg encoding + jbe .reg_reg_imm3 + .reg.imm8: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov ch,0x30 + mov edx,[immediate_value] + test edx,edx ;negative? + jns .reg_imm8_check_range + neg edx + mov ch,0x38 ;change to sub reg,imm8 + .reg_imm8_check_range: + cmp edx,0xff + ja .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp ah,7 + ja .reg_reg_imm.32 + mov al,dl + or ah,ch + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .reg_reg_imm3: + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_7 + mov edx,[immediate_value] + mov ch,0x1c + test edx,edx ;negative? + jns .reg_reg_imm3_check_range + neg edx + mov ch,0x1e ;change to sub reg,reg,imm3 + .reg_reg_imm3_check_range: + cmp edx,7 + ja .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ax,0x0808 + jnz .reg_reg_imm.32 + shl ah,3 + or al,ah + mov ah,ch + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .sp_imm7: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x1fc + mov ecx,0xb000 + mov eax,[immediate_value] + test eax,eax ;negative? + jns .sp_imm7_check_range + neg eax + mov cl,0x80 ;change to sub sp,imm7 + .sp_imm7_check_range: + cmp eax,0x7f*4 + ja .reg_reg_imm.32 + test eax,3 + jnz .reg_reg_imm.32 + shr eax,2 + or eax,ecx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .rd_sp_imm8: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc + mov edx,[immediate_value] + cmp edx,0xff*4 + ja .reg_reg_imm.32 + test edx,3 + jnz .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp al,7 + ja .reg_reg_imm.32 + mov ah,al + shr edx,2 + mov al,dl + or ah,0xa8 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_imm.32 + .rd_pc_imm8: + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc + mov edx,[immediate_value] + cmp edx,0xff*4 + ja .reg_reg_imm.32 + test edx,3 + jnz .reg_reg_imm.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp al,7 + ja .reg_reg_imm.32 + mov ah,al + shr edx,2 + mov al,dl + or ah,0xa0 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_imm.32: + mov ebp,[thumb32_instruction] + mov [thumb32_instruction],0xf2000000 ;ADDW + call THUMB_check_12bit_immediate + jnc THUMB_rd_rn_imm12.encode + cmp [operand_register1],15 ;PC? + jz THUMB_rd_rn_imm12.encode + mov [thumb32_instruction],ebp + cmp [operand_register1],13 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov cl,0x03 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set + .reg_reg_reg: + mov eax,[operand_registers] + mov edx,eax + shr edx,16 + cmp dl,al ;rd=rm? + jz .check_hregs + cmp ah,al ;rd=rn? + jne .reg1_reg2_reg3 + .check_hregs: + test eax,0x080808 + jnz .hreg1_hreg1_hreg2 + ;special case for 'add lreg,lreg' + ;if: + ;1. UAL + ;2. no S and not conditional + ;3. V6M + ;then use 'add hreg,hreg' version + test [code_type],CPU_ACTIVITY_THUMB_UAL + jz .reg1_reg2_reg3 ;encode the lreg version 'adds lreg,lreg,lreg' + test [instruction_condition],FLAG_CONDITION_SET + jnz .reg1_reg2_reg3 ;encode the lreg version 'adds lreg,lreg,lreg' + cmp [instruction_condition],0xe shl 4 + jb .reg1_reg2_reg3 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_6m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jnz .hreg1_hreg1_hreg2.do ;encode the hreg version in UAL without S + .reg1_reg2_reg3: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_reg.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test eax,0x080808 + jnz .reg_reg_reg.32 + shl ah,3 + or al,ah + mov ah,0 + mov dh,0 + shl edx,6 + or eax,edx + or ah,0x18 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp .reg_reg_reg.32 + .hreg1_hreg1_hreg2: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_reg.32 + .hreg1_hreg1_hreg2.do: + cmp ah,al ;rd=rn? + jz .swap_okay + xchg dl,ah + .swap_okay: + and ax,0x0807 + shl ah,4 + or al,ah + shl dl,3 + or al,dl + mov ah,0x44 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_reg.32: + cmp [operand_register1],13 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp [operand_register0],13 + jnz .shift_checked + mov [thumb32_error],ERROR_shift_type_must_be_LSL + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz THUMB_post_process + mov [thumb32_error],ERROR_shift_value_out_of_range.0_3 + cmp [immediate_value],3 + ja THUMB_post_process + .shift_checked: + mov cl,0x47 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm.valid_regs_set + +THUMB_MOV_rd_rn_shifter: + cmp al,6 + jz .reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz .reg_reg + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz .reg_reg_shift_imm + cmp al,11 + jz .reg_reg_shift_reg + ud2 + .reg_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov ah,[operand_register0] + mov edx,[immediate_value] + cmp edx,0xff + ja THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp ah,7 + ja THUMB_GEN_rd_rn_shifter.reg_reg_imm + mov al,dl + or ah,0x20 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_imm + .reg_reg: + ;special case for 'mov lreg,lreg' + ;if: + ;1. UAL + ;2. no S + ;3. V6T + ;then use 'cpy reg,reg' + mov al,[operand_register0] + mov ah,[operand_register2] + mov word[operand_registers+0],ax + test ax,0x0808 ;any high registers used? + jnz .hreg1_hreg2 + test [code_type],CPU_ACTIVITY_THUMB_UAL + jz .lreg1_lreg2 ;encode the lreg version 'adds reg,reg,0' + test [instruction_condition],FLAG_CONDITION_SET + jnz .lreg1_lreg2 ;encode the lreg version 'adds reg,reg,0' + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v6t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T + jnz .hreg1_hreg2 + .lreg1_lreg2: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg + shl ah,3 + or al,ah + mov ah,0x1c + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_reg.32 + .hreg1_hreg2: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg + .hreg1_hreg2.do: + mov dl,ah + mov ah,al + and ax,0x0807 + shl ah,4 + or al,ah + shl dl,3 + or al,dl + mov ah,0x46 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + cmp [operand_register0],0xf + jnz .T2 + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + .T2: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov cl,0x55 + call THUMB2_check_bad_regs + jnc .T2.do + test [instruction_condition],FLAG_CONDITION_SET + jnz THUMB_post_process + mov cl,0x11 ;mov rx,{sp|pc} is allowed + call THUMB2_check_bad_regs + jnc .T2.do + mov cl,0x45 ;mov sp,rx is allowed + call THUMB2_check_bad_regs + jc THUMB_post_process + .T2.do: + mov edx,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register2] + or edx,eax + test [instruction_condition],FLAG_CONDITION_SET + setnz cl + movzx ecx,cl + shl ecx,20 + or edx,ecx + or edx,1 shl 27 + 1 shl 25 + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + .reg_reg_shift_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_ROR + jnz .not_ror + cmp [immediate_value],0 + jnz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + mov [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + .not_ror: + call ARM_check_shift_range + movzx eax,[instruction_shift_op] + mov ecx,0 shl 11 + mov edx,1 shl 11 + cmp al,ARM_SHIFT_OPCODE_LSR + cmovz ecx,edx + mov edx,2 shl 11 + cmp al,ARM_SHIFT_OPCODE_ASR + cmovz ecx,edx + mov al,[operand_register0] + mov ah,[operand_register2] + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp al,7 + ja THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp ah,7 + ja THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + shl ah,3 + or al,ah + mov ah,ch + mov edx,[immediate_value] + and edx,0x1f + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + .reg_reg_shift_reg: + mov eax,[operand_registers] + mov ecx,eax + shr eax,8 + mov al,cl + mov [operand_registers],eax + movzx eax,[instruction_shift_op] + mov dx,THUMB_INSTRUCTION_OPCODE_LSL + mov cx,THUMB_INSTRUCTION_OPCODE_LSR + cmp al,ARM_SHIFT_OPCODE_LSR + cmovz dx,cx + mov cx,THUMB_INSTRUCTION_OPCODE_ASR + cmp al,ARM_SHIFT_OPCODE_ASR + cmovz dx,cx + mov cx,THUMB_INSTRUCTION_OPCODE_ROR + cmp al,ARM_SHIFT_OPCODE_ROR + cmovz dx,cx + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .reg_reg_shift_reg.32 + mov [thumb16_error],ERROR_dest_and_source_must_be_the_same + mov eax,[operand_registers] + cmp ah,al ;rd=rn? + jnz .reg_reg_shift_reg.32 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + shr eax,8 + cmp al,7 + ja .reg_reg_shift_reg.32 + cmp ah,7 + ja .reg_reg_shift_reg.32 + shl ah,3 + or al,ah + mov ah,0x40 + shl edx,6 + or eax,edx + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .reg_reg_shift_reg.32: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov edx,0xfa00f000 + movzx eax,[instruction_shift_op] + shl eax,21 + or edx,eax + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register1] + shl eax,16 + or edx,eax + movzx eax,[operand_register2] + or edx,eax + test [instruction_condition],FLAG_CONDITION_SET + setnz cl + movzx ecx,cl + shl ecx,20 + or edx,ecx + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMB_rd_rn_shifter_ORN: + ;used by ORN + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ; 0=reg,imm alternate for reg,reg,imm + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ; 1=reg,byte,rot alternate for reg,reg,byte,rot + <TMPL_base_reg,TMPL_base_reg>,\ ; 2=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ; 3=reg,reg,rrx alternate for reg,reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ; 4=reg,reg,shift imm alternate for reg,reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\ ; 5=reg,reg,shift reg alternate for reg,reg,reg,shift reg + <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\ ; 6=reg,reg,imm + <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ; 7=reg,reg,byte,rot + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\ ; 8=reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\ ; 9=reg,reg,reg,rrx + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;10=reg,reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;11=reg,reg,reg,shift reg + cmp al,6 + jae .encode_instruction + mov edx,[operand_registers] + movzx ecx,dl + shl edx,8 + or edx,ecx + mov [operand_registers],edx + add al,6 + .encode_instruction: + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + cmp al,6 + jz THUMB_GEN_rd_rn_shifter.reg_reg_imm + cmp al,7 + jz ERROR_byte_rotation_in_thumb + cmp al,8 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg.32 + cmp al,9 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx + cmp al,10 + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm + cmp al,11 + jz THUMB_post_process + ud2 + +THUMB_MUL_rd_rm_rs: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m + mov al,[operand_register0] + mov cl,[operand_register1] + mov ah,[operand_register2] + cmp al,cl + jz .encode_al_ah + xchg cl,ah + .encode_al_ah: + ;v6t allows rd=rs + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v6t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T + jnz .encode + cmp al,ah + jz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m + .encode: + mov [thumb16_error],ERROR_dest_and_source_must_be_the_same + cmp al,cl + jnz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ax,0x0808 + jnz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m + shl ah,3 + or al,ah + mov ah,0x40 + or eax,THUMB_INSTRUCTION_OPCODE_MUL shl 6 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m + +; Branch Length Condition matched? b.n cc b.n b.w cc b.w T16 is BCC T32 is BCC +; <0x7f al x x Plain x Plain n n +; <0x7ff al x x Plain x Plain n n +; <0xfffff al x x x x Plain x n +; <0xffffff al x x x x Plain x n +; <0x7f mi n Plain x Plain x y y +; <0x7ff mi n x New IT Plain x n y +; <0xfffff mi n x x Plain x x y +; <0xffffff mi n x x x New IT x n +; <0x7f mi y x Extend x Extend n n +; <0x7ff mi y x Extend x Extend n n +; <0xfffff mi y x x x Extend x n +; <0xffffff mi y x x x Extend x n + +THUMB_B_target: + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov ecx,[addressing_space] + mov ecx,[ecx+0x00] + add ecx,[immediate_value] + sub ecx,edi + sub ecx,4 + cmp [value_undefined],0 + jz .offset_okay + xor ecx,ecx + .offset_okay: + sar ecx,1 + jc .not_aligned + mov [thumb16_error],ERROR_relative_jump_out_of_range + mov [thumb32_error],ERROR_relative_jump_out_of_range + mov edx,[arm_instruction] + and edx,0xf shl 21 + cmp edx,8 shl 21 + jz .linked + mov al,4 + irp v,7,10,19,23 { ;Bcc.n, B.n, Bcc.w, B.w + cmp ecx,1 shl v + setl dl + cmp ecx,-(1 shl v) + setge dh + and dl,dh + sub al,dl + } ;al=branch distance 0-4 + cmp al,4 ;branch too far? + jae THUMB_post_process + mov ah,[instruction_condition] + and ah,0xf0 + cmp ah,0xe0 + jae .unconditional_16 + push eax ecx + call THUMB_query_condition_match + pop ecx eax + jnc .unconditional_16 + cmp al,2 + je .conditional_32 + cmp al,0 + je .conditional_16 + dec ecx ;adjust for IT block inclusion + cmp al,3 + je .unconditional_32 + inc ecx ;adjust for no IT block inclusion + cmp ecx,-(1 shl 10) ;can fit into narrow branch? + jle .conditional_32 + dec ecx ;adjust for IT block inclusion + ;set unconditional 16 + mov edx,ecx + and edx,0x7ff + or dh,0xe0 + mov [thumb16_instruction],dx + mov [thumb16_error],0 + inc ecx ;adjust for no IT block inclusion + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jnz .conditional_32 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + jmp .conditional_32 + .conditional_16: + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_IS_BCC + mov dl,cl + mov dh,ah + shr dh,4 + or dh,0xd0 + mov [thumb16_instruction],dx + mov [thumb16_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jnz .conditional_32 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + .conditional_32: + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_IS_BCC + xor edx,edx + mov dl,ah + shl edx,22-4 + ;imm11 + mov eax,ecx + and eax,0x7ff + or edx,eax + ;imm6 + mov eax,ecx + and eax,0x3f shl 11 + shl eax,16-11 + or edx,eax + ;j1 + mov eax,ecx + and eax,1 shl (11+6) + shr eax,11+6-13 + or edx,eax + ;j2 + mov eax,ecx + and eax,1 shl (11+6+1) + shr eax,11+6+1-11 + or edx,eax + ;s + mov eax,ecx + and eax,1 shl (11+6+1+1) + shl eax,26-(11+6+1+1) + or edx,eax + or edx,0xf0008000 + mov [thumb32_instruction],edx + mov [thumb32_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jnz THUMB_post_process + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + jmp THUMB_post_process + .unconditional_16: + cmp al,1 + ja .unconditional_32 + mov edx,ecx + and edx,0x7ff + or dh,0xe0 + mov [thumb16_instruction],dx + mov [thumb16_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jnz .unconditional_32 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + .unconditional_32: + mov edx,0xf0009000 + mov [thumb32_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jnz .encode_b_bl + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + .encode_b_bl: + ;imm11 + mov eax,ecx + and eax,0x7ff + or edx,eax + ;imm10 + mov eax,ecx + and eax,0x3ff shl 11 + shl eax,16-11 + or edx,eax + ;j2 + mov eax,ecx + and eax,1 shl (11+10) + shr eax,11+10-11 + or edx,eax + ;j1 + mov eax,ecx + and eax,1 shl (11+10+1) + shr eax,11+10+1-13 + or edx,eax + ;s + mov eax,ecx + and eax,1 shl (11+10+1+1) + shl eax,26-(11+10+1+1) + or edx,eax + ;fixup i1 and i2 + sar ecx,31 ;get the sign + not ecx + and ecx,1 shl 13 + 1 shl 11 + xor edx,ecx + mov [thumb32_instruction],edx + jmp THUMB_post_process + .linked: + mov ah,[instruction_condition] + and ah,0xf0 + cmp ah,0xe0 + jae .unconditional_linked + push eax ecx + call THUMB_query_condition_match + pop ecx eax + setc dl + movzx edx,dl + sub ecx,edx ;adjust for IT block + .unconditional_linked: + cmp ecx,1 shl 23 + jge THUMB_post_process ;use default error of out of range + cmp ecx,-(1 shl 23) + jl THUMB_post_process ;use default error of out of range + mov [thumb32_error],0 + mov edx,0xf000d000 + cmp ecx,1 shl 21 + setl al + cmp ecx,-(1 shl 21) + setge ah + and al,ah + jnz .check_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jnz .encode_b_bl + mov [thumb32_error],ERROR_requires_cpu_capability_arm_6m + jmp .encode_b_bl + .check_v4t: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jnz .encode_b_bl + mov [thumb32_error],ERROR_requires_cpu_capability_arm_v4t + jmp .encode_b_bl + .not_aligned: + mov [thumb16_error],ERROR_relative_jump_not_aligned + mov [thumb32_error],ERROR_relative_jump_not_aligned + jmp THUMB_post_process + +ARM_rm: + ;used by BX + call decode_template + TEMPLATE \ + <TMPL_base_reg> ;0=rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz ERROR_requires_cpu_capability_arm_v4t + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_rm + movzx eax,[operand_register0] + or ebp,eax + jmp ARM_store_instruction + +THUMB_rm: + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov al,[operand_register0] + shl al,3 + mov ah,0x47 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +THUMB_rn_address4: + ;used by LDM, STM + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .T2 + cmp [operand_register0],8 ;<r8 + jae .check_v4 + mov [thumb16_error],ERROR_instruction_not_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jnz .T2 + .check_v4: + mov [thumb16_error],ERROR_instruction_not_16bit + ;if LDM and reg is in set then must be rn,{..} + ;if STM then reg in set can only be first register + cmp [operand_register0],13 ;SP + jz .high_reg_okay + test [operand_register0],8 ;high reg? + jnz .T2 + .high_reg_okay: + test ebp,1 shl 20 ;1=LDM + jz .check_list_stm + movzx ecx,[operand_register0] + bt [reg_list_bitmap],ecx + jnc .check_rn!_list + test [code_type],CPU_ACTIVITY_THUMB_UAL + jz .check_rn!_list + cmp al,0 ;0=rn,{..} + jz .do_16 + jmp .T2 + .check_rn!_list: + cmp al,2 ;2=rn!,{..} + jz .do_16 + jmp .T2 + .check_list_stm: + cmp al,2 ;2=rn!,{..} + jnz .T2 + movzx ecx,[operand_register0] + bt [reg_list_bitmap],ecx + jnc .do_16 + bsf edx,[reg_list_bitmap] + cmp ecx,edx + jnz .T2 + .do_16: + cmp [operand_register0],13 ;SP + jz THUMB_address4 + mov edx,[arm_instruction] + and edx,0xf shl 21 + cmp edx,4 shl 21 ;IA version of LDM & STM? + mov [thumb16_error],ERROR_instruction_not_16bit + jnz .T2 + mov cl,[operand_register0] + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + cmp cl,7 + ja .T2 + mov edx,[reg_list_bitmap] + test edx,0xff00 + mov [thumb16_error],ERROR_high_base_registers_not_allowed_in_list + jnz .T2 + mov dh,cl + or dh,0xc0 + bt ebp,20 ;1=LDM, 0=STM + jnc .store + or dh,0x8 + .store: + mov [thumb16_instruction],dx + mov [thumb16_error],0 + bt ebp,20 ;1=LDM, 0=STM + jnc .T2 + mov edx,[reg_list_bitmap] + dec edx + and edx,[reg_list_bitmap] + jnz .T2 + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov edx,0xf8500b04 + mov eax,0xf8d00000 + bsr ecx,[reg_list_bitmap] + cmp cl,[operand_register0] + cmovz edx,eax + shl ecx,12 + or edx,ecx + movzx ecx,[operand_register0] + shl ecx,16 + or edx,ecx + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + .T2_2: + mov al,2 + .T2: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + ;only IA and DB are valid, bit24 <> bit23 + lea ecx,[ebp*2] + xor ecx,ebp + test ecx,1 shl 24 + mov [thumb32_error],ERROR_instruction_not_16bit + jz THUMB_post_process + cmp al,0 + jz .rn_list + cmp al,1 + jz .rn_list_t + cmp al,2 + jz .rn!_list + cmp al,3 + jz .rn!_list_t + ud2 + .rn!_list: + or [thumb32_instruction],1 shl 21 + movzx eax,[operand_register0] + bt [reg_list_bitmap],eax + mov [thumb32_error],ERROR_destination_register_not_allowed_in_list + jc THUMB_post_process + .rn_list: + mov eax,[reg_list_bitmap] + lea ecx,[eax-1] + and eax,ecx + jz .small_set + cmp [operand_register0],0xf + jz ERROR_r15_not_valid.first + test [reg_list_bitmap],1 shl 13 + jnz ERROR_sp_in_set + test ebp,1 shl 20 ;1=LDM, 0=STM + jnz .T2_LDM_checks + test [reg_list_bitmap],1 shl 15 + jnz ERROR_pc_in_set + jmp .encode + .T2_LDM_checks: + cmp [reg_list_bitmap],0xc000 + jae ERROR_invalid_set_with_lr_pc + test [reg_list_bitmap],1 shl 15 + jz .encode + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + .encode: + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,16 + or ebp,eax + or ebp,[reg_list_bitmap] + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .rn!_list_t: + .rn_list_t: + mov [thumb32_error],ERROR_instruction_not_16bit + jmp THUMB_post_process + .small_set: + ;convert to ldr/str for a register set of 1 + mov eax,[reg_list_bitmap] + mov ebp,[thumb32_instruction] + bsf eax,eax + mov ah,[operand_register0] + mov word[operand_registers+0],ax + ;IA = [reg] type 0 + ;IA! = [reg],4 type 1 + ;DB = [reg,-4] type 2 + ;DB! = [reg,-4]! type 3 + mov ecx,ebp + and ebp,1 shl 20 + or ebp,0xf8400000 ;LDR/STR + mov [thumb32_instruction],ebp + and ecx,1 shl 23 + 1 shl 21 + mov [immediate_value],0 + mov al,0 + cmp ecx,1 shl 23 + 0 shl 21 ;IA + jz THUMB2_rd_address.do + mov [immediate_value],4 + mov al,1 + cmp ecx,1 shl 23 + 1 shl 21 ;IA! + jz THUMB2_rd_address.do + mov [immediate_value],-4 + mov al,2 + cmp ecx,0 shl 23 + 0 shl 21 ;DB + jz THUMB2_rd_address.do + mov al,3 ;DB! + jmp THUMB2_rd_address.do + +THUMB_address4: + ;used by POP, PUSH + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz THUMB_rn_address4.T2_2 + mov edx,[arm_instruction] + and edx,0xf shl 21 + shr edx,21 + mov eax,[reg_list_bitmap] + bt ebp,20 ;1=POP, 0=PUSH + jc .pop + ;push + cmp dl,0x8 ;DB version of STM? + mov [thumb16_error],ERROR_instruction_not_16bit + jnz THUMB_rn_address4.T2_2 + test ax,not 0x40ff ;LR with STM + mov [thumb16_error],ERROR_high_base_registers_not_allowed_in_list.not_lr + jnz THUMB_rn_address4.T2_2 + mov ch,0xb4 + jmp .encode + .pop: + cmp dl,0x4 ;IA version of LDM? + mov [thumb16_error],ERROR_instruction_not_16bit + jnz THUMB_rn_address4.T2_2 + test ax,not 0x80ff ;PC with LDM + mov [thumb16_error],ERROR_high_base_registers_not_allowed_in_list.not_pc + jnz THUMB_rn_address4.T2_2 + mov ch,0xbc + test [reg_list_bitmap],1 shl 15 + jz .encode + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + .encode: + test ah,ah + setnz cl + or ch,cl + mov ah,ch + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_rn_address4.T2_2 + +THUMB_immediate8: + ;used by SWI + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz ERROR_requires_cpu_capability_arm_v4t + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov eax,[immediate_value] + cmp eax,0xff + ja THUMB_post_process + mov ah,0xdf + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +;v5 + +ARM_immediate16: + ;used by BKPT + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + call BKPT_force_condition_match + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_immediate8 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + mov eax,[immediate_value] + cmp eax,0x0000ffff + ja .out_of_range + mov ecx,eax + and eax,0xf + and ecx,0xfff0 + shl ecx,4 + or eax,ecx + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0xffff + jmp ARM_store_instruction_with_error + .THUMB_immediate8: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5T + jz ERROR_requires_cpu_capability_arm_v5t + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + mov eax,[immediate_value] + cmp eax,0xff + ja THUMB_post_process + mov ah,0xbe + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +ARM_Xtarget: + ;used by BLX + call decode_template + TEMPLATE \ + <TMPL_address>,\ ;0=imm PC relative + <TMPL_base_reg> ;1=rm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_Xtarget + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + cmp al,0 + jz .address + cmp al,1 + jz .rm + ud2 + .address: + mov eax,[addressing_space] + mov eax,[eax+0x00] + add eax,[immediate_value] + sub eax,edi + sub eax,8 + test eax,1 + jnz .not_aligned + cmp eax,1 shl 25 + jge .jump_out_of_range + cmp eax,-(1 shl 25) + jl .jump_out_of_range + shr eax,2 + setc cl + or cl,0xfa + and eax,0x00ffffff + or ebp,eax + shl ecx,24 + or ebp,ecx + jmp ARM_store_instruction + .jump_out_of_range: + mov ecx,ERROR_relative_jump_out_of_range + jmp ARM_store_instruction_with_error + .not_aligned: + mov ecx,ERROR_relative_jump_not_aligned + jmp ARM_store_instruction_with_error + .rm: + movzx eax,[operand_register0] + cmp eax,15 ;PC? + je ERROR_r15_not_valid + or ebp,eax + or ebp,0x012fff30 + jmp ARM_store_instruction + .THUMB_Xtarget: + cmp al,1 + jz .rm32 + mov [thumb32_error],ERROR_instruction_not_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jnz THUMB_post_process + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + call THUMB_query_condition_pc + mov eax,[addressing_space] + sub ecx,[eax+0x00] + btr ecx,1 + neg ecx + add ecx,[immediate_value] + sub ecx,4 + test ecx,3 + jnz .not_aligned32 + sar ecx,1 + mov [thumb32_error],ERROR_relative_jump_out_of_range + cmp ecx,1 shl 23 + jge THUMB_post_process + cmp ecx,-(1 shl 23) + jl THUMB_post_process + mov [thumb32_error],0 + mov edx,0xf000c000 + cmp ecx,1 shl 21 + setl al + cmp ecx,-(1 shl 21) + setge ah + and al,ah + jnz .check_x + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jnz THUMB_B_target.encode_b_bl + mov [thumb32_error],ERROR_requires_cpu_capability_arm_t2 + jmp THUMB_B_target.encode_b_bl + .check_x: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_X + jnz THUMB_B_target.encode_b_bl + mov [thumb32_error],ERROR_requires_cpu_capability_arm_x + jmp THUMB_B_target.encode_b_bl + .rm32: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v5t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5T + jz THUMB_post_process + movzx eax,[operand_register0] + cmp eax,15 ;PC? + je ERROR_r15_not_valid + shl eax,3 + or eax,0x4780 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + .not_aligned32: + mov [thumb32_error],ERROR_relative_jump_not_aligned + jmp THUMB_post_process + +ARM_nop: + ;used by NOP + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_nop + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_K + jnz ARM_store_instruction + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1 + jz ERROR_requires_cpu_capability_arm_v1 + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,24 + or ebp,0x01a00000 ;movcc r0,r0 + jmp ARM_store_instruction + .THUMB_nop: + mov [thumb16_instruction],0xbf00 ;nop.n + mov [thumb16_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jnz .32 + mov [thumb16_instruction],0x46C0 ;mov r8,r8 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jnz .32 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + .32: + mov [thumb32_instruction],0xf3af8000 ;nop.w + mov [thumb32_error],0 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jnz THUMB_post_process + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + jmp THUMB_post_process + +ARM_rd_rm_CLZ: + ;used by CLZ + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg> ;0=rd,rm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm_CLZ + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5 + jz ERROR_requires_cpu_capability_arm_v5 + movzx eax,[operand_register0] + cmp eax,15 ;PC? + je ERROR_r15_not_valid.first + movzx ecx,[operand_register1] + cmp ecx,15 ;PC? + je ERROR_r15_not_valid.second + shl eax,12 + or ebp,eax + or ebp,ecx + jmp ARM_store_instruction + .THUMB_rd_rm_CLZ: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov cl,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov edx,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + movzx eax,[operand_register1] + or edx,eax + shl eax,16 + or edx,eax + mov [thumb32_instruction],edx + mov [thumb32_error],0 + jmp THUMB_post_process + +;E + +ARM_rd_rm_rn: + ;used by QADD, QSUB, QDADD, QDSUB + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=rdm,rn alternate for rd,rm,rn + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=rd,rm,rn + cmp al,0 + jnz .registers_defined + mov ecx,[operand_registers] + shl ecx,8 + mov cl,ch + mov [operand_registers],ecx + .registers_defined: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm_rn + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_E + jz ERROR_requires_cpu_capability_arm_e + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.all + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,15 + jz ERROR_r15_not_valid.all + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.all + shl eax,16 + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_rm_rn: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rm + or ebp,eax + movzx eax,[operand_register2] ;rn + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_rs_rn_E: + ;used by SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rd,rm,rs,rn + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm_rn_ra + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_E + jz ERROR_requires_cpu_capability_arm_e + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,8 + or ebp,eax + movzx eax,[operand_register3] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.fourth + shl eax,12 + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_rm_rn_ra: + ;used by SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov cl,0xff + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rm + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rn + or ebp,eax + movzx eax,[operand_register3] ;ra + shl eax,12 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rdlo_rdhi_rm_rs_E: + ;used by SMLALBB, SMLALBT, SMLALTB, SMLALTT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rdlo,rdhi,rm,rs + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rdlo_rdhi_rm_rs.THUMB_rdlo_rdhi_rn_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_E + jz ERROR_requires_cpu_capability_arm_e + movzx eax,[operand_register0] ;rdlo + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rdhi + shl eax,16 + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.third + or ebp,eax + movzx eax,[operand_register3] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.fourth + shl eax,8 + or ebp,eax + mov al,[operand_register0] ;rdlo + mov ah,[operand_register1] ;rdhi + cmp al,ah + jz ERROR_destination_registers_must_differ + jmp ARM_store_instruction + +ARM_rd_rm_rs_E: + ;used by SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=rdm,rs + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=rd,rm,rs + cmp al,0 + jnz .registers_defined + mov ax,word[operand_registers+0] + mov word[operand_registers+1],ax + .registers_defined: + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rd_rm_rs_rn_E.THUMB_rd_rm_rn_ra + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_E + jz ERROR_requires_cpu_capability_arm_e + movzx eax,[operand_register0] ;rd + shl eax,16 + cmp eax,0xf + jz ERROR_r15_not_valid.first + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,8 + or ebp,eax + jmp ARM_store_instruction + +;P + +ARM_copro_op1_rd_rn_crm: + ;used by MCRR, MRRC, MCRR2, MRRC2 + call decode_template + TEMPLATE \ + <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_base_reg,TMPL_cpro_reg> ;0=copro,op1,rd,rn,crm + test [code_type],CPU_ACTIVITY_ARM + jz .check_v7m + cmp ebp,0xf shl 28 ;MCRR2 or MRRC2? + jae .check_v6 + jmp .check_p + .check_v7m: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + jmp .version_check_okay + .check_p: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_P + jz ERROR_requires_cpu_capability_arm_p + jmp .version_check_okay + .check_v6: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + .version_check_okay: + movzx eax,[operand_register0] ;cpnum + shl eax,8 + or ebp,eax + movzx eax,[copro_opcode1] ;op1 + cmp eax,15 + ja .out_of_range + shl eax,4 + or ebp,eax + movzx eax,[operand_register1] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.third + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.fourth + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;crm + or ebp,eax + test ebp,1 shl 20 ;MRRC? + jz ARM_post_process_copro + movzx eax,word[operand_register1] ;rd,rn + cmp al,ah + jz ERROR_destination_registers_must_differ + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_opcode4_out_of_range + jmp ARM_post_process_copro_with_error + +ARM_address2: + ;used by PLD, PLDW, PLI + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_address + call decode_template + TEMPLATE \ + <TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=[rn] + <TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=[rn,imm] + <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ;2=[rn,+-rm] + <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\ ;3=[rn,+-rm,shift imm] + <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right>,\ ;4=[rn,+-rm,rrx] + <TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;5=[imm] PC relative + <TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;6=[exp] implicit reg from structure + test ebp,1 shl 24 ;PLI=1? + jnz .check_v7 + test ebp,1 shl 22 ;PLDW=0? + jnz .check_P + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_MP + jz ERROR_requires_cpu_capability_arm_mp + cmp [operand_register0],0xf + jz ERROR_r15_not_valid.base + jmp .version_check_okay + .check_v7: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz ERROR_requires_cpu_capability_arm_v7 + jmp .version_check_okay + .check_P: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_P + jz ERROR_requires_cpu_capability_arm_p + .version_check_okay: + or ebp,0xf shl 28 + mov ecx,[operand_registers] + shl ecx,8 + mov cl,0xf + mov [operand_registers],ecx + cmp al,0 + jz ARM_rd_address2.rd_q_rn_p + cmp al,1 + jz ARM_rd_address2.rd_q_rn_imm_p + cmp al,2 + jz ARM_rd_address2.rd_q_rn_PMrm_p + cmp al,3 + jz ARM_rd_address2.rd_q_rn_PMrm_shift_imm_p + cmp al,4 + jz ARM_rd_address2.rd_q_rn_PMrm_rrx_p + cmp al,5 + jz ARM_rd_address2.rd_q_imm_p + cmp al,6 + jz ARM_rd_address2.rd_q_exp_p + ud2 + +THUMB2_address: + ;used by PLD + call decode_template + TEMPLATE \ + <TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0(0)=[rn] + <TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1(2)=[rn,imm] + <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ;2(4)=[rn,rm] + <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm2,TMPL_bracket_right>,\ ;3(5)=[rn,rm,shift imm] + <TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;4(6)=[imm] PC relative + <TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5(7)=[exp] implicit reg from structure + mov ecx,[operand_registers] + shl ecx,8 + or ecx,8 ;fake rd as r8 to prevent 16bit code generation + mov [operand_registers],ecx + add al,2 + cmp al,3 + ja THUMB2_rd_address.do + dec al + shr al,1 + add al,al + jmp THUMB2_rd_address.do + +;J + +ARM_rm_J: + ;used by BXJ + call decode_template + TEMPLATE \ + <TMPL_base_reg> ;0=rm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rm_j + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_J + jz ERROR_requires_cpu_capability_arm_j + movzx eax,[operand_register0] + or ebp,eax + cmp eax,15 ;PC? + jz ERROR_r15_not_valid + jmp ARM_store_instruction + .THUMB_rm_j: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov ecx,0x11 + call THUMB2_check_bad_regs + jc THUMB_post_process + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +;v6 + +ARM_mode: + ;used by CPS + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm5 + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_mode + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + mov eax,[immediate_value] + cmp eax,31 + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0x1f + jmp ARM_store_instruction_with_error + .THUMB_mode: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + mov ebp,[thumb32_instruction] + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f + mov eax,[immediate_value] + cmp eax,31 + ja THUMB_post_process + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_iflags_mode: + ;used by CPSID, CPSIE + call decode_template + TEMPLATE \ + <TMPL_iflags>,\ ;0=flags + <TMPL_iflags,TMPL_imm> ;1=flags,mode + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_iflags_mode + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + cmp al,1 + jnz .iflags + .iflags_mode: + mov eax,[immediate_value] + cmp eax,31 + ja .out_of_range + or ebp,1 shl 17 + or ebp,eax + .iflags: + movzx eax,[operand_register0] + shl eax,6 + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0x1f + jmp ARM_store_instruction_with_error + .THUMB_iflags_mode: + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + mov [thumb16_error],ERROR_requires_cpu_capability_arm_7m + cmp al,1 + jz .T2 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_ALIGN + jnz .THUMB_iflags_aif + mov [thumb16_error],ERROR_requires_cpu_capability_arm_align + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jnz .THUMB_iflags_if + mov [thumb16_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jnz .THUMB_iflags_i + mov [thumb16_error],ERROR_requires_cpu_capability_arm_6m + jmp .T2 + .THUMB_iflags_i: + test [operand_register0],101b + jnz .T2 + .THUMB_iflags_if: + test [operand_register0],100b + jnz .T2 + .THUMB_iflags_aif: + mov ebp,0xb660 + mov ecx,[arm_instruction] + and ecx,1 shl 18 + shr ecx,18-4 + or ebp,ecx + movzx ecx,[operand_register0] + or ebp,ecx + mov [thumb16_instruction],bp + mov [thumb16_error],0 + .T2: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_t2 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz THUMB_post_process + mov ebp,[thumb32_instruction] + cmp al,1 + jnz .T2_iflags + .T2_iflags_mode: + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f + mov eax,[immediate_value] + cmp eax,31 + ja THUMB_post_process + or ebp,1 shl 8 + or ebp,eax + .T2_iflags: + movzx eax,[operand_register0] + shl eax,5 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_CPY: + ;used by CPY + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg> ;0=reg,reg + test [code_type],CPU_ACTIVITY_ARM + mov al,2 + jnz ARM_rd_shifter.do + .THUMB_rd_rm: + mov ax,word[operand_registers+0] + mov [operand_register2],ah + test ax,0x0808 ;any high registers used? + jnz THUMB_MOV_rd_rn_shifter.hreg1_hreg2 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v6t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T + jz THUMB_GEN_rd_rn_shifter.reg_reg_reg + jmp THUMB_MOV_rd_rn_shifter.hreg1_hreg2.do + +ARM_rd_q_rn_p: + ;used by LDREX, LDREXB, LDREXH, LDA, LDAB, LDAH, LDAEX, LDAEXB, LDAEXH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=reg,[reg] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=reg,[reg,imm] (for T2 ldrex only) + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=reg,[exp] (for T2 ldrex only) + test ebp,1 shl 8 + jnz .not_v8 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + test [code_type],CPU_ACTIVITY_ARM + jnz .version_okay + cmp [immediate_value],0 + jnz ERROR_immediate_cannot_be_encoded + jmp .THUMB_version_okay + .not_v8: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_q_rn_imm_p + test ebp,3 shl 21 ;LDREXB or LDREXH? + jz .check_v6 + .check_v6k: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_K + jz ERROR_requires_cpu_capability_arm_k + jmp .version_okay + .check_v6: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + .version_okay: + cmp [immediate_value],0 + jnz ERROR_immediate_cannot_be_encoded + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_q_rn_imm_p: + test ebp,3 shl 21 ;LDREXB or LDREXH (!=0)? + jz .check_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_SYNC + jz ERROR_requires_cpu_capability_arm_sync + cmp [immediate_value],0 + jnz ERROR_immediate_cannot_be_encoded + jmp .THUMB_version_okay + .check_7m: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + .THUMB_version_okay: + mov cl,0x13 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x3fc + test eax,not (0xff shl 2) + jnz THUMB_post_process + shr eax,2 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rn_rm_shift_imm: + ;used by PKHBT, PKHTB + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;1=reg,reg,shift imm alternate for reg,reg,reg,shift imm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\ ;2=reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm> ;3=reg,reg,reg,shift imm + cmp al,2 + jae .do + mov cx,word[operand_register0] + mov word[operand_register1],cx + .do: + test ebp,1 shl 6 + jz .lsl + test al,1 + jnz .asr + ;convert to pkhbt rd,rm,rn + .convert: + mov ax,word[operand_register1] + xchg ah,al + mov word[operand_register1],ax + and ebp,not (1 shl 6) + and [thumb32_instruction],not (1 shl 5) + jmp .encode + .asr: + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_ASR + jnz ERROR_shift_type_must_be_ASR + mov eax,[immediate_value] + sub eax,1 + jc .convert + cmp eax,31 + ja ERROR_shift_value_out_of_range.1_32 + inc eax + and eax,0x1f + mov [immediate_value],eax + jmp .encode + .lsl: + cmp al,0 + jz .encode + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz ERROR_shift_type_must_be_LSL + mov eax,[immediate_value] + cmp eax,31 + ja ERROR_shift_value_out_of_range.0_31 + .encode: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_encode + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + mov eax,[immediate_value] + shl eax,7 + or ebp,eax + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,15 + jz ERROR_r15_not_valid.third + or ebp,eax + jmp ARM_store_instruction + .THUMB_encode: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + mov eax,[immediate_value] + mov ecx,eax + and eax,0x3 + and ecx,0x7 shl 2 + shl eax,6 + shl ecx,12-2 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rn_rm: + ;used by QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, + ; SADD16, SADD8, SADDSUBX, SSUB16, SSUB8, SSUBADDX, + ; SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX, + ; UADD16, UADD8, UADDSUBX, USUB16, USUB8, USUBADDX, + ; UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX, + ; UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX, + ; SEL + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=reg,reg,reg + cmp al,0 + jnz .encode + mov ax,word[operand_register0] + mov word[operand_register1],ax + .encode: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rn_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,15 + jz ERROR_r15_not_valid.third + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_rn_rm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_REV: + ;used by RBIT, REV, REV16, REVSH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg> ;0=rd,rm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm + mov ecx,ebp + and ecx,1 shl 22 + 1 shl 7 + cmp ecx,1 shl 22 + 0 shl 7 ;RBIT? + jnz .check_v6 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + jmp .ARM_version_okay + .check_v6: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + .ARM_version_okay: + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,15 + jz ERROR_r15_not_valid.second + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_rm: + mov ecx,ebp + and ecx,1 shl 22 + 1 shl 7 + cmp ecx,1 shl 22 + 0 shl 7 ;RBIT? + jz .T2 + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v6t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T + jz .T2 + mov eax,ebp + and eax,1 shl 7 + and ebp,1 shl 22 + shr eax,7-6 + shr ebp,22-7 + or ebp,eax + movzx eax,[operand_register0] ;rd + cmp eax,7 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + ja .T2 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,7 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + ja .T2 + shl eax,3 + or ebp,eax + or ebp,0xba00 + mov [thumb16_instruction],bp + mov [thumb16_error],0 + .T2: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov cl,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rm + or ebp,eax + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rn: + ;used by RFE + call decode_template + TEMPLATE \ + <TMPL_base_reg>,\ ;0=rn + <TMPL_base_reg!> ;1=rn! + movzx eax,al + shl eax,21 + movzx ecx,[operand_register0] ;rn + cmp ecx,15 + jz ERROR_r15_not_valid.first + shl ecx,16 + or ecx,eax ;define W bit + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rn + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + or ebp,ecx + jmp ARM_store_instruction + .THUMB_rn: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov eax,ebp + shl eax,1 + xor eax,ebp + test eax,1 shl 24 ;bit23 <> bit24? + jz ERROR_instruction_not_16bit + mov ebp,[thumb32_instruction] + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_endian: + ;used by SETEND + call decode_template + TEMPLATE \ + <TMPL_endian> ;0=endian + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_endian + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx eax,[operand_register0] ;endian + shl eax,9 + or ebp,eax + jmp ARM_store_instruction + .THUMB_endian: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_ALIGN + jz ERROR_requires_cpu_capability_arm_align + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + movzx ebp,[operand_register0] ;endian + shl ebp,3 + or ebp,0xb650 + mov [thumb16_instruction],bp + mov [thumb16_error],0 + jmp THUMB_post_process + +ARM_rd_rm_rs_rn_D: + ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8 + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rd,rm,rs,rn + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + jmp ARM_rd_rm_rs_rn.encode + +ARM_rdlo_rdhi_rm_rs_D: + ;used by SMLALD, SMLALDX, SMLSLD, SMLSLDX + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rdlo,rdhi,rm,rs + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rdlo_rdhi_rm_rs.THUMB_rdlo_rdhi_rn_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + jmp ARM_rdlo_rdhi_rm_rs.encode + +ARM_rd_rm_rs_M: + ;used by SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUSDX + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=rd,rm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=rd,rm,rs + mov [operand_register3],0 ;rn=0 + cmp al,0 + jnz .do + mov ax,word[operand_registers+0] + mov word[operand_registers+1],ax + .do: + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + jmp ARM_rd_rm_rs_rn.encode + +ARM_reg_mode: + ;used by SRS + call decode_template + TEMPLATE \ + <TMPL_imm>,\ ;0=mode + <TMPL_imm,TMPL_modifier_exclaim>,\ ;1=mode ! + <TMPL_base_reg,TMPL_imm>,\ ;2=sp,mode + <TMPL_base_reg!,TMPL_imm> ;3=sp!,mode + cmp al,2 + jb .set_mode + cmp [operand_register0],13 ;SP? + jnz ERROR_register_out_of_range.must_be_sp + .set_mode: + mov ecx,eax + and ecx,1 + shl ecx,21 + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_reg_mode + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + or ebp,ecx ;define W bit + mov eax,[immediate_value] + cmp eax,31 + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0x1f + jmp ARM_store_instruction_with_error + .THUMB_reg_mode: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov eax,ebp + shl eax,1 + xor eax,ebp + test eax,1 shl 24 ;bit23 <> bit24? + jz ERROR_instruction_not_16bit + mov ebp,[thumb32_instruction] + or ebp,ecx + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f + mov eax,[immediate_value] + cmp eax,31 + ja THUMB_post_process + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_imm_rm_shift: + ;used by SSAT, USAT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg>,\ ;0=reg,imm,reg + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg,TMPL_shift_op,TMPL_imm2> ;1=reg,imm,reg,shift imm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_imm_rm_shift + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx ecx,[operand_register0] ;rd + cmp ecx,15 + jz ERROR_r15_not_valid.first + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + cmp ecx,15 + jz ERROR_r15_not_valid.third + or ebp,ecx + mov ecx,[immediate_value] + test ebp,1 shl 22 ;USAT=1? + setz dl + movzx edx,dl + sub ecx,edx + cmp ecx,31 + ja .immediate_value_out_of_range + shl ecx,16 + or ebp,ecx + cmp al,1 ;reg,imm,reg,shift imm? + jnz ARM_store_instruction + mov dl,[instruction_shift_op] + cmp dl,ARM_SHIFT_OPCODE_LSL + jz .lsl + cmp dl,ARM_SHIFT_OPCODE_ASR + jnz ERROR_shift_type_must_be_LSL_or_ASR + mov ecx,ERROR_shift_value_out_of_range.1_32 + mov edx,[immediate_value2] + test edx,edx + jz .lsl + cmp edx,32 + ja ARM_store_instruction_with_error + and edx,0x1f + shl edx,7 + or ebp,edx + or ebp,1 shl 6 + jmp ARM_store_instruction + .lsl: + mov ecx,ERROR_shift_value_out_of_range.0_31 + mov edx,[immediate_value2] + cmp edx,31 + ja ARM_store_instruction_with_error + shl edx,7 + or ebp,edx + jmp ARM_store_instruction + .immediate_value_out_of_range: + test ebp,1 shl 22 ;USAT=1? + mov ecx,ERROR_immediate_value_out_of_range.1_32 + mov edx,ERROR_immediate_value_out_of_range.0_31 + cmovnz ecx,edx + jmp ARM_store_instruction_with_error + .THUMB_rd_imm_rm_shift: + mov ebp,[thumb32_instruction] + mov cl,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + movzx ecx,[operand_register0] ;rd + shl ecx,8 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + shl ecx,16 + or ebp,ecx + mov ecx,ERROR_immediate_value_out_of_range.1_32 + mov edx,ERROR_immediate_value_out_of_range.0_31 + test ebp,1 shl 23 ;USAT=1? + cmovnz ecx,edx + mov [thumb32_error],ecx + mov ecx,[immediate_value] + setz dl + movzx edx,dl + sub ecx,edx + cmp ecx,31 + ja THUMB_post_process + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + cmp al,1 ;reg,imm,reg,shift imm? + jnz THUMB_post_process + mov dl,[instruction_shift_op] + cmp dl,ARM_SHIFT_OPCODE_LSL + jz .THUMB_lsl + cmp dl,ARM_SHIFT_OPCODE_ASR + jnz ERROR_shift_type_must_be_LSL_or_ASR + mov [thumb32_error],ERROR_shift_value_out_of_range.1_31 + mov edx,[immediate_value2] + test edx,edx + jz .THUMB_encode_shift + cmp edx,31 + ja THUMB_post_process + or ebp,1 shl 21 + .THUMB_encode_shift: + mov eax,edx + and eax,3 + and edx,7 shl 2 + shl eax,6 + shl edx,12-2 + or ebp,eax + or ebp,edx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .THUMB_lsl: + mov [thumb32_error],ERROR_shift_value_out_of_range.0_31 + mov edx,[immediate_value2] + cmp edx,31 + ja THUMB_post_process + jmp .THUMB_encode_shift + +ARM_rd_imm_rm: + ;used by SSAT16, USAT16 + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg> ;0=reg,imm,reg + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_imm_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx ecx,[operand_register0] ;rd + cmp ecx,15 + jz ERROR_r15_not_valid.first + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + cmp ecx,15 + jz ERROR_r15_not_valid.third + or ebp,ecx + mov ecx,[immediate_value] + test ebp,1 shl 22 ;USAT16=1? + setz dl + movzx edx,dl + sub ecx,edx + cmp ecx,15 + ja .immediate_value_out_of_range + shl ecx,16 + or ebp,ecx + jmp ARM_store_instruction + .immediate_value_out_of_range: + test ebp,1 shl 22 ;USAT16=1? + mov ecx,ERROR_immediate_value_out_of_range.1_16 + mov edx,ERROR_immediate_value_out_of_range.0_15 + cmovnz ecx,edx + jmp ARM_store_instruction_with_error + .THUMB_rd_imm_rm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov ebp,[thumb32_instruction] + mov cl,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + movzx ecx,[operand_register0] ;rd + shl ecx,8 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + shl ecx,16 + or ebp,ecx + mov ecx,ERROR_immediate_value_out_of_range.1_16 + mov edx,ERROR_immediate_value_out_of_range.0_15 + test ebp,1 shl 23 ;USAT16=1? + cmovnz ecx,edx + mov [thumb32_error],ecx + mov ecx,[immediate_value] + setz dl + movzx edx,dl + sub ecx,edx + cmp ecx,15 + ja THUMB_post_process + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_q_rn_p_STREX: + ;used by STREX, STREXB, STREXH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,rm,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=rd,rm,[rn,imm] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=rd,rm,[exp] + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_rd_rm_q_rn_p_STREX + mov ecx,ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz ARM_store_instruction_with_error + test ebp,3 shl 21 ;STREXB or STREXH? + jz .check_v6 + .check_v6k: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_K + jz ERROR_requires_cpu_capability_arm_k + jmp .version_okay + .check_v6: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + .version_okay: + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,16 + or ebp,eax + mov al,[operand_register0] ;rd + mov ah,[operand_register1] ;rm + mov cl,[operand_register2] ;rn + cmp al,cl + jz ERROR_dest_cannot_be_source_or_memory_address + cmp al,ah + jz ERROR_dest_cannot_be_source_or_memory_address + jmp ARM_store_instruction + +THUMB_rd_rm_q_rn_p_STREX: + mov cl,0x37 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov [thumb32_error],ERROR_dest_cannot_be_source_or_memory_address + movzx eax,[operand_register0] ;rd + movzx ecx,[operand_register1] ;rm + movzx edx,[operand_register2] ;rn + cmp eax,ecx + jz THUMB_post_process + cmp eax,edx + jz THUMB_post_process + test ebp,3 shl 21 ;STREXB or STREXH? + mov ebp,[thumb32_instruction] + jz .strex + ;STREXB or STREXH + or ebp,eax + shl ecx,12 + or ebp,ecx + shl edx,16 + or ebp,edx + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_SYNC + jz ERROR_requires_cpu_capability_arm_sync + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz THUMB_post_process + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .strex: + shl eax,8 + or ebp,eax + shl ecx,12 + or ebp,ecx + shl edx,16 + or ebp,edx + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x3fc + mov eax,[immediate_value] + test eax,not (0xff shl 2) + jnz THUMB_post_process + shr eax,2 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rn_rm_rotation: + ;used by SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\ ;0=rd,rn,rm + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm> ;1=rd,rn,rm,ror imm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rn_rm_rotation + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx ecx,[operand_register0] ;rd + cmp ecx,0xf + jz ERROR_r15_not_valid.first + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;rn + cmp ecx,0xf + jz ERROR_r15_not_valid.second + shl ecx,16 + or ebp,ecx + movzx ecx,[operand_register2] ;rm + cmp ecx,0xf + jz ERROR_r15_not_valid.third + or ebp,ecx + cmp al,1 + jnz ARM_store_instruction + mov cl,[instruction_shift_op] + cmp cl,ARM_SHIFT_OPCODE_ROR + jnz ERROR_shift_type_must_be_ROR + mov ecx,[immediate_value] + test ecx,not (3 shl 3) + jnz ERROR_shift_value_out_of_range.0_24 + shl ecx,10-3 + or ebp,ecx + jmp ARM_store_instruction + .THUMB_rd_rn_rm_rotation: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx ecx,[operand_register0] ;rd + shl ecx,8 + or ebp,ecx + movzx ecx,[operand_register1] ;rn + shl ecx,16 + or ebp,ecx + movzx ecx,[operand_register2] ;rm + or ebp,ecx + cmp al,1 + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jnz THUMB_post_process + mov [thumb32_error],ERROR_shift_type_must_be_ROR + mov cl,[instruction_shift_op] + cmp cl,ARM_SHIFT_OPCODE_ROR + jnz THUMB_post_process + mov [thumb32_error],ERROR_shift_value_out_of_range.0_24 + mov ecx,[immediate_value] + test ecx,not (3 shl 3) + jnz THUMB_post_process + shl ecx,4-3 + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_rotation: + ;used by SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH + call decode_template + TEMPLATE \ + <TMPL_base_reg>,\ ;0=rdm + <TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\ ;1=rdm,ror imm + <TMPL_base_reg,TMPL_base_reg>,\ ;2=rd,rm + <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm> ;3=rd,rm,ror imm + sub al,2 + jnc .registers_okay + mov cl,[operand_register0] + mov [operand_register1],cl + .registers_okay: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx ecx,[operand_register0] ;rd + cmp ecx,0xf + jz ERROR_r15_not_valid.first + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + cmp ecx,0xf + jz ERROR_r15_not_valid.second + or ebp,ecx + cmp al,1 + jnz ARM_store_instruction + mov cl,[instruction_shift_op] + cmp cl,ARM_SHIFT_OPCODE_ROR + jnz ERROR_shift_type_must_be_ROR + mov ecx,[immediate_value] + test ecx,not (3 shl 3) + jnz ERROR_shift_value_out_of_range.0_24 + shl ecx,10-3 + or ebp,ecx + jmp ARM_store_instruction + .THUMB_rd_rm: + test ebp,1 shl 21 + jz .THUMB_rd_rm_rotation.t2 ;SXTB16, UXTB16 not encodable + cmp al,0 + jz .rotation_okay + cmp [immediate_value],0 + jnz .THUMB_rd_rm_rotation + .rotation_okay: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v6t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T + jz .THUMB_rd_rm_rotation + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + movzx edx,word[operand_register0] ;rd,rm + test dx,0x0808 + jnz .THUMB_rd_rm_rotation + shl dh,3 + or dl,dh + test ebp,1 shl 20 + setz cl + shl cl,6 + or dl,cl + test ebp,1 shl 22 + setnz cl + shl cl,7 + or dl,cl + mov dh,0xb2 + mov [thumb16_instruction],dx + mov [thumb16_error],0 + .THUMB_rd_rm_rotation.t2: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_t2 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz THUMB_post_process + jmp .THUMB_rd_rm_rotation.do + .THUMB_rd_rm_rotation: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + .THUMB_rd_rm_rotation.do: + mov cl,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx ecx,[operand_register0] ;rd + shl ecx,8 + or ebp,ecx + movzx ecx,[operand_register1] ;rm + or ebp,ecx + cmp al,1 + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jnz THUMB_post_process + mov [thumb32_error],ERROR_shift_type_must_be_ROR + mov cl,[instruction_shift_op] + cmp cl,ARM_SHIFT_OPCODE_ROR + jnz THUMB_post_process + mov [thumb32_error],ERROR_shift_value_out_of_range.0_24 + mov ecx,[immediate_value] + test ecx,not (3 shl 3) + jnz THUMB_post_process + shl ecx,4-3 + or ebp,ecx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rm_rs_SAD: + ;used by USAD8 + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=rd,rm,rs + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rd_rn_rm.THUMB_rd_rn_rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6 + jz ERROR_requires_cpu_capability_arm_v6 + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,8 + or ebp,eax + jmp ARM_store_instruction + +;K + +ARM_clrex: + ;used by CLREX + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_clrex + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_K + jz ERROR_requires_cpu_capability_arm_k + jmp ARM_store_instruction + .THUMB_clrex: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rt_rt2_q_rn_p: + ;used by LDREXD, LDAEXD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rt,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right> ;1=rt,rt2,[rn] + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rt_rt2_q_rn_p + mov ecx,[operand_registers] ;rt,rt2,rn + cmp al,1 + jnz .check_rt + sub ch,1 + cmp ch,cl + jnz ERROR_destination_registers_must_be_consecutive + shr ecx,8 + .check_rt: + test cl,1 + jnz ERROR_destination_register_must_be_even + cmp cl,14 + jz ERROR_r14_not_valid.first + mov [operand_registers],ecx ;rt,rn + test ebp,1 shl 8 + jnz ARM_rd_q_rn_p.check_v6k + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + jmp ARM_rd_q_rn_p.version_okay + .THUMB_rt_rt2_q_rn_p: + test ebp,1 shl 8 + jnz .check_v7 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + jmp .THUMB_version_okay + .check_v7: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz ERROR_requires_cpu_capability_arm_v7 + .THUMB_version_okay: + cmp al,1 + jz .check_bad + mov ecx,[operand_registers] ;rt,rn + shl ecx,8 + mov cl,ch + inc ch + mov [operand_registers],ecx ;rt,rt2,rn + .check_bad: + mov cl,0x37 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov [thumb32_error],ERROR_destination_registers_must_differ + mov ecx,[operand_registers] + cmp ch,cl + jz THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rt + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rt2 + shl eax,8 + or ebp,eax + movzx eax,[operand_register2] ;rn + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rt_rt2_q_rn_p: + ;used by STREXD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,rt,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right> ;1=rd,rt,rt2,[rn] + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rt_rt2_q_rn_p + mov ecx,[operand_registers] ;rd,rt,rt2,rn + cmp al,1 + jnz .check_rt + mov eax,ecx + shr eax,8 + sub ah,1 + cmp ah,al + jnz ERROR_source_registers_must_be_consecutive + mov eax,ecx + shr ecx,8 + mov ch,cl + mov cl,al + .check_rt: + test ch,1 + jnz ERROR_source_register_must_be_even + cmp ch,14 + jz ERROR_r14_not_valid.second + mov [operand_registers],ecx ;rd,rt,rn + inc ch + cmp ch,cl + jz ERROR_source_and_dest_must_differ + jmp ARM_rd_rm_q_rn_p_STREX.check_v6k + .THUMB_rd_rt_rt2_q_rn_p: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz ERROR_requires_cpu_capability_arm_v7 + .THUMB_adjust_three_to_four: + cmp al,1 + jz .check_bad + mov ecx,[operand_registers] ;rd,rt,rn + mov edx,ecx + inc ch + shl ecx,8 + mov cx,dx + mov [operand_registers],ecx + .check_bad: + mov cl,0x7f + call THUMB2_check_bad_regs + jc THUMB_post_process + mov [thumb32_error],ERROR_source_and_dest_must_differ + mov cl,[operand_register0] + cmp cl,[operand_register1] + jz THUMB_post_process + cmp cl,[operand_register2] + jz THUMB_post_process + cmp cl,[operand_register3] + jz THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + or ebp,eax + movzx eax,[operand_register1] ;rt + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rt2 + shl eax,8 + or ebp,eax + movzx eax,[operand_register3] ;rn + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +;Z + +ARM_immediate4: + ;used by SMC, SMI + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_Z + jz ERROR_requires_cpu_capability_arm_z + mov eax,[immediate_value] + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_immediate4 + cmp eax,0xf + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_15 + jmp ARM_store_instruction_with_error + .THUMB_immediate4: + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb32_error],ERROR_immediate_value_out_of_range.0_15 + cmp eax,0xf + ja THUMB_post_process + mov ebp,[thumb32_instruction] + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +;v6T2 + +ARM_rd_address3T: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB2_rd_address + ;used by LDRHT, LDRSHT, LDRSBT, STRHT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ;1=rd,[rn],+-rm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm> ;2=rd,[rn],imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + jmp ARM_rd_address3.version_check_okay + +THUMB_rd_rn_imm12: + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_rd_rn_shifter + ;used by ADDW, SUBW + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm>,\ ;0=reg,imm alternate for reg,reg,imm + <TMPL_base_reg,TMPL_base_reg,TMPL_imm> ;1=reg,reg,imm + cmp al,1 + jz .encode + mov al,[operand_register0] + mov [operand_register1],al + .encode: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov [thumb32_error],ERROR_instruction_not_16bit + test [instruction_condition],FLAG_CONDITION_SET + jnz THUMB_post_process + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0xfff + mov eax,[immediate_value] + mov edx,[thumb32_instruction] + mov ecx,eax + mov ebp,edx + xor ebp,5 shl 21 + neg ecx + cmovns eax,ecx + cmovns edx,ebp + mov [thumb32_instruction],edx + mov [immediate_value],eax + test eax,not 0xfff + jnz THUMB_post_process + mov cl,0x31 + cmp [operand_register1],13 + jnz .check_bad_regs + mov cl,0x03 + .check_bad_regs: + jmp THUMB_GEN_rd_rn_shifter.reg_reg_imm.encode + +ARM_rd_imm_imm: + ;used by BFC + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;0=reg,imm,imm + jmp ARM_rd_rn_imm_imm.do + +ARM_rd_rn_imm_imm: + ;used by BFI + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;0=reg,reg,imm,imm + .do: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rn_imm_imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + movzx eax,[operand_register0] + cmp eax,15 + jz ERROR_r15_not_valid + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + cmp eax,15 + jz ERROR_r15_not_valid + or ebp,eax + mov eax,[immediate_value] + cmp eax,31 + mov ecx,ERROR_lsb_out_of_range.0_31 + ja ARM_store_instruction_with_error + shl eax,7 + or ebp,eax + mov ecx,ERROR_width_out_of_range + mov edx,[immediate_value2] + shr eax,7 + add eax,edx + jc ARM_store_instruction_with_error + cmp eax,32 + ja ARM_store_instruction_with_error + dec eax + shl eax,16 + or ebp,eax + jmp ARM_store_instruction + .THUMB_rd_rn_imm_imm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov ecx,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + mov [thumb32_error],ERROR_lsb_out_of_range.0_31 + mov eax,[immediate_value] + cmp eax,31 + ja THUMB_post_process + mov ecx,eax + mov edx,eax + and ecx,3 + and edx,0x1c + shl ecx,6 + shl edx,12-2 + or ebp,ecx + or ebp,edx + mov [thumb32_error],ERROR_width_out_of_range + mov edx,[immediate_value2] + add eax,edx + jc THUMB_post_process + cmp eax,32 + ja THUMB_post_process + dec eax + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMB_reg_address: + ;used by CBNZ, CBZ + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_address> ;0=reg,imm PC relative + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + mov ebp,[thumb32_instruction] + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + movzx eax,[operand_register0] + cmp eax,7 + ja THUMB_post_process + or ebp,eax + mov [thumb16_error],ERROR_relative_jump_not_aligned + mov ecx,edi + mov eax,[addressing_space] + sub ecx,[eax+0x00] + neg ecx + add ecx,[immediate_value] + sub ecx,4 + cmp [value_undefined],0 + jz .offset_okay + xor ecx,ecx + .offset_okay: + test ecx,1 + jnz THUMB_post_process + sar ecx,1 + mov [thumb32_error],ERROR_relative_jump_out_of_range + cmp ecx,1 shl 6 + jae THUMB_post_process + mov eax,ecx + and eax,0x1f + and ecx,0x20 + shl eax,3 + shl ecx,9-5 + or ebp,eax + or ebp,ecx + mov [thumb16_instruction],bp + mov [thumb16_error],0 + jmp THUMB_post_process + +THUMB_condition: + ;used by IT + call decode_template + TEMPLATE \ + <TMPL_condition> ;0=condition + test [code_type],CPU_ACTIVITY_ARM + jnz .version_check_okay + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + .version_check_okay: + cmp [explicit_IT_state],0 + jnz ERROR_instruction_not_conditional + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + cmp eax,0xe ;AL? + jnz .AL_okay + bsf ecx,ebp + mov edx,ebp + btr edx,ecx + and edx,0xf + jnz ERROR_al_has_no_inverse + .AL_okay: + shl eax,4 + mov edx,eax + or edx,1 + or ebp,eax + and eax,0x10 + bsf ecx,ebp + cmp ecx,3 + jz .store + mov ebx,8 + .next_bit: + shl edx,8 + mov dl,[operand_register0] + test ebp,ebx + setnz ch + xor dl,ch + shl dl,4 + or dl,1 + shr eax,1 + xor ebp,eax + shr ebx,1 + inc cl + cmp cl,3 + jnz .next_bit + .store: + xor eax,eax + .swap_order: + shl eax,8 + mov al,dl + shr edx,8 + jnz .swap_order + or eax,2 + mov [explicit_IT_state],eax + mov [thumb16_instruction],bp + mov [thumb16_error],0 + .finalise: + test [code_type],CPU_ACTIVITY_ARM + jz THUMB_post_process + and eax,not 2 ;activate the block + mov [explicit_IT_state],eax + jmp instruction_assembled + +THUMB2_rd_address_rm_translate_table: + ;bits 24..20 translate to 11..9 + ;used for rd,[rn,rm] 16bit encoding + db 00100b ;000 str + db 00010b ;001 strh + db 00000b ;010 strb + db 10001b ;011 ldrsb + db 00101b ;100 ldr + db 00011b ;101 ldrh + db 00001b ;110 ldrb + db 10011b ;111 ldrsh + +THUMB2_rd_address_imm_translate_table: + ;bits 22..20 translate to 15..11 + ;used for rd,[rn,imm] 16bit encoding + db 01110b ;strb 000 + db 01111b ;ldrb 001 + db 10000b ;strh 010 + db 10001b ;ldrh 011 + db 01100b ;str 100 + db 01101b ;ldr 101 + +THUMB2_rd_address: + cmp [operand_size],8 ;LDRD or STRD? + jz THUMB2_rd_rd2_address + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=rd,[rn],imm POP {reg} + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;2=rd,[rn,imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;3=rd,[rn,imm]! PUSH {reg} + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ;4=rd,[rn,rm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm2,TMPL_bracket_right>,\ ;5=rd,[rn,rm,shift imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;6=rd,[imm] PC relative + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;7=rd,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;8=rd,[exp]! implicit reg from structure + ; T2 encoding, *???(??) = available in T1, ??? = bits 11..9, ????? = bits 15..11, ^=modified behaviour in T2EE mode + ; + ;* ldr 11111000u101<pc>ttttiiiiiiiiiiii if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE + ; ldrb 11111000u001<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLD if t=15 (6T2) + ; ldrh 11111000u011<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; + ; ldrsb 11111001u001<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLI if t=15 (v7) + ; ldrsh 11111001u011<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; + ; + ;*01101 ldr 111110001101nnnnttttiiiiiiiiiiii if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE + ;*01111 ldrb 111110001001nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLD if t=15 (6T2) + ;*10001 ldrh 111110001011nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLDW if t=15 (MP) + ; ldrsb 111110011001nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLI if t=15 (v7) + ; ldrsh 111110011011nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; + ; + ; ldrt 111110000101nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE; + ; ldrbt 111110000001nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE; + ; ldrht 111110000011nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE; + ; ldrsbt 111110010001nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE; + ; ldrsht 111110010011nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE; + ; + ; ldr 111110000101nnnntttt1puwiiiiiiii if (wback & n=t) | (t=15 & InITBlock() & !LastInITBlock()) then UNPREDICTABLE; POP {reg} + ; ldrb 111110000001nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLD if t=15 (6T2) + ; ldrh 111110000011nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLDW if t=15 (MP) + ; ldrsb 111110010001nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLI if t=15 (v7) + ; ldrsh 111110010011nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; + ; + ;*100^ ldr 111110000101nnnntttt000000iimmmm if BadReg(m) then UNPREDICTABLE; if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE + ;*110 ldrb 111110000001nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLD if t=15 (6T2) + ;*101^ ldrh 111110000011nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLDW if t=15 (MP) + ;*011 ldrsb 111110010001nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLI if t=15 (v7) + ;*111^ ldrsh 111110010011nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; + ; + ;*01100 str 111110001100nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if t=15 then UNPREDICTABLE; + ;*01110 strb 111110001000nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE; + ;*10000 strh 111110001010nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE; + ; + ; strt 111110000100nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE; + ; strbt 111110000000nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE; + ; strht 111110000010nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE; + ; + ; str 111110000100nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if t=15 | (wback & n=t) then UNPREDICTABLE; PUSH {reg} + ; strb 111110000000nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if BadReg(t) | (wback & n=t) then UNPREDICTABLE; + ; strh 111110000010nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if BadReg(t) | (wback & n=t) then UNPREDICTABLE; + ; + ;*000^ str 111110000100nnnntttt000000iimmmm if n=15 then UNDEFINED; if t=15 | BadReg(m) then UNPREDICTABLE; + ;*010 strb 111110000000nnnntttt000000iimmmm if n=15 then UNDEFINED; if BadReg(t) | BadReg(m) then UNPREDICTABLE; + ;*001^ strh 111110000010nnnntttt000000iimmmm if n=15 then UNDEFINED; if BadReg(t) | BadReg(m) then UNPREDICTABLE; + ; + .do: + mov ebp,[thumb32_instruction] + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz .check_bad_rn + test ebp,1 shl 20 ;0=STRx, 1=LDRx + jnz .check_rd + .check_bad_rn: + cmp [operand_register1],0xf + jz ERROR_r15_not_valid.second + cmp [value_undefined],0 + jnz .check_rd + cmp al,6 + jz ERROR_r15_not_valid.second + .check_rd: + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz .check_bad_rd + test ebp,1 shl 22 ;word? + jz .check_bad_rd + test ebp,1 shl 20 ;0=STRx, 1=LDRx + jz .check_rd_for_pc + jmp .check_rm ;word loads to PC are okay + .check_bad_rd: + cmp [operand_register0],0xd + jz ERROR_dest_cannot_be_sp_pc + .check_rd_for_pc: + cmp [operand_register0],0xf + jz ERROR_dest_cannot_be_sp_pc + .check_rm: + test [operand_register2],0x80 ;-rm? + jnz ERROR_instruction_not_16bit + cmp [operand_register2],0xd + jz ERROR_offset_register_cannot_be_sp_pc + cmp [operand_register2],0xf + jz ERROR_offset_register_cannot_be_sp_pc + cmp [operand_register0],0xf + jnz .IT_block_okay + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + .IT_block_okay: + mov ecx,[operand_registers] + cmp al,0 + jz .rd_q_rn_p + cmp al,1 + jz .rd_q_rn_p_imm + cmp al,2 + jz .rd_q_rn_imm_p + cmp al,3 + jz .rd_q_rn_imm_p! + cmp al,4 + jz .rd_q_rn_rm_p + cmp al,5 + jz .rd_q_rn_rm_shift_imm_p + cmp al,6 + jz .rd_q_imm_p + cmp al,7 + jz .rd_q_exp_p + cmp al,8 + jz .rd_q_exp_p! + ud2 + .rd_q_rn_p_imm: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .rd_q_rn_p_imm.32 + cmp [operand_size],4 + jnz .rd_q_rn_p_imm.32 + ;special case for ldr lreg|pc,[sp],4 to use pop {lreg} + cmp [immediate_value],4 + jnz .rd_q_rn_p_imm.32 + cmp ch,13 + jnz .rd_q_rn_p_imm.not_sp + test ebp,1 shl 20 ;0=STRx, 1=LDRx + jz .rd_q_rn_p_imm.32 + cmp cl,15 + mov dx,0xbd00 + jz .rd_q_rn_p_imm.pc + cmp cl,7 + ja .rd_q_rn_p_imm.32 + mov dx,0xbc01 + shl dl,cl + .rd_q_rn_p_imm.pc: + mov [thumb16_instruction],dx + mov [thumb16_error],0 + jmp .rd_q_rn_p_imm.32 + .rd_q_rn_p_imm.not_sp: + ;special case for ldr/str lreg1,[lreg2],4 to use ldmia/stmia lreg2,{lreg1} + test cx,0x0808 + jnz .rd_q_rn_p_imm.32 + test ebp,1 shl 20 ;0=STRx, 1=LDRx + jz .rd_q_rn_p_imm.ldr_okay + mov [thumb16_error],ERROR_base_and_dest_must_differ_with_writeback + cmp cl,ch + jz .rd_q_rn_p_imm.32 + .rd_q_rn_p_imm.ldr_okay: + mov edx,ebp + shr edx,20-11 + and dx,0x0800 ;get L bit + or dx,0xc001 + shl dl,cl + or dh,ch + mov [thumb16_instruction],dx + mov [thumb16_error],0 + .rd_q_rn_p_imm.32: + mov [thumb32_error],ERROR_base_and_dest_must_differ_with_writeback + cmp cl,ch + jz THUMB_post_process + cmp ch,0xf + jz ERROR_r15_not_valid.post + cmp [immediate_value],0 + jz .rd_q_rn_imm_p + mov [thumb32_error],ERROR_instruction_not_16bit + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz THUMB_post_process + or ebp,1 shl 8 + jmp .encode_imm8 + .rd_q_exp_p!: + .rd_q_rn_imm_p!: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .rd_q_rn_imm_p!.32 + cmp [operand_size],4 + jnz .rd_q_rn_imm_p!.32 + ;special case for str lreg|pc,[sp,-4]! to use push {lreg} + test ebp,1 shl 20 ;0=STRx, 1=LDRx + jnz .rd_q_rn_imm_p!.32 + cmp ch,13 + jnz .rd_q_rn_imm_p!.32 + cmp [immediate_value],-4 + jnz .rd_q_rn_imm_p!.32 + cmp cl,14 + mov dx,0xb500 + jz .rd_q_rn_imm_p!.lr + cmp cl,7 + ja .rd_q_rn_imm_p!.32 + mov dx,0xb401 + shl dl,cl + .rd_q_rn_imm_p!.lr: + mov [thumb16_instruction],dx + mov [thumb16_error],0 + .rd_q_rn_imm_p!.32: + cmp cl,ch + jz ERROR_base_and_dest_must_differ_with_writeback + cmp ch,0xf + jz ERROR_r15_not_valid.post + mov [thumb32_error],ERROR_instruction_not_16bit + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz THUMB_post_process + or ebp,1 shl 10 + 1 shl 8 + jmp .encode_imm8 + .rd_q_imm_p: + mov [operand_register1],0xf + push ecx + call THUMB_query_condition_pc + mov eax,ecx + pop ecx + mov ch,0xf + cmp [value_undefined],0 + jnz .rd_q_exp_p + mov edx,[addressing_space] + sub eax,[edx+0x00] + and eax,not 3 ;round down + neg eax + add eax,[immediate_value] + sub eax,4 + test eax,3 + jz .place_aligned_offset + cmp dword[adjustment],0 + jz .place_aligned_offset + mov [next_pass_needed],-1 + and eax,not 3 ;assume the offset will be aligned + .place_aligned_offset: + mov [immediate_value],eax + .rd_q_exp_p: + .rd_q_rn_imm_p: + .rd_q_rn_p: + mov [thumb16_error],ERROR_immediate_cannot_be_encoded + test [immediate_value],-1 + jns .positive_offset + test ebp,1 shl 20 ;LDRx=1? + jz .rd_q_rn_p.thumb + test ebp,1 shl 22 ;LDR=1? + jz .rd_q_rn_p.thumb + test [code_type],CPU_ACTIVITY_THUMBEE + jz .rd_q_rn_p.thumb + mov [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz .rd_q_rn_p.thumb + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ecx,0x0808 ;any high registers? + jnz .rd_q_rn_p.thumb + mov [thumb16_error],ERROR_immediate_offset_out_of_range.m28_0 + mov edx,[immediate_value] + neg edx + test edx,not (7 shl 2) + jnz .rd_q_rn_p.thumb + movzx eax,ch + shl eax,3 + or al,cl + shl edx,6-2 + or eax,edx + or ax,0xc800 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + .rd_q_rn_p.thumb: + cmp ch,0xf + jz .encode_imm12 + or ebp,1 shl 10 + jmp .encode_imm8 + .positive_offset: + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz .encode_imm8 + or ebp,1 shl 23 + mov [thumb16_error],ERROR_instruction_not_16bit + test ebp,1 shl 24 ;if it is a signed load then no 16bit form is available + jnz .encode_imm12 + test [code_type],CPU_ACTIVITY_THUMBEE + jz .positive_offset.v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz .positive_offset.v4t + cmp ch,9 + jz .positive_offset.r9 + cmp ch,10 + jnz .positive_offset.v4t + test ebp,1 shl 20 ;LDRx=1? + jz .encode_imm12 + test ebp,1 shl 22 ;LDR=1? + jz .encode_imm12 + ;ldr rt,[r10,imm] + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test cl,0x08 ;high register? + jnz .encode_imm12 + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x7c + mov edx,[immediate_value] + test edx,not (0x1f shl 2) + jnz .encode_imm12 + shl edx,3-2 + movzx ecx,cl + lea edx,[edx+ecx+0xcb00] + mov [thumb16_instruction],dx + mov [thumb16_error],0 + jmp .encode_imm12 + .positive_offset.r9: + test ebp,1 shl 22 ;LDR or STR (=1)? + jz .encode_imm12 + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test cl,0x08 ;high register? + jnz .encode_imm12 + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xfc + mov edx,[immediate_value] + test edx,not (0x3f shl 2) + jnz .encode_imm12 + shl edx,3-2 + movzx ecx,cl + lea edx,[edx+ecx+0xcc00] + bt ebp,20 + setnc cl + movzx ecx,cl + shl ecx,9 + or edx,ecx + mov [thumb16_instruction],dx + mov [thumb16_error],0 + jmp .encode_imm12 + .positive_offset.v4t: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .encode_imm12 + mov dx,0x9000 + cmp ch,0xd ;SP? + jz .16bit_imm8 + mov dx,0x4000 + cmp ch,0xf ;PC? + jz .16bit_imm8 + mov [thumb16_error],ERROR_register_out_of_range + test ecx,0x0808 ;any high registers? + jnz .encode_imm12 + mov [thumb16_error],ERROR_immediate_cannot_be_encoded + mov ecx,ebp + shr ecx,20 + and ecx,6 + setz dl + add cl,dl ;ecx=1, 2 or 4 for B, H, W + imul edx,ecx,31 + not edx + test [immediate_value],edx + jnz .encode_imm12 + mov edx,ebp + shr edx,20 + and edx,111b + movzx edx,byte[edx+THUMB2_rd_address_imm_translate_table] + shl edx,11 + movzx eax,[operand_register0] + or edx,eax + movzx eax,[operand_register1] + shl eax,3 + or edx,eax + mov eax,[immediate_value] + shl eax,6 + shr ecx,1 + shr eax,cl + or edx,eax + mov [thumb16_instruction],dx + mov [thumb16_error],0 + jmp .encode_imm12 + .16bit_imm8: + mov [thumb16_error],ERROR_instruction_not_16bit + cmp [operand_size],4 ;LDR or STR? + jnz .encode_imm12 + mov [thumb16_error],ERROR_register_out_of_range + test ecx,0x08 ;a high register? + jnz .encode_imm12 + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc + test [immediate_value],not (0xff shl 2) + jnz .encode_imm12 + movzx eax,[operand_register0] + shl eax,8 + or edx,eax + mov eax,[immediate_value] + shr eax,2 + mov dl,al + mov eax,ebp + shr eax,20-11 + and eax,1 shl 11 + or edx,eax + mov [thumb16_instruction],dx + mov [thumb16_error],0 + jmp .encode_imm12 + .rd_q_rn_rm_p: + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz .rd_q_rn_rm_shift_imm_p + mov [thumb16_error],ERROR_register_out_of_range.r0_r7 + test ecx,0x080808 ;any high registers? + jnz .rd_q_rn_rm_shift_imm_p + test [code_type],CPU_ACTIVITY_THUMBEE + jz .rd_q_rn_rm_p.thumb + ;only byte version encodings are available in T2EE mode + mov [thumb16_error],ERROR_instruction_not_t2ee + test ebp,01110b shl 20 + jnz .rd_q_rn_rm_shift_imm_p + mov [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz .rd_q_rn_rm_shift_imm_p + jmp .rd_q_rn_rm_p.thumbee + .rd_q_rn_rm_p.thumb: + mov [thumb16_error],ERROR_requires_cpu_capability_arm_v4t + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T + jz .rd_q_rn_rm_shift_imm_p + .rd_q_rn_rm_p.thumbee: + ;encode a 16bit form + mov eax,ebp + shr eax,20 + and eax,11111b + mov edx,THUMB2_rd_address_rm_translate_table + .find_16bit_rm_code: + cmp al,[edx] + jz .found_16bit_rm_code + inc edx + cmp edx,THUMB2_rd_address_rm_translate_table+8 + jb .find_16bit_rm_code + ud2 + .found_16bit_rm_code: + sub edx,THUMB2_rd_address_rm_translate_table + shl edx,9 + or edx,0x5000 + movzx eax,[operand_register0] + or edx,eax + movzx eax,[operand_register1] + shl eax,3 + or edx,eax + movzx eax,[operand_register2] + shl eax,6 + or edx,eax + mov [thumb16_instruction],dx + mov [thumb16_error],0 + .rd_q_rn_rm_shift_imm_p: + mov [thumb32_error],ERROR_r15_not_valid.base + cmp ch,0xf + jz THUMB_post_process + mov [thumb32_error],ERROR_shift_type_must_be_LSL + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz THUMB_post_process + ;T2EE + cmp [thumb16_error],0 ;second time around? + jz .rd_q_rn_rm_shift_imm_p.thumb + test [code_type],CPU_ACTIVITY_THUMBEE + jz .rd_q_rn_rm_shift_imm_p.thumb + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz .rd_q_rn_rm_shift_imm_p.thumb + mov [thumb16_error],ERROR_register_out_of_range + test ecx,0x080808 ;any high registers? + jnz .rd_q_rn_rm_shift_imm_p.thumb + ;hword and word version encodings are available in T2EE mode + mov [thumb16_error],ERROR_instruction_not_t2ee + test ebp,01110b shl 20 + jz .rd_q_rn_rm_shift_imm_p.thumb + mov [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz .rd_q_rn_rm_shift_imm_p.thumb + ;check bits 22:21 match the shift count + mov ecx,ERROR_shift_value_out_of_range.1 + mov edx,ERROR_shift_value_out_of_range.2 + test ebp,1 shl 22 + cmovnz ecx,edx + mov [thumb16_error],ecx + mov ecx,ebp + shr ecx,21 + and ecx,3 + cmp ecx,[immediate_value2] + jz .rd_q_rn_rm_p.thumbee + .rd_q_rn_rm_shift_imm_p.thumb: + mov [thumb32_error],ERROR_shift_value_out_of_range.0_3 + cmp [immediate_value2],3 + ja THUMB_post_process + mov [thumb32_error],ERROR_instruction_not_16bit + test ebp,1111b shl 8 ;STRxT/LDRxT? + jnz THUMB_post_process + jmp .encode_regs + .encode_imm12: + mov eax,[immediate_value] + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xfff + test ebp,1 shl 23 + jnz .imm12_positive_only + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0xfff + or ebp,1 shl 23 + test eax,eax + jns .imm12_positive_only + and ebp,not (1 shl 23) + neg eax + .imm12_positive_only: + cmp eax,0xfff + ja THUMB_post_process + or ebp,eax + jmp .encode_regs + .encode_imm8: + or ebp,1 shl 11 + mov eax,[immediate_value] + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xff + test ebp,1 shl 9 + jnz .imm8_positive_only + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0xff + or ebp,1 shl 9 + test eax,eax + jns .imm8_positive_only + and ebp,not (1 shl 9) + neg eax + .imm8_positive_only: + cmp eax,0xff + ja THUMB_post_process + or ebp,eax + .encode_regs: + mov ecx,ebp + and ecx,0x17 shl 20 + 0xf shl 12 + ;if bits[24..20]=0x011 and bits[15..12]=1111 then check for MP (PLDW) + cmp ecx,0x03 shl 20 + 0xf shl 12 + jz .check_PLDW + ;if bits[24..20]=1x001 and bits[15..12]=1111 then check for v7 (PLI) + cmp ecx,0x11 shl 20 + 0xf shl 12 + jz .check_PLI + mov [thumb32_error],ERROR_requires_cpu_capability_arm_7m + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + jmp .version_check_okay + .check_PLDW: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_mp + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_MP + jz THUMB_post_process + mov [thumb32_error],ERROR_r15_not_valid.base + cmp [operand_register1],0xf + jz THUMB_post_process + jmp .version_check_okay + .check_PLI: + mov [thumb32_error],ERROR_requires_cpu_capability_arm_v7 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz THUMB_post_process + .version_check_okay: + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + or ebp,eax + mov eax,[immediate_value2] + shl eax,4 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMB2_rd_rd2_address: + ;used by STRD, LDRD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 0=rd,[rn] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=rd,[rn],imm + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=rd,[rn,imm] + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=rd,[rn,imm]! + <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ; 4=rd,[imm] PC relative + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 5=rd,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 6=rd,[exp]! implicit reg from structure + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 7=rd,rd2,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 8=rd,rd2,[rn],imm + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 9=rd,rd2,[rn,imm] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;10=rd,rd2,[rn,imm]! + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;11=rd,rd2,[imm] PC relative + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=rd,rd2,[exp] implicit reg from structure + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;13=rd,rd2,[exp]! implicit reg from structure + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov ebp,[thumb32_instruction] + sub al,7 + jae .dest_registers_defined + mov ecx,[operand_registers] + mov dl,cl + inc cl + shl ecx,8 + mov cl,dl + mov [operand_registers],ecx + add al,7 + .dest_registers_defined: + mov cl,0x33 + mov dl,0x37 + test ebp,1 shl 20 ;LDRD? + cmovz ecx,edx + call THUMB2_check_bad_regs + jc THUMB_post_process + test ebp,1 shl 20 ;LDRD? + jz .same_regs_okay + mov ecx,[operand_registers] + cmp cl,ch + mov [thumb32_error],ERROR_destination_registers_must_differ + jz THUMB_post_process + .same_regs_okay: + cmp al,0 + jz .rd_q_rn_p + cmp al,1 + jz .rd_q_rn_p_imm + cmp al,2 + jz .rd_q_rn_imm_p + cmp al,3 + jz .rd_q_rn_imm_p! + cmp al,4 + jz .rd_q_imm_p + cmp al,5 + jz .rd_q_exp_p + cmp al,6 + jz .rd_q_exp_p! + ud2 + .rd_q_rn_p_imm: + cmp [operand_register2],0xf + jz ERROR_r15_not_valid.post + or ebp,1 shl 21 ;set W + jmp .check_dest_and_source_differ + .rd_q_imm_p: + mov [operand_register2],0xf + call THUMB_query_condition_pc + mov eax,ecx + mov ch,0xf + cmp [value_undefined],0 + jnz .rd_q_exp_p + mov edx,[addressing_space] + sub eax,[edx+0x00] + and eax,not 3 ;round down + neg eax + add eax,[immediate_value] + sub eax,4 + mov [immediate_value],eax + .rd_q_exp_p: + .rd_q_rn_imm_p: + .rd_q_rn_p: + or ebp,1 shl 24 ;set P + jmp .encode + .rd_q_exp_p!: + .rd_q_rn_imm_p!: + cmp [operand_register2],0xf + jz ERROR_r15_not_valid.post + or ebp,1 shl 24 + 1 shl 21 ;set P & W + .check_dest_and_source_differ: + mov [thumb32_error],ERROR_base_and_dest_must_differ_with_writeback + mov cl,[operand_register2] + cmp cl,[operand_register1] + jz THUMB_post_process + cmp cl,[operand_register0] + jz THUMB_post_process + .encode: + mov eax,[immediate_value] + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0x3fc + or ebp,1 shl 23 + test eax,eax + jns .imm8_positive + and ebp,not (1 shl 23) + neg eax + .imm8_positive: + test eax,not (0xff shl 2) + jnz THUMB_post_process + shr eax,2 + or ebp,eax + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,8 + or ebp,eax + movzx eax,[operand_register2] + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_imm16: + ;used by MOVW, MOVT + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm> ;0=reg,imm + .do: + ;entry from MOV + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_imm16 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + movzx eax,[operand_register0] + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + mov eax,[immediate_value] + cmp eax,0xffff + mov ecx,ERROR_immediate_value_out_of_range.0_0xffff + ja ARM_store_instruction_with_error + mov ecx,eax + and eax,0x0fff + and ecx,0xf000 + shl ecx,16-12 + or ebp,eax + or ebp,ecx + jmp ARM_store_instruction + .THUMB_rd_imm16: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov ebp,[thumb32_instruction] + mov cl,0x11 + call THUMB2_check_bad_regs + jc THUMB_post_process + movzx eax,[operand_register0] + shl eax,8 + or ebp,eax + mov eax,[immediate_value] + cmp eax,0xffff + mov [thumb32_error],ERROR_immediate_value_out_of_range.0_0xffff + ja THUMB_post_process + mov ecx,eax + mov edx,eax + mov ebx,eax + and eax,0x00ff + and ecx,0x0700 + and edx,0x0800 + and ebx,0xf000 + shl ecx,12-8 + shl edx,26-11 + shl ebx,16-12 + or ebp,eax + or ebp,ecx + or ebp,edx + or ebp,ebx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rn_imm_imm_X: + ;used by SBFX, UBFX + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;0=reg,reg,imm,imm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rn_imm_imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2 + jz ERROR_requires_cpu_capability_arm_t2 + movzx eax,[operand_register0] + cmp eax,15 + jz ERROR_r15_not_valid + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + cmp eax,15 + jz ERROR_r15_not_valid + or ebp,eax + mov eax,[immediate_value] + cmp eax,31 + mov ecx,ERROR_lsb_out_of_range.0_31 + ja ARM_store_instruction_with_error + shl eax,7 + or ebp,eax + mov ecx,ERROR_width_out_of_range + mov edx,[immediate_value2] + shr eax,7 + add eax,edx + jc ARM_store_instruction_with_error + cmp eax,32 + ja ARM_store_instruction_with_error + dec edx + shl edx,16 + or ebp,edx + jmp ARM_store_instruction + .THUMB_rd_rn_imm_imm: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov ecx,0x33 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + mov [thumb32_error],ERROR_lsb_out_of_range.0_31 + mov eax,[immediate_value] + cmp eax,31 + ja THUMB_post_process + mov ecx,eax + mov edx,eax + and ecx,3 + and edx,0x1c + shl ecx,6 + shl edx,12-2 + or ebp,ecx + or ebp,edx + mov [thumb32_error],ERROR_width_out_of_range + mov edx,[immediate_value2] + add eax,edx + jc THUMB_post_process + cmp eax,32 + ja THUMB_post_process + dec edx + or ebp,edx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMB_q_rn_rm_p: + ;used by TBB + call decode_template + TEMPLATE \ + <TMPL_bracket_left,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_right> ;0=[rn,rm] + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov ecx,0x32 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMB_q_rn_rm_lsl_1_p: + ;used by TBH + call decode_template + TEMPLATE \ + <TMPL_bracket_left,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right> ;0=[rn,rm] + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov ecx,0x32 + call THUMB2_check_bad_regs + jc THUMB_post_process + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz ERROR_shift_type_must_be_LSL + cmp [immediate_value],1 + jnz ERROR_immediate_offset_out_of_range.1 + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +;thumbee + +THUMBEE_enterx: + ;used by ENTERX, LEAVEX + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=EOL + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz ERROR_requires_cpu_capability_arm_t2ee + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + mov [thumb32_error],0 + jmp THUMB_post_process + +THUMBEE_rn_rm: + ;used by CHKA + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg> ;0=rn,rm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz ERROR_requires_cpu_capability_arm_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jz ERROR_instruction_needs_t2ee + mov cl,0x23 + call THUMB2_check_bad_regs + jc THUMB_post_process + movzx eax,[operand_register0] + movzx ecx,[operand_register1] + mov edx,eax + and eax,7 + and edx,8 + shl edx,7-3 + or eax,edx + shl ecx,3 + lea eax,[eax+ecx+0xca00] + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +THUMBEE_imm: + ;used by HB, HBL + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz ERROR_requires_cpu_capability_arm_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jz ERROR_instruction_needs_t2ee + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_0xff + mov eax,[immediate_value] + cmp eax,0xff + ja THUMB_post_process + or eax,ebp + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +THUMBEE_imm5_imm5: + ;used by HBLP + call decode_template + TEMPLATE \ + <TMPL_imm,TMPL_comma,TMPL_imm2> ;0=imm,imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz ERROR_requires_cpu_capability_arm_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jz ERROR_instruction_needs_t2ee + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_31 + mov eax,[immediate_value] + cmp eax,0x1f + ja THUMB_post_process + shl eax,5 + or ebp,eax + mov eax,[immediate_value2] + cmp eax,0x1f + ja THUMB_post_process + or eax,ebp + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +THUMBEE_imm3_imm5: + ;used by HBP + call decode_template + TEMPLATE \ + <TMPL_imm,TMPL_comma,TMPL_imm2> ;0=imm,imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE + jz ERROR_requires_cpu_capability_arm_t2ee + test [code_type],CPU_ACTIVITY_THUMBEE + jz ERROR_instruction_needs_t2ee + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_7 + mov eax,[immediate_value] + cmp eax,7 + ja THUMB_post_process + shl eax,5 + or ebp,eax + mov [thumb16_error],ERROR_immediate_value_out_of_range.0_31 + mov eax,[immediate_value2] + cmp eax,0x1f + ja THUMB_post_process + or eax,ebp + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +;v7 + +ARM_imm4: + ;used by DBG + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_imm4 + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz ERROR_requires_cpu_capability_arm_v7 + mov eax,[immediate_value] + cmp eax,15 + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_15 + jmp ARM_store_instruction_with_error + .THUMB_imm4: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz ERROR_requires_cpu_capability_arm_7m + mov ebp,[thumb32_instruction] + mov [thumb32_error],ERROR_immediate_value_out_of_range.0_15 + mov eax,[immediate_value] + cmp eax,15 + ja THUMB_post_process + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_barrier: + ;used by DMB, DSB, ISB + call decode_template + TEMPLATE \ + <TMPL_barrier>,\ ;0=barrier + <TMPL_imm>,\ ;1=imm + <TMPL_EOL> ;2=default + cmp al,1 + jz .encode + mov [immediate_value],0xf + cmp al,2 + jz .encode + movzx eax,[operand_register0] + mov [immediate_value],eax + .encode: + test ebp,0x20 ;ISB? + jz .do + cmp [immediate_value],0xf ;only SY is valid + jnz ERROR_parameter_n_not_valid.all + .do: + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_barrier + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7 + jz ERROR_requires_cpu_capability_arm_v7 + mov eax,[immediate_value] + cmp eax,15 + ja .out_of_range + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_15 + jmp ARM_store_instruction_with_error + .THUMB_barrier: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + jz ERROR_requires_cpu_capability_arm_6m + mov ebp,[thumb32_instruction] + mov [thumb32_error],ERROR_immediate_value_out_of_range.0_15 + mov eax,[immediate_value] + cmp eax,15 + ja THUMB_post_process + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_nops: + ;used by SEV, SEVL, WFE, WFI, YIELD + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_nops + mov ecx,ebp + and cl,0xf + cmp cl,5 ;SEVL? + jnz .check_k + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + jmp ARM_store_instruction + .check_k: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_K + jz ERROR_requires_cpu_capability_arm_k + jmp ARM_store_instruction + .THUMB_nops: + mov ecx,ebp + and cl,0xf + cmp cl,5 ;SEVL? + jnz .THUMB_check_k + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + mov [thumb32_error],0 + mov [thumb16_error],0 + jmp .THUMB_version_okay + .THUMB_check_k: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + setz cl + movzx ecx,cl + neg ecx + and ecx,ERROR_requires_cpu_capability_arm_7m + mov [thumb32_error],ecx + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M + setz cl + movzx ecx,cl + neg ecx + and ecx,ERROR_requires_cpu_capability_arm_6m + mov [thumb16_error],ecx + .THUMB_version_okay: + mov eax,[thumb32_instruction] + and eax,0xf + shl eax,4 + or eax,0xbf00 + mov [thumb16_instruction],ax + jmp THUMB_post_process + +;DIV + +ARM_rd_rn_rm_DIV: + ;used by SDIV, UDIV + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg>,\ ;0=reg,reg alternate for reg,reg,reg + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;1=reg,reg,reg + cmp al,0 + jnz .encode + mov ax,word[operand_register0] + mov word[operand_register1],ax + .encode: + test [code_type],CPU_ACTIVITY_ARM + jnz .v7ve + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_DIV + jz ERROR_requires_cpu_capability_arm_div + mov cl,0x77 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + .v7ve: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE + jz ERROR_requires_cpu_capability_arm_ve + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.all + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.all + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,0xf + jz ERROR_r15_not_valid.all + shl eax,8 + or ebp,eax + jmp ARM_store_instruction + +;versionless + +ARM_und: + ;used by UND + call decode_template + TEMPLATE \ + <TMPL_imm>,\ ;0=imm + <TMPL_EOL> ;1=empty + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_und + mov eax,[immediate_value] + cmp eax,0xffff + ja ERROR_immediate_offset_out_of_range.0_0xffff + mov ecx,eax + and eax,0x000f + and ecx,0xfff0 + shl ecx,4 + or ebp,eax + or ebp,ecx + jmp ARM_store_instruction + .THUMB_und: + mov eax,[immediate_value] + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff + cmp eax,0xff + ja .T2 + mov ah,0xde + mov [thumb16_instruction],ax + mov [thumb16_error],0 + mov eax,[immediate_value] + .T2: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M + jz THUMB_post_process + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xfff + cmp eax,0xfff + ja THUMB_post_process + mov ecx,eax + mov edx,eax + and eax,0x00f + and ecx,0x0f0 + and edx,0xf00 + shl ecx,8-4 + shl edx,16-8 + or eax,ecx + or eax,edx + or [thumb32_instruction],eax + mov [thumb32_error],0 + jmp THUMB_post_process + +;FPA + +FPA_fn_fm: + ;used by CMF, CMFE, CNF, CNFE + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_fpa_freg>,\ ;0=fn,fm + <TMPL_fpa_freg,TMPL_imm_float> ;1=fn,const + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx ecx,[operand_register0] ;fn + shl ecx,16 + or ebp,ecx + cmp al,1 + jz FPA_encode_constant + movzx ecx,[operand_register1] ;fm + or ebp,ecx + jmp ARM_post_process_copro + +FPA_rd: + ;used by RFC, RFS, WFC, WFS + call decode_template + TEMPLATE \ + <TMPL_base_reg> ;0=rd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx eax,[operand_register0] ;rd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +FPA_fd_fn_fm: + ;used by ADFD, ADFDM, ADFDP, ADFDZ, ADFE, ADFEM, ADFEP, ADFEZ, ADFS, ADFSM, ADFSP, ADFSZ, + ; DVFD, DVFDM, DVFDP, DVFDZ, DVFE, DVFEM, DVFEP, DVFEZ, DVFS, DVFSM, DVFSP, DVFSZ, + ; FDVD, FDVDM, FDVDP, FDVDZ, FDVE, FDVEM, FDVEP, FDVEZ, FDVS, FDVSM, FDVSP, FDVSZ, + ; FMLD, FMLDM, FMLDP, FMLDZ, FMLE, FMLEM, FMLEP, FMLEZ, FMLS, FMLSM, FMLSP, FMLSZ, + ; FRDD, FRDDM, FRDDP, FRDDZ, FRDE, FRDEM, FRDEP, FRDEZ, FRDS, FRDSM, FRDSP, FRDSZ, + ; MUFD, MUFDM, MUFDP, MUFDZ, MUFE, MUFEM, MUFEP, MUFEZ, MUFS, MUFSM, MUFSP, MUFSZ, + ; POLD, POLDM, POLDP, POLDZ, POLE, POLEM, POLEP, POLEZ, POLS, POLSM, POLSP, POLSZ, + ; POWD, POWDM, POWDP, POWDZ, POWE, POWEM, POWEP, POWEZ, POWS, POWSM, POWSP, POWSZ, + ; RDFD, RDFDM, RDFDP, RDFDZ, RDFE, RDFEM, RDFEP, RDFEZ, RDFS, RDFSM, RDFSP, RDFSZ, + ; RMFD, RMFDM, RMFDP, RMFDZ, RMFE, RMFEM, RMFEP, RMFEZ, RMFS, RMFSM, RMFSP, RMFSZ, + ; RPWD, RPWDM, RPWDP, RPWDZ, RPWE, RPWEM, RPWEP, RPWEZ, RPWS, RPWSM, RPWSP, RPWSZ, + ; RSFD, RSFDM, RSFDP, RSFDZ, RSFE, RSFEM, RSFEP, RSFEZ, RSFS, RSFSM, RSFSP, RSFSZ, + ; SUFD, SUFDM, SUFDP, SUFDZ, SUFE, SUFEM, SUFEP, SUFEZ, SUFS, SUFSM, SUFSP, SUFSZ + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_fpa_freg,TMPL_fpa_freg>,\ ;0=fd,fn,fm + <TMPL_fpa_freg,TMPL_fpa_freg,TMPL_imm_float> ;1=fd,fn,const + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx ecx,[operand_register0] ;fd + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;fn + shl ecx,16 + or ebp,ecx + cmp al,1 + jz FPA_encode_constant + movzx ecx,[operand_register2] ;fm + or ebp,ecx + jmp ARM_post_process_copro + +FPA_fn_rd: + ;used by FLTD, FLTDM, FLTDP, FLTDZ, FLTE, FLTEM, FLTEP, FLTEZ, FLTS, FLTSM, FLTSP, FLTSZ + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_base_reg> ;0=fn,rd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx eax,[operand_register0] ;fn + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +FPA_fd_imm_address5: + ;used by LFM, SFM + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=fd,imm2,[rn] + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=fd,imm2,[rn],imm + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ;2=fd,imm2,[rn],{imm} + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;3=fd,imm2,[rn,imm] + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\;4=fd,imm2,[rn,imm]! + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;5=fd,imm2,[imm] PC relative + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;6=fd,imm2,[exp] implicit reg from structure + <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;7=fd,imm2,[exp]! implicit reg from structure + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V2 + jz ERROR_requires_copro_capability_fpa_v2 + mov ecx,[immediate_value2] + dec ecx + cmp ecx,4 + ja ERROR_count_value_out_of_range.1_4 + inc ecx + and ecx,3 + mov edx,ecx + and ecx,1 + and edx,2 + shl ecx,15 + shl edx,22-1 + or ebp,ecx + or ebp,edx + mov ecx,[operand_registers] + shl ecx,8 + mov [operand_registers],ecx + jmp ARM_copro_crd_address5.version_check_okay + +FPA_fd_imm_rn: + ;used by LFMEA, LFMFD, SFMEA, SFMFD + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_imm,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=fd,imm,[rn] + <TMPL_fpa_freg,TMPL_imm,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_modifier_exclaim> ;1=fd,imm,[rn]! + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V2 + jz ERROR_requires_copro_capability_fpa_v2 + movzx eax,al + shl eax,21 + or ebp,eax ;set W bit + movzx eax,[operand_register0] ;fd + shl eax,12 + or ebp,eax + mov ecx,[immediate_value] + dec ecx + cmp ecx,4 + ja ERROR_count_value_out_of_range.1_4 + inc ecx + and ecx,3 + mov edx,ecx + and ecx,1 + and edx,2 + shl ecx,15 + shl edx,22-1 + or ebp,ecx + or ebp,edx + movzx eax,[operand_register1] ;rn + test ebp,1 shl 21 ;W? + jz .rn_okay + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.third + .rn_okay: + shl eax,16 + or ebp,eax + mov ecx,ebp + and ecx,1 shl 24 + 1 shl 23 + 1 shl 21 ;P, U, W + cmp ecx,0 shl 24 + 1 shl 23 + 0 shl 21 ;0, 1, 0 + jz ARM_post_process_copro + mov ecx,[immediate_value] + imul ecx,3 + or ebp,ecx ;set the offset field + jmp ARM_post_process_copro + +FPA_fd_address5: + ;used by LDFD, LDFE, LDFP, LDFS, STFD, STFE, STFP, STFS + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=fd,[rn] + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=fd,[rn],imm + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ;2=fd,[rn],{imm} + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;3=fd,[rn,imm] + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;4=fd,[rn,imm]! + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;5=fd,[imm] PC relative + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;6=fd,[exp] implicit reg from structure + <TMPL_fpa_freg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;7=fd,[exp]! implicit reg from structure + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + mov ecx,[operand_registers] + shl ecx,8 + mov [operand_registers],ecx + jmp ARM_copro_crd_address5.version_check_okay + +FPA_fd_fm: + ;used by ABSD, ABSDM, ABSDP, ABSDZ, ABSE, ABSEM, ABSEP, ABSEZ, ABSS, ABSSM, ABSSP, ABSSZ, + ; ACSD, ACSDM, ACSDP, ACSDZ, ACSE, ACSEM, ACSEP, ACSEZ, ACSS, ACSSM, ACSSP, ACSSZ, + ; ASND, ASNDM, ASNDP, ASNDZ, ASNE, ASNEM, ASNEP, ASNEZ, ASNS, ASNSM, ASNSP, ASNSZ, + ; ATND, ATNDM, ATNDP, ATNDZ, ATNE, ATNEM, ATNEP, ATNEZ, ATNS, ATNSM, ATNSP, ATNSZ, + ; COSD, COSDM, COSDP, COSDZ, COSE, COSEM, COSEP, COSEZ, COSS, COSSM, COSSP, COSSZ, + ; EXPD, EXPDM, EXPDP, EXPDZ, EXPE, EXPEM, EXPEP, EXPEZ, EXPS, EXPSM, EXPSP, EXPSZ, + ; LGND, LGNDM, LGNDP, LGNDZ, LGNE, LGNEM, LGNEP, LGNEZ, LGNS, LGNSM, LGNSP, LGNSZ, + ; LOGD, LOGDM, LOGDP, LOGDZ, LOGE, LOGEM, LOGEP, LOGEZ, LOGS, LOGSM, LOGSP, LOGSZ, + ; MNFD, MNFDM, MNFDP, MNFDZ, MNFE, MNFEM, MNFEP, MNFEZ, MNFS, MNFSM, MNFSP, MNFSZ, + ; MVFD, MVFDM, MVFDP, MVFDZ, MVFE, MVFEM, MVFEP, MVFEZ, MVFS, MVFSM, MVFSP, MVFSZ, + ; NRMD, NRMDM, NRMDP, NRMDZ, NRME, NRMEM, NRMEP, NRMEZ, NRMS, NRMSM, NRMSP, NRMSZ, + ; RNDD, RNDDM, RNDDP, RNDDZ, RNDE, RNDEM, RNDEP, RNDEZ, RNDS, RNDSM, RNDSP, RNDSZ, + ; SIND, SINDM, SINDP, SINDZ, SINE, SINEM, SINEP, SINEZ, SINS, SINSM, SINSP, SINSZ, + ; SQTD, SQTDM, SQTDP, SQTDZ, SQTE, SQTEM, SQTEP, SQTEZ, SQTS, SQTSM, SQTSP, SQTSZ, + ; TAND, TANDM, TANDP, TANDZ, TANE, TANEM, TANEP, TANEZ, TANS, TANSM, TANSP, TANSZ, + ; URDD, URDDM, URDDP, URDDZ, URDE, URDEM, URDEP, URDEZ, URDS, URDSM, URDSP, URDSZ + call decode_template + TEMPLATE \ + <TMPL_fpa_freg,TMPL_fpa_freg>,\ ;0=fd,fm + <TMPL_fpa_freg,TMPL_imm_float> ;1=fd,const + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx ecx,[operand_register0] ;fd + shl ecx,12 + or ebp,ecx + cmp al,1 + jz FPA_encode_constant + movzx ecx,[operand_register1] ;fm + or ebp,ecx + jmp ARM_post_process_copro + +FPA_rd_fm: + ;used by FIX, FIXM, FIXP, FIXZ + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_fpa_freg> ;0=rd,fm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1 + jz ERROR_requires_copro_capability_fpa_v1 + movzx ecx,[operand_register0] ;rd + shl ecx,12 + or ebp,ecx + movzx ecx,[operand_register1] ;fm + or ebp,ecx + jmp ARM_post_process_copro + + align 4 +FPA_constants: + dd 0.0 + dd 1.0 + dd 2.0 + dd 3.0 + dd 4.0 + dd 5.0 + dd 0.5 + dd 10.0 + +FPA_encode_constant: + mov eax,[immediate_value] + mov ecx,FPA_constants + mov edx,8 + .find_constant: + dec edx + js .not_found + cmp eax,[ecx+edx*4] + jnz .find_constant + lea eax,[edx+8] + or ebp,eax + jmp ARM_post_process_copro + .not_found: + mov ecx,ERROR_constant_cannot_be_encoded + jmp ARM_post_process_copro_with_error + +;MAVERICK + +MAVERICK_crd_crn: + ;used by CFABS32, CFABS64, CFABSS, CFABSD, CFCPYS, CFCPYD, CFCVT32S, CFCVT32D, CFCVT64S, CFCVT64D, CFCVTD32, + ; CFCVTDS, CFCVTS32, CFCVTSD, CFNEG32, CFNEG64, CFNEGS, CFNEGD, CFTRUNCS32, CFTRUNCD32 + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_cpro_reg> ;0=crd,crn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crd_crn_crm: + ;used by CFADD32, CFADD64, CFADDD, CFADDS, CFMAC32, CFMSC32, CFMUL32, CFMUL64, CFMULS, CFMULD, + ; CFSUB32, CFSUB64, CFSUBD, CFSUBS + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg> ;0=crd,crn,crm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;crm + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_rd_crn_crm: + ;used by CFCMP32, CFCMP64, CFCMPS, CFCMPD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg> ;0=rd,crn,crm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;rd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;crm + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crd_address5: + ;used by CFLDR32, CFLDR64, CFLDRS, CFLDRD, CFSTR32, CFSTR64, CFSTRS, CFSTRD + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=crd,[rn] + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=crd,[rn],imm + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ;2=crd,[rn],{imm} + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;3=crd,[rn,imm] + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;4=crd,[rn,imm]! + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;5=crd,[imm] PC relative + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;6=crd,[exp] implicit reg from structure + <TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;7=crd,[exp]! implicit reg from structure + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + mov ecx,[operand_registers] + shl ecx,8 + mov [operand_registers],ecx + jmp ARM_copro_crd_address5.version_check_okay + +MAVERICK_aa_crd_crn_crm: + ;used by CFMADD32, CFMSUB32 + call decode_template + TEMPLATE \ + <TMPL_mvrk_areg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg> ;0=aa,crd,crn,crm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;aa + shl eax,5 + or ebp,eax + movzx eax,[operand_register1] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;crm + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_aa_ad_crn_crm: + ;used by CFMADDA32, CFMSUBA32 + call decode_template + TEMPLATE \ + <TMPL_mvrk_areg,TMPL_mvrk_areg,TMPL_cpro_reg,TMPL_cpro_reg> ;0=aa,ad,crn,crm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;aa + shl eax,5 + or ebp,eax + movzx eax,[operand_register1] ;ad + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;crm + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crd_an: + ;used by CFMV32A, CFMV32AH, CFMV32AL, CFMV32AM, CFMV64A + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_mvrk_areg> ;0=crd,an + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;an + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crd_psc: + ;used by CFMV32SC + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_mvrk_psc> ;0=crd,psc + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_psc_crd: + ;used by CFMVSC32 + call decode_template + TEMPLATE \ + <TMPL_mvrk_psc,TMPL_cpro_reg> ;0=psc,crd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crn_rd: + ;used by CFMV64HR, CFMV64LR, CFMVDHR, CFMVDLR, CFMVSR + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_base_reg> ;0=crn,rd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_ad_crn: + ;used by CFMVA32, CFMVA64, CFMVAH32, CFMVAL32, CFMVAM32 + call decode_template + TEMPLATE \ + <TMPL_mvrk_areg,TMPL_cpro_reg> ;0=ad,crn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;ad + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_rd_crn: + ;used by CFMVR64H, CFMVR64L, CFMVRDH, CFMVRDL, CFMVRS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_cpro_reg> ;0=rd,crn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;rd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crm_crn_rd: + ;used by CFRSHL32, CFRSHL64 + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_base_reg> ;0=crm,crn,rd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crm + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rd + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +MAVERICK_crd_crn_imm: + ;used by CFSH32, CFSH64 + call decode_template + TEMPLATE \ + <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_imm> ;0=crm,crn,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK + jz ERROR_requires_copro_capability_maverick + movzx eax,[operand_register0] ;crd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;crn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] ;imm + cmp eax,-64 + jl .out_of_range + cmp eax,63 + jg .out_of_range + mov ecx,eax + and eax,0x0f + and ecx,0x70 + shl ecx,1 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.m64_63 + jmp ARM_post_process_copro_with_error + +;vfp1 + +VFP_sd_sn_sm: + ;used by FMULS, FNMULS, FADDS, FSUBS, FDIVS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;0=sdn,sm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;1=sd,sn,sm + .v1xd_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + .do: + cmp al,0 + jnz .registers_shifted + mov eax,[operand_registers] + mov cl,al + shl eax,8 + mov al,cl + mov [operand_registers],eax + .registers_shifted: + movzx eax,[operand_register0] ;fd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;fn + xor ecx,ecx + shr eax,1 + setc cl + shl eax,16 + shl ecx,7 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register2] ;fm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + +VFP_dd_dn_dm: + ;used by FMULD, FNMULD, FADDD, FSUBD, FDIVD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;1=dd,dn,dm + .begin: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sn_sm.do + mov edx,[operand_registers] ;fd,fn,fm + test edx,0x010101 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sn_sm.do + +VFP_sd_sm: + ;used by FABSS, FCPYS, FNEGS, FSITOS, FSQRTS, FTOSIS, FTOSIZS, FTOUIS, FTOUIZS, FUITOS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sm + .v1xd_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + .do: + movzx eax,[operand_register0] ;fd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;fm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + +VFP_dd_dm: + ;used by FABSD, FCPYD, FNEGD, FSQRTD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=dd,dm + .encode: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sm.do + mov edx,[operand_registers] ;fd,fm + test edx,0x0101 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sm.do + +VFP_sd_sm_zero: + ;used by FCMPS, FCMPES + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;0=sd,sm + <TMPL_vfps_reg,TMPL_imm> ;1=sd,0.0 + test al,al + jz VFP_sd_sm.v1xd_test + cmp [immediate_value],0 + mov ecx,ERROR_immediate_offset_out_of_range.0 + jnz ARM_post_process_copro_with_error + or ebp,1 shl 16 ;set for FCMP(E)Z + jmp VFP_sd_sm.v1xd_test + +VFP_dd_dm_zero: + ;used by FCMPD, FCMPED + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,0.0 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + test al,al + jnz .zero + .check_d32: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sm.do + mov edx,[operand_registers] ;fd,fm + test edx,0x0101 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sm.do + .zero: + cmp [immediate_value],0 + mov ecx,ERROR_immediate_offset_out_of_range.0 + jnz ARM_post_process_copro_with_error + or ebp,1 shl 16 ;set for FCMP(E)Z + jmp .check_d32 + +VFP_sd: + ;used by FCMPZS, FCMPEZS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg> ;0=sd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1 + mov [operand_register1],0 ;fm + jmp VFP_sd_sm.do + +VFP_dd: + ;used by FCMPZD, FCMPEZD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg> ;0=dd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + mov [operand_register1],0 ;fm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sm.do + mov edx,[operand_registers] ;fd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sm.do + +VFP_dd_sm: + ;used by FCVTDS, FSITOD, FUITOD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfps_reg> ;0=dd,sm + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sm.do + mov edx,[operand_registers] ;fd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sm.do + +VFP_sd_dm: + ;used by FCVTSD, FTOSID, FTOSIZD, FTOUID, FTOUIZD + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfpd_reg> ;0=sd,dm + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1 + jz ERROR_requires_copro_capability_vfp_v1 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_sm.do + mov edx,[operand_registers] ;fm + test edx,0x0100 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_sm.do + +VFP_sd_sm_HP: + ;used by VCVTB, VCVTT + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_HP + jz ERROR_requires_copro_capability_vfp_hp + jmp VFP_sd_sm.do + +VFP_sd_rn_offset: + ;used by FLDS, FSTS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=sd,[rn] + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=sd,[rn,imm] + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;2=sd,[imm] PC relative + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;3=sd,[exp] implicit reg from structure + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + cmp al,0 + jz .fd_q_rn_p + cmp al,1 + jz .fd_q_rn_imm_p + cmp al,2 + jz .fd_q_imm_p + cmp al,3 + jz .fd_q_exp_p + ud2 + .fd_q_imm_p: + mov [operand_register1],0xf + call THUMB_query_condition_pc + mov eax,[addressing_space] + sub ecx,[eax+0x00] + and ecx,not 3 ;round down + neg ecx + add ecx,[immediate_value] + test [code_type],CPU_ACTIVITY_ARM + setnz al + movzx eax,al + shl eax,2 + add eax,4 ;offset=4 for THUMB and 8 for ARM + sub ecx,eax + mov [immediate_value],ecx + .fd_q_exp_p: + .fd_q_rn_p: + .fd_q_rn_imm_p: + or ebp,1 shl 23 + mov eax,[immediate_value] + test eax,eax + jns .positive_imm + and ebp,not (1 shl 23) + neg eax + .positive_imm: + test eax,3 + jnz .out_of_range + shr eax,2 + cmp eax,0xff + ja .out_of_range + or ebp,eax + movzx eax,[operand_register0] ;fd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0x3fc + jmp ARM_post_process_copro_with_error + +VFP_dd_rn_offset: + ;used by FLDD, FSTD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=dd,[rn] + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=dd,[rn,imm] + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;2=dd,[imm] PC relative + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;3=dd,[exp] implicit reg from structure + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_sd_rn_offset.do + mov edx,[operand_registers] ;fd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_sd_rn_offset.do + +VFP_rn_list_s: + ;used by FLDMIAS, FLDMDBS, FSTMIAS, FSTMDBS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfp_reg_list_s>,\ ;0=rn,{..} + <TMPL_base_reg!,TMPL_vfp_reg_list_s> ;1=rn!,{..} + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + cmp al,1 ;writeback? + jnz .rn_okay + cmp [operand_register0],15 ;PC? + jz ERROR_r15_not_valid.first + or ebp,1 shl 21 + .rn_okay: + mov eax,ebp + and eax,1 shl 24 + 1 shl 21 ;isolate P and W + xor eax,1 shl 24 ;P=!P + jz ERROR_must_have_writeback_operator ;P=1 & W=0 is FLD/FST, not valid + mov edx,[reg_list_bitmap] + bsf eax,edx + bsr ecx,edx + ;check for a contiguous set + xor ecx,31 + shl edx,cl + add ecx,eax + sar edx,cl + inc edx + jnz ERROR_non_contiguous_set + mov ecx,[reg_list_bitmap] + bsf eax,ecx ;eax=start register + bsr edx,ecx + sub edx,eax + inc edx ;edx=register count + test ebp,1 shl 8 ;FLDMD? + jz .encode + cmp edx,16 + ja ERROR_large_set + ;double everything + add eax,eax + add edx,edx + ;shift high bit to LSb + mov ah,al + shr ah,5 + and ax,0x011e + or al,ah + movzx eax,al + .encode: + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,eax + or ebp,ecx + or ebp,edx + movzx eax,[operand_register0] ;rn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +VFP_rn_list_d: + ;used by FLDMIAD, FLDMDBD, FLDMIAX, FLDMDBX, FSTMIAD, FSTMDBD, FSTMIAX, FSTMDBX + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfp_reg_list_d>,\ ;0=rn,{..} + <TMPL_base_reg!,TMPL_vfp_reg_list_d> ;1=rn!,{..} + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz VFP_rn_list_s.do + mov edx,[reg_list_bitmap] + test edx,0xffff0000 + jnz ERROR_requires_copro_capability_vfp_d32 + jmp VFP_rn_list_s.do + +VFP_dn_rd: + ;used by FMDHR, FMDLR + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_base_reg> ;0=dn,rd + .test_version: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + movzx eax,[operand_register0] ;dn + xor ecx,ecx + shr eax,1 + setc cl + shl eax,16 + shl ecx,7 + or ebp,ecx + or ebp,eax + movzx eax,[operand_register1] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +VFP_rd_dn: + ;used by FMRDH, FMRDL + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfpd_reg> ;0=rd,dn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x0100 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + .encode: + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + and eax,0xf + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;dn + xor ecx,ecx + shr eax,1 + setc cl + shl eax,16 + shl ecx,7 + or ebp,ecx + or ebp,eax + jmp ARM_post_process_copro + +VFP_rd_sn: + ;used by FMRS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfps_reg> ;0=rd,sn + jmp VFP_rd_dn.do + +VFP_sn_rd: + ;used by FMSR + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_base_reg> ;0=sn,rd + .do: + mov ax,word[operand_register0] + xchg ah,al + mov word[operand_register0],ax + jmp VFP_rd_dn.do + +VFP_rd_sysreg: + ;used by FMRX, VMRS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfp_syst>,\ ;0=rd,sysreg + <TMPL_psr,TMPL_vfp_syst> ;0=apsr_nzcv,sysreg + cmp al,0 + mov ax,word[operand_registers+0] + jz .dest_okay + cmp al,34 ;apsr? + jnz ERROR_parameter_n_not_valid.first + mov al,0xf + .dest_okay: + shl ah,1 ;set sysreg encoding + cmp ah,1 shl 1 ;fpscr? + setz cl + shl cl,4 + or al,cl ;disable r15 check, r15 is okay here if reading fpscr + mov word[operand_registers+0],ax + jmp VFP_rd_dn.do + +VFP_sysreg_rd: + ;used by FMXR, VMSR + call decode_template + TEMPLATE \ + <TMPL_vfp_syst,TMPL_base_reg> ;0=sysreg,rd + mov ax,word[operand_registers+0] + xchg ah,al + shl ah,1 ;set sysreg encoding + mov word[operand_registers+0],ax + jmp VFP_rd_dn.do + +;vfp2 + +VFP_dm_rd_rn: + ;used by FMDRR + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_base_reg,TMPL_base_reg> ;0=dm,rd,rn + .test_version: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2 + jz ERROR_requires_copro_capability_vfp_v2 + movzx eax,[operand_register0] ;dm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,ecx + or ebp,eax + movzx eax,[operand_register1] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.third + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +VFP_rd_rn_dm: + ;used by FMRRD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_vfpd_reg> ;0=rd,rn,dm + .test_version: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x010000 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2 + jz ERROR_requires_copro_capability_vfp_v2 + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;dm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,ecx + or ebp,eax + jmp ARM_post_process_copro + +VFP_rd_rn_sm: + ;used by FMRRS + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_vfp_reg_list_s> ;0=rd,rn,{..} + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2 + jz ERROR_requires_copro_capability_vfp_v2 + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + mov ecx,[reg_list_bitmap] + bsf eax,ecx ;eax=start register + bsr edx,ecx + ;check for a 2 register set + dec edx + cmp edx,eax + jnz ERROR_two_registers_required + cmp eax,30 + ja ERROR_two_registers_required + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,ecx + or ebp,eax + jmp ARM_post_process_copro + +VFP_sm_rd_rn: + ;used by FMSRR + call decode_template + TEMPLATE \ + <TMPL_vfp_reg_list_s,TMPL_comma,TMPL_base_reg,TMPL_base_reg> ;0={..},rd,rn + jmp VFP_rd_rn_sm.do + +VFP_fmstat: + ;used by FMSTAT + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD + jz ERROR_requires_copro_capability_vfp_v1xd + jmp ARM_post_process_copro + +VFP_convert_single_to_quarter: + mov eax,[immediate_value] + mov ecx,eax + mov edx,eax + and eax,1 shl 23-1 ;eax=mantissa + shr ecx,23 + and ecx,0xff ;ecx=exponent + add eax,1 shl 18 + shr eax,19 + cmp eax,0xf + jbe .rounding_done + xor eax,eax + inc ecx + .rounding_done: + cmp cl,01111100b + jb .out_of_range + cmp cl,10000011b + ja .out_of_range + shr edx,31-7 + and edx,0x80 ;dl=sign + and ecx,7 + shl ecx,4 + or edx,ecx + or eax,edx + mov [immediate_value],eax + ret + .out_of_range: + or eax,-1 + mov [immediate_value],eax + ret + +VFP_dm_imm: + ;used by FCONSTD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm_float>,\ ;0=dd,float + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,imm + .vesion_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x01 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V3 + jz ERROR_requires_copro_capability_vfp_v3 + cmp al,1 + jz .constant_converted + call VFP_convert_single_to_quarter + .constant_converted: + movzx eax,[operand_register0] ;dd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,ecx + or ebp,eax + mov eax,[immediate_value] + cmp eax,0xff + ja .out_of_range + mov ecx,eax + and eax,0xf + and ecx,0xf0 + shl ecx,16-4 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0xff + jmp ARM_post_process_copro_with_error + +VFP_sm_imm: + ;used by FCONSTS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_imm_float>,\ ;0=sd,float + <TMPL_vfps_reg,TMPL_imm> ;1=sd,imm + jmp VFP_dm_imm.do + +VFP_dd_dd_imm: + ;used by FSHTOD, FSLTOD, FUHTOD, FULTOD, FTOSHD, FTOSLD, FTOUHD, FTOULD + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=dd,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm> ;1=dd,dd,imm + .test_version: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz .do + mov edx,[operand_registers] ;dd + test edx,0x0101 + jnz ERROR_requires_copro_capability_vfp_d32 + .do: + shr al,1 + jc .register_okay + mov cl,[operand_register0] + mov [operand_register1],cl + .register_okay: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V3 + jz ERROR_requires_copro_capability_vfp_v3 + movzx eax,word[operand_register0] ;dd,dd + cmp ah,al + jnz ERROR_dest_and_source_must_be_the_same + mov ah,0 + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,ecx + or ebp,eax + mov ecx,[immediate_value] + test ebp,1 shl 7 + jz .half + ;long + cmp ecx,1 + jb .out_of_range_long + cmp ecx,32 + ja .out_of_range_long + mov eax,32 + jmp .encode + .half: + cmp ecx,16 + ja .out_of_range_half + mov eax,16 + .encode: + sub eax,ecx + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,ecx + or ebp,eax + jmp ARM_post_process_copro + .out_of_range_long: + mov ecx,ERROR_immediate_value_out_of_range.1_32 + jmp ARM_post_process_copro_with_error + .out_of_range_half: + mov ecx,ERROR_immediate_value_out_of_range.0_16 + jmp ARM_post_process_copro_with_error + +VFP_sd_sd_imm: + ;used by FSHTOS, FSLTOS, FUHTOS, FULTOS, FTOSHS, FTOSLS, FTOUHS, FTOULS + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_imm>,\ ;0=sd,imm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_imm> ;1=sd,sd,imm + jmp VFP_dd_dd_imm.do + +;xScale + +XSCALE_acc_rm_rs: + ;used by MIA, MIAPH, MIABB, MIABT, MIATB, MIATT + call decode_template + TEMPLATE \ + <TMPL_acc_40bt,TMPL_base_reg,TMPL_base_reg> ;0=acc,rm,rs + test [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE + jz ERROR_requires_copro_capability_xscale + movzx eax,[operand_register0] ;acc + shl eax,5 + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.third + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +XSCALE_acc_rdlo_rdhi: + ;used by MAR + call decode_template + TEMPLATE \ + <TMPL_acc_40bt,TMPL_base_reg,TMPL_base_reg> ;0=acc,rdlo,rdhi + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE + jz ERROR_requires_copro_capability_xscale + movzx eax,[operand_register0] ;acc + or ebp,eax + movzx eax,[operand_register1] ;rm + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rs + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.third + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +XSCALE_rdlo_rdhi_acc: + ;used by MRA + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_acc_40bt> ;0=rdlo,rdhi,acc + test [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE + jz ERROR_requires_copro_capability_xscale + mov eax,[operand_registers] + mov ecx,eax + shl eax,8 + shr ecx,16 + mov al,cl + mov [operand_registers],eax + jmp XSCALE_acc_rdlo_rdhi.do + +;IWMMXT V1 + +IWMMXT_r15: + ;used by TANDCB, TANDCH, TANDCW, TORCB, TORCH, TORCW + call decode_template + TEMPLATE \ + <TMPL_base_reg> ;0=r15 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;r15 + cmp eax,15 ;PC? + jnz ERROR_must_be_r15.first + jmp ARM_post_process_copro + +IWMMXT_wrd_rn: + ;used by TBCSTB, TBCSTH, TBCSTW + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_base_reg> ;0=wrd,rn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_r15_imm: + ;used by TEXTRCB, TEXTRCH, TEXTRCW + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_imm> ;0=r15,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;r15 + cmp eax,15 ;PC? + jnz ERROR_must_be_r15.first + mov eax,[immediate_value] + cmp eax,7 + ja .out_of_range + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_7 + jmp ARM_post_process_copro_with_error + +IWMMXT_rd_wrn_imm: + ;used by TEXTRMSB, TEXTRMSH, TEXTRMSW, TEXTRMUB, TEXTRMUH, TEXTRMUW + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_iwmmx_wreg,TMPL_imm> ;0=rd,wrn,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + cmp eax,7 + ja .out_of_range + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_7 + jmp ARM_post_process_copro_with_error + +IWMMXT_wrd_rn_imm: + ;used by TINSRB, TINSRH, TINSRW + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_imm> ;0=wrd,rn,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,12 + or ebp,eax + mov eax,[immediate_value] + cmp eax,7 + ja .out_of_range + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_7 + jmp ARM_post_process_copro_with_error + +IWMMXT_wcd_rn: + ;used by TMCR + call decode_template + TEMPLATE \ + <TMPL_iwmmx_creg,TMPL_base_reg> ;0=wcd,rn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wcd + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_rdlo_rdhi: + ;used by TMCRR + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_base_reg> ;0=wrd,rdlo,rdhi + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + or ebp,eax + movzx eax,[operand_register1] ;rdlo + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] ;rdhi + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_rm_rs: + ;used by TMIA, TMIAPH, TMIAxy + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_base_reg> ;0=wrd,rm,rs + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,5 + or ebp,eax + movzx eax,[operand_register1] ;rm + or ebp,eax + movzx eax,[operand_register2] ;rs + shl eax,12 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_rd_wrn: + ;used by TMOVMSKB, TMOVMSKH, TMOVMSKW + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_iwmmx_wreg> ;0=rd,wrn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_rd_wcn: + ;used by TMRC + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_iwmmx_creg> ;0=rd,wcn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;rd + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wcn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_rdlo_rdhi_wrn: + ;used by TMRRC + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_iwmmx_wreg> ;0=rdlo,rdhi,wrn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,word[operand_register0] + cmp ah,al + jz ERROR_destination_registers_must_differ + movzx eax,[operand_register0] ;rdlo + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rdhi + cmp eax,15 ;PC? + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrn + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn: + ;used by WACCB, WACCH, WACCW, WUNPCKEHUB, WUNPCKEHUH, WUNPCKEHUW, WUNPCKEHSB, WUNPCKEHSH, WUNPCKEHSW + ; WUNPCKELUB, WUNPCKELUH, WUNPCKELUW, WUNPCKELSB, WUNPCKELSH, WUNPCKELSW + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg> ;0=wrd,wrn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn_wrm: + ;used by WADDB, WADDH, WADDW, WADDBSS, WADDHSS, WADDWSS, WADDBUS, WADDHUS, WADDWUS, + ; WALIGNR0, WALIGNR1, WALIGNR2, WALIGNR3, WAND, WANDN, WAVG2B, WAVG2H, WAVG2BR, WAVG2HR, + ; WCMPEQB, WCMPEQH, WCMPEQW, WCMPGTSB, WCMPGTSH, WCMPGTSW, WCMPGTUB, WCMPGTUH, WCMPGTUW, + ; WMACS, WMACU, WMACSZ, WMACUZ, WMADDU, WMADDS, WMAXUB, WMAXUH, WMAXUW, WMAXSB, WMAXSH, WMAXSW, + ; WMINUB, WMINUH, WMINUW, WMINSB, WMINSH, WMINSW, WMULSM, WMULSL, WMULUM, WMULUL, + ; WPACKDSS, WPACKDUS, WPACKHSS, WPACKHUS, WPACKWSS, WPACKWUS, WSADB, WSADH, WSADBZ, WSADHZ, + ; WSUBB, WSUBH, WSUBW, WSUBBSS, WSUBHSS, WSUBWSS, WSUBBUS, WSUBHUS, WSUBWUS, + ; WUNPCKIHB, WUNPCKIHH, WUNPCKIHW, WUNPCKILB, WUNPCKILH, WUNPCKILW, WXOR + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg> ;0=wrd,wrn,wrm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrm + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn_wrm_imm: + ;used by WALIGNI + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm> ;0=wrd,wrn,wrm,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrm + or ebp,eax + mov eax,[immediate_value] + cmp eax,7 + ja .out_of_range + shl eax,20 + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_7 + jmp ARM_post_process_copro_with_error + +IWMMXT_wrd_address5: + ;used by WLDRB, WLDRH, WLDRW, WSTRB, WSTRH, WSTRW + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 0=wrd,[rn] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=wrd,[rn],imm + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ; 2=wrd,[rn],{imm} + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 3=wrd,[rn,imm] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 4=wrd,[rn,imm]! + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ; 5=wrd,[imm] PC relative + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 6=wrd,[exp] implicit reg from structure + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 7=wrd,[exp]! implicit reg from structure + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 8=crd,[rn] + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 9=crd,[rn],imm + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ;10=crd,[rn],{imm} + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;11=crd,[rn,imm] + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;12=crd,[rn,imm]! + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;13=crd,[imm] PC relative + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;14=crd,[exp] implicit reg from structure + <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;15=crd,[exp]! implicit reg from structure + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + cmp al,8 ;wcr? + jb .wcr_okay + ;check for W mode + mov ecx,ebp + and ecx,1 shl 22 + 1 shl 8 + cmp ecx,1 shl 8 + jnz ERROR_control_register_only_valid_with_word + sub al,8 + or ebp,0xf shl 28 + .wcr_okay: + cmp al,5 ;wrd,[imm]? + jnz .offset_okay + mov [operand_register1],0xf + call THUMB_query_condition_pc + mov eax,[addressing_space] + sub ecx,[eax+0x00] + and ecx,not 3 ;round down + neg ecx + add ecx,[immediate_value] + test [code_type],CPU_ACTIVITY_ARM + setnz al + movzx eax,al + shl eax,2 + add eax,4 ;offset=4 for THUMB and 8 for ARM + sub ecx,eax + mov [immediate_value],ecx + mov eax,3 ;wrd,[rn,imm] + .offset_okay: + test ebp,1 shl 8 ;WLDRB/WLDRH? + jnz .imm_adjusted + cmp al,2 ;option? + jz .imm_adjusted + shl [immediate_value],2 + .imm_adjusted: + mov ecx,[operand_registers] + shl ecx,8 + mov [operand_registers],ecx + jmp ARM_copro_crd_address5.version_check_okay + +IWMMXT_wrd_wrn_WMOV: + ;used by WMOV + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg> ;0=wrd,wrn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + or ebp,eax + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn_wcm: + ;used by WRORHG, WRORWG, WRORDG, WSLLHG, WSLLWG, WSLLDG, WSRAHG, WSRAWG, WSRADG, WSRLHG, WSRLWG, WSRLDG + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_creg> ;0=wrd,wrn,wcm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wcm + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn_imm: + ;used by WSHUFH + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm> ;0=wrd,wrn,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + cmp eax,0xff + ja .out_of_range + mov ecx,eax + and eax,0xf + and ecx,0xf0 + shl ecx,20-4 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_0xff + jmp ARM_post_process_copro_with_error + +IWMMXT_wrd: + ;used by WZERO + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg> ;0=wrd + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + or ebp,eax + shl eax,12 + or ebp,eax + shl eax,4 + or ebp,eax + jmp ARM_post_process_copro + +;IWMMXT V2 + +IWMMXT_r15_v2: + ;used by TORVSCB, TORVSCH, TORVSCW + call decode_template + TEMPLATE \ + <TMPL_base_reg> ;0=r15 + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + movzx eax,[operand_register0] ;r15 + cmp eax,15 ;PC? + jnz ERROR_must_be_r15.first + jmp ARM_post_process_copro + +IWMMXT_rd_rn_rm_imm: + ;used by WMERGE + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm> ;0=wrd,wrn,wrm,imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrm + or ebp,eax + mov eax,[immediate_value] + cmp eax,7 + ja .out_of_range + shl eax,21 + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_7 + jmp ARM_post_process_copro_with_error + +IWMMXT_rd_rn_v2: + ;used by WABSB, WABSH, WABSW + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg> ;0=wrd,wrn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_rd_rn_rm_v2: + ;used by WABSDIFFB, WABSDIFFH, WABSDIFFW, WADDBHUSL, WADDBHUSM, WADDHC, WADDSUBHX, WADDWC, + ; WAVG4, WAVG4R, WMADDSN, WMADDSX, WMADDUN, WMADDUX, WMIABB, WMIABBN, WMIABT, WMIABTN, + ; WMIATB, WMIATBN, WMIATT, WMIATTN, WMIAWBB, WMIAWBBN, WMIAWBT, WMIAWBTN, WMIAWTB, + ; WMIAWTBN, WMIAWTT, WMIAWTTN, WMULSMR, WMULUMR, WMULWL, WMULWSM, WMULWSMR, WMULWUM, + ; WMULWUMR, WQMIABB, WQMIABBN, WQMIABT, WQMIABTN, WQMIATB, WQMIATBN, WQMIATT, WQMIATTN, + ; WQMULM, WQMULMR, WQMULWM, WQMULWMR, WSUBADDHX + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg> ;0=wrd,wrn,wrm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrm + or ebp,eax + jmp ARM_post_process_copro + +IWMMXT_wrd_wrn_param: + ;used by WSLLH, WSLLW, WSLLD, WSRAH, WSRAW, WSRAD, WSRLH, WSRLW, WSRLD, WRORH, WRORW, WRORD + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>,\ ;0=wrd,wrn,wrm + <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm> ;1=wrd,wrn,imm + cmp al,1 + jz .wrd_wrn_imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1 + jz ERROR_requires_copro_capability_iwmmxt_v1 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;wrm + or ebp,eax + jmp ARM_post_process_copro + .wrd_wrn_imm: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + or ebp,0xf shl 28 + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;wrn + shl eax,16 + or ebp,eax + mov eax,[immediate_value] + cmp eax,32 + ja .out_of_range + cmp eax,0 + jz .shift_0 + mov ecx,eax + and ecx,0x10 + and eax,0x0f + shl ecx,8-4 + or ebp,eax + or ebp,ecx + jmp ARM_post_process_copro + .shift_0: + or ebp,3 shl 20 ;force to WROR + mov ecx,ebp + and ecx,3 shl 22 + cmp ecx,1 shl 22 ;H? + jz .shift_0_H + cmp ecx,2 shl 22 ;W? + jz ARM_post_process_copro ;WRORW wrd,wrn,32 + ;shift 0 D + and ebp,not (0x10f00ff0) ;force to WOR + movzx eax,[operand_register1] ;wrn + or ebp,eax ;WOR wrd,wrn,wrn + jmp ARM_post_process_copro + .shift_0_H: + or ebp,1 shl 8 ;WRORH wrd,wrn,16 + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.0_32 + jmp ARM_post_process_copro_with_error + +IWMMXT_wrd_address5_reg_offset_translate: + db 0 ;0 0=wrd,[rn] + db -1 ;1 + db -1 ;2 + db 1 ;3 1=wrd,[rn],imm + db 2 ;4 2=wrd,[rn],{imm} + db 3 ;5 3=wrd,[rn,imm] + db 4 ;6 4=wrd,[rn,imm]! + db -1 ;7 + db -1 ;8 + db -1 ;9 + db -1 ;10 + db 5 ;11 5=wrd,[imm] PC relative + db 6 ;12 6=wrd,[exp] implicit reg from structure + db 7 ;13 7=wrd,[exp]! implicit reg from structure + +IWMMXT_wrd_address5_reg_offset: + ;used by WLDRD, WSTRD + call decode_template + TEMPLATE \ + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ; 0=wrd,[rn] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\ ; 1=wrd,[rn],+-rm + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\ ; 2=wrd,[rn],+-rm,lsl imm + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\ ; 3=wrd,[rn],imm + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\ ; 4=wrd,[rn],{imm} + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ; 5=wrd,[rn,imm] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 6=wrd,[rn,imm]! + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\ ; 7=wrd,[rn,+-rm] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 8=wrd,[rn,+-rm]! + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\ ; 9=wrd,[rn,+-rm,lsl imm] + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;10=wrd,[rn,+-rm,lsl imm]! + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;11=wrd,[imm] PC relative + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=wrd,[exp] implicit reg from structure + <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;13=wrd,[exp]! implicit reg from structure + mov cl,al + movzx eax,al + mov al,[eax+IWMMXT_wrd_address5_reg_offset_translate] + cmp al,-1 + jnz IWMMXT_wrd_address5.do + test [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2 + jz ERROR_requires_copro_capability_iwmmxt_v2 + or ebp,0xf shl 28 + mov al,[operand_register2] ;rm + movzx edx,al + not edx + and edx,0x80 ;get '+' state + shl edx,23-7 + or ebp,edx ;set U if '+' + and al,0xf + cmp al,0xf + jz ERROR_r15_not_valid.third + mov [operand_register2],al ;rm + mov eax,[immediate_value] + cmp eax,15 + ja .out_of_range + cmp cl,1 + jz .wrd_q_rn_p_PMrm + cmp cl,2 + jz .wrd_q_rn_p_PMrm_lsl_imm + cmp cl,7 + jz .wrd_q_rn_PMrm_p + cmp cl,8 + jz .wrd_q_rn_PMrm_p! + cmp cl,9 + jz .wrd_q_rn_PMrm_lsl_imm_p + cmp cl,10 + jz .wrd_q_rn_PMrm_lsl_imm_p! + ud2 + .wrd_q_rn_p_PMrm_lsl_imm: + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz ERROR_shift_type_must_be_LSL + .wrd_q_rn_p_PMrm: + or ebp,1 shl 21 ;set W + jmp .encode + .wrd_q_rn_PMrm_lsl_imm_p!: + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz ERROR_shift_type_must_be_LSL + .wrd_q_rn_PMrm_p!: + or ebp,1 shl 21 + 1 shl 24 ;set W & P + jmp .encode + .wrd_q_rn_PMrm_lsl_imm_p: + cmp [instruction_shift_op],ARM_SHIFT_OPCODE_LSL + jnz ERROR_shift_type_must_be_LSL + .wrd_q_rn_PMrm_p: + or ebp,1 shl 24 ;set P + .encode: + movzx eax,[operand_register0] ;wrd + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + or ebp,eax + mov eax,[immediate_value] + shl eax,4 + or ebp,eax + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.0_15 + jmp ARM_post_process_copro_with_error + +;SIMD + +SIMD_INT_vd_vn_vm: + ;used by VABA.S16, VABA.S32, VABA.S8, VABA.U16, VABA.U32, VABA.U8, + ; VMLA.S8, VMLA.U8, VMLA.I8, VMLS.S8, VMLS.U8, VMLS.I8 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;1=qd,qn,qm + .int_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + .encode: + movzx eax,al + shl eax,6 + or ebp,eax ;set Q bit + movzx eax,[operand_register0] ;vd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 ;D bit + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;vn + xor ecx,ecx + shr eax,1 + setc cl + shl eax,16 + shl ecx,7 ;N bit + or ebp,eax + or ebp,ecx + movzx eax,[operand_register2] ;vm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 ;M bit + or ebp,eax + or ebp,ecx + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction + cmp ebp,0xf0000000 + jb ARM_post_process_copro.thumb + jmp ARM_post_process_simd + +SIMD_INT_vd_vn_vm_alt: + ;used by VABD.S16, VABD.S32, VABD.S8, VABD.U16, VABD.U32, VABD.U8, + ; VADD.I8, VADD.I16, VADD.I32, VADD.I64, VAND, VBIC, VBIF, VBIT, VBSL, + ; VCGE.U8, VCGE.U16, VCGE.U32, VCGT.U8, VCGT.U16, VCGT.U32, VEOR, + ; VHADD.S8, VHADD.S16, VHADD.S32, VHADD.U8, VHADD.U16, VHADD.U32, + ; VHSUB.S8, VHSUB.S16, VHSUB.S32, VHSUB.U8, VHSUB.U16, VHSUB.U32, + ; VMAX.S8, VMAX.S16, VMAX.S32, VMAX.U8, VMAX.U16, VMAX.U32, + ; VMIN.S8, VMIN.S16, VMIN.S32, VMIN.U8, VMIN.U16, VMIN.U32, + ; VMUL.I8, VMUL.S8, VMUL.S16, VMUL.S32, VMUL.U8, VMUL.U16, VMUL.U32, VMUL.P8, + ; VQADD.S8, VQADD.S16, VQADD.S32, VQADD.S64, VQADD.U8, VQADD.U16, VQADD.U32, VQADD.U64, + ; VQRSHL.S8, VQRSHL.S16, VQRSHL.S32, VQRSHL.S64, VQRSHL.U8, VQRSHL.U16, VQRSHL.U32, VQRSHL.U64, + ; VQSUB.S8, VQSUB.S16, VQSUB.S32, VQSUB.S64, VQSUB.U8, VQSUB.U16, VQSUB.U32, VQSUB.U64, + ; VRHADD.S8, VRHADD.S16, VRHADD.S32, VRHADD.U8, VRHADD.U16, VRHADD.U32, + ; VRSHL.S16, VRSHL.S32, VRSHL.S64, VRSHL.S8, VRSHL.U16, VRSHL.U32, VRSHL.U64, VRSHL.U8, + ; VSHL.S16, VSHL.S32, VSHL.S64, VSHL.S8, VSHL.U16, VSHL.U32, VSHL.U64, VSHL.U8, + ; VSUB.I8, VSUB.I16, VSUB.I32, VSUB.I64, VTST.8, VTST.16, VTST.32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;3=qd,qn,qm + .encode: + shr al,1 + jc SIMD_INT_vd_vn_vm.int_test + mov cx,word[operand_registers+0] + mov word[operand_registers+1],cx + jmp SIMD_INT_vd_vn_vm.int_test + +SIMD_INT_vd_vn_vm_alt_zero: + ;used by VCEQ.I8, VCEQ.I16, VCEQ.I32, VCGE.S8, VCGE.S16, VCGE.S32, VCGT.S8, VCGT.S16, VCGT.S32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qdm,0 + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;5=qd,qm,0 + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + test al,010b + jnz .not_zero + .zero: + cmp [immediate_value],0 + mov ecx,ERROR_immediate_offset_out_of_range.0 + jnz ARM_post_process_simd_with_error + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + mov ah,al + shr al,2 + test ah,1 + jnz SIMD_INT_vd_vm.int_test + mov cl,[operand_register0] + mov [operand_register1],cl + jmp SIMD_INT_vd_vm.int_test + .not_zero: + mov ah,al + and ax,0x0401 + shr ah,1 + or al,ah + jmp SIMD_INT_vd_vn_vm_alt.encode + +SIMD_INT_vd_vn_vm_long: + ;used by VABAL.S16, VABAL.S32, VABAL.S8, VABAL.U16, VABAL.U32, VABAL.U8, + ; VABDL.S16, VABDL.S32, VABDL.S8, VABDL.U16, VABDL.U32, VABDL.U8, + ; VADDL.S16, VADDL.S32, VADDL.S8, VADDL.U16, VADDL.U32, VADDL.U8, + ; VSUBL.S16, VSUBL.S32, VSUBL.S8, VSUBL.U16, VSUBL.U32, VSUBL.U8, + ; VMLAL.S8, VMLAL.U8, VMLSL.S8, VMLSL.U8, VMULL.S8, VMULL.U8, VMULL.P8 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=qd,dn,dm + jmp SIMD_INT_vd_vn_vm.int_test + +SIMD_INT_vd_vn_vm_wide: + ;used by VADDW.S16, VADDW.S32, VADDW.S8, VADDW.U16, VADDW.U32, VADDW.U8 + ; VSUBW.S16, VSUBW.S32, VSUBW.S8, VSUBW.U16, VSUBW.U32, VSUBW.U8 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg>,\ ;0=qdn,dm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpd_reg> ;1=qd,qn,dm + jmp SIMD_INT_vd_vn_vm_alt.encode + +SIMD_FLOAT_vd_vn_vm_alt: + ;used by VABD.F32, VACGE.F32, VACGT.F32, VMAX.F32, VMIN.F32, VRECPS.F32, VRSQRTS.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;3=qd,qn,qm + .float_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + shr al,1 + jc SIMD_INT_vd_vn_vm.encode + mov cx,word[operand_registers+0] + mov word[operand_registers+1],cx + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_FLOAT_vd_vn_vm_alt_zero: + ;used by VCEQ.F32, VCGE.F32, VCGT.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qdm,0 + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;5=qd,qm,0 + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + test al,010b + jnz .not_zero + .zero: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + cmp [immediate_value],0 + mov ecx,ERROR_immediate_offset_out_of_range.0 + jnz ARM_post_process_simd_with_error + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + mov ah,al + shr al,2 + test ah,1 + jnz SIMD_INT_vd_vm.encode + mov cl,[operand_register0] + mov [operand_register1],cl + jmp SIMD_INT_vd_vm.encode + .not_zero: + mov ah,al + and ax,0x0401 + shr ah,1 + or al,ah + jmp SIMD_FLOAT_vd_vn_vm_alt.float_test + +SIMD_FLOAT_vd_vm_vn_alt: + ;used by VACLE.F32, VACLT.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddm,dn + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dm,dn + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qdm,qn + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;3=qd,qm,qn + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + .swap: + mov cx,word[operand_registers+1] + xchg ch,cl + mov word[operand_registers+1],cx + shr al,1 + jc SIMD_INT_vd_vn_vm.encode + mov cl,ch + mov ch,[operand_register0] + mov word[operand_registers+1],cx + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_INT_vd_vn_vm_alt_swap: + ;used by VCLE.U8, VCLE.U16, VCLE.U32, VCLT.U8, VCLT.U16, VCLT.U32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;3=qd,qn,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + jmp SIMD_FLOAT_vd_vm_vn_alt.swap + +SIMD_INT_vd_vn_vm_alt_zero_swap: + ;used by VCLE.S8, VCLE.S16, VCLE.S32, VCLT.S8, VCLT.S16, VCLT.S32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qdm,0 + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;5=qd,qm,0 + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + test al,010b + jz SIMD_INT_vd_vn_vm_alt_zero.zero + mov ah,al + and ax,0x0401 + shr ah,1 + or al,ah + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + jmp SIMD_FLOAT_vd_vm_vn_alt.swap + +SIMD_FLOAT_vd_vn_vm_alt_zero_swap: + ;used by VCLE.F32, VCLT.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,0 + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qdm,0 + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;5=qd,qm,0 + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + test al,010b + jz SIMD_FLOAT_vd_vn_vm_alt_zero.zero + mov ah,al + and ax,0x0401 + shr ah,1 + or al,ah + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + jmp SIMD_FLOAT_vd_vm_vn_alt.swap + +SIMD_INT_vd_vm: + ;used by VABS.S8, VABS.S16, VABS.S32, VCLS.S8, VCLS.S16, VCLS.S32, VCLZ.S8, VCLZ.S16, VCLZ.S32, VCNT.8, + ; VMVN, VNEG.S8, VNEG.S16, VNEG.S32, VPADAL.S8, VPADAL.S16, VPADAL.S32, VPADAL.U8, VPADAL.U16, VPADAL.U32 + ; VPADDL.S8, VPADDL.S16, VPADDL.S32, VPADDL.U8, VPADDL.U16, VPADDL.U32, VQABS.S8, VQABS.S16, VQABS.S32, + ; VQNEG.S8, VQNEG.S16, VQNEG.S32, VRECPE.U32, VREV16.8, VREV32.16, VREV32.8, VREV64.16, VREV64.32, VREV64.8, + ; VRSQRTE.U32, VSWP, VTRN.8, VTRN.16, VTRN.32, VUZP.8, VUZP.16, VUZP.32, VZIP.8, VZIP.16, VZIP.32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_simd_qreg,TMPL_simd_qreg> ;1=qd,qm + .int_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + .encode: + movzx eax,al + shl eax,6 + or ebp,eax ;set Q bit + movzx eax,[operand_register0] ;vd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 ;D bit + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;vm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 ;M bit + or ebp,eax + or ebp,ecx + jmp ARM_post_process_simd + +SIMD_FLOAT_vd_vm_imm: + ;used by VCVT.F32.S32, VCVT.F32.U32, VCVT.S32.F32, VCVT.U32.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,imm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qd,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;3=qd,qm,imm + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;4=sd,sm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_imm>,\ ;5=sd,sm,imm + <TMPL_vfps_reg,TMPL_imm> ;6=sdm,imm + cmp al,6 + jnz .registers_okay + mov cl,[operand_register0] + mov [operand_register1],cl + mov al,5 + .registers_okay: + shr al,1 + jnc SIMD_FLOAT_vd_vm_f32.encode + ;recode for immediate forms + mov ecx,ebp + mov edx,ebp + and ecx,1 shl 7 ;signed=0, unsigned=1 + and edx,1 shl 8 ;to float=0, to int=1 + shl edx,(18-8)-(16-7) + or edx,ecx + shl edx,16-7 + or edx,0x0eba0ac0 ;fsltos + mov [thumb32_instruction],edx + shl ecx,24-7 + and ebp,1 shl 8 + or ebp,ecx + or ebp,0xf2a00e10 ;vcvt.f32.s32 without imm + cmp al,2 + jz .VFP_alias + mov ecx,[immediate_value] + cmp ecx,1 + jb .out_of_range + cmp ecx,32 + ja .out_of_range + mov edx,32 + sub edx,ecx + shl edx,16 + or ebp,edx + jmp SIMD_FLOAT_vd_vm_f32.float_test + .VFP_alias: + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + jmp VFP_dd_dd_imm.do + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.1_32 + jmp ARM_post_process_copro_with_error + +SIMD_FLOAT_vd_vm_f32: + ;used by VABS.F32, VNEG.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;1=qd,qm + <TMPL_vfps_reg,TMPL_vfps_reg> ;2=sd,sm + .encode: + cmp al,2 + jnz .float_test + ;VFP alias + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + jmp VFP_sd_sm.v1xd_test + .float_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + jmp SIMD_INT_vd_vm.encode + +SIMD_FLOAT_vd_vn_vm_f32: + ;used by VADD.F32, VSUB.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;2=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;3=qd,qn,qm + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;4=sdn,sm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;5=sd,sn,sm + .do: + cmp al,4 + jb SIMD_FLOAT_vd_vn_vm_alt.float_test + ;VFP alias + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + sub al,4 + jmp VFP_sd_sn_sm.v1xd_test + +SIMD_INT_vd_vn_vm_narrow: + ;used by VADDHN.I16, VADDHN.I32, VADDHN.I64, VRADDHN.I16, VRADDHN.I32, VRADDHN.I64, + ; VRSUBHN.I16, VRSUBHN.I32, VRSUBHN.I64, VSUBHN.I16, VSUBHN.I32, VSUBHN.I64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_simd_qreg,TMPL_simd_qreg> ;0=dd,qn,qm + jmp SIMD_INT_vd_vn_vm.int_test + +SIMD_INT_vd_imm: + ;used by VAND.I32, VAND.I16, VBIC.I32, VBIC.I16, VORN.I32, VORN.I16, VORR.I32, VORR.I16 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_imm>,\ ;0=qd,imm + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,imm + mov ecx,[immediate_value] + btr ebp,0 ;test for VAND + jnc .inversion_done + not ecx + test ebp,1000b shl 8 ;test for .I16 instruction + jz .inversion_done + cmp ecx,0xffff0000 + jb .inversion_done + movzx ecx,cx + .inversion_done: + test ecx,not 0xff + jz .encode + xor ebp,0010b shl 8 + ror ecx,8 + test ecx,not 0xff + jz .encode + test ebp,1000b shl 8 ;test for .I16 instruction + jnz .out_of_range + xor ebp,0110b shl 8 + ror ecx,8 + test ecx,not 0xff + jz .encode + xor ebp,0010b shl 8 + ror ecx,8 + test ecx,not 0xff + jnz .out_of_range + .encode: + and eax,1 + xor eax,1 + shl eax,6 + or ebp,eax ;set Q + mov eax,ecx + mov edx,ecx + and eax,0x0f + and ecx,0x70 + and edx,0x80 + shl ecx,16-4 + shl edx,24-7 + or ebp,eax ;imm4 + or ebp,ecx ;imm3 + or ebp,edx ;i + movzx eax,[operand_register0] ;vd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 ;D bit + or ebp,eax + or ebp,ecx + jmp ARM_post_process_simd + .out_of_range: + mov ecx,ERROR_immediate_cannot_be_encoded + jmp ARM_post_process_simd_with_error + +SIMD_FLOAT_qd_dm: + ;used by VCVT.F32.F16 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg> ;0=qd,dm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_HP + jz ERROR_requires_copro_capability_simd_hp + jmp SIMD_INT_vd_vm.encode + +SIMD_FLOAT_dd_qm: + ;used by VCVT.F16.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_simd_qreg> ;0=dd,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_HP + jz ERROR_requires_copro_capability_simd_hp + jmp SIMD_INT_vd_vm.encode + +SIMD_INT_qd_dmx: + ;used by VDUP.8, VDUP.16, VDUP.32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;0=dd,dm[x] + <TMPL_vfpd_reg,TMPL_base_reg>,\ ;1=dd,rt + <TMPL_simd_qreg,TMPL_vfpdx_reg>,\ ;2=qd,dm[x] + <TMPL_simd_qreg,TMPL_base_reg> ;3=qd,rt + shr al,1 + jc .reg + mov ecx,ebp + shr ecx,16 + and ecx,0xf ;ecx=1, 2 or 3 for 8, 16 or 32 size + and ebp,not (0xf shl 16) + mov edx,16 + shr edx,cl + cmp edx,[immediate_value] + jbe .out_of_range + mov edx,[immediate_value] + shl edx,1 + or edx,1 + add ecx,16-1 + shl edx,cl + or ebp,edx + jmp SIMD_INT_vd_vm.int_test + .reg: + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + shl eax,21 + or ebp,eax ;set Q + movzx eax,[operand_register0] ;vd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,16 + shl ecx,7 ;D bit + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;rt + cmp eax,15 ;PC? + jz ERROR_r15_not_valid + shl eax,12 + or ebp,eax + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_post_process_copro + cmp eax,13 shl 12 ;SP? + jz ERROR_r13_not_valid + jmp ARM_post_process_copro + .out_of_range: + mov ecx,ERROR_immediate_cannot_be_encoded + jmp ARM_post_process_simd_with_error + +SIMD_INT_vd_vn_vm_imm: + ;used by VEXT.8, VEXT.16, VEXT.32, VEXT.64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddn,dm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dn,dm,imm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;2=qdn,qm,imm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm> ;3=qd,qn,qm,imm + mov edx,[immediate_value] + mov ecx,ebp + shr ecx,8 + and ecx,0xf ;ecx=multiplier + imul edx,ecx + mov ecx,eax + shr ecx,1 + and ecx,1 + xor ecx,1 + shl edx,cl + cmp edx,16 + jae .out_of_range + shr edx,cl + and ebp,not (0xf shl 8) + shl edx,8 + or ebp,edx + shr al,1 + jc SIMD_INT_vd_vn_vm.int_test + mov cx,word[operand_registers+0] + mov word[operand_registers+1],cx + jmp SIMD_INT_vd_vn_vm.int_test + .out_of_range: + mov ecx,ERROR_immediate_cannot_be_encoded + jmp ARM_post_process_simd_with_error + +SIMD_INT_list_rn_rm_1: + ;used by VLD1.8, VLD1.16, VLD1.32, VLD1.64, VST1.8, VST1.16, VST1.32, VST1.64 + call decode_template + TEMPLATE \ + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\ ;0={dy[x]},[rn] + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;1={dy[x]},[rn]! + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\ ;2={dy[x]},[rn],rm + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm> ;3={dy[x]},[rn],imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + jz .element + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + jz .vector + ;register + mov ah,[simd_reg_list_count] + xor ecx,ecx + mov edx,7 shl 8 ;type = 0111 + cmp ah,1 + cmovz ecx,edx + mov edx,10 shl 8 ;type = 1010 + cmp ah,2 + cmovz ecx,edx + mov edx,6 shl 8 ;type = 0110 + cmp ah,3 + cmovz ecx,edx + mov edx,2 shl 8 ;type = 0010 + cmp ah,4 + cmovz ecx,edx + or ebp,ecx + test ecx,ecx + mov ecx,ERROR_register_list_invalid + jz ARM_post_process_simd_with_error + mov ah,[operand_register0] ;rn + mov ecx,0 shl 4 ;align = 00 + shr ah,4 + jz .set_alignment + mov ecx,1 shl 4 ;align = 01 + cmp ah,3 ;@64 + jz .set_alignment + mov ecx,2 shl 4 ;align = 10 + cmp ah,4 ;@128 + jz .set_alignment + cmp ah,5 ;@256 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + mov ecx,3 shl 4 ;align = 11 + .set_alignment: + or ebp,ecx + movzx ebx,[simd_reg_list_count] + shl ebx,3 ;ebx=writeback offset + .encode: + mov edx,0xf + cmp al,0 + jz .set_rm + mov edx,0xd + cmp al,1 + jz .set_rm + movzx edx,[operand_register1] ;rm + mov ecx,ERROR_r13_r15_not_valid.third + cmp edx,13 + jz ARM_post_process_simd_with_error + cmp edx,15 + jz ARM_post_process_simd_with_error + cmp al,2 + jz .set_rm + ;immediate post update + cmp ebx,[immediate_value] + mov ecx,ERROR_immediate_offset_out_of_range + jnz ARM_post_process_simd_with_error + mov edx,0xd + .set_rm: + or ebp,edx + movzx eax,[simd_reg_list_first] ;vd + mov ecx,eax + and eax,0x0f + and ecx,0x10 + shl eax,12 + shl ecx,22-4 ;D bit + or ebp,eax + or ebp,ecx + movzx eax,[operand_register0] ;rn + and eax,0xf + cmp eax,0xf + mov ecx,ERROR_r15_not_valid.second + jz ARM_post_process_simd_with_error + shl eax,16 + or ebp,eax + jmp ARM_post_process_simd + .element: + or ebp,1 shl 23 + cmp [simd_reg_list_count],1 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + mov edx,ebp + and edx,3 shl 6 + cmp edx,3 shl 6 ;.64 size? + mov ecx,ERROR_use_fldr_for_single_reg + jz ARM_post_process_simd_with_error + and ebp,not (3 shl 6) + shl edx,10-6 + or ebp,edx + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 10 + movzx edx,[simd_reg_list_x] + ja .element.32 + jz .element.16 + ;element.8 + test ah,ah + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + cmp edx,7 + mov ecx,ERROR_element_value_out_of_range.0_7 + ja ARM_post_process_simd_with_error + shl edx,4+1 + or ebp,edx + mov ebx,1 + jmp .encode + .element.16: + cmp ah,1 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp edx,3 + mov ecx,ERROR_element_value_out_of_range.0_3 + ja ARM_post_process_simd_with_error + shl edx,2 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,2 + jmp .encode + .element.32: + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + cmp edx,1 + mov ecx,ERROR_element_value_out_of_range.0_1 + ja ARM_post_process_simd_with_error + shl edx,3 + or dl,ah + shr ah,1 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,4 + jmp .encode + .vector: + mov ecx,ERROR_register_list_invalid + test ebp,1 shl 21 ;VST1=0 + jz ARM_post_process_simd_with_error + or ebp,1 shl 23 + 3 shl 10 + movzx edx,[simd_reg_list_count] + cmp edx,2 + mov ecx,ERROR_register_list_invalid + ja ARM_post_process_simd_with_error + dec edx + shl edx,5 + or ebp,edx ;set T bit + mov edx,ebp + and edx,3 shl 6 + cmp edx,3 shl 6 ;.64 size? + mov ecx,ERROR_reg_size_64_not_encodable + jz ARM_post_process_simd_with_error + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 6 + movzx edx,ah + ja .vector.32 + jz .vector.16 + ;vector.8 + test ah,ah + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + mov ebx,1 + jmp .encode + .vector.16: + cmp ah,1 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + shl edx,4 + or ebp,edx + mov ebx,2 + jmp .encode + .vector.32: + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + shl edx,3 + or ebp,edx + mov ebx,4 + jmp .encode + +SIMD_INT_list_rn_rm_2: + ;used by VLD2.8, VLD2.16, VLD2.32, VST2.8, VST2.16, VST2.32 + call decode_template + TEMPLATE \ + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\ ;0={dy[x]},[rn] + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;1={dy[x]},[rn]! + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\ ;2={dy[x]},[rn],rm + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm> ;3={dy[x]},[rn],imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + jz .element + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + jz .vector + ;register + mov ah,[simd_reg_list_count] + xor ecx,ecx + mov edx,8 shl 8 ;type = 1000 + cmp ah,2 + cmovz ecx,edx + mov edx,9 shl 8 ;type = 1001 + cmp ah,0x82 + cmovz ecx,edx + mov edx,3 shl 8 ;type = 0011 + cmp ah,4 + cmovz ecx,edx + or ebp,ecx + test ecx,ecx + mov ecx,ERROR_register_list_invalid + jz ARM_post_process_simd_with_error + mov ah,[operand_register0] ;rn + mov ecx,0 shl 4 ;align = 00 + shr ah,4 + jz .set_alignment + mov ecx,1 shl 4 ;align = 01 + cmp ah,3 ;@64 + jz .set_alignment + mov ecx,2 shl 4 ;align = 10 + cmp ah,4 ;@128 + jz .set_alignment + cmp ah,5 ;@256 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + cmp [simd_reg_list_count],4 + jnz ARM_post_process_simd_with_error + mov ecx,3 shl 4 ;align = 11 + .set_alignment: + or ebp,ecx + mov bl,[simd_reg_list_count] + and ebx,0x7f + shl ebx,3 ;ebx=writeback offset + jmp SIMD_INT_list_rn_rm_1.encode + .element: + or ebp,1 shl 23 + 1 shl 8 + mov cl,[simd_reg_list_count] + test ebp,3 shl 6 ;.8? + setz ch + shl ch,7 + or ch,0x7f + and cl,ch + cmp cl,2 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + mov edx,ebp + and edx,3 shl 6 + and ebp,not (3 shl 6) + shl edx,10-6 + or ebp,edx + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 10 + movzx edx,[simd_reg_list_x] + ja .element.32 + jz .element.16 + ;element.8 + cmp ah,1 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp edx,7 + mov ecx,ERROR_element_value_out_of_range.0_7 + ja ARM_post_process_simd_with_error + shl edx,1 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,2 + jmp SIMD_INT_list_rn_rm_1.encode + .element.16: + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + cmp edx,3 + mov ecx,ERROR_element_value_out_of_range.0_3 + ja ARM_post_process_simd_with_error + shl edx,1 + mov cl,[simd_reg_list_count] + shr cl,7 + or dl,cl + shl edx,1 + shr ah,1 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,4 + jmp SIMD_INT_list_rn_rm_1.encode + .element.32: + cmp ah,3 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + cmp edx,1 + mov ecx,ERROR_element_value_out_of_range.0_1 + ja ARM_post_process_simd_with_error + shl edx,1 + mov cl,[simd_reg_list_count] + shr cl,7 + or dl,cl + shl edx,2 + and ah,1 + xor ah,1 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,8 + jmp SIMD_INT_list_rn_rm_1.encode + .vector: + mov ecx,ERROR_register_list_invalid + test ebp,1 shl 21 ;VST2=0 + jz ARM_post_process_simd_with_error + or ebp,1 shl 23 + 0xd shl 8 + mov dl,[simd_reg_list_count] + mov dh,dl + and dx,0x7f80 + cmp dh,2 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + shr edx,7-5 + and edx,0x20 + or ebp,edx ;set T bit + mov edx,ebp + and edx,3 shl 6 + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 6 + movzx edx,ah + ja .vector.32 + jz .vector.16 + ;vector.8 + cmp ah,1 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + shl edx,4 + or ebp,edx + mov ebx,2 + jmp SIMD_INT_list_rn_rm_1.encode + .vector.16: + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + shl edx,3 + or ebp,edx + mov ebx,4 + jmp SIMD_INT_list_rn_rm_1.encode + .vector.32: + cmp ah,3 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + and edx,1 + shl edx,4 + or ebp,edx + mov ebx,8 + jmp SIMD_INT_list_rn_rm_1.encode + +SIMD_INT_list_rn_rm_3: + ;used by VLD3.8, VLD3.16, VLD3.32, VST3.8, VST3.16, VST3.32 + call decode_template + TEMPLATE \ + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\ ;0={dy[x]},[rn] + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;1={dy[x]},[rn]! + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\ ;2={dy[x]},[rn],rm + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm> ;3={dy[x]},[rn],imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + jz .element + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + jz .vector + ;register + mov ah,[simd_reg_list_count] + xor ecx,ecx + mov edx,4 shl 8 ;type = 0100 + cmp ah,3 + cmovz ecx,edx + mov edx,5 shl 8 ;type = 0101 + cmp ah,0x83 + cmovz ecx,edx + or ebp,ecx + test ecx,ecx + mov ecx,ERROR_register_list_invalid + jz ARM_post_process_simd_with_error + mov ah,[operand_register0] ;rn + mov ecx,0 shl 4 ;align = 00 + shr ah,4 + jz .set_alignment + cmp ah,3 ;@64 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + mov ecx,1 shl 4 ;align = 01 + .set_alignment: + or ebp,ecx + mov ebx,24 ;ebx=writeback offset + jmp SIMD_INT_list_rn_rm_1.encode + .element: + or ebp,1 shl 23 + 2 shl 8 + mov ah,[simd_reg_list_count] + and ah,0x7f + cmp ah,3 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + mov edx,ebp + and edx,3 shl 6 + and ebp,not (3 shl 6) + shl edx,10-6 + or ebp,edx + mov ah,[simd_reg_list_count] + shr ah,7 + test [operand_register0],0xf0 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + cmp edx,1 shl 10 + movzx edx,[simd_reg_list_x] + ja .element.32 + jz .element.16 + ;element.8 + test [simd_reg_list_count],0x80 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + cmp edx,7 + mov ecx,ERROR_element_value_out_of_range.0_7 + ja ARM_post_process_simd_with_error + shl edx,4+1 + or ebp,edx + mov ebx,3 + jmp SIMD_INT_list_rn_rm_1.encode + .element.16: + cmp edx,3 + mov ecx,ERROR_element_value_out_of_range.0_3 + ja ARM_post_process_simd_with_error + shl edx,1 + or dl,ah + shl edx,4+1 + or ebp,edx + mov ebx,6 + jmp SIMD_INT_list_rn_rm_1.encode + .element.32: + cmp edx,1 + mov ecx,ERROR_element_value_out_of_range.0_1 + ja ARM_post_process_simd_with_error + shl edx,1 + or dl,ah + shl edx,4+2 + or ebp,edx + mov ebx,12 + jmp SIMD_INT_list_rn_rm_1.encode + .vector: + mov ecx,ERROR_register_list_invalid + test ebp,1 shl 21 ;VST3=0 + jz ARM_post_process_simd_with_error + or ebp,1 shl 23 + 0xe shl 8 + mov ah,[simd_reg_list_count] + and ah,0x7f + cmp ah,3 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + movzx edx,[simd_reg_list_count] + shr edx,7-5 + or ebp,edx ;set T bit + test [operand_register0],0xf0 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + mov ecx,ebp + shr ecx,6 + and ecx,3 + mov ebx,3 + shl ebx,cl + jmp SIMD_INT_list_rn_rm_1.encode + +SIMD_INT_list_rn_rm_4: + ;used by VLD4.8, VLD4.16, VLD4.32, VST4.8, VST4.16, VST4.32 + call decode_template + TEMPLATE \ + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\ ;0={dy[x]},[rn] + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;1={dy[x]},[rn]! + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\ ;2={dy[x]},[rn],rm + <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm> ;3={dy[x]},[rn],imm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT + jz .element + cmp [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR + jz .vector + ;register + mov ah,[simd_reg_list_count] + or ecx,-1 + mov edx,0 shl 8 ;type = 0000 + cmp ah,4 + cmovz ecx,edx + mov edx,1 shl 8 ;type = 0001 + cmp ah,0x84 + cmovz ecx,edx + or ebp,ecx + inc ecx + mov ecx,ERROR_register_list_invalid + jz ARM_post_process_simd_with_error + mov ah,[operand_register0] ;rn + mov ecx,0 shl 4 ;align = 00 + shr ah,4 + jz .set_alignment + mov ecx,1 shl 4 ;align = 01 + cmp ah,3 ;@64 + jz .set_alignment + mov ecx,2 shl 4 ;align = 10 + cmp ah,4 ;@128 + jz .set_alignment + cmp ah,5 ;@256 + mov ecx,ERROR_alignment_invalid + jnz ARM_post_process_simd_with_error + mov ecx,3 shl 4 ;align = 11 + .set_alignment: + or ebp,ecx + mov ebx,32 + jmp SIMD_INT_list_rn_rm_1.encode + .element: + or ebp,1 shl 23 + 3 shl 8 + mov cl,[simd_reg_list_count] + test ebp,3 shl 6 ;.8? + setz ch + shl ch,7 + or ch,0x7f + and cl,ch + cmp cl,4 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + mov edx,ebp + and edx,3 shl 6 + and ebp,not (3 shl 6) + shl edx,10-6 + or ebp,edx + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 10 + movzx edx,[simd_reg_list_x] + ja .element.32 + jz .element.16 + ;element.8 + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + cmp edx,7 + mov ecx,ERROR_element_value_out_of_range.0_7 + ja ARM_post_process_simd_with_error + shl edx,2 + or dl,ah + shl edx,3 + or ebp,edx + mov ebx,4 + jmp SIMD_INT_list_rn_rm_1.encode + .element.16: + cmp ah,3 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + cmp edx,3 + mov ecx,ERROR_element_value_out_of_range.0_3 + ja ARM_post_process_simd_with_error + shl edx,1 + mov cl,[simd_reg_list_count] + shr cl,7 + or dl,cl + shl edx,1 + and ah,1 + xor ah,1 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,8 + jmp SIMD_INT_list_rn_rm_1.encode + .element.32: + cmp ah,4 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + cmp edx,1 + mov ecx,ERROR_element_value_out_of_range.0_1 + ja ARM_post_process_simd_with_error + shl edx,1 + mov cl,[simd_reg_list_count] + shr cl,7 + or dl,cl + shl edx,2 + inc ah + shr ah,1 + and ah,3 + or dl,ah + shl edx,4 + or ebp,edx + mov ebx,16 + jmp SIMD_INT_list_rn_rm_1.encode + .vector: + mov ecx,ERROR_register_list_invalid + test ebp,1 shl 21 ;VST4=0 + jz ARM_post_process_simd_with_error + or ebp,1 shl 23 + 0xf shl 8 + mov dl,[simd_reg_list_count] + mov dh,dl + and dx,0x7f80 + cmp dh,4 + mov ecx,ERROR_register_list_invalid + jnz ARM_post_process_simd_with_error + shr edx,7-5 + and edx,0x20 + or ebp,edx ;set T bit + mov edx,ebp + and edx,3 shl 6 + mov ah,[operand_register0] ;rn + shr ah,4 + cmp edx,1 shl 6 + movzx edx,ah + ja .vector.32 + jz .vector.16 + ;vector.8 + cmp ah,2 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + cmp ah,1 + mov ecx,ERROR_alignment_invalid + jz ARM_post_process_simd_with_error + shl edx,3 + or ebp,edx + mov ebx,4 + jmp SIMD_INT_list_rn_rm_1.encode + .vector.16: + cmp ah,3 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + and edx,1 + shl edx,4 + or ebp,edx + mov ebx,8 + jmp SIMD_INT_list_rn_rm_1.encode + .vector.32: + cmp ah,4 + mov ecx,ERROR_alignment_invalid + ja ARM_post_process_simd_with_error + dec ah + cmp ah,2 + mov ecx,ERROR_alignment_invalid + jb ARM_post_process_simd_with_error + and edx,4 + shl edx,6-2 + not ah + and ah,0x10 + or dl,ah + or ebp,edx + mov ebx,16 + jmp SIMD_INT_list_rn_rm_1.encode + +SIMD_INT_rn_list: + ;used by VLDMIA, VLDMDB, VSTMIA, VSTMDB + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfp_reg_list_s>,\ ;0=rn,{s..} + <TMPL_base_reg,TMPL_vfp_reg_list_d>,\ ;1=rn,{d..} + <TMPL_base_reg!,TMPL_vfp_reg_list_s>,\ ;2=rn!,{s..} + <TMPL_base_reg!,TMPL_vfp_reg_list_d> ;3=rn!,{d..} + shr al,1 + jnc VFP_rn_list_s.do + or ebp,1 shl 8 + jmp VFP_rn_list_d.do + +SIMD_INT_vd_rn_offset: + ;used by VLDR, VSTR + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=sd,[rn] + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=sd,[rn,imm] + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;2=sd,[imm] PC relative + <TMPL_vfps_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;3=sd,[exp] implicit reg from structure + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;4=dd,[rn] + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;5=dd,[rn,imm] + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\ ;6=dd,[imm] PC relative + <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;7=dd,[exp] implicit reg from structure + cmp al,3 + jbe VFP_sd_rn_offset.do + or ebp,1 shl 8 + sub al,4 + jmp VFP_dd_rn_offset.do + +SIMD_INT_vd_vn_vmx: + ;used by VMLA.S16, VMLA.S32, VMLA.U16, VMLA.U32, VMLA.I16, VMLA.I32, + ; VMLS.S16, VMLS.S32, VMLS.U16, VMLS.U32, VMLS.I16, VMLS.I32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;1=dd,dn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;2=qd,qn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg> ;3=qd,qn,dm[x] + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + shr al,1 + jnc SIMD_INT_vd_vn_vm.encode + mov ecx,ebp + and ebp,0x00300000 + and ecx,0x01000000 + or ebp,0xf2800040 + shr ecx,24-10 + or ebp,ecx + .encode: + mov dl,[operand_register2] + shr dl,1 + sbb cl,cl + and cl,0x10 + or dl,cl + mov [operand_register2],dl + movzx eax,al + shl eax,24 + or ebp,eax ;set Q + mov ecx,ebp + shr ecx,21 + and ecx,1 ;ecx=1 for size .32 + mov eax,3 + mov edx,8 + shr eax,cl ;eax=maximum index value + shl edx,cl ;edx=maximum register + 1 + test ecx,ecx + mov ecx,ERROR_element_value_out_of_range.0_1 + mov ebx,ERROR_element_value_out_of_range.0_3 + cmovz ecx,ebx + cmp [immediate_value],eax + ja ARM_post_process_simd_with_error + mov ecx,ERROR_scalar_register_out_of_range.0_7 + mov ebx,ERROR_scalar_register_out_of_range.0_15 + cmp edx,8 + cmovnz ecx,ebx + cmp [operand_register2],dl + jae ARM_post_process_simd_with_error + shr edx,4 + mov ecx,edx + mov eax,[immediate_value] + shl eax,cl + mov edx,eax + and edx,1 + shl edx,3 + or dl,[operand_register2] + shr eax,2 + rcl edx,1 + mov [operand_register2],dl + xor eax,eax + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_FLOAT_vd_vn_vmx_f32: + ;used by VMLA.F32, VMLS.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;1=dd,dn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;2=qd,qn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;3=qd,qn,dm[x] + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;4=sd,sn,sm + cmp al,4 + jae .vfp_alias + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + shr al,1 + jnc SIMD_INT_vd_vn_vm.encode + and ebp,0x00200000 + shr ebp,21-10 + or ebp,0xf2a00140 + jmp SIMD_INT_vd_vn_vmx.encode + .vfp_alias: + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + mov al,1 + jmp VFP_sd_sn_sm.v1xd_test + +SIMD_INT_vd_vn_vmx_long: + ;used by VMLAL.S16, VMLAL.S32, VMLAL.U16, VMLAL.U32, VMLSL.S16, VMLSL.S32, VMLSL.U16, VMLSL.U32, + ; VMULL.S16, VMULL.S32, VMULL.U16, VMULL.U32, VQDMLAL.S16, VQDMLAL.S32, VQDMLSL.S16, VQDMLSL.S32, + ; VQDMULL.S16, VQDMULL.S32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=qd,dn,dm + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpdx_reg> ;1=qd,dn,dm[x] + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + shr al,1 + jnc SIMD_INT_vd_vn_vm.encode + mov ebp,[thumb32_instruction] + jmp SIMD_INT_vd_vn_vmx.encode + +SIMD_INT_vd_imm_i8: + ;used by VMOV.I8, VMOV.I64 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_imm>,\ ;0=qd,imm + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,imm + mov ecx,[immediate_value] + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + jmp SIMD_INT_vd_imm.out_of_range + +SIMD_INT_vd_imm_i16: + ;used by VMOV.I16, VMVN.I16 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_imm>,\ ;0=qd,imm + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,imm + mov ecx,[immediate_value] + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + xor ebp,0x00000200 ;cmode=a + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + xor ebp,1 shl 5 + 0x00000200 ;cmode=8, invert op, VMVN<-->VMOV + mov ecx,[immediate_value] + not cx + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + xor ebp,0x00000200 ;cmode=a + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + jmp SIMD_INT_vd_imm.out_of_range + +SIMD_INT_vd_imm_i32: + ;used by VMOV.I32, VMVN.I32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_imm>,\ ;0=qd,imm + <TMPL_vfpd_reg,TMPL_imm> ;1=dd,imm + mov ecx,[immediate_value] + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=2 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=4 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=6 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000600 ;cmode=c + ror ecx,8+8 + xor ecx,0xff000000 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000100 ;cmode=d + ror ecx,8 + xor ecx,0xff000000 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + xor ebp,1 shl 5 + 0x00000d00 ;cmode=0, invert op, VMVN<-->VMOV + mov ecx,[immediate_value] + not ecx + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=2 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=4 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000200 ;cmode=6 + ror ecx,8 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000600 ;cmode=c + ror ecx,8+8 + xor ecx,0xff000000 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + add ebp,0x00000100 ;cmode=d + ror ecx,8 + xor ecx,0xff000000 + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + jmp SIMD_INT_vd_imm.out_of_range + +SIMD_FLOAT_dm_imm: + ;used by VMOV.F64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm_float>,\ ;0=dd,float + <TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg> ;2=dd,dm + cmp al,2 + jb VFP_dm_imm.vesion_test + or ebp,0x00000040 ;FCPYD + jmp VFP_dd_dm.encode + +SIMD_FLOAT_sm_imm: + ;used by VMOV.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_imm_float>,\ ;0=sd,float + <TMPL_vfps_reg,TMPL_imm>,\ ;1=sd,imm + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;2=sd,sm + <TMPL_simd_qreg,TMPL_imm_float>,\ ;3=qd,float + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qd,imm + <TMPL_vfpd_reg,TMPL_imm_float>,\ ;5=dd,float + <TMPL_vfpd_reg,TMPL_imm> ;6=dd,imm + cmp al,2 + jb VFP_dm_imm.do + lea ebp,[ebp+0x00000040] ;FCPYS + jz VFP_sd_sm.v1xd_test + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + sub al,3 + shr al,1 + movzx ebp,al + jc .constant_converted + call VFP_convert_single_to_quarter + .constant_converted: + mov eax,ebp + mov ebp,[thumb32_instruction] + mov ecx,[immediate_value] + test ecx,not 0xff + jz SIMD_INT_vd_imm.encode + jmp SIMD_INT_vd_imm.out_of_range + +SIMD_INT_rd_dnx: + ;used by VMOV.S8, VMOV.S16, VMOV.U8, VMOV.U16 + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_vfpdx_reg> ;0=rd,dn[x] + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + mov edx,[immediate_value] + mov ecx,ebp + shr ecx,5 + and ecx,1 + shl edx,cl + test ecx,ecx + mov ecx,ERROR_element_value_out_of_range.0_3 + mov ebx,ERROR_element_value_out_of_range.0_7 + cmovz ecx,ebx + cmp edx,7 + ja ARM_post_process_simd_with_error + mov ecx,edx + and edx,3 + and ecx,4 + shl edx,5 + shl ecx,21-2 + or ebp,edx + or ebp,ecx + test [code_type],CPU_ACTIVITY_ARM + jnz VFP_rd_dn.encode + movzx eax,[operand_register0] ;rd + cmp eax,13 ;SP? + jz ERROR_r13_not_valid + jmp VFP_rd_dn.encode + +SIMD_INT_ddx_rn: + ;used by VMOV.8, VMOV.16 + call decode_template + TEMPLATE \ + <TMPL_vfpdx_reg,TMPL_base_reg> ;0=dd[x],rn + mov ax,word[operand_registers+0] + xchg ah,al + mov word[operand_registers+0],ax + jmp SIMD_INT_rd_dnx.do + +SIMD_INT_rdd_rdn: + ;used by VMOV.32 + call decode_template + TEMPLATE \ + <TMPL_vfpdx_reg,TMPL_base_reg>,\ ;0=dd[x],rn + <TMPL_base_reg,TMPL_vfpdx_reg> ;1=rd,dn[x] + .do: + movzx eax,al + mov cx,word[operand_registers+0] + mov dx,cx + xchg ch,cl + shl eax,20 + cmovz ecx,edx + mov word[operand_registers+0],cx + or ebp,eax + mov edx,[immediate_value] + cmp edx,1 + mov ecx,ERROR_element_value_out_of_range.0_1 + ja ARM_post_process_simd_with_error + shl edx,21 + or ebp,edx + test [code_type],CPU_ACTIVITY_ARM + jnz VFP_dn_rd.test_version + movzx eax,[operand_register0] ;rd + cmp eax,13 ;SP? + jz ERROR_r13_not_valid + jmp VFP_dn_rd.test_version + + align 4 +SIMD_INT_MOV_table: + dd 0x0e000a10,VFP_sn_rd.do,0 ;0=FMSR + dd 0x0c400a10,SIMD_INT_MOV.msrr,0 ;1=FMSRR + dd 0x0e000b10,SIMD_INT_rdd_rdn.do,0 ;2=VMOV.32 + dd 0xf2200110,SIMD_INT_MOV.vd_vm,0 ;3=dd,dn + dd 0x0c400b10,VFP_dm_rd_rn.test_version,0 ;4=FMDRR + dd 0x0e000b10,SIMD_INT_rdd_rdn.do,1 ;5=VMOV.32 + dd 0x0e100a10,VFP_rd_dn.do,0 ;6=FMRS + dd 0x0c500a10,SIMD_INT_MOV.mrrs,0 ;7=FMRRS + dd 0x0c500b10,VFP_rd_rn_dm.test_version,0 ;8=FMRRD + dd 0xf2200150,SIMD_INT_MOV.vd_vm,0 ;9=qd,qn + +SIMD_INT_MOV: + ;used by VMOV + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_base_reg>,\ ;0=sn,rd + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_base_reg,TMPL_base_reg>,\ ;1=sd1,sd2,rn1,rn2 + <TMPL_vfpdx_reg,TMPL_base_reg>,\ ;2=dd[x],rn + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn + <TMPL_vfpd_reg,TMPL_base_reg,TMPL_base_reg>,\ ;4=dd,rn1,rn2 + <TMPL_base_reg,TMPL_vfpdx_reg>,\ ;5=rd,dn[x] + <TMPL_base_reg,TMPL_vfps_reg>,\ ;6=rd,sn + <TMPL_base_reg,TMPL_base_reg,TMPL_vfps_reg,TMPL_vfps_reg>,\ ;7=rd1,rd2,sn1,sn2 + <TMPL_base_reg,TMPL_base_reg,TMPL_vfpd_reg>,\ ;8=rd1,rd2,dn + <TMPL_simd_qreg,TMPL_simd_qreg> ;9=qd,qn + movzx eax,al + imul eax,12 + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[eax+SIMD_INT_MOV_table+0] + mov ecx,[eax+SIMD_INT_MOV_table+4] + mov eax,[eax+SIMD_INT_MOV_table+8] + jmp vcx + .msrr: + xor edx,edx + movzx ecx,[operand_register0] + bts edx,ecx + movzx ecx,[operand_register1] + bts edx,ecx + mov [reg_list_bitmap],edx + mov ecx,[operand_registers] + shr ecx,16 + mov [operand_registers],ecx + jmp VFP_rd_rn_sm.do + .mrrs: + xor edx,edx + movzx ecx,[operand_register2] + bts edx,ecx + movzx ecx,[operand_register3] + bts edx,ecx + mov [reg_list_bitmap],edx + jmp VFP_rd_rn_sm.do + .vd_vm: + mov cl,[operand_register1] + mov [operand_register2],cl + jmp SIMD_INT_vd_vn_vm.int_test + +SIMD_INT_qd_dm: + ;used by VMOVL.S8, VMOVL.S16, VMOVL.S32, VMOVL.U8, VMOVL.U16, VMOVL.U32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg> ;0=qd,dm + jmp SIMD_INT_vd_vm.int_test + +SIMD_INT_dd_qm: + ;used by VMOVN.I8, VMOVN.I16, VMOVN.I32, VQMOVN.S16, VQMOVN.S32, VQMOVN.S64, VQMOVN.U16, + ; VQMOVN.U32, VQMOVN.U64, VQMOVUN.S16, VQMOVUN.S32, VQMOVUN.S64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_simd_qreg> ;0=dd,qm + jmp SIMD_INT_vd_vm.int_test + +SIMD_INT_vd_vn_vmx_alt: + ;used by VMUL.I16, VMUL.I32, VQDMULH.S16, VQDMULH.S32, VQRDMULH.S16, VQRDMULH.S32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;0=ddn,dm[x] + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;1=dd,dn,dm[x] + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_vfpdx_reg>,\ ;4=qdn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;5=qd,qn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT + jz ERROR_requires_copro_capability_simd_int + .do: + shr al,1 + jc .registers_okay + mov cx,word[operand_registers+0] + mov word[operand_registers+1],cx + .registers_okay: + shr al,1 + jc SIMD_INT_vd_vn_vm.encode + mov ebp,[thumb32_instruction] + jmp SIMD_INT_vd_vn_vmx.encode + +SIMD_FLOAT_vd_vn_vmx_alt_f32: + ;used by VMUL.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;0=ddn,dm[x] + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\ ;1=dd,dn,dm[x] + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;2=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_vfpdx_reg>,\ ;4=qdn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;5=qd,qn,dm[x] + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;6=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;7=qd,qn,qm + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;8=sdn,sm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;9=sd,sn,sm + cmp al,8 + jae .vfp_alias + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + mov [thumb32_instruction],0xf2a00940 ;scalar + jmp SIMD_INT_vd_vn_vmx_alt.do + .vfp_alias: + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + sub al,8 + jmp VFP_sd_sn_sm.v1xd_test + +SIMD_INT_dd_dn_dm_alt: + ;used by VPADD.I8, VPADD.I16, VPADD.I32, VPMAX.S8, VPMAX.S16, VPMAX.S32, VPMAX.U8, VPMAX.U16, VPMAX.U32 + ; VPMIN.S8, VPMIN.S16, VPMIN.S32, VPMIN.U8, VPMIN.U16, VPMIN.U32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;1=dd,dn,dm + jmp SIMD_INT_vd_vn_vm_alt.encode + +SIMD_FLOAT_dd_dn_dm_alt: + ;used by VPADD.F32, VPMAX.F32, VPMIN.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;1=dd,dn,dm + jmp SIMD_FLOAT_vd_vn_vm_alt.float_test + +SIMD_INT_list: + ;used by VPOP, VPUSH + call decode_template + TEMPLATE \ + <TMPL_vfp_reg_list_s>,\ ;0={s..} + <TMPL_vfp_reg_list_d> ;1={d..} + cmp al,0 + mov [operand_register0],13 ;SP + mov al,1 ;rn! + jz VFP_rn_list_s.do + or ebp,0x00000100 + jmp VFP_rn_list_d.do + +SIMD_INT_list.32: + ;used by VPOP, VPUSH + call decode_template + TEMPLATE \ + <TMPL_vfp_reg_list_s> ;0={s..} + mov [operand_register0],13 ;SP + mov al,1 ;rn! + jmp VFP_rn_list_s.do + +SIMD_INT_list.64: + ;used by VPOP, VPUSH + call decode_template + TEMPLATE \ + <TMPL_vfp_reg_list_d> ;0={d..} + mov [operand_register0],13 ;SP + mov al,1 ;rn! + jmp VFP_rn_list_d.do + +SIMD_INT_dd_qm_imm: + ;used by VQRSHRN.S16, VQRSHRN.S32, VQRSHRN.S64, VQRSHRN.U16, VQRSHRN.U32, VQRSHRN.U64, + ; VQRSHRUN.S16, VQRSHRUN.S32, VQRSHRUN.S64, VQSHRN.S16, VQSHRN.S32, VQSHRN.S64, + ; VQSHRN.U16, VQSHRN.U32, VQSHRN.U64, VQSHRUN.S16, VQSHRUN.S32, VQSHRUN.S64, + ; VRSHRUN.I16, VRSHRUN.I32, VRSHRUN.I64, VSHRN.I16, VSHRN.I32, VSHRN.I64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_simd_qreg,TMPL_imm> ;0=dd,qm,imm + .encode: + mov ecx,ebp + mov edx,ebp + shr ecx,16 + shr edx,7-6 + and ecx,0x3f + and edx,0x40 + or ecx,edx + mov edx,ecx + sub ecx,[immediate_value] + shl ecx,16 + or ebp,ecx + shr ecx,16 + dec edx + not edx + test ecx,edx + jz SIMD_INT_vd_vm.int_test + mov ecx,ERROR_shift_value_out_of_range.1_8 + mov eax,ERROR_shift_value_out_of_range.1_16 + test edx,1 shl 3 + cmovz ecx,eax + mov eax,ERROR_shift_value_out_of_range.1_32 + test edx,1 shl 4 + cmovz ecx,eax + mov eax,ERROR_shift_value_out_of_range.1_64 + test edx,1 shl 5 + cmovz ecx,eax + jmp ARM_post_process_simd_with_error + +SIMD_INT_vd_vn_vm_imm_alt: + ;used by VQSHL.S8, VQSHL.S16, VQSHL.S32, VQSHL.S64, VQSHL.U8, VQSHL.U16, VQSHL.U32, VQSHL.U64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=ddn,dm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;2=dd,dm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;3=dd,dn,dm + <TMPL_simd_qreg,TMPL_imm>,\ ;4=qdm,imm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;5=qdn,qm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\ ;6=qd,qm,imm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;7=qd,qn,qm + shr al,1 + jc SIMD_INT_vd_vn_vm_alt.encode + mov ebp,[thumb32_instruction] + .encode: + shr al,1 + jc .registers_okay + mov cl,[operand_register0] + mov [operand_register1],cl + .registers_okay: + mov ecx,ebp + mov edx,ebp + shr ecx,16 + shr edx,7-6 + and ecx,0x3f + and edx,0x40 + or edx,ecx + mov ecx,[immediate_value] + shl ecx,16 + or ebp,ecx + cmp edx,[immediate_value] + ja SIMD_INT_vd_vm.int_test + mov ecx,ERROR_shift_value_out_of_range.0_7 + mov eax,ERROR_shift_value_out_of_range.0_15 + test edx,1 shl 4 + cmovnz ecx,eax + mov eax,ERROR_shift_value_out_of_range.0_31 + test edx,1 shl 5 + cmovnz ecx,eax + mov eax,ERROR_shift_value_out_of_range.0_63 + test edx,1 shl 6 + cmovnz ecx,eax + jmp ARM_post_process_simd_with_error + +SIMD_INT_vd_vm_imm_alt: + ;used by VQSHLU.S8, VQSHLU.S16, VQSHLU.S32, VQSHLU.S64, + ; VSHL.I8, VSHL.I16, VSHL.I32, VSHL.I64, VSLI.8, VSLI.16, VSLI.32, VSLI.64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,imm + <TMPL_simd_qreg,TMPL_imm>,\ ;2=qdm,imm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm> ;3=qd,qm,imm + jmp SIMD_INT_vd_vn_vm_imm_alt.encode + +SIMD_INT_vd_vm_imm_alt_neg: + ;used by VRSHR.S8, VRSHR.S16, VRSHR.S32, VRSHR.S64, VRSHR.U8, VRSHR.U16, VRSHR.U32, VRSHR.U64, + ; VRSRA.S8, VRSRA.S16, VRSRA.S32, VRSRA.S64, VRSRA.U8, VRSRA.U16, VRSRA.U32, VRSRA.U64, + ; VSHR.S8, VSHR.S16, VSHR.S32, VSHR.S64, VSHR.U8, VSHR.U16, VSHR.U32, VSHR.U64, + ; VSRA.S8, VSRA.S16, VSRA.S32, VSRA.S64, VSRA.U8, VSRA.U16, VSRA.U32, VSRA.U64, + ; VSRI.8, VSRI.16, VSRI.32, VSRI.64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_imm>,\ ;0=ddm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\ ;1=dd,dm,imm + <TMPL_simd_qreg,TMPL_imm>,\ ;2=qdm,imm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm> ;3=qd,qm,imm + shr al,1 + jc .registers_okay + mov cl,[operand_register0] + mov [operand_register1],cl + .registers_okay: + jmp SIMD_INT_dd_qm_imm.encode + +SIMD_FLOAT_vd_vm: + ;used by VRECPE.F32, VRSQRTE.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_simd_qreg,TMPL_simd_qreg> ;1=qd,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT + jz ERROR_requires_copro_capability_simd_float + jmp SIMD_INT_vd_vm.encode + +SIMD_INT_qd_dm_imm: + ;used by VSHLL.S8, VSHLL.S16, VSHLL.S32, VSHLL.U8, VSHLL.U16, VSHLL.U32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_imm> ;0=qd,qm,imm + mov ecx,[immediate_value] + mov edx,ebp + and edx,0x3f shl 16 + rol ecx,16 + or ebp,ecx + cmp ecx,edx ;imm=size? + jz .imm_eq_size + dec edx + and edx,0x3f shl 16 + not edx + test ecx,edx + jz SIMD_INT_vd_vm.int_test + mov ecx,ERROR_shift_value_out_of_range.0_8 + mov eax,ERROR_shift_value_out_of_range.0_16 + test edx,1 shl (3+16) + cmovz ecx,eax + mov eax,ERROR_shift_value_out_of_range.0_32 + test edx,1 shl (4+16) + cmovz ecx,eax + jmp ARM_post_process_simd_with_error + .imm_eq_size: + mov ebp,[thumb32_instruction] + jmp SIMD_INT_vd_vm.int_test + +SIMD_INT_qd_dm_imm_I: + ;used by VSHLL.I8, VSHLL.I16, VSHLL.I32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_imm> ;0=qd,qm,imm + mov ecx,ebp + shr ecx,18 + and ecx,3 + mov edx,8 + shl edx,cl + mov ecx,[immediate_value] + cmp ecx,edx ;imm=size? + jz SIMD_INT_vd_vm.int_test + mov ecx,ERROR_shift_value_out_of_range.8 + mov eax,ERROR_shift_value_out_of_range.16 + cmp edx,16 + cmovz ecx,eax + mov eax,ERROR_shift_value_out_of_range.32 + cmp edx,32 + cmovz ecx,eax + jmp ARM_post_process_simd_with_error + +SIMD_dn_list_dm: + ;used by VTBL.8, VTBX.8 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfp_reg_list_d,TMPL_comma,TMPL_vfpd_reg> ;0=dd,{dn,..},dm + mov edx,[reg_list_bitmap] + bsf eax,edx + bsr ecx,edx + ;check for a contiguous set + xor ecx,31 + shl edx,cl + add ecx,eax + sar edx,cl + inc edx + mov ecx,ERROR_non_contiguous_set + jnz ARM_post_process_simd_with_error + mov ecx,[reg_list_bitmap] + bsf eax,ecx ;eax=start register + bsr edx,ecx + sub edx,eax ;edx=register count - 1 + cmp edx,3 + mov ecx,ERROR_register_list_invalid ;too many registers + ja ARM_post_process_simd_with_error + shl edx,8 + or ebp,edx + mov cl,[operand_register1] ;dm + mov [operand_register2],cl ;dm + add eax,eax + mov ah,al + shr ah,5 + and ax,0x011e + or al,ah + mov [operand_register1],al ;dn + xor eax,eax + jmp SIMD_INT_vd_vn_vm.int_test + +SIMD_FLOAT_dd_sm_CVT: + ;used by VCVT.F64.S32, VCVT.F64.U32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfps_reg>,\ ;0=dd,sm + <TMPL_vfpd_reg,TMPL_imm>,\ ;1=ddm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm> ;2=dd,dm,imm + sub al,1 + jc VFP_dd_sm.do + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + jmp VFP_dd_dd_imm.test_version + +SIMD_FLOAT_sd_dm_CVT: + ;used by VCVT.S32.F64, VCVT.U32.F64, + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfpd_reg>,\ ;0=sd,dm + <TMPL_vfpd_reg,TMPL_imm>,\ ;1=ddm,imm + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm> ;2=dd,dm,imm + sub al,1 + jc VFP_sd_dm.do + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + jmp VFP_dd_dd_imm.test_version + +VFP_FLOAT_dd_dn_dm: + ;used by FMACD, FNMACD, FMSCD, FNMSCD, VNMLA.F64, VNMLS.F64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=dd,dn,dm + mov al,1 + jmp VFP_dd_dn_dm.begin + +VFP_FLOAT_sd_sn_sm: + ;used by FMACS, FNMACS, FMSCS, FNMSCS, VNMLA.F32, VNMLS.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sn,sm + mov al,1 + jmp VFP_sd_sn_sm.v1xd_test + +;VFPv4 and SIMDv2 + +SIMD_FLOAT_vd_vn_vm: + ;used by VFMA.F32, VFMS.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;1=qd,qn,qm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;2=sd,sn,sm + cmp al,2 + jb .simdv2_test + .vfpv4_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V4 + jz ERROR_requires_copro_capability_vfp_v4 + movzx ebp,[instruction_condition] + and ebp,0xf0 + shl ebp,28-4 + or ebp,[thumb32_instruction] + jmp VFP_sd_sn_sm.registers_shifted + .simdv2_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V2 + jz ERROR_requires_copro_capability_simd_v2 + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_FLOAT_dd_dn_dm: + ;used by VFMA.F64, VFMS.F64, VFNMA.F64, VFNMS.F64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=dd,dn,dm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32 + jnz SIMD_FLOAT_vd_vn_vm.vfpv4_test + mov edx,[operand_registers] ;fd,fn,fm + test edx,0x010101 + jnz ERROR_requires_copro_capability_vfp_d32 + mov al,1 + jmp SIMD_FLOAT_vd_vn_vm.vfpv4_test + +SIMD_FLOAT_sd_sn_sm: + ;used by VFNMA.F32, VFNMS.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sn,sm + mov al,1 + jmp SIMD_FLOAT_vd_vn_vm.vfpv4_test + +;v7VE + +ARM_eret: + ;used by ERET + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE + jz ERROR_requires_cpu_capability_arm_ve + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_eret + jmp ARM_store_instruction + .THUMB_eret: + or [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT + or [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_immediate16_ve: + ;used by HVC + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE + jz ERROR_requires_cpu_capability_arm_ve + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB + mov eax,[immediate_value] + cmp eax,0x0000ffff + ja .out_of_range + mov ecx,eax + and eax,0xf + and ecx,0xfff0 + shl ecx,4 + or eax,ecx + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0xffff + jmp ARM_store_instruction_with_error + .THUMB: + or [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + or [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + mov [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xffff + mov eax,[immediate_value] + cmp eax,0xffff + ja THUMB_post_process + mov ecx,eax + and eax,0xfff + and ecx,0xf000 + shl ecx,4 + or eax,ecx + or [thumb32_instruction],eax + mov [thumb32_error],0 + jmp THUMB_post_process + +;v8 + +ARM_immediate16_v8: + ;used by HLT + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_immediate6 + mov eax,[immediate_value] + cmp eax,0x0000ffff + ja .out_of_range + mov ecx,eax + and eax,0xf + and ecx,0xfff0 + shl ecx,4 + or eax,ecx + or ebp,eax + jmp ARM_store_instruction + .out_of_range: + mov ecx,ERROR_immediate_offset_out_of_range.0_0xffff + jmp ARM_store_instruction_with_error + .THUMB_immediate6: + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + mov [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3f + mov eax,[immediate_value] + cmp eax,0x3f + ja THUMB_post_process + or ax,0xba80 + mov [thumb16_instruction],ax + mov [thumb16_error],0 + jmp THUMB_post_process + +ARM_rt_q_rn_p: + ;used by STL, STLB, STLH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right> ;0=reg,[reg] + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rt_q_rn_p + movzx eax,[operand_register0] ;rt + cmp eax,15 + jz ERROR_r15_not_valid.first + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + jmp ARM_store_instruction + .THUMB_rt_q_rn_p: + mov cl,0x03 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rt + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rt_q_rn_p_STLEX: + ;used by STLEX, STLEXB, STLEXH + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,rm,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=rd,rm,[rn,imm] + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=rd,rm,[exp] + mov ecx,ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz ARM_store_instruction_with_error + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rt_q_rn_p_STLEX + movzx eax,[operand_register0] ;rd + cmp eax,0xf + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rt + cmp eax,0xf + jz ERROR_r15_not_valid.second + or ebp,eax + movzx eax,[operand_register2] ;rn + cmp eax,0xf + jz ERROR_r15_not_valid.third + shl eax,16 + or ebp,eax + mov al,[operand_register0] ;rd + mov ah,[operand_register1] ;rt + mov cl,[operand_register2] ;rn + cmp al,cl + jz ERROR_dest_cannot_be_source_or_memory_address + cmp al,ah + jz ERROR_dest_cannot_be_source_or_memory_address + jmp ARM_store_instruction + .THUMB_rd_rt_q_rn_p_STLEX: + mov ebp,[thumb32_instruction] + mov cl,0x07 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov [thumb32_error],ERROR_dest_cannot_be_source_or_memory_address + movzx eax,[operand_register0] ;rd + movzx ecx,[operand_register1] ;rt + movzx edx,[operand_register2] ;rn + cmp eax,ecx + jz THUMB_post_process + cmp eax,edx + jz THUMB_post_process + or ebp,eax + shl ecx,12 + or ebp,ecx + shl edx,16 + or ebp,edx + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +ARM_rd_rt_rt2_q_rn_p_STLEXD: + ;used by STLEXD + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\ ;0=rd,rt,[rn] + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right> ;1=rd,rt,rt2,[rn] + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + test [code_type],CPU_ACTIVITY_ARM + jz ARM_rd_rt_rt2_q_rn_p.THUMB_adjust_three_to_four + mov ecx,[operand_registers] ;rd,rt,rt2,rn + cmp al,1 + jnz .check_rt + mov eax,ecx + shr eax,8 + sub ah,1 + cmp ah,al + jnz ERROR_source_registers_must_be_consecutive + mov eax,ecx + shr ecx,8 + mov ch,cl + mov cl,al + .check_rt: + test ch,1 + jnz ERROR_source_register_must_be_even + cmp ch,14 + jz ERROR_r14_not_valid.second + mov [operand_registers],ecx ;rd,rt,rn + inc ch + cmp ch,cl + jz ERROR_source_and_dest_must_differ + jmp ARM_rd_rm_q_rn_p_STREX.version_okay + +THUMB_v8: + ;used by DCPS1, DCPS2, DCPS3 + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [code_type],CPU_ACTIVITY_ARM + jnz ERROR_instruction_not_32bit + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8 + jz ERROR_requires_cpu_capability_arm_v8 + mov [thumb32_error],0 + jmp THUMB_post_process + +SIMD_sd_sm: + ;used by VCVTM.S32.F32, VCVTM.U32.F32, VCVTN.S32.F32, VCVTN.U32.F32, VCVTP.S32.F32, VCVTP.U32.F32, VCVTA.S32.F32, VCVTA.U32.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg>,\ ;0=sd,sm + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;1=dd,dm + <TMPL_simd_qreg,TMPL_simd_qreg> ;2=qd,qm + .do: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V8 + jz ERROR_requires_copro_capability_simd_v8 + cmp al,0 + jz .encode + mov ebp,[thumb32_instruction] ;get the SIMD encoding + cmp al,2 + jnz .encode + or ebp,1 shl 6 ;set the Q bit + .encode: + movzx eax,[operand_register0] ;fd + xor ecx,ecx + shr eax,1 + setc cl + shl eax,12 + shl ecx,22 + or ebp,eax + or ebp,ecx + movzx eax,[operand_register1] ;fm + xor ecx,ecx + shr eax,1 + setc cl + shl ecx,5 + or ebp,eax + or ebp,ecx + xor ecx,ecx ;clear the error code + test [code_type],CPU_ACTIVITY_ARM + jnz ARM_store_instruction + cmp ebp,0xf0000000 + jb ARM_post_process_copro.thumb + jmp ARM_post_process_simd + +SIMD_sd_dm: + ;used by VCVTM.S32.F64, VCVTM.U32.F64, VCVTN.S32.F64, VCVTN.U32.F64, VCVTP.S32.F64, VCVTP.U32.F64, VCVTA.S32.F64, VCVTA.U32.F64 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfpd_reg> ;0=sd,dm + jmp SIMD_sd_sm.do + +VFP_sd_dm_HP: + ;used by VCVTB.F16.F64, VCVTT.F16.F64 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfpd_reg> ;0=sd,dm + jmp SIMD_sd_sm.do + +VFP_dd_sm_HP: + ;used by VCVTB.F64.F16, VCVTT.F64.F16 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfps_reg> ;0=dd,sm + jmp SIMD_sd_sm.do + +SIMD_FLOAT_vd_vn_vm_v8: + ;used by VMAXNM.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dn,dm + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;1=qd,qn,qm + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;2=sd,sn,sm + .v8_test: + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V8 + jz ERROR_requires_copro_capability_simd_v8 + cmp al,2 + jz .encode + mov ebp,[thumb32_instruction] ;get the SIMD encoding + test [code_type],CPU_ACTIVITY_ARM + jnz .encode + ;in THUMB mode no v8 SIMD instructions can be conditional + mov ah,[instruction_condition] + and ah,0xf0 + cmp ah,0xe0 + jb ERROR_instruction_not_conditional + .encode: + and al,1 ;extract the Q bit + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_FLOAT_sd_sn_sm_v8: + ;used by VSELEQ.F32, VSELVS.F32, VSELGE.F32, VSELGT.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sn,sm + jmp SIMD_FLOAT_vd_vn_vm_v8.v8_test + +SIMD_FLOAT_dd_dn_dm_v8: + ;used by VMAXNM.F64, VSELEQ.F64, VSELVS.F64, VSELGE.F64, VSELGT.F64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=dd,dn,dm + jmp SIMD_FLOAT_vd_vn_vm_v8.v8_test + +SIMD_FLOAT_vd_vn_v8: + ;used by VRINTM.F32.F32, VRINTN.F32.F32, VRINTP.F32.F32, VRINTA.F32.F32, VRINTX.F32.F32, VRINTZ.F32.F32 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg>,\ ;0=dd,dm + <TMPL_simd_qreg,TMPL_simd_qreg>,\ ;1=qd,qm + <TMPL_vfps_reg,TMPL_vfps_reg> ;2=sd,sm + .do: + mov cl,[operand_register1] + mov [operand_register1],0 + mov [operand_register2],cl + jmp SIMD_FLOAT_vd_vn_vm_v8.v8_test + +SIMD_FLOAT_sd_sn_v8: + ;used by VRINTR.F32.F32 + call decode_template + TEMPLATE \ + <TMPL_vfps_reg,TMPL_vfps_reg> ;0=sd,sm + mov al,2 + jmp SIMD_FLOAT_vd_vn_v8.do + +SIMD_FLOAT_dd_dn_v8: + ;used by VRINTM.F64.F64, VRINTN.F64.F64, VRINTP.F64.F64, VRINTA.F64.F64, VRINTX.F64.F64, VRINTR.F64.F64, VRINTZ.F64.F64 + call decode_template + TEMPLATE \ + <TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=dd,dm + mov al,2 + jmp SIMD_FLOAT_vd_vn_v8.do + +ARM_rd_rn_rm_crc: + ;used by CRC32B + call decode_template + TEMPLATE \ + <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg> ;0=reg,reg,reg + test [cpu_capability_flags],1 shl CPU32_CAPABILITY_CRC + jz ERROR_requires_cpu_capability_crc + test [code_type],CPU_ACTIVITY_ARM + jz .THUMB_rd_rn_rm + movzx eax,[operand_register0] ;rd + cmp eax,15 + jz ERROR_r15_not_valid.first + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] ;rn + cmp eax,15 + jz ERROR_r15_not_valid.second + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + cmp eax,15 + jz ERROR_r15_not_valid.third + or ebp,eax + and ebp,not 0x10000000 ;force to 0xE... opcode + jmp ARM_store_instruction + .THUMB_rd_rn_rm: + mov cl,0x07 + call THUMB2_check_bad_regs + jc THUMB_post_process + mov ebp,[thumb32_instruction] + movzx eax,[operand_register0] ;rd + shl eax,8 + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] ;rm + or ebp,eax + mov [thumb32_instruction],ebp + mov [thumb32_error],0 + jmp THUMB_post_process + +SIMD_CRYPTO_qd_qm: + ;used by AESD.8, AESE.8, AESIMC.8, AESMC.8, SHA1H.32, SHA1SU1.32, SHA256SU0.32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_simd_qreg> ;0=qd,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO + jz ERROR_requires_copro_capability_simd_crypto + mov cl,[operand_register1] + mov [operand_register1],0 + mov [operand_register2],cl + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_CRYPTO_qd_qn_qm: + ;used by SHA1C.32, SHA1P.32, SHA1M.32, SHA1SU0.32, SHA256H.32, SHA256H2.32, SHA256SU1.32 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg> ;0=qd,qn,qm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO + jz ERROR_requires_copro_capability_simd_crypto + jmp SIMD_INT_vd_vn_vm.encode + +SIMD_INT_qd_dn_dm: + ;used by VMULL.P64 + call decode_template + TEMPLATE \ + <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg> ;0=qd,dn,dm + test [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO + jz ERROR_requires_copro_capability_simd_crypto + jmp SIMD_INT_vd_vn_vm.encode + +;v8 64 bit + +ARM64_encode_bitmask: + ;create N:immr:imms from immediate_value_high:immediate_value + ;return carry = true if failed + ;return eax = N:immr:imms if successful + ;first stage: find the smallest unit that can be replicated + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ebx,64 ;ebx = current replicate bit size + cmp edx,eax + jnz .find_rotation + shr ebx,1 ;32 + ror edx,16 + cmp dx,ax + jnz .find_rotation + shr ebx,1 ;16 + cmp ah,al + jnz .find_rotation + shr ebx,1 ;8 + ror ah,4 + cmp ah,al + jnz .find_rotation + shr ebx,1 ;4 + ror ah,2 + cmp ah,al + jnz .find_rotation + shr ebx,1 ;2 + cmp al,-1 ;all ones? + jz .cannot_encode + .find_rotation: + push ebx + ;second stage: find a rotation that puts all the bits at the lower end + cmp bl,64 + jz .mask_done + mov ecx,ebx + neg ecx + rol eax,cl + cdq + sar eax,cl + .mask_done: + ;count leading 1's + not edx + not eax + bsr ecx,edx + lea ecx,[ecx+32] + jnz .leading_ones_count_okay + bsr ecx,eax + .leading_ones_count_okay: + not edx + not eax + not ecx + and ecx,0x3f + jnz .rotate_and_check + ;count trailing 0's + bsf ecx,eax + jnz .trailing_zeros_count_okay + bsf ecx,edx + jz .zero_value + add ecx,32 + .trailing_zeros_count_okay: + ;invert the count + sub ecx,64 + neg ecx + and ecx,0x3f + .rotate_and_check: + push ecx + ;rotate left by ecx bits + cmp ecx,32 + jb .rotate_small + xchg edx,eax + .rotate_small: + mov ebx,eax + shld eax,edx,cl + shld edx,ebx,cl + ;check that it is one less than a power of 2 + mov ecx,eax + mov ebx,edx + add ecx,1 + adc ebx,0 + and eax,ecx + and edx,ebx + or eax,edx + jnz .fail + ;get the bit size + bsf eax,ecx + jnz .trailing_zeros_count_okay2 + bsf eax,ebx + add eax,32 + .trailing_zeros_count_okay2: + dec eax ;get length (imms) + pop ecx ;get rotation (immr) + pop ebx ;get replicate bit size + lea edx,[ebx-1] + and eax,edx + and ecx,edx + not edx + shl edx,1 + or eax,edx + and eax,0x3f + shl ecx,6 + or eax,ecx + and ebx,0x40 + shl ebx,12-6 + or eax,ebx + ;success + clc + ret + .fail: + pop eax ;dummy to restore stack + .zero_value: + pop eax ;dummy to restore stack + .cannot_encode: + stc + ret + +ARM64_dz_nz_mz: + ;used by ADC, ADCS, MNEG, SBC, SBCS, SDIV, UDIV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg> ;1=xd,xn,xm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + .do: + mov ebp,[arm64_instruction] ;recover the template + shl eax,31 + or ebp,eax ;set sf + .encode_rd: + movzx eax,[operand_register0] ;rd + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,5 + or ebp,eax + movzx eax,[operand_register2] ;rm + shl eax,16 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_wz_wz_wz: + ;used by CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, CRC32CW + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg> ;0=wd,wn,wm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_CRC shr 32 + jz ERROR_requires_cpu64_capability_crc + jmp ARM64_dz_nz_mz.do + +ARM64_wz_wz_xz: + ;used by CRC32X, CRC32CX + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_dword_z_reg> ;0=wd,wn,xm + jmp ARM64_wz_wz_wz.encode + +ARM64_xz_xz_xz: + ;used by SMULH + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg> ;0=xd,xn,xm + jmp ARM64_dz_nz_mz.encode + +ARM64_dz_nz_mz_az: + ;used by MADD, MSUB + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn,wm,wa + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg> ;1=xd,xn,xm,xa + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + shl eax,31 + or ebp,eax ;set sf + .encode_rd: + movzx eax,[operand_register0] ;rd + or ebp,eax + movzx eax,[operand_register1] ;rn + shl eax,5 + or ebp,eax + movzx eax,[operand_register2] ;rm + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;ra + shl eax,10 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_dx_nw_mw_ax: + ;used by SMADDL, SMSUBL, UMADDL, UMSUBL + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_dword_z_reg> ;0=xd,wn,wm,xa + jmp ARM64_dz_nz_mz_az.encode + +ARM64_dx_nw_mw: + ;used by SMNEGL, UMNEGL + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg> ;0=xd,wn,wm + jmp ARM64_dz_nz_mz_az.encode + +ARM64_dz_nw: + ;used by SXTB, SXTH + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn + <TMPL_dword_z_reg,TMPL_word_z_reg> ;1=xd,wn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx ecx,al + shl ecx,22 + shl eax,31 + or ebp,ecx ;set N + or ebp,eax ;set sf + jmp ARM64_dz_nz_mz.encode_rd + +ARM64_dw_nw: + ;used by UXTB, UXTH + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg> ;0=wd,wn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + jmp ARM64_dz_nz_mz.encode + +ARM64_dx_nw: + ;used by SXTW + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_word_z_reg> ;0=xd,wn + jmp ARM64_dz_nz_mz.encode + +ARM64_arithmetic1: + ;used by ADD, ADDS, SUB, SUBS + bt ecx,29 + jnc .non_S + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_sp_reg>,\ ; 0=wd,wn,wm (reversed sp without imm) + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 1=wd,wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\ ; 2=wd,wn,wm,shift imm + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ; 3=wd,wn,wm,extend + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\ ; 4=wd,wn,wm,extend imm + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\ ; 5=wd,wn,wm,lsl imm + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\ ; 6=wd,wn,wm (catch sp without imm) + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_imm>,\ ; 7=wd,wn,imm + <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 8=wd,wn,imm,lsl imm2 + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_sp_reg>,\ ; 9=xd,xn,xm (reversed sp without imm) + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;10=xd,xn,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\ ;11=xd,xn,xm,shift imm + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\ ;12=xd,xn,xm,extend + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\ ;13=xd,xn,xm,extend imm + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\ ;14=xd,xn,xm,lsl imm + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\ ;15=xd,xn,xm (catch sp without imm) + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_imm>,\ ;16=xd,xn,imm + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;17=xd,xn,imm,lsl imm2 + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ;18=xd,xn,wm,extend + <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm> ;19=xd,xn,wm,extend imm + jmp .encode + .non_S_adjust_table: + db 1,2,3,4,5,6,7,8,0 + db 10,11,12,13,14,15,16,17,18,19,9 + db 20,21,22,23,24,25,26,27 + .non_S: + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 0=wd,wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\ ; 1=wd,wn,wm,shift imm + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ; 2=wd,wn,wm,extend + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\ ; 3=wd,wn,wm,extend imm + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\ ; 4=wd,wn,wm,lsl imm + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\ ; 5=wd,wn,wm (catch sp without imm) + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_imm>,\ ; 6=wd,wn,imm + <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 7=wd,wn,imm,lsl imm2 + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_word_sp_reg>,\ ; 8=wd,wn,wm (reversed sp without imm) + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ; 9=xd,xn,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\ ;10=xd,xn,xm,shift imm + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\ ;11=xd,xn,xm,extend + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\ ;12=xd,xn,xm,extend imm + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\ ;13=xd,xn,xm,lsl imm + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\ ;14=xd,xn,xm (catch sp without imm) + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_imm>,\ ;15=xd,xn,imm + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;16=xd,xn,imm,lsl imm2 + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ;17=xd,xn,wm,extend + <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\ ;18=xd,xn,wm,extend imm + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_dword_sp_reg>,\ ;19=xd,xn,xm (reversed sp without imm) + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;20=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;21=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;22=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;23=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;24=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;25=vd,vn,vm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\ ;26=dd,dn,dm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d> ;27=vd,vn,vm + movzx eax,al + mov al,[.non_S_adjust_table+eax] + .encode: + mov ebp,[arm64_instruction] ;recover the template + cmp al,20 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + cmp al,9 + cmc + sbb ecx,ecx + and cl,9 + sub al,cl + mov cl,ch + shl ecx,31 + or ebp,ecx ;set sf + cmp al,0 + jnz .swap_okay + bt ebp,30 ;sub? + jc ERROR_parameter_n_not_valid.third ;can't swap r,r,sp with sub + mov cl,[operand_register1] + mov ch,[operand_register2] + mov [operand_register1],ch + mov [operand_register2],cl + add al,6 + .swap_okay: + cmp al,9 + jae .extended_register_xxw + cmp al,2 + jbe .shifted_register + cmp al,6 + ja .immediate + jmp .extended_register + .extended_register_xxw: + mov cl,[instruction_shift_op] + and cl,0x3 + cmp cl,0x3 + jz ERROR_parameter_n_not_valid.third ;can't have w with [su]xtx + sub al,7 + .extended_register: + or ebp,0x59 shl 21 + ;set lsl + cmp al,5 + jz .set_lsl + cmp al,6 + jnz .lsl_okay + .set_lsl: + test ebp,ebp + sets cl + add cl,2 + mov [instruction_shift_op],cl + .lsl_okay: + movzx ecx,[instruction_shift_op] + shl ecx,13 + or ebp,ecx + mov edx,[immediate_value] + cmp edx,4 + ja ERROR_shift_value_out_of_range.0_4 + jmp .encode_immediate + .shifted_register: + or ebp,0xb shl 24 + .encode_shifted_register: + movzx eax,[instruction_shift_op] + shl eax,22 + or ebp,eax + mov ecx,ERROR_shift_value_out_of_range.0_63 + mov edx,ERROR_shift_value_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + mov edx,[immediate_value] + cmp edx,eax + jae ARM_store_instruction_with_error + .encode_immediate: + shl edx,10 + or ebp,edx + .encode_rm: + movzx eax,[operand_register2] + shl eax,16 + or ebp,eax + .encode_rn: + movzx eax,[operand_register1] + shl eax,5 + or ebp,eax + .encode_rd: + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + .immediate: + or ebp,0x11 shl 24 + mov edx,[immediate_value] + test edx,edx + jz .encode_immediate + jns .immediate_positive + neg edx + xor ebp,1 shl 30 ;invert the operation ADD<-->SUB + .immediate_positive: + mov ecx,[immediate_value2] + cmp ecx,32 + jae .immediate_out_of_range + xor eax,eax + shld eax,edx,cl + test eax,eax + jnz .immediate_out_of_range + shl edx,cl + cmp edx,0xfff + jbe .encode_immediate + or ebp,1 shl 22 ;enable lsl 12 + test edx,0xfff + jnz .immediate_out_of_range + shr edx,12 + cmp edx,0xfff + jbe .encode_immediate + .immediate_out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_0xfff_lsl_12 + jmp ARM_store_instruction_with_error + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + and ebp,1 shl 30 ;isolate the add/sub bit + shr ebp,1 + or ebp,0x0e208400 + sub al,18+2 + .vector_encode: + cmp al,6 ;scalar? + setz dl + shr al,1 + setc cl + shl ecx,30 + or ebp,ecx ;set Q + mov ah,0 + shl eax,22 + or ebp,eax ;set size + neg dl + and dl,5 + shl edx,28 + or ebp,edx ;set for scalar + jmp .encode_rm + +ARM64_arithmetic1_zr: + ;used by CMN, CMP + call decode_template + TEMPLATE \ + <TMPL_never>,\ ; 0=sp swap not valid + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 1=wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\ ; 2=wn,wm,shift imm + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ; 3=wn,wm,extend + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\ ; 4=wn,wm,extend imm + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\ ; 5=wn,wm,lsl imm + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\ ; 6=wn,wm (catch sp without imm) + <TMPL_word_s_reg,TMPL_imm>,\ ; 7=wn,imm + <TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 8=wn,imm,lsl imm2 + <TMPL_never>,\ ; 9=sp swap not valid + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;10=xn,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\ ;11=xn,xm,shift imm + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\ ;12=xn,xm,extend + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\ ;13=xn,xm,extend imm + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\ ;14=xn,xm,lsl imm + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\ ;15=xn,xm (catch sp without imm) + <TMPL_dword_s_reg,TMPL_imm>,\ ;16=xn,imm + <TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;17=xn,imm,lsl imm2 + <TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\ ;18=xn,wm,extend + <TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm> ;19=xd,xn,wm,extend imm + mov edx,[operand_registers] + shl edx,8 + or edx,0x1f + mov [operand_registers],edx + jmp ARM64_arithmetic1.encode + +ARM64_arithmetic2: + ;used by AND, ANDS, BIC, BICS, EOR, EON, ORN, ORR + test al,FLAG_CONDITION_SET + setnz bl + shl ebx,30 + or ecx,ebx + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 0=wd,wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\ ; 1=wd,wn,wm,shift imm + <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_imm>,\ ; 2=wd,wn,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ; 3=xd,xn,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\ ; 4=xd,xn,xm,shift imm + <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_imm64>,\ ; 5=xd,xn,imm + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 6=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 7=vd,vn,vm + <TMPL_vect_v4h,TMPL_imm>,\ ; 8=vd,imm + <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 9=vd,imm,lsl imm + <TMPL_vect_v8h,TMPL_imm>,\ ;10=vd,imm + <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;11=vd,imm,lsl imm + <TMPL_vect_v2s,TMPL_imm>,\ ;12=vd,imm + <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;13=vd,imm,lsl imm + <TMPL_vect_v4s,TMPL_imm>,\ ;14=vd,imm + <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2> ;15=vd,imm,lsl imm + mov ebp,[arm64_instruction] ;recover the template + .encode: + cmp al,6 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + cmp al,3 + cmc + sbb ecx,ecx + and cl,3 + sub al,cl + mov cl,ch + shl ecx,31 + or ebp,ecx ;set sf + cmp al,2 + je .immediate + .shifted_register: + or ebp,0xa shl 24 + jmp ARM64_arithmetic1.encode_shifted_register + .immediate: + btr ebp,21 + jnc .inversion_okay + .invert: + ;for BIC, BICS, EON and ORN the immediate is inverted + mov ecx,[immediate_value] + mov edx,[immediate_value_high] + not ecx + not edx + mov [immediate_value],ecx + mov [immediate_value_high],edx + .inversion_okay: + or ebp,0x12 shl 24 + js .immediate_prepared + mov eax,[immediate_value] + mov [immediate_value_high],eax + .immediate_prepared: + call ARM64_encode_bitmask + mov ecx,ERROR_immediate_cannot_be_encoded + jc ARM_store_instruction_with_error + mov edx,eax + jmp ARM64_arithmetic1.encode_immediate + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + ;S forms are invalid + test [instruction_condition],FLAG_CONDITION_SET + jnz ERROR_parameter_n_not_valid.first + ;EON is invalid + mov ecx,ebp + and ecx,3 shl 29 + 1 shl 21 + cmp ecx,2 shl 29 + 1 shl 21 + jz ERROR_parameter_n_not_valid.first + cmp al,8 + jae .vector_immediate + mov ecx,ebp + mov edx,ebp + and ebp,1 shl 30 + and ecx,1 shl 29 + and edx,1 shl 21 + shr ebp,30-29 + shr ecx,29-23 + shl edx,22-21 + or ebp,ecx + or ebp,edx + or ebp,0x0e201c00 + sub al,6 + jmp ARM64_arithmetic1.vector_encode + .vector_immediate: + ;EOR is invalid + test ebp,1 shl 30 + jnz ERROR_parameter_n_not_valid.first + mov edx,[immediate_value] + test al,4 + setz bl + mov bh,0 + shl ebx,16 + neg ebx + test edx,ebx + jz .primary_range_okay + xor edx,ebx + test edx,ebx + jnz .out_of_range + .primary_range_okay: + not ebx + ;invert AND + test ebp,ebp + jz .vector_invert + ;invert ORN + cmp ebp,1 shl 29 + 1 shl 21 + jnz .vector_invert_okay + .vector_invert: + ;for AND and ORN the immediate is inverted + xor edx,ebx + ;convert AND to BIC and ORN to ORR + xor ebp,1 shl 21 + .vector_invert_okay: + ;build the number + test edx,edx + jz .immediate_built + mov ecx,[immediate_value2] + cmp cl,32 + jae .out_of_range + push ebx + xor ebx,ebx + shld ebx,edx,cl + test ebx,ebx + pop ebx + jnz .out_of_range + shl edx,cl + not ebx + test edx,ebx + jnz .out_of_range + .immediate_built: + and ebp,1 shl 21 + shl ebp,29-21 + or ebp,0x0f001400 + sub al,8 + test al,2 + setnz cl + shl ecx,30 + or ebp,ecx ;set Q + test al,4 + setz cl + shl ecx,15 + or ebp,ecx ;set cmode = x001b + shr ecx,14 + sub ecx,4 + neg ecx + xor ebx,ebx + .try_immediate: + cmp edx,0xff + jbe .immediate_ready + test edx,0xff + jnz .out_of_range + shr edx,8 + inc bl + cmp bl,cl + jae .out_of_range + jmp .try_immediate + .immediate_ready: + shl ebx,13 + or ebp,ebx + mov eax,edx + and edx,0x1f + and eax,0xe0 + shl edx,5 + shl eax,16-5 + or ebp,edx + or ebp,eax + jmp ARM64_arithmetic1.encode_rd + .out_of_range: + test ebp,1 shl 15 + mov ecx,ERROR_immediate_value_out_of_range.0_0xff_lsl_8 + mov edx,ERROR_immediate_value_out_of_range.0_0xff_lsl_24 + cmovz ecx,edx + jmp ARM_store_instruction_with_error + +ARM64_arithmetic3: + ;used by ASR, LSL, LSR, ROR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm>,\ ;1=wd,wn,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;2=wd,wn,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm> ;3=wd,wn,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + cmp al,2 + setae cl + shl ecx,31 + or ebp,ecx ;set sf + and al,1 + jz ARM64_arithmetic1.encode_rm + ;immediate + test ebp,ebp + mov ecx,ERROR_shift_value_out_of_range.0_63 + mov edx,ERROR_shift_value_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + sets bl + movzx ebx,bl + shl ebx,22 + cmp eax,[immediate_value] + jbe ARM_store_instruction_with_error + test ebp,3 shl 10 + jnz .asr_lsr_ror + .lsl: + dec eax + mov edx,[immediate_value] + and ebp,1 shl 31 + or ebp,ebx ;set N + or ebp,0x53000000 + mov ecx,edx + neg edx + and edx,eax + sub eax,ecx + shl edx,16 + or ebp,edx + shl eax,10 + or ebp,eax + jmp ARM64_arithmetic1.encode_rm + .asr_lsr_ror: + mov edx,ebp + shl edx,30-10 + cmp edx,0xc0000000 + jae .ror + and edx,1 shl 30 + and ebp,1 shl 31 + or ebp,edx + or ebp,ebx ;set N + shr ebx,22-15 + or ebp,0x13007c00 + mov edx,[immediate_value] + shl edx,16 + .set_shift_and_N: + or ebp,edx + or ebp,ebx + jmp ARM64_arithmetic1.encode_rm + .ror: + and ebp,1 shl 31 + or ebp,0x13800000 + mov cl,[operand_register1] + mov [operand_register2],cl + mov edx,[immediate_value] + shl edx,10 + jmp .set_shift_and_N + +ARM64_arithmetic4: + ;used by CLS, CLZ + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;1=xd,xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;2=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ;3=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ;4=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h>,\ ;5=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;6=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s> ;7=vd,vn + mov ebp,[arm64_instruction] ;recover the template + cmp al,2 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + shl eax,31 + or ebp,eax ;set sf + jmp ARM64_arithmetic1.encode_rn + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + not ebp + and ebp,1 shl 10 + shl ebp,29-10 + or ebp,0x0e204800 + sub al,2 + jmp ARM64_arithmetic1.vector_encode + +ARM64_arithmetic5: + ;used by EXTR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm>,\ ;0=wd,wn,wm,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm> ;1=xd,xn,xm,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + shl eax,31 + or ebp,eax ;set sf + shr eax,31-22 + or ebp,eax ;set N + mov ecx,ERROR_shift_value_out_of_range.0_63 + mov edx,ERROR_shift_value_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + mov edx,[immediate_value] + cmp edx,eax + jae ARM_store_instruction_with_error + jmp ARM64_arithmetic1.encode_immediate + +ARM64_register_rotate: + ;used by ASRV, LSLV, LSRV, RORV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg> ;1=xd,xn,xm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + shl eax,31 + or ebp,eax ;set sf + jmp ARM64_arithmetic1.encode_rm + +ARM64_adr: + ;used by ADR, ADRP + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_address64> ;0=xd,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ecx,[addressing_space] + add eax,[ecx+0] + adc edx,[ecx+4] + sub eax,edi + sbb edx,0 + test ebp,ebp ;ADRP? + jns .offset_okay + shrd eax,edx,12 + sar edx,12 + .offset_okay: + mov ecx,edx + cdq + cmp ecx,edx + mov ecx,ERROR_branch_too_far + jnz ARM_store_instruction_with_error + cmp eax,0xfffff + jg ARM_store_instruction_with_error + cmp eax,-0x100000 + jl ARM_store_instruction_with_error + mov ecx,eax + and eax,0x1ffffc + and ecx,0x000003 + shl eax,5-2 + shl ecx,29 + or eax,ecx + or ebp,eax + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + +ARM64_sys_predefined_at: + ;used by AT + call decode_template + TEMPLATE \ + <TMPL_at_op,TMPL_dword_z_reg> ;0=at,xd + mov edx,sys_encode_table_at + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + mov eax,[immediate_value] + movzx ecx,word[edx+eax*2] + shl ecx,5 + or ebp,ecx + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + +ARM64_sys_predefined_dc: + ;used by DC + call decode_template + TEMPLATE \ + <TMPL_dc_op,TMPL_dword_z_reg> ;0=dc,xd + mov edx,sys_encode_table_dc + jmp ARM64_sys_predefined_at.encode + +ARM64_sys_predefined_ic: + ;used by IC + call decode_template + TEMPLATE \ + <TMPL_ic_op>,\ ;0=ic + <TMPL_ic_op,TMPL_dword_z_reg> ;1=ic,xd + mov edx,sys_encode_table_ic + .do: + mov cl,[operand_register0] + mov bl,0x1f ;defailt to xzr + test al,al + cmovz ecx,ebx + mov [operand_register0],cl + jmp ARM64_sys_predefined_at.encode + +ARM64_sys_predefined_tlbi: + ;used by TLBI + call decode_template + TEMPLATE \ + <TMPL_tlbi_op>,\ ;0=tlbi + <TMPL_tlbi_op,TMPL_dword_z_reg> ;1=tlbi,xd + mov edx,sys_encode_table_tlbi + jmp ARM64_sys_predefined_ic.do + +ARM64_sys_predefined_mrs: + ;used by MRS + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_msr_reg>,\ ;0=xd,sysreg (predefined) + <TMPL_dword_z_reg,TMPL_sysreg_dynamic> ;1=xd,sysreg (implementation defined) + test al,al + mov edx,sys_encode_table_msr + jz ARM64_sys_predefined_at.encode + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + .dynamic_reg: + mov ebp,[arm64_instruction] + mov ecx,[immediate_value] + shl ecx,5 + or ebp,ecx + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + +ARM64_sys_predefined_msr: + ;used by MSR + call decode_template + TEMPLATE \ + <TMPL_msr_reg,TMPL_dword_z_reg>,\ ;0=sysreg,xd + <TMPL_msr_reg,TMPL_imm2>,\ ;1=sysreg,imm (catch spsel) + <TMPL_pstate_reg,TMPL_imm2>,\ ;2=sysreg,imm + <TMPL_sysreg_dynamic,TMPL_dword_z_reg> ;3=sysreg,xd + test al,al + mov edx,sys_encode_table_msr + jz ARM64_sys_predefined_at.encode + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + cmp al,2 + jz .pstate + cmp al,3 + jz ARM64_sys_predefined_mrs.dynamic_reg + cmp [immediate_value],(sys_encode_spsel-sys_encode_table_msr) shr 1 + jnz ERROR_parameter_n_not_valid.first + mov [immediate_value],(sys_pencode_spsel-sys_encode_table_pstate) shr 1 + mov edx,[immediate_value2] + cmp edx,1 + mov ecx,ERROR_immediate_value_out_of_range.0_1 + ja ARM_store_instruction_with_error + .pstate: + mov ebp,[arm64_instruction] + mov edx,[immediate_value2] + cmp edx,15 + mov ecx,ERROR_immediate_value_out_of_range.0_15 + ja ARM_store_instruction_with_error + shl edx,8 + or ebp,edx + or ebp,0x1f + mov [arm64_instruction],ebp + mov edx,sys_encode_table_pstate + jmp ARM64_sys_predefined_at.encode + +ARM64_b_cond: + ;used by B.<cond> + call decode_template + TEMPLATE \ + <TMPL_address64> ;0=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + .encode: + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ecx,[addressing_space] + add eax,[ecx+0] + adc edx,[ecx+4] + sub eax,edi + sbb edx,0 + test eax,3 + mov ecx,ERROR_branch_misaligned + jnz ARM_store_instruction_with_error + mov ebx,edx + cdq + cmp ebx,edx + mov ecx,ERROR_branch_too_far + jnz ARM_store_instruction_with_error + cmp eax,0xfffff + jg ARM_store_instruction_with_error + cmp eax,-0x100000 + jl ARM_store_instruction_with_error + and eax,0x1ffffc + shl eax,(5-2) + or ebp,eax + jmp ARM64_store_instruction + +ARM64_b_reg: + ;used by CBNZ, CBZ + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_address64>,\ ;0=wt,imm + <TMPL_dword_z_reg,TMPL_address64> ;1=xt,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + shl eax,31 + or ebp,eax ;set sf + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_b_cond.encode + +ARM64_b: + call decode_template + ;used by B, BL + TEMPLATE \ + <TMPL_address64> ;0=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ecx,[addressing_space] + add eax,[ecx+0] + adc edx,[ecx+4] + sub eax,edi + sbb edx,0 + test eax,3 + mov ecx,ERROR_branch_misaligned + jnz ARM_store_instruction_with_error + mov ecx,edx + cdq + cmp ecx,edx + mov ecx,ERROR_branch_too_far + jnz ARM_store_instruction_with_error + cmp eax,0x7ffffff + jg ARM_store_instruction_with_error + cmp eax,-0x8000000 + jl ARM_store_instruction_with_error + and eax,0xffffffc + shr eax,2 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_bfi: + ;used by BFI, SBFIZ, UBFIZ + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;0=wd,wn,imm,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;1=wd,wn,imm,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,al + shl eax,22 + or ebp,eax ;set N + shl eax,(31-22) + or ebp,eax ;set sf + ;if BFI then check that rn <> 0x1f + test ebp,1 shl 29 + jz .rn_okay + cmp [operand_register1],0x1f + jz ERROR_zr_not_valid.second + .rn_okay: + test ebp,ebp + mov ecx,ERROR_lsb_out_of_range.0_63 + mov edx,ERROR_lsb_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + cmp eax,[immediate_value] + jbe ARM_store_instruction_with_error + test ebp,ebp + mov ecx,ERROR_width_out_of_range.1_64 + mov edx,ERROR_width_out_of_range.1_32 + cmovns ecx,edx + mov ebx,[immediate_value2] + cmp eax,ebx + jb ARM_store_instruction_with_error + test ebx,ebx + jz ARM_store_instruction_with_error + ;encode the immediate + mov edx,[immediate_value] + dec eax + neg edx + and edx,eax + dec ebx + test ebp,ebp + mov ecx,ERROR_width_out_of_range.64 + mov eax,ERROR_width_out_of_range + cmovns ecx,eax + cmp ebx,edx + jae ARM_store_instruction_with_error + shl edx,6 + or edx,ebx + jmp ARM64_arithmetic1.encode_immediate + +ARM64_bfm: + ;used by BFM, SBFM, UBFM + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;0=wd,wn,imm,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;1=wd,wn,imm,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,al + shl eax,22 + or ebp,eax ;set N + shl eax,(31-22) + or ebp,eax ;set sf + test ebp,ebp + mov ecx,ERROR_immr_out_of_range.0_63 + mov edx,ERROR_immr_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + cmp eax,[immediate_value] + jbe ARM_store_instruction_with_error + test ebp,ebp + mov ecx,ERROR_imms_out_of_range.0_63 + mov edx,ERROR_imms_out_of_range.0_31 + cmovns ecx,edx + mov ebx,[immediate_value2] + cmp eax,ebx + jbe ARM_store_instruction_with_error + ;encode the immediate + mov edx,[immediate_value] + shl edx,6 + or edx,ebx + jmp ARM64_arithmetic1.encode_immediate + +ARM64_bfxil: + ;used by BFXIL, SBFX, UBFX + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\ ;0=wd,wn,imm,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2> ;1=wd,wn,imm,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,al + shl eax,22 + or ebp,eax ;set N + shl eax,(31-22) + or ebp,eax ;set sf + test ebp,ebp + mov ecx,ERROR_lsb_out_of_range.0_63 + mov edx,ERROR_lsb_out_of_range.0_31 + cmovns ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovns eax,edx + cmp eax,[immediate_value] + jbe ARM_store_instruction_with_error + test ebp,ebp + mov ecx,ERROR_width_out_of_range.1_64 + mov edx,ERROR_width_out_of_range.1_32 + cmovns ecx,edx + mov ebx,[immediate_value2] + cmp eax,ebx + jb ARM_store_instruction_with_error + test ebx,ebx + jz ARM_store_instruction_with_error + ;encode the immediate + test ebp,ebp + mov ecx,ERROR_width_out_of_range.64 + mov edx,ERROR_width_out_of_range + cmovns ecx,edx + mov edx,[immediate_value] + lea ebx,[edx+ebx-1] + cmp ebx,eax + jae ARM_store_instruction_with_error + shl edx,6 + or edx,ebx + jmp ARM64_arithmetic1.encode_immediate + +ARM64_br: + ;used by BLR, BR + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg> ;0=xd + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,[operand_register0] + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_debug: + ;used by BRK, HLT, HVC, SMC, SVC + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + mov eax,[immediate_value] + cmp eax,0x10000 + jae ERROR_immediate_value_out_of_range.0_0xffff + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_debug2: + ;used by DCPS1, DCPS2, DCPS3 + call decode_template + TEMPLATE \ + <TMPL_EOL>,\ ;0=empty + <TMPL_imm> ;1=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + mov eax,[immediate_value] + cmp eax,0xffff + ja ERROR_immediate_value_out_of_range.0_0xffff + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_hint: + ;used by HINT + call decode_template + TEMPLATE \ + <TMPL_imm> ;0=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + mov eax,[immediate_value] + cmp eax,0x7f + ja ERROR_immediate_value_out_of_range.0_0x7f + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_debug3: + ;used by DRPS, ERET, NOP, SEV, SEVL, WFE, WFI, YIELD + call decode_template + TEMPLATE \ + <TMPL_EOL> ;0=empty + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + jmp ARM64_store_instruction + +ARM64_conditional_compare: + ;used by CCMN, CCMP + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\ ;0=wn,wm,imm,cond + <TMPL_word_z_reg,TMPL_imm2,TMPL_comma,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\ ;1=wn,imm,imm,cond + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\ ;2=xn,xm,imm,cond + <TMPL_dword_z_reg,TMPL_imm2,TMPL_comma,TMPL_imm,TMPL_comma,TMPL_condition_nv> ;3=xn,imm,imm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + cmp al,2 + setae cl + shl ecx,31 + or ebp,ecx ;set sf + and eax,1 + shl eax,11 + or ebp,eax ;set immediate bit + .encode: + mov ecx,ERROR_condition_value_out_of_range + mov edx,[immediate_value] + cmp edx,15 + ja ARM_store_instruction_with_error + or ebp,edx + movzx edx,[operand_register0] + shl edx,5 + or ebp,edx + test eax,eax + jnz .immediate + movzx eax,[operand_register1] + shl eax,16 + or ebp,eax + movzx eax,[operand_register2] + .store_condition: + shl eax,12 + or ebp,eax + jmp ARM64_store_instruction + .immediate: + mov edx,[immediate_value2] + test edx,edx + jns .positive + neg edx + xor ebp,1 shl 30 + .positive: + mov ecx,ERROR_immediate_value_out_of_range.0_31 + cmp edx,31 + ja ARM_store_instruction_with_error + shl edx,16 + or ebp,edx + movzx eax,[operand_register1] + jmp .store_condition + +ARM64_conditional_modify: + ;used by CINC, CINV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\ ;0=wn,wm,cond + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv> ;1=xn,xm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + movzx edx,[operand_register1] + cmp edx,31 + jz ERROR_zr_not_valid.second + .encode: + shl edx,5 + or ebp,edx + shl edx,16-5 + or ebp,edx + shl eax,31 + or ebp,eax ;set sf + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[operand_register2] ;get condition + .check_condition: + cmp eax,14 + jae ERROR_al_nv_not_valid + xor al,1 + shl eax,12 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_conditional_modify_zr: + ;used by CNEG + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\ ;0=wn,wm,cond + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv> ;1=xn,xm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + movzx edx,[operand_register1] + jmp ARM64_conditional_modify.encode + +ARM64_conditional_select: + ;used by CSEL, CSINC, CSINV, CSNEG + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\ ;0=wd,wn,wm,cond + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv> ;1=xd,xn,xm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + shl eax,31 + .encode: + or ebp,eax ;set sf + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[operand_register1] + shl eax,5 + or ebp,eax + movzx eax,[operand_register2] + shl eax,16 + or ebp,eax + movzx eax,[operand_register3] ;get condition + shl eax,12 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_conditional_set: + ;used by CSET, CSETM + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_condition_nv>,\ ;0=wd,cond + <TMPL_dword_z_reg,TMPL_condition_nv> ;1=xd,cond + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + shl eax,31 + or ebp,eax ;set sf + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[operand_register1] ;get condition + jmp ARM64_conditional_modify.check_condition + +ARM64_clrex: + ;used by CLREX + call decode_template + TEMPLATE \ + <TMPL_EOL>,\ ;0=empty + <TMPL_imm> ;1=imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + test al,al + mov eax,[immediate_value] + mov ecx,0xf + cmovz eax,ecx + cmp eax,0xf + ja ERROR_immediate_value_out_of_range.0_15 + shl eax,8 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_data_barrier: + ;used by DMB, DSB + call decode_template + TEMPLATE \ + <TMPL_barrier>,\ ;0=barrier + <TMPL_imm> ;1=imm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + test al,al + mov eax,[immediate_value] + movzx ecx,[operand_register0] + cmovz eax,ecx + cmp eax,0xf + ja ERROR_immediate_value_out_of_range.0_15 + shl eax,8 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_instruction_barrier: + ;used by ISB + call decode_template + TEMPLATE \ + <TMPL_barrier>,\ ;0=barrier + <TMPL_imm>,\ ;1=imm + <TMPL_EOL> ;2=empty + cmp al,2 + mov edx,[immediate_value] + mov ecx,0xf + cmovz edx,ecx + mov [immediate_value],edx + jmp ARM64_data_barrier.encode + +ARM64_memory_single_fixed: + ;used by LDAR, LDAXR, LDXR, STLR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=wt,[xn] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=wt,[address] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=xt,[xn] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=xt,[address] + .encode: + mov ebp,[arm64_instruction] + .encode2: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov edx,[immediate_value] + mov ecx,ERROR_immediate_offset_out_of_range.0 + test edx,edx + jnz ARM_store_instruction_with_error + cmp al,3 + setae al + shl eax,30 + or ebp,eax + jmp ARM64_arithmetic1.encode_rn + +ARM64_memory_word_single_fixed: + ;used by LDARB, LDARH, LDAXRB, LDAXRH, LDXRB, LDXRH, STLRB, STLRH + test ecx,1 shl 30 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=wt,[xn] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=wt,[address] + jmp ARM64_memory_single_fixed.encode + +ARM64_memory_double_fixed: + ;used by LDAXP, LDXP + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=wt1,wt2,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=wt1,wt2,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=wt1,wt2,[address] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=xt1,xt2,[xn] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=xt1,xt2,[xn,imm] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=xt1,xt2,[address] + mov ebp,[arm64_instruction] + .encode: + mov edx,[operand_registers] + cmp dh,dl + jz ERROR_destination_registers_must_differ + shr edx,8 + mov [operand_register1],dh + movzx edx,dl + shl edx,10 + or ebp,edx + jmp ARM64_memory_single_fixed.encode2 + +ARM64_memory_word_double_release_fixed: + ;used by STLXRB, STLRXH, STXRB, STRRH + test ecx,1 shl 30 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=ws,wt,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=ws,wt,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=ws,wt,[address] + .encode: + mov ebp,[arm64_instruction] + mov ecx,[operand_registers] + movzx edx,cl + shr ecx,8 + mov [operand_registers],ecx + cmp dl,cl + jz ERROR_dest_cannot_be_source_or_memory_address + cmp ch,31 + jz .regs_okay + cmp dl,ch + jz ERROR_dest_cannot_be_source_or_memory_address + .regs_okay: + shl edx,16 + or ebp,edx + jmp ARM64_memory_single_fixed.encode2 + +ARM64_memory_double_release_fixed: + ;used by STLXR, STXR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=ws,wt,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=ws,wt,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=ws,wt,[address] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=ws,xt,[xn] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=ws,xt,[xn,imm] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=ws,xt,[address] + jmp ARM64_memory_word_double_release_fixed.encode + +ARM64_memory_triple_fixed: + ;used by STLXP, STXP + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=ws,wt1,wt2,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=ws,wt1,wt2,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=ws,wt1,wt2,[address] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=ws,xt1,xt2,[xn] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=ws,xt1,xt2,[xn,imm] + <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=ws,xt1,xt2,[address] + mov ebp,[arm64_instruction] + mov ecx,[operand_registers] ;n,t2,t1,s + movzx ebx,cl ;Ws + shl ebx,16 + or ebp,ebx + shr ebx,16 + shr ecx,8 ;n,t2,t1 + cmp bl,cl ;t1 + jz .bad_regs + cmp bl,ch ;t2 + jz .bad_regs + xchg ch,cl ;n,t1,t2 + movzx edx,cl + shl edx,10 + or ebp,edx + shr ecx,8 ;n,t1 + mov [operand_registers],ecx + cmp ch,31 + jz ARM64_memory_single_fixed.encode2 + cmp bl,ch + jnz ARM64_memory_single_fixed.encode2 + .bad_regs: + jmp ERROR_dest_cannot_be_source_or_memory_address + +ARM64_memory_double_imm7_post_pre_offset: + ;used by LDP, STP + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=wt1,wt2,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=wt1,wt2,[xn],imm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=wt1,wt2,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=wt1,wt2,[xn,imm]! + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 4=wt1,wt2,[address] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 5=wt1,wt2,[address]! + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 6=xt1,xt2,[xn] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 7=xt1,xt2,[xn],imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 8=xt1,xt2,[xn,imm] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 9=xt1,xt2,[xn,imm]! + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;10=xt1,xt2,[address] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;11=xt1,xt2,[address]! + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;12=st1,st2,[xn] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;13=st1,st2,[xn],imm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;14=st1,st2,[xn,imm] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;15=st1,st2,[xn,imm]! + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;16=st1,st2,[address] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;17=st1,st2,[address]! + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;18=dt1,dt2,[xn] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;19=dt1,dt2,[xn],imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;20=dt1,dt2,[xn,imm] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;21=dt1,dt2,[xn,imm]! + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;22=dt1,dt2,[address] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;23=dt1,dt2,[address]! + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;24=qt1,qt2,[xn] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;25=qt1,qt2,[xn],imm + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;26=qt1,qt2,[xn,imm] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;27=qt1,qt2,[xn,imm]! + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;28=qt1,qt2,[address] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;29=qt1,qt2,[address]! + .do: + mov ebp,[arm64_instruction] + mov ah,0 + mov cl,6 + div cl + cmp ah,4 + setae cl + add cl,cl + sub ah,cl + movzx ecx,ah + setz dl + add dl,dl + or cl,dl + shl ecx,23 + or ebp,ecx + .encode: + mov dx,word[operand_register0] + test ebp,1 shl 22 + jz .reg_pair_okay + cmp dh,dl + jz ERROR_destination_registers_must_differ + .reg_pair_okay: + cmp al,2 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + test ah,1 + jz .writeback_okay + cmp [operand_register2],31 + jz .writeback_okay + cmp dl,[operand_register2] + jz ERROR_base_and_dest_must_differ_with_writeback + cmp dh,[operand_register2] + jz ERROR_base_and_dest_must_differ_with_writeback + .writeback_okay: + shl eax,31 + or ebp,eax + shr eax,31 + jmp .set_multiplier + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + or ebp,1 shl 26 + sub al,2 + shl eax,30 + or ebp,eax + shr eax,30 + .set_multiplier: + lea ecx,[eax+2] + mov eax,ERROR_immediate_offset_out_of_range.m256_252 + mov edx,ERROR_immediate_offset_out_of_range.m512_504 + mov ebx,ERROR_immediate_offset_out_of_range.m1024_1008 + cmp ecx,3 + cmovz eax,edx + cmova eax,ebx + mov ebx,[immediate_value] + or edx,-1 + shl edx,cl + not edx + test ebx,edx + cmovnz ecx,eax + jnz ARM_store_instruction_with_error + sar ebx,cl + mov ecx,eax + cmp ebx,-64 + jl ARM_store_instruction_with_error + cmp ebx,+64 + jge ARM_store_instruction_with_error + and ebx,0x7f + shl ebx,15 + or ebp,ebx + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[operand_register1] + shl eax,10 + or ebp,eax + movzx eax,[operand_register2] + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_memory_double_imm7: + ;used by LDNP, STNP + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=wt1,wt2,[xn] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 1=wt1,wt2,[xn,imm] + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 2=wt1,wt2,[address] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 3=xt1,xt2,[xn] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 4=xt1,xt2,[xn,imm] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 5=xt1,xt2,[address] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 6=st1,st2,[xn] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 7=st1,st2,[xn,imm] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 8=st1,st2,[address] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 9=dt1,dt2,[xn] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;10=dt1,dt2,[xn,imm] + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;11=dt1,dt2,[address] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;12=qt1,qt2,[xn] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;13=qt1,qt2,[xn,imm] + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;14=qt1,qt2,[address] + mov ebp,[arm64_instruction] + mov ah,0 + mov cl,3 + div cl + add ah,ah + jmp ARM64_memory_double_imm7_post_pre_offset.encode + +ARM64_memory_double_imm7_signed: + ;used by LDPSW + mov [operand_size],8 + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=xt1,xt2,[xn] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;1=xt1,xt2,[xn],imm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;2=xt1,xt2,[xn,imm] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;3=xt1,xt2,[xn,imm]! + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;4=wt1,wt2,[address] + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;5=wt1,wt2,[address]! + mov ebp,[arm64_instruction] + jmp ARM64_memory_double_imm7_post_pre_offset.do + +ARM64_memory: + ;used by LDR, STR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=wt,[xn] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=wt,[xn],imm + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=wt,[xn,imm]! + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 4=wt,[xn,wm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 5=wt,[xn,wm,extend] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=wt,[xn,wm,extend imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 7=wt,[xn,wm,lsl imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 8=wt,[xn,xm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 9=wt,[xn,xm,extend] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 10=wt,[xn,xm,extend imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 11=wt,[xn,xm,lsl imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 12=wt,[address] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 13=wt,[address]! + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ; 14=wt,[address] + <TMPL_word_z_reg,TMPL_size_4,TMPL_address64>,\ ; 15=wt,address + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 16=xt,[xn] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 17=xt,[xn],imm + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 18=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 19=xt,[xn,imm]! + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 20=xt,[xn,wm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 21=xt,[xn,wm,extend] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 22=xt,[xn,wm,extend imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 23=xt,[xn,wm,lsl imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 24=xt,[xn,xm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 25=xt,[xn,xm,extend] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 26=xt,[xn,xm,extend imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 27=xt,[xn,xm,lsl imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 28=xt,[address] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 29=xt,[address]! + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ; 30=xt,[address] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_address64>,\ ; 31=xt,address + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 32=bt,[xn] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 33=bt,[xn],imm + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 34=bt,[xn,imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 35=bt,[xn,imm]! + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 36=bt,[xn,wm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 37=bt,[xn,wm,extend] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 38=bt,[xn,wm,extend imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 39=bt,[xn,wm,lsl imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 40=bt,[xn,xm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 41=bt,[xn,xm,extend] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 42=bt,[xn,xm,extend imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 43=bt,[xn,xm,lsl imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 44=bt,[address] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 45=bt,[address]! + <TMPL_never>,\ ; 46=- + <TMPL_never>,\ ; 47=- + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 48=ht,[xn] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 49=ht,[xn],imm + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 50=ht,[xn,imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 51=ht,[xn,imm]! + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 52=ht,[xn,wm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 53=ht,[xn,wm,extend] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 54=ht,[xn,wm,extend imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 55=ht,[xn,wm,lsl imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 56=ht,[xn,xm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 57=ht,[xn,xm,extend] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 58=ht,[xn,xm,extend imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 59=ht,[xn,xm,lsl imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 60=ht,[address] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 61=ht,[address]! + <TMPL_never>,\ ; 62=- + <TMPL_never>,\ ; 63=- + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 64=st,[xn] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 65=st,[xn],imm + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 66=st,[xn,imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 67=st,[xn,imm]! + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 68=st,[xn,wm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 69=st,[xn,wm,extend] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 70=st,[xn,wm,extend imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 71=st,[xn,wm,lsl imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 72=st,[xn,xm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 73=st,[xn,xm,extend] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 74=st,[xn,xm,extend imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 75=st,[xn,xm,lsl imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 76=st,[address] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 77=st,[address]! + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ; 78=st,[address] + <TMPL_vect_sreg,TMPL_size_4,TMPL_address64>,\ ; 79=st,address + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 80=dt,[xn] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 81=dt,[xn],imm + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 82=dt,[xn,imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 83=dt,[xn,imm]! + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 84=dt,[xn,wm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 85=dt,[xn,wm,extend] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 86=dt,[xn,wm,extend imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 87=dt,[xn,wm,lsl imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 88=dt,[xn,xm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 89=dt,[xn,xm,extend] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 90=dt,[xn,xm,extend imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 91=dt,[xn,xm,lsl imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 92=dt,[address] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 93=dt,[address]! + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ; 94=dt,[address] + <TMPL_vect_dreg,TMPL_size_8,TMPL_address64>,\ ; 95=dt,address + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 96=qt,[xn] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 97=qt,[xn],imm + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 98=qt,[xn,imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 99=qt,[xn,imm]! + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ;100=qt,[xn,wm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;101=qt,[xn,wm,extend] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;102=qt,[xn,wm,extend imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;103=qt,[xn,wm,lsl imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ;104=qt,[xn,xm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;105=qt,[xn,xm,extend] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;106=qt,[xn,xm,extend imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;107=qt,[xn,xm,lsl imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;108=qt,[address] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;109=qt,[address]! + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ;110=qt,[address] + <TMPL_vect_qreg,TMPL_size_16,TMPL_address64> ;111=qt,address + ; + ;W&X + ;unscaled off AB11-1000-CD0i-iiii-iiii-00nn-nnnt-tttt + ;immediate post AB11-1000-CD0i-iiii-iiii-01nn-nnnt-tttt + ;unprivileged AB11-1000-010i-iiii-iiii-10nn-nnnt-tttt + ;immediate pre AB11-1000-CD0i-iiii-iiii-11nn-nnnt-tttt + ;register AB11-1000-CD1m-mmmm-xxxx-10nn-nnnt-tttt + ;immediate off AB11-1001-CDii-iiii-iiii-iinn-nnnt-tttt + ;literal JK01-1000-iiii-iiii-iiii-iiii-iiit-tttt + ; + ;ABCD=0000 ---> strb W B(st) sttrb W + ;ABCD=0001 ---> ldrb W B(ld) ldtrb W + ;ABCD=0010 ---> ldrsb X Q(st) ldtrsb X + ;ABCD=0011 ---> ldrsb W Q(ld) ldtrsb W + ;ABCD=0100 ---> strh W H(st) sttrh W + ;ABCD=0101 ---> ldrh W H(ld) ldtrh W + ;ABCD=0110 ---> ldrsh X ldtrsh X + ;ABCD=0111 ---> ldrsh W ldtrsh W + ;ABCD=1000 ---> str W S(st) sttr W + ;ABCD=1001 ---> ldr W S(ld) ldtr W + ;ABCD=1010 ---> ldrsw X ldtrsw X + ;ABCD=1011 ---> ---- + ;ABCD=1100 ---> str X D(st) sttr X + ;ABCD=1101 ---> ldr X D(ld) ldtr X + ;ABCD=1110 ---> prfm i + ;ABCD=1111 ---> ---- + ; + ;JK=00 ---> W + ;JK=01 ---> X + ;JK=10 ---> SW + ;JK=11 ---> PRFM + ; + ;BHSD&Q + ;immediate post EF11-1100-G10i-iiii-iiii-01nn-nnnt-tttt + ;immediate pre EF11-1100-G10i-iiii-iiii-11nn-nnnt-tttt + ;immediate off EF11-1101-G1ii-iiii-iiii-iinn-nnnt-tttt + ;register EF11-1100-G11m-mmmm-xxxx-10nn-nnnt-tttt + ;literal KL01-1100-iiii-iiii-iiii-iiii-iiit-tttt + ;EFG=000 ---> B + ;EFG=010 ---> H + ;EFG=100 ---> S + ;EFG=110 ---> D + ;EFG=001 ---> Q + ; + ;KL=00 ---> S + ;KL=01 ---> D + ;KL=10 ---> Q + .decode: + mov ch,2 ;set register offset for Wt and Xt + .do: + mov ebp,[arm64_instruction] + mov ah,al + shr al,4 + and ah,0xf ;al=target reg index, ah=parameters + ;set target register + cmp al,1 + ja .set_vector_reg + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + cmp ah,1 ;t,[n],imm + jz .check_writeback + cmp ah,3 ;t,[n,imm]! + jz .check_writeback + cmp ah,13 ;t,[exp]! + jnz .writeback_okay + .check_writeback: + mov dx,word[operand_register0] + cmp dh,31 + jz .writeback_okay + cmp dl,dh + jz ERROR_base_and_dest_must_differ_with_writeback + .writeback_okay: + cmp al,1 + ja .set_vector_reg + setz cl + add cl,ch ;cl=log register size + mov edx,ecx + shl edx,30 + or ebp,edx + jmp .set_paramters + .set_vector_reg: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + or ebp,1 shl 26 + lea ecx,[eax-2] ;cl=log register size + mov ebx,ecx + shl ebx,30 + setc dl + mov dh,0 + or ebp,ebx + shl edx,23 + or ebp,edx + cmp al,2 ;b? + jnz .set_paramters + mov dl,ah + and dl,0xe + cmp dl,6 + setz dh + cmp dl,10 + setz dl + or dl,dh + shl dx,12 + or bp,dx ;set S + .set_paramters: + cmp ah,14 + jae .literal + cmp ah,12 + jae .expression + cmp ah,3 + ja .register + .indexed: + test ah,1 + jnz .pre_post + ;offset + or ebp,1 shl 24 + mov eax,ERROR_immediate_offset_out_of_range.0_0xfff.m256_255 + mov edx,ERROR_immediate_offset_out_of_range.0_0x1ffe.m256_255 + mov ebx,ERROR_immediate_offset_out_of_range.0_0x3ffc.m256_255 + cmp cl,1 + cmovz eax,edx + cmp cl,2 + cmovz eax,ebx + mov edx,ERROR_immediate_offset_out_of_range.0_0x7ff8.m256_255 + mov ebx,ERROR_immediate_offset_out_of_range.0_0xfff0.m256_255 + cmp cl,3 + cmovz eax,edx + cmova eax,ebx + mov ebx,[immediate_value] + or edx,-1 + shl edx,cl + not edx + test ebx,edx + jnz .try_unscaled + sar ebx,cl + cmp ebx,0xfff + ja .try_unscaled + shl ebx,10 + .encode_imm: + or ebp,ebx + .encode_rt: + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[operand_register1] + shl eax,5 + or ebp,eax + movzx eax,[operand_register2] + shl eax,16 + or ebp,eax + jmp ARM64_store_instruction + .expression: + sub ah,10 + jmp .indexed + .try_unscaled: + xor ebp,1 shl 24 + mov ecx,eax + xor eax,eax + jmp .pre_post.do + .pre_post: + mov ecx,ERROR_immediate_offset_out_of_range.m256_255 + .pre_post.do: + and eax,3 shl 8 + shl eax,10-8 + xor ebp,eax + mov ebx,[immediate_value] + cmp ebx,-0x100 + jl ARM_store_instruction_with_error + cmp ebx,0xff + jg ARM_store_instruction_with_error + and ebx,0x1ff + shl ebx,12 + jmp .encode_imm + .register: + or ebp,1 shl 11 + 1 shl 21 + movzx edx,[instruction_shift_op] + xchg ch,cl + mov cl,3 + mov al,ah + and al,3 + cmovz dx,cx ;set default to LSL + cmp al,3 ;LSL specified? + cmovz dx,cx + mov dh,0 + xchg ch,cl + test dl,010b + jz ERROR_extend_type + test ah,8 + jnz .extend_reg_okay + test dl,1 + jnz ERROR_parameter_n_not_valid.third ;can't have w with [su]xtx + .extend_reg_okay: + mov eax,[immediate_value] + test eax,eax + jz .extend_amount_okay + or ebp,1 shl 12 + cmp cl,al + jz .extend_amount_okay + mov eax,ERROR_shift_value_out_of_range.0 + mov edx,ERROR_shift_value_out_of_range.0or1 + mov ebx,ERROR_shift_value_out_of_range.0or2 + cmp cl,1 + cmovz eax,edx + cmp cl,2 + cmovz eax,ebx + mov edx,ERROR_shift_value_out_of_range.0or3 + mov ebx,ERROR_shift_value_out_of_range.0or4 + cmp cl,3 + cmovz eax,edx + cmova eax,ebx + mov ecx,eax + jmp ARM_store_instruction_with_error + .extend_amount_okay: + shl edx,13 + or ebp,edx + jmp .encode_rt + .literal: + cmp [arm64_instruction],0x38000000 ;STR? + jz ERROR_parameter_n_not_valid.second + and ebp,not (7 shl 29 + 3 shl 22) + sub cl,2 + shl ecx,30 + or ebp,ecx + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ecx,[addressing_space] + add eax,[ecx+0] + adc edx,[ecx+4] + sub eax,edi + sbb edx,0 + test eax,3 + mov ecx,ERROR_branch_misaligned + jnz ARM_store_instruction_with_error + mov ebx,edx + cdq + cmp ebx,edx + mov ecx,ERROR_branch_too_far + jnz ARM_store_instruction_with_error + cmp eax,0xfffff + jg ARM_store_instruction_with_error + cmp eax,-0x100000 + jl ARM_store_instruction_with_error + and eax,0x1ffffc + shl eax,(5-2) + or ebp,eax + jmp .encode_rt + +ARM64_memory_byte_hword: + ;used by LDRB, LDRH, STRB, STRH + test cl,1 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=wt,[xn] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=wt,[xn],imm + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=wt,[xn,imm]! + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 4=wt,[xn,wm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 5=wt,[xn,wm,extend] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=wt,[xn,wm,extend imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 7=wt,[xn,wm,lsl imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 8=wt,[xn,xm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 9=wt,[xn,xm,extend] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;10=wt,[xn,xm,extend imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;11=wt,[xn,xm,lsl imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=wt,[address] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;13=wt,[address]! + <TMPL_never>,\ ;Note: the following template section is non standard to allow both Xt and Wt syntax ;14=- + <TMPL_never>,\ ;they encode to the same instructions ;15=- + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;16=xt,[xn] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;17=xt,[xn],imm + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;18=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;19=xt,[xn,imm]! + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ;20=xt,[xn,wm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;21=xt,[xn,wm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;22=xt,[xn,wm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;23=xt,[xn,wm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ;24=xt,[xn,xm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;25=xt,[xn,xm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;26=xt,[xn,xm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;27=xt,[xn,xm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;28=xt,[address] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;29=xt,[address]! + mov edx,[arm64_instruction] + and al,0xf ;X and W forms are the same instruction + test dl,1 + jnz .byte_imm_done + mov cl,al + and cl,0xe + cmp cl,6 + setz ch + cmp cl,10 + setz cl + or cl,ch + shl cx,12 + or dx,cx ;set S + .byte_imm_done: + btr edx,0 + setc ch ;set register offset for Wt + mov [arm64_instruction],edx + jmp ARM64_memory.do + +ARM64_memory_signed_byte_hword: + ;used by LDRSB, LDRSH + test cl,1 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=xt,[xn] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=xt,[xn],imm + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=xt,[xn,imm]! + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 4=xt,[xn,wm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 5=xt,[xn,wm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=xt,[xn,wm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 7=xt,[xn,wm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 8=xt,[xn,xm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 9=xt,[xn,xm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;10=xt,[xn,xm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;11=xt,[xn,xm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=xt,[address] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;13=xt,[address]! + <TMPL_never>,\ ;14=- + <TMPL_never>,\ ;15=- + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;16=wt,[xn] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ;17=wt,[xn],imm + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;18=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;19=wt,[xn,imm]! + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ;20=wt,[xn,wm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;21=wt,[xn,wm,extend] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;22=wt,[xn,wm,extend imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;23=wt,[xn,wm,lsl imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ;24=wt,[xn,xm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;25=wt,[xn,xm,extend] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;26=wt,[xn,xm,extend imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;27=wt,[xn,xm,lsl imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;28=wt,[address] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim> ;29=wt,[address]! + mov edx,[arm64_instruction] + test dl,1 + jnz .byte_imm_done + mov cl,al + and cl,0xe + cmp cl,6 + setz ch + cmp cl,10 + setz cl + or cl,ch + shl cx,12 + or dx,cx ;set S + .byte_imm_done: + btr edx,0 + setc ch ;set register offset for Wt/Xt + mov [arm64_instruction],edx + cmp al,15 + jbe ARM64_memory.do + sub al,16 + or edx,1 shl 22 + mov [arm64_instruction],edx + jmp ARM64_memory.do + +ARM64_memory_signed_word: + ;used by LDRSW + mov [operand_size],4 + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=xt,[xn] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\ ; 1=xt,[xn],imm + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 3=xt,[xn,imm]! + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 4=xt,[xn,wm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 5=xt,[xn,wm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=xt,[xn,wm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 7=xt,[xn,wm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 8=xt,[xn,xm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 9=xt,[xn,xm,extend] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;10=xt,[xn,xm,extend imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;11=xt,[xn,xm,lsl imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=xt,[address] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ;13=xt,[address]! + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ;14=xt,[address] + <TMPL_dword_z_reg,TMPL_address64> ;15=xt,address + cmp al,13 + jbe ARM64_memory.decode + mov ch,4 ;set literal size for Xt + jmp ARM64_memory.do + +ARM64_memory_unprivileged: + ;used by LDTR, STTR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=wt,[xn] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=wt,[address] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=xt,[xn] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=xt,[address] + .decode_v8: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + .decode: + mov ebp,[arm64_instruction] + mov cl,3 + xor ah,ah + div cl + mov ah,1 + mov ch,2 ;set register offset for Wt and Xt + jmp ARM64_memory.writeback_okay + +ARM64_memory_unscaled: + ;used by LDUR, STUR + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=wt,[xn] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 1=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 2=wt,[address] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 3=xt,[xn] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 4=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 5=xt,[address] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 6=bt,[xn] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 7=bt,[xn,imm] + <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ; 8=bt,[address] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 9=ht,[xn] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;10=ht,[xn,imm] + <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;11=ht,[address] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;12=st,[xn] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;13=st,[xn,imm] + <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;14=st,[address] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;15=dt,[xn] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;16=dt,[xn,imm] + <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;17=dt,[address] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;18=qt,[xn] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;19=qt,[xn,imm] + <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;20=qt,[address] + cmp al,6 + jb ARM64_memory_unprivileged.decode_v8 + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + jmp ARM64_memory_unprivileged.decode + +ARM64_memory_unprivileged_byte_hword: + ;used by LDTRB, LDTRH, LDURB, LDURH, STTRB, STTRH, STURB, STURH + test cl,1 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=wt,[xn] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=wt,[address] + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + btr ebp,0 + setc ch ;set register offset for Wt + mov ax,0x100 + jmp ARM64_memory.writeback_okay + +ARM64_memory_unprivileged_signed_byte_hword: + ;used by LDTRSB, LDTRSH, LDURSB, LDURSH + test cl,1 + setnz dl + add dl,1 + mov [operand_size],dl + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=xt,[xn] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;2=xt,[address] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;3=wt,[xn] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=wt,[xn,imm] + <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;5=wt,[address] + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + btr ebp,0 + setc ch ;set register offset for Wt/Xt + cmp al,3 + setae al + movzx eax,al + shl eax,22 + or ebp,eax + mov ax,0x100 + jmp ARM64_memory.writeback_okay + +ARM64_memory_unprivileged_signed_word: + ;used by LDTRSW, LDURSW + mov [operand_size],4 + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;0=xt,[xn] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;1=xt,[xn,imm] + <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right> ;2=xt,[address] + jmp ARM64_memory_unprivileged.decode_v8 + +ARM64_mov_aliases: + ;used by MOV + call decode_template + TEMPLATE \ + <TMPL_word_sp_reg,TMPL_word_s_reg>,\ ; 0=wd,wn + <TMPL_word_sp_reg,TMPL_imm>,\ ; 1=wd,imm + <TMPL_word_zr_reg,TMPL_word_z_reg>,\ ; 2=wd,wn + <TMPL_word_zr_reg,TMPL_imm>,\ ; 3=wd,imm + <TMPL_word_zr_reg,TMPL_vect_element_s>,\ ; 4=wd,vn.s[] + <TMPL_word_gen_reg,TMPL_word_sp_reg>,\ ; 5=wd,wn + <TMPL_word_gen_reg,TMPL_word_zr_reg>,\ ; 6=wd,wn + <TMPL_word_gen_reg,TMPL_word_gen_reg>,\ ; 7=wd,wn + <TMPL_word_gen_reg,TMPL_imm>,\ ; 8=wd,imm + <TMPL_word_gen_reg,TMPL_vect_element_s>,\ ; 9=wd,vn.s[] + <TMPL_dword_sp_reg,TMPL_dword_s_reg>,\ ;10=xd,xn + <TMPL_dword_sp_reg,TMPL_imm64>,\ ;11=xd,imm + <TMPL_dword_zr_reg,TMPL_dword_z_reg>,\ ;12=xd,xn + <TMPL_dword_zr_reg,TMPL_imm64>,\ ;13=xd,imm + <TMPL_dword_zr_reg,TMPL_vect_element_d>,\ ;14=xd,vn.d[] + <TMPL_dword_gen_reg,TMPL_dword_sp_reg>,\ ;15=xd,wn + <TMPL_dword_gen_reg,TMPL_dword_zr_reg>,\ ;16=xd,wn + <TMPL_dword_gen_reg,TMPL_dword_gen_reg>,\ ;17=xd,wn + <TMPL_dword_gen_reg,TMPL_imm64>,\ ;18=xd,imm + <TMPL_dword_gen_reg,TMPL_vect_element_d>,\ ;19=xd,vn.d[] + <TMPL_vect_breg,TMPL_vect_element_b>,\ ;20=bd,vn.b[] + <TMPL_vect_hreg,TMPL_vect_element_h>,\ ;21=hd,vn.h[] + <TMPL_vect_sreg,TMPL_vect_element_s>,\ ;22=sd,vn.s[] + <TMPL_vect_dreg,TMPL_vect_element_d>,\ ;23=dd,vn.d[] + <TMPL_vect_element_b,TMPL_vect_element_b>,\ ;24=vd.b[],vn.b[] + <TMPL_vect_element_b,TMPL_word_z_reg>,\ ;25=vd.b[],wn + <TMPL_vect_element_h,TMPL_vect_element_h>,\ ;26=vd.h[],vn.h[] + <TMPL_vect_element_h,TMPL_word_z_reg>,\ ;27=vd.h[],wn + <TMPL_vect_element_s,TMPL_vect_element_s>,\ ;28=vd.s[],vn.s[] + <TMPL_vect_element_s,TMPL_word_z_reg>,\ ;29=vd.s[],wn + <TMPL_vect_element_d,TMPL_vect_element_d>,\ ;30=vd.d[],vn.d[] + <TMPL_vect_element_d,TMPL_dword_z_reg>,\ ;31=vd.d[],xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;32=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b> ;33=vd,vn + .encode: + cmp al,20 + jae .vector + cmp al,10 + setae cl + shl ecx,31 + mov ebp,ecx + sets cl + neg cl + and cl,10 + sub al,cl + cmp al,4 + jz .gen_vect + cmp al,9 + jz .gen_vect + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + cmp al,0 + jz .reg_sp + cmp al,1 + jz .imm_sp + cmp al,3 + jz .imm_gen + cmp al,8 + jz .imm_gen + cmp al,5 + jz .reg_sp + .reg_gen: + mov cl,[operand_register1] + mov [operand_register2],cl + or ebp,0x2a0003e0 + jmp ARM64_dz_nz_mz.encode_rd + .reg_sp: + or ebp,0x11000000 + jmp ARM64_dz_nz_mz.encode_rd + .imm_gen: + or ebp,0x52800000 + mov eax,[immediate_value] + mov edx,[immediate_value_high] + .try_wide_immediate: + mov cl,0 + test ebp,ebp + js .check_wide_loop + xor edx,edx + .check_wide_loop: + test edx,edx + setz bh + test eax,0xffff0000 + setz bl + and bl,bh + jnz .put_wide_immediate + mov ebx,eax + shrd eax,edx,16 + shrd edx,ebx,16 + inc cl + cmp cl,4 + jb .check_wide_loop + not edx + not eax + btr ebp,30 ;try inverted + jc .try_wide_immediate + cmp [operand_register0],0x1f ;ZR? + mov ecx,ERROR_immediate_cannot_be_encoded + jz ARM_store_instruction_with_error + and ebp,1 shl 31 + .imm_sp: + or ebp,0x320003e0 + js .immediate_prepared + mov eax,[immediate_value] + mov [immediate_value_high],eax + .immediate_prepared: + call ARM64_encode_bitmask + mov ecx,ERROR_immediate_cannot_be_encoded + jc ARM_store_instruction_with_error + mov edx,eax + jmp ARM64_arithmetic1.encode_immediate + .put_wide_immediate: + shl eax,5 + or ebp,eax + movzx ecx,cl + shl ecx,21 + or ebp,ecx + jmp ARM64_dz_nz_mz.encode_rd + .gen_vect: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + shr ebp,1 ;set Q + setnz cl + add cl,18 + or ebp,0x0e003c00 + mov eax,[immediate_value2] + .encode_imm5: + add eax,eax + inc eax + shl eax,cl + or ebp,eax + jmp ARM64_dz_nz_mz.encode_rd + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + cmp al,24 + jb .scalar + cmp al,32 + jae .vect_vect + shr al,1 + jc .vect_gen + ;vector element to vector element + lea ecx,[eax-12+11] + mov eax,[immediate_value2] + shl eax,cl + lea ebp,[eax+0x6e000400] + add cl,5 + mov eax,[immediate_value] + jmp .encode_imm5 + .scalar: + lea ecx,[eax-20+16] + mov ebp,0x5e000400 + mov eax,[immediate_value2] + jmp .encode_imm5 + .vect_vect: + shr al,1 + setc al + shl eax,30 + lea ebp,[eax+0x0ea01c00] + mov al,[operand_register1] + mov [operand_register2],al + jmp ARM64_dz_nz_mz.encode_rd + .vect_gen: + lea ecx,[eax-12+16] + mov ebp,0x4e001c00 + mov eax,[immediate_value] + jmp .encode_imm5 + +ARM64_mov_wide: + ;used by MOVK, MOVN, MOVZ + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_imm64>,\ ;0=wd,imm + <TMPL_word_z_reg,TMPL_imm64,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;1=wd,imm,lsl imm + <TMPL_dword_z_reg,TMPL_imm64>,\ ;2=xd,imm + <TMPL_dword_z_reg,TMPL_imm64,TMPL_comma,TMPL_lsl,TMPL_imm2> ;3=xd,imm,lsl imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] + shr al,1 + shl eax,31 + or ebp,eax + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ebx,eax + or ebx,edx + jz .check_immediate_zero + mov ecx,[immediate_value2] + cmp ecx,64 + jae .out_of_range + cmp ecx,32 + jb .do_shift + mov edx,eax + xor eax,eax + sub ecx,32 + .do_shift: + xor ebx,ebx + shld ebx,edx,cl + test ebx,ebx + jnz .out_of_range + shld edx,eax,cl + test edx,edx + jz .imm32_okay + test ebp,ebp + jns .out_of_range + .imm32_okay: + shl eax,cl + .check_immediate: + test edx,edx + jnz .try_next_shift + test eax,0xffff0000 + jz .immediate_okay + .try_next_shift: + test eax,0xffff + jnz .out_of_range + shrd eax,edx,16 + shr edx,16 + inc bl + cmp bl,4 + jb .check_immediate + jmp .out_of_range + .check_immediate_zero: + mov ebx,[immediate_value2] + bt ebp,29 ;MOVK? + jnc .scale_shift + ;for MOVK we have to honour the shift value + .encode_shift: + test ebx,not 3 shl 4 + jnz .out_of_range + .scale_shift: + ;otherwise use floor(value/16) + shr ebx,4 + .immediate_okay: + shl ebx,21 + shl eax,5 + or ebp,ebx + or ebp,eax + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + .out_of_range: + test ebp,ebp + mov ecx,ERROR_immediate_value_out_of_range.0_0xffff_lsl_16 + mov edx,ERROR_immediate_value_out_of_range.0_0xffff_lsl_48 + cmovs ecx,edx + jmp ARM_store_instruction_with_error + +ARM64_arithmetic6: + ;used by MUL + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 0=wd,wn,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ; 1=xd,xn,xm + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 2=vd,vn,vm + <TMPL_never>,\ ; 3 + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 4=vd,vn,vm + <TMPL_never>,\ ; 5 + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 6=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\ ; 7=vd,vn,vm.h[] + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 8=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\ ; 9=vd,vn,vm.h[] + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;10=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\ ;11=vd,vn,vm.s[] + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;12=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s> ;13=vd,vn,vm.s[] + cmp al,1 + ja .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + shl eax,31 + lea ebp,[eax+0x1b007c00] + jmp ARM64_dz_nz_mz.encode_rd + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + sub al,2 + mov ebp,0x0e209c00 ;vector + mov ebx,0x0f008000 ;element + .vector_encode: + shr al,1 + setc dl ;element flag + shr al,1 + setc cl ;Q + shl ecx,30 + movzx eax,al ;size + shl eax,22 + or ecx,eax + test dl,dl + jnz .element + or ebp,ecx + jmp ARM64_dz_nz_mz.encode_rd + .element: + lea ebp,[ecx+ebx] + mov edx,[immediate_value2] + shr eax,22-4 + cmp al,[operand_register2] + jbe ERROR_vector_register_out_of_range + mov cl,al + shr cl,5 + shl edx,cl + mov eax,edx + mov ecx,edx + and edx,100b + and eax,011b + shl edx,11-2 ;H + shl eax,20-0 ;L:M + or ebp,edx + or ebp,eax + jmp ARM64_dz_nz_mz.encode_rd + +ARM64_arithmetic7: + ;used by MVN + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\ ;1=wd,wm,shift imm + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;2=xd,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\ ;3=xd,xm,shift imm + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;4=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b> ;5=vd,vn + cmp al,4 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + shr al,2 + setc al + shl eax,31 + lea ebp,[eax+0x2a2003e0] + mov al,[operand_register1] + mov [operand_register2],al + jmp ARM64_arithmetic1.encode_shifted_register + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + shl eax,31 + shr eax,1 + lea ebp,[eax+0x2e205800] + jmp ARM64_dz_nz_mz.encode_rd + +ARM64_arithmetic8: + ;used by NEG, NEGS + bt ecx,29 + jnc .non_S + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\ ;1=wd,wm,shift imm + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;2=xd,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm> ;3=xd,xm,shift imm + jmp .encode + .non_S: + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ; 0=wd,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\ ; 1=wd,wm,shift imm + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ; 2=xd,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\ ; 3=xd,xm,shift imm + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 4=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 5=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 6=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 7=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 8=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ; 9=vd,vn + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ;10=dd,dn + <TMPL_vect_v2d,TMPL_vect_v2d> ;11=vd,vn + .encode: + mov ebp,[arm64_instruction] ;recover the template + cmp al,4 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov dl,[operand_register1] + mov [operand_register2],dl + cmp al,2 + setae cl + add al,cl + jmp ARM64_arithmetic2.encode + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,0x2e20b800 + sub al,4 + jmp ARM64_arithmetic1.vector_encode + +ARM64_arithmetic9: + ;used by NGC, NGCS + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg> ;1=xd,xm + mov dl,[operand_register1] + mov [operand_register2],dl + jmp ARM64_dz_nz_mz.encode + +ARM64_prefetch: + ;used by PRFM + call decode_template + TEMPLATE \ + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0=op,[xn] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\ ; 1 + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 2=op,[xn,imm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\ ; 3 + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ; 4=op,[xn,wm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 5=op,[xn,wm,extend] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=op,[xn,wm,extend imm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ; 7=op,[xn,wm,lsl imm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ; 8=op,[xn,xm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ; 9=op,[xn,xm,extend] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;10=op,[xn,xm,extend imm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;11=op,[xn,xm,lsl imm] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;12=op,[address] + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_never>,\ ;13= + <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ;14=op,[address] + <TMPL_imm2,TMPL_comma,TMPL_address64>,\ ;15=op,address + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;16=op,[xn] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\ ;17 + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;18=op,[xn,imm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\ ;19 + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\ ;20=op,[xn,wm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;21=op,[xn,wm,extend] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;22=op,[xn,wm,extend imm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;23=op,[xn,wm,lsl imm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\ ;24=op,[xn,xm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\ ;25=op,[xn,xm,extend] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;26=op,[xn,xm,extend imm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\ ;27=op,[xn,xm,lsl imm] + <TMPL_prf_op,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\ ;28=op,[address] + <TMPL_prf_op,TMPL_bracket_left,TMPL_never>,\ ;29= + <TMPL_prf_op,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\ ;30=op,[address] + <TMPL_prf_op,TMPL_address64> ;31=op,address + cmp al,16 + jae .check_literal + mov edx,[operand_registers] + mov ecx,[immediate_value2] + shl edx,8 + mov dl,cl + mov [operand_registers],edx + cmp ecx,0x1f + mov ecx,ERROR_immediate_value_out_of_range.0_31 + ja ARM_store_instruction_with_error + add al,16 + .check_literal: + cmp al,30 + jb ARM64_memory.decode + mov ch,4 ;set literal size for Xt + jmp ARM64_memory.do + +ARM64_arithmetic10: + ;used by RBIT + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;1=xd,xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;2=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b> ;3=vd,vn + mov ebp,[arm64_instruction] ;recover the template + cmp al,2 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + shl eax,31 + or ebp,eax ;set sf + jmp ARM64_arithmetic1.encode_rn + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + and al,1 + shl eax,30 ;set Q + lea ebp,[eax+0x2e605800] + jmp ARM64_arithmetic1.encode_rn + +ARM64_ret: + ;used by RET + call decode_template + TEMPLATE \ + <TMPL_EOL>,\ ;0=empty + <TMPL_dword_z_reg> ;1=xn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,[operand_register0] + mov ecx,30 + cmp al,1 + cmovnz eax,ecx + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_arithmetic11: + ;used by REV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wm + <TMPL_dword_z_reg,TMPL_dword_z_reg> ;1=xd,xm + movzx ecx,al + shl ecx,10 + or [arm64_instruction],ecx + jmp ARM64_dz_nz_mz.encode + +ARM64_arithmetic12: + ;used by REV16 + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wd,wn + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;1=xd,xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;2=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b> ;3=vd,vn + mov ebp,[arm64_instruction] ;recover the template + cmp al,2 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + shl eax,31 + or ebp,eax ;set sf + jmp ARM64_arithmetic1.encode_rn + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + and al,1 + shl eax,30 ;set Q + lea ebp,[eax+0x0e201800] + jmp ARM64_arithmetic1.encode_rn + +ARM64_arithmetic13: + ;used by REV32 + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;1=xd,xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;2=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ;3=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ;4=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h> ;5=vd,vn + mov ebx,0x2e200800 + .do: + mov ebp,[arm64_instruction] ;recover the template + cmp al,1 + jae .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + jmp ARM64_arithmetic1.encode_rn + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,ebx + dec al + shr al,1 + setc cl + shl ecx,30 ;set Q + mov ah,0 + shl eax,22 ;set size + or ebp,ecx + or ebp,eax + jmp ARM64_arithmetic1.encode_rn + +ARM64_arithmetic14: + ;used by REV64 + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;1=xd,xn + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;2=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ;3=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ;4=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h>,\ ;5=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;6=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s> ;7=vd,vn + mov ebx,0x0e200800 + jmp ARM64_arithmetic13.do + +ARM64_arithmetic15: + ;used by SMULL, UMULL + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=xd,wn,wm + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;1=vd,vn,vm + <TMPL_never>,\ ;2 + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;3=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\ ;4=vd,vn,vm.h[] + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;5=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s> ;6=vd,vn,vm.s[] + mov ebp,[arm64_instruction] ;recover the template + dec al + jns .vector + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + jmp ARM64_dz_nz_mz_az.encode + .vector: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + shr al,1 + lea eax,[eax+eax] + rcl al,1 + and ebp,1 shl 23 ;isolate U + shl ebp,29-23 + lea ebx,[ebp+0x0f00a000] ;element + or ebp,0x0e20c000 ;vector + jmp ARM64_arithmetic6.vector_encode + +ARM64_sys: + ;used by SYS + call decode_template + TEMPLATE \ + <TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2>,\ ;0=op1,crn,crm,op2 + <TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2,TMPL_dword_z_reg> ;1=op1,crn,crm,op2,xt + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + dec al + and al,0x1f ;default register + or al,[operand_register2] + movzx eax,al + or ebp,eax + movzx eax,[copro_opcode1] + cmp eax,7 + mov ecx,ERROR_immediate_value_out_of_range.0_7 + ja ARM_store_instruction_with_error + shl eax,16 + or ebp,eax + movzx eax,[operand_register0] + shl eax,12 + or ebp,eax + movzx eax,[operand_register1] + shl eax,8 + or ebp,eax + movzx eax,[copro_opcode2] + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_sysl: + ;used by SYSL + call decode_template + TEMPLATE \ + <TMPL_dword_z_reg,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2> ;0=xt,op1,crn,crm,op2 + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + movzx eax,[operand_register0] + or ebp,eax + movzx eax,[copro_opcode1] + cmp eax,7 + mov ecx,ERROR_immediate_value_out_of_range.0_7 + ja ARM_store_instruction_with_error + shl eax,16 + or ebp,eax + movzx eax,[operand_register1] + shl eax,12 + or ebp,eax + movzx eax,[operand_register2] + shl eax,8 + or ebp,eax + movzx eax,[copro_opcode2] + shl eax,5 + or ebp,eax + jmp ARM64_store_instruction + +ARM64_tb: + ;used by TBNZ + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_imm2,TMPL_comma,TMPL_address64>,\ ;0=wt,imm,address + <TMPL_dword_z_reg,TMPL_imm2,TMPL_comma,TMPL_address64> ;1=xt,imm,address + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32 + jz ERROR_requires_cpu64_capability_v8 + mov ebp,[arm64_instruction] ;recover the template + test al,al + mov ecx,ERROR_bit_out_of_range.0_63 + mov edx,ERROR_bit_out_of_range.0_31 + cmovz ecx,edx + mov eax,1 shl 6 + mov edx,1 shl 5 + cmovz eax,edx + cmp eax,[immediate_value2] + jbe ARM_store_instruction_with_error + mov eax,[immediate_value2] + mov ecx,eax + and eax,0x1f + shl eax,19 + or ebp,eax + and ecx,0x20 + shl ecx,31-5 + or ebp,ecx + mov eax,[immediate_value] + mov edx,[immediate_value_high] + mov ecx,[addressing_space] + add eax,[ecx+0] + adc edx,[ecx+4] + sub eax,edi + sbb edx,0 + test eax,3 + mov ecx,ERROR_branch_misaligned + jnz ARM_store_instruction_with_error + mov ecx,edx + cdq + cmp ecx,edx + mov ecx,ERROR_branch_too_far + jnz ARM_store_instruction_with_error + cmp eax,0x7fff + jg ARM_store_instruction_with_error + cmp eax,-0x8000 + jl ARM_store_instruction_with_error + and eax,0xfffc + shl eax,5-2 + or ebp,eax + movzx eax,[operand_register0] + or ebp,eax + jmp ARM64_store_instruction + +ARM64_arithmetic16: + ;used by TST + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_word_z_reg>,\ ;0=wn,wm + <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\ ;1=wn,wm,shift imm + <TMPL_word_z_reg,TMPL_imm>,\ ;2=wn,imm + <TMPL_dword_z_reg,TMPL_dword_z_reg>,\ ;3=xn,xm + <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\ ;4=xn,xm,shift imm + <TMPL_dword_z_reg,TMPL_imm64> ;5=xn,imm + mov ebp,[arm64_instruction] ;recover the template + mov ecx,[operand_registers] + shl ecx,8 + or ecx,0x1f + mov [operand_registers],ecx + jmp ARM64_arithmetic2.encode + +ARM64_vector_scalar_bhsd_two_reg: + ;used by ABS + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ;1=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h>,\ ;3=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ;5=vd,vn + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ;6=dd,dn + <TMPL_vect_v2d,TMPL_vect_v2d> ;7=vd,vn + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + jmp ARM64_arithmetic1.vector_encode + +ARM64_vector_narrow_low: + ;used by ADDHN, RADDHN, RSUBHN, SUBHN + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;0=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;1=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_vect_v2d> ;2=vd,vn,vm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + mov ah,0 + shl eax,22 + or ebp,eax + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_narrow_high: + ;used by ADDHN2, RADDHN2, RSUBHN2, SUBHN2 + call decode_template + TEMPLATE \ + <TMPL_vect_v16b,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;0=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;1=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v2d,TMPL_vect_v2d> ;2=vd,vn,vm + jmp ARM64_vector_narrow_low.encode + +ARM64_vector_narrow_3reg_scalar_2reg: + ;used by ADDP + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;1=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;3=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;5=vd,vn,vm + <TMPL_vect_dreg,TMPL_vect_v2d>,\ ;6=dn,vn + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d> ;7=vd,vn,vm + cmp al,6 + jnz ARM64_vector_scalar_bhsd_two_reg.encode + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + xor ebp,0x50110400 + jmp ARM64_arithmetic1.vector_encode + +ARM64_vector_reduce_bhs: + ;used by ADDV, SMAXV, SMINV, UMAXV, UMINV + call decode_template + TEMPLATE \ + <TMPL_vect_breg,TMPL_vect_v8b>,\ ;0=vd,vn + <TMPL_vect_breg,TMPL_vect_v16b>,\ ;1=vd,vn + <TMPL_vect_hreg,TMPL_vect_v4h>,\ ;2=vd,vn + <TMPL_vect_hreg,TMPL_vect_v8h>,\ ;3=vd,vn + <TMPL_never>,\ ;4=- + <TMPL_vect_sreg,TMPL_vect_v4s> ;5=vd,vn + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_crypto_two_reg: + ;used by AESD, AESE, AESIMC, AESMC + call decode_template + TEMPLATE \ + <TMPL_vect_v16b,TMPL_vect_v16b> ;0=vd,vn + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_CRYPTO shr 32 + jz ERROR_requires_cpu64_capability_crypto + mov ebp,[arm64_instruction] ;recover the template + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_scalar_b_three_reg: + ;used by BIF, BIT, BSL, PMUL + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b> ;1=vd,vn,vm + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_scalar_bhsd_three_reg_zero: + ;used by CMEQ, CMGE, CMGT + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 0=vd,vn,vm + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ; 1=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\; 2=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ; 3=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 4=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ; 5=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 6=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ; 7=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 8=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ; 9=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;10=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ;11=vd,vn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;12=dd,dn,dm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;13=dd,dn,imm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;14=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm> ;15=vd,vn,imm + shr al,1 + jnc ARM64_vector_scalar_bhsd_two_reg.encode + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ecx,ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz ARM_store_instruction_with_error + mov ebp,[arm64_instruction] + mov ebx,1 shl 29 + 0x05 shl 10 ;eq + mov edx,0 shl 29 + 0x2f shl 10 ;gt + mov ecx,1 shl 29 + 0x2d shl 10 ;eq + test ebp,1 shl 11 + cmovz ecx,edx + test ebp,1 shl 13 ;cmeq? + cmovz ecx,ebx + xor ebp,ecx + jmp ARM64_arithmetic1.vector_encode + +ARM64_vector_scalar_bhsd_three_reg: + ;used by CMHI, CMHS, CMTST, SRSHL, SSHL, URSHL, USHL + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\;1=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;3=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;5=vd,vn,vm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;6=dd,dn,dm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d> ;7=vd,vn,vm + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_scalar_bhsd_two_reg_zero: + ;used by CMLE, CMLT + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ;2=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ;3=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;4=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ;5=vd,vn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;6=dd,dn,imm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm> ;7=vd,vn,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ecx,ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz ARM_store_instruction_with_error + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_b_two_reg: + ;used by CNT, NOT + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b> ;1=vd,vn + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_dup: + ;used by DUP + call decode_template + TEMPLATE \ + <TMPL_vect_breg,TMPL_vect_element_b>,\ ; 0=bd,vn.b[] + <TMPL_vect_hreg,TMPL_vect_element_h>,\ ; 1=hd,vn.h[] + <TMPL_vect_sreg,TMPL_vect_element_s>,\ ; 2=sd,vn.s[] + <TMPL_vect_dreg,TMPL_vect_element_d>,\ ; 3=dd,vn.d[] + <TMPL_vect_v8b,TMPL_vect_element_b>,\ ; 4=bd,vn.b[] + <TMPL_vect_v8b,TMPL_word_z_reg>,\ ; 5=bd,wn + <TMPL_vect_v16b,TMPL_vect_element_b>,\ ; 6=bd,vn.b[] + <TMPL_vect_v16b,TMPL_word_z_reg>,\ ; 7=bd,wn + <TMPL_vect_v4h,TMPL_vect_element_h>,\ ; 8=hd,vn.h[] + <TMPL_vect_v4h,TMPL_word_z_reg>,\ ; 9=hd,wn + <TMPL_vect_v8h,TMPL_vect_element_h>,\ ;10=hd,vn.h[] + <TMPL_vect_v8h,TMPL_word_z_reg>,\ ;11=hd,wn + <TMPL_vect_v2s,TMPL_vect_element_s>,\ ;12=sd,vn.s[] + <TMPL_vect_v2s,TMPL_word_z_reg>,\ ;13=sd,wn + <TMPL_vect_v4s,TMPL_vect_element_s>,\ ;14=sd,vn.s[] + <TMPL_vect_v4s,TMPL_word_z_reg>,\ ;15=sd,wn + <TMPL_never>,\ ;16=- + <TMPL_never>,\ ;17=- + <TMPL_vect_v2d,TMPL_vect_element_d>,\ ;18=dd,vn.d[] + <TMPL_vect_v2d,TMPL_dword_z_reg> ;19=dd,xn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + sub al,4 + jae .reg_element + lea ecx,[eax+4+16] + mov ebp,0x5e000400 + mov eax,[immediate_value2] + jmp ARM64_mov_aliases.encode_imm5 + .reg_element: + mov ebp,0x0e000400 + shr al,1 + setc dl + movzx edx,dl + shl edx,11 + or ebp,edx + shr al,1 + lea ecx,[eax+16] + setc al + shl eax,30 + or ebp,eax + mov eax,[immediate_value2] + jmp ARM64_mov_aliases.encode_imm5 + +ARM64_vector_b_three_reg_imm: + ;used by EXT + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm> ;1=vd,vn,vm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + mov edx,[immediate_value] + mov ecx,ERROR_immediate_value_out_of_range.0_7 + mov ebx,ERROR_immediate_value_out_of_range.0_15 + test al,al + cmovnz ecx,ebx + setnz bl + movzx ebx,bl + lea ebx,[ebx*8+8] + cmp edx,ebx + jae ARM_store_instruction_with_error + shl edx,11 + or ebp,edx + jmp ARM64_arithmetic1.vector_encode + +ARM64_vector_scalar_sd_three_reg: + ;used by FABD, FACGE, FACGT, FADD, FDIV, FMAX, FMAXNM, FMIN, FMINNM, FRECPS, FRSQRTS, FSUB + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;1=dd,dn,dm sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;2=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;3=vd,vn,vm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s> ;4=vd,vn,vm sz=0 q=1 + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + cmp al,2 + cmovb ebp,[arm64_instruction] ;recover the scalar template + cmovae ebp,[arm64_instruction2] ;recover the vector template + cmp al,3 + setae cl + and eax,1 + shl eax,22 + or ebp,eax ;set sz + shl ecx,30 + or ebp,ecx ;set Q + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_scalar_sd_two_reg: + ;used by FABS, FNEG, FRECPE, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, FRINTZ, FRSQRTE, FSQRT + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ;1=dd,dn sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;2=vd,vn sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d>,\ ;3=vd,vn sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s> ;4=vd,vn sz=0 q=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_scalar_sd_pairs: + ;used by FADDP, FMAXNMP, FMAXP, FMINNMP, FMINP + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_v2s>,\ ;0=sd,vn sz=0 + <TMPL_vect_dreg,TMPL_vect_v2d>,\ ;1=dd,vn sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;2=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;3=vd,vn,vm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s> ;4=vd,vn,vm sz=0 q=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_conditional_compare_float: + ;used by FCCMP, FCCMPE + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\ ;0=sn,sm,imm,cond + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm,TMPL_comma,TMPL_condition_nv> ;1=dn,dm,imm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + mov ebp,[arm64_instruction] + and eax,1 + shl eax,22 ;set sz + or ebp,eax + xor eax,eax + jmp ARM64_conditional_compare.encode + +ARM64_vector_scalar_sd_compare_mask_eq: + ;used by FCMEQ + push 0x00803c00 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm sz=0 + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ;1=sd,sn,imm sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;2=dd,dn,dm sz=1 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;3=dd,dn,imm sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;5=vd,vn,imm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;6=vd,vn,vm sz=1 q=1 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ;7=vd,vn,imm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;8=vd,vn,vm sz=0 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm> ;9=vd,vn,imm sz=0 q=1 + pop edx + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + shr al,1 + jnc ARM64_vector_scalar_sd_three_reg.do + mov ecx,ERROR_immediate_offset_out_of_range.0 + cmp [immediate_value],0 + jnz ARM_store_instruction_with_error + xor [arm64_instruction],edx + xor [arm64_instruction2],edx + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_scalar_sd_compare_mask_ge: + ;used by FCMGE + push 0x00802c00 + jmp ARM64_vector_scalar_sd_compare_mask_eq.do + +ARM64_vector_scalar_sd_compare_mask_gt: + ;used by FCMGT + push 0x20002c00 + jmp ARM64_vector_scalar_sd_compare_mask_eq.do + +ARM64_vector_scalar_sd_compare_mask_le: + ;used by FCMLE, FCMLT + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ;0=sd,sn,imm sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;1=dd,dn,imm sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;2=vd,vn,imm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ;3=vd,vn,imm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm> ;4=vd,vn,imm sz=0 q=1 + xor edx,edx + lea eax,[eax*2+1] + jmp ARM64_vector_scalar_sd_compare_mask_eq.encode + +ARM64_scalar_sd_compare: + ;used by FCMP, FCMPE + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn sz=0 opc=0 + <TMPL_vect_sreg,TMPL_imm>,\ ;1=sd,imm sz=0 opc=1 + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ;2=dd,dn sz=1 opc=0 + <TMPL_vect_dreg,TMPL_imm> ;3=dd,imm sz=1 opc=1 + mov edx,0x00000008 + mov ecx,[operand_registers] + shl ecx,8 + mov [operand_registers],ecx + jmp ARM64_vector_scalar_sd_compare_mask_eq.encode + +ARM64_scalar_conditional_select: + ;used by FCSEL + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg,TMPL_condition_nv>,\ ;0=sd,sn,sm,cond + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg,TMPL_condition_nv> ;1=dd,dn,dm,cond + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + mov ebp,[arm64_instruction] + and eax,1 + shl eax,22 + jmp ARM64_conditional_select.encode + +ARM64_scalar_hsd_convert: + ;used by FCVT + call decode_template + TEMPLATE \ + <TMPL_vect_hreg,TMPL_never>,\ ;0=- opc=11 type=11 + <TMPL_vect_hreg,TMPL_vect_sreg>,\ ;1=hd,sn opc=11 type=00 + <TMPL_vect_hreg,TMPL_vect_dreg>,\ ;2=hd,dn opc=11 type=01 + <TMPL_vect_sreg,TMPL_vect_hreg>,\ ;3=sd,hn opc=00 type=11 + <TMPL_vect_sreg,TMPL_never>,\ ;4=- opc=00 type=00 + <TMPL_vect_sreg,TMPL_vect_dreg>,\ ;5=sd,dn opc=00 type=01 + <TMPL_vect_dreg,TMPL_vect_hreg>,\ ;6=dd,hn opc=01 type=11 + <TMPL_vect_dreg,TMPL_vect_sreg> ;7=dd,sn opc=01 type=00 + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + mov ebp,[arm64_instruction] + mov ah,0 + mov cl,3 + div cl ;al=opc, ah=type + dec ah + dec al + mov cl,ah + and eax,3 + and ecx,3 + shl eax,15 + shl ecx,22 + or ebp,eax + or ebp,ecx + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_scalar_sdwx_two_reg_as: + ;used by FCVTAS + push 0x1e240000 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ;1=dd,dn sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;2=vd,vn sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d>,\ ;3=vd,vn sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ;4=vd,vn sz=0 q=1 + <TMPL_word_z_reg,TMPL_vect_sreg>,\ ;5=wd,sn + <TMPL_word_z_reg,TMPL_vect_dreg>,\ ;6=wd,dn + <TMPL_dword_z_reg,TMPL_vect_sreg>,\ ;7=xd,sn + <TMPL_dword_z_reg,TMPL_vect_dreg> ;8=xd,dn + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + pop edx + cmp al,4 + jbe ARM64_vector_scalar_sd_three_reg.do + sub al,5 + shr al,1 + setc cl + shl eax,31 + mov ch,0 + shl ecx,22 + lea ebp,[edx+eax] + or ebp,ecx + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_scalar_sdwx_two_reg_au: + ;used by FCVTAU + push 0x1e250000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_ms: + ;used by FCVTMS + push 0x1e300000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_mu: + ;used by FCVTMU + push 0x1e310000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_ns: + ;used by FCVTNS + push 0x1e200000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_nu: + ;used by FCVTNU + push 0x1e210000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_ps: + ;used by FCVTPS + push 0x1e280000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_scalar_sdwx_two_reg_pu: + ;used by FCVTPU + push 0x1e290000 + jmp ARM64_vector_scalar_sdwx_two_reg_as.do + +ARM64_vector_convert_long: + ;used by FCVTL + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v4h>,\ ;0=vd,vn sz=0 + <TMPL_vect_v2d,TMPL_vect_v2s> ;1=vd,vn sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_convert_long2: + ;used by FCVTL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v8h>,\ ;0=vd,vn sz=0 + <TMPL_vect_v2d,TMPL_vect_v4s> ;1=vd,vn sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_convert_narrow: + ;used by FCVTN + call decode_template + TEMPLATE \ + <TMPL_vect_v4h,TMPL_vect_v4s>,\ ;0=vd,vn sz=0 + <TMPL_vect_v2s,TMPL_vect_v2d> ;1=vd,vn sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_convert_narrow2: + ;used by FCVTN2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v4s>,\ ;0=vd,vn sz=0 + <TMPL_vect_v4s,TMPL_vect_v2d> ;1=vd,vn sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_convert_odd_narrow: + ;used by FCVTXN + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_dreg>,\ ;0=sd,dn + <TMPL_vect_v2s,TMPL_vect_v2d> ;1=vd,vn + add al,al + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_convert_odd_narrow2: + ;used by FCVTXN2 + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v2d> ;0=vd,vn + shl al,2 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_scalar_sd_convert_zero_s: + ;used by FCVTZS + push 0x1e380000 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ; 0=sd,sn,sm sz=0 + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ; 1=sd,sn,imm sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ; 2=dd,dn,dm sz=1 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ; 3=dd,dn,imm sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 4=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ; 5=vd,vn,imm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d>,\ ; 6=vd,vn,vm sz=1 q=1 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ; 7=vd,vn,imm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ; 8=vd,vn,vm sz=0 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ; 9=vd,vn,imm sz=0 q=1 + <TMPL_word_z_reg,TMPL_vect_sreg>,\ ;10=wd,sn + <TMPL_word_z_reg,TMPL_vect_sreg,TMPL_imm>,\ ;11=wd,sn,imm + <TMPL_word_z_reg,TMPL_vect_dreg>,\ ;12=wd,dn + <TMPL_word_z_reg,TMPL_vect_dreg,TMPL_imm>,\ ;13=wd,dn,imm + <TMPL_dword_z_reg,TMPL_vect_sreg>,\ ;14=xd,sn + <TMPL_dword_z_reg,TMPL_vect_sreg,TMPL_imm>,\ ;15=xd,sn,imm + <TMPL_dword_z_reg,TMPL_vect_dreg>,\ ;16=xd,dn + <TMPL_dword_z_reg,TMPL_vect_dreg,TMPL_imm> ;17=xd,dn,imm + shr al,1 + jnc ARM64_vector_scalar_sdwx_two_reg_as.encode + ;fixed point + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + xor dword[esp],1 shl 21 + xor [arm64_instruction],0x01a14400 + xor [arm64_instruction2],0x01a14400 + .encode: + cmp al,5 + jae .gp_reg + bt eax,0 + call .test_immediate_size + shl ebx,1 + sub ebx,edx + shl ebx,16 + or [arm64_instruction],ebx + or [arm64_instruction2],ebx + jmp ARM64_vector_scalar_sdwx_two_reg_as.encode + jmp ARM64_vector_scalar_sd_three_reg.do + .gp_reg: + cmp al,7 + cmc + call .test_immediate_size + neg edx + and edx,0x3f + shl edx,10 + or dword[esp],edx + jmp ARM64_vector_scalar_sdwx_two_reg_as.encode + jmp ARM64_vector_scalar_sd_three_reg.do + .test_immediate_size: + mov ecx,ERROR_immediate_value_out_of_range.1_32 + mov edx,ERROR_immediate_value_out_of_range.1_64 + cmovc ecx,edx + mov ebx,32 + mov edx,64 + cmovc ebx,edx + mov edx,[immediate_value] + cmp edx,ebx + jae ARM_store_instruction_with_error + ret + +ARM64_vector_scalar_sd_convert_zero_u: + ;used by FCVTZU + push 0x1e390000 + jmp ARM64_vector_scalar_sd_convert_zero_s.do + +ARM64_scalar_sd_four_reg: + ;used by FMADD, FMSUB, FNMADD, FNMSUB + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn,sm,sa sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg> ;1=dd,dn,dm,sa sz=1 + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + mov ebp,[arm64_instruction] + .encode_size: + mov ah,0 + shl eax,22 + or ebp,eax + jmp ARM64_dz_nz_mz_az.encode_rd + +ARM64_vector_4_to_1: + ;used by FMAXNMV, FMAXV, FMINNMV, FMINV + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_v4s> ;0=sd,vn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + jmp ARM64_dz_nz_mz.do + +ARM64_vector_scalar_sd_two_reg_element_add: + ;used by FMLA + push 0x0e20cc00 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s>,\ ;0=sd,sn,vn.s[] sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_element_d>,\ ;1=dd,dn,vn.d[] sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\ ;2=vd,vn,vn.s[] sz=0 q=0 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;3=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_element_d>,\ ;4=vd,vn,vn.d[] sz=1 q=1 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;5=vd,vn,vm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>,\ ;6=vd,vn,vn.s[] sz=0 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s> ;7=vd,vn,vm sz=0 q=1 + pop edx + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + cmp al,2 + jb .scalar + shr al,1 + cmovnc edx,[arm64_instruction2] + inc al + mov [arm64_instruction2],edx + .scalar: + mov edx,[immediate_value2] + mov cl,al + and cl,1 + shl edx,cl + mov ecx,edx + and edx,10b + and ecx,01b + shl edx,11-1 ;H + shl ecx,21-0 ;L + or edx,ecx + or [arm64_instruction],edx + or [arm64_instruction2],edx + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_scalar_sd_two_reg_element_sub: + ;used by FMLS + push 0x0ea0cc00 + jmp ARM64_vector_scalar_sd_two_reg_element_add.do + +align 4 +ARM64_fmov_table: + dd 0x1e260000 ;wd,sn + dd 0x9e660000 ;xd,dn + dd 0x9eae0003 ;xd,vn.d[] + dd 0x9eaf0003 ;vd.d[],xn + dd 0x1e270000 ;sd,wn + dd 0x1e204000 ;sd,sn + dd 0x1e201001 ;sd,imm + dd 0x9e670000 ;dd,xn + dd 0x1e604000 ;dd,dn + dd 0x1e601001 ;dd,imm + dd 0x0f00f402 ;vd,imm + dd 0x6f00f402 ;vd,imm + dd 0x4f00f402 ;vd,imm + +ARM64_fmov: + ;used by FMOV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_vect_sreg>,\ ; 0=wd,sn + <TMPL_dword_z_reg,TMPL_vect_dreg>,\ ; 1=xd,dn + <TMPL_dword_z_reg,TMPL_vect_element_d>,\ ; 2=xd,vn.d[] + <TMPL_vect_element_d,TMPL_dword_z_reg>,\ ; 3=vd.d[],xn + <TMPL_vect_sreg,TMPL_word_z_reg>,\ ; 4=sd,wn + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ; 5=sd,sn + <TMPL_vect_sreg,TMPL_imm_float>,\ ; 6=sd,imm + <TMPL_vect_dreg,TMPL_dword_z_reg>,\ ; 7=dd,xn + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ; 8=dd,dn + <TMPL_vect_dreg,TMPL_imm_float>,\ ; 9=dd,imm + <TMPL_vect_v2s,TMPL_imm_float>,\ ;10=vd,imm op=0 q=0 + <TMPL_vect_v2d,TMPL_imm_float>,\ ;11=vd,imm op=1 q=1 + <TMPL_vect_v4s,TMPL_imm_float> ;12=vd,imm op=0 q=1 + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + movzx eax,al + mov ebp,[ARM64_fmov_table+eax*4] + mov edx,ebp + and ebp,not 3 + cmp dl,1 + jb ARM64_arithmetic1.encode_rn + je .scalar_immediate + cmp dl,2 + ja .check_element + ;vector immediate + call VFP_convert_single_to_quarter + mov eax,[immediate_value] + cmp eax,0xff + ja .out_of_range + mov ecx,eax + and eax,0x1f + and ecx,0xe0 + shl eax,5 + shl ecx,16-5 + or ebp,eax + or ebp,ecx + jmp ARM64_arithmetic1.encode_rd + .scalar_immediate: + call VFP_convert_single_to_quarter + mov eax,[immediate_value] + cmp eax,0xff + ja .out_of_range + shl eax,13 + or ebp,eax + jmp ARM64_arithmetic1.encode_rd + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.quarter + jmp ARM_store_instruction_with_error + .check_element: + mov ebx,[immediate_value] + mov edx,[immediate_value2] + test al,1 + cmovz ebx,edx + mov ecx,ERROR_immediate_offset_out_of_range.1 + cmp ebx,1 + jnz ARM_store_instruction_with_error + jmp ARM64_arithmetic1.encode_rn + +ARM64_vector_scalar_sd_three_reg_element: + ;used by FMUL + push 0x5f809000 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn,sm sz=0 + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s>,\ ;1=sd,sn,v.s[] sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\ ;2=dd,dn,dm sz=1 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_element_d>,\ ;3=dd,dn,v.d[] sz=1 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm sz=0 q=0 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\ ;5=vd,vn,v.s[] sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;6=vd,vn,vm sz=1 q=1 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_element_d>,\ ;7=vd,vn,v.d[] sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;8=vd,vn,vm sz=0 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s> ;9=vd,vn,v.s[] sz=0 q=1 + pop edx + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + shr al,1 + jnc ARM64_vector_scalar_sd_three_reg.do + mov ebx,[immediate_value2] + mov cl,al + and cl,1 + shl ebx,cl + mov ecx,ebx + and ebx,10b + and ecx,01b + shl ebx,11-1 ;H + shl ecx,21-0 ;L + or ebx,ecx + or edx,ebx + mov [arm64_instruction],edx + xor edx,5 shl 28 + mov [arm64_instruction2],edx + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_vector_scalar_sd_three_reg_element_x: + ;used by FMULX + push 0x7f809000 + jmp ARM64_vector_scalar_sd_three_reg_element.do + +ARM64_scalar_sd_three_reg: + ;used by FNMUL + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg> ;1=dd,dn,dm sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_scalar_sd_rwo_reg: + ;used by FRECPX + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn sz=0 + <TMPL_vect_dreg,TMPL_vect_dreg> ;1=dd,dn sz=1 + jmp ARM64_vector_scalar_sd_three_reg.do + +ARM64_ins: + ;used by INS + call decode_template + TEMPLATE \ + <TMPL_vect_element_b,TMPL_vect_element_b>,\ ;0=vd.b[],vn.b[] + <TMPL_vect_element_b,TMPL_word_z_reg>,\ ;1=vd.b[],wn + <TMPL_vect_element_h,TMPL_vect_element_h>,\ ;2=vd.h[],vn.h[] + <TMPL_vect_element_h,TMPL_word_z_reg>,\ ;3=vd.h[],wn + <TMPL_vect_element_s,TMPL_vect_element_s>,\ ;4=vd.s[],vn.s[] + <TMPL_vect_element_s,TMPL_word_z_reg>,\ ;5=vd.s[],wn + <TMPL_vect_element_d,TMPL_vect_element_d>,\ ;6=vd.d[],vn.d[] + <TMPL_vect_element_d,TMPL_dword_z_reg> ;7=vd.d[],xn + add al,24 + jmp ARM64_mov_aliases.encode + +align 4 +ARM64_ld1_error_table1: + dd ERROR_immediate_offset_out_of_range.8 + dd ERROR_immediate_offset_out_of_range.16 + dd ERROR_immediate_offset_out_of_range.24 + dd ERROR_immediate_offset_out_of_range.32 + dd 0 + dd ERROR_immediate_offset_out_of_range.48 + dd 0 + dd ERROR_immediate_offset_out_of_range.64 +ARM64_ld1_opcode_table1: + db 5,8,4,0 +ARM64_ld1_error_table2: + dd ERROR_immediate_offset_out_of_range.1 + dd ERROR_immediate_offset_out_of_range.2 + dd ERROR_immediate_offset_out_of_range.3 + dd ERROR_immediate_offset_out_of_range.4 + dd 0 + dd ERROR_immediate_offset_out_of_range.6 + dd 0 + dd ERROR_immediate_offset_out_of_range.8 + dd 0 + dd 0 + dd 0 + dd ERROR_immediate_offset_out_of_range.12 + dd 0 + dd 0 + dd 0 + dd ERROR_immediate_offset_out_of_range.16 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd ERROR_immediate_offset_out_of_range.24 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd 0 + dd ERROR_immediate_offset_out_of_range.32 +ARM64_ld1_opcode_table2: + db 0,16,32,33 + +ARM64_ld1: + ;used by LD1, ST1 + push 0x00000401 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0={vt.8b},[xn] + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 1={vt.8b},[xn],xm + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 2={vt.8b},[xn],imm + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 3={vt.16b},[xn] + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 4={vt.16b},[xn],xm + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 5={vt.16b},[xn],imm + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 6={vt.4h},[xn] + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 7={vt.4h},[xn],xm + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 8={vt.4h},[xn],imm + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 9={vt.8h},[xn] + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;10={vt.8h},[xn],xm + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;11={vt.8h},[xn],imm + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;12={vt.2s},[xn] + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;13={vt.2s},[xn],xm + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;14={vt.2s},[xn],imm + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;15={vt.4s},[xn] + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;16={vt.4s},[xn],xm + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;17={vt.4s},[xn],imm + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;18={vt.1d},[xn] + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;19={vt.1d},[xn],xm + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;20={vt.1d},[xn],imm + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;21={vt.2d},[xn] + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;22={vt.2d},[xn],xm + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;23={vt.2d},[xn],imm + <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;24={vt.b}[imm],[xn] + <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;25={vt.b}[imm],[xn],xm + <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;26={vt.b}[imm],[xn],imm + <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;27={vt.h}[imm],[xn] + <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;28={vt.h}[imm],[xn],xm + <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;29={vt.h}[imm],[xn],imm + <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;30={vt.s}[imm],[xn] + <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;31={vt.s}[imm],[xn],xm + <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;32={vt.s}[imm],[xn],imm + <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;33={vt.d}[imm],[xn] + <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;34={vt.d}[imm],[xn],xm + <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2> ;35={vt.d}[imm],[xn],imm + pop ebx + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + cmp [simd_reg_list_count],bl + jb ERROR_parameter_n_not_valid.first + cmp [simd_reg_list_count],bh + ja ERROR_parameter_n_not_valid.first + mov ah,0 + mov cl,3 + div cl ;al=reg selection, ah=address mode + cmp bl,bh + jnz .1d_okay + cmp al,6 + jz ERROR_parameter_n_not_valid.first + .1d_okay: + cmp al,8 + jae .single + mov ebp,[arm64_instruction2] + cmp ah,1 + jz .encode_multiple + ;check immediate + btr ebp,23 + test ah,ah + jz .encode_multiple + bts ebp,23 + mov [operand_register2],0x1f + movzx edx,[simd_reg_list_count] + mov cl,al + and cl,1 + shl edx,cl + mov ecx,[ARM64_ld1_error_table1-4+edx*4] + shl edx,3 + cmp edx,[immediate_value2] + jnz ARM_store_instruction_with_error + .encode_multiple: + movzx eax,al + mov edx,eax + and eax,110b + and edx,001b + shl eax,10-1 + shl edx,30-0 + or ebp,eax ;set size + or ebp,edx ;set Q + movzx edx,[simd_reg_list_count] + mov dl,[ARM64_ld1_opcode_table1-1+edx] + shl edx,12 + or ebp,edx + jmp ARM64_arithmetic1.encode_rm + .single: + cmp [simd_reg_list_count],bl + jnz ERROR_parameter_n_not_valid.first + sub al,8 + mov ebp,[arm64_instruction] + cmp ah,1 + jz .encode_single + ;check immediate + btr ebp,23 + test ah,ah + jz .encode_single + bts ebp,23 + mov [operand_register2],0x1f + movzx ecx,al + movzx edx,[simd_reg_list_count] + shl edx,cl + mov ecx,[ARM64_ld1_error_table2-4+edx*4] + cmp edx,[immediate_value2] + jnz ARM_store_instruction_with_error + .encode_single: + movzx eax,al + mov ecx,eax + mov al,[ARM64_ld1_opcode_table2+eax] + shl eax,10 + or ebp,eax ;set size and opcode + mov edx,[immediate_value] + shl edx,cl + mov eax,edx + and edx,1000b + and eax,0111b + shl edx,30-3 + shl eax,10-0 + or ebp,edx ;set Q + or ebp,eax ;set S:size + jmp ARM64_arithmetic1.encode_rm + +ARM64_ld2: + ;used by LD2, ST2 + push 0x00000202 + jmp ARM64_ld1.do + +ARM64_ld3: + ;used by LD3, ST3 + push 0x00000303 + jmp ARM64_ld1.do + +ARM64_ld4: + ;used by LD4, ST4 + push 0x00000404 + jmp ARM64_ld1.do + +ARM64_ld1r: + ;used by LD1R + push 1 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 0={vt.8b},[xn] + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 1={vt.8b},[xn],xm + <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 2={vt.8b},[xn],imm + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 3={vt.16b},[xn] + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 4={vt.16b},[xn],xm + <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 5={vt.16b},[xn],imm + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 6={vt.4h},[xn] + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 7={vt.4h},[xn],xm + <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ; 8={vt.4h},[xn],imm + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ; 9={vt.8h},[xn] + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;10={vt.8h},[xn],xm + <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;11={vt.8h},[xn],imm + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;12={vt.2s},[xn] + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;13={vt.2s},[xn],xm + <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;14={vt.2s},[xn],imm + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;15={vt.4s},[xn] + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;16={vt.4s},[xn],xm + <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;17={vt.4s},[xn],imm + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;18={vt.1d},[xn] + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;19={vt.1d},[xn],xm + <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\ ;20={vt.1d},[xn],imm + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\ ;21={vt.2d},[xn] + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ;22={vt.2d},[xn],xm + <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2> ;23={vt.2d},[xn],imm + pop ebx + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + cmp [simd_reg_list_count],bl + jnz ERROR_parameter_n_not_valid.first + mov ah,0 + mov cl,3 + div cl ;al=reg selection, ah=address mode + mov ebp,[arm64_instruction] + cmp ah,1 + jz .encode + ;check immediate + btr ebp,23 + test ah,ah + jz .encode + bts ebp,23 + mov [operand_register2],0x1f + movzx ecx,al + shr ecx,1 + movzx edx,[simd_reg_list_count] + shl edx,cl + mov ecx,[ARM64_ld1_error_table2-4+edx*4] + cmp edx,[immediate_value2] + jnz ARM_store_instruction_with_error + .encode: + movzx eax,al + mov edx,eax + and eax,110b + and edx,001b + shl eax,10-1 + shl edx,30-0 + or ebp,eax ;set size + or ebp,edx ;set Q + jmp ARM64_arithmetic1.encode_rm + +ARM64_ld2r: + ;used by LD2R + push 2 + jmp ARM64_ld1r.do + +ARM64_ld3r: + ;used by LD3R + push 3 + jmp ARM64_ld1r.do + +ARM64_ld4r: + ;used by LD4R + push 4 + jmp ARM64_ld1r.do + +ARM64_arithmetic17: + ;used by MLA + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 0=vd,vn,vm + <TMPL_never>,\ ; 1 + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 2=vd,vn,vm + <TMPL_never>,\ ; 3 + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 4=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\ ; 5=vd,vn,vm.h[] + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 6=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\ ; 7=vd,vn,vm.h[] + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 8=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\ ; 9=vd,vn,vm.s[] + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;10=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s> ;11=vd,vn,vm.s[] + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;vector + mov ebx,[arm64_instruction2] ;element + jmp ARM64_arithmetic6.vector_encode + +ARM64_movi_table: + ;Q:op,cmode + db 0000b,1110b,0+0 shl 4,12-3+1 ; 0=vd,imm + db 0000b,1110b,0+0 shl 4,12-3+1 ; 1=vd,imm,lsl imm + db 0100b,1110b,0+0 shl 4,12-3+1 ; 2=vd,imm + db 0100b,1110b,0+0 shl 4,12-3+1 ; 3=vd,imm,lsl imm + db 0000b,1000b,0+1 shl 4,12-3+1 ; 4=vd,imm + db 0000b,1000b,0+1 shl 4,12-3+1 ; 5=vd,imm,lsl imm + db 0100b,1000b,0+1 shl 4,12-3+1 ; 6=vd,imm + db 0100b,1000b,0+1 shl 4,12-3+1 ; 7=vd,imm,lsl imm + db 0000b,0000b,0+3 shl 4,12-3+1 ; 8=vd,imm + db 0000b,0000b,0+3 shl 4,12-3+1 ; 9=vd,imm,lsl imm + db 0000b,1100b,1+2 shl 4,12-3+0 ;10=vd,imm,msl imm + db 0100b,0000b,0+3 shl 4,12-3+1 ;11=vd,imm + db 0100b,0000b,0+3 shl 4,12-3+1 ;12=vd,imm,lsl imm + db 0100b,1100b,1+2 shl 4,12-3+0 ;13=vd,imm,msl imm + db 0010b,1110b,0,0 ;14=dd,imm + db 0110b,1110b,0,0 ;15=vd,imm + +ARM64_movi: + ;used by MOVI + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_imm>,\ ; 0=vd,imm + <TMPL_vect_v8b,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 1=vd,imm,lsl imm + <TMPL_vect_v16b,TMPL_imm>,\ ; 2=vd,imm + <TMPL_vect_v16b,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 3=vd,imm,lsl imm + <TMPL_vect_v4h,TMPL_imm>,\ ; 4=vd,imm + <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 5=vd,imm,lsl imm + <TMPL_vect_v8h,TMPL_imm>,\ ; 6=vd,imm + <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 7=vd,imm,lsl imm + <TMPL_vect_v2s,TMPL_imm>,\ ; 8=vd,imm + <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ; 9=vd,imm,lsl imm + <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\ ;10=vd,imm,msl imm + <TMPL_vect_v4s,TMPL_imm>,\ ;11=vd,imm + <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;12=vd,imm,lsl imm + <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\ ;13=vd,imm,msl imm + <TMPL_vect_dreg,TMPL_imm64>,\ ;14=dd,imm + <TMPL_vect_v2d,TMPL_imm64> ;15=vd,imm + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] + cmp al,14 + jae .imm64 + xor ah,ah + ;construct the immediate + mov edx,[immediate_value] + mov ecx,[immediate_value2] + xor ebx,ebx + cmp al,10 ;imm,msl imm + jz .msl + cmp al,13 ;imm,msl imm + jz .msl + test edx,edx + jz .immediate_ready + cmp ecx,32 + jae .out_of_range + shld ebx,edx,cl + test ebx,ebx + jnz .out_of_range + shl edx,cl + jmp .immediate_ready + .msl: + sub al,2 + cmp ecx,32 + jae .out_of_range + inc edx + shld ebx,edx,cl + shl edx,cl + sub edx,1 + sbb ebx,0 + jnz .out_of_range + .immediate_ready: + push eax edx + xor ecx,ecx + test edx,edx + jz .immediate_shifted + bsf ecx,edx + and ecx,not 7 + shr edx,cl + cmp edx,0xff + jbe .immediate_shifted + test ecx,ecx + jnz .try_inverse + cmp al,8 + jb .try_inverse + setz cl + cmp al,11 + setz ch + or cl,ch + lea eax,[eax+ecx+1] + cmp dl,0xff + jnz .try_inverse + mov ecx,8 + shr edx,8 + cmp dl,0xff + jnz .immediate_shifted + mov ecx,16 + shr edx,8 + .immediate_shifted: + cmp edx,0xff + ja .try_inverse + mov [immediate_value],edx + mov [immediate_value2],ecx + movzx eax,al + movzx ecx,byte[ARM64_movi_table+eax*4+2] + shl ecx,3 + mov ebx,ecx + and ecx,0x78 + shr ebx,4 + and ebx,0x78 + mov edx,[immediate_value2] + test edx,0x7 + jnz .try_inverse + cmp edx,ecx + jz .imm2_okay + cmp edx,ebx + ja .try_inverse + .imm2_okay: + sub edx,ecx + movzx ecx,byte[ARM64_movi_table+eax*4+3] + shl edx,cl + or ebp,edx + mov edx,[immediate_value] + add esp,8 + .encode_imm: + mov ecx,edx + and edx,00011111b + and ecx,11100000b + shl edx,5 + shl ecx,16-5 + or ebp,edx + or ebp,ecx + movzx eax,al + movzx edx,byte[ARM64_movi_table+eax*4+0] + movzx ecx,byte[ARM64_movi_table+eax*4+1] + shl edx,28 + shl ecx,12 + or ebp,edx + or ebp,ecx + jmp ARM64_arithmetic1.encode_rd + .imm64: + mov ecx,[immediate_value] + mov ebx,[immediate_value_high] + mov edx,1 shl 7 + .check_imm64: + inc cl + cmp cl,1 + ja .cannot_encode + rcr dl,1 + jc .encode_imm + shrd ecx,ebx,8 + shr ebx,8 + jmp .check_imm64 + .cannot_encode: + mov ecx,ERROR_immediate_cannot_be_encoded + jmp ARM_store_instruction_with_error + .try_inverse: + xor ebp,1 shl 29 + pop edx eax + cmp al,4 + jb .out_of_range + mov ecx,0xffff + mov ebx,0xffffffff + cmp al,8 + cmovb ebx,ecx + xor edx,ebx + xor ah,0xff + jnz .immediate_ready + .out_of_range: + mov ecx,ERROR_immediate_value_out_of_range.0_0xff + cmp al,4 + jb ARM_store_instruction_with_error + mov ecx,ERROR_immediate_value_out_of_range.0_0xff_lsl_8 + cmp al,8 + jb ARM_store_instruction_with_error + mov ecx,ERROR_immediate_value_out_of_range.0_0xff_msl + jmp ARM_store_instruction_with_error + +ARM64_mvni: + ;used by MVNI + call decode_template + TEMPLATE \ + <TMPL_vect_v4h,TMPL_imm>,\ ;0=vd,imm + <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;1=vd,imm,lsl imm + <TMPL_vect_v8h,TMPL_imm>,\ ;2=vd,imm + <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;3=vd,imm,lsl imm + <TMPL_vect_v2s,TMPL_imm>,\ ;4=vd,imm + <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;5=vd,imm,lsl imm + <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\ ;6=vd,imm,msl imm + <TMPL_vect_v4s,TMPL_imm>,\ ;7=vd,imm + <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\ ;8=vd,imm,lsl imm + <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2> ;9=vd,imm,msl imm + add al,4 + jmp ARM64_movi.do + +ARM64_polynomial: + ;used by PMULL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v1q,TMPL_vect_v1d,TMPL_vect_v1d> ;1=vd,vn,vm + test al,al + jz ARM64_vector_scalar_bhsd_two_reg.encode + or [arm64_instruction],11b shl 22 + jmp ARM64_crypto_two_reg.do + +ARM64_polynomial2: + ;used by PMULL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;0=vd,vn,vm + <TMPL_vect_v1q,TMPL_vect_v2d,TMPL_vect_v2d> ;1=vd,vn,vm + test al,al + jz ARM64_vector_scalar_bhsd_two_reg.encode + or [arm64_instruction],11b shl 22 + jmp ARM64_crypto_two_reg.do + +ARM64_vector_narrow_shift_low: + ;used by RSHRN, SHRN + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_imm> ;2=vd,vn,imm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + mov cl,al + mov ebx,8 + shl ebx,cl + mov edx,[immediate_value] + cmp edx,ebx + ja .out_of_range + test edx,edx + jz .out_of_range + shl ebx,1 + sub ebx,edx + shl ebx,16 + or ebp,ebx + jmp ARM64_arithmetic1.encode_rn + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.1_8 + mov edx,ERROR_shift_value_out_of_range.1_16 + mov eax,ERROR_shift_value_out_of_range.1_32 + cmp ebx,16 + cmovz ecx,edx + cmova ecx,eax + jmp ARM_store_instruction_with_error + +ARM64_vector_narrow_shift_high: + ;used by RSHRN2, SHRN2, SQRSHRN2, SQRSHRUN2, SQSRHN2, SQSHRUN2, UQRSHRN2, UQSHRN2 + call decode_template + TEMPLATE \ + <TMPL_vect_v16b,TMPL_vect_v8h,TMPL_imm>,\ ;0=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v4s,TMPL_imm>,\ ;1=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v2d,TMPL_imm> ;2=vd,vn,vm + jmp ARM64_vector_narrow_shift_low.encode + +ARM64_vector_bhs_three_reg: + ;used by SABA, SABD, SHADD, SHSUB, SMAX, SMAXP, SMIN, SMINP, SRHADD, + ; UABA, UABD, UHADD, UHSUB, UMAX, UMAXP, UMIN, UMINP, URHADD + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;1=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;3=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s> ;5=vd,vn,vm + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_bhs_three_reg_long: + ;used by SABAL, SABDL, SADDL, SSUBL, UABAL, SABDL, UADDL, USUBL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;1=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s> ;2=vd,vn,vm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_bhs_three_reg_long2: + ;used by SABAL2, SABDL2, SADDL2, SSUBL2, UABAL2, SABDL2, UADDL2, USUBL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;1=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s> ;2=vd,vn,vm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_bhs_two_reg_pair: + ;used by SADALP, SADDLP, UADALP, UADDLP + call decode_template + TEMPLATE \ + <TMPL_vect_v4h,TMPL_vect_v8b>,\ ;0=vd,vn + <TMPL_vect_v8h,TMPL_vect_v16b>,\ ;1=vd,vn + <TMPL_vect_v2s,TMPL_vect_v4h>,\ ;2=vd,vn + <TMPL_vect_v4s,TMPL_vect_v8h>,\ ;3=vd,vn + <TMPL_vect_v1d,TMPL_vect_v2s>,\ ;4=vd,vn + <TMPL_vect_v2d,TMPL_vect_v4s> ;5=vd,vn + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_scalar_vector_bhs_two_reg: + ;used by SADALV, UADDLV + call decode_template + TEMPLATE \ + <TMPL_vect_hreg,TMPL_vect_v8b>,\ ;0=hd,vn + <TMPL_vect_hreg,TMPL_vect_v16b>,\ ;1=hd,vn + <TMPL_vect_sreg,TMPL_vect_v4h>,\ ;2=sd,vn + <TMPL_vect_sreg,TMPL_vect_v8h>,\ ;3=sd,vn + <TMPL_never>,\ ;4=- + <TMPL_vect_dreg,TMPL_vect_v4s> ;5=dd,vn + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_bhs_three_reg_wide: + ;used by SADDW, SSUBW, UADDW, USUBW + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4h>,\ ;1=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2s> ;2=vd,vn,vm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_vector_bhs_three_reg_wide2: + ;used by SADDW2, SSUBW2, UADDW2, USUBW2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v16b>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v8h>,\ ;1=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v4s> ;2=vd,vn,vm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_scalar_vector_sd_convert_zero_s_table: + db 0,1,10,11,14,15,2,3,12,13,16,17,4,5,6,7,8,9 + +ARM64_scalar_vector_sd_convert_zero_s: + ;used by SCVTF + push 0x1e220000 + .do: + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ; 0=sd,sn sz=0 + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ; 1=sd,sn,imm sz=0 + <TMPL_vect_sreg,TMPL_word_z_reg>,\ ; 2=sd,wn + <TMPL_vect_sreg,TMPL_word_z_reg,TMPL_imm>,\ ; 3=sd,wn,imm + <TMPL_vect_sreg,TMPL_dword_z_reg>,\ ; 4=sd,xn + <TMPL_vect_sreg,TMPL_dword_z_reg,TMPL_imm>,\ ; 5=sd,xn,imm + <TMPL_vect_dreg,TMPL_vect_dreg>,\ ; 6=dd,dn sz=1 + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ; 7=dd,dn,imm sz=1 + <TMPL_vect_dreg,TMPL_word_z_reg>,\ ; 8=dd,wn + <TMPL_vect_dreg,TMPL_word_z_reg,TMPL_imm>,\ ; 9=dd,wn,imm + <TMPL_vect_dreg,TMPL_dword_z_reg>,\ ;10=dd,xn + <TMPL_vect_dreg,TMPL_dword_z_reg,TMPL_imm>,\ ;11=dd,xn,imm + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;12=vd,vn sz=0 q=0 + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;13=vd,vn,imm sz=0 q=0 + <TMPL_vect_v2d,TMPL_vect_v2d>,\ ;14=vd,vn sz=1 q=1 + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ;15=vd,vn,imm sz=1 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ;16=vd,vn sz=0 q=1 + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm> ;17=vd,vn,imm sz=0 q=1 + movzx eax,al + mov al,[ARM64_scalar_vector_sd_convert_zero_s_table+eax] + shr al,1 + jnc ARM64_vector_scalar_sdwx_two_reg_as.encode + ;fixed point + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + xor dword[esp],1 shl 21 + xor [arm64_instruction],0x01213c00 + xor [arm64_instruction2],0x01213c00 + jmp ARM64_vector_scalar_sd_convert_zero_s.encode + +ARM64_scalar_vector_sd_convert_zero_u: + ;used by UCVTF + push 0x1e230000 + jmp ARM64_scalar_vector_sd_convert_zero_s.do + +ARM64_sha_qsv: + ;used by SHA1C, SHA1M, SHA1P + call decode_template + TEMPLATE \ + <TMPL_vect_qreg,TMPL_vect_sreg,TMPL_vect_v4s> ;0=qd,sn,vm + jmp ARM64_crypto_two_reg.do + +ARM64_sha_s_two_reg: + ;used by SHA1H + call decode_template + TEMPLATE \ + <TMPL_vect_sreg,TMPL_vect_sreg> ;0=sd,sn + jmp ARM64_crypto_two_reg.do + +ARM64_sha_vs_three_reg: + ;used by SHA1SU0, SHA256SU1 + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s> ;0=vd,vn,vm + jmp ARM64_crypto_two_reg.do + +ARM64_sha_vs_two_reg: + ;used by SHA1SU1, SHA256SU0 + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v4s> ;0=vd,vn + jmp ARM64_crypto_two_reg.do + +ARM64_sha_qqv: + ;used by SHA256H, SHA256H2 + call decode_template + TEMPLATE \ + <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_vect_v4s> ;0=qd,qn,vm + jmp ARM64_crypto_two_reg.do + +ARM64_vector_scalar_bhsd_two_reg_left_imm: + ;used by SHL, SLI + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ;2=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ;3=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;4=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ;5=vd,vn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;6=dd,dn,imm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm> ;7=vd,vn,imm + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + .immediate_encode: + movzx ecx,al + shr ecx,1 + mov edx,8 + shl edx,cl + cmp edx,[immediate_value] + jbe .out_of_range + add edx,[immediate_value] + shl edx,16 + or ebp,edx + .vector_encode: + cmp al,6 ;scalar? + setz dl + shr al,1 + setc cl + shl ecx,30 + or ebp,ecx ;set Q + neg dl + and dl,5 + shl edx,28 + or ebp,edx ;set for scalar + jmp ARM64_arithmetic1.encode_rm + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.0_7 + mov ebx,ERROR_shift_value_out_of_range.0_15 + mov eax,ERROR_shift_value_out_of_range.0_31 + mov ebp,ERROR_shift_value_out_of_range.0_63 + cmp edx,16 + cmovz ecx,ebx + cmp edx,32 + cmovz ecx,eax + cmova ecx,ebp + jmp ARM_store_instruction_with_error + +ARM64_vector_scalar_bhsd_two_reg_right_imm: + ;used by SRI, SRSHR, SRSRA, SSHR, SSRA, URSHR, URSRA, USHR, USRA + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ;2=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ;3=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ;4=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ;5=vd,vn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\ ;6=dd,dn,imm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm> ;7=vd,vn,imm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + .immediate_encode: + movzx ecx,al + shr ecx,1 + mov edx,8 + shl edx,cl + mov ebx,[immediate_value] + test ebx,ebx + je .out_of_range + cmp edx,ebx + jb .out_of_range + add edx,edx + sub edx,ebx + shl edx,16 + or ebp,edx + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.vector_encode + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.1_8 + mov ebx,ERROR_shift_value_out_of_range.1_16 + mov eax,ERROR_shift_value_out_of_range.1_32 + mov ebp,ERROR_shift_value_out_of_range.1_64 + cmp edx,16 + cmovz ecx,ebx + cmp edx,32 + cmovz ecx,eax + cmova ecx,ebp + jmp ARM_store_instruction_with_error + +ARM64_vector_scalar_bhs_long_size: + ;used by SHLL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_imm> ;2=vd,vn,imm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + movzx ecx,al + mov edx,8 + shl edx,cl + cmp edx,[immediate_value] + jne .out_of_range + add al,al + jmp ARM64_arithmetic1.vector_encode + .out_of_range: + mov ecx,ERROR_shift_value_out_of_range.8 + mov ebx,ERROR_shift_value_out_of_range.16 + mov eax,ERROR_shift_value_out_of_range.32 + cmp edx,16 + cmovz ecx,ebx + cmova ecx,eax + jmp ARM_store_instruction_with_error + +ARM64_vector_scalar_bhs_long2_size: + ;used by SHLL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_imm> ;2=vd,vn,imm + jmp ARM64_vector_scalar_bhs_long_size.encode + +ARM64_arithmetic18_long: + ;used by SMLAL, SMLSL, UMLAL, UMLSL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_never>,\ ;1=- + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\ ;3=vd,vn,vm.h[] + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s> ;5=vd,vn,vm.s[] + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;vector + mov ebx,[arm64_instruction2] ;element + shr al,1 + lea eax,[eax+eax] + rcl al,1 + jmp ARM64_arithmetic6.vector_encode + +ARM64_arithmetic18_long2: + ;used by SMLAL2, SMLSL2, SMULL2, UMLAL2, UMLSL2, UMULL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;0=vd,vn,vm + <TMPL_never>,\ ;1=- + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;2=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_element_h>,\ ;3=vd,vn,vm.h[] + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;4=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_element_s> ;5=vd,vn,vm.s[] + jmp ARM64_arithmetic18_long.do + +ARM64_smov: + ;used by SMOV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_vect_element_b>,\ ;0=wd,vn.b[] + <TMPL_word_z_reg,TMPL_vect_element_h>,\ ;1=wd,vn.h[] + <TMPL_never>,\ ;2=- + <TMPL_dword_z_reg,TMPL_vect_element_b>,\ ;3=xd,vn.b[] + <TMPL_dword_z_reg,TMPL_vect_element_h>,\ ;4=xd,vn.h[] + <TMPL_dword_z_reg,TMPL_vect_element_s> ;5=xd,vn.s[] + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + cmp al,3 + jb .Q_okay + or ebp,1 shl 30 + sub al,3 + .Q_okay: + lea ecx,[eax+16] + mov eax,[immediate_value2] + add eax,eax + inc eax + shl eax,cl + or ebp,eax + jmp ARM64_dz_nz_mz.encode_rd + +ARM64_umov: + ;used by UMOV + call decode_template + TEMPLATE \ + <TMPL_word_z_reg,TMPL_vect_element_b>,\ ;0=wd,vn.b[] + <TMPL_word_z_reg,TMPL_vect_element_h>,\ ;1=wd,vn.h[] + <TMPL_word_z_reg,TMPL_vect_element_s>,\ ;2=wd,vn.s[] + <TMPL_dword_z_reg,TMPL_vect_element_d>,\ ;3=xd,vn.d[] + <TMPL_dword_z_reg,TMPL_vect_element_b>,\ ;4=xd,vn.b[] + <TMPL_dword_z_reg,TMPL_vect_element_h>,\ ;5=xd,vn.h[] + <TMPL_dword_z_reg,TMPL_vect_element_s> ;6=xd,vn.s[] + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + and al,3 + cmp al,3 + setae cl + shl ecx,30 + or ebp,ecx + lea ecx,[eax+16] + mov eax,[immediate_value2] + add eax,eax + inc eax + shl eax,cl + or ebp,eax + jmp ARM64_dz_nz_mz.encode_rd + +ARM64_vector_scalar_bhsd_two_reg_q: + ;used by SQABS, SQNEG, SUQADD, USQADD + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 0=vd,vn + <TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 1=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 2=vd,vn + <TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 3=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 4=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s>,\ ; 5=vd,vn + <TMPL_never>,\ ; 6=- + <TMPL_vect_v2d,TMPL_vect_v2d>,\ ; 7=vd,vn + <TMPL_vect_breg,TMPL_vect_breg>,\ ; 8=bd,bn + <TMPL_vect_hreg,TMPL_vect_hreg>,\ ; 9=hd,hn + <TMPL_vect_sreg,TMPL_vect_sreg>,\ ;10=sd,sn + <TMPL_vect_dreg,TMPL_vect_dreg> ;11=dd,dn + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + cmp al,7 + jbe ARM64_arithmetic1.vector_encode + sub al,8 + or ebp,5 shl 28 + jmp ARM64_scalar_sd_four_reg.encode_size + +ARM64_vector_scalar_bhsd_three_reg_q: + ;used by SQADD, SQRSHL, SQSUB, UQADD, UQRSHL, UQSUB + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 1=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 3=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 4=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ; 5=vd,vn,vm + <TMPL_never>,\ ; 6=- + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ; 7=vd,vn,vm + <TMPL_vect_breg,TMPL_vect_breg,TMPL_vect_breg>,\ ; 8=bd,bn,bm + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\ ; 9=hd,hn,hm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;10=sd,sn,sm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg> ;11=dd,dn,dm + .encode: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + cmp al,7 + jbe ARM64_arithmetic1.vector_encode + sub al,8 + or ebp,5 shl 28 + jmp ARM64_scalar_sd_four_reg.encode_size + +ARM64_arithmetic19_long: + ;used by SQDMLAL, SQDMLSL, SQDMULL + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\ ;1=vd,vn,vm.h[] + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;2=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s> ;3=vd,vn,vm.s[] + .do: + add al,2 + jmp ARM64_arithmetic18_long.do + +ARM64_arithmetic19_long2: + ;used by SQDMLAL2, SQDMLSL2, SQDMULL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;0=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_element_h>,\ ;1=vd,vn,vm.h[] + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;2=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_element_s> ;3=vd,vn,vm.s[] + jmp ARM64_arithmetic19_long.do + +ARM64_arithmetic20: + ;used by SQDMULH, SQRDMULH + call decode_template + TEMPLATE \ + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 0=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\ ; 1=vd,vn,vm.h[] + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\ ; 3=vd,vn,vm.h[] + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 4=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\ ; 5=vd,vn,vm.s[] + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ; 6=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>,\ ; 7=vd,vn,vm.s[] + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\ ; 8=hd,hn,hm + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_element_h>,\ ; 9=hd,hn,vm.h[] + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;10=sd,sn,sm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s> ;11=sd,sn,vm.s[] + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + cmp al,7 + jbe .vector + sub al,8 + shr al,1 + lea eax,[eax+eax] + rcl al,1 + or [arm64_instruction],5 shl 28 + or [arm64_instruction2],5 shl 28 + .vector: + add al,4 + jmp ARM64_arithmetic17.do + +ARM64_vector_scalar_narrow_shift_high: + ;used by SQRSHRN, SQRSHRUN, SQSHRN, SQSHRUN, UQRSHRN, UQSHRN + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_imm>,\ ;2=vd,vn,imm + <TMPL_vect_breg,TMPL_vect_hreg,TMPL_imm>,\ ;3=bd,hn,imm + <TMPL_vect_hreg,TMPL_vect_sreg,TMPL_imm>,\ ;4=hd,sn,imm + <TMPL_vect_sreg,TMPL_vect_dreg,TMPL_imm> ;5=sd,dn,imm + cmp al,3 + jb ARM64_vector_narrow_shift_low.encode + sub al,3 + or [arm64_instruction],0x5 shl 28 + jmp ARM64_vector_narrow_shift_low.encode + +ARM64_vector_scalar_bhsd_shift_reg_imm: + ;used by SQSHL, UQSHL + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ; 0=vd,vn,vm + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ; 1=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\ ; 2=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ; 3=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ; 4=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ; 5=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ; 6=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ; 7=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ; 8=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ; 9=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;10=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ;11=vd,vn,imm + <TMPL_never>,\ ;12=- + <TMPL_never>,\ ;13=- + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\ ;14=vd,vn,vm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ;15=vd,vn,imm + <TMPL_vect_breg,TMPL_vect_breg,TMPL_vect_breg>,\ ;16=bd,bn,bm + <TMPL_vect_breg,TMPL_vect_breg,TMPL_imm>,\ ;17=bd,bn,imm + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\ ;18=hd,hn,hm + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_imm>,\ ;19=hd,hn,imm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;20=sd,sn,sm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ;21=sd,sn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\ ;22=dd,dn,dm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm> ;23=dd,dn,imm + .do: + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + shr al,1 + jc .immediate + mov ebp,[arm64_instruction] ;recover the template + cmp al,7 + jbe ARM64_arithmetic1.vector_encode + sub al,8 + or ebp,5 shl 28 + jmp ARM64_scalar_sd_four_reg.encode_size + .immediate: + mov ebp,[arm64_instruction2] ;recover the other template + cmp al,7 + jbe ARM64_vector_scalar_bhsd_two_reg_left_imm.immediate_encode + sub al,8 + add al,al + or ebp,5 shl 28 + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.immediate_encode + +ARM64_vector_scalar_bhsd_shift_imm: + ;used by SQSHLU + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\ ; 0=vd,vn,imm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\ ; 1=vd,vn,imm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\ ; 2=vd,vn,imm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\ ; 3=vd,vn,imm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\ ; 4=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\ ; 5=vd,vn,imm + <TMPL_never>,\ ; 6=- + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\ ; 7=vd,vn,imm + <TMPL_vect_breg,TMPL_vect_breg,TMPL_imm>,\ ; 8=bd,bn,imm + <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_imm>,\ ; 9=hd,hn,imm + <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\ ;10=sd,sn,imm + <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm> ;11=dd,dn,imm + lea eax,[eax+eax+1] + jmp ARM64_vector_scalar_bhsd_shift_reg_imm.do + +ARM64_vector_scalar_narrow_extract_low: + ;used by SQXTN, SQXTUN, UQXTN + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8h>,\ ;0=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4s>,\ ;1=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2d>,\ ;2=vd,vn + <TMPL_vect_breg,TMPL_vect_hreg>,\ ;3=bd,hn + <TMPL_vect_hreg,TMPL_vect_sreg>,\ ;4=hd,sn + <TMPL_vect_sreg,TMPL_vect_dreg> ;5=sd,dn + cmp al,3 + jb ARM64_vector_narrow_low.encode + sub al,3 + or [arm64_instruction],0x5 shl 28 + jmp ARM64_vector_narrow_low.encode + +ARM64_vector_narrow_extract_low: + ;used by XTN + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8h>,\ ;0=vd,vn + <TMPL_vect_v4h,TMPL_vect_v4s>,\ ;1=vd,vn + <TMPL_vect_v2s,TMPL_vect_v2d> ;2=vd,vn + jmp ARM64_vector_narrow_low.encode + +ARM64_vector_narrow_extract_high: + ;used by SQXTN2, SQXTUN2, UQXTN2, XTN2 + call decode_template + TEMPLATE \ + <TMPL_vect_v16b,TMPL_vect_v8h>,\ ;0=vd,vn + <TMPL_vect_v8h,TMPL_vect_v4s>,\ ;1=vd,vn + <TMPL_vect_v4s,TMPL_vect_v2d> ;2=vd,vn + jmp ARM64_vector_narrow_low.encode + +ARM64_vector_scalar_bhs_long_imm: + ;used by SSHLL, USHLL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_imm> ;2=vd,vn,imm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.do + +ARM64_vector_scalar_bhs_long2_imm: + ;used by SSHLL2, USHLL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_imm>,\ ;0=vd,vn,imm + <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_imm>,\ ;1=vd,vn,imm + <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_imm> ;2=vd,vn,imm + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.do + +ARM64_vector_scalar_bhs_long: + ;used by SXTL, UXTL + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v8b>,\ ;0=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4h>,\ ;1=vd,vn + <TMPL_vect_v2d,TMPL_vect_v2s> ;2=vd,vn + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.do + +ARM64_vector_scalar_bhs_long2: + ;used by SXTL2, UXTL2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8h,TMPL_vect_v16b>,\ ;0=vd,vn + <TMPL_vect_v4s,TMPL_vect_v8h>,\ ;1=vd,vn + <TMPL_vect_v2d,TMPL_vect_v4s> ;2=vd,vn + add al,al + jmp ARM64_vector_scalar_bhsd_two_reg_left_imm.do + +ARM64_tb1: + ;used by TBL, TBX + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_list_16b,TMPL_vect_v8b>,\ ;0=vd,{vn.16b},vm + <TMPL_vect_v16b,TMPL_vect_list_16b,TMPL_vect_v16b> ;1=vd,{vn.16b},vm + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32 + jz ERROR_requires_cpu64_capability_SIMD + mov ebp,[arm64_instruction] ;recover the template + movzx edx,[simd_reg_list_count] + shl eax,30 + or ebp,eax ;set Q + dec edx + shl edx,13 + or ebp,edx ;set len + jmp ARM64_arithmetic1.encode_rm + +ARM64_vector_bhsd_three_reg: + ;used by TRN1, TRN2, UZP1, UZP2, ZIP1, ZIP2 + call decode_template + TEMPLATE \ + <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\ ;0=vd,vn,vm + <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\;1=vd,vn,vm + <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\ ;2=vd,vn,vm + <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\ ;3=vd,vn,vm + <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\ ;4=vd,vn,vm + <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\ ;5=vd,vn,vm + <TMPL_never>,\ ;6=dd,dn,dm + <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d> ;7=vd,vn,vm + jmp ARM64_vector_scalar_bhsd_two_reg.encode + +ARM64_arithmetic21: + ;used by URECPE, URSQRTE + call decode_template + TEMPLATE \ + <TMPL_vect_v2s,TMPL_vect_v2s>,\ ;0=vd,vn + <TMPL_vect_v4s,TMPL_vect_v4s> ;1=vd,vn + test [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32 + jz ERROR_requires_cpu64_capability_FP + mov ebp,[arm64_instruction] ;recover the template + shl eax,30 + or ebp,eax ;set Q + jmp ARM64_arithmetic1.encode_rn + +;CRC + +CRC32_polynomial_ISO3309 = 0xedb88320 ;x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + x^0 +CRC32_table_length = 256*4*4 ;a constant, don't adjust +CRC32_loop_size = 4 ;an optimising parameter, adjust if you want + +CRC_32: + ;used by CRC32 + ;crc32 dest_var from start,length[,polynomial] + lodsw + cmp ax,0x1128 ;'(' + 0x11 + jne ERROR_parameter_n_not_valid.first + lodsd + push eax ;save dest_var + lodsb + cmp al,')' + jne ERROR_parameter_n_not_valid.first + mov [operand_size],1 + and dword[value],0 + and dword[value+4],0 + lodsb + cmp al,82h ;from? + jne ERROR_parameter_n_not_valid.second + call get_data_point + sbb ecx,ecx + not ecx + and ebx,ecx + lodsb + cmp al,',' + jnz ERROR_parameter_n_not_valid.second + push ebx + call get_value + pop ebx + cmp [value_type],0 + jne ERROR_parameter_n_not_valid.third + test edx,edx + jne ERROR_parameter_n_not_valid.third + lea edx,[eax+ebx] + sub edx,[ds:ebp+0x18] + cmp [ds:ebp+0x1c],edx + sbb ecx,ecx + not ecx + and ebx,ecx + mov ebp,CRC32_polynomial_ISO3309 + push ebx eax + cmp byte[esi],',' ;is the polynomial specified? + jnz .construct + inc esi + call get_value + cmp [value_type],0 + jne ERROR_parameter_n_not_valid.fourth + test edx,edx + jne ERROR_parameter_n_not_valid.fourth + mov ebp,eax + .construct: + call CRC32_construct_table + pop ecx edx + test edx,edx + jz .out_of_range + or eax,-1 ;eax=crc + test ecx,ecx + jz .done + test dl,3 + jne .align + .begin: + sub ecx,CRC32_loop_size*8 + jb .tail + .main_loop: + repeat CRC32_loop_size + xor eax,[edx+(%-1)*8] + movzx ebp,al + mov ebx,[edi+3*256*4+4*ebp] + movzx ebp,ah + xor ebx,[edi+2*256*4+4*ebp] + shr eax,16 + movzx ebp,al + xor ebx,[edi+1*256*4+4*ebp] + shr eax,8 + xor ebx,[edi+0*256*4+4*eax] + xor ebx,[edx+(%-1)*8+4] + movzx ebp,bl + mov eax,[edi+3*256*4+4*ebp] + movzx ebp,bh + xor eax,[edi+2*256*4+4*ebp] + shr ebx,16 + movzx ebp,bl + xor eax,[edi+1*256*4+4*ebp] + shr ebx,8 + xor eax,[edi+0*256*4+4*ebx] + end repeat + add edx,CRC32_loop_size*8 + sub ecx,CRC32_loop_size*8 + jae .main_loop + .tail: + sub ecx,4-CRC32_loop_size*8 + jb .finish + .tail_loop: + xor eax,[edx] + add edx,4 + movzx ebp,al + mov ebx,[edi+3*256*4+4*ebp] + movzx ebp,ah + xor ebx,[edi+2*256*4+4*ebp] + shr eax,16 + movzx ebp,al + xor ebx,[edi+1*256*4+4*ebp] + shr eax,8 + xor ebx,[edi+0*256*4+4*eax] + mov eax,ebx + sub ecx,4 + jae .tail_loop + .finish: + sub ecx,1-4 + jb .done + .prolog: + movzx ebx,byte[edx] + xor bl,al + shr eax,8 + xor eax,[edi+4*ebx] + inc edx + dec ecx + jns .prolog + .done: + mov dword[value],eax + .store_crc: + mov [value_sign],0 + mov eax,dword[value] + mov edx,dword[value+4] + pop ebx + xor cx,cx + jmp make_constant + .align: + movzx ebx,byte[edx] + xor bl,al + shr eax,8 + xor eax,[edi+4*ebx] + inc edx + dec ecx + je .done + test dl,3 + jne .align + jmp .begin + .out_of_range: + call recoverable_overflow + jmp .store_crc + +CRC32_construct_table: + lea eax,[edi+CRC32_table_length] + cmp eax,[tagged_blocks] + jae out_of_memory + xor edx,edx + .a: mov eax,edx + mov ebx,8 + .b: shr eax,1 + sbb ecx,ecx + and ecx,ebp + xor eax,ecx + dec ebx + jnz .b + mov [edi+4*edx],eax + inc dl + jnz .a + xor edx,edx + .c: mov eax,[edi+4*edx] + mov ebx,3 + lea ebp,[edi+4*edx+1*256*4] + .d: movzx ecx,al + mov ecx,[edi+4*ecx] + shr eax,8 + xor eax,ecx + mov [ebp],eax + add ebp,1*256*4 + dec ebx + jnz .d + inc dl + jnz .c + ret + +;shared errors + +ERROR_illegal_instruction =illegal_instruction +ERROR_value_out_of_range =value_out_of_range +ERROR_relative_jump_out_of_range =relative_jump_out_of_range +ERROR_operand_sizes_do_not_match =operand_sizes_do_not_match + +ERROR_code_is_not_in_a_section: + call assembler_error + db 'Code placed before section defined',0 +ERROR_expecting_section_name: + call assembler_error + db 'Section directive must be followed by the section name',0 +ERROR_duplicate_align_setting: + call assembler_error + db 'An alignment setting was specified twice',0 +ERROR_duplicate_flag_setting: + call assembler_error + db 'A flag setting was specified twice',0 +ERROR_invalid_use_of_symbol_in_align: + call assembler_error + db 'Invalid use of symbol for "align" setting',0 +ERROR_invalid_use_of_symbol_in_at: + call assembler_error + db 'Invalid use of symbol for "at" setting',0 +ERROR_section_flags_zero: + call assembler_error + db 'At least one section flag (executable, readable or writeable) must be specified',0 +ERROR_section_align_zero: + call assembler_error + db 'Section alignment must be specified',0 +ERROR_line_processing_error: + call fatal_error + db 'Fatal: Failure when processing line numbers. There is a bug!',0 +ERROR_thumb_recode_error: + call assembler_error + db 'Fatal: Unable to recode instruction for thumb. There is a bug!',0 +ERROR_org_not_allowed: + call assembler_error + db '"ORG" not allowed in DWARF, use "SECTION ... at X" instead',0 +ERROR_section_at_not_aligned: + call assembler_error + db 'Section alignement and "AT" specified are not compatible',0 +ERROR_instruction_not_aligned: + call assembler_error + db 'Instruction origin not aligned',0 +ERROR_relative_jump_not_aligned: + call assembler_error + db 'Relative jump destination not aligned',0 +ERROR_shift_value_out_of_range: + .0: + call assembler_error + db 'Shift value out of range, only 0 allowed',0 + .0or1: + call assembler_error + db 'Shift value out of range (must be 0 or 1)',0 + .0or2: + call assembler_error + db 'Shift value out of range (must be 0 or 2)',0 + .0or3: + call assembler_error + db 'Shift value out of range (must be 0 or 3)',0 + .0or4: + call assembler_error + db 'Shift value out of range (must be 0 or 4)',0 + .0_3: + call assembler_error + db 'Shift value out of range (0-3)',0 + .0_4: + call assembler_error + db 'Shift value out of range (0-4)',0 + .0_7: + call assembler_error + db 'Shift value out of range (0-7)',0 + .0_8: + call assembler_error + db 'Shift value out of range (0-8)',0 + .0_15: + call assembler_error + db 'Shift value out of range (0-15)',0 + .0or16: + call assembler_error + db 'Shift value out of range (0 or 16)',0 + .0_16: + call assembler_error + db 'Shift value out of range (0-16)',0 + .0_24: + call assembler_error + db 'Shift value out of range (0, 8, 16 or 24)',0 + .0_31: + call assembler_error + db 'Shift value out of range (0-31)',0 + .0_32: + call assembler_error + db 'Shift value out of range (0-32)',0 + .0_48: + call assembler_error + db 'Shift value out of range (0, 16, 32 or 48)',0 + .1: + call assembler_error + db 'Shift value out of range (must be 1)',0 + .2: + call assembler_error + db 'Shift value out of range (must be 2)',0 + .8: + call assembler_error + db 'Shift value out of range (must be 8)',0 + .12: + call assembler_error + db 'Shift value out of range (must be 0 or 12)',0 + .16: + call assembler_error + db 'Shift value out of range (must be 16)',0 + .32: + call assembler_error + db 'Shift value out of range (must be 32)',0 + .1_8: + call assembler_error + db 'Shift value out of range (1-8)',0 + .1_16: + call assembler_error + db 'Shift value out of range (1-16)',0 + .1_31: + call assembler_error + db 'Shift value out of range (1-31)',0 + .1_32: + call assembler_error + db 'Shift value out of range (1-32)',0 + .0_63: + call assembler_error + db 'Shift value out of range (0-63)',0 + .1_64: + call assembler_error + db 'Shift value out of range (1-64)',0 +ERROR_immediate_offset_out_of_range: + call assembler_error + db 'Immediate offset out of range',0 + .0: + call assembler_error + db 'Immediate offset out of range (must be 0)',0 + .1: + call assembler_error + db 'Immediate offset out of range (must be 1)',0 + .2: + call assembler_error + db 'Immediate offset out of range (must be 2)',0 + .3: + call assembler_error + db 'Immediate offset out of range (must be 3)',0 + .4: + call assembler_error + db 'Immediate offset out of range (must be 4)',0 + .6: + call assembler_error + db 'Immediate offset out of range (must be 6)',0 + .8: + call assembler_error + db 'Immediate offset out of range (must be 8)',0 + .12: + call assembler_error + db 'Immediate offset out of range (must be 12)',0 + .16: + call assembler_error + db 'Immediate offset out of range (must be 16)',0 + .24: + call assembler_error + db 'Immediate offset out of range (must be 24)',0 + .32: + call assembler_error + db 'Immediate offset out of range (must be 32)',0 + .48: + call assembler_error + db 'Immediate offset out of range (must be 48)',0 + .64: + call assembler_error + db 'Immediate offset out of range (must be 64)',0 + .0xff: + call assembler_error + db 'Immediate offset out of range (-0xff to 0xff)',0 + .0x3fc: + call assembler_error + db 'Immediate offset out of range (-0xff to 0xff)*4',0 + .0xfff: + call assembler_error + db 'Immediate offset out of range (-0xfff to 0xfff)',0 + .0_0xffffff: + call assembler_error + db 'Immediate offset out of range (0 to 0xffffff)',0 + .0_0x3f: + call assembler_error + db 'Immediate offset out of range (0 to 0x3f)',0 + .0_0xff: + call assembler_error + db 'Immediate offset out of range (0 to 0xff)',0 + .0_0xfff: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff)',0 + .0_0xfff.m256_255: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff) and (-0x100 to +0xff)',0 + .0_0x1ffe.m256_255: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff)*2 and (-0x100 to +0xff)',0 + .0_0x3ffc.m256_255: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff)*4 and (-0x100 to +0xff)',0 + .0_0x7ff8.m256_255: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff)*8 and (-0x100 to +0xff)',0 + .0_0xfff0.m256_255: + call assembler_error + db 'Immediate offset out of range (0 to 0xfff)*16 and (-0x100 to +0xff)',0 + .0_0xffff: + call assembler_error + db 'Immediate offset out of range (0 to 0xffff)',0 + .0_0x1f: + call assembler_error + db 'Immediate offset out of range (0 to 0x1f)',0 + .0_0x3e: + call assembler_error + db 'Immediate offset out of range (0 to 0x1f)*2',0 + .0_0x7c: + call assembler_error + db 'Immediate offset out of range (0 to 0x1f)*4',0 + .0_0xfc: + call assembler_error + db 'Immediate offset out of range (0 to 0x3f)*4',0 + .0_0x1fc: + call assembler_error + db 'Immediate offset out of range (0 to 0x7f)*4',0 + .0_0x3fc: + call assembler_error + db 'Immediate offset out of range (0 to 0xff)*4',0 + .m28_0: + call assembler_error + db 'Immediate offset out of range (-7 to 0)*4',0 + .m256_252: + call assembler_error + db 'Immediate offset out of range (-64 to +63)*4, (-256 to +252 in multiples of 4)',0 + .m256_255: + call assembler_error + db 'Immediate offset out of range (-256 to +255)',0 + .m512_504: + call assembler_error + db 'Immediate offset out of range (-64 to +63)*8, (-512 to +504 in multiples of 8)',0 + .m1024_1008: + call assembler_error + db 'Immediate offset out of range (-64 to +63)*16, (-1024 to +1008 in multiples of 16)',0 +ERROR_immediate_value_out_of_range: + .0_1: + call assembler_error + db 'Immediate value out of range (can only be 0 or 1)',0 + .0_7: + call assembler_error + db 'Immediate value out of range (0 to 7)',0 + .0_15: + call assembler_error + db 'Immediate value out of range (0 to 15)',0 + .0_16: + call assembler_error + db 'Immediate value out of range (0 to 16)',0 + .0_31: + call assembler_error + db 'Immediate value out of range (0 to 31)',0 + .0_0x7f: + call assembler_error + db 'Immediate value out of range (0 to 0x7f)',0 + .0_0xff: + call assembler_error + db 'Immediate value out of range (0 to 0xff)',0 + .0_0xff_lsl_8: + call assembler_error + db 'Immediate value out of range (0 to 0xff with optional left shift of 8)',0 + .0_0xff_msl: + call assembler_error + db 'Immediate value out of range (0 to 0xff with optional ones shift of 8 or 16 or left shift of 8, 16 or 24)',0 + .0_0xff_lsl_24: + call assembler_error + db 'Immediate value out of range (0 to 0xff with optional left shift of 8, 16 or 24)',0 + .0_0xfff: + call assembler_error + db 'Immediate value out of range (0 to 0xfff)',0 + .0_0xfff_lsl_12: + call assembler_error + db 'Immediate value out of range (0 to 0xfff with optional left shift of 12)',0 + .0_0xffff: + call assembler_error + db 'Immediate value out of range (0 to 0xffff)',0 + .0_0xffff_lsl_16: + call assembler_error + db 'Immediate value out of range (0 to 0xffff with optional left shift of 16)',0 + .0_0xffff_lsl_48: + call assembler_error + db 'Immediate value out of range (0 to 0xffff with optional left shift of 16, 32 or 48)',0 + .1_16: + call assembler_error + db 'Immediate value out of range (1 to 16)',0 + .1_32: + call assembler_error + db 'Immediate value out of range (1 to 32)',0 + .1_64: + call assembler_error + db 'Immediate value out of range (1 to 64)',0 + .m64_63: + call assembler_error + db 'Immediate value out of range (-64 to 63)',0 + .quarter: + call assembler_error + db 'Immediate value out of range (-31.0 to +31.0)',0 +ERROR_byte_value_out_of_range: + call assembler_error + db 'Byte value out of range (0 to 0xff)',0 +ERROR_rotation_value_out_of_range: + call assembler_error + db 'Rotation value out of range (0 to 0xf)*2',0 +ERROR_byte_rotation_in_thumb: + call assembler_error + db 'Explicit byte and rotation values not valid in THUMB mode',0 +ERROR_count_value_out_of_range: + .1_4: + call assembler_error + db 'Count value out of range (1 to 4)',0 +ERROR_lsb_out_of_range: + .0_31: + call assembler_error + db 'LSB value out of range (0 to 31)',0 + .0_63: + call assembler_error + db 'LSB value out of range (0 to 63)',0 +ERROR_immr_out_of_range: + .0_31: + call assembler_error + db 'IMMR value out of range (0 to 31)',0 + .0_63: + call assembler_error + db 'IMMR value out of range (0 to 63)',0 +ERROR_imms_out_of_range: + .0_31: + call assembler_error + db 'IMMS value out of range (0 to 31)',0 + .0_63: + call assembler_error + db 'IMMS value out of range (0 to 63)',0 +ERROR_bit_out_of_range: + .0_31: + call assembler_error + db 'Bit number out of range (0 to 31)',0 + .0_63: + call assembler_error + db 'Bit number out of range (0 to 63)',0 +ERROR_width_out_of_range: + call assembler_error + db 'Width field + LSB cannot exceed 32',0 + .64: + call assembler_error + db 'Width field + LSB cannot exceed 64',0 + .1_32: + call assembler_error + db 'Width value out of range (1 to 32)',0 + .1_64: + call assembler_error + db 'Width value out of range (1 to 64)',0 +ERROR_constant_cannot_be_encoded: + call assembler_error + db 'Constant cannot be encoded (0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 or 10.0 only)',0 +ERROR_immediate_cannot_be_encoded: + call assembler_error + db 'Immediate value cannot be encoded',0 +ERROR_must_have_writeback_operator: + call assembler_error + db 'Must have writeback operator "!"',0 +ERROR_option_out_of_range: + call assembler_error + db 'Option out of range (0x00-0xff)',0 +ERROR_opcode4_out_of_range: + call assembler_error + db 'Coprocessor opcode out of range (0-15) in second parameter',0 +ERROR_opcode3_out_of_range: + call assembler_error + db 'Coprocessor opcode out of range (0-7) in sixth parameter',0 +ERROR_expecting_curly_bracket_close: + call assembler_error + db 'Expecting curly bracket "}"',0 +ERROR_expecting_square_bracket_close: + call assembler_error + db 'Expecting square bracket "]"',0 +ERROR_repeated_register_in_list: + call assembler_error + db 'Repeated register in list',0 +ERROR_instruction_not_16bit: + call assembler_error + db 'Instruction not encodable in THUMB',0 +ERROR_instruction_not_t2ee: + call assembler_error + db 'Instruction not encodable in THUMBEE',0 +ERROR_instruction_needs_t2ee: + call assembler_error + db 'Instruction requires THUMBEE mode, use "THUMBEE" to select',0 +ERROR_instruction_not_32bit: + call assembler_error + db 'Instruction not encodable in ARM',0 +ERROR_instruction_not_64bit: + call assembler_error + db 'Instruction not encodable in ARM64',0 +ERROR_register_out_of_range: + .r0_r7: + call assembler_error + db 'Register out of range (R0-R7)',0 + .r0_r7_sp_pc: + call assembler_error + db 'Register out of range (R0-R7, SP or PC)',0 + .must_be_sp: + call assembler_error + db 'Register must be SP',0 + .sp: + call assembler_error + db 'Register cannot be SP',0 + .pc: + call assembler_error + db 'Register cannot be PC',0 + .sp_pc: + call assembler_error + db 'Register cannot be SP or PC',0 + .too_complex: + call assembler_error + db 'Expression can only have one register with no scaling',0 + .only_base: + call assembler_error + db 'Expression can only have an unaligned register (R0-R15)',0 + .only_base64: + call assembler_error + db 'Expression can only have 64-bit register (X0-X30,SP)',0 +ERROR_dest_cannot_be_sp_pc: + call assembler_error + db 'Destination register cannot be SP or PC',0 +ERROR_offset_register_cannot_be_sp_pc: + call assembler_error + db 'Offset register cannot be SP or PC',0 +ERROR_dest_and_source_must_be_the_same: + call assembler_error + db 'Destination register and first source register must be the same',0 +ERROR_r14_not_valid: + .first: + call assembler_error + db 'LR (R14) not valid as first parameter',0 + .second: + call assembler_error + db 'LR (R14) not valid as second parameter',0 +ERROR_r13_not_valid: + call assembler_error + db 'SP (R13) not valid',0 + .second: + call assembler_error + db 'SP (R13) not valid as second parameter',0 +ERROR_r13_r15_not_valid: + call assembler_error + db 'SP (R13) and PC (R15) not valid',0 + .third: + call assembler_error + db 'SP (R13) and PC (R15) not valid as third parameter',0 +ERROR_r15_not_valid: + call assembler_error + db 'PC (R15) not valid',0 + .all: + call assembler_error + db 'PC (R15) not valid for any parameter',0 + .first: + call assembler_error + db 'PC (R15) not valid as first parameter',0 + .second: + call assembler_error + db 'PC (R15) not valid as second parameter',0 + .third: + call assembler_error + db 'PC (R15) not valid as third parameter',0 + .fourth: + call assembler_error + db 'PC (R15) not valid as fourth parameter',0 + .base: + call assembler_error + db 'PC (R15) not valid as base register',0 + .post: + call assembler_error + db 'PC (R15) not valid as base register with post update',0 +ERROR_register_writeback_not_allowed: + call assembler_error + db 'Register writeback not allowed here',0 +ERROR_destination_register_not_allowed_in_list: + call assembler_error + db 'Destination register with writeback not allowed in source list',0 +ERROR_source_and_dest_must_differ: + call assembler_error + db 'Source and destination registers must differ',0 +ERROR_base_and_dest_must_differ_with_writeback: + call assembler_error + db 'Base and destination registers must differ when using writeback',0 +ERROR_offset_and_dest_must_differ_with_LDRD: + call assembler_error + db 'Offset and destination registers must differ with LDRD',0 +ERROR_source_register_must_be_even: + call assembler_error + db 'First source register must be even',0 +ERROR_destination_register_must_be_even: + call assembler_error + db 'First destination register must be even',0 +ERROR_source_registers_must_be_consecutive: + call assembler_error + db 'Source registers must be consecutive',0 +ERROR_destination_registers_must_be_consecutive: + call assembler_error + db 'Destination registers must be consecutive',0 +ERROR_source_rm_and_dest_must_differ: + call assembler_error + db 'Destination and first source must differ',0 +ERROR_base_and_offset_must_differ_with_writeback: + call assembler_error + db 'Base and offset registers must differ when using writeback',0 +ERROR_must_use_full_psr: + call assembler_error + db 'Must use full PSR here, either APSR, CPSR or SPSR',0 +ERROR_must_specify_psr_bit_fields: + call assembler_error + db 'Must specify PSR bit fields here, (APSR_nzcvqg, CPSR_fsxc or SPSR_fsxc)',0 +ERROR_memory_address_cannot_be_source_or_dest: + call assembler_error + db 'Address register cannot be source or destination',0 +ERROR_dest_cannot_be_source_or_memory_address: + call assembler_error + db 'Destination cannot be source or address register',0 +ERROR_destination_registers_must_differ: + call assembler_error + db 'Destination registers must differ',0 +ERROR_empty_set: + call assembler_error + db 'Cannot use empty set',0 +ERROR_sp_in_set: + call assembler_error + db 'SP (R13) not valid in register list',0 +ERROR_pc_in_set: + call assembler_error + db 'PC (R15) not valid in register list',0 +ERROR_invalid_set_with_lr_pc: + call assembler_error + db 'Cannot have LR (R14) and PC (R15) both in the list',0 +ERROR_shift_type_must_be_LSL: + call assembler_error + db 'Shift type must be LSL',0 +ERROR_shift_type_must_be_LSL_or_ASR: + call assembler_error + db 'Shift type must be LSL or ASR',0 +ERROR_shift_type_must_be_ASR: + call assembler_error + db 'Shift type must be ASR',0 +ERROR_shift_type_must_be_ROR: + call assembler_error + db 'Shift type must be ROR',0 +ERROR_extend_type: + call assembler_error + db 'Extend type must be UXTW, UXTX, SXTW, SXTX or LSL',0 +ERROR_requires_cpu_capability_arm_26bit: + call assembler_error + db 'Requires CPU capability 26BIT, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v1: + call assembler_error + db 'Requires CPU capability V1, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v2: + call assembler_error + db 'Requires CPU capability V2, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v2a: + call assembler_error + db 'Requires CPU capability A, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v3: + call assembler_error + db 'Requires CPU capability V3, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_m: + call assembler_error + db 'Requires CPU capability M, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v4: + call assembler_error + db 'Requires CPU capability V4, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v4t: + call assembler_error + db 'Requires CPU capability V4T, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v5: + call assembler_error + db 'Requires CPU capability V5, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v5t: + call assembler_error + db 'Requires CPU capability V5T, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_p: + call assembler_error + db 'Requires CPU capability P, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_e: + call assembler_error + db 'Requires CPU capability E, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_j: + call assembler_error + db 'Requires CPU capability J, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_x: + call assembler_error + db 'Requires CPU capability X, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v6: + call assembler_error + db 'Requires CPU capability V6, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v6t: + call assembler_error + db 'Requires CPU capability V6T, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_align: + call assembler_error + db 'Requires CPU capability ALIGN, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_k: + call assembler_error + db 'Requires CPU capability K, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_z: + call assembler_error + db 'Requires CPU capability Z, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_6m: + call assembler_error + db 'Requires CPU capability 6M, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_7m: + call assembler_error + db 'Requires CPU capability 7M, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_t2: + call assembler_error + db 'Requires CPU capability T2, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v7: + call assembler_error + db 'Requires CPU capability V7, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_sync: + call assembler_error + db 'Requires CPU capability SYNC, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_div: + call assembler_error + db 'Requires CPU capability DIV, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_t2ee: + call assembler_error + db 'Requires CPU capability T2EE, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_mp: + call assembler_error + db 'Requires CPU capability MP, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_ve: + call assembler_error + db 'Requires CPU capability VE, use directive "processor" to select',0 +ERROR_requires_cpu_capability_crc: + call assembler_error + db 'Requires CPU capability CRC, use directive "processor" to select',0 +ERROR_requires_cpu_capability_arm_v8: + call assembler_error + db 'Requires CPU capability V8, use directive "processor" to select',0 +ERROR_requires_cpu64_capability_v8: + call assembler_error + db 'Requires CPU64 capability V8, use directive "processor" to select',0 +ERROR_requires_cpu64_capability_FP: + call assembler_error + db 'Requires CPU64 capability FP, use directive "processor" to select',0 +ERROR_requires_cpu64_capability_SIMD: + call assembler_error + db 'Requires CPU64 capability SIMD, use directive "processor" to select',0 +ERROR_requires_cpu64_capability_crc: + call assembler_error + db 'Requires CPU64 capability CRC, use directive "processor" to select',0 +ERROR_requires_cpu64_capability_crypto: + call assembler_error + db 'Requires CPU64 capability CRYPTO, use directive "processor" to select',0 +ERROR_requires_copro_capability_fpa_v1: + call assembler_error + db 'Requires coprocessor capability FPA V1, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_fpa_v2: + call assembler_error + db 'Requires coprocessor capability FPA V2, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_v1xd: + call assembler_error + db 'Requires coprocessor capability VFP V1xD, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_v1: + call assembler_error + db 'Requires coprocessor capability VFP V1, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_v2: + call assembler_error + db 'Requires coprocessor capability VFP V2, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_v3: + call assembler_error + db 'Requires coprocessor capability VFP V3, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_v4: + call assembler_error + db 'Requires coprocessor capability VFP V4, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_d32: + call assembler_error + db 'Requires coprocessor capability VFP D32, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_vfp_hp: + call assembler_error + db 'Requires coprocessor capability VFP HP, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_xscale: + call assembler_error + db 'Requires coprocessor capability XSCALE, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_iwmmxt_v1: + call assembler_error + db 'Requires coprocessor capability IWMMXT V1, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_iwmmxt_v2: + call assembler_error + db 'Requires coprocessor capability IWMMXT V2, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_maverick: + call assembler_error + db 'Requires coprocessor capability MAVERICK, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_int: + call assembler_error + db 'Requires coprocessor capability SIMD INT, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_float: + call assembler_error + db 'Requires coprocessor capability SIMD FLOAT, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_hp: + call assembler_error + db 'Requires coprocessor capability SIMD HP, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_v2: + call assembler_error + db 'Requires coprocessor capability SIMD V2, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_v8: + call assembler_error + db 'Requires coprocessor capability SIMD V8, use directive "coprocessor" to select',0 +ERROR_requires_copro_capability_simd_crypto: + call assembler_error + db 'Requires coprocessor capability SIMD CRYPTO, use directive "coprocessor" to select',0 +ERROR_narrow_instructions_are_not_encodable_in_arm_mode: + call assembler_error + db 'Narrow instructions are not encodable in ARM mode',0 +ERROR_unexpected_end_of_line: + call assembler_error + db 'Unexpected end of line',0 +ERROR_parameter_n_not_valid: + .all: + call assembler_error + db 'Parameter is invalid',0 + .first: + call assembler_error + db 'First parameter is invalid',0 + .second: + call assembler_error + db 'Second parameter is invalid',0 + .third: + call assembler_error + db 'Third parameter is invalid',0 + .fourth: + call assembler_error + db 'Fourth parameter is invalid',0 + .fifth: + call assembler_error + db 'Fifth parameter is invalid',0 + .sixth: + call assembler_error + db 'Sixth parameter is invalid',0 +ERROR_high_base_registers_not_allowed_in_list: + call assembler_error + db 'High registers (R8-R15) not allowed in list',0 + .not_pc: + call assembler_error + db 'High registers (R8-R14) not allowed in list',0 + .not_lr: + call assembler_error + db 'High registers (R8-R13,R15) not allowed in list',0 +ERROR_instruction_not_conditional: + call assembler_error + db 'Instruction cannot be conditional',0 +ERROR_non_contiguous_set: + call assembler_error + db 'Register set must be contiguous',0 +ERROR_large_set: + call assembler_error + db 'Register set cannot contain more than 16 registers',0 +ERROR_two_registers_required: + call assembler_error + db 'Register list must have two consecutive registers',0 +ERROR_must_be_r15: + .first: + call assembler_error + db 'First parameter must be PC {R15}',0 +ERROR_control_register_only_valid_with_word: + call assembler_error + db 'Control register only valid with word size operations',0 +ERROR_condition_does_not_match_IT_specifier: + call assembler_error + db 'Condition does not match IT specifier',0 +ERROR_instruction_must_be_last_in_IT_block: + call assembler_error + db 'Instruction must be last in IT block',0 +ERROR_al_has_no_inverse: + call assembler_error + db 'No "else" condition available with AL',0 +ERROR_label_inside_IT_block: + call assembler_error + db 'Cannot access labels inside of an IT block',0 +ERROR_mode_change_inside_IT_block: + call assembler_error + db 'Cannot change CPU mode inside of an IT block',0 +ERROR_register_list_invalid: + call assembler_error + db 'The register list cannot be encoded',0 +ERROR_alignment_invalid: + call assembler_error + db 'The alignment cannot be encoded',0 +ERROR_use_fldr_for_single_reg: + call assembler_error + db 'Use VLDR or FLDR to load single 64 bit registers',0 +ERROR_element_value_out_of_range: + .0_1: + call assembler_error + db 'Element value out of range (0 to 1)',0 + .0_3: + call assembler_error + db 'Element value out of range (0 to 3)',0 + .0_7: + call assembler_error + db 'Element value out of range (0 to 7)',0 +ERROR_scalar_register_out_of_range: + .0_7: + call assembler_error + db 'Scalar register out of range (d0 to d7)',0 + .0_15: + call assembler_error + db 'Scalar register out of range (d0 to d15)',0 +ERROR_reg_size_64_not_encodable: + call assembler_error + db 'Register size of 64 bits is not encodable',0 +ERROR_zr_not_valid: + .second: + call assembler_error + db 'Second parameter cannot be the zero register (WZR or XZR)',0 +ERROR_condition_value_out_of_range: + .0_15: + call assembler_error + db 'Condition value out of range (0 to 15)',0 +ERROR_al_nv_not_valid: + call assembler_error + db 'Conditions AL and NV are not valid',0 +ERROR_cannot_set_flags: + call assembler_error + db 'This instruction cannot set the flags in ARM64 mode',0 +ERROR_vector_register_out_of_range: + call assembler_error + db 'Indexed vector register can be v0 to v15 only',0 +ERROR_branch_misaligned: + call assembler_error + db 'Address is not aligned',0 +ERROR_branch_too_far: + call assembler_error + db 'Address cannot be reached',0 +ERROR_expecting_CPU_selection_symbol: + call assembler_error + db 'Expecting a CPU selection symbol after the PROCESSOR operator',0 +ERROR_expecting_COPRO_selection_symbol: + call assembler_error + db 'Expecting a COPRO selection symbol after the COPROCESSOR operator',0 diff --git a/source/ide/fasmw/fasmarm.inc b/source/ide/fasmw/fasmarm.inc new file mode 100644 index 0000000..aa1f919 --- /dev/null +++ b/source/ide/fasmw/fasmarm.inc @@ -0,0 +1,465 @@ + +; flat assembler interface for Win32 IDE +; Copyright (c) 1999-2016, Tomasz Grysztar. +; All rights reserved. + +flat_assembler: + + mov [initial_definitions],0 + mov edx,[esp+4] + mov [input_file],edx + invoke GetFullPathName,edx,1000h,path_buffer,param_buffer + mov edi,[param_buffer] + mov byte [edi-1],0 + mov [symbols_file],0 + test [command_flags],2 + jz symbols_file_name_ok + mov [symbols_file],edi + mov ecx,eax + add ecx,path_buffer + sub ecx,edi + lea edi,[edi+ecx-1] + mov ebx,edi + mov al,'.' + std + repne scasb + cld + je attach_fas_extension + mov edi,ebx + attach_fas_extension: + inc edi + mov eax,'.fas' + stosd + xor al,al + stosb + symbols_file_name_ok: + invoke SetCurrentDirectory,path_buffer + mov [hfile],0 + invoke GlobalAlloc,GMEM_MOVEABLE,1 + mov [hmem_display],eax + invoke GlobalLock,[hmem_display] + mov byte [eax],0 + invoke GlobalUnlock,[hmem_display] + mov [display_size],1 + mov [error_data_size],0 + mov [allocated_memory],0 + mov eax,[compiler_memory] + shl eax,10 + jz out_of_memory + allocate_memory: + mov edx,eax + shr edx,2 + mov ecx,eax + sub ecx,edx + mov [memory_end],ecx + mov [additional_memory_end],edx + invoke VirtualAlloc,0,eax,MEM_COMMIT,PAGE_READWRITE + or eax,eax + jnz memory_allocated + mov eax,[additional_memory_end] + shl eax,1 + cmp eax,4000h + jb out_of_memory + jmp allocate_memory + memory_allocated: + mov [allocated_memory],eax + mov [memory_start],eax + mov [code_start],eax + add eax,[memory_end] + mov [memory_end],eax + mov [additional_memory],eax + add [additional_memory_end],eax + mov [tagged_blocks],0 + + mov eax,esp + and eax,not 0FFFh + add eax,1000h-10000h + mov [stack_limit],eax + + invoke PostMessage,[hwnd_progress],PBM_SETPOS,0,0 + invoke SetThreadPriority,[hthread],[compiler_priority] + invoke GetTickCount + mov [start_time],eax + mov [preprocessing_done],0 + call preprocessor + invoke PostMessage,[hwnd_progress],PBM_SETPOS,1,0 + or [preprocessing_done],-1 + call parser + invoke PostMessage,[hwnd_progress],PBM_SETPOS,2,0 + call ARM_label_walker ;this line added for ARM + call assembler + call ARM_close_dwarf ;this line added for ARM + invoke PostMessage,[hwnd_progress],PBM_SETPOS,3,0 + call formatter + invoke PostMessage,[hwnd_progress],PBM_SETPOS,4,0 + call show_display_buffer + invoke GetTickCount + sub eax,[start_time] + mov [total_time],eax + mov esi,[output_file] + mov edi,path_buffer + copy_executable_name: + lodsb + stosb + or al,al + jnz copy_executable_name + xor al,al + +exit_program: + movzx eax,al + push eax + mov eax,[allocated_memory] + or eax,eax + jz memory_ok + invoke VirtualFree,eax,0,MEM_RELEASE + mov [allocated_memory],0 + memory_ok: + mov eax,[hfile] + or eax,eax + jz handle_ok + invoke CloseHandle,eax + handle_ok: + invoke PostMessage,[hwnd_compiler],WM_COMMAND,IDOK,0 + call [ExitThread] + +get_environment_variable: + invoke GetEnvironmentVariable,esi,string_buffer,1000h + mov ecx,[memory_end] + sub ecx,edi + cmp ecx,1000h + jbe get_local_variable + mov ecx,1000h + get_local_variable: + invoke GetPrivateProfileString,_section_environment,esi,string_buffer,edi,ecx,ini_path + add edi,eax + cmp edi,[memory_end] + jae out_of_memory + retn + +open: + mov ebx,edx + invoke WaitForSingleObject,[mutex],-1 + invoke CreateFile,ebx,GENERIC_READ,FILE_SHARE_READ,0,OPEN_EXISTING,0,0 + cmp eax,-1 + je file_error + mov [hfile],eax + mov ebx,eax + clc + retn + file_error: + stc + retn +create: + mov ebx,edx + invoke WaitForSingleObject,[mutex],-1 + invoke CreateFile,ebx,GENERIC_WRITE,0,0,CREATE_ALWAYS,0,0 + cmp eax,-1 + je file_error + mov ebx,eax + clc + retn +write: + invoke WriteFile,ebx,edx,ecx,bytes_count,0 + or eax,eax + jz file_error + clc + retn +read: + mov ebp,ecx + invoke ReadFile,ebx,edx,ecx,bytes_count,0 + or eax,eax + jz file_error + cmp ebp,[bytes_count] + jne file_error + clc + retn +close: + cmp ebx,[hfile] + jne close_handle + mov [hfile],0 + close_handle: + invoke CloseHandle,ebx + invoke ReleaseMutex,[mutex] + retn +lseek: + movzx eax,al + invoke SetFilePointer,ebx,edx,0,eax + cmp eax,-1 + je file_error + retn + +display_block: + push edi + push ecx + add ecx,[display_size] + invoke GlobalReAlloc,[hmem_display],ecx,GMEM_MOVEABLE + or eax,eax + jz out_of_memory + mov [hmem_display],eax + invoke GlobalLock,[hmem_display] + add eax,[display_size] + lea edi,[eax-1] + pop ecx + add [display_size],ecx + rep movsb + xor al,al + stosb + invoke GlobalUnlock,[hmem_display] + pop edi + retn +fatal_error: + cmp [hthread],0 + je error_outside_compiler + pop [error_message] + error_with_no_source: + mov al,0FFh + jmp exit_program +assembler_error: + cmp [hthread],0 + je error_outside_compiler + call show_display_buffer + pop [error_message] + mov ebx,[current_line] + test ebx,ebx + jz error_with_no_source + xor ecx,ecx + get_error_lines: + mov eax,[ebx] + cmp byte [eax],0 + je get_next_error_line + test byte [ebx+7],80h + jz error_lines_ok + inc ecx + mov edx,ebx + find_definition_origin: + mov edx,[edx+12] + test byte [edx+7],80h + jnz find_definition_origin + mov eax,[edx+4] + and eax,7FFFFFFFh + push eax + mov edx,[edx] + push edx + get_next_error_line: + mov ebx,[ebx+8] + jmp get_error_lines + error_lines_ok: + inc ecx + mov eax,[ebx+4] + and eax,7FFFFFFFh + push eax + mov edx,[ebx] + push edx + mov ebx,ecx + inc ecx + shl ecx,3 + mov [error_data_size],ecx + invoke GlobalAlloc,GMEM_MOVEABLE,ecx + mov [hmem_error_data],eax + invoke GlobalLock,[hmem_error_data] + mov [eax],ebx + invoke GlobalUnlock,[hmem_error_data] + xor ebx,ebx + store_error_lines: + pop edx + invoke GetFullPathName,edx,1000h,path_buffer,param_buffer + inc eax + mov esi,eax + add eax,[error_data_size] + invoke GlobalReAlloc,[hmem_error_data],eax,GMEM_MOVEABLE + invoke GlobalLock,[hmem_error_data] + mov edi,eax + add edi,[error_data_size] + mov ecx,esi + mov esi,path_buffer + rep movsb + pop edx + mov [eax+8+ebx*8+4],edx + sub edi,eax + xchg [error_data_size],edi + mov [eax+8+ebx*8],edi + mov esi,[eax] + invoke GlobalUnlock,[hmem_error_data] + inc ebx + cmp ebx,esi + jb store_error_lines + mov edi,[additional_memory] + cmp [preprocessing_done],0 + jne error_in_preprocessed + xor al,al + stosb + jmp instruction_converted + error_in_preprocessed: + mov esi,[current_line] + add esi,16 + xor dl,dl + convert_instruction: + lodsb + cmp al,1Ah + je copy_symbol + cmp al,22h + je copy_symbol + cmp al,3Bh + je ignore_preprocessor_symbols + stosb + or al,al + jz instruction_converted + xor dl,dl + jmp convert_instruction + copy_symbol: + or dl,dl + jz space_ok + mov byte [edi],20h + inc edi + space_ok: + cmp al,22h + je quoted + lodsb + movzx ecx,al + rep movsb + or dl,-1 + jmp convert_instruction + quoted: + mov al,27h + stosb + lodsd + mov ecx,eax + jecxz quoted_copied + copy_quoted: + lodsb + stosb + cmp al,27h + jne quote_ok + stosb + quote_ok: + loop copy_quoted + quoted_copied: + mov al,27h + stosb + or dl,-1 + jmp convert_instruction + ignore_preprocessor_symbols: + xor al,al + stosb + instruction_converted: + sub edi,[additional_memory] + mov ebx,[error_data_size] + lea eax,[ebx+edi] + invoke GlobalReAlloc,[hmem_error_data],eax,GMEM_MOVEABLE + invoke GlobalLock,[hmem_error_data] + mov ecx,edi + mov [eax+4],ebx + lea edi,[eax+ebx] + mov esi,[additional_memory] + rep movsb + invoke GlobalUnlock,[hmem_error_data] + mov al,2 + jmp exit_program + error_outside_compiler: + mov esp,[resume_esp] + jmp [resume_eip] + +make_timestamp: + invoke GetSystemTime,systime + movzx ecx,[systime.wYear] + mov eax,ecx + sub eax,1970 + mov ebx,365 + mul ebx + mov ebp,eax + mov eax,ecx + sub eax,1969 + shr eax,2 + add ebp,eax + mov eax,ecx + sub eax,1901 + mov ebx,100 + div ebx + sub ebp,eax + mov eax,ecx + xor edx,edx + sub eax,1601 + mov ebx,400 + div ebx + add ebp,eax + movzx ecx,[systime.wMonth] + mov eax,ecx + dec eax + mov ebx,30 + mul ebx + add ebp,eax + cmp ecx,8 + jbe months_correction + mov eax,ecx + sub eax,7 + shr eax,1 + add ebp,eax + mov ecx,8 + months_correction: + mov eax,ecx + shr eax,1 + add ebp,eax + cmp ecx,2 + jbe day_correction_ok + sub ebp,2 + movzx ecx,word [systime.wYear] + test ecx,11b + jnz day_correction_ok + xor edx,edx + mov eax,ecx + mov ebx,100 + div ebx + or edx,edx + jnz day_correction + mov eax,ecx + mov ebx,400 + div ebx + or edx,edx + jnz day_correction_ok + day_correction: + inc ebp + day_correction_ok: + movzx eax,[systime.wDay] + dec eax + add eax,ebp + mov ebx,24 + mul ebx + movzx ecx,[systime.wHour] + add eax,ecx + mov ebx,60 + mul ebx + movzx ecx,[systime.wMinute] + add eax,ecx + mov ebx,60 + mul ebx + movzx ecx,[systime.wSecond] + add eax,ecx + adc edx,0 + retn + +include '..\..\errors.inc' +include '..\..\symbdump.inc' +include '..\..\preproce.inc' +include '..\..\parser.inc' +include '..\..\exprpars.inc' +include '..\..\exprcalc.inc' +include '..\..\assemble.inc' +include '..\..\formats.inc' +include '..\..\armv8.inc' + +include '..\..\armtable.inc' +include '..\..\messages.inc' + +_logo db 'flat assembler for ARM version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0 + +section '.bss' readable writeable + +include '..\..\variable.inc' + +allocated_memory dd ? +start_time dd ? +total_time dd ? +display_size dd ? +error_message dd ? +error_data_size dd ? +preprocessing_done db ? diff --git a/source/ide/fasmw/make_arm.bat b/source/ide/fasmw/make_arm.bat new file mode 100644 index 0000000..a8ff189 --- /dev/null +++ b/source/ide/fasmw/make_arm.bat @@ -0,0 +1,6 @@ +@echo off +ren FASM.INC FASMx86.INC +ren FASMARM.INC FASM.INC +..\..\..\fasm fasmw.asm ..\..\..\FASMWARM.EXE +ren FASM.INC FASMARM.INC +ren FASMx86.INC FASM.INC diff --git a/source/libc/fasmarm.asm b/source/libc/fasmarm.asm new file mode 100644 index 0000000..ec83dd1 --- /dev/null +++ b/source/libc/fasmarm.asm @@ -0,0 +1,356 @@ + +; flat assembler interface for Unix/libc +; Copyright (c) 1999-2016, Tomasz Grysztar. +; All rights reserved. + + format ELF + public main + +macro ccall proc,[arg] + { common + local size + size = 0 + mov ebp,esp + if ~ arg eq + forward + size = size + 4 + common + sub esp,size + end if + and esp,-16 + if ~ arg eq + add esp,size + reverse + pushd arg + common + end if + call proc + mov esp,ebp } + +extrn gettimeofday + +section '.text' executable align 16 + +main: + mov ecx,[esp+4] + mov [argc],ecx + mov ebx,[esp+8] + mov [argv],ebx + push ebp + mov [stack_frame],esp + + mov [con_handle],1 + mov esi,_logo + call display_string + + call get_params + jc information + + call init_memory + + mov esi,_memory_prefix + call display_string + mov eax,[memory_end] + sub eax,[memory_start] + add eax,[additional_memory_end] + sub eax,[additional_memory] + shr eax,10 + call display_number + mov esi,_memory_suffix + call display_string + + ccall gettimeofday,buffer,0 + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + mov [start_time],eax + + and [preprocessing_done],0 + call preprocessor + or [preprocessing_done],-1 + call parser + call ARM_label_walker ;this line added for ARM + call assembler + call ARM_close_dwarf ;this line added for ARM + call formatter + + call display_user_messages + movzx eax,[current_pass] + inc eax + call display_number + mov esi,_passes_suffix + call display_string + ccall gettimeofday,buffer,0 + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + sub eax,[start_time] + jnc time_ok + add eax,3600000 + time_ok: + xor edx,edx + mov ebx,100 + div ebx + or eax,eax + jz display_bytes_count + xor edx,edx + mov ebx,10 + div ebx + push edx + call display_number + mov dl,'.' + call display_character + pop eax + call display_number + mov esi,_seconds_suffix + call display_string + display_bytes_count: + mov eax,[written_size] + call display_number + mov esi,_bytes_suffix + call display_string + xor al,al + jmp exit_program + +information: + mov esi,_usage + call display_string + mov al,1 + jmp exit_program + +get_params: + mov [input_file],0 + mov [output_file],0 + mov [symbols_file],0 + mov [memory_setting],0 + mov [passes_limit],100 + + mov ecx,[argc] + mov ebx,[argv] + add ebx,4 + dec ecx + jz bad_params + mov [definitions_pointer],predefinitions + get_param: + mov esi,[ebx] + mov al,[esi] + cmp al,'-' + je option_param + cmp [input_file],0 + jne get_output_file + mov [input_file],esi + jmp next_param + get_output_file: + cmp [output_file],0 + jne bad_params + mov [output_file],esi + jmp next_param + option_param: + inc esi + lodsb + cmp al,'m' + je memory_option + cmp al,'M' + je memory_option + cmp al,'p' + je passes_option + cmp al,'P' + je passes_option + cmp al,'d' + je definition_option + cmp al,'D' + je definition_option + cmp al,'s' + je symbols_option + cmp al,'S' + je symbols_option + bad_params: + stc + ret + memory_option: + cmp byte [esi],0 + jne get_memory_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_memory_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,1 shl (32-10) + jae bad_params + mov [memory_setting],edx + jmp next_param + passes_option: + cmp byte [esi],0 + jne get_passes_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_passes_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,10000h + ja bad_params + mov [passes_limit],dx + next_param: + add ebx,4 + dec ecx + jnz get_param + cmp [input_file],0 + je bad_params + mov eax,[definitions_pointer] + mov byte [eax],0 + mov [initial_definitions],predefinitions + clc + ret + definition_option: + cmp byte [esi],0 + jne get_definition + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_definition: + push edi + mov edi,[definitions_pointer] + call convert_definition_option + mov [definitions_pointer],edi + pop edi + jc bad_params + jmp next_param + symbols_option: + cmp byte [esi],0 + jne get_symbols_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_symbols_setting: + mov [symbols_file],esi + jmp next_param + get_option_value: + xor eax,eax + mov edx,eax + get_option_digit: + lodsb + cmp al,20h + je option_value_ok + cmp al,0Dh + je option_value_ok + or al,al + jz option_value_ok + sub al,30h + jc invalid_option_value + cmp al,9 + ja invalid_option_value + imul edx,10 + jo invalid_option_value + add edx,eax + jc invalid_option_value + jmp get_option_digit + option_value_ok: + dec esi + clc + ret + invalid_option_value: + stc + ret + convert_definition_option: + mov edx,edi + xor al,al + stosb + copy_definition_name: + lodsb + cmp al,'=' + je copy_definition_value + cmp al,20h + je bad_definition_option + or al,al + jz bad_definition_option + stosb + inc byte [edx] + jnz copy_definition_name + bad_definition_option: + stc + ret + copy_definition_value: + lodsb + cmp al,20h + je definition_value_end + or al,al + jz definition_value_end + stosb + jmp copy_definition_value + definition_value_end: + dec esi + xor al,al + stosb + clc + ret + +include 'system.inc' + +include '..\version.inc' + +include '..\errors.inc' +include '..\symbdump.inc' +include '..\preproce.inc' +include '..\parser.inc' +include '..\exprpars.inc' +include '..\exprcalc.inc' +include '..\assemble.inc' +include '..\formats.inc' +include '..\armv8.inc' + +include '..\armtable.inc' +include '..\messages.inc' + +_copyright db 'Copyright (c) 2005-2023, revolution',0Ah,\ + 'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0 + +_logo db 'flat assembler for ARM version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0 +_usage db 0xA + db 'usage: fasmasm <source> [output]',0xA + db 'optional settings:',0xA + db ' -m <limit> set the limit in kilobytes for the available memory',0Ah + db ' -p <limit> set the maximum allowed number of passes',0Ah + db ' -d <name>=<value> define symbolic variable',0Ah + db ' -s <file> dump symbolic information for debugging',0Ah + db 0 +_memory_prefix db ' (',0 +_memory_suffix db ' kilobytes memory)',0xA,0 +_passes_suffix db ' passes, ',0 +_seconds_suffix db ' seconds, ',0 +_bytes_suffix db ' bytes.',0xA,0 + +section '.bss' writeable align 4 + +include '..\variable.inc' + +argc dd ? +argv dd ? +stack_frame dd ? +memory_setting dd ? +definitions_pointer dd ? +start_time dd ? +timestamp dq ? +con_handle dd ? +displayed_count dd ? +last_displayed db ? +character db ? +preprocessing_done db ? + +predefinitions rb 1000h +buffer rb 1000h diff --git a/source/linux/fasmarm.asm b/source/linux/fasmarm.asm new file mode 100644 index 0000000..78f7992 --- /dev/null +++ b/source/linux/fasmarm.asm @@ -0,0 +1,441 @@ + +; flat assembler interface for Linux +; Copyright (c) 1999-2016, Tomasz Grysztar. +; All rights reserved. + + format ELF executable 3 + entry start + +stdin = 0 +stdout = 1 +stderr = 2 + +segment readable executable + +start: + + mov [con_handle],stdout + mov [command_line],esp + mov ecx,[esp] + lea ebx,[esp+4+ecx*4+4] + mov [environment],ebx + call get_params + pushf + jc show_logo + cmp [con_handle],stdout + jnz logo_done + show_logo: + mov esi,_logo + call display_string + logo_done: + popf + jc information + + call init_memory + + cmp [con_handle],stdout + jnz memory_done + mov esi,_memory_prefix + call display_string + mov eax,[memory_end] + sub eax,[memory_start] + add eax,[additional_memory_end] + sub eax,[additional_memory] + shr eax,10 + call display_number + mov esi,_memory_suffix + call display_string + memory_done: + + mov eax,78 + mov ebx,buffer + xor ecx,ecx + int 0x80 + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + mov [start_time],eax + + and [preprocessing_done],0 + call preprocessor + or [preprocessing_done],-1 + call parser + call ARM_label_walker ;this line added for ARM + call assembler + call ARM_close_dwarf ;this line added for ARM + call formatter + + call display_user_messages + cmp [con_handle],stdout + jnz details_done + movzx eax,[current_pass] + inc eax + call display_number + mov esi,_passes_suffix + call display_string + mov eax,78 + mov ebx,buffer + xor ecx,ecx + int 0x80 + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + sub eax,[start_time] + jnc time_ok + add eax,3600000 + time_ok: + xor edx,edx + mov ebx,100 + div ebx + or eax,eax + jz display_bytes_count + xor edx,edx + mov ebx,10 + div ebx + push edx + call display_number + mov dl,'.' + call display_character + pop eax + call display_number + mov esi,_seconds_suffix + call display_string + display_bytes_count: + mov eax,[written_size] + call display_number + mov esi,_bytes_suffix + call display_string + details_done: + xor al,al + jmp exit_program + +information: + mov esi,_usage + call display_string + mov al,1 + jmp exit_program + +get_params: + mov ebx,[command_line] + mov [input_file],0 + mov [output_file],0 + mov [symbols_file],0 + mov [memory_setting],0 + mov [passes_limit],100 + mov ecx,[ebx] + add ebx,8 + dec ecx + jz bad_params + mov [definitions_pointer],predefinitions + get_param: + mov esi,[ebx] + mov ax,[esi] + cmp ax,'-' + jz stdin_stdout + cmp al,'-' + je option_param + stdin_stdout: + cmp [input_file],0 + jne get_output_file + mov [input_file],esi + jmp next_param + get_output_file: + cmp [output_file],0 + jne bad_params + mov [output_file],esi + jmp next_param + option_param: + inc esi + lodsb + cmp al,'m' + je memory_option + cmp al,'M' + je memory_option + cmp al,'p' + je passes_option + cmp al,'P' + je passes_option + cmp al,'d' + je definition_option + cmp al,'D' + je definition_option + cmp al,'s' + je symbols_option + cmp al,'S' + je symbols_option + bad_params: + stc + ret + memory_option: + cmp byte [esi],0 + jne get_memory_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_memory_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,1 shl (32-10) + jae bad_params + mov [memory_setting],edx + jmp next_param + passes_option: + cmp byte [esi],0 + jne get_passes_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_passes_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,10000h + ja bad_params + mov [passes_limit],dx + next_param: + add ebx,4 + dec ecx + jnz get_param + mov eax,[input_file] + test eax,eax + je bad_params + mov ecx,[output_file] + cmp word[eax],'-' + jnz output_file_okay + test ecx,ecx + jnz check_con_handle + mov [output_file],eax + mov ecx,eax + output_file_okay: + test ecx,ecx + jz con_handle_okay + check_con_handle: + cmp word[ecx],'-' + jnz con_handle_okay + mov [con_handle],stderr + con_handle_okay: + mov eax,[definitions_pointer] + mov byte [eax],0 + mov [initial_definitions],predefinitions + clc + ret + definition_option: + cmp byte [esi],0 + jne get_definition + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_definition: + push edi + mov edi,[definitions_pointer] + call convert_definition_option + mov [definitions_pointer],edi + pop edi + jc bad_params + jmp next_param + symbols_option: + cmp byte [esi],0 + jne get_symbols_setting + dec ecx + jz bad_params + add ebx,4 + mov esi,[ebx] + get_symbols_setting: + mov [symbols_file],esi + jmp next_param + get_option_value: + xor eax,eax + mov edx,eax + get_option_digit: + lodsb + cmp al,20h + je option_value_ok + or al,al + jz option_value_ok + sub al,30h + jc invalid_option_value + cmp al,9 + ja invalid_option_value + imul edx,10 + jo invalid_option_value + add edx,eax + jc invalid_option_value + jmp get_option_digit + option_value_ok: + dec esi + clc + ret + invalid_option_value: + stc + ret + convert_definition_option: + mov edx,edi + cmp edi,predefinitions+1000h + jae bad_definition_option + xor al,al + stosb + copy_definition_name: + lodsb + cmp al,'=' + je copy_definition_value + cmp al,20h + je bad_definition_option + or al,al + jz bad_definition_option + cmp edi,predefinitions+1000h + jae bad_definition_option + stosb + inc byte [edx] + jnz copy_definition_name + bad_definition_option: + stc + ret + copy_definition_value: + lodsb + cmp al,20h + je definition_value_end + or al,al + jz definition_value_end + cmp edi,predefinitions+1000h + jae bad_definition_option + stosb + jmp copy_definition_value + definition_value_end: + dec esi + cmp edi,predefinitions+1000h + jae bad_definition_option + xor al,al + stosb + clc + ret + +open_stdin: + cmp word[edx],'-' + jnz adapt_path + mov ebx,stdin + pop eax ebp edi esi + clc + ret + +open_stdout: + cmp word[edx],'-' + jnz adapt_path + mov ebx,stdout + pop eax edx ebp edi esi + clc + ret + +ARM_preprocess_file: + push [memory_end] + push esi + ;ebx = file handle + ;edi = start of free memory + push edi + mov edx,edi ; destination + keep_reading: + mov ecx,[memory_end] + dec ecx + sub ecx,edx ; memory buffer size + jbe out_of_memory + call read + add edx,eax + test eax,eax + jnz keep_reading + lea esi,[edx-1] + sub edx,edi ; input length + mov ecx,edx + mov edi,[memory_end] + sub edi,2 + mov byte [edi+1],1Ah + std + rep movs byte [edi],[esi] + cld + inc edi + mov [memory_end],edi + mov esi,edi + pop edi + call close + pop edx + xor ecx,ecx + mov ebx,esi + jmp preprocess_source + +include 'system.inc' + +include '..\version.inc' + +include '..\errors.inc' +include '..\symbdump.inc' +include '..\preproce.inc' +include '..\parser.inc' +include '..\exprpars.inc' +include '..\exprcalc.inc' +include '..\assemble.inc' +include '..\formats.inc' +include '..\armv8.inc' + +;patches to enable "-" to read/write using stdin/stdout + +patch open, call adapt_path, call open_stdin, 3 +patch create, call adapt_path, call open_stdout, 4 +patch read, <<cmp eax,ecx>>, <<cmp eax,eax>>, 23 +patch predefinitions_ok, call preprocess_file, call ARM_preprocess_file, 25 +patch copy_preprocessed_path, call preprocess_file, call ARM_preprocess_file, 28 + +;patch to fix bug with lseek error detection + +patch lseek, <<cmp eax,-1>,<je file_error>,<clc>>, <<cmp eax,-4095>,<cmc>>, 13 + +include '..\armtable.inc' +include '..\messages.inc' + +_copyright db 'Copyright (c) 2005-2023, revolution',0Ah,\ + 'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0 + +_logo db 'flat assembler for ARM version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0 +_usage db 0xA + db 'usage: fasmarm <source> [output]',0xA + db 'optional settings:',0xA + db ' -m <limit> set the limit in kilobytes for the available memory',0Ah + db ' -p <limit> set the maximum allowed number of passes',0Ah + db ' -d <name>=<value> define symbolic variable',0Ah + db ' -s <file> dump symbolic information for debugging',0Ah + db 0 +_memory_prefix db ' (',0 +_memory_suffix db ' kilobytes memory)',0xA,0 +_passes_suffix db ' passes, ',0 +_seconds_suffix db ' seconds, ',0 +_bytes_suffix db ' bytes.',0xA,0 + +segment readable writeable + +align 4 + +include '..\variable.inc' + +command_line dd ? +memory_setting dd ? +definitions_pointer dd ? +environment dd ? +timestamp dq ? +start_time dd ? +con_handle dd ? +displayed_count dd ? +last_displayed db ? +character db ? +preprocessing_done db ? + +predefinitions rb 1000h +buffer rb 1000h diff --git a/source/linux/x64/fasmarm.asm b/source/linux/x64/fasmarm.asm new file mode 100644 index 0000000..5dfd274 --- /dev/null +++ b/source/linux/x64/fasmarm.asm @@ -0,0 +1,460 @@ + +; flat assembler interface for Linux x64 +; Copyright (c) 1999-2022, Tomasz Grysztar. +; All rights reserved. + + format ELF64 executable 3 at 400000h + entry start + +stdin = 0 +stdout = 1 +stderr = 2 + + include 'modes.inc' + +segment readable executable + +start: + + mov [con_handle],stdout + + mov [command_line],rsp + mov rcx,[rsp] + lea rbx,[rsp+8+rcx*8+8] + mov [environment],rbx + call get_params + pushf + jc show_logo + cmp [con_handle],stdout + jnz logo_done + show_logo: + mov esi,_logo + call display_string + logo_done: + popf + jc information + call init_memory + + cmp [con_handle],stdout + jnz memory_done + mov esi,_memory_prefix + call display_string + mov eax,[memory_end] + sub eax,[memory_start] + add eax,[additional_memory_end] + sub eax,[additional_memory] + shr eax,10 + call display_number + mov esi,_memory_suffix + call display_string + memory_done: + + mov eax,96 + mov edi,buffer + xor esi,esi + syscall + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + mov [start_time],eax + + and [preprocessing_done],0 + call preprocessor + or [preprocessing_done],-1 + call parser + call ARM_label_walker ;this line added for ARM + call assembler + call ARM_close_dwarf ;this line added for ARM + call formatter + + call display_user_messages + cmp [con_handle],stdout + jnz details_done + movzx eax,[current_pass] + inc eax + call display_number + mov esi,_passes_suffix + call display_string + mov eax,96 + mov edi,buffer + xor esi,esi + syscall + mov eax,dword [buffer] + mov ecx,1000 + mul ecx + mov ebx,eax + mov eax,dword [buffer+4] + div ecx + add eax,ebx + sub eax,[start_time] + jnc time_ok + add eax,3600000 + time_ok: + xor edx,edx + mov ebx,100 + div ebx + or eax,eax + jz display_bytes_count + xor edx,edx + mov ebx,10 + div ebx + push edx + call display_number + mov dl,'.' + call display_character + pop eax + call display_number + mov esi,_seconds_suffix + call display_string + display_bytes_count: + mov eax,[written_size] + call display_number + mov esi,_bytes_suffix + call display_string + details_done: + xor al,al + jmp exit_program + +information: + mov esi,_usage + call display_string + mov al,1 + jmp exit_program + +get_params: + mov rbx,[command_line] + mov [input_file],0 + mov [output_file],0 + mov [symbols_file],0 + mov [memory_setting],0 + mov [passes_limit],100 + mov rcx,[rbx] + add rbx,8*2 + dec rcx + jz bad_params + mov [definitions_pointer],predefinitions + mov [path_pointer],paths + get_param: + mov rsi,[rbx] + mov ax,[rsi] + cmp ax,'-' + jz stdin_stdout + cmp al,'-' + je option_param + stdin_stdout: + cmp [input_file],0 + jne get_output_file + call collect_path + mov [input_file],edx + jmp next_param + get_output_file: + cmp [output_file],0 + jne bad_params + call collect_path + mov [output_file],edx + jmp next_param + option_param: + inc rsi + lodsb + cmp al,'m' + je memory_option + cmp al,'M' + je memory_option + cmp al,'p' + je passes_option + cmp al,'P' + je passes_option + cmp al,'d' + je definition_option + cmp al,'D' + je definition_option + cmp al,'s' + je symbols_option + cmp al,'S' + je symbols_option + bad_params: + stc + ret + memory_option: + cmp byte [rsi],0 + jne get_memory_setting + dec rcx + jz bad_params + add rbx,8 + mov rsi,[rbx] + get_memory_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,1 shl (32-10) + jae bad_params + mov [memory_setting],edx + jmp next_param + passes_option: + cmp byte [rsi],0 + jne get_passes_setting + dec rcx + jz bad_params + add rbx,8 + mov rsi,[rbx] + get_passes_setting: + call get_option_value + or edx,edx + jz bad_params + cmp edx,10000h + ja bad_params + mov [passes_limit],dx + next_param: + add rbx,8 + dec rcx + jnz get_param + mov eax,[input_file] + test eax,eax + je bad_params + mov ecx,[output_file] + cmp word[eax],'-' + jnz output_file_okay + test ecx,ecx + jnz check_con_handle + mov [output_file],eax + mov ecx,eax + output_file_okay: + test ecx,ecx + jz con_handle_okay + check_con_handle: + cmp word[ecx],'-' + jnz con_handle_okay + mov [con_handle],stderr + con_handle_okay: + mov eax,[definitions_pointer] + mov byte [eax],0 + mov [initial_definitions],predefinitions + clc + ret + definition_option: + cmp byte [rsi],0 + jne get_definition + dec rcx + jz bad_params + add rbx,8 + mov rsi,[rbx] + get_definition: + mov r12d,edi + mov edi,[definitions_pointer] + call convert_definition_option + mov [definitions_pointer],edi + mov edi,r12d + jc bad_params + jmp next_param + symbols_option: + cmp byte [rsi],0 + jne get_symbols_setting + dec rcx + jz bad_params + add rbx,8 + mov rsi,[rbx] + get_symbols_setting: + call collect_path + mov [symbols_file],edx + jmp next_param + get_option_value: + xor eax,eax + mov edx,eax + get_option_digit: + lodsb + cmp al,20h + je option_value_ok + or al,al + jz option_value_ok + sub al,30h + jc invalid_option_value + cmp al,9 + ja invalid_option_value + imul edx,10 + jo invalid_option_value + add edx,eax + jc invalid_option_value + jmp get_option_digit + option_value_ok: + dec rsi + clc + ret + invalid_option_value: + stc + ret + convert_definition_option: + mov edx,edi + cmp edi,predefinitions+1000h + jae bad_definition_option + xor al,al + stosb + copy_definition_name: + lodsb + cmp al,'=' + je copy_definition_value + cmp al,20h + je bad_definition_option + or al,al + jz bad_definition_option + cmp edi,predefinitions+1000h + jae bad_definition_option + stosb + inc byte [edx] + jnz copy_definition_name + bad_definition_option: + stc + ret + copy_definition_value: + lodsb + cmp al,20h + je definition_value_end + or al,al + jz definition_value_end + cmp edi,predefinitions+1000h + jae bad_definition_option + stosb + jmp copy_definition_value + definition_value_end: + dec rsi + cmp edi,predefinitions+1000h + jae bad_definition_option + xor al,al + stosb + clc + ret +collect_path: + mov edi,[path_pointer] + mov edx,edi + copy_path_to_low_memory: + lodsb + stosb + test al,al + jnz copy_path_to_low_memory + mov [path_pointer],edi + retn + +open_stdin: + cmp word[edx],'-' + jnz adapt_path + mov ebx,stdin + POP rcx + clc + ret + +open_stdout: + cmp word[edx],'-' + jnz adapt_path + mov ebx,stdout + POP rcx + clc + ret + +ARM_preprocess_file: + push [memory_end] + push esi + ;ebx = file handle + ;edi = start of free memory + push edi + mov edx,edi ; destination + keep_reading: + mov ecx,[memory_end] + dec ecx + sub ecx,edx ; memory buffer size + jbe out_of_memory + call read + add edx,eax + test eax,eax + jnz keep_reading + lea esi,[edx-1] + sub edx,edi ; input length + mov ecx,edx + mov edi,[memory_end] + sub edi,2 + mov byte [edi+1],1Ah + std + rep movs byte [edi],[esi] + cld + inc edi + mov [memory_end],edi + mov esi,edi + pop edi + call close + pop edx + xor ecx,ecx + mov ebx,esi + jmp preprocess_source + +include 'system.inc' + +include '..\..\version.inc' + +include '..\..\errors.inc' +include '..\..\symbdump.inc' +include '..\..\preproce.inc' +include '..\..\parser.inc' +include '..\..\exprpars.inc' +include '..\..\exprcalc.inc' +include '..\..\assemble.inc' +include '..\..\formats.inc' +include '..\..\armv8.inc' + +;patches to enable "-" to read/write using stdin/stdout + +patch open, call adapt_path, call open_stdin, 6 +patch create, call adapt_path, call open_stdout, 9 +patch read, <<cmp eax,ecx>>, <<cmp eax,eax>>, 33 +patch predefinitions_ok, call preprocess_file, call ARM_preprocess_file, 25 +patch copy_preprocessed_path, call preprocess_file, call ARM_preprocess_file, 49 + +;patch to fix bug with lseek error detection + +patch lseek, <<cmp eax,-1>,<je file_error>,<clc>>, <<cmp eax,-4095>,<cmc>>, 27 + +include '..\..\armtable.inc' +include '..\..\messages.inc' + +_copyright db 'Copyright (c) 2005-2023, revolution',0Ah,\ + 'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0 + +_logo db 'flat assembler for ARM version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0 +_usage db 0xA + db 'usage: fasmarm <source> [output]',0xA + db 'optional settings:',0xA + db ' -m <limit> set the limit in kilobytes for the available memory',0xA + db ' -p <limit> set the maximum allowed number of passes',0xA + db ' -d <name>=<value> define symbolic variable',0xA + db ' -s <file> dump symbolic information for debugging',0xA + db 0 +_memory_prefix db ' (',0 +_memory_suffix db ' kilobytes memory, x64)',0xA,0 +_passes_suffix db ' passes, ',0 +_seconds_suffix db ' seconds, ',0 +_bytes_suffix db ' bytes.',0xA,0 +_no_low_memory db 'failed to allocate memory within 32-bit addressing range',0 + +segment readable writeable + +align 4 + +include '..\..\variable.inc' + +command_line dq ? +memory_setting dd ? +path_pointer dd ? +definitions_pointer dd ? +environment dq ? +timestamp dq ? +start_time dd ? +con_handle dd ? +displayed_count dd ? +last_displayed db ? +character db ? +preprocessing_done db ? + +buffer rb 1000h +predefinitions rb 1000h +paths rb 10000h diff --git a/source/win32/fasmarm.asm b/source/win32/fasmarm.asm new file mode 100644 index 0000000..cb42e06 --- /dev/null +++ b/source/win32/fasmarm.asm @@ -0,0 +1,423 @@ + +; flat assembler interface for Win32 +; Copyright (c) 1999-2016, Tomasz Grysztar. +; All rights reserved. + + format PE console large + +section '.text' code readable executable + +start: + + mov [con_handle],STD_OUTPUT_HANDLE + mov esi,_logo + call display_string + + call get_params + jc information + + call init_memory + + mov esi,_memory_prefix + call display_string + mov eax,[memory_end] + sub eax,[memory_start] + add eax,[additional_memory_end] + sub eax,[additional_memory] + shr eax,10 + call display_number + mov esi,_memory_suffix + call display_string + + call [GetTickCount] + mov [start_time],eax + + and [preprocessing_done],0 + call preprocessor + or [preprocessing_done],-1 + call parser + call ARM_label_walker ;this line added for ARM + call assembler + call ARM_close_dwarf ;this line added for ARM + call formatter + + call display_user_messages + movzx eax,[current_pass] + inc eax + call display_number + mov esi,_passes_suffix + call display_string + call [GetTickCount] + sub eax,[start_time] + xor edx,edx + mov ebx,100 + div ebx + or eax,eax + jz display_bytes_count + xor edx,edx + mov ebx,10 + div ebx + push edx + call display_number + mov dl,'.' + call display_character + pop eax + call display_number + mov esi,_seconds_suffix + call display_string + display_bytes_count: + mov eax,[written_size] + call display_number + mov esi,_bytes_suffix + call display_string + xor al,al + jmp exit_program + +information: + mov esi,_usage + call display_string + mov al,1 + jmp exit_program + +get_params: + mov [input_file],0 + mov [output_file],0 + mov [symbols_file],0 + mov [memory_setting],0 + mov [passes_limit],100 + call [GetCommandLine] + mov [definitions_pointer],predefinitions + mov esi,eax + mov edi,params + find_command_start: + lodsb + cmp al,20h + je find_command_start + cmp al,22h + je skip_quoted_name + skip_name: + lodsb + cmp al,20h + je find_param + or al,al + jz all_params + jmp skip_name + skip_quoted_name: + lodsb + cmp al,22h + je find_param + or al,al + jz all_params + jmp skip_quoted_name + find_param: + lodsb + cmp al,20h + je find_param + cmp al,'-' + je option_param + cmp al,0Dh + je all_params + or al,al + jz all_params + cmp [input_file],0 + jne get_output_file + mov [input_file],edi + jmp process_param + get_output_file: + cmp [output_file],0 + jne bad_params + mov [output_file],edi + process_param: + cmp al,22h + je string_param + copy_param: + stosb + lodsb + cmp al,20h + je param_end + cmp al,0Dh + je param_end + or al,al + jz param_end + jmp copy_param + string_param: + lodsb + cmp al,22h + je string_param_end + cmp al,0Dh + je param_end + or al,al + jz param_end + stosb + jmp string_param + option_param: + lodsb + cmp al,'m' + je memory_option + cmp al,'M' + je memory_option + cmp al,'p' + je passes_option + cmp al,'P' + je passes_option + cmp al,'d' + je definition_option + cmp al,'D' + je definition_option + cmp al,'s' + je symbols_option + cmp al,'S' + je symbols_option + bad_params: + stc + ret + get_option_value: + xor eax,eax + mov edx,eax + get_option_digit: + lodsb + cmp al,20h + je option_value_ok + cmp al,0Dh + je option_value_ok + or al,al + jz option_value_ok + sub al,30h + jc invalid_option_value + cmp al,9 + ja invalid_option_value + imul edx,10 + jo invalid_option_value + add edx,eax + jc invalid_option_value + jmp get_option_digit + option_value_ok: + dec esi + clc + ret + invalid_option_value: + stc + ret + memory_option: + lodsb + cmp al,20h + je memory_option + cmp al,0Dh + je bad_params + or al,al + jz bad_params + dec esi + call get_option_value + or edx,edx + jz bad_params + cmp edx,1 shl (32-10) + jae bad_params + mov [memory_setting],edx + jmp find_param + passes_option: + lodsb + cmp al,20h + je passes_option + cmp al,0Dh + je bad_params + or al,al + jz bad_params + dec esi + call get_option_value + or edx,edx + jz bad_params + cmp edx,10000h + ja bad_params + mov [passes_limit],dx + jmp find_param + definition_option: + lodsb + cmp al,20h + je definition_option + cmp al,0Dh + je bad_params + or al,al + jz bad_params + dec esi + push edi + mov edi,[definitions_pointer] + call convert_definition_option + mov [definitions_pointer],edi + pop edi + jc bad_params + jmp find_param + symbols_option: + mov [symbols_file],edi + find_symbols_file_name: + lodsb + cmp al,20h + jne process_param + jmp find_symbols_file_name + param_end: + dec esi + string_param_end: + xor al,al + stosb + jmp find_param + all_params: + cmp [input_file],0 + je bad_params + mov eax,[definitions_pointer] + mov byte [eax],0 + mov [initial_definitions],predefinitions + clc + ret + convert_definition_option: + mov ecx,edi + xor al,al + stosb + copy_definition_name: + lodsb + cmp al,'=' + je copy_definition_value + cmp al,20h + je bad_definition_option + cmp al,0Dh + je bad_definition_option + or al,al + jz bad_definition_option + stosb + inc byte [ecx] + jnz copy_definition_name + bad_definition_option: + stc + ret + copy_definition_value: + lodsb + cmp al,20h + je definition_value_end + cmp al,0Dh + je definition_value_end + or al,al + jz definition_value_end + cmp al,'\' + jne definition_value_character + cmp byte [esi],20h + jne definition_value_character + lodsb + definition_value_character: + stosb + jmp copy_definition_value + definition_value_end: + dec esi + xor al,al + stosb + clc + ret + +include '..\version.inc' +include 'systemarm.inc' + +include '..\errors.inc' +include '..\symbdump.inc' +include '..\preproce.inc' +include '..\parser.inc' +include '..\exprpars.inc' +include '..\exprcalc.inc' +include '..\assemble.inc' +include '..\formats.inc' +include '..\armv8.inc' + +include '..\armtable.inc' +include '..\messages.inc' + +section '.data' data readable writeable + +_copyright db 'Copyright (c) 2005-2023, revolution',0Dh,0Ah,\ + 'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Dh,0Ah,0 + +_logo db 'flat assembler for ARM version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0 +_usage db 0Dh,0Ah + db 'usage: fasmarm <source> [output]',0Dh,0Ah + db 'optional settings:',0Dh,0Ah + db ' -m <limit> set the limit in kilobytes for the available memory',0Dh,0Ah + db ' -p <limit> set the maximum allowed number of passes',0Dh,0Ah + db ' -d <name>=<value> define symbolic variable',0Dh,0Ah + db ' -s <file> dump symbolic information for debugging',0Dh,0Ah + db 0 +_memory_prefix db ' (',0 +_memory_suffix db ' kilobytes memory)',0Dh,0Ah,0 +_passes_suffix db ' passes, ',0 +_seconds_suffix db ' seconds, ',0 +_bytes_suffix db ' bytes.',0Dh,0Ah,0 + +align 4 + +include '..\variable.inc' + +con_handle dd ? +memory_setting dd ? +start_time dd ? +definitions_pointer dd ? +bytes_count dd ? +displayed_count dd ? +character db ? +last_displayed rb 2 +preprocessing_done db ? + +params rb 1000h +options rb 1000h +predefinitions rb 1000h +buffer rb 4000h + +stack 10000h + +section '.idata' import data readable writeable + + dd 0,0,0,rva kernel_name,rva kernel_table + dd 0,0,0,0,0 + + kernel_table: + ExitProcess dd rva _ExitProcess + CreateFile dd rva _CreateFileA + ReadFile dd rva _ReadFile + WriteFile dd rva _WriteFile + CloseHandle dd rva _CloseHandle + SetFilePointer dd rva _SetFilePointer + GetCommandLine dd rva _GetCommandLineA + GetEnvironmentVariable dd rva _GetEnvironmentVariable + GetStdHandle dd rva _GetStdHandle + VirtualAlloc dd rva _VirtualAlloc + VirtualFree dd rva _VirtualFree + GetTickCount dd rva _GetTickCount + GetSystemTime dd rva _GetSystemTime + SetUnhandledExceptionFilter dd rva _SetUnhandledExceptionFilter + dd 0 + + kernel_name db 'KERNEL32.DLL',0 + + _ExitProcess dw 0 + db 'ExitProcess',0 + _CreateFileA dw 0 + db 'CreateFileA',0 + _ReadFile dw 0 + db 'ReadFile',0 + _WriteFile dw 0 + db 'WriteFile',0 + _CloseHandle dw 0 + db 'CloseHandle',0 + _SetFilePointer dw 0 + db 'SetFilePointer',0 + _GetCommandLineA dw 0 + db 'GetCommandLineA',0 + _GetEnvironmentVariable dw 0 + db 'GetEnvironmentVariableA',0 + _GetStdHandle dw 0 + db 'GetStdHandle',0 + _VirtualAlloc dw 0 + db 'VirtualAlloc',0 + _VirtualFree dw 0 + db 'VirtualFree',0 + _GetTickCount dw 0 + db 'GetTickCount',0 + _GetSystemTime dw 0 + db 'GetSystemTime',0 + _SetUnhandledExceptionFilter dw 0 + db 'SetUnhandledExceptionFilter',0 + +section '.reloc' fixups data readable discardable diff --git a/source/win32/systemarm.inc b/source/win32/systemarm.inc new file mode 100644 index 0000000..510f489 --- /dev/null +++ b/source/win32/systemarm.inc @@ -0,0 +1,628 @@ +MEMORY_ALLOCATION_BLOCK_SIZE = 1 shl 16 ;64kB. Higher numbers reduce the number of calls to the allocator. A value of 1 will allocate just the page where the memory is accessed +MEMORY_ALLOCATION_MAX_SIZE = 0x7ffc0000 ;Windows fails all calls that try to allocate more than this + +; flat assembler interface for Win32 +; Copyright (c) 1999-2015, Tomasz Grysztar. +; All rights reserved. + +CREATE_NEW = 1 +CREATE_ALWAYS = 2 +OPEN_EXISTING = 3 +OPEN_ALWAYS = 4 +TRUNCATE_EXISTING = 5 + +FILE_SHARE_READ = 1 +FILE_SHARE_WRITE = 2 +FILE_SHARE_DELETE = 4 + +GENERIC_READ = 80000000h +GENERIC_WRITE = 40000000h + +STD_INPUT_HANDLE = 0FFFFFFF6h +STD_OUTPUT_HANDLE = 0FFFFFFF5h +STD_ERROR_HANDLE = 0FFFFFFF4h + +MEM_COMMIT = 1000h +MEM_RESERVE = 2000h +MEM_DECOMMIT = 4000h +MEM_RELEASE = 8000h +MEM_FREE = 10000h +MEM_PRIVATE = 20000h +MEM_MAPPED = 40000h +MEM_RESET = 80000h +MEM_TOP_DOWN = 100000h + +PAGE_NOACCESS = 1 +PAGE_READONLY = 2 +PAGE_READWRITE = 4 +PAGE_WRITECOPY = 8 +PAGE_EXECUTE = 10h +PAGE_EXECUTE_READ = 20h +PAGE_EXECUTE_READWRITE = 40h +PAGE_EXECUTE_WRITECOPY = 80h +PAGE_GUARD = 100h +PAGE_NOCACHE = 200h + +init_memory: + xor eax,eax + mov [memory_start],eax + mov eax,esp + and eax,not 0FFFh + add eax,1000h-10000h + mov [stack_limit],eax + mov ebx,[memory_setting] + shl ebx,10 + jnz allocate_memory + mov ebx,MEMORY_ALLOCATION_MAX_SIZE + allocate_memory: + push PAGE_READWRITE + push MEM_RESERVE + push ebx + push 0 + call [VirtualAlloc] ;allocate the main section + test eax,eax + jz not_enough_memory + mov [memory_start],eax + add eax,ebx + mov [memory_end],eax + cmp [memory_setting],0 + jnz .use_single_section + mov eax,ebx + shr eax,1 + push PAGE_READWRITE + push MEM_RESERVE + push eax + push 0 + call [VirtualAlloc] ;allocate the additional section + test eax,eax + jz .use_single_section + mov [additional_memory],eax + shr ebx,1 + add eax,ebx + mov [additional_memory_end],eax + .memory_okay: + push memory_allocation_handler + call [SetUnhandledExceptionFilter] + ret + .use_single_section: + mov eax,[memory_end] + mov [additional_memory_end],eax + shr ebx,2 + sub eax,ebx + mov [memory_end],eax + mov [additional_memory],eax + jmp .memory_okay + not_enough_memory: + shr ebx,2 + lea ebx,[ebx*3] + cmp ebx,4000h + jae allocate_memory + jmp out_of_memory + +exit_program: + movzx eax,al + push eax + mov eax,[memory_start] + test eax,eax + jz do_exit + push MEM_RELEASE + push 0 + push eax + call [VirtualFree] + push MEM_RELEASE + push 0 + push [additional_memory] + call [VirtualFree] + do_exit: + call [ExitProcess] + +memory_allocation_handler: + mov eax,[esp+4] ;get pointer to exception information + mov ecx,[eax] ;EXCEPTION_POINTERS.ExceptionRecord + mov edx,[ecx] ;EXCEPTION_RECORD.ExceptionCode + cmp edx,0xc0000005 ;EXCEPTION_ACCESS_VIOLATION + jnz .fail + mov edx,[ecx+24] ;EXCEPTION_RECORD.ExceptionAddress + cmp edx,[memory_start] + jb .check_additional + mov eax,[memory_end] + sub eax,edx ;don't allocate more than EAX bytes + ja .allocate + .check_additional: + cmp edx,[additional_memory] + jb .fail + mov eax,[additional_memory_end] + sub eax,edx ;don't allocate more than EAX bytes + jbe .fail + .allocate: + mov ecx,MEMORY_ALLOCATION_BLOCK_SIZE + cmp eax,ecx + jbe .allocation_size_defined + mov eax,ecx ;don't allocate more than ECX bytes + .allocation_size_defined: + push PAGE_READWRITE + push MEM_COMMIT + push eax ;allocate this many bytes + push edx ;at this address + call [VirtualAlloc] + test eax,eax + jz out_of_memory + mov eax,-1 ;EXCEPTION_CONTINUE_EXECUTION + retn 4 + .fail: ;some other exception happened + mov eax,0 ;EXCEPTION_CONTINUE_SEARCH + retn 4 + +get_environment_variable: + mov ecx,[memory_end] + sub ecx,edi + cmp ecx,4000h + jbe buffer_for_variable_ok + mov ecx,4000h + buffer_for_variable_ok: + push ecx + push edi + push esi + call [GetEnvironmentVariable] + add edi,eax + cmp edi,[memory_end] + jae out_of_memory + ret + +open: + push 0 + push 0 + push OPEN_EXISTING + push 0 + push FILE_SHARE_READ + push GENERIC_READ + push edx + call [CreateFile] + cmp eax,-1 + je file_error + mov ebx,eax + clc + ret + file_error: + stc + ret +create: + push 0 + push 0 + push CREATE_ALWAYS + push 0 + push FILE_SHARE_READ + push GENERIC_WRITE + push edx + call [CreateFile] + cmp eax,-1 + je file_error + mov ebx,eax + clc + ret +write: + push 0 + push bytes_count + push ecx + push edx + push ebx + call [WriteFile] + or eax,eax + jz file_error + clc + ret +read: + mov ebp,ecx + test ecx,ecx + jz .zero_length + push edx + push PAGE_READWRITE + push MEM_COMMIT + push ecx ;allocate the required number of bytes + push edx ;at this address + call [VirtualAlloc] + pop edx + test eax,eax + jz out_of_memory + .zero_length: + push 0 + push bytes_count + push ebp + push edx + push ebx + call [ReadFile] + or eax,eax + jz file_error + cmp ebp,[bytes_count] + jne file_error + clc + ret +close: + push ebx + call [CloseHandle] + ret +lseek: + movzx eax,al + push eax + push 0 + push edx + push ebx + call [SetFilePointer] + ret + +display_string: + push [con_handle] + call [GetStdHandle] + mov ebp,eax + mov edi,esi + or ecx,-1 + xor al,al + repne scasb + neg ecx + sub ecx,2 + push 0 + push bytes_count + push ecx + push esi + push ebp + call [WriteFile] + ret +display_character: + push ebx + mov [character],dl + push [con_handle] + call [GetStdHandle] + mov ebx,eax + push 0 + push bytes_count + push 1 + push character + push ebx + call [WriteFile] + pop ebx + ret +display_number: + push ebx + mov ecx,1000000000 + xor edx,edx + xor bl,bl + display_loop: + div ecx + push edx + cmp ecx,1 + je display_digit + or bl,bl + jnz display_digit + or al,al + jz digit_ok + not bl + display_digit: + mov dl,al + add dl,30h + push ecx + call display_character + pop ecx + digit_ok: + mov eax,ecx + xor edx,edx + mov ecx,10 + div ecx + mov ecx,eax + pop eax + or ecx,ecx + jnz display_loop + pop ebx + ret + +display_user_messages: + mov [displayed_count],0 + call show_display_buffer + cmp [displayed_count],1 + jb line_break_ok + je make_line_break + mov ax,word [last_displayed] + cmp ax,0A0Dh + je line_break_ok + cmp ax,0D0Ah + je line_break_ok + make_line_break: + mov word [buffer],0A0Dh + push [con_handle] + call [GetStdHandle] + push 0 + push bytes_count + push 2 + push buffer + push eax + call [WriteFile] + line_break_ok: + ret +display_block: + add [displayed_count],ecx + cmp ecx,1 + ja take_last_two_characters + jb block_displayed + mov al,[last_displayed+1] + mov ah,[esi] + mov word [last_displayed],ax + jmp block_ok + take_last_two_characters: + mov ax,[esi+ecx-2] + mov word [last_displayed],ax + block_ok: + push ecx + push [con_handle] + call [GetStdHandle] + pop ecx + push 0 + push bytes_count + push ecx + push esi + push eax + call [WriteFile] + block_displayed: + ret + +fatal_error: + mov [con_handle],STD_ERROR_HANDLE + mov esi,error_prefix + call display_string + pop esi + call display_string + mov esi,error_suffix + call display_string + mov al,0FFh + jmp exit_program +assembler_error: + mov [con_handle],STD_ERROR_HANDLE + call display_user_messages + mov ebx,[current_line] + test ebx,ebx + jz display_error_message + push dword 0 + get_error_lines: + mov eax,[ebx] + cmp byte [eax],0 + je get_next_error_line + push ebx + test byte [ebx+7],80h + jz display_error_line + mov edx,ebx + find_definition_origin: + mov edx,[edx+12] + test byte [edx+7],80h + jnz find_definition_origin + push edx + get_next_error_line: + mov ebx,[ebx+8] + jmp get_error_lines + display_error_line: + mov esi,[ebx] + call display_string + mov esi,line_number_start + call display_string + mov eax,[ebx+4] + and eax,7FFFFFFFh + call display_number + mov dl,']' + call display_character + pop esi + cmp ebx,esi + je line_number_ok + mov dl,20h + call display_character + push esi + mov esi,[esi] + movzx ecx,byte [esi] + inc esi + call display_block + mov esi,line_number_start + call display_string + pop esi + mov eax,[esi+4] + and eax,7FFFFFFFh + call display_number + mov dl,']' + call display_character + line_number_ok: + mov esi,line_data_start + call display_string + mov esi,ebx + mov edx,[esi] + call open + mov al,2 + xor edx,edx + call lseek + mov edx,[esi+8] + sub eax,edx + jz line_data_displayed + push eax + xor al,al + call lseek + mov ecx,[esp] + mov edx,[additional_memory] + lea eax,[edx+ecx] + cmp eax,[additional_memory_end] + ja out_of_memory + call read + call close + pop ecx + mov esi,[additional_memory] + get_line_data: + mov al,[esi] + cmp al,0Ah + je display_line_data + cmp al,0Dh + je display_line_data + cmp al,1Ah + je display_line_data + or al,al + jz display_line_data + inc esi + loop get_line_data + display_line_data: + mov ecx,esi + mov esi,[additional_memory] + sub ecx,esi + call display_block + line_data_displayed: + mov esi,cr_lf + call display_string + pop ebx + or ebx,ebx + jnz display_error_line + cmp [preprocessing_done],0 + je display_error_message + mov esi,preprocessed_instruction_prefix + call display_string + mov esi,[current_line] + add esi,16 + mov edi,[additional_memory] + xor dl,dl + convert_instruction: + lodsb + cmp al,1Ah + je copy_symbol + cmp al,22h + je copy_symbol + cmp al,3Bh + je instruction_converted + stosb + or al,al + jz instruction_converted + xor dl,dl + jmp convert_instruction + copy_symbol: + or dl,dl + jz space_ok + mov byte [edi],20h + inc edi + space_ok: + cmp al,22h + je quoted + lodsb + movzx ecx,al + rep movsb + or dl,-1 + jmp convert_instruction + quoted: + mov al,27h + stosb + lodsd + mov ecx,eax + jecxz quoted_copied + copy_quoted: + lodsb + stosb + cmp al,27h + jne quote_ok + stosb + quote_ok: + loop copy_quoted + quoted_copied: + mov al,27h + stosb + or dl,-1 + jmp convert_instruction + instruction_converted: + xor al,al + stosb + mov esi,[additional_memory] + call display_string + mov esi,cr_lf + call display_string + display_error_message: + mov esi,error_prefix + call display_string + pop esi + call display_string + mov esi,error_suffix + call display_string + mov al,2 + jmp exit_program + +make_timestamp: + push buffer + call [GetSystemTime] + movzx ecx,word [buffer] + mov eax,ecx + sub eax,1970 + mov ebx,365 + mul ebx + mov ebp,eax + mov eax,ecx + sub eax,1969 + shr eax,2 + add ebp,eax + mov eax,ecx + sub eax,1901 + mov ebx,100 + div ebx + sub ebp,eax + mov eax,ecx + xor edx,edx + sub eax,1601 + mov ebx,400 + div ebx + add ebp,eax + movzx ecx,word [buffer+2] + mov eax,ecx + dec eax + mov ebx,30 + mul ebx + add ebp,eax + cmp ecx,8 + jbe months_correction + mov eax,ecx + sub eax,7 + shr eax,1 + add ebp,eax + mov ecx,8 + months_correction: + mov eax,ecx + shr eax,1 + add ebp,eax + cmp ecx,2 + jbe day_correction_ok + sub ebp,2 + movzx ecx,word [buffer] + test ecx,11b + jnz day_correction_ok + xor edx,edx + mov eax,ecx + mov ebx,100 + div ebx + or edx,edx + jnz day_correction + mov eax,ecx + mov ebx,400 + div ebx + or edx,edx + jnz day_correction_ok + day_correction: + inc ebp + day_correction_ok: + movzx eax,word [buffer+6] + dec eax + add eax,ebp + mov ebx,24 + mul ebx + movzx ecx,word [buffer+8] + add eax,ecx + mov ebx,60 + mul ebx + movzx ecx,word [buffer+10] + add eax,ecx + mov ebx,60 + mul ebx + movzx ecx,word [buffer+12] + add eax,ecx + adc edx,0 + ret + +error_prefix db 'error: ',0 +error_suffix db '.' +cr_lf db 0Dh,0Ah,0 +line_number_start db ' [',0 +line_data_start db ':',0Dh,0Ah,0 +preprocessed_instruction_prefix db 'processed: ',0