download 2023-06-01

diff --git a/ReadMe.txt b/ReadMe.txt
new file mode 100644 (file)
index 0000000..6d1583e
--- /dev/null
+++ b/ReadMe.txt
@@ -0,0 +1,781 @@
+\r
+FASMARM v1.44\r
+\r
+This package is an ARM assembler add-on for FASM.\r
+\r
+FASMARM currently supports the full range of instructions for 32-bit and 64-bit\r
+ARM processors and coprocessors up to and including v8.\r
+\r
+Contents:\r
+\r
+        1. ARM assembly compatibility\r
+        2. UAL and pre-UAL syntaxes\r
+        3. IT block handling\r
+        4. Alternate encodings\r
+        5. Output formats\r
+        6. Control directives\r
+        7. Data definitions\r
+        8. Defining registers lists inside macros\r
+        9. Half-precision number formatting\r
+       10. Variants supported\r
+       11. Further information\r
+       12. Version history\r
+\r
+_______________________________________________________________________________\r
+                       1. ARM assembly compatibility\r
+\r
+There are a few restrictions how the ARM instruction set is implemented. The\r
+changes are minor and mostly have a minor impact. For the most part the basic\r
+instruction outline is the same. Where possible the original style is used but\r
+there are some differences:\r
+\r
+Not everything matches the ARM ADS assembly style, where possible the original\r
+style is used but there are some differences\r
+1) label names cannot begin with a digit\r
+2) CPSIE and CPSID formats are changed, use "iflags_aif" form instead of "aif"\r
+   (eg. "CPSIE iflags_i" instead of "CPSID i")\r
+3) SRS with writeback must have a separating space after the mode number and\r
+   before "!" (eg. "SRSDB 16 !" instead of "SRSDB 16!")\r
+4) macro, rept, irp, format, if, virtual etc. are all significant changes from\r
+   the ARM ADS, so you will need to re-write those sections of existing code\r
+\r
+       Original ARM Syntax   | fasmarm Syntax\r
+       ----------------------+----------------------\r
+       cpsie a               | cpsie iflags_a\r
+                             |\r
+       srsdb #29!            | srsdb #29 !      ;or,\r
+                             | srsdb 29 !\r
+\r
+_______________________________________________________________________________\r
+                       2. UAL and pre-UAL syntaxes\r
+\r
+fasmarm supports the original pre-UAL syntax and the newer UAL syntax. These\r
+two syntaxes only affect THUMB encodings.\r
+\r
+UAL stands for: Universal Assembly Language.\r
+\r
+pre-UAL syntax is selected with the directive CODE16.\r
+UAL syntax is selected with the directive THUMB.\r
+\r
+pre-UAL syntax does not specify the "s" (flag update) in the opcodes for\r
+arithmetic operations involving the low set of registers (r0-r7). For example:\r
+\r
+       pre-UAL Syntax  | UAL Syntax  ;Note\r
+       ----------------+------------------------------------------------------\r
+       add r0,r1       | adds r0,r1  ;"s" was implicit with all registers <=r7\r
+       adds r0,r1      | adds r0,r1\r
+       <no opcode>     | add r0,r1   ;only available inside an IT block, or\r
+                       |             ;as 32-bit T2 instruction\r
+       add r8,r1       | add r8,r1   ;high register used, does not update PSR\r
+       adds r8,r1      | adds r8,r1  ;only available as 32-bit T2 instruction\r
+                       |\r
+       mov r0,r1       | movs r0,r1  ;"s" was implicit with all registers <=r7\r
+       mov r8,r1       | mov r8,r1   ;high register used, does not update PSR\r
+       movs r0,r1      | movs r0,r1\r
+       movs r8,r1      | movs r8,r1  ;only available as 32-bit T2 instruction\r
+                       |\r
+       cpy r0,r1       | cpy r0,r1   ;also: mov r0,r1 in UAL\r
+\r
+Code written in UAL syntax can generally be assembled without modification in\r
+both ARM and THUMB modes. It is recommended to use UAL syntax for all new code.\r
+UAL syntax is get-what-you-write, whereas pre-UAL syntax has an implicit "s"\r
+flag which can potentially be unclear about what you will get. This is\r
+especially important in macros and structures where register numbers may be\r
+unknown until instantiated.\r
+\r
+Both syntaxes support triple and double register operands: "add r0,r0,r1" can\r
+be shortened to "add r0,r1"\r
+\r
+_______________________________________________________________________________\r
+                       3. IT block handling\r
+\r
+In THUMB mode fasmarm can insert IT blocks automatically:\r
+\r
+       thumb           ;use UAL syntax\r
+       ;itet   eq      ;fasmarm inserts an automatic "IT EQ" block\r
+       subeq   r0,r1   ;T(rue) = eq\r
+       subsne  r2,r3   ;E(lse) = ne\r
+       subseq  r4,r5   ;T(rue) = eq\r
+\r
+\r
+fasmarm will check that manually placed IT blocks are consistent with\r
+subsequent code:\r
+\r
+       thumb           ;use UAL syntax\r
+       itet    eq      ;manually placed IT block\r
+       subeq   r0,r1   ;T(rue) = eq, fasmarm checks the conditions are matched\r
+       subsne  r2,r3   ;E(lse) = ne, fasmarm checks the conditions are matched\r
+       subseq  r4,r5   ;T(rue) = eq, fasmarm checks the conditions are matched\r
+\r
+\r
+IT blocks cannot span across labels:\r
+\r
+       thumb           ;use UAL syntax\r
+       ;it     eq      ;fasmarm inserts an automatic "IT EQ" block\r
+       subeq   r0,r1   ;T(rue) = eq\r
+lab1:  ;ite    ne      ;fasmarm inserts a new "IT NE" block\r
+       subsne  r2,r3   ;T(rue) = ne\r
+       subseq  r4,r5   ;E(lse) = eq\r
+\r
+\r
+fasmarm will check that manually placed IT blocks do not span labels:\r
+\r
+       ite     mi      ;manually placed IT block\r
+       submi   r0,r1   ;T(rue) = mi, fasmarm checks the conditions are matched\r
+lab2:  subspl  r2,r3   ;Error: IT block would span across the label\r
+\r
+\r
+IT blocks cannot span across changes to PC:\r
+\r
+       thumb           ;use UAL syntax\r
+       ;ite    eq      ;fasmarm inserts an automatic "IT EQ" block\r
+       subeq   r0,r1   ;T(rue) = eq\r
+       bne     lab2    ;E(lse) = ne, branch will finish the IT block\r
+       ;it     eq      ;fasmarm inserts a new "IT EQ" block\r
+       subseq  r4,r5   ;T(rue) = eq\r
+\r
+_______________________________________________________________________________\r
+                       4. Alternate encodings\r
+\r
+fasmarm follows this principle: Find a way to encode it, the smaller the better\r
+\r
+What this means is that even though you may write a particular opcocde, fasmarm\r
+may assemble another as a replacement. This can only happen where the\r
+functionality is exactly the same. The reason for doing this is to increase the\r
+likelihood of a successful assembly. This will only affect you if you want to\r
+look at a disassembly listing and match it to the original source. Example:\r
+\r
+       What you coded     | What is assembled  ;reason\r
+       -------------------+---------------------------------------------------\r
+                         ARM\r
+       and r0,0xfffffff0  | bic r0,0x0000000f  ;immediate could not be encoded\r
+       add r1,-4          | sub r1,4           ;immediate could not be encoded\r
+       cmp r2,0xffffe500  | cmn r2,0x00001b00  ;immediate could not be encoded\r
+       lsr r1,r2,r3       | mov r1,r2,lsr r3   ;ARM mode does not have LSR\r
+       pop {r0-r3}        | ldmfd r13!,{r0-r3} ;ARM mode does not have POP\r
+       mul r4,r4,r11      | mul r4,r11,r4      ;encoding restriction for\r
+                          |                    ;CPU versions before v6\r
+                        THUMB\r
+       ldmfd r13!,{r0-r3} | pop {r0-r3}        ;THUMB mode uses pop\r
+       ldmfd r10!,{r8}    | ldr r8,[r10],4     ;forbidden single register LDMs\r
+       pop {r8}           | ldr r8,[r13],4     ;forbidden single register POP\r
+       add r2,0x89a       | addw r2,0x89a      ;immediate could not be encoded\r
+                        BOTH\r
+       mov r1,0x4567      | movw r1,0x4567     ;immediate could not be encoded\r
+\r
+Other instructions than just what is shown above are also affected.\r
+\r
+The last part of the principles, the smaller the better, may impact THUMB code\r
+where a particular alignment is required. If you need to ensure that a\r
+particular instruction is always 32-bit, or always 16-bit, then you can use the\r
+qualifiers ".W" and ".N" after the opcodes and conditions to force either wide\r
+(32-bit) or narrow (16-bit) encodings. If the instruction cannot be encoded in\r
+the desired width fasmarm will give an error. If the instruction does not have\r
+both wide an narrow forms then the .W and .N suffixes are undefined. If you\r
+give no width suffix fasmarm will select the narrow form if it is available and\r
+encodable, and the wide form otherwise.\r
+\r
+To see how this impacts code using IT blocks examine the following example:\r
+\r
+       thumb           ;use UAL syntax\r
+       sub     r0,r1   ;only encodable as 32-bit outside an IT block\r
+       subs    r2,r3   ;fasmarm chooses the 16-bit form\r
+       subs.w  r4,r5   ;32-bit "wide" encoding forced\r
+       b       .next1\r
+       ;...\r
+    .next1:\r
+       ;ittt   al      ;fasmarm inserts an automatic "IT AL" block\r
+       sub     r0,r1   ;fasmarm chooses the 16-bit form inside an IT block\r
+       sub     r2,r3   ;fasmarm chooses the 16-bit form inside an IT block\r
+       b       .next2  ;IT block extends to here\r
+       ;...\r
+    .next2:\r
+       ;itttt  al      ;fasmarm inserts an automatic "IT AL" block\r
+       sub     r0,r1   ;fasmarm chooses the 16-bit form inside an IT block\r
+       sub     r2,r3   ;fasmarm chooses the 16-bit form inside an IT block\r
+       sub     r9,r5   ;high register used, only encodable as 32-bit\r
+       sub     r6,r7   ;fasmarm chooses the 16-bit form inside an IT block\r
+\r
+The insertion of automatic "IT AL" blocks is only done when a reduction in code\r
+size is possible. To inhibit automatic "IT AL" block insertion you can force\r
+affected instructions to use the wide encoding with a .W suffix, or use the\r
+directive ITNOAUTO. To enable automatic insertion of IT AL blocks use the\r
+ITAUTO directive. ITAUTO is the default mode at startup. ITNOAUTO and ITAUTO\r
+directives only affect IT blocks using AL. Other condition codes will still\r
+be inserted automatically if not included explicitly.\r
+\r
+       itauto          ;enable automatic IT AL insertion from now onwards\r
+       thumb           ;use UAL syntax\r
+       sub.w   r0,r1   ;32-bit "wide" encoding forced\r
+       sub.w   r2,r3   ;32-bit "wide" encoding forced\r
+       b       .next2\r
+       ;...\r
+    .next2:\r
+       itnoauto        ;inhibit automatic IT AL insertion from now onwards\r
+       sub     r0,r1   ;32-bit "wide" encoding used\r
+       sub     r2,r3   ;32-bit "wide" encoding used\r
+\r
+_______________________________________________________________________________\r
+                       5. Output formats\r
+\r
+The "format" directive will produce ARM code in all the same formats as the X86\r
+version plus one additional format: ELF DWARF. The ELF DWARF is compatible with\r
+the ARM AXD debugger. The DWARF format produced includes all program labels,\r
+line numbers and module names for full symbolic debugging. The ELF format has\r
+been changed to set the FLAGS, code base and machine type compatible for\r
+ARM-LINUX. The PE format has been changed to set the machine type, subsystem\r
+and code base compatible with WinCE. PE64 format is available without\r
+relocations. ELF64 format has not yet been updated.\r
+\r
+Use format like this to get the dwarf output:\r
+\r
+       format elf dwarf executable [at ?]\r
+\r
+Line number and the symbol table generation are automatically enabled with this\r
+format. Using "at" is optional and defaults to 0.\r
+\r
+The "section" directive for DWARF output is like this:\r
+\r
+       section "name" [executable | readable | writeable | at ?] align ?\r
+\r
+The "name" is required. Align is required and must be a power of 2. All other\r
+attributes are optional except that at least one of executable, readable or\r
+writeable must be specified. Using "at" is optional and defaults to the next\r
+aligned address. Attributes can be specified in any order except "name" which\r
+must be first.\r
+\r
+The "org" directive is not allowed in DWARF output mode, otherwise everything\r
+is the same as for normal ELF output.\r
+\r
+Relocations for ELF and PE are not supported at this time.\r
+\r
+_______________________________________________________________________________\r
+                       6. Control directives\r
+\r
+There are five directives to control the code generation state:\r
+\r
+       CODE64  - Switches to ARM64 (64bit instructions) code generation (alias\r
+                 USE64)\r
+       CODE32  - Switches to ARM (32bit instructions) code generation (alias\r
+                 USE32)\r
+       CODE16  - Switches to THUMB pre-UAL (16bit instructions) code\r
+                 generation (alias USE16)\r
+       THUMB   - Switches to THUMB UAL (16bit instructions) code generation\r
+       THUMBEE - Switches to ThumbEE UAL (16bit instructions) code generation\r
+\r
+At startup the default is CODE32.\r
+\r
+There are two directives to control the instruction set classes enabled:\r
+\r
+       PROCESSOR <selection>\r
+       COPROCESSOR <selection>\r
+\r
+Where <selection> is a list instruction classes to enable or disable. Use a\r
+plus symbol (+) to enable, and a minus symbol (-) to disable. By default only\r
+the CPU32_* and COPRO_* instructions are enabled.\r
+\r
+To enable or disable one or more instruction classes without changing other\r
+classes use a leading plus (+) or minus (-) to incrementally update the\r
+settings. For example:\r
+\r
+       processor cpu64_v8      ;enable only 64-bit version 8 base instructions\r
+                               ;all other instruction classes are disabled\r
+       processor +cpu64_fp     ;additionally enable the 64-bit floating point.\r
+                               ;If they were already enabled then they remain\r
+                               ;enabled. Other classes are unaffected.\r
+\r
+       processor cpu64_v8 +cpu64_fp    ;Both combined has the same effect as\r
+                                       ;above two examples.\r
+\r
+       coprocessor -copro_vfp_v4       ;disable only the VFP V4 instructions.\r
+                                       ;If they were already disabled then\r
+                                       ;they remain disabled. Other classes\r
+                                       ;are unaffected.\r
+\r
+To query the selected instruction classes you can use the 'if' directive to do\r
+logical tests. For example:\r
+\r
+       if processor cpu32_v7 | processor cpu32_7m\r
+               ;do something\r
+       end if\r
+\r
+       if coprocessor copro_vfp_v4\r
+               ;do something\r
+       else\r
+               ;do something else\r
+       end if\r
+\r
+The following is a list of processor instruction classes supported:\r
+       CPU32_26BIT, CPU32_V1, CPU32_V2, CPU32_A, CPU32_V3, CPU32_M, CPU32_V4,\r
+       CPU32_V4T, CPU32_V5, CPU32_V5T, CPU32_E, CPU32_P, CPU32_J, CPU32_X,\r
+       CPU32_V6, CPU32_V6T, CPU32_ALIGN, CPU32_K, CPU32_Z, CPU32_6M, CPU32_7M,\r
+       CPU32_T2, CPU32_V7, CPU32_SYNC, CPU32_DIV, CPU32_T2EE, CPU32_MP,\r
+       CPU32_VE, CPU32_V8, CPU32_CRC, CPU64_V8, CPU64_FP, CPU64_SIMD,\r
+       CPU64_CRC, CPU64_CRYPTO\r
+\r
+The following is a list of coprocessor instruction classes supported:\r
+       COPRO_FPA_V1, COPRO_FPA_V2, COPRO_MAVERICK, COPRO_VFP_V1XD,\r
+       COPRO_VFP_V1, COPRO_VFP_V2, COPRO_VFP_V3, COPRO_VFP_D32, COPRO_VFP_HP,\r
+       COPRO_XSCALE, COPRO_IWMMXT_V1, COPRO_IWMMXT_V2, COPRO_SIMD_INT,\r
+       COPRO_SIMD_FLOAT, COPRO_SIMD_HP, COPRO_VFP_V4, COPRO_SIMD_V2,\r
+       COPRO_SIMD_V8, COPRO_SIMD_CRYPTO\r
+\r
+There are three combination instruction classes that will either enable or\r
+disable all instructions within the class:\r
+       CPU32_ALL, CPU64_ALL, COPRO_ALL\r
+\r
+For backward compatibility with previous versions a single numeric constant can\r
+be specified instead of a list of classes. This is only supported for the\r
+following values:\r
+\r
+       PROCESSOR supported immediate values:\r
+               CPU32_CAPABILITY_26BIT          = 1 shl 00\r
+               CPU32_CAPABILITY_V1             = 1 shl 01\r
+               CPU32_CAPABILITY_V2             = 1 shl 02\r
+               CPU32_CAPABILITY_A              = 1 shl 03\r
+               CPU32_CAPABILITY_V3             = 1 shl 04\r
+               CPU32_CAPABILITY_M              = 1 shl 05\r
+               CPU32_CAPABILITY_V4             = 1 shl 06\r
+               CPU32_CAPABILITY_V4T            = 1 shl 07\r
+               CPU32_CAPABILITY_V5             = 1 shl 08\r
+               CPU32_CAPABILITY_V5T            = 1 shl 09\r
+               CPU32_CAPABILITY_E              = 1 shl 10\r
+               CPU32_CAPABILITY_P              = 1 shl 11\r
+               CPU32_CAPABILITY_J              = 1 shl 12\r
+               CPU32_CAPABILITY_X              = 1 shl 13\r
+               CPU32_CAPABILITY_V6             = 1 shl 14\r
+               CPU32_CAPABILITY_V6T            = 1 shl 15\r
+               CPU32_CAPABILITY_ALIGN          = 1 shl 16\r
+               CPU32_CAPABILITY_K              = 1 shl 17\r
+               CPU32_CAPABILITY_Z              = 1 shl 18\r
+               CPU32_CAPABILITY_6M             = 1 shl 19\r
+               CPU32_CAPABILITY_7M             = 1 shl 20\r
+               CPU32_CAPABILITY_T2             = 1 shl 21\r
+               CPU32_CAPABILITY_V7             = 1 shl 22\r
+               CPU32_CAPABILITY_SYNC           = 1 shl 23\r
+               CPU32_CAPABILITY_DIV            = 1 shl 24\r
+               CPU32_CAPABILITY_T2EE           = 1 shl 25\r
+               CPU32_CAPABILITY_MP             = 1 shl 26\r
+               CPU32_CAPABILITY_VE             = 1 shl 27\r
+               CPU32_CAPABILITY_V8             = 1 shl 28\r
+               CPU32_CAPABILITY_CRC            = 1 shl 29\r
+\r
+       COPROCESSOR supported immediate values:\r
+               COPRO_CAPABILITY_FPA_V1         = 1 shl 00\r
+               COPRO_CAPABILITY_FPA_V2         = 1 shl 01\r
+               COPRO_CAPABILITY_MAVERICK       = 1 shl 02\r
+               COPRO_CAPABILITY_VFP_V1xD       = 1 shl 03\r
+               COPRO_CAPABILITY_VFP_V1         = 1 shl 04\r
+               COPRO_CAPABILITY_VFP_V2         = 1 shl 05\r
+               COPRO_CAPABILITY_VFP_V3         = 1 shl 06\r
+               COPRO_CAPABILITY_VFP_D32        = 1 shl 07\r
+               COPRO_CAPABILITY_VFP_HP         = 1 shl 08\r
+               COPRO_CAPABILITY_XSCALE         = 1 shl 09\r
+               COPRO_CAPABILITY_IWMMXT_V1      = 1 shl 10\r
+               COPRO_CAPABILITY_IWMMXT_V2      = 1 shl 11\r
+               COPRO_CAPABILITY_SIMD_INT       = 1 shl 12\r
+               COPRO_CAPABILITY_SIMD_FLOAT     = 1 shl 13\r
+               COPRO_CAPABILITY_SIMD_HP        = 1 shl 14\r
+               COPRO_CAPABILITY_VFP_V4         = 1 shl 15\r
+               COPRO_CAPABILITY_SIMD_V2        = 1 shl 16\r
+               COPRO_CAPABILITY_SIMD_V8        = 1 shl 17\r
+               COPRO_CAPABILITY_SIMD_CRYPTO    = 1 shl 18\r
+\r
+The above symbol names and values are not defined by fasmarm. You can add them\r
+to your source file to use them, or you can use just the raw numbers.\r
+\r
+There are two associated predefined symbols: %c and %p. %c is the bitmap value\r
+of the current coprocessor set enabled. %p is the bitmap value of the current\r
+processor set enabled. These predefined symbols only return values in the range\r
+as shown above. That means you can't the %p value to determine if any of the\r
+CPU64* instruction classes have been enabled. Instead use the 'if' form as\r
+shown earlier.\r
+\r
+Examples using a numeric constant:\r
+       For ARM7TDMI CPUs:\r
+               processor 0xfe\r
+               coprocessor 0x0\r
+\r
+       For PXA25x CPUs:\r
+               processor 0x2ffe\r
+               coprocessor 0x0200\r
+\r
+       For PXA27x CPUs:\r
+               processor 0x2ffe\r
+               coprocessor 0x0600\r
+\r
+       For Cortex-A8 CPUs:\r
+               processor 0x2fffffe\r
+               coprocessor 0x30f8\r
+\r
+       For Cortex-A9 CPUs:\r
+               processor 0x6fffffe\r
+               coprocessor 0x30f8\r
+\r
+At start-up the default is to enable the CPU32* instructions and all\r
+coprocessors. It you want to use later instruction classes and any 64-bit\r
+instructions these need to be specified with PROCESSOR before use.\r
+\r
+See the files in the ARMDOC folder for details about which instructions are\r
+enabled by each setting.\r
+\r
+_______________________________________________________________________________\r
+                       7. Data definitions\r
+\r
+Data definitions are different between ARM and X86. A "word" in ARM is 32 bits.\r
+\r
+       X86  ARM  comment\r
+       ---+----+---------\r
+       DB | DB | byte: 8 bits\r
+       DW | DH | half word: 16 bits\r
+       DU | DU | half word strings: 16 bits\r
+       DD | DW | word: 32 bits\r
+       DQ | DD | double word: 64 bits\r
+       RB | RB | byte: 8 bits\r
+       RW | RH | half word: 16 bits\r
+       RD | RW | word: 32 bits\r
+       RQ | RD | double word: 64 bits\r
+       DF | -- |  not valid\r
+       DP | -- |  not valid\r
+       DT | -- |  not valid\r
+       RF | -- |  not valid\r
+       RP | -- |  not valid\r
+       RT | -- |  not valid\r
+\r
+Address sizes are always 64 bits in ARM64 state and 32 bits in ARM and THUMB\r
+states, you can't use any address overrides.\r
+\r
+Data sizes are different between ARM and X86. A "word" in ARM is 32 bits.\r
+\r
+         X86      ARM     comment\r
+       --------+--------+---------------------\r
+        BYTE   | BYTE   | same: 8 bits\r
+        WORD   | HWORD  | half word: 16 bits\r
+        DWORD  | WORD   | word: 32 bits\r
+        QWORD  | DWORD  | double word: 64 bits\r
+        DQWORD | QWORD  | quad word: 128 bits\r
+        QQWORD | DQWORD | double quad word: 256 bits\r
+\r
+You can still use all the pre-processor and assembly features of FASM including\r
+macros, structures, repeats etc.\r
+\r
+_______________________________________________________________________________\r
+                       8. Defining registers lists inside macros\r
+\r
+The standard ARM syntax uses curly brackets, {}, to enclose registers lists.\r
+The standard fasm syntax uses curly brackets to enclose macros. Both standards\r
+are supported in fasmarm and you can mix them together. The way to state\r
+registers lists within macros is to escape the closing curly bracket with a\r
+leading backslash.\r
+\r
+       macro block_copy destination, source, length {\r
+               local   .loop\r
+               mov     r0,source\r
+               mov     r1,destination\r
+               add     r2,r0,length\r
+           .loop:\r
+               ldmia   r0!,{r3-r10\}   ;we have to escape the closing bracket\r
+               stmia   r1!,{r3-r10\}   ;we have to escape the closing bracket\r
+               cmp     r0,r2\r
+               blo     .loop\r
+       }\r
+\r
+_______________________________________________________________________________\r
+                       9. Half-precision number formatting\r
+\r
+The ARM specification allows extended range half-precision numbers. Care must\r
+be taken when defining numbers that fall within the extended range. Numbers in\r
+the range 65520.0 to 131039.0 inclusive can be defined using the DH directive\r
+and do not give any error. Values within this range place the exponent field at\r
+0x1f. If the CPU is not placed into alternative half-precision (AHP) mode then\r
+these numbers fall within the NaN and infinity encoding space.\r
+\r
+_______________________________________________________________________________\r
+                       10. Variants supported\r
+\r
+Five standard variants of FASM binaries can been produced for FASMARM:\r
+\r
+       FASMARM.EXE  - WIN32 console\r
+       FASMWARM.EXE - WIN32 IDE\r
+       FASMARM      - LINUX\r
+       FASMARM.X64  - LINUX64 console\r
+       FASMARM.O    - LIBC\r
+\r
+_______________________________________________________________________________\r
+                       11. Further information\r
+\r
+Visit http://www.arm.com for information on the ARM instruction sets and\r
+processors.\r
+\r
+Visit http://flatassembler.net for the FASM x86 assembler package and tools.\r
+\r
+If you want to recompile the FASMARM code you will need the flatassembler\r
+package from the above URL.\r
+\r
+To see what others have said and to participate in the development of fasmarm\r
+see the active thread on the fasm message board:\r
+http://board.flatassembler.net/topic.php?t=4191\r
+\r
+If you have a problem, question, suggestion, comment etc. you can contact me at\r
+http://board.flatassembler.net - my handle is revolution.\r
+\r
+_______________________________________________________________________________\r
+                       12. Version history\r
+\r
+v1.44 2023-Jul-01 - Update for compatibility with fasm v1.73.30\r
+                 - MOVN/MOVZ with zero immediate now encodes any given shift\r
+                 - Add Linux 64-bit version: fasmarm.x64\r
+                 - Add PE64 support for PIE code without relocations\r
+                 - Fix PE header bug in SizeOf(Un)InitializedData values\r
+                 - Fix errant check for thumb STRD duplicated source registers\r
+                 - Add allowance for DSB, DMB and ISB to accept numeric values\r
+                 - Honour two reg encoding for small immediates in thumb code\r
+                 - Add missing {VPUSH|VPOP}{.32|.64} aliases\r
+                 - Fix bug with 'IT LE' condition mis-tracking\r
+                 - Add alias of APSR_NZCV to R15 for VMRS/FMRX\r
+                 - Encode ROR by 0 to use LSL 0\r
+                 - Fix bug using LDMIA/STMDB for LDRB/STRB and LDRH/STRH\r
+                 - Reduce aggressiveness of register swapping in thumb mode\r
+                 - Fix detection of invalid values, this improves the\r
+                    minimisation in thumb mode\r
+                 - Fix STMDB/LDMIA conversion to PUsH/POP in thumb mode\r
+                 - Encode single reg LDM as LDM, not as LDR, in thumb mode\r
+                 - Fix bug with LDRD literal load permitting writeback\r
+                 - Delay triggering of using wide instructions until 6 passes\r
+                    before the last\r
+                 - Add ITAUTO and ITNOAUTO directives\r
+                 - Add support for '-' as input/output file in Linux, enabling\r
+                    FASMARM to be used in pipeline\r
+                 - Add Windows armpe64.asm example\r
+                 - Add swapping of ADD(S) X?,X?,SP & W?,W?,WSP in 64-bit code\r
+                 - Fix bug with ADRP erroneously giving unaligned error\r
+                 - Fix ELF format flags for Version5 EABI\r
+                 - Fix bug with undefined symbol used as an implicit address\r
+                    giving unexpected invalid R15 usage error\r
+                 - Fix crash bug in square and curly expression parsers\r
+                 - Set machine type for ELF64 to AARCH64\r
+                 - Fix bug with explicit register expressions creating bad\r
+                    immediate offsets\r
+\r
+v1.43 2017-Dec-26 - Fix a code minimisation logic regression\r
+\r
+v1.42 2017-Jul-23 - Fix a bug with unclosed curly and square bracket parsing\r
+\r
+v1.41 2016-Nov-09 - Fix a bug with forward referencing of labels in thumb mode\r
+\r
+v1.40 2016-May-14 - Fix a bug with unexpected size checks in 64-bit code for\r
+                    immediate values not used for addressing\r
+                 - Fix a bug with MOVK not respecting the shift amount when\r
+                    the immediate is zero\r
+                 - Change the IDE error summary dialog to show the full error\r
+                    message\r
+\r
+v1.39 2016-May-01 - Add 64-bit v8 instructions\r
+                 - Add simple expression evaluation inside address fields,\r
+                    e.g. "ldr x1,[x2-4]" and/or "ldr x1,[x2,-4]"\r
+                 - Add processing for lists of instruction classes to\r
+                    PROCESSOR and COPROCESSOR directives\r
+                 - Add 64-bit SemiHosting example program\r
+\r
+v1.38 2016-Apr-11 - Fixed more bugs with elf dwarf format file corruption\r
+                 - Fixed a bug with "section ... at 0" not updating PC to 0\r
+                 - Fixed an encoding bug with VMULL.P8\r
+                 - Add 32-bit v8 instructions\r
+\r
+v1.37 2015-Nov-16 - Added code and data generation from macro lines to the line\r
+                    number information table\r
+                 - Fixed a bug with elf dwarf format symbol table corruption\r
+                 - Fixed a bug where post-update instructions with a positive\r
+                    sign (eg. ldr r0,[r1],+r2) would always be forced negative\r
+\r
+v1.36 2015-Oct-05 - Fixed another bug with elf dwarf format file corruption\r
+\r
+v1.35 2015-Oct-01 - Fixed a bug with elf dwarf format file corruption\r
+\r
+v1.34 2015-Jun-18 - Fixed a bug with elf section offsets using "at"\r
+\r
+v1.33 2015-May-28 - Added on demand memory allocation for WIN32\r
+                 - Fixed MRC bug with R15 as the destination\r
+\r
+v1.32 2014-Dec-21 - Update with all fasm changes as at 1.71.31\r
+                 - Change the format of the undocumented CRC32 directive\r
+\r
+v1.31 2014-Jan-29 - Fixed long file names error during line number processing\r
+\r
+v1.30 2013-Sep-12 - Fixed THUMB encoding of LDRB and LDRH. Updated for fasm\r
+                     v1.71.13\r
+\r
+v1.29 2012-Dec-24 - Added missing assert directive. Updated for fasm v1.71.07,\r
+                    address space additions\r
+\r
+v1.28 2012-Jul-11 - Fixed a bug with 65-bit values in section origins\r
+\r
+v1.27 2012-Jun-09 - Updated for compatibility with fasm v1.70.02, 65-bit values\r
+\r
+v1.26 2012-Feb-24 - Added support for ARM/THUMB mode v7VE instructions\r
+                 - Added support for ARM/THUMB mode VFPv4 instructions\r
+                 - Added support for ARM/THUMB mode SIMDv2 instructions\r
+                 - Added alternate two operand forms for absolute difference\r
+                 - Removed alternate two operand forms for multiply-accumulate\r
+\r
+v1.25 2011-Oct-31 - Fixed a bug with BKPT handling in IT blocks in ARM mode\r
+\r
+v1.24 2011-Oct-29 - Fixed a bug with crashes during expression parsing\r
+\r
+v1.23 2011-Jul-31 - Fixed a bug with relocations corrupting patch code\r
+\r
+v1.22 2010-Nov-24 - Fixed a bug with handling nameless sections in dwarf format\r
+\r
+v1.21 2010-Oct-17 - Minimising the "code cannot be generated" problem. If the\r
+                    assembler gets to a third repetition at the same state\r
+                    then it takes action and uses wide instructions in\r
+                    situations where the narrow instructions are causing\r
+                    problems\r
+\r
+v1.20 2010-Sep-17 - Fixed a bug with handling of files names in dwarf format\r
+\r
+v1.19 2010-Sep-16 - Add support for half-precision and extended half-precision\r
+                    number formatting. Compatible with fasm v1.69.24\r
+\r
+v1.18 2010-Sep-09 - Update for compatibility with fasm v1.69.22\r
+\r
+v1.17 2010-Sep-08 - Added support to separate byte and rotation values for\r
+                    immediate values in shifter encoding\r
+\r
+v1.16 2010-Apr-26 - Added experimental instruction CRC32\r
+                 - Added experimental operator FIT\r
+                 - Added alternate encoding logic for VMOV/VMVN 16-bit and\r
+                    32-bit forms\r
+                 - Generate an error with more than 16 double registers in\r
+                    FLDMD/FSTMD/VLDM/VSTM/VPOP/VPUSH\r
+                 - Fixed erroneous generation of conditional instructions when\r
+                    mixing VIRTUAL with IT blocks\r
+                 - Fixed encoding for THUMB mode PC relative immediate\r
+                    addressing when placed inside auto IT block\r
+                 - Fixed encoding for WLDRx/WSTRx with PC relative addressing\r
+\r
+v1.15 2010-Apr-21 - Added support for ARM/THUMB mode v6T2 instructions\r
+                 - Added support for ARM/THUMB mode v7 instructions\r
+                 - Added support for ThumbEE instructions\r
+                 - Added support for FPA coprocessors up to v2\r
+                 - Added support for VFP coprocessors up to v3\r
+                 - Added support for MAVERICK coprocessors\r
+                 - Added support for Intel WMMXT coprocessors up to v2\r
+                 - Added support for Advanced SIMD coprocessors\r
+                 - Added support for alternate two register data processing\r
+                    operands. Implicit destination is the first operand\r
+                 - Added support for expressions in addresses to access PC\r
+                    relative variables and locations\r
+                 - Added support for automatic efficient IT block generation\r
+                    in THUMB mode\r
+                 - Added support for UAL assembly syntax\r
+                 - Added support for an optional hash (#) before literal\r
+                    values\r
+                 - Added predefined variables %c and %p\r
+                 - Added ARMDOC folder with example instruction formats for\r
+                    each opcode supported\r
+                 - Extended the alternate encoding logic\r
+                 - Changed numeric separation character from single quote (')\r
+                    to underscore (_)\r
+                 - Changed non-UAL SRS syntax to use a space, instead of a\r
+                    comma, between the mode number and writeback operator\r
+                 - Removed directives CODEFP, CODENOFP, CODEV5, CODEV6,\r
+                    CODEVFP1, CODEVFP2, ARM5, ARM6, VFP1 and VFP2. Use\r
+                    PROCESSOR and COPROCESSOR instead\r
+\r
+v1.14 2010-Feb-02 - Updated for compatibility with FASM 1.69.11\r
+                 - Changed "LDRx reg,[reg,0]!" to generate  "LDRx reg,[reg,0]"\r
+                 - Changed "LDRx reg,[reg],0" to generate  "LDRx reg,[reg,0]"\r
+                 - Changed "LDC Px,Cx,[reg,0]!" to generate\r
+                    "LDC Px,Cx,[reg,0]"\r
+                 - Changed "LDC Px,Cx,[reg],0" to generate\r
+                    "LDC Px,Cx,[reg,0]"\r
+                 - Fixed encoding for thumb mode BLX\r
+                 - Fixed encoding for PKHTB without shift\r
+                 - Fixed encoding for SSAT, SSAT16\r
+                 - Fixed encoding for UMAAL\r
+                 - Allowed rotation parameter for SXTB, SXTH, UXTB, UXTH\r
+\r
+v1.13 2008-Nov-04 - Updated register restrictions for STREX, SMLALD, SMLSLD,\r
+                    UMAAL, SMLALxy\r
+                 - Relaxed restriction of rotation count=0 (or omitted) for\r
+                    PKHTB\r
+                 - Enabled THUMB mode aliases for SXTB, SXTH, UXTB, UXTH\r
+\r
+v1.12 2008-Jul-13 - Updated for compatibility with FASM 1.67.27\r
+                 - Fixed "error: undefined symbol" displaying the wrong line\r
+\r
+v1.11 2008-Mar-20 - Updated for compatibility with FASM 1.67.26 (note: no\r
+                    version change)\r
+\r
+v1.11 2007-Aug-31 - Updated for compatibility with FASM 1.67.22\r
+                 - Fixed an address parser bug allowing "ldr rx,[constant]"\r
+                    without a register base\r
+\r
+v1.10 2007-Mar-04 - Updated for compatibility with FASM 1.67.21 expression\r
+                    calculation\r
+                 - Allowed forward referencing of register based structure\r
+                    addressing\r
+                 - Fixed a bug in the ARMLITRL.INC when generating PC relative\r
+                    offsets\r
+\r
+v1.09 2006-Aug-30 - Updated ARMTABLE.INC for compatibility with FASM 1.67\r
+                    binary searches\r
+                 - Updated PE format to initialise several accounting fields\r
+                    and also to reset the "relocs stripped" flag if relocs are\r
+                    included\r
+\r
+v1.08 2006-Jun-09 - Fixed erroneous error with implicit r0 based addressing\r
+                 - Fixed priority of unary minus to match FASM v1.66 priority\r
+                 - Relaxed restrictions with register structure addresses when\r
+                    using zero offset\r
+                 - Enhanced MOV/MOVS to use ADD/SUB encoding when loading a\r
+                    register structure member\r
+                 - Generation of special encoding to allow user code to detect\r
+                    unencodable immediate values and then select an alternate\r
+                    coding without causing assembly errors\r
+                 - Alignment bytes changed to 0xff to facilitate faster FLASH\r
+                    ROM updates\r
+                 - Added proc, apscall, import and literals macros to package,\r
+                    see each individual file for usage and special notes\r
+                 - STRUCT and RESOURCE converted from x86 to ARM format\r
+                 - COREDLL.INC converted to an imports definition file\r
+\r
+v1.07 2006-May-26 - Patch for basic "format PE" support for WinCE\r
+                 - Added ARMPE example for WinCE (2006-06-02)\r
+                 - COREDLL.DLL import ordinal equates added in "COREDLL.INC"\r
+                    (2006-06-02)\r
+\r
+v1.06 2006-Mar-03 - Updated to work within FASM version 1.66\r
+\r
+v1.05 2006-Feb-14 - Patch for basic "format ELF executable" support\r
+                 - Added ARMELF example\r
+\r
+v1.04 2005-Nov-09 - Fixed incorrect classification of data/code when using\r
+                    TIMES\r
+                 - Improved line number embedding generation for more\r
+                    efficient tables\r
+\r
+v1.03 2005-Oct-20 - Fixed IF/ELSE/END IF skip bug with commas\r
+\r
+v1.02 2005-Oct-03 - Fixed CPS mode change code generation\r
+                 - Fixed THUMB ASR and LSR shift range check\r
+\r
+v1.01 2005-Oct-01 - Fixed STMIA THUMB instruction checking for base register\r
+                    validity\r
+                 - Fixed error deferring for some expressions\r
+                 - Fixed shift count of 32\r
+                 - Added ARMv6 instructions\r
+                 - Added VFPv2 instructions\r
+                 - Added register aliases a1-a4, v1-v8, sb, sl, fp, ip\r
+                 - Added CODE16, CODE32, CODEFP, CODENOFP, CODEV5, CODEV6,\r
+                    CODEVFP1, CODEVFP2 directives\r
+                 - Added ARM5, ARM6, VFP1, VFP2  combination directives\r
+                 - Enforced code typing (generates an error if new\r
+                    instructions are used but not enabled)\r
+                 - Enforced VFP to be explicitly enabled before use\r
+                 - Removed condition code "NV"\r
+\r
+v1    2005-Sep-29 - First public release\r
+\r
+(C) 01-Jul-2023 revolution\r

diff --git a/armdoc/InstructionFormatsARM.asm b/armdoc/InstructionFormatsARM.asm
new file mode 100644 (file)
index 0000000..2ae7ac5
--- /dev/null
+++ b/armdoc/InstructionFormatsARM.asm
@@ -0,0 +1,1884 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition or flag\r
+;writeback ("s") syntaxes. Almost all instructions can\r
+;be conditional. The condition code should be added at\r
+;the end of the main opcode and before any size/type\r
+;specifiers. For example: "addhi" and "vaddhi.i16". The\r
+;syntax also supports the pre-UAL style of putting the\r
+;condition before any modifiers like "s" or "fd". For\r
+;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+processor CPU32_26BIT\r
+\r
+       cmnp    r0,1\r
+       cmnp    r0,1,2\r
+       cmnp    r0,r1\r
+       cmnp    r0,r1,rrx\r
+       cmnp    r0,r1,lsl 2\r
+       cmnp    r0,r1,lsr 2\r
+       cmnp    r0,r1,asr 2\r
+       cmnp    r0,r1,ror 2\r
+       cmnp    r0,r1,lsl r2\r
+       cmnp    r0,r1,lsr r2\r
+       cmnp    r0,r1,asr r2\r
+       cmnp    r0,r1,ror r2\r
+\r
+       cmpp    r0,1\r
+       cmpp    r0,1,2\r
+       cmpp    r0,r1\r
+       cmpp    r0,r1,rrx\r
+       cmpp    r0,r1,lsl 2\r
+       cmpp    r0,r1,lsr 2\r
+       cmpp    r0,r1,asr 2\r
+       cmpp    r0,r1,ror 2\r
+       cmpp    r0,r1,lsl r2\r
+       cmpp    r0,r1,lsr r2\r
+       cmpp    r0,r1,asr r2\r
+       cmpp    r0,r1,ror r2\r
+\r
+       teqp    r0,1\r
+       teqp    r0,1,2\r
+       teqp    r0,r1\r
+       teqp    r0,r1,rrx\r
+       teqp    r0,r1,lsl 2\r
+       teqp    r0,r1,lsr 2\r
+       teqp    r0,r1,asr 2\r
+       teqp    r0,r1,ror 2\r
+       teqp    r0,r1,lsl r2\r
+       teqp    r0,r1,lsr r2\r
+       teqp    r0,r1,asr r2\r
+       teqp    r0,r1,ror r2\r
+\r
+       tstp    r0,1\r
+       tstp    r0,1,2\r
+       tstp    r0,r1\r
+       tstp    r0,r1,rrx\r
+       tstp    r0,r1,lsl 2\r
+       tstp    r0,r1,lsr 2\r
+       tstp    r0,r1,asr 2\r
+       tstp    r0,r1,ror 2\r
+       tstp    r0,r1,lsl r2\r
+       tstp    r0,r1,lsr r2\r
+       tstp    r0,r1,asr r2\r
+       tstp    r0,r1,ror r2\r
+\r
+processor CPU32_V1\r
+\r
+       adc     r0,1\r
+       adc     r0,1,2\r
+       adc     r0,r1\r
+       adc     r0,r1,rrx\r
+       adc     r0,r1,lsl 2\r
+       adc     r0,r1,lsr 2\r
+       adc     r0,r1,asr 2\r
+       adc     r0,r1,ror 2\r
+       adc     r0,r1,lsl r2\r
+       adc     r0,r1,lsr r2\r
+       adc     r0,r1,asr r2\r
+       adc     r0,r1,ror r2\r
+       adc     r0,r1,2\r
+       adc     r0,r1,2,4\r
+       adc     r0,r1,r2\r
+       adc     r0,r1,r2,rrx\r
+       adc     r0,r1,r2,lsl 3\r
+       adc     r0,r1,r2,lsr 3\r
+       adc     r0,r1,r2,asr 3\r
+       adc     r0,r1,r2,ror 3\r
+       adc     r0,r1,r2,lsl r3\r
+       adc     r0,r1,r2,lsr r3\r
+       adc     r0,r1,r2,asr r3\r
+       adc     r0,r1,r2,ror r3\r
+\r
+       add     r0,1\r
+       add     r0,1,2\r
+       add     r0,r1\r
+       add     r0,r1,rrx\r
+       add     r0,r1,lsl 2\r
+       add     r0,r1,lsr 2\r
+       add     r0,r1,asr 2\r
+       add     r0,r1,ror 2\r
+       add     r0,r1,lsl r2\r
+       add     r0,r1,lsr r2\r
+       add     r0,r1,asr r2\r
+       add     r0,r1,ror r2\r
+       add     r0,r1,2\r
+       add     r0,r1,2,4\r
+       add     r0,r1,r2\r
+       add     r0,r1,r2,rrx\r
+       add     r0,r1,r2,lsl 3\r
+       add     r0,r1,r2,lsr 3\r
+       add     r0,r1,r2,asr 3\r
+       add     r0,r1,r2,ror 3\r
+       add     r0,r1,r2,lsl r3\r
+       add     r0,r1,r2,lsr r3\r
+       add     r0,r1,r2,asr r3\r
+       add     r0,r1,r2,ror r3\r
+\r
+       addw    r0,1\r
+       addw    r0,r1,2\r
+\r
+       label_adr:\r
+       adr     r0,label_adr\r
+\r
+       and     r0,1\r
+       and     r0,1,2\r
+       and     r0,r1\r
+       and     r0,r1,rrx\r
+       and     r0,r1,lsl 2\r
+       and     r0,r1,lsr 2\r
+       and     r0,r1,asr 2\r
+       and     r0,r1,ror 2\r
+       and     r0,r1,lsl r2\r
+       and     r0,r1,lsr r2\r
+       and     r0,r1,asr r2\r
+       and     r0,r1,ror r2\r
+       and     r0,r1,2\r
+       and     r0,r1,2,4\r
+       and     r0,r1,r2\r
+       and     r0,r1,r2,rrx\r
+       and     r0,r1,r2,lsl 3\r
+       and     r0,r1,r2,lsr 3\r
+       and     r0,r1,r2,asr 3\r
+       and     r0,r1,r2,ror 3\r
+       and     r0,r1,r2,lsl r3\r
+       and     r0,r1,r2,lsr r3\r
+       and     r0,r1,r2,asr r3\r
+       and     r0,r1,r2,ror r3\r
+\r
+       asr     r0,1\r
+       asr     r0,r1\r
+       asr     r0,r1,2\r
+       asr     r0,r1,r2\r
+\r
+       label_b:\r
+       b       label_b\r
+\r
+       bic     r0,1\r
+       bic     r0,1,2\r
+       bic     r0,r1\r
+       bic     r0,r1,rrx\r
+       bic     r0,r1,lsl 2\r
+       bic     r0,r1,lsr 2\r
+       bic     r0,r1,asr 2\r
+       bic     r0,r1,ror 2\r
+       bic     r0,r1,lsl r2\r
+       bic     r0,r1,lsr r2\r
+       bic     r0,r1,asr r2\r
+       bic     r0,r1,ror r2\r
+       bic     r0,r1,2\r
+       bic     r0,r1,2,4\r
+       bic     r0,r1,r2\r
+       bic     r0,r1,r2,rrx\r
+       bic     r0,r1,r2,lsl 3\r
+       bic     r0,r1,r2,lsr 3\r
+       bic     r0,r1,r2,asr 3\r
+       bic     r0,r1,r2,ror 3\r
+       bic     r0,r1,r2,lsl r3\r
+       bic     r0,r1,r2,lsr r3\r
+       bic     r0,r1,r2,asr r3\r
+       bic     r0,r1,r2,ror r3\r
+\r
+       label_bl:\r
+       bl      label_bl\r
+\r
+       cmn     r0,1\r
+       cmn     r0,1,2\r
+       cmn     r0,r1\r
+       cmn     r0,r1,rrx\r
+       cmn     r0,r1,lsl 2\r
+       cmn     r0,r1,lsr 2\r
+       cmn     r0,r1,asr 2\r
+       cmn     r0,r1,ror 2\r
+       cmn     r0,r1,lsl r2\r
+       cmn     r0,r1,lsr r2\r
+       cmn     r0,r1,asr r2\r
+       cmn     r0,r1,ror r2\r
+\r
+       cmp     r0,1\r
+       cmp     r0,1,2\r
+       cmp     r0,r1\r
+       cmp     r0,r1,rrx\r
+       cmp     r0,r1,lsl 2\r
+       cmp     r0,r1,lsr 2\r
+       cmp     r0,r1,asr 2\r
+       cmp     r0,r1,ror 2\r
+       cmp     r0,r1,lsl r2\r
+       cmp     r0,r1,lsr r2\r
+       cmp     r0,r1,asr r2\r
+       cmp     r0,r1,ror r2\r
+\r
+       cpy     r0,r1\r
+\r
+       eor     r0,1\r
+       eor     r0,1,2\r
+       eor     r0,r1\r
+       eor     r0,r1,rrx\r
+       eor     r0,r1,lsl 2\r
+       eor     r0,r1,lsr 2\r
+       eor     r0,r1,asr 2\r
+       eor     r0,r1,ror 2\r
+       eor     r0,r1,lsl r2\r
+       eor     r0,r1,lsr r2\r
+       eor     r0,r1,asr r2\r
+       eor     r0,r1,ror r2\r
+       eor     r0,r1,2\r
+       eor     r0,r1,2,4\r
+       eor     r0,r1,r2\r
+       eor     r0,r1,r2,rrx\r
+       eor     r0,r1,r2,lsl 3\r
+       eor     r0,r1,r2,lsr 3\r
+       eor     r0,r1,r2,asr 3\r
+       eor     r0,r1,r2,ror 3\r
+       eor     r0,r1,r2,lsl r3\r
+       eor     r0,r1,r2,lsr r3\r
+       eor     r0,r1,r2,asr r3\r
+       eor     r0,r1,r2,ror r3\r
+\r
+       ldm     r0,{r1}\r
+       ldm     r0,{r1,r2}\r
+       ldm     r0,{r1-r3}\r
+       ldm     r0,{r1-r3,r5}\r
+       ldm     r0,{r1}^\r
+       ldm     r0,{r1,r2}^\r
+       ldm     r0,{r1-r3}^\r
+       ldm     r0,{r1-r3,r5}^\r
+       ldm     r0!,{r1}\r
+       ldm     r0!,{r1,r2}\r
+       ldm     r0!,{r1-r3}\r
+       ldm     r0!,{r1-r3,r5}\r
+       ldm     r0!,{r15}^\r
+       ldm     r0!,{r1,r2,r15}^\r
+       ldm     r0!,{r1-r3,r15}^\r
+       ldm     r0!,{r1-r3,r15}^\r
+\r
+       ldmda   r0,{r1}\r
+       ldmda   r0,{r1,r2}\r
+       ldmda   r0,{r1-r3}\r
+       ldmda   r0,{r1-r3,r5}\r
+       ldmda   r0,{r1}^\r
+       ldmda   r0,{r1,r2}^\r
+       ldmda   r0,{r1-r3}^\r
+       ldmda   r0,{r1-r3,r5}^\r
+       ldmda   r0!,{r1}\r
+       ldmda   r0!,{r1,r2}\r
+       ldmda   r0!,{r1-r3}\r
+       ldmda   r0!,{r1-r3,r5}\r
+       ldmda   r0!,{r15}^\r
+       ldmda   r0!,{r1,r2,r15}^\r
+       ldmda   r0!,{r1-r3,r15}^\r
+       ldmda   r0!,{r1-r3,r15}^\r
+\r
+       ldmdb   r0,{r1}\r
+       ldmdb   r0,{r1,r2}\r
+       ldmdb   r0,{r1-r3}\r
+       ldmdb   r0,{r1-r3,r5}\r
+       ldmdb   r0,{r1}^\r
+       ldmdb   r0,{r1,r2}^\r
+       ldmdb   r0,{r1-r3}^\r
+       ldmdb   r0,{r1-r3,r5}^\r
+       ldmdb   r0!,{r1}\r
+       ldmdb   r0!,{r1,r2}\r
+       ldmdb   r0!,{r1-r3}\r
+       ldmdb   r0!,{r1-r3,r5}\r
+       ldmdb   r0!,{r15}^\r
+       ldmdb   r0!,{r1,r2,r15}^\r
+       ldmdb   r0!,{r1-r3,r15}^\r
+       ldmdb   r0!,{r1-r3,r15}^\r
+\r
+       ldmea   r0,{r1}\r
+       ldmea   r0,{r1,r2}\r
+       ldmea   r0,{r1-r3}\r
+       ldmea   r0,{r1-r3,r5}\r
+       ldmea   r0,{r1}^\r
+       ldmea   r0,{r1,r2}^\r
+       ldmea   r0,{r1-r3}^\r
+       ldmea   r0,{r1-r3,r5}^\r
+       ldmea   r0!,{r1}\r
+       ldmea   r0!,{r1,r2}\r
+       ldmea   r0!,{r1-r3}\r
+       ldmea   r0!,{r1-r3,r5}\r
+       ldmea   r0!,{r15}^\r
+       ldmea   r0!,{r1,r2,r15}^\r
+       ldmea   r0!,{r1-r3,r15}^\r
+       ldmea   r0!,{r1-r3,r15}^\r
+\r
+       ldmed   r0,{r1}\r
+       ldmed   r0,{r1,r2}\r
+       ldmed   r0,{r1-r3}\r
+       ldmed   r0,{r1-r3,r5}\r
+       ldmed   r0,{r1}^\r
+       ldmed   r0,{r1,r2}^\r
+       ldmed   r0,{r1-r3}^\r
+       ldmed   r0,{r1-r3,r5}^\r
+       ldmed   r0!,{r1}\r
+       ldmed   r0!,{r1,r2}\r
+       ldmed   r0!,{r1-r3}\r
+       ldmed   r0!,{r1-r3,r5}\r
+       ldmed   r0!,{r15}^\r
+       ldmed   r0!,{r1,r2,r15}^\r
+       ldmed   r0!,{r1-r3,r15}^\r
+       ldmed   r0!,{r1-r3,r15}^\r
+\r
+       ldmfa   r0,{r1}\r
+       ldmfa   r0,{r1,r2}\r
+       ldmfa   r0,{r1-r3}\r
+       ldmfa   r0,{r1-r3,r5}\r
+       ldmfa   r0,{r1}^\r
+       ldmfa   r0,{r1,r2}^\r
+       ldmfa   r0,{r1-r3}^\r
+       ldmfa   r0,{r1-r3,r5}^\r
+       ldmfa   r0!,{r1}\r
+       ldmfa   r0!,{r1,r2}\r
+       ldmfa   r0!,{r1-r3}\r
+       ldmfa   r0!,{r1-r3,r5}\r
+       ldmfa   r0!,{r15}^\r
+       ldmfa   r0!,{r1,r2,r15}^\r
+       ldmfa   r0!,{r1-r3,r15}^\r
+       ldmfa   r0!,{r1-r3,r15}^\r
+\r
+       ldmfd   r0,{r1}\r
+       ldmfd   r0,{r1,r2}\r
+       ldmfd   r0,{r1-r3}\r
+       ldmfd   r0,{r1-r3,r5}\r
+       ldmfd   r0,{r1}^\r
+       ldmfd   r0,{r1,r2}^\r
+       ldmfd   r0,{r1-r3}^\r
+       ldmfd   r0,{r1-r3,r5}^\r
+       ldmfd   r0!,{r1}\r
+       ldmfd   r0!,{r1,r2}\r
+       ldmfd   r0!,{r1-r3}\r
+       ldmfd   r0!,{r1-r3,r5}\r
+       ldmfd   r0!,{r15}^\r
+       ldmfd   r0!,{r1,r2,r15}^\r
+       ldmfd   r0!,{r1-r3,r15}^\r
+       ldmfd   r0!,{r1-r3,r15}^\r
+\r
+       ldmia   r0,{r1}\r
+       ldmia   r0,{r1,r2}\r
+       ldmia   r0,{r1-r3}\r
+       ldmia   r0,{r1-r3,r5}\r
+       ldmia   r0,{r1}^\r
+       ldmia   r0,{r1,r2}^\r
+       ldmia   r0,{r1-r3}^\r
+       ldmia   r0,{r1-r3,r5}^\r
+       ldmia   r0!,{r1}\r
+       ldmia   r0!,{r1,r2}\r
+       ldmia   r0!,{r1-r3}\r
+       ldmia   r0!,{r1-r3,r5}\r
+       ldmia   r0!,{r15}^\r
+       ldmia   r0!,{r1,r2,r15}^\r
+       ldmia   r0!,{r1-r3,r15}^\r
+       ldmia   r0!,{r1-r3,r15}^\r
+\r
+       ldmib   r0,{r1}\r
+       ldmib   r0,{r1,r2}\r
+       ldmib   r0,{r1-r3}\r
+       ldmib   r0,{r1-r3,r5}\r
+       ldmib   r0,{r1}^\r
+       ldmib   r0,{r1,r2}^\r
+       ldmib   r0,{r1-r3}^\r
+       ldmib   r0,{r1-r3,r5}^\r
+       ldmib   r0!,{r1}\r
+       ldmib   r0!,{r1,r2}\r
+       ldmib   r0!,{r1-r3}\r
+       ldmib   r0!,{r1-r3,r5}\r
+       ldmib   r0!,{r15}^\r
+       ldmib   r0!,{r1,r2,r15}^\r
+       ldmib   r0!,{r1-r3,r15}^\r
+       ldmib   r0!,{r1-r3,r15}^\r
+\r
+       label_ldr:\r
+       ldr     r0,[r1]\r
+       ldr     r0,[r1],+r2\r
+       ldr     r0,[r1],-r2\r
+       ldr     r0,[r1],-r2,lsl 3\r
+       ldr     r0,[r1],r2,lsr 3\r
+       ldr     r0,[r1],r2,asr 3\r
+       ldr     r0,[r1],r2,ror 3\r
+       ldr     r0,[r1],-r2,lsl 3\r
+       ldr     r0,[r1],-r2,lsr 3\r
+       ldr     r0,[r1],-r2,asr 3\r
+       ldr     r0,[r1],-r2,ror 3\r
+       ldr     r0,[r1],r2,rrx\r
+       ldr     r0,[r1],-r2,rrx\r
+       ldr     r0,[r1],2\r
+       ldr     r0,[r1,2]\r
+       ldr     r0,[r1,2]!\r
+       ldr     r0,[r1,r2]\r
+       ldr     r0,[r1,-r2]\r
+       ldr     r0,[r1,r2]!\r
+       ldr     r0,[r1,-r2]!\r
+       ldr     r0,[r1,r2,lsl 3]\r
+       ldr     r0,[r1,r2,lsr 3]\r
+       ldr     r0,[r1,r2,asr 3]\r
+       ldr     r0,[r1,r2,ror 3]\r
+       ldr     r0,[r1,-r2,lsl 3]\r
+       ldr     r0,[r1,-r2,lsr 3]\r
+       ldr     r0,[r1,-r2,asr 3]\r
+       ldr     r0,[r1,-r2,ror 3]\r
+       ldr     r0,[r1,r2,lsl 3]!\r
+       ldr     r0,[r1,r2,lsr 3]!\r
+       ldr     r0,[r1,r2,asr 3]!\r
+       ldr     r0,[r1,r2,ror 3]!\r
+       ldr     r0,[r1,-r2,lsl 3]!\r
+       ldr     r0,[r1,-r2,lsr 3]!\r
+       ldr     r0,[r1,-r2,asr 3]!\r
+       ldr     r0,[r1,-r2,ror 3]!\r
+       ldr     r0,[r1,r2,rrx]\r
+       ldr     r0,[r1,-r2,rrx]\r
+       ldr     r0,[r1,r2,rrx]!\r
+       ldr     r0,[r1,-r2,rrx]!\r
+       ldr     r0,[label_ldr]\r
+       ldr     r0,[expression.word]\r
+       ldr     r0,[expression.word]!\r
+\r
+       label_ldrb:\r
+       ldrb    r0,[r1]\r
+       ldrb    r0,[r1],r2\r
+       ldrb    r0,[r1],-r2\r
+       ldrb    r0,[r1],-r2,lsl 3\r
+       ldrb    r0,[r1],r2,lsr 3\r
+       ldrb    r0,[r1],r2,asr 3\r
+       ldrb    r0,[r1],r2,ror 3\r
+       ldrb    r0,[r1],-r2,lsl 3\r
+       ldrb    r0,[r1],-r2,lsr 3\r
+       ldrb    r0,[r1],-r2,asr 3\r
+       ldrb    r0,[r1],-r2,ror 3\r
+       ldrb    r0,[r1],r2,rrx\r
+       ldrb    r0,[r1],-r2,rrx\r
+       ldrb    r0,[r1],2\r
+       ldrb    r0,[r1,2]\r
+       ldrb    r0,[r1,2]!\r
+       ldrb    r0,[r1,r2]\r
+       ldrb    r0,[r1,-r2]\r
+       ldrb    r0,[r1,r2]!\r
+       ldrb    r0,[r1,-r2]!\r
+       ldrb    r0,[r1,r2,lsl 3]\r
+       ldrb    r0,[r1,r2,lsr 3]\r
+       ldrb    r0,[r1,r2,asr 3]\r
+       ldrb    r0,[r1,r2,ror 3]\r
+       ldrb    r0,[r1,-r2,lsl 3]\r
+       ldrb    r0,[r1,-r2,lsr 3]\r
+       ldrb    r0,[r1,-r2,asr 3]\r
+       ldrb    r0,[r1,-r2,ror 3]\r
+       ldrb    r0,[r1,r2,lsl 3]!\r
+       ldrb    r0,[r1,r2,lsr 3]!\r
+       ldrb    r0,[r1,r2,asr 3]!\r
+       ldrb    r0,[r1,r2,ror 3]!\r
+       ldrb    r0,[r1,-r2,lsl 3]!\r
+       ldrb    r0,[r1,-r2,lsr 3]!\r
+       ldrb    r0,[r1,-r2,asr 3]!\r
+       ldrb    r0,[r1,-r2,ror 3]!\r
+       ldrb    r0,[r1,r2,rrx]\r
+       ldrb    r0,[r1,-r2,rrx]\r
+       ldrb    r0,[r1,r2,rrx]!\r
+       ldrb    r0,[r1,-r2,rrx]!\r
+       ldrb    r0,[label_ldrb]\r
+       ldrb    r0,[expression.byte]\r
+       ldrb    r0,[expression.byte]!\r
+\r
+       ldrbt   r0,[r1]\r
+       ldrbt   r0,[r1],r2\r
+       ldrbt   r0,[r1],-r2\r
+       ldrbt   r0,[r1],r2,lsl 3\r
+       ldrbt   r0,[r1],r2,lsr 3\r
+       ldrbt   r0,[r1],r2,asr 3\r
+       ldrbt   r0,[r1],r2,ror 3\r
+       ldrbt   r0,[r1],-r2,lsl 3\r
+       ldrbt   r0,[r1],-r2,lsr 3\r
+       ldrbt   r0,[r1],-r2,asr 3\r
+       ldrbt   r0,[r1],-r2,ror 3\r
+       ldrbt   r0,[r1],r2,rrx\r
+       ldrbt   r0,[r1],-r2,rrx\r
+       ldrbt   r0,[r1],2\r
+\r
+       ldrt    r0,[r1]\r
+       ldrt    r0,[r1],r2\r
+       ldrt    r0,[r1],-r2\r
+       ldrt    r0,[r1],r2,lsl 3\r
+       ldrt    r0,[r1],r2,lsr 3\r
+       ldrt    r0,[r1],r2,asr 3\r
+       ldrt    r0,[r1],r2,ror 3\r
+       ldrt    r0,[r1],-r2,lsl 3\r
+       ldrt    r0,[r1],-r2,lsr 3\r
+       ldrt    r0,[r1],-r2,asr 3\r
+       ldrt    r0,[r1],-r2,ror 3\r
+       ldrt    r0,[r1],r2,rrx\r
+       ldrt    r0,[r1],-r2,rrx\r
+       ldrt    r0,[r1],2\r
+\r
+       lsl     r0,1\r
+       lsl     r0,r1\r
+       lsl     r0,r1,2\r
+       lsl     r0,r1,r2\r
+\r
+       lsr     r0,1\r
+       lsr     r0,r1\r
+       lsr     r0,r1,2\r
+       lsr     r0,r1,r2\r
+\r
+       mov     r0,1\r
+       mov     r0,1,2\r
+       mov     r0,r1\r
+       mov     r0,r1,rrx\r
+       mov     r0,r1,lsl 2\r
+       mov     r0,r1,lsr 2\r
+       mov     r0,r1,asr 2\r
+       mov     r0,r1,ror 2\r
+       mov     r0,r1,lsl r2\r
+       mov     r0,r1,lsr r2\r
+       mov     r0,r1,asr r2\r
+       mov     r0,r1,ror r2\r
+       mov     r0,expression.word\r
+\r
+       mvn     r0,1\r
+       mvn     r0,1,2\r
+       mvn     r0,r1\r
+       mvn     r0,r1,rrx\r
+       mvn     r0,r1,lsl 2\r
+       mvn     r0,r1,lsr 2\r
+       mvn     r0,r1,asr 2\r
+       mvn     r0,r1,ror 2\r
+       mvn     r0,r1,lsl r2\r
+       mvn     r0,r1,lsr r2\r
+       mvn     r0,r1,asr r2\r
+       mvn     r0,r1,ror r2\r
+\r
+       neg     r0\r
+       neg     r0,r1\r
+\r
+       nop\r
+\r
+       orr     r0,1\r
+       orr     r0,1,2\r
+       orr     r0,r1\r
+       orr     r0,r1,rrx\r
+       orr     r0,r1,lsl 2\r
+       orr     r0,r1,lsr 2\r
+       orr     r0,r1,asr 2\r
+       orr     r0,r1,ror 2\r
+       orr     r0,r1,lsl r2\r
+       orr     r0,r1,lsr r2\r
+       orr     r0,r1,asr r2\r
+       orr     r0,r1,ror r2\r
+       orr     r0,r1,2\r
+       orr     r0,r1,2,4\r
+       orr     r0,r1,r2\r
+       orr     r0,r1,r2,rrx\r
+       orr     r0,r1,r2,lsl 3\r
+       orr     r0,r1,r2,lsr 3\r
+       orr     r0,r1,r2,asr 3\r
+       orr     r0,r1,r2,ror 3\r
+       orr     r0,r1,r2,lsl r3\r
+       orr     r0,r1,r2,lsr r3\r
+       orr     r0,r1,r2,asr r3\r
+       orr     r0,r1,r2,ror r3\r
+\r
+       pop     {r0}\r
+       pop     {r0,r1}\r
+       pop     {r0-r2}\r
+       pop     {r0-r2,r4}\r
+\r
+       push    {r0}\r
+       push    {r0,r1}\r
+       push    {r0-r2}\r
+       push    {r0-r2,r4}\r
+\r
+       ror     r0,1\r
+       ror     r0,r1\r
+       ror     r0,r1,2\r
+       ror     r0,r1,r2\r
+\r
+       rrx     r0\r
+       rrx     r0,r1\r
+\r
+       rsb     r0,1\r
+       rsb     r0,1,2\r
+       rsb     r0,r1\r
+       rsb     r0,r1,rrx\r
+       rsb     r0,r1,lsl 2\r
+       rsb     r0,r1,lsr 2\r
+       rsb     r0,r1,asr 2\r
+       rsb     r0,r1,ror 2\r
+       rsb     r0,r1,lsl r2\r
+       rsb     r0,r1,lsr r2\r
+       rsb     r0,r1,asr r2\r
+       rsb     r0,r1,ror r2\r
+       rsb     r0,r1,2\r
+       rsb     r0,r1,2,4\r
+       rsb     r0,r1,r2\r
+       rsb     r0,r1,r2,rrx\r
+       rsb     r0,r1,r2,lsl 3\r
+       rsb     r0,r1,r2,lsr 3\r
+       rsb     r0,r1,r2,asr 3\r
+       rsb     r0,r1,r2,ror 3\r
+       rsb     r0,r1,r2,lsl r3\r
+       rsb     r0,r1,r2,lsr r3\r
+       rsb     r0,r1,r2,asr r3\r
+       rsb     r0,r1,r2,ror r3\r
+\r
+       rsc     r0,1\r
+       rsc     r0,1,2\r
+       rsc     r0,r1\r
+       rsc     r0,r1,rrx\r
+       rsc     r0,r1,lsl 2\r
+       rsc     r0,r1,lsr 2\r
+       rsc     r0,r1,asr 2\r
+       rsc     r0,r1,ror 2\r
+       rsc     r0,r1,lsl r2\r
+       rsc     r0,r1,lsr r2\r
+       rsc     r0,r1,asr r2\r
+       rsc     r0,r1,ror r2\r
+       rsc     r0,r1,2\r
+       rsc     r0,r1,2,4\r
+       rsc     r0,r1,r2\r
+       rsc     r0,r1,r2,rrx\r
+       rsc     r0,r1,r2,lsl 3\r
+       rsc     r0,r1,r2,lsr 3\r
+       rsc     r0,r1,r2,asr 3\r
+       rsc     r0,r1,r2,ror 3\r
+       rsc     r0,r1,r2,lsl r3\r
+       rsc     r0,r1,r2,lsr r3\r
+       rsc     r0,r1,r2,asr r3\r
+       rsc     r0,r1,r2,ror r3\r
+\r
+       sbc     r0,1\r
+       sbc     r0,1,2\r
+       sbc     r0,r1\r
+       sbc     r0,r1,rrx\r
+       sbc     r0,r1,lsl 2\r
+       sbc     r0,r1,lsr 2\r
+       sbc     r0,r1,asr 2\r
+       sbc     r0,r1,ror 2\r
+       sbc     r0,r1,lsl r2\r
+       sbc     r0,r1,lsr r2\r
+       sbc     r0,r1,asr r2\r
+       sbc     r0,r1,ror r2\r
+       sbc     r0,r1,2\r
+       sbc     r0,r1,2,4\r
+       sbc     r0,r1,r2\r
+       sbc     r0,r1,r2,rrx\r
+       sbc     r0,r1,r2,lsl 3\r
+       sbc     r0,r1,r2,lsr 3\r
+       sbc     r0,r1,r2,asr 3\r
+       sbc     r0,r1,r2,ror 3\r
+       sbc     r0,r1,r2,lsl r3\r
+       sbc     r0,r1,r2,lsr r3\r
+       sbc     r0,r1,r2,asr r3\r
+       sbc     r0,r1,r2,ror r3\r
+\r
+       stm     r0,{r1}\r
+       stm     r0,{r1,r2}\r
+       stm     r0,{r1-r3}\r
+       stm     r0,{r1-r3,r5}\r
+       stm     r0,{r1}^\r
+       stm     r0,{r1,r2}^\r
+       stm     r0,{r1-r3}^\r
+       stm     r0,{r1-r3,r5}^\r
+       stm     r0!,{r1}\r
+       stm     r0!,{r1,r2}\r
+       stm     r0!,{r1-r3}\r
+       stm     r0!,{r1-r3,r5}\r
+\r
+       stmda   r0,{r1}\r
+       stmda   r0,{r1,r2}\r
+       stmda   r0,{r1-r3}\r
+       stmda   r0,{r1-r3,r5}\r
+       stmda   r0,{r1}^\r
+       stmda   r0,{r1,r2}^\r
+       stmda   r0,{r1-r3}^\r
+       stmda   r0,{r1-r3,r5}^\r
+       stmda   r0!,{r1}\r
+       stmda   r0!,{r1,r2}\r
+       stmda   r0!,{r1-r3}\r
+       stmda   r0!,{r1-r3,r5}\r
+\r
+       stmdb   r0,{r1}\r
+       stmdb   r0,{r1,r2}\r
+       stmdb   r0,{r1-r3}\r
+       stmdb   r0,{r1-r3,r5}\r
+       stmdb   r0,{r1}^\r
+       stmdb   r0,{r1,r2}^\r
+       stmdb   r0,{r1-r3}^\r
+       stmdb   r0,{r1-r3,r5}^\r
+       stmdb   r0!,{r1}\r
+       stmdb   r0!,{r1,r2}\r
+       stmdb   r0!,{r1-r3}\r
+       stmdb   r0!,{r1-r3,r5}\r
+\r
+       stmea   r0,{r1}\r
+       stmea   r0,{r1,r2}\r
+       stmea   r0,{r1-r3}\r
+       stmea   r0,{r1-r3,r5}\r
+       stmea   r0,{r1}^\r
+       stmea   r0,{r1,r2}^\r
+       stmea   r0,{r1-r3}^\r
+       stmea   r0,{r1-r3,r5}^\r
+       stmea   r0!,{r1}\r
+       stmea   r0!,{r1,r2}\r
+       stmea   r0!,{r1-r3}\r
+       stmea   r0!,{r1-r3,r5}\r
+\r
+       stmed   r0,{r1}\r
+       stmed   r0,{r1,r2}\r
+       stmed   r0,{r1-r3}\r
+       stmed   r0,{r1-r3,r5}\r
+       stmed   r0,{r1}^\r
+       stmed   r0,{r1,r2}^\r
+       stmed   r0,{r1-r3}^\r
+       stmed   r0,{r1-r3,r5}^\r
+       stmed   r0!,{r1}\r
+       stmed   r0!,{r1,r2}\r
+       stmed   r0!,{r1-r3}\r
+       stmed   r0!,{r1-r3,r5}\r
+\r
+       stmfa   r0,{r1}\r
+       stmfa   r0,{r1,r2}\r
+       stmfa   r0,{r1-r3}\r
+       stmfa   r0,{r1-r3,r5}\r
+       stmfa   r0,{r1}^\r
+       stmfa   r0,{r1,r2}^\r
+       stmfa   r0,{r1-r3}^\r
+       stmfa   r0,{r1-r3,r5}^\r
+       stmfa   r0!,{r1}\r
+       stmfa   r0!,{r1,r2}\r
+       stmfa   r0!,{r1-r3}\r
+       stmfa   r0!,{r1-r3,r5}\r
+\r
+       stmfd   r0,{r1}\r
+       stmfd   r0,{r1,r2}\r
+       stmfd   r0,{r1-r3}\r
+       stmfd   r0,{r1-r3,r5}\r
+       stmfd   r0,{r1}^\r
+       stmfd   r0,{r1,r2}^\r
+       stmfd   r0,{r1-r3}^\r
+       stmfd   r0,{r1-r3,r5}^\r
+       stmfd   r0!,{r1}\r
+       stmfd   r0!,{r1,r2}\r
+       stmfd   r0!,{r1-r3}\r
+       stmfd   r0!,{r1-r3,r5}\r
+\r
+       stmia   r0,{r1}\r
+       stmia   r0,{r1,r2}\r
+       stmia   r0,{r1-r3}\r
+       stmia   r0,{r1-r3,r5}\r
+       stmia   r0,{r1}^\r
+       stmia   r0,{r1,r2}^\r
+       stmia   r0,{r1-r3}^\r
+       stmia   r0,{r1-r3,r5}^\r
+       stmia   r0!,{r1}\r
+       stmia   r0!,{r1,r2}\r
+       stmia   r0!,{r1-r3}\r
+       stmia   r0!,{r1-r3,r5}\r
+\r
+       stmib   r0,{r1}\r
+       stmib   r0,{r1,r2}\r
+       stmib   r0,{r1-r3}\r
+       stmib   r0,{r1-r3,r5}\r
+       stmib   r0,{r1}^\r
+       stmib   r0,{r1,r2}^\r
+       stmib   r0,{r1-r3}^\r
+       stmib   r0,{r1-r3,r5}^\r
+       stmib   r0!,{r1}\r
+       stmib   r0!,{r1,r2}\r
+       stmib   r0!,{r1-r3}\r
+       stmib   r0!,{r1-r3,r5}\r
+\r
+       label_str:\r
+       str     r0,[r1]\r
+       str     r0,[r1],r2\r
+       str     r0,[r1],-r2\r
+       str     r0,[r1],-r2,lsl 3\r
+       str     r0,[r1],r2,lsr 3\r
+       str     r0,[r1],r2,asr 3\r
+       str     r0,[r1],r2,ror 3\r
+       str     r0,[r1],-r2,lsl 3\r
+       str     r0,[r1],-r2,lsr 3\r
+       str     r0,[r1],-r2,asr 3\r
+       str     r0,[r1],-r2,ror 3\r
+       str     r0,[r1],r2,rrx\r
+       str     r0,[r1],-r2,rrx\r
+       str     r0,[r1],2\r
+       str     r0,[r1,2]\r
+       str     r0,[r1,2]!\r
+       str     r0,[r1,r2]\r
+       str     r0,[r1,-r2]\r
+       str     r0,[r1,r2]!\r
+       str     r0,[r1,-r2]!\r
+       str     r0,[r1,r2,lsl 3]\r
+       str     r0,[r1,r2,lsr 3]\r
+       str     r0,[r1,r2,asr 3]\r
+       str     r0,[r1,r2,ror 3]\r
+       str     r0,[r1,-r2,lsl 3]\r
+       str     r0,[r1,-r2,lsr 3]\r
+       str     r0,[r1,-r2,asr 3]\r
+       str     r0,[r1,-r2,ror 3]\r
+       str     r0,[r1,r2,lsl 3]!\r
+       str     r0,[r1,r2,lsr 3]!\r
+       str     r0,[r1,r2,asr 3]!\r
+       str     r0,[r1,r2,ror 3]!\r
+       str     r0,[r1,-r2,lsl 3]!\r
+       str     r0,[r1,-r2,lsr 3]!\r
+       str     r0,[r1,-r2,asr 3]!\r
+       str     r0,[r1,-r2,ror 3]!\r
+       str     r0,[r1,r2,rrx]\r
+       str     r0,[r1,-r2,rrx]\r
+       str     r0,[r1,r2,rrx]!\r
+       str     r0,[r1,-r2,rrx]!\r
+       str     r0,[label_str]\r
+       str     r0,[expression.word]\r
+       str     r0,[expression.word]!\r
+\r
+       label_strb:\r
+       strb    r0,[r1]\r
+       strb    r0,[r1],r2\r
+       strb    r0,[r1],-r2\r
+       strb    r0,[r1],-r2,lsl 3\r
+       strb    r0,[r1],r2,lsr 3\r
+       strb    r0,[r1],r2,asr 3\r
+       strb    r0,[r1],r2,ror 3\r
+       strb    r0,[r1],-r2,lsl 3\r
+       strb    r0,[r1],-r2,lsr 3\r
+       strb    r0,[r1],-r2,asr 3\r
+       strb    r0,[r1],-r2,ror 3\r
+       strb    r0,[r1],r2,rrx\r
+       strb    r0,[r1],-r2,rrx\r
+       strb    r0,[r1],2\r
+       strb    r0,[r1,2]\r
+       strb    r0,[r1,2]!\r
+       strb    r0,[r1,r2]\r
+       strb    r0,[r1,-r2]\r
+       strb    r0,[r1,r2]!\r
+       strb    r0,[r1,-r2]!\r
+       strb    r0,[r1,r2,lsl 3]\r
+       strb    r0,[r1,r2,lsr 3]\r
+       strb    r0,[r1,r2,asr 3]\r
+       strb    r0,[r1,r2,ror 3]\r
+       strb    r0,[r1,-r2,lsl 3]\r
+       strb    r0,[r1,-r2,lsr 3]\r
+       strb    r0,[r1,-r2,asr 3]\r
+       strb    r0,[r1,-r2,ror 3]\r
+       strb    r0,[r1,r2,lsl 3]!\r
+       strb    r0,[r1,r2,lsr 3]!\r
+       strb    r0,[r1,r2,asr 3]!\r
+       strb    r0,[r1,r2,ror 3]!\r
+       strb    r0,[r1,-r2,lsl 3]!\r
+       strb    r0,[r1,-r2,lsr 3]!\r
+       strb    r0,[r1,-r2,asr 3]!\r
+       strb    r0,[r1,-r2,ror 3]!\r
+       strb    r0,[r1,r2,rrx]\r
+       strb    r0,[r1,-r2,rrx]\r
+       strb    r0,[r1,r2,rrx]!\r
+       strb    r0,[r1,-r2,rrx]!\r
+       strb    r0,[label_strb]\r
+       strb    r0,[expression.byte]\r
+       strb    r0,[expression.byte]!\r
+\r
+       strbt   r0,[r1]\r
+       strbt   r0,[r1],r2\r
+       strbt   r0,[r1],-r2\r
+       strbt   r0,[r1],r2,lsl 3\r
+       strbt   r0,[r1],r2,lsr 3\r
+       strbt   r0,[r1],r2,asr 3\r
+       strbt   r0,[r1],r2,ror 3\r
+       strbt   r0,[r1],-r2,lsl 3\r
+       strbt   r0,[r1],-r2,lsr 3\r
+       strbt   r0,[r1],-r2,asr 3\r
+       strbt   r0,[r1],-r2,ror 3\r
+       strbt   r0,[r1],r2,rrx\r
+       strbt   r0,[r1],-r2,rrx\r
+       strbt   r0,[r1],2\r
+\r
+       strt    r0,[r1]\r
+       strt    r0,[r1],r2\r
+       strt    r0,[r1],-r2\r
+       strt    r0,[r1],r2,lsl 3\r
+       strt    r0,[r1],r2,lsr 3\r
+       strt    r0,[r1],r2,asr 3\r
+       strt    r0,[r1],r2,ror 3\r
+       strt    r0,[r1],-r2,lsl 3\r
+       strt    r0,[r1],-r2,lsr 3\r
+       strt    r0,[r1],-r2,asr 3\r
+       strt    r0,[r1],-r2,ror 3\r
+       strt    r0,[r1],r2,rrx\r
+       strt    r0,[r1],-r2,rrx\r
+       strt    r0,[r1],2\r
+\r
+       sub     r0,1\r
+       sub     r0,1,2\r
+       sub     r0,r1\r
+       sub     r0,r1,rrx\r
+       sub     r0,r1,lsl 2\r
+       sub     r0,r1,lsr 2\r
+       sub     r0,r1,asr 2\r
+       sub     r0,r1,ror 2\r
+       sub     r0,r1,lsl r2\r
+       sub     r0,r1,lsr r2\r
+       sub     r0,r1,asr r2\r
+       sub     r0,r1,ror r2\r
+       sub     r0,r1,2\r
+       sub     r0,r1,2,4\r
+       sub     r0,r1,r2\r
+       sub     r0,r1,r2,rrx\r
+       sub     r0,r1,r2,lsl 3\r
+       sub     r0,r1,r2,lsr 3\r
+       sub     r0,r1,r2,asr 3\r
+       sub     r0,r1,r2,ror 3\r
+       sub     r0,r1,r2,lsl r3\r
+       sub     r0,r1,r2,lsr r3\r
+       sub     r0,r1,r2,asr r3\r
+       sub     r0,r1,r2,ror r3\r
+\r
+       subw    r0,1\r
+       subw    r0,r1,2\r
+\r
+       svc     1\r
+\r
+       swi     1\r
+\r
+       teq     r0,1\r
+       teq     r0,1,2\r
+       teq     r0,r1\r
+       teq     r0,r1,rrx\r
+       teq     r0,r1,lsl 2\r
+       teq     r0,r1,lsr 2\r
+       teq     r0,r1,asr 2\r
+       teq     r0,r1,ror 2\r
+       teq     r0,r1,lsl r2\r
+       teq     r0,r1,lsr r2\r
+       teq     r0,r1,asr r2\r
+       teq     r0,r1,ror r2\r
+\r
+       tst     r0,1\r
+       tst     r0,1,2\r
+       tst     r0,r1\r
+       tst     r0,r1,rrx\r
+       tst     r0,r1,lsl 2\r
+       tst     r0,r1,lsr 2\r
+       tst     r0,r1,asr 2\r
+       tst     r0,r1,ror 2\r
+       tst     r0,r1,lsl r2\r
+       tst     r0,r1,lsr r2\r
+       tst     r0,r1,asr r2\r
+       tst     r0,r1,ror r2\r
+\r
+processor CPU32_V2\r
+\r
+       cdp     p9,1,c2,c3,c4\r
+       cdp     p9,1,c2,c3,c4,5\r
+\r
+       label_ldc:\r
+       ldc     p9,c1,[r2]\r
+       ldc     p9,c1,[r2],4\r
+       ldc     p9,c1,[r2],{4}\r
+       ldc     p9,c1,[r2,4]\r
+       ldc     p9,c1,[r2,4]!\r
+       ldc     p9,c1,[label_ldc]\r
+       ldc     p9,c1,[expression.word]\r
+       ldc     p9,c1,[expression.word]!\r
+\r
+       label_ldcl:\r
+       ldcl    p9,c1,[r2]\r
+       ldcl    p9,c1,[r2],4\r
+       ldcl    p9,c1,[r2],{4}\r
+       ldcl    p9,c1,[r2,4]\r
+       ldcl    p9,c1,[r2,4]!\r
+       ldcl    p9,c1,[label_ldcl]\r
+       ldcl    p9,c1,[expression.word]\r
+       ldcl    p9,c1,[expression.word]!\r
+\r
+       mcr     p9,1,r2,c3,c4\r
+       mcr     p9,1,r2,c3,c4,5\r
+\r
+       mla     r0,r1,r2,r3\r
+\r
+       mrc     p9,1,r2,c3,c4\r
+       mrc     p9,1,r15,c3,c4,5\r
+\r
+       mul     r0,r1\r
+       mul     r0,r1,r2\r
+\r
+       label_stc:\r
+       stc     p9,c1,[r2]\r
+       stc     p9,c1,[r2],4\r
+       stc     p9,c1,[r2],{4}\r
+       stc     p9,c1,[r2,4]\r
+       stc     p9,c1,[r2,4]!\r
+       stc     p9,c1,[label_stc]\r
+       stc     p9,c1,[expression.word]\r
+       stc     p9,c1,[expression.word]!\r
+\r
+       label_stcl:\r
+       stcl    p9,c1,[r2]\r
+       stcl    p9,c1,[r2],4\r
+       stcl    p9,c1,[r2],{4}\r
+       stcl    p9,c1,[r2,4]\r
+       stcl    p9,c1,[r2,4]!\r
+       stcl    p9,c1,[label_stcl]\r
+       stcl    p9,c1,[expression.word]\r
+       stcl    p9,c1,[expression.word]!\r
+\r
+processor CPU32_A\r
+\r
+       swp     r0,r1,[r2]\r
+       swpb    r0,r1,[r2]\r
+\r
+processor CPU32_V3\r
+\r
+       mrs     r0,apsr\r
+       mrs     r0,cpsr\r
+       mrs     r0,spsr\r
+\r
+       msr     cpsr,r1\r
+       msr     cpsr_fsxc,r1\r
+       msr     cpsr,1\r
+       msr     cpsr_fsxc,1\r
+\r
+processor CPU32_M\r
+\r
+       smlal   r0,r1,r2,r3\r
+\r
+       smull   r0,r1,r2,r3\r
+\r
+       umlal   r0,r1,r2,r3\r
+\r
+       umull   r0,r1,r2,r3\r
+\r
+processor CPU32_V4\r
+\r
+       label_ldrh:\r
+       ldrh    r0,[r1]\r
+       ldrh    r0,[r1],r2\r
+       ldrh    r0,[r1],-r2\r
+       ldrh    r0,[r1],2\r
+       ldrh    r0,[r1,2]\r
+       ldrh    r0,[r1,2]!\r
+       ldrh    r0,[r1,r2]\r
+       ldrh    r0,[r1,-r2]\r
+       ldrh    r0,[r1,r2]!\r
+       ldrh    r0,[r1,-r2]!\r
+       ldrh    r0,[label_ldrh]\r
+       ldrh    r0,[expression.hword]\r
+       ldrh    r0,[expression.hword]!\r
+\r
+       label_ldrsb:\r
+       ldrsb   r0,[r1]\r
+       ldrsb   r0,[r1],r2\r
+       ldrsb   r0,[r1],-r2\r
+       ldrsb   r0,[r1],2\r
+       ldrsb   r0,[r1,2]\r
+       ldrsb   r0,[r1,2]!\r
+       ldrsb   r0,[r1,r2]\r
+       ldrsb   r0,[r1,-r2]\r
+       ldrsb   r0,[r1,r2]!\r
+       ldrsb   r0,[r1,-r2]!\r
+       ldrsb   r0,[label_ldrsb]\r
+       ldrsb   r0,[expression.byte]\r
+       ldrsb   r0,[expression.byte]!\r
+\r
+       label_ldrsh:\r
+       ldrsh   r0,[r1]\r
+       ldrsh   r0,[r1],r2\r
+       ldrsh   r0,[r1],-r2\r
+       ldrsh   r0,[r1],2\r
+       ldrsh   r0,[r1,2]\r
+       ldrsh   r0,[r1,2]!\r
+       ldrsh   r0,[r1,r2]\r
+       ldrsh   r0,[r1,-r2]\r
+       ldrsh   r0,[r1,r2]!\r
+       ldrsh   r0,[r1,-r2]!\r
+       ldrsh   r0,[label_ldrsh]\r
+       ldrsh   r0,[expression.hword]\r
+       ldrsh   r0,[expression.hword]!\r
+\r
+       label_strh:\r
+       strh    r0,[r1]\r
+       strh    r0,[r1],r2\r
+       strh    r0,[r1],-r2\r
+       strh    r0,[r1],2\r
+       strh    r0,[r1,2]\r
+       strh    r0,[r1,2]!\r
+       strh    r0,[r1,r2]\r
+       strh    r0,[r1,-r2]\r
+       strh    r0,[r1,r2]!\r
+       strh    r0,[r1,-r2]!\r
+       strh    r0,[label_strh]\r
+       strh    r0,[expression.hword]\r
+       strh    r0,[expression.hword]!\r
+\r
+processor CPU32_V4T\r
+\r
+       bx      r0\r
+\r
+processor CPU32_V5\r
+\r
+       label_blx:\r
+       blx     label_blx\r
+       blx     r0\r
+\r
+       bkpt    0\r
+\r
+       cdp2    p9,1,c2,c3,c4\r
+       cdp2    p9,1,c2,c3,c4,5\r
+\r
+       clz     r0,r1\r
+\r
+       label_ldc2:\r
+       ldc2    p9,c1,[r2]\r
+       ldc2    p9,c1,[r2],4\r
+       ldc2    p9,c1,[r2],{4}\r
+       ldc2    p9,c1,[r2,4]\r
+       ldc2    p9,c1,[r2,4]!\r
+       ldc2    p9,c1,[label_ldc2]\r
+       ldc2    p9,c1,[expression.word]\r
+       ldc2    p9,c1,[expression.word]!\r
+\r
+       label_ldc2l:\r
+       ldc2l   p9,c1,[r2]\r
+       ldc2l   p9,c1,[r2],4\r
+       ldc2l   p9,c1,[r2],{4}\r
+       ldc2l   p9,c1,[r2,4]\r
+       ldc2l   p9,c1,[r2,4]!\r
+       ldc2l   p9,c1,[label_ldc2l]\r
+       ldc2l   p9,c1,[expression.word]\r
+       ldc2l   p9,c1,[expression.word]!\r
+\r
+       mcr2    p9,1,r2,c3,c4\r
+       mcr2    p9,1,r2,c3,c4,5\r
+\r
+       mrc2    p9,1,r2,c3,c4\r
+       mrc2    p9,1,r15,c3,c4,5\r
+\r
+       label_stc2:\r
+       stc2    p9,c1,[r2]\r
+       stc2    p9,c1,[r2],4\r
+       stc2    p9,c1,[r2],{4}\r
+       stc2    p9,c1,[r2,4]\r
+       stc2    p9,c1,[r2,4]!\r
+       stc2    p9,c1,[label_stc2]\r
+       stc2    p9,c1,[expression.word]\r
+       stc2    p9,c1,[expression.word]!\r
+\r
+       label_stc2l:\r
+       stc2l   p9,c1,[r2]\r
+       stc2l   p9,c1,[r2],4\r
+       stc2l   p9,c1,[r2],{4}\r
+       stc2l   p9,c1,[r2,4]\r
+       stc2l   p9,c1,[r2,4]!\r
+       stc2l   p9,c1,[label_stc2l]\r
+       stc2l   p9,c1,[expression.word]\r
+       stc2l   p9,c1,[expression.word]!\r
+\r
+processor CPU32_E\r
+\r
+       qadd    r0,r1\r
+       qadd    r0,r1,r2\r
+\r
+       qdadd   r0,r1\r
+       qdadd   r0,r1,r2\r
+\r
+       qdsub   r0,r1\r
+       qdsub   r0,r1,r2\r
+\r
+       qsub    r0,r1\r
+       qsub    r0,r1,r2\r
+\r
+       smlabb  r0,r1,r2,r3\r
+\r
+       smlabt  r0,r1,r2,r3\r
+\r
+       smlalbb r0,r1,r2,r3\r
+\r
+       smlalbt r0,r1,r2,r3\r
+\r
+       smlaltb r0,r1,r2,r3\r
+\r
+       smlaltt r0,r1,r2,r3\r
+\r
+       smlatb  r0,r1,r2,r3\r
+\r
+       smlatt  r0,r1,r2,r3\r
+\r
+       smlawb  r0,r1,r2,r3\r
+\r
+       smlawt  r0,r1,r2,r3\r
+\r
+       smulbb  r0,r1\r
+       smulbb  r0,r1,r2\r
+\r
+       smulbt  r0,r1\r
+       smulbt  r0,r1,r2\r
+\r
+       smultb  r0,r1\r
+       smultb  r0,r1,r2\r
+\r
+       smultt  r0,r1\r
+       smultt  r0,r1,r2\r
+\r
+       smulwb  r0,r1\r
+       smulwb  r0,r1,r2\r
+\r
+       smulwt  r0,r1\r
+       smulwt  r0,r1,r2\r
+\r
+processor CPU32_P\r
+\r
+       label_ldrd:\r
+       ldrd    r0,[r2]\r
+       ldrd    r0,[r2],r3\r
+       ldrd    r0,[r2],-r3\r
+       ldrd    r0,[r2],3\r
+       ldrd    r0,[r2,3]\r
+       ldrd    r0,[r2,3]!\r
+       ldrd    r0,[r2,r3]\r
+       ldrd    r0,[r2,-r3]\r
+       ldrd    r0,[r2,r3]!\r
+       ldrd    r0,[r2,-r3]!\r
+       ldrd    r0,[label_ldrd]\r
+       ldrd    r0,[expression.dword]\r
+       ldrd    r0,[expression.dword]!\r
+       ldrd    r0,r1,[r2]\r
+       ldrd    r0,r1,[r2],r3\r
+       ldrd    r0,r1,[r2],-r3\r
+       ldrd    r0,r1,[r2],3\r
+       ldrd    r0,r1,[r2,3]\r
+       ldrd    r0,r1,[r2,3]!\r
+       ldrd    r0,r1,[r2,r3]\r
+       ldrd    r0,r1,[r2,-r3]\r
+       ldrd    r0,r1,[r2,r3]!\r
+       ldrd    r0,r1,[r2,-r3]!\r
+       ldrd    r0,r1,[label_ldrd]\r
+       ldrd    r0,r1,[expression.dword]\r
+       ldrd    r0,r1,[expression.dword]!\r
+\r
+       mcrr    p9,1,r2,r3,c4\r
+\r
+       mrrc    p9,1,r2,r3,c4\r
+\r
+       label_pld:\r
+       pld     [r0]\r
+       pld     [r0,1]\r
+       pld     [r0,r1]\r
+       pld     [r0,-r1]\r
+       pld     [r0,r1,lsl 2]\r
+       pld     [r0,r1,lsr 2]\r
+       pld     [r0,r1,asr 2]\r
+       pld     [r0,r1,ror 2]\r
+       pld     [r0,-r1,lsl 2]\r
+       pld     [r0,-r1,lsr 2]\r
+       pld     [r0,-r1,asr 2]\r
+       pld     [r0,-r1,ror 2]\r
+       pld     [r0,r1,rrx]\r
+       pld     [r0,-r1,rrx]\r
+       pld     [label_pld]\r
+       pld     [expression.byte]\r
+\r
+       label_strd:\r
+       strd    r0,[r2]\r
+       strd    r0,[r2],r3\r
+       strd    r0,[r2],-r3\r
+       strd    r0,[r2],3\r
+       strd    r0,[r2,3]\r
+       strd    r0,[r2,3]!\r
+       strd    r0,[r2,r3]\r
+       strd    r0,[r2,-r3]\r
+       strd    r0,[r2,r3]!\r
+       strd    r0,[r2,-r3]!\r
+       strd    r0,[label_strd]\r
+       strd    r0,[expression.dword]\r
+       strd    r0,[expression.dword]!\r
+       strd    r0,r1,[r2]\r
+       strd    r0,r1,[r2],r3\r
+       strd    r0,r1,[r2],-r3\r
+       strd    r0,r1,[r2],3\r
+       strd    r0,r1,[r2,3]\r
+       strd    r0,r1,[r2,3]!\r
+       strd    r0,r1,[r2,r3]\r
+       strd    r0,r1,[r2,-r3]\r
+       strd    r0,r1,[r2,r3]!\r
+       strd    r0,r1,[r2,-r3]!\r
+       strd    r0,r1,[label_strd]\r
+       strd    r0,r1,[expression.dword]\r
+       strd    r0,r1,[expression.dword]!\r
+\r
+processor CPU32_J\r
+\r
+       bxj     r0\r
+\r
+processor CPU32_V6\r
+\r
+       cps     0\r
+\r
+       cpsid   iflags_a\r
+       cpsid   iflags_a,1\r
+\r
+       cpsie   iflags_a\r
+       cpsie   iflags_a,1\r
+\r
+       ldrex   r0,[r1]\r
+       ldrex   r0,[r1,0]\r
+\r
+       mcrr2   p9,1,r2,r3,c4\r
+\r
+       mrrc2   p9,1,r2,r3,c4\r
+\r
+       pkhbt   r0,r1\r
+       pkhbt   r0,r1,lsl 3\r
+       pkhbt   r0,r1,r2\r
+       pkhbt   r0,r1,r2,lsl 3\r
+\r
+       pkhtb   r0,r1\r
+       pkhtb   r0,r1,asr 3\r
+       pkhtb   r0,r1,r2\r
+       pkhtb   r0,r1,r2,asr 3\r
+\r
+       qadd16  r0,r1\r
+       qadd16  r0,r1,r2\r
+\r
+       qadd8   r0,r1\r
+       qadd8   r0,r1,r2\r
+\r
+       qaddsubx        r0,r1\r
+       qaddsubx        r0,r1,r2\r
+\r
+       qasx    r0,r1\r
+       qasx    r0,r1,r2\r
+\r
+       qsax    r0,r1\r
+       qsax    r0,r1,r2\r
+\r
+       qsub16  r0,r1\r
+       qsub16  r0,r1,r2\r
+\r
+       qsub8   r0,r1\r
+       qsub8   r0,r1,r2\r
+\r
+       qsubaddx        r0,r1\r
+       qsubaddx        r0,r1,r2\r
+\r
+       rev     r0,r1\r
+\r
+       rev16   r0,r1\r
+\r
+       revsh   r0,r1\r
+\r
+       rfe     r0\r
+       rfe     r0!\r
+\r
+       rfeda   r0\r
+       rfeda   r0!\r
+\r
+       rfedb   r0\r
+       rfedb   r0!\r
+\r
+       rfeea   r0\r
+       rfeea   r0!\r
+\r
+       rfeed   r0\r
+       rfeed   r0!\r
+\r
+       rfefa   r0\r
+       rfefa   r0!\r
+\r
+       rfefd   r0\r
+       rfefd   r0!\r
+\r
+       rfeia   r0\r
+       rfeia   r0!\r
+\r
+       rfeib   r0\r
+       rfeib   r0!\r
+\r
+       sadd16  r0,r1\r
+       sadd16  r0,r1,r2\r
+\r
+       sadd8   r0,r1\r
+       sadd8   r0,r1,r2\r
+\r
+       saddsubx        r0,r1\r
+       saddsubx        r0,r1,r2\r
+\r
+       sasx    r0,r1\r
+       sasx    r0,r1,r2\r
+\r
+       sel     r0,r1\r
+       sel     r0,r1,r2\r
+\r
+       setend  le\r
+\r
+       ssax    r0,r1\r
+       ssax    r0,r1,r2\r
+\r
+       ssub16  r0,r1\r
+       ssub16  r0,r1,r2\r
+\r
+       ssub8   r0,r1\r
+       ssub8   r0,r1,r2\r
+\r
+       ssubaddx        r0,r1\r
+       ssubaddx        r0,r1,r2\r
+\r
+       shadd16 r0,r1\r
+       shadd16 r0,r1,r2\r
+\r
+       shadd8  r0,r1\r
+       shadd8  r0,r1,r2\r
+\r
+       shaddsubx       r0,r1\r
+       shaddsubx       r0,r1,r2\r
+\r
+       shasx   r0,r1\r
+       shasx   r0,r1,r2\r
+\r
+       shsax   r0,r1\r
+       shsax   r0,r1,r2\r
+\r
+       shsub16 r0,r1\r
+       shsub16 r0,r1,r2\r
+\r
+       shsub8  r0,r1\r
+       shsub8  r0,r1,r2\r
+\r
+       shsubaddx       r0,r1\r
+       shsubaddx       r0,r1,r2\r
+\r
+       smlad   r0,r1,r2,r3\r
+\r
+       smladx  r0,r1,r2,r3\r
+\r
+       smlald  r0,r1,r2,r3\r
+\r
+       smlaldx r0,r1,r2,r3\r
+\r
+       smlsd   r0,r1,r2,r3\r
+\r
+       smlsdx  r0,r1,r2,r3\r
+\r
+       smlsld  r0,r1,r2,r3\r
+\r
+       smlsldx r0,r1,r2,r3\r
+\r
+       smmla   r0,r1,r2,r3\r
+\r
+       smmlar  r0,r1,r2,r3\r
+\r
+       smmls   r0,r1,r2,r3\r
+\r
+       smmlsr  r0,r1,r2,r3\r
+\r
+       smmul   r0,r1\r
+       smmul   r0,r1,r2\r
+\r
+       smmulr  r0,r1\r
+       smmulr  r0,r1,r2\r
+\r
+       smuad   r0,r1\r
+       smuad   r0,r1,r2\r
+\r
+       smuadx  r0,r1\r
+       smuadx  r0,r1,r2\r
+\r
+       smusd   r0,r1\r
+       smusd   r0,r1,r2\r
+\r
+       smusdx  r0,r1\r
+       smusdx  r0,r1,r2\r
+\r
+       srs     0\r
+       srs     0 !\r
+       srs     sp,0\r
+       srs     sp!,0\r
+\r
+       srsda   0\r
+       srsda   0 !\r
+       srsda   sp,0\r
+       srsda   sp!,0\r
+\r
+       srsdb   0\r
+       srsdb   0 !\r
+       srsdb   sp,0\r
+       srsdb   sp!,0\r
+\r
+       srsea   0\r
+       srsea   0 !\r
+       srsea   sp,0\r
+       srsea   sp!,0\r
+\r
+       srsed   0\r
+       srsed   0 !\r
+       srsed   sp,0\r
+       srsed   sp!,0\r
+\r
+       srsfa   0\r
+       srsfa   0 !\r
+       srsfa   sp,0\r
+       srsfa   sp!,0\r
+\r
+       srsfd   0\r
+       srsfd   0 !\r
+       srsfd   sp,0\r
+       srsfd   sp!,0\r
+\r
+       srsia   0\r
+       srsia   0 !\r
+       srsia   sp,0\r
+       srsia   sp!,0\r
+\r
+       srsib   0\r
+       srsib   0 !\r
+       srsib   sp,0\r
+       srsib   sp!,0\r
+\r
+       ssat    r0,1,r2\r
+       ssat    r0,1,r2,lsl 3\r
+       ssat    r0,1,r2,asr 3\r
+\r
+       ssat16  r0,1,r2\r
+\r
+       strex   r0,r1,[r1]\r
+       strex   r0,r1,[r1,0]\r
+\r
+       sxtab   r0,r1,r2\r
+       sxtab   r0,r1,r2,ror 8\r
+\r
+       sxtab16 r0,r1,r2\r
+       sxtab16 r0,r1,r2,ror 8\r
+\r
+       sxtah   r0,r1,r2\r
+       sxtah   r0,r1,r2,ror 8\r
+\r
+       sxtb    r0,r1\r
+       sxtb    r0,r1,ror 8\r
+\r
+       sxtb16  r0,r1\r
+       sxtb16  r0,r1,ror 8\r
+\r
+       sxth    r0,r1\r
+       sxth    r0,r1,ror 8\r
+\r
+       uadd16  r0,r1\r
+       uadd16  r0,r1,r2\r
+\r
+       uadd8   r0,r1\r
+       uadd8   r0,r1,r2\r
+\r
+       uaddsubx        r0,r1\r
+       uaddsubx        r0,r1,r2\r
+\r
+       uasx    r0,r1\r
+       uasx    r0,r1,r2\r
+\r
+       usax    r0,r1\r
+       usax    r0,r1,r2\r
+\r
+       usub16  r0,r1\r
+       usub16  r0,r1,r2\r
+\r
+       usub8   r0,r1\r
+       usub8   r0,r1,r2\r
+\r
+       usubaddx        r0,r1\r
+       usubaddx        r0,r1,r2\r
+\r
+       uhadd16 r0,r1\r
+       uhadd16 r0,r1,r2\r
+\r
+       uhadd8  r0,r1\r
+       uhadd8  r0,r1,r2\r
+\r
+       uhaddsubx       r0,r1\r
+       uhaddsubx       r0,r1,r2\r
+\r
+       uhasx   r0,r1\r
+       uhasx   r0,r1,r2\r
+\r
+       uhsax   r0,r1\r
+       uhsax   r0,r1,r2\r
+\r
+       uhsub16 r0,r1\r
+       uhsub16 r0,r1,r2\r
+\r
+       uhsub8  r0,r1\r
+       uhsub8  r0,r1,r2\r
+\r
+       uhsubaddx       r0,r1\r
+       uhsubaddx       r0,r1,r2\r
+\r
+       umaal   r0,r1,r2,r3\r
+\r
+       uqadd16 r0,r1\r
+       uqadd16 r0,r1,r2\r
+\r
+       uqadd8  r0,r1\r
+       uqadd8  r0,r1,r2\r
+\r
+       uqaddsubx       r0,r1\r
+       uqaddsubx       r0,r1,r2\r
+\r
+       uqasx   r0,r1\r
+       uqasx   r0,r1,r2\r
+\r
+       uqsax   r0,r1\r
+       uqsax   r0,r1,r2\r
+\r
+       uqsub16 r0,r1\r
+       uqsub16 r0,r1,r2\r
+\r
+       uqsub8  r0,r1\r
+       uqsub8  r0,r1,r2\r
+\r
+       uqsubaddx       r0,r1\r
+       uqsubaddx       r0,r1,r2\r
+\r
+       usad8   r0,r1,r2\r
+\r
+       usada8  r0,r1,r2,r3\r
+\r
+       usat    r0,1,r2\r
+       usat    r0,1,r2,lsl 3\r
+       usat    r0,1,r2,asr 3\r
+\r
+       usat16  r0,1,r2\r
+\r
+       uxtab   r0,r1,r2\r
+       uxtab   r0,r1,r2,ror 8\r
+\r
+       uxtab16 r0,r1,r2\r
+       uxtab16 r0,r1,r2,ror 8\r
+\r
+       uxtah   r0,r1,r2\r
+       uxtah   r0,r1,r2,ror 8\r
+\r
+       uxtb    r0,r1\r
+       uxtb    r0,r1,ror 8\r
+\r
+       uxtb16  r0,r1\r
+       uxtb16  r0,r1,ror 8\r
+\r
+       uxth    r0,r1\r
+       uxth    r0,r1,ror 8\r
+\r
+processor CPU32_K\r
+\r
+       clrex\r
+\r
+       ldrexb  r0,[r1]\r
+       ldrexb  r0,[r1,0]\r
+\r
+       ldrexd  r0,[r1]\r
+       ldrexd  r0,r1,[r2]\r
+\r
+       ldrexh  r0,[r1]\r
+       ldrexh  r0,[r1,0]\r
+\r
+       strexb  r0,r1,[r2]\r
+       strexb  r0,r1,[r2,0]\r
+\r
+       strexd  r0,r2,[r4]\r
+       strexd  r0,r2,r3,[r4]\r
+\r
+       strexh  r0,r1,[r2]\r
+       strexh  r0,r1,[r2,0]\r
+\r
+       sev\r
+\r
+       wfe\r
+\r
+       wfi\r
+\r
+       yield\r
+\r
+processor CPU32_Z\r
+\r
+       smc     0\r
+\r
+       smi     0\r
+\r
+processor CPU32_T2\r
+\r
+       bfc     r0,1,2\r
+\r
+       bfi     r0,r1,2,3\r
+\r
+       mls     r0,r1,r2,r3\r
+\r
+       rbit    r0,r1\r
+\r
+       ldrht   r0,[r1]\r
+       ldrht   r0,[r1],r2\r
+       ldrht   r0,[r1],-r2\r
+       ldrht   r0,[r1],2\r
+\r
+       ldrsbt  r0,[r1]\r
+       ldrsbt  r0,[r1],-r2\r
+       ldrsbt  r0,[r1],r2\r
+       ldrsbt  r0,[r1],2\r
+\r
+       ldrsht  r0,[r1]\r
+       ldrsht  r0,[r1],r2\r
+       ldrsht  r0,[r1],-r2\r
+       ldrsht  r0,[r1],2\r
+\r
+       movt    r0,1\r
+\r
+       movw    r0,1\r
+\r
+       sbfx    r0,r1,2,3\r
+\r
+       strht   r0,[r1]\r
+       strht   r0,[r1],r2\r
+       strht   r0,[r1],-r2\r
+       strht   r0,[r1],2\r
+\r
+       ubfx    r0,r1,2,3\r
+\r
+processor CPU32_V7\r
+\r
+       dbg     0\r
+\r
+       dmb\r
+       dmb     sy\r
+\r
+       dsb\r
+       dsb     sy\r
+\r
+       isb\r
+       isb     sy\r
+\r
+       label_pli:\r
+       pli     [r0]\r
+       pli     [r0,1]\r
+       pli     [r0,r1]\r
+       pli     [r0,-r1]\r
+       pli     [r0,r1,lsl 2]\r
+       pli     [r0,r1,lsr 2]\r
+       pli     [r0,r1,asr 2]\r
+       pli     [r0,r1,ror 2]\r
+       pli     [r0,-r1,lsl 2]\r
+       pli     [r0,-r1,lsr 2]\r
+       pli     [r0,-r1,asr 2]\r
+       pli     [r0,-r1,ror 2]\r
+       pli     [r0,r1,rrx]\r
+       pli     [r0,-r1,rrx]\r
+       pli     [label_pli]\r
+       pli     [expression.byte]\r
+\r
+processor CPU32_MP\r
+\r
+       label_pldw:\r
+       pldw    [r0]\r
+       pldw    [r0,1]\r
+       pldw    [r0,r1]\r
+       pldw    [r0,-r1]\r
+       pldw    [r0,r1,lsl 2]\r
+       pldw    [r0,r1,lsr 2]\r
+       pldw    [r0,r1,asr 2]\r
+       pldw    [r0,r1,ror 2]\r
+       pldw    [r0,-r1,lsl 2]\r
+       pldw    [r0,-r1,lsr 2]\r
+       pldw    [r0,-r1,asr 2]\r
+       pldw    [r0,-r1,ror 2]\r
+       pldw    [r0,r1,rrx]\r
+       pldw    [r0,-r1,rrx]\r
+       pldw    [label_pldw]\r
+       pldw    [expression.byte]\r
+\r
+processor CPU32_VE\r
+\r
+       eret\r
+\r
+       hvc     0\r
+\r
+       msr     lr_fiq,r0\r
+\r
+       mrs     r0,lr_fiq\r
+\r
+       sdiv    r0,r1\r
+       sdiv    r0,r1,r2\r
+\r
+       udiv    r0,r1\r
+       udiv    r0,r1,r2\r
+\r
+processor CPU32_V8\r
+\r
+       hlt     0\r
+\r
+       lda     r0,[r1]\r
+       ldab    r0,[r1]\r
+       ldah    r0,[r1]\r
+\r
+       ldaex   r0,[r1]\r
+       ldaexb  r0,[r1]\r
+       ldaexh  r0,[r1]\r
+       ldaexd  r0,[r2]\r
+       ldaexd  r0,r1,[r2]\r
+\r
+       sevl\r
+       \r
+       stl     r0,[r1]\r
+       stlb    r0,[r1]\r
+       stlh    r0,[r1]\r
+\r
+       stlex   r2,r0,[r3]\r
+       stlexb  r2,r0,[r3]\r
+       stlexh  r2,r0,[r3]\r
+       stlexd  r2,r0,[r3]\r
+       stlexd  r2,r0,r1,[r3]\r
+\r
+processor CPU32_CRC\r
+\r
+       crc32b  r0,r1,r2\r
+       crc32h  r0,r1,r2\r
+       crc32w  r0,r1,r2\r
+\r
+       crc32cb r0,r1,r2\r
+       crc32ch r0,r1,r2\r
+       crc32cw r0,r1,r2\r
+\r
+processor 0    ;In ARM mode, UND is always encodable, it ignores the processor directive\r
+\r
+       und\r
+       und     0\r

diff --git a/armdoc/InstructionFormatsARM64.asm b/armdoc/InstructionFormatsARM64.asm
new file mode 100644 (file)
index 0000000..d312ed0
--- /dev/null
+++ b/armdoc/InstructionFormatsARM64.asm
@@ -0,0 +1,3831 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions show the condition or flag\r
+;writeback ("s") syntaxes. Only the branch (b.cc)\r
+;instruction can be conditional. The condition code\r
+;should be added at the end of the main opcode. For\r
+;example: "b.hi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+label expression.byte   byte   at x2+1\r
+label expression.hword  hword  at x2+2\r
+label expression.word   word   at x2+4\r
+label expression.dword  dword  at x2+8\r
+label expression.qword  qword  at x2+16\r
+label expression.dqword dqword at x2+32\r
+\r
+       ;**************************************************\r
+       ;ARM64 mode, all instructions are 32-bits in length\r
+       ;**************************************************\r
+\r
+       code64\r
+\r
+processor CPU64_V8\r
+\r
+       adc     w0,w1,w2\r
+       adc     x0,x1,x2\r
+\r
+       adcs    w0,w1,w2\r
+       adcs    x0,x1,x2\r
+\r
+       add     sp,sp,0x123\r
+       add     sp,x2,0x123\r
+       add     w1,w2,0x123\r
+       add     w4,w8,0x123,lsl 12\r
+       add     wsp,w2,0x123\r
+       add     wsp,wsp,0x123\r
+       add     w1,w2,wzr\r
+       add     w1,w2,w3\r
+       add     w1,w2,w3,asr 1\r
+       add     w1,w2,w3,lsl 1\r
+       add     w1,w2,w3,lsr 1\r
+       add     w1,w2,w3,sxtb\r
+       add     w1,w2,w3,sxtb 1\r
+       add     w1,w2,w3,sxth\r
+       add     w1,w2,w3,sxth 1\r
+       add     w1,w2,w3,sxtw\r
+       add     w1,w2,w3,sxtw 1\r
+       add     w1,w2,w3,uxtb\r
+       add     w1,w2,w3,uxtb 1\r
+       add     w1,w2,w3,uxth\r
+       add     w1,w2,w3,uxth 1\r
+       add     w1,w2,w3,uxtw\r
+       add     w1,w2,w3,uxtw 1\r
+       add     w1,wsp,w2,uxtw 2\r
+       add     w1,wsp,w3,uxtw\r
+       add     w1,wsp,w3,uxtw 1\r
+       add     wsp,w2,w3,uxtw\r
+       add     wsp,wsp,w3,uxtw\r
+       add     wzr,w2,w3\r
+       add     wzr,w2,wzr\r
+       add     wzr,wzr,w3\r
+       add     wzr,wzr,wzr\r
+       add     x1,x2,x3\r
+       add     x1,x2,0x123\r
+       add     x1,x2,0xFFF\r
+       add     x1,x2,0xFFF,lsl 12\r
+       add     x1,sp,0x123\r
+       add     x1,sp,x3,uxtx\r
+       add     x1,sp,x3,uxtx 4\r
+       add     x1,x2,w3,sxtb\r
+       add     x1,x2,w3,sxtb 2\r
+       add     x1,x2,w3,sxth\r
+       add     x1,x2,w3,sxth 2\r
+       add     x1,x2,w3,sxtw\r
+       add     x1,x2,w3,sxtw 2\r
+       add     x1,x2,w3,uxtb\r
+       add     x1,x2,w3,uxtb 2\r
+       add     x1,x2,w3,uxth\r
+       add     x1,x2,w3,uxth 2\r
+       add     x1,x2,w3,uxtw\r
+       add     x1,x2,w3,uxtw 2\r
+       add     x1,x2,x3,asr 1\r
+       add     x1,x2,x3,asr 63\r
+       add     x1,x2,x3,lsl 1\r
+       add     x1,x2,x3,lsr 1\r
+       add     x1,x2,x3,sxtx\r
+       add     x1,x2,x3,sxtx 3\r
+       add     x1,x2,x3,uxtx\r
+       add     x1,x2,x3,uxtx 2\r
+       add     w1,wsp,w3\r
+       add     w1,w3,wsp\r
+       add     x1,sp,x3\r
+       add     x1,x3,sp\r
+\r
+       adds    w1,w2,w3\r
+       adds    w1,w2,wzr\r
+       adds    w1,wsp,0x123\r
+       adds    w1,wsp,w3,uxtw\r
+       adds    w1,wsp,w2,uxtw 2\r
+       adds    w1,wzr,w3\r
+       adds    w1,wzr,wzr\r
+       adds    w8,w16,0x123,lsl 12\r
+       adds    x8,x16,0x123,lsl 12\r
+       adds    x1,x2,x3,asr 63\r
+       adds    w1,wsp,w3\r
+       adds    w1,w3,wsp\r
+       adds    x1,sp,x3\r
+       adds    x1,x3,sp\r
+\r
+       label_adr:\r
+       adr     x1,label_adr\r
+\r
+       adrp    x1,$\r
+\r
+       and     w1,w2,0x0001FE00\r
+       and     w1,w2,w3\r
+       and     w1,w2,w3,asr 4\r
+       and     w1,w2,w3,lsl 4\r
+       and     w1,w2,w3,lsr 4\r
+       and     w1,w2,w3,ror 4\r
+       and     wzr,w2,w3,ror 4\r
+       and     x1,x2,0x0003FC0000000000\r
+       and     x1,x2,x3\r
+       and     x1,x2,x3,lsl 4\r
+       and     x1,x2,x3,ror 4\r
+       and     xzr,x2,x3,ror 4\r
+\r
+       ands    w1,w2,0xFFFFFFF1\r
+       ands    w1,w2,w3\r
+       ands    w1,w2,w3,lsl 4\r
+       ands    w1,w2,w3,ror 4\r
+       ands    x1,x2,0x5555555555555555\r
+       ands    x1,x2,x3\r
+       ands    x1,x2,x3,lsl 4\r
+       ands    x1,x2,x3,ror 4\r
+\r
+       asr     w1,w2,1\r
+       asr     w1,w2,w3\r
+       asr     x1,x2,1\r
+       asr     x1,x2,x3\r
+\r
+       asrv    w1,w2,w3\r
+       asrv    x1,x2,x3\r
+\r
+       at      s12e0r,x1\r
+       at      s12e0w,x1\r
+       at      s12e1r,x1\r
+       at      s12e1w,x1\r
+       at      s1e0r,x1\r
+       at      s1e0w,x1\r
+       at      s1e1r,x1\r
+       at      s1e1w,x1\r
+       at      s1e2r,x1\r
+       at      s1e2w,x1\r
+       at      s1e3r,x1\r
+       at      s1e3w,x1\r
+\r
+       label_b:\r
+       b       label_b\r
+       b.al    label_b\r
+       b.eq    label_b\r
+       b.eq    label_b\r
+       b.ge    label_b\r
+       b.gt    label_b\r
+       b.hi    label_b\r
+       b.hs    label_b\r
+       b.le    label_b\r
+       b.lo    label_b\r
+       b.ls    label_b\r
+       b.lt    label_b\r
+       b.mi    label_b\r
+       b.ne    label_b\r
+       b.pl    label_b\r
+       b.vc    label_b\r
+       b.vs    label_b\r
+\r
+       bfi     w1,w2,3,27\r
+       bfi     x1,x2,3,59\r
+\r
+       bfm     w1,w2,3,31\r
+       bfm     x1,x2,3,45\r
+\r
+       bfxil   w1,w2,3,29\r
+       bfxil   x1,x2,3,29\r
+\r
+       bic     w1,w2,w3\r
+       bic     w1,w2,w3,asr 4\r
+       bic     w1,w2,w3,lsl 4\r
+       bic     w1,w2,w3,lsr 4\r
+       bic     w1,w2,w3,ror 4\r
+       bic     x1,x2,x3\r
+       bic     x1,x2,x3,lsl 4\r
+       bic     x1,x2,x3,ror 4\r
+\r
+       bics    w1,w2,w3\r
+       bics    w1,w2,w3,lsl 4\r
+       bics    w1,w2,w3,ror 4\r
+       bics    x1,x2,x3\r
+       bics    x1,x2,x3,lsl 4\r
+       bics    x1,x2,x3,ror 4\r
+\r
+       label_bl:\r
+       bl      label_bl\r
+\r
+       blr     x1\r
+\r
+       br      x1\r
+\r
+       brk     0xFFFF\r
+\r
+       label_cbnz:\r
+       cbnz    w1,label_cbnz\r
+       cbnz    x1,label_cbnz\r
+\r
+       label_cbz:\r
+       cbz     w1,label_cbz\r
+       cbz     x1,label_cbz\r
+\r
+       ccmn    w1,2,0x0,ls\r
+       ccmn    w1,w2,0x0,hs\r
+       ccmn    x1,31,0x0,vs\r
+       ccmn    x1,x2,0x1,ge\r
+\r
+       ccmp    w1,2,0x0,ls\r
+       ccmp    w1,w2,0x0,hs\r
+       ccmp    x1,31,0x0,vs\r
+       ccmp    x1,x2,0x1,ge\r
+\r
+       cinc    w1,w2,hs\r
+\r
+       cinv    w1,w2,hs\r
+\r
+       clrex   0x5\r
+\r
+       cls     w1,w2\r
+       cls     x1,x2\r
+\r
+       clz     w1,w2\r
+       clz     x1,x2\r
+\r
+       cmn     sp,x3,uxtx\r
+       cmn     sp,x3,uxtx 1\r
+       cmn     w2,w3\r
+       cmn     w2,w3,asr 1\r
+       cmn     w2,w3,asr 31\r
+       cmn     w2,w3,lsl 1\r
+       cmn     w2,w3,lsr 1\r
+       cmn     wsp,w3,uxtw\r
+       cmn     wsp,w3,uxtw 1\r
+       cmn     x1,0x2\r
+       cmn     x2,x3\r
+       cmn     x2,x3,asr 1\r
+       cmn     x2,x3,asr 63\r
+       cmn     x2,x3,lsl 1\r
+       cmn     x2,x3,lsr 1\r
+\r
+       cmp     sp,x3,uxtx\r
+       cmp     sp,x3,uxtx 1\r
+       cmp     w2,w3\r
+       cmp     w2,w3,asr 1\r
+       cmp     w2,w3,asr 31\r
+       cmp     w2,w3,lsl 1\r
+       cmp     w2,w3,lsr 1\r
+       cmp     wsp,w3,uxtw\r
+       cmp     wsp,w3,uxtw 1\r
+       cmp     x1,0x2\r
+       cmp     x2,x3\r
+       cmp     x2,x3,asr 1\r
+       cmp     x2,x3,asr 63\r
+       cmp     x2,x3,lsl 1\r
+       cmp     x2,x3,lsr 1\r
+\r
+       cneg    w1,w2,hs\r
+       cneg    xzr,xzr,hs\r
+\r
+       csel    w1,w2,w3,ne\r
+       csel    x1,x2,x3,vs\r
+\r
+       cset    w1,ne\r
+       cset    x1,vs\r
+\r
+       csetm   w1,ne\r
+       csetm   x1,vs\r
+\r
+       csinc   w1,w2,w3,ne\r
+       csinc   x1,x2,x3,vs\r
+\r
+       csinv   w1,w2,w3,ne\r
+       csinv   x1,x2,x3,vs\r
+\r
+       csneg   w1,w2,w3,ne\r
+       csneg   x1,x2,x3,vs\r
+\r
+       dc      cisw,x1\r
+       dc      civac,x1\r
+       dc      csw,x1\r
+       dc      cvac,x1\r
+       dc      cvau,x1\r
+       dc      isw,x1\r
+       dc      ivac,x1\r
+       dc      zva,x1\r
+\r
+       dcps1   0x0\r
+\r
+       dcps1   0xFFFF\r
+\r
+       dcps2   0xFFFF\r
+\r
+       dcps3   0xFFFF\r
+\r
+       dmb     ish\r
+       dmb     ishld\r
+       dmb     ishst\r
+       dmb     ld\r
+       dmb     nsh\r
+       dmb     nshld\r
+       dmb     nshst\r
+       dmb     osh\r
+       dmb     oshld\r
+       dmb     oshst\r
+       dmb     st\r
+       dmb     sy\r
+\r
+       drps\r
+\r
+       dsb     ish\r
+       dsb     ishld\r
+       dsb     ishst\r
+       dsb     ld\r
+       dsb     nsh\r
+       dsb     nshld\r
+       dsb     nshst\r
+       dsb     osh\r
+       dsb     oshld\r
+       dsb     oshst\r
+       dsb     st\r
+       dsb     sy\r
+\r
+       eon     w1,w2,w3\r
+       eon     w1,w2,w3,asr 4\r
+       eon     w1,w2,w3,lsl 4\r
+       eon     w1,w2,w3,lsr 4\r
+       eon     w1,w2,w3,ror 4\r
+       eon     wzr,w2,w3,ror 4\r
+       eon     x1,x2,x3\r
+       eon     x1,x2,x3,lsl 4\r
+       eon     x1,x2,x3,ror 4\r
+       eon     xzr,x2,x3,ror 4\r
+\r
+       eor     sp,x2,0xAAAAAAAAAAAAAAAA\r
+       eor     w1,w2,0xFFFFFFF1\r
+       eor     w1,w2,w3\r
+       eor     w1,w2,w3,asr 4\r
+       eor     w1,w2,w3,lsl 4\r
+       eor     w1,w2,w3,lsr 4\r
+       eor     w1,w2,w3,ror 4\r
+       eor     wzr,w2,w3,ror 4\r
+       eor     x1,x2,0xFFFFFFFFFFFFFFF1\r
+       eor     x1,x2,x3\r
+       eor     x1,x2,x3,lsl 4\r
+       eor     x1,x2,x3,ror 4\r
+       eor     xzr,x2,x3,ror 4\r
+\r
+       eret\r
+\r
+       extr    w1,w2,w3,3\r
+       extr    x1,x2,x3,35\r
+\r
+       hint    4\r
+\r
+       hlt     0xFFFF\r
+\r
+       hvc     0xFFFF\r
+\r
+       ic      iallu\r
+       ic      ialluis\r
+       ic      ivau,x1\r
+       ic      ivau,xzr\r
+\r
+       isb     sy\r
+\r
+       ldar    w1,[x2]\r
+       ldar    w1,[x2,0]\r
+       ldar    x3,[x8]\r
+       ldar    x3,[x8,0]\r
+\r
+       ldarb   w1,[x2]\r
+       ldarb   w1,[x2,0]\r
+\r
+       ldarh   w1,[x2]\r
+       ldarh   w1,[x2,0]\r
+\r
+       ldaxp   w1,w8,[x2]\r
+       ldaxp   w1,w8,[x2,0]\r
+       ldaxp   x3,x2,[x8]\r
+       ldaxp   x3,x2,[x8,0]\r
+\r
+       ldaxr   w1,[x2]\r
+       ldaxr   w1,[x2,0]\r
+       ldaxr   x3,[x8]\r
+       ldaxr   x3,[x8,0]\r
+\r
+       ldaxrb  w1,[x2]\r
+       ldaxrb  w1,[x2,0]\r
+\r
+       ldaxrh  w1,[x2]\r
+       ldaxrh  w1,[x2,0]\r
+\r
+       ldnp    w0,w1,[x2]\r
+       ldnp    w0,w1,[x2,+0x8]\r
+       ldnp    w0,w1,[expression.dword]\r
+       ldnp    x0,x1,[x2]\r
+       ldnp    x0,x1,[x2,+0x8]\r
+       ldnp    x0,x1,[expression.qword]\r
+\r
+       ldp     w0,w1,[x2]\r
+       ldp     w0,w1,[x2,+0x8]\r
+       ldp     w0,w1,[expression.dword]\r
+       ldp     w0,w1,[x2,+0x8]!\r
+       ldp     w0,w1,[expression.dword]!\r
+       ldp     w0,w1,[x2],+0x8\r
+       ldp     x0,x1,[x2]\r
+       ldp     x0,x1,[x2,+0x8]\r
+       ldp     x0,x1,[expression.qword]\r
+       ldp     x0,x1,[x2,+0x8]!\r
+       ldp     x0,x1,[expression.qword]!\r
+       ldp     x0,x1,[x2],+0x8\r
+\r
+       ldpsw   x0,x1,[x2]\r
+       ldpsw   x0,x1,[x2,+0x8]\r
+       ldpsw   x0,x1,[expression.dword]\r
+       ldpsw   x0,x1,[x2,+0x8]!\r
+       ldpsw   x0,x1,[expression.dword]!\r
+       ldpsw   x0,x1,[x2],+0x8\r
+\r
+       label_ldr:\r
+       ldr     w0,[x2,+0x8]\r
+       ldr     w0,[expression.word]\r
+       ldr     w0,[x2,+0x8]!\r
+       ldr     w0,[expression.word]!\r
+       ldr     w0,[x2],+0x8\r
+       ldr     w0,[x2,w3,sxtw]\r
+       ldr     w0,[x2,w3,sxtw 2]\r
+       ldr     w0,[x2,w3,uxtw]\r
+       ldr     w0,[x2,w3,uxtw 2]\r
+       ldr     w0,[x2,x3]\r
+       ldr     w0,[x2,x3,lsl 2]\r
+       ldr     w0,[x2,x3,sxtx]\r
+       ldr     w0,[x2,x3,sxtx 2]\r
+       ldr     w0,label_ldr\r
+       ldr     w0,[label_ldr]\r
+       ldr     x0,[x2,+0x8]\r
+       ldr     x0,[expression.dword]\r
+       ldr     x0,[x2,+0x8]!\r
+       ldr     x0,[expression.dword]!\r
+       ldr     x0,[x2],+0x8\r
+       ldr     x0,[x2,w3,sxtw]\r
+       ldr     x0,[x2,w3,sxtw 3]\r
+       ldr     x0,[x2,w3,uxtw]\r
+       ldr     x0,[x2,w3,uxtw 3]\r
+       ldr     x0,[x2,x3]\r
+       ldr     x0,[x2,x3,lsl 3]\r
+       ldr     x0,[x2,x3,sxtx]\r
+       ldr     x0,[x2,x3,sxtx 3]\r
+       ldr     x0,label_ldr\r
+       ldr     x0,[label_ldr]\r
+\r
+       ldrb    w0,[x2]\r
+       ldrb    w0,[x2,+0x8]\r
+       ldrb    w0,[expression.byte]\r
+       ldrb    w0,[x2,+0x8]!\r
+       ldrb    w0,[expression.byte]!\r
+       ldrb    w0,[x2],+0x8\r
+       ldrb    w0,[x2,w3,sxtw]\r
+       ldrb    w0,[x2,w3,sxtw 0]\r
+       ldrb    w0,[x2,w3,uxtw]\r
+       ldrb    w0,[x2,w3,uxtw 0]\r
+       ldrb    w0,[x2,x3]\r
+       ldrb    w0,[x2,x3,lsl 0]\r
+       ldrb    w0,[x2,x3,sxtx]\r
+       ldrb    w0,[x2,x3,sxtx 0]\r
+\r
+       ldrh    w0,[x2]\r
+       ldrh    w0,[x2,+0x8]\r
+       ldrh    w0,[expression.hword]\r
+       ldrh    w0,[x2,+0x8]!\r
+       ldrh    w0,[expression.hword]!\r
+       ldrh    w0,[x2],+0x8\r
+       ldrh    w0,[x2,w3,sxtw]\r
+       ldrh    w0,[x2,w3,sxtw 1]\r
+       ldrh    w0,[x2,w3,uxtw]\r
+       ldrh    w0,[x2,w3,uxtw 1]\r
+       ldrh    w0,[x2,x3]\r
+       ldrh    w0,[x2,x3,lsl 1]\r
+       ldrh    w0,[x2,x3,sxtx]\r
+       ldrh    w0,[x2,x3,sxtx 1]\r
+\r
+       ldrsb   w0,[x2]\r
+       ldrsb   w0,[x2,+0x8]\r
+       ldrsb   w0,[expression.byte]\r
+       ldrsb   w0,[x2,+0x8]!\r
+       ldrsb   w0,[expression.byte]!\r
+       ldrsb   w0,[x2],+0x8\r
+       ldrsb   w0,[x2,w3,sxtw]\r
+       ldrsb   w0,[x2,w3,sxtw 0]\r
+       ldrsb   w0,[x2,w3,uxtw]\r
+       ldrsb   w0,[x2,w3,uxtw 0]\r
+       ldrsb   w0,[x2,x3]\r
+       ldrsb   w0,[x2,x3,lsl 0]\r
+       ldrsb   w0,[x2,x3,sxtx]\r
+       ldrsb   w0,[x2,x3,sxtx 0]\r
+\r
+       ldrsh   w0,[x2]\r
+       ldrsh   w0,[x2,+0x8]\r
+       ldrsh   w0,[expression.hword]\r
+       ldrsh   w0,[x2,+0x8]!\r
+       ldrsh   w0,[expression.hword]!\r
+       ldrsh   w0,[x2],+0x8\r
+       ldrsh   w0,[x2,w3,sxtw]\r
+       ldrsh   w0,[x2,w3,sxtw 1]\r
+       ldrsh   w0,[x2,w3,uxtw]\r
+       ldrsh   w0,[x2,w3,uxtw 1]\r
+       ldrsh   w0,[x2,x3]\r
+       ldrsh   w0,[x2,x3,lsl 1]\r
+       ldrsh   w0,[x2,x3,sxtx]\r
+       ldrsh   w0,[x2,x3,sxtx 1]\r
+\r
+       label_ldrsw:\r
+       ldrsw   x0,[x2]\r
+       ldrsw   x0,[x2,+0x8]\r
+       ldrsw   x0,[expression.word]\r
+       ldrsw   x0,[x2,+0x8]!\r
+       ldrsw   x0,[expression.word]!\r
+       ldrsw   x0,[x2],+0x8\r
+       ldrsw   x0,[x2,w3,sxtw]\r
+       ldrsw   x0,[x2,w3,sxtw 2]\r
+       ldrsw   x0,[x2,w3,uxtw]\r
+       ldrsw   x0,[x2,w3,uxtw 2]\r
+       ldrsw   x0,[x2,x3]\r
+       ldrsw   x0,[x2,x3,lsl 2]\r
+       ldrsw   x0,[x2,x3,sxtx]\r
+       ldrsw   x0,[x2,x3,sxtx 2]\r
+       ldrsw   x1,label_ldrsw\r
+       ldrsw   x1,[label_ldrsw]\r
+\r
+       ldtr    w0,[x2]\r
+       ldtr    w0,[x2,+0x8]\r
+       ldtr    w0,[expression.word]\r
+       ldtr    x0,[x2]\r
+       ldtr    x0,[x2,+0x8]\r
+       ldtr    x0,[expression.dword]\r
+\r
+       ldtrb   w0,[x2]\r
+       ldtrb   w0,[x2,+0x8]\r
+       ldtrb   w0,[expression.byte]\r
+\r
+       ldtrh   w0,[x2]\r
+       ldtrh   w0,[x2,+0x8]\r
+       ldtrh   w0,[expression.hword]\r
+\r
+       ldtrsb  w0,[x2]\r
+       ldtrsb  w0,[x2,+0x8]\r
+       ldtrsb  w0,[expression.byte]\r
+\r
+       ldtrsh  w0,[x2]\r
+       ldtrsh  w0,[x2,+0x8]\r
+       ldtrsh  w0,[expression.hword]\r
+\r
+       ldtrsw  x0,[x2]\r
+       ldtrsw  x0,[x2,+0x8]\r
+       ldtrsw  x0,[expression.word]\r
+\r
+       ldur    w0,[x2]\r
+       ldur    w0,[x2,+0x8]\r
+       ldur    w0,[expression.word]\r
+       ldur    x0,[x2]\r
+       ldur    x0,[x2,+0x8]\r
+       ldur    x0,[expression.dword]\r
+\r
+       ldurb   w0,[x2]\r
+       ldurb   w0,[x2,+0x8]\r
+       ldurb   w0,[expression.byte]\r
+\r
+       ldurh   w0,[x2]\r
+       ldurh   w0,[x2,+0x8]\r
+       ldurh   w0,[expression.hword]\r
+\r
+       ldursb  w0,[x2]\r
+       ldursb  w0,[x2,+0x8]\r
+       ldursb  w0,[expression.byte]\r
+\r
+       ldursh  w0,[x2]\r
+       ldursh  w0,[x2,+0x8]\r
+       ldursh  w0,[expression.hword]\r
+\r
+       ldursw  x0,[x2]\r
+       ldursw  x0,[x2,+0x8]\r
+       ldursw  x0,[expression.word]\r
+\r
+       ldxp    w1,w8,[x2]\r
+       ldxp    w1,w8,[x2,0]\r
+       ldxp    x3,x2,[x8]\r
+       ldxp    x3,x2,[x8,0]\r
+\r
+       ldxr    w1,[x2]\r
+       ldxr    w1,[x2,0]\r
+       ldxr    x3,[x8]\r
+       ldxr    x3,[x8,0]\r
+\r
+       ldxrb   w1,[x2]\r
+       ldxrb   w1,[x2,0]\r
+\r
+       ldxrh   w1,[x2]\r
+       ldxrh   w1,[x2,0]\r
+\r
+       lsl     w1,w2,1\r
+       lsl     w1,w2,w3\r
+       lsl     x1,x2,1\r
+       lsl     x1,x2,x3\r
+\r
+       lslv    w1,w2,w3\r
+       lslv    x1,x2,x3\r
+\r
+       lsr     w1,w2,1\r
+       lsr     w1,w2,w3\r
+       lsr     x1,x2,1\r
+       lsr     x1,x2,x3\r
+\r
+       lsrv    w1,w2,w3\r
+       lsrv    x1,x2,x3\r
+\r
+       madd    w1,w2,w3,w4\r
+       madd    x1,x2,x3,x4\r
+\r
+       mneg    w1,w2,w3\r
+       mneg    x1,x2,x3\r
+\r
+       mov     sp,sp\r
+       mov     sp,x1\r
+       mov     w0,w1\r
+       mov     w1,0x00FFFFF0\r
+       mov     w1,0x000FFFFF\r
+       mov     w1,0x100FFFFF\r
+       mov     wsp,0x0000FFFF\r
+       mov     wsp,w1\r
+       mov     wsp,wsp\r
+       mov     wzr,w1\r
+       mov     wzr,wzr\r
+       mov     x0,x1\r
+       mov     x1,0x000FFFFFFFFFFFF0\r
+       mov     x1,0x0000FFFFFFFFFFFF\r
+       mov     x1,0x1000FFFFFFFFFFFF\r
+       mov     x1,sp\r
+       mov     xzr,x1\r
+       mov     xzr,xzr\r
+\r
+       movk    x0,0,lsl 0\r
+       movk    x0,0,lsl 16\r
+       movk    x0,0,lsl 32\r
+       movk    x0,0,lsl 48\r
+\r
+       movn    x0,0,lsl 0\r
+       movn    x0,0,lsl 16\r
+       movn    x0,0,lsl 32\r
+       movn    x0,0,lsl 48\r
+\r
+       movz    x0,0,lsl 0\r
+       movz    x0,0,lsl 16\r
+       movz    x0,0,lsl 32\r
+       movz    x0,0,lsl 48\r
+\r
+       movk    w1,0xFFFF\r
+       movk    w1,0xFFFF,lsl 16\r
+       movk    x1,0xFFFF,lsl 32\r
+       movk    x1,0xFFFF,lsl 48\r
+\r
+       movn    w1,0xFFFF\r
+       movn    w1,0xFFFF,lsl 16\r
+\r
+       movz    w1,0xffff\r
+       movz    w1,0xffff,lsl 0\r
+       movz    w1,0xffff,lsl 16\r
+       movz    x1,0xffff,lsl 32\r
+       movz    x1,0xffff,lsl 48\r
+\r
+       mrs     x1,vttbr_el2\r
+       mrs     x2,s3_2_c3_c4_5\r
+       mrs     x8,spsel\r
+\r
+       msr     actlr_el1,x1\r
+       msr     s3_2_c3_c4_5,x1\r
+\r
+       msub    w1,w2,w3,w4\r
+       msub    x1,x2,x3,x4\r
+\r
+       mul     w1,w2,w3\r
+       mul     x2,x3,x4\r
+\r
+       mvn     w1,w2\r
+       mvn     w1,w2,asr 4\r
+       mvn     w1,w2,lsl 4\r
+       mvn     w1,w2,lsr 4\r
+       mvn     w1,w2,ror 4\r
+       mvn     x1,x2\r
+       mvn     x1,x2,asr 4\r
+       mvn     x1,x2,lsl 4\r
+       mvn     x1,x2,lsr 4\r
+       mvn     x1,x2,ror 4\r
+\r
+       neg     w1,w2\r
+       neg     w1,w2,asr 14\r
+       neg     w1,w2,lsl 4\r
+       neg     w1,w2,lsr 4\r
+       neg     x1,x2\r
+       neg     x1,x2,asr 14\r
+       neg     x1,x2,lsl 4\r
+       neg     x1,x2,lsr 4\r
+\r
+       negs    w1,w2\r
+       negs    x1,x2\r
+\r
+       ngc     w1,w2\r
+       ngc     x1,x2\r
+\r
+       ngcs    w1,w2\r
+       ngcs    x1,x2\r
+\r
+       nop\r
+\r
+       orn     w1,w2,w3\r
+       orn     w1,w2,w3,asr 4\r
+       orn     w1,w2,w3,lsl 4\r
+       orn     w1,w2,w3,lsr 4\r
+       orn     w1,w2,w3,ror 4\r
+       orn     x1,x2,x3\r
+       orn     x1,x2,x3,asr 4\r
+       orn     x1,x2,x3,lsl 4\r
+       orn     x1,x2,x3,lsr 4\r
+       orn     x1,x2,x3,ror 4\r
+\r
+       orr     w1,w2,0xFFFFFFF1\r
+       orr     w1,w2,w3\r
+       orr     w1,w2,w3,asr 4\r
+       orr     w1,w2,w3,lsl 4\r
+       orr     w1,w2,w3,lsr 4\r
+       orr     w1,w2,w3,ror 4\r
+       orr     x1,x2,0xAAAAAAAAAAAAAAAA\r
+       orr     x1,x2,x3\r
+       orr     x1,x2,x3,lsl 4\r
+       orr     x1,x2,x3,ror 4\r
+\r
+       label_prfm:\r
+       prfm    pldl2strm,[x2,+0x8]\r
+       prfm    pldl2strm,[expression.dword]\r
+       prfm    pldl2strm,[x2,w3,sxtw]\r
+       prfm    pldl2strm,[x2,w3,sxtw 3]\r
+       prfm    pldl2strm,[x2,w3,uxtw]\r
+       prfm    pldl2strm,[x2,w3,uxtw 3]\r
+       prfm    pldl2strm,[x2,x3]\r
+       prfm    pldl2strm,[x2,x3,lsl 3]\r
+       prfm    pldl2strm,[x2,x3,sxtx]\r
+       prfm    pldl2strm,[x2,x3,sxtx 3]\r
+       prfm    pldl2strm,label_prfm\r
+       prfm    pldl2strm,[label_prfm]\r
+       prfm    0x00,[x2,+0x8]\r
+       prfm    0x01,[expression.dword]\r
+       prfm    0x02,[x2,w3,sxtw]\r
+       prfm    0x03,[x2,w3,sxtw 3]\r
+       prfm    0x04,[x2,w3,uxtw]\r
+       prfm    0x05,[x2,w3,uxtw 3]\r
+       prfm    0x06,[x2,x3]\r
+       prfm    0x07,[x2,x3,lsl 3]\r
+       prfm    0x08,[x2,x3,sxtx]\r
+       prfm    0x09,[x2,x3,sxtx 3]\r
+       prfm    0x0a,label_prfm\r
+       prfm    0x0b,[label_prfm]\r
+\r
+       rbit    w1,w2\r
+       rbit    x1,x2\r
+\r
+       ret\r
+       ret     x1\r
+\r
+       rev     w1,w2\r
+       rev     x1,x2\r
+\r
+       rev16   w1,w2\r
+       rev16   x1,x2\r
+\r
+       rev32   x1,x2\r
+\r
+       rev64   x1,x2\r
+\r
+       ror     w1,w2,1\r
+       ror     w1,w2,w3\r
+       ror     x1,x2,1\r
+       ror     x1,x2,x3\r
+\r
+       rorv    w1,w2,w3\r
+       rorv    x1,x2,x3\r
+\r
+       sbc     w0,w1,w2\r
+       sbc     x0,x1,x2\r
+\r
+       sbcs    w0,w1,w2\r
+       sbcs    x0,x1,x2\r
+\r
+       sbfiz   w1,w2,3,28\r
+       sbfiz   x1,x2,3,60\r
+\r
+       sbfm    w1,w2,3,30\r
+       sbfm    x1,x2,3,45\r
+\r
+       sbfx    w1,w2,3,4\r
+       sbfx    x1,x2,3,29\r
+\r
+       sdiv    w1,w2,w3\r
+       sdiv    x1,x2,x3\r
+\r
+       sev\r
+\r
+       sevl\r
+\r
+       smaddl  x1,w2,w3,x4\r
+\r
+       smc     0xFFFF\r
+\r
+       smnegl  x1,w2,w3\r
+\r
+       smsubl  x1,w2,w3,x4\r
+\r
+       smulh   x1,x2,x3\r
+\r
+       smull   x1,w2,w3\r
+\r
+       stlr    w1,[x2]\r
+       stlr    w1,[x2,0]\r
+       stlr    x3,[x8]\r
+       stlr    x3,[x8,0]\r
+\r
+       stlrb   w1,[x2]\r
+       stlrb   w1,[x2,0]\r
+\r
+       stlrh   w1,[x2]\r
+       stlrh   w1,[x2,0]\r
+\r
+       stlxp   w1,w2,w3,[x4]\r
+       stlxp   w1,w2,w3,[x4,0]\r
+       stlxp   w1,x2,x3,[x4]\r
+       stlxp   w1,x2,x3,[x4,0]\r
+\r
+       stlxr   w1,w2,[x3]\r
+       stlxr   w1,w2,[x3,0]\r
+       stlxr   w1,x2,[x3]\r
+       stlxr   w1,x2,[x3,0]\r
+\r
+       stlxrb  w1,w2,[x3]\r
+       stlxrb  w1,w2,[x3,0]\r
+\r
+       stlxrh  w1,w2,[x3]\r
+       stlxrh  w1,w2,[x3,0]\r
+\r
+       stnp    w0,w1,[x2]\r
+       stnp    w0,w1,[x2,+0x8]\r
+       stnp    w0,w1,[expression.dword]\r
+       stnp    x0,x1,[x2]\r
+       stnp    x0,x1,[x2,+0x8]\r
+       stnp    x0,x1,[expression.qword]\r
+\r
+       stp     w0,w1,[x2]\r
+       stp     w0,w1,[x2,+0x8]\r
+       stp     w0,w1,[expression.dword]\r
+       stp     w0,w1,[x2,+0x8]!\r
+       stp     w0,w1,[expression.dword]!\r
+       stp     w0,w1,[x2],+0x8\r
+       stp     x0,x1,[x2]\r
+       stp     x0,x1,[x2,+0x8]\r
+       stp     x0,x1,[expression.qword]\r
+       stp     x0,x1,[x2,+0x8]!\r
+       stp     x0,x1,[expression.qword]!\r
+       stp     x0,x1,[x2],+0x8\r
+\r
+       str     w0,[x2,+0x8]\r
+       str     w0,[expression.word]\r
+       str     w0,[x2,+0x8]!\r
+       str     w0,[expression.word]!\r
+       str     w0,[x2],+0x8\r
+       str     w0,[x2,w3,sxtw]\r
+       str     w0,[x2,w3,sxtw 2]\r
+       str     w0,[x2,w3,uxtw]\r
+       str     w0,[x2,w3,uxtw 2]\r
+       str     w0,[x2,x3]\r
+       str     w0,[x2,x3,lsl 2]\r
+       str     w0,[x2,x3,sxtx]\r
+       str     w0,[x2,x3,sxtx 2]\r
+       str     x0,[x2,+0x8]\r
+       str     x0,[expression.dword]\r
+       str     x0,[x2,+0x8]!\r
+       str     x0,[expression.dword]!\r
+       str     x0,[x2],+0x8\r
+       str     x0,[x2,w3,sxtw]\r
+       str     x0,[x2,w3,sxtw 3]\r
+       str     x0,[x2,w3,uxtw]\r
+       str     x0,[x2,w3,uxtw 3]\r
+       str     x0,[x2,x3]\r
+       str     x0,[x2,x3,lsl 3]\r
+       str     x0,[x2,x3,sxtx]\r
+       str     x0,[x2,x3,sxtx 3]\r
+\r
+       strb    w0,[x2]\r
+       strb    w0,[x2,+0x8]\r
+       strb    w0,[expression.byte]\r
+       strb    w0,[x2,+0x8]!\r
+       strb    w0,[expression.byte]!\r
+       strb    w0,[x2],+0x8\r
+       strb    w0,[x2,w3,sxtw]\r
+       strb    w0,[x2,w3,sxtw 0]\r
+       strb    w0,[x2,w3,uxtw]\r
+       strb    w0,[x2,w3,uxtw 0]\r
+       strb    w0,[x2,x3]\r
+       strb    w0,[x2,x3,lsl 0]\r
+       strb    w0,[x2,x3,sxtx]\r
+       strb    w0,[x2,x3,sxtx 0]\r
+\r
+       strh    w0,[x2]\r
+       strh    w0,[x2,+0x8]\r
+       strh    w0,[expression.hword]\r
+       strh    w0,[x2,+0x8]!\r
+       strh    w0,[expression.hword]!\r
+       strh    w0,[x2],+0x8\r
+       strh    w0,[x2,w3,sxtw]\r
+       strh    w0,[x2,w3,sxtw 1]\r
+       strh    w0,[x2,w3,uxtw]\r
+       strh    w0,[x2,w3,uxtw 1]\r
+       strh    w0,[x2,x3]\r
+       strh    w0,[x2,x3,lsl 1]\r
+       strh    w0,[x2,x3,sxtx]\r
+       strh    w0,[x2,x3,sxtx 1]\r
+\r
+       sttr    w0,[x2]\r
+       sttr    w0,[x2,+0x8]\r
+       sttr    w0,[expression.word]\r
+       sttr    x0,[x2]\r
+       sttr    x0,[x2,+0x8]\r
+       sttr    x0,[expression.dword]\r
+\r
+       sttrb   w0,[x2]\r
+       sttrb   w0,[x2,+0x8]\r
+       sttrb   w0,[expression.byte]\r
+\r
+       sttrh   w0,[x2]\r
+       sttrh   w0,[x2,+0x8]\r
+       sttrh   w0,[expression.hword]\r
+\r
+       stur    w0,[x2]\r
+       stur    w0,[x2,+0x8]\r
+       stur    w0,[expression.word]\r
+       stur    x0,[x2]\r
+       stur    x0,[x2,+0x8]\r
+       stur    x0,[expression.dword]\r
+\r
+       sturb   w0,[x2]\r
+       sturb   w0,[x2,+0x8]\r
+       sturb   w0,[expression.byte]\r
+\r
+       sturh   w0,[x2]\r
+       sturh   w0,[x2,+0x8]\r
+       sturh   w0,[expression.hword]\r
+\r
+       stxp    w1,w2,w3,[x4]\r
+       stxp    w1,w2,w3,[x4,0]\r
+       stxp    w1,x2,x3,[x4]\r
+       stxp    w1,x2,x3,[x4,0]\r
+\r
+       stxr    w1,w2,[x3]\r
+       stxr    w1,w2,[x3,0]\r
+       stxr    w1,x2,[x3]\r
+       stxr    w1,x2,[x3,0]\r
+\r
+       stxrb   w1,w2,[x3]\r
+       stxrb   w1,w2,[x3,0]\r
+\r
+       stxrh   w1,w2,[x3]\r
+       stxrh   w1,w2,[x3,0]\r
+\r
+       sub     sp,sp,0x123\r
+       sub     sp,x2,0x123\r
+       sub     w1,w2,0x123\r
+       sub     w4,w8,0x123,lsl 12\r
+       sub     wsp,w2,0x123\r
+       sub     wsp,wsp,0x123\r
+       sub     w1,w2,wzr\r
+       sub     w1,w2,w3\r
+       sub     w1,w2,w3,asr 1\r
+       sub     w1,w2,w3,lsl 1\r
+       sub     w1,w2,w3,lsr 1\r
+       sub     w1,w2,w3,sxtb\r
+       sub     w1,w2,w3,sxtb 1\r
+       sub     w1,w2,w3,sxth\r
+       sub     w1,w2,w3,sxth 1\r
+       sub     w1,w2,w3,sxtw\r
+       sub     w1,w2,w3,sxtw 1\r
+       sub     w1,w2,w3,uxtb\r
+       sub     w1,w2,w3,uxtb 1\r
+       sub     w1,w2,w3,uxth\r
+       sub     w1,w2,w3,uxth 1\r
+       sub     w1,w2,w3,uxtw\r
+       sub     w1,w2,w3,uxtw 1\r
+       sub     w1,wsp,w2,uxtw 2\r
+       sub     w1,wsp,w3,uxtw\r
+       sub     w1,wsp,w3,uxtw 1\r
+       sub     wsp,w2,w3,uxtw\r
+       sub     wsp,wsp,w3,uxtw\r
+       sub     wzr,w2,w3\r
+       sub     wzr,w2,wzr\r
+       sub     wzr,wzr,w3\r
+       sub     wzr,wzr,wzr\r
+       sub     x1,x2,x3\r
+       sub     x1,x2,0x123\r
+       sub     x1,x2,0xFFF\r
+       sub     x1,x2,0xFFF,lsl 12\r
+       sub     x1,sp,0x123\r
+       sub     x1,sp,x3,uxtx\r
+       sub     x1,sp,x3,uxtx 4\r
+       sub     x1,x2,w3,sxtb\r
+       sub     x1,x2,w3,sxtb 2\r
+       sub     x1,x2,w3,sxth\r
+       sub     x1,x2,w3,sxth 2\r
+       sub     x1,x2,w3,sxtw\r
+       sub     x1,x2,w3,sxtw 2\r
+       sub     x1,x2,w3,uxtb\r
+       sub     x1,x2,w3,uxtb 2\r
+       sub     x1,x2,w3,uxth\r
+       sub     x1,x2,w3,uxth 2\r
+       sub     x1,x2,w3,uxtw\r
+       sub     x1,x2,w3,uxtw 2\r
+       sub     x1,x2,x3,asr 1\r
+       sub     x1,x2,x3,asr 63\r
+       sub     x1,x2,x3,lsl 1\r
+       sub     x1,x2,x3,lsr 1\r
+       sub     x1,x2,x3,sxtx\r
+       sub     x1,x2,x3,sxtx 3\r
+       sub     x1,x2,x3,uxtx\r
+       sub     x1,x2,x3,uxtx 2\r
+\r
+       subs    w1,w2,w3\r
+       subs    w1,w2,wzr\r
+       subs    w1,wsp,0x123\r
+       subs    w1,wsp,w3,uxtw\r
+       subs    w1,wsp,w2,uxtw 2\r
+       subs    w1,wzr,w3\r
+       subs    w1,wzr,wzr\r
+       subs    w8,w16,0x123,lsl 12\r
+       subs    x8,x16,0x123,lsl 12\r
+       subs    x1,x2,x3,asr 63\r
+\r
+       svc     0xFFFF\r
+\r
+       sxtb    w1,w2\r
+       sxtb    x1,w2\r
+\r
+       sxth    w1,w2\r
+       sxth    x1,w2\r
+\r
+       sxtw    x1,w2\r
+\r
+       sys     1,c2,c3,4\r
+       sys     1,c2,c3,4,x5\r
+\r
+       sysl    x1,2,c3,c4,5\r
+\r
+       label_tbnz:\r
+       tbnz    w1,2,label_tbnz\r
+       tbnz    x1,63,label_tbnz\r
+\r
+       label_tbz:\r
+       tbz     w1,2,label_tbz\r
+       tbz     x1,63,label_tbz\r
+\r
+       tlbi    alle1\r
+       tlbi    aside1,x1\r
+\r
+       tst     w1,0x0000000E\r
+       tst     w1,w2\r
+       tst     w2,w3,asr 4\r
+       tst     w2,w3,lsl 4\r
+       tst     w2,w3,lsr 4\r
+       tst     w2,w3,ror 4\r
+       tst     x1,0x00000000000FFE00\r
+       tst     x1,x2\r
+       tst     x2,x3,ror 4\r
+\r
+       ubfiz   w1,w2,3,28\r
+       ubfiz   x1,x2,3,60\r
+\r
+       ubfm    w1,w2,3,31\r
+       ubfm    x1,x2,3,31\r
+\r
+       ubfx    w1,w2,3,4\r
+       ubfx    x1,x2,3,29\r
+\r
+       udiv    w1,w2,w3\r
+       udiv    x1,x2,x3\r
+\r
+       umaddl  x1,w2,w3,x4\r
+\r
+       umnegl  x1,w2,w3\r
+\r
+       umsubl  x1,w2,w3,x4\r
+\r
+       umull   x1,w2,w3\r
+\r
+       umulh   x1,x2,x3\r
+\r
+       uxtb    w1,w2\r
+\r
+       uxth    w1,w2\r
+\r
+       wfe\r
+\r
+       wfi\r
+\r
+       yield\r
+\r
+processor CPU64_FP\r
+\r
+       fabd    d1,d2,d3\r
+       fabd    s1,s2,s3\r
+       fabd    v1.2d,v2.2d,v3.2d\r
+       fabd    v1.2s,v2.2s,v3.2s\r
+       fabd    v1.4s,v2.4s,v3.4s\r
+\r
+       fabs    d1,d2\r
+       fabs    s1,s2\r
+       fabs    v1.2d,v2.2d\r
+       fabs    v1.2s,v2.2s\r
+       fabs    v1.4s,v2.4s\r
+\r
+       facge   d1,d2,d3\r
+       facge   s1,s2,s3\r
+       facge   v1.2d,v2.2d,v3.2d\r
+       facge   v1.2s,v2.2s,v3.2s\r
+       facge   v1.4s,v2.4s,v3.4s\r
+\r
+       facgt   d1,d2,d3\r
+       facgt   s1,s2,s3\r
+       facgt   v1.2d,v2.2d,v3.2d\r
+       facgt   v1.2s,v2.2s,v3.2s\r
+       facgt   v1.4s,v2.4s,v3.4s\r
+\r
+       fadd    d1,d2,d3\r
+       fadd    s1,s2,s3\r
+       fadd    v1.2d,v2.2d,v3.2d\r
+       fadd    v1.2s,v2.2s,v3.2s\r
+       fadd    v1.4s,v2.4s,v3.4s\r
+\r
+       faddp   d1,v2.2d\r
+       faddp   s1,v2.2s\r
+       faddp   v1.2d,v2.2d,v3.2d\r
+       faddp   v1.2s,v2.2s,v3.2s\r
+       faddp   v1.4s,v2.4s,v3.4s\r
+\r
+       fccmp   d1,d2,0x1,ge\r
+       fccmp   s1,s2,0x0,hs\r
+\r
+       fccmpe  d1,d2,0x1,ge\r
+       fccmpe  s1,s2,0x0,hs\r
+\r
+       fcmeq   d1,d2,0\r
+       fcmeq   d1,d2,d3\r
+       fcmeq   s1,s2,0\r
+       fcmeq   s1,s2,s3\r
+       fcmeq   v1.2d,v2.2d,0\r
+       fcmeq   v1.2d,v2.2d,v3.2d\r
+       fcmeq   v1.2s,v2.2s,0\r
+       fcmeq   v1.2s,v2.2s,v3.2s\r
+       fcmeq   v1.4s,v2.4s,0\r
+       fcmeq   v1.4s,v2.4s,v3.4s\r
+\r
+       fcmge   d1,d2,0\r
+       fcmge   d1,d2,d3\r
+       fcmge   s1,s2,0\r
+       fcmge   s1,s2,s3\r
+       fcmge   v1.2d,v2.2d,0\r
+       fcmge   v1.2d,v2.2d,v3.2d\r
+       fcmge   v1.2s,v2.2s,0\r
+       fcmge   v1.2s,v2.2s,v3.2s\r
+       fcmge   v1.4s,v2.4s,0\r
+       fcmge   v1.4s,v2.4s,v3.4s\r
+\r
+       fcmgt   d1,d2,0\r
+       fcmgt   d1,d2,d3\r
+       fcmgt   s1,s2,0\r
+       fcmgt   s1,s2,s3\r
+       fcmgt   v1.2d,v2.2d,0\r
+       fcmgt   v1.2d,v2.2d,v3.2d\r
+       fcmgt   v1.2s,v2.2s,0\r
+       fcmgt   v1.2s,v2.2s,v3.2s\r
+       fcmgt   v1.4s,v2.4s,0\r
+       fcmgt   v1.4s,v2.4s,v3.4s\r
+\r
+       fcmle   d1,d2,0\r
+       fcmle   s1,s2,0\r
+       fcmle   v1.2d,v2.2d,0\r
+       fcmle   v1.2s,v2.2s,0\r
+       fcmle   v1.4s,v2.4s,0\r
+\r
+       fcmlt   d1,d2,0\r
+       fcmlt   s1,s2,0\r
+       fcmlt   v1.2d,v2.2d,0\r
+       fcmlt   v1.2s,v2.2s,0\r
+       fcmlt   v1.4s,v2.4s,0\r
+\r
+       fcmp    d1,0.0\r
+       fcmp    d1,d2\r
+       fcmp    s1,0.0\r
+       fcmp    s1,s2\r
+\r
+       fcmpe   d1,0.0\r
+       fcmpe   d1,d2\r
+       fcmpe   s1,0.0\r
+       fcmpe   s1,s2\r
+\r
+       fcsel   d1,d2,d3,vs\r
+       fcsel   s1,s2,s3,ls\r
+\r
+       fcvt    d1,h2\r
+       fcvt    d1,s2\r
+       fcvt    h1,d2\r
+       fcvt    h1,s2\r
+       fcvt    s1,d2\r
+       fcvt    s1,h2\r
+\r
+       fcvtas  d1,d2\r
+       fcvtas  s1,s2\r
+       fcvtas  v1.2d,v2.2d\r
+       fcvtas  v1.2s,v2.2s\r
+       fcvtas  v1.4s,v2.4s\r
+       fcvtas  w1,d2\r
+       fcvtas  w1,s2\r
+       fcvtas  x1,d2\r
+       fcvtas  x1,s2\r
+\r
+       fcvtau  d1,d2\r
+       fcvtau  s1,s2\r
+       fcvtau  v1.2d,v2.2d\r
+       fcvtau  v1.2s,v2.2s\r
+       fcvtau  v1.4s,v2.4s\r
+       fcvtau  w1,d2\r
+       fcvtau  w1,s2\r
+       fcvtau  x1,d2\r
+       fcvtau  x1,s2\r
+\r
+       fcvtl   v1.2d,v2.2s\r
+       fcvtl   v1.4s,v2.4h\r
+\r
+       fcvtl2  v1.2d,v2.4s\r
+       fcvtl2  v1.4s,v2.8h\r
+\r
+       fcvtms  d1,d2\r
+       fcvtms  s1,s2\r
+       fcvtms  v1.2d,v2.2d\r
+       fcvtms  v1.2s,v2.2s\r
+       fcvtms  v1.4s,v2.4s\r
+       fcvtms  w1,d2\r
+       fcvtms  w1,s2\r
+       fcvtms  x1,d2\r
+       fcvtms  x1,s2\r
+\r
+       fcvtmu  d1,d2\r
+       fcvtmu  s1,s2\r
+       fcvtmu  v1.2d,v2.2d\r
+       fcvtmu  v1.2s,v2.2s\r
+       fcvtmu  v1.4s,v2.4s\r
+       fcvtmu  w1,d2\r
+       fcvtmu  w1,s2\r
+       fcvtmu  x1,d2\r
+       fcvtmu  x1,s2\r
+\r
+       fcvtn   v1.2s,v2.2d\r
+       fcvtn   v1.4h,v2.4s\r
+\r
+       fcvtn2  v1.4s,v2.2d\r
+       fcvtn2  v1.8h,v2.4s\r
+\r
+       fcvtns  d1,d2\r
+       fcvtns  s1,s2\r
+       fcvtns  v1.2d,v2.2d\r
+       fcvtns  v1.2s,v2.2s\r
+       fcvtns  v1.4s,v2.4s\r
+       fcvtns  w1,d2\r
+       fcvtns  w1,s2\r
+       fcvtns  x1,d2\r
+       fcvtns  x1,s2\r
+\r
+       fcvtnu  d1,d2\r
+       fcvtnu  s1,s2\r
+       fcvtnu  v1.2d,v2.2d\r
+       fcvtnu  v1.2s,v2.2s\r
+       fcvtnu  v1.4s,v2.4s\r
+       fcvtnu  w1,d2\r
+       fcvtnu  w1,s2\r
+       fcvtnu  x1,d2\r
+       fcvtnu  x1,s2\r
+\r
+       fcvtps  d1,d2\r
+       fcvtps  s1,s2\r
+       fcvtps  v1.2d,v2.2d\r
+       fcvtps  v1.2s,v2.2s\r
+       fcvtps  v1.4s,v2.4s\r
+       fcvtps  w1,d2\r
+       fcvtps  w1,s2\r
+       fcvtps  x1,d2\r
+       fcvtps  x1,s2\r
+\r
+       fcvtpu  d1,d2\r
+       fcvtpu  s1,s2\r
+       fcvtpu  v1.2d,v2.2d\r
+       fcvtpu  v1.2s,v2.2s\r
+       fcvtpu  v1.4s,v2.4s\r
+       fcvtpu  w1,d2\r
+       fcvtpu  w1,s2\r
+       fcvtpu  x1,d2\r
+       fcvtpu  x1,s2\r
+\r
+       fcvtxn  s1,d2\r
+       fcvtxn  v1.2s,v2.2d\r
+\r
+       fcvtxn2 v1.4s,v2.2d\r
+\r
+       fcvtzs  d1,d2\r
+       fcvtzs  d1,d2,5\r
+       fcvtzs  s1,s2\r
+       fcvtzs  s1,s2,5\r
+       fcvtzs  v1.2d,v2.2d\r
+       fcvtzs  v1.2d,v2.2d,5\r
+       fcvtzs  v1.2s,v2.2s\r
+       fcvtzs  v1.2s,v2.2s,5\r
+       fcvtzs  v1.4s,v2.4s\r
+       fcvtzs  v1.4s,v2.4s,5\r
+       fcvtzs  w1,d2\r
+       fcvtzs  w1,d2,5\r
+       fcvtzs  w1,s2\r
+       fcvtzs  w1,s2,5\r
+       fcvtzs  x1,d2\r
+       fcvtzs  x1,d2,5\r
+       fcvtzs  x1,s2\r
+       fcvtzs  x1,s2,5\r
+\r
+       fcvtzu  d1,d2\r
+       fcvtzu  d1,d2,5\r
+       fcvtzu  s1,s2\r
+       fcvtzu  s1,s2,5\r
+       fcvtzu  v1.2d,v2.2d\r
+       fcvtzu  v1.2d,v2.2d,5\r
+       fcvtzu  v1.2s,v2.2s\r
+       fcvtzu  v1.2s,v2.2s,5\r
+       fcvtzu  v1.4s,v2.4s\r
+       fcvtzu  v1.4s,v2.4s,5\r
+       fcvtzu  w1,d2\r
+       fcvtzu  w1,d2,5\r
+       fcvtzu  w1,s2\r
+       fcvtzu  w1,s2,5\r
+       fcvtzu  x1,d2\r
+       fcvtzu  x1,d2,5\r
+       fcvtzu  x1,s2\r
+       fcvtzu  x1,s2,5\r
+\r
+       fdiv    d1,d2,d3\r
+       fdiv    s1,s2,s3\r
+       fdiv    v1.2d,v2.2d,v3.2d\r
+       fdiv    v1.2s,v2.2s,v3.2s\r
+       fdiv    v1.4s,v2.4s,v3.4s\r
+\r
+       fmadd   d1,d2,d3,d4\r
+       fmadd   s1,s2,s3,s4\r
+\r
+       fmax    d1,d2,d3\r
+       fmax    s1,s2,s3\r
+       fmax    v1.2d,v2.2d,v3.2d\r
+       fmax    v1.2s,v2.2s,v3.2s\r
+       fmax    v1.4s,v2.4s,v3.4s\r
+\r
+       fmaxnm  d1,d2,d3\r
+       fmaxnm  s1,s2,s3\r
+       fmaxnm  v1.2d,v2.2d,v3.2d\r
+       fmaxnm  v1.2s,v2.2s,v3.2s\r
+       fmaxnm  v1.4s,v2.4s,v3.4s\r
+\r
+       fmaxnmp d1,v2.2d\r
+       fmaxnmp s1,v2.2s\r
+       fmaxnmp v1.2d,v2.2d,v3.2d\r
+       fmaxnmp v1.2s,v2.2s,v3.2s\r
+       fmaxnmp v1.4s,v2.4s,v3.4s\r
+\r
+       fmaxnmv s1,v2.4s\r
+\r
+       fmaxp   d1,v2.2d\r
+       fmaxp   s1,v2.2s\r
+       fmaxp   v1.2d,v2.2d,v3.2d\r
+       fmaxp   v1.2s,v2.2s,v3.2s\r
+       fmaxp   v1.4s,v2.4s,v3.4s\r
+\r
+       fmaxv   s1,v2.4s\r
+\r
+       fmin    d1,d2,d3\r
+       fmin    s1,s2,s3\r
+       fmin    v1.2d,v2.2d,v3.2d\r
+       fmin    v1.2s,v2.2s,v3.2s\r
+       fmin    v1.4s,v2.4s,v3.4s\r
+\r
+       fminnm  d1,d2,d3\r
+       fminnm  s1,s2,s3\r
+       fminnm  v1.2d,v2.2d,v3.2d\r
+       fminnm  v1.2s,v2.2s,v3.2s\r
+       fminnm  v1.4s,v2.4s,v3.4s\r
+\r
+       fminnmp d1,v2.2d\r
+       fminnmp s1,v2.2s\r
+       fminnmp v1.2d,v2.2d,v3.2d\r
+       fminnmp v1.2s,v2.2s,v3.2s\r
+       fminnmp v1.4s,v2.4s,v3.4s\r
+\r
+       fminnmv s1,v2.4s\r
+\r
+       fminp   d1,v2.2d\r
+       fminp   s1,v2.2s\r
+       fminp   v1.2d,v2.2d,v3.2d\r
+       fminp   v1.2s,v2.2s,v3.2s\r
+       fminp   v1.4s,v2.4s,v3.4s\r
+\r
+       fminv   s1,v2.4s\r
+\r
+       fmla    d1,d2,v3.d[1]\r
+       fmla    s1,s2,v3.s[3]\r
+       fmla    v1.2d,v2.2d,v3.2d\r
+       fmla    v1.2d,v2.2d,v3.d[0]\r
+       fmla    v1.2s,v2.2s,v3.2s\r
+       fmla    v1.2s,v2.2s,v3.s[2]\r
+       fmla    v1.4s,v2.4s,v3.4s\r
+       fmla    v1.4s,v2.4s,v3.s[1]\r
+\r
+       fmls    d1,d2,v3.d[1]\r
+       fmls    s1,s2,v3.s[3]\r
+       fmls    v1.2d,v2.2d,v3.2d\r
+       fmls    v1.2d,v2.2d,v3.d[0]\r
+       fmls    v1.2s,v2.2s,v3.2s\r
+       fmls    v1.2s,v2.2s,v3.s[2]\r
+       fmls    v1.4s,v2.4s,v3.4s\r
+       fmls    v1.4s,v2.4s,v3.s[1]\r
+\r
+       fmov    d1,3.375\r
+       fmov    d1,d2\r
+       fmov    d1,x2\r
+       fmov    s1,4.25\r
+       fmov    s1,s2\r
+       fmov    s1,w2\r
+       fmov    v1.2d,7.75\r
+       fmov    v1.2s,5.5\r
+       fmov    v1.4s,6.75\r
+       fmov    v1.d[1],x2\r
+       fmov    w1,s2\r
+       fmov    x1,d2\r
+       fmov    x1,v2.d[1]\r
+\r
+       fmsub   d1,d2,d3,d4\r
+       fmsub   s1,s2,s3,s4\r
+\r
+       fmul    d1,d2,d3\r
+       fmul    d1,d2,v3.d[1]\r
+       fmul    s1,s2,s3\r
+       fmul    s1,s2,v3.s[3]\r
+       fmul    v1.2d,v2.2d,v3.2d\r
+       fmul    v1.2d,v2.2d,v3.d[0]\r
+       fmul    v1.2s,v2.2s,v3.2s\r
+       fmul    v1.2s,v2.2s,v3.s[2]\r
+       fmul    v1.4s,v2.4s,v3.4s\r
+       fmul    v1.4s,v2.4s,v3.s[1]\r
+\r
+       fmulx   d1,d2,d3\r
+       fmulx   d1,d2,v3.d[1]\r
+       fmulx   s1,s2,s3\r
+       fmulx   s1,s2,v3.s[3]\r
+       fmulx   v1.2d,v2.2d,v3.2d\r
+       fmulx   v1.2d,v2.2d,v3.d[0]\r
+       fmulx   v1.2s,v2.2s,v3.2s\r
+       fmulx   v1.2s,v2.2s,v3.s[2]\r
+       fmulx   v1.4s,v2.4s,v3.4s\r
+       fmulx   v1.4s,v2.4s,v3.s[1]\r
+\r
+       fneg    d1,d2\r
+       fneg    s1,s2\r
+       fneg    v1.2d,v2.2d\r
+       fneg    v1.2s,v2.2s\r
+       fneg    v1.4s,v2.4s\r
+\r
+       fnmadd  d1,d2,d3,d4\r
+       fnmadd  s1,s2,s3,s4\r
+\r
+       fnmsub  d1,d2,d3,d4\r
+       fnmsub  s1,s2,s3,s4\r
+\r
+       fnmul   d1,d2,d3\r
+       fnmul   s1,s2,s3\r
+\r
+       frecpe  d1,d2\r
+       frecpe  s1,s2\r
+       frecpe  v1.2d,v2.2d\r
+       frecpe  v1.2s,v2.2s\r
+       frecpe  v1.4s,v2.4s\r
+\r
+       frecps  d1,d2,d3\r
+       frecps  s1,s2,s3\r
+       frecps  v1.2d,v2.2d,v3.2d\r
+       frecps  v1.2s,v2.2s,v3.2s\r
+       frecps  v1.4s,v2.4s,v3.4s\r
+\r
+       frecpx  d1,d2\r
+       frecpx  s1,s2\r
+\r
+       frinta  d1,d2\r
+       frinta  s1,s2\r
+       frinta  v1.2d,v2.2d\r
+       frinta  v1.2s,v2.2s\r
+       frinta  v1.4s,v2.4s\r
+\r
+       frinti  d1,d2\r
+       frinti  s1,s2\r
+       frinti  v1.2d,v2.2d\r
+       frinti  v1.2s,v2.2s\r
+       frinti  v1.4s,v2.4s\r
+\r
+       frintm  d1,d2\r
+       frintm  s1,s2\r
+       frintm  v1.2d,v2.2d\r
+       frintm  v1.2s,v2.2s\r
+       frintm  v1.4s,v2.4s\r
+\r
+       frintn  d1,d2\r
+       frintn  s1,s2\r
+       frintn  v1.2d,v2.2d\r
+       frintn  v1.2s,v2.2s\r
+       frintn  v1.4s,v2.4s\r
+\r
+       frintp  d1,d2\r
+       frintp  s1,s2\r
+       frintp  v1.2d,v2.2d\r
+       frintp  v1.2s,v2.2s\r
+       frintp  v1.4s,v2.4s\r
+\r
+       frintx  d1,d2\r
+       frintx  s1,s2\r
+       frintx  v1.2d,v2.2d\r
+       frintx  v1.2s,v2.2s\r
+       frintx  v1.4s,v2.4s\r
+\r
+       frintz  d1,d2\r
+       frintz  s1,s2\r
+       frintz  v1.2d,v2.2d\r
+       frintz  v1.2s,v2.2s\r
+       frintz  v1.4s,v2.4s\r
+\r
+       frsqrte d1,d2\r
+       frsqrte s1,s2\r
+       frsqrte v1.2d,v2.2d\r
+       frsqrte v1.2s,v2.2s\r
+       frsqrte v1.4s,v2.4s\r
+       frsqrts d1,d2,d3\r
+       frsqrts s1,s2,s3\r
+       frsqrts v1.2d,v2.2d,v3.2d\r
+       frsqrts v1.2s,v2.2s,v3.2s\r
+       frsqrts v1.4s,v2.4s,v3.4s\r
+\r
+       fsqrt   d1,d2\r
+       fsqrt   s1,s2\r
+       fsqrt   v1.2d,v2.2d\r
+       fsqrt   v1.2s,v2.2s\r
+       fsqrt   v1.4s,v2.4s\r
+\r
+       fsub    d1,d2,d3\r
+       fsub    s1,s2,s3\r
+       fsub    v1.2d,v2.2d,v3.2d\r
+       fsub    v1.2s,v2.2s,v3.2s\r
+       fsub    v1.4s,v2.4s,v3.4s\r
+\r
+       scvtf   d1,d2\r
+       scvtf   d1,d2,5\r
+       scvtf   d2,w1\r
+       scvtf   d2,w1,5\r
+       scvtf   d2,x1\r
+       scvtf   d2,x1,5\r
+       scvtf   s1,s2\r
+       scvtf   s1,s2,5\r
+       scvtf   s2,w1\r
+       scvtf   s2,w1,5\r
+       scvtf   s2,x1\r
+       scvtf   s2,x1,5\r
+       scvtf   v1.2d,v2.2d\r
+       scvtf   v1.2d,v2.2d,5\r
+       scvtf   v1.2s,v2.2s\r
+       scvtf   v1.2s,v2.2s,5\r
+       scvtf   v1.4s,v2.4s\r
+       scvtf   v1.4s,v2.4s,5\r
+\r
+       ucvtf   d1,d2\r
+       ucvtf   d1,d2,5\r
+       ucvtf   d2,w1\r
+       ucvtf   d2,w1,5\r
+       ucvtf   d2,x1\r
+       ucvtf   d2,x1,5\r
+       ucvtf   s1,s2\r
+       ucvtf   s1,s2,5\r
+       ucvtf   s2,w1\r
+       ucvtf   s2,w1,5\r
+       ucvtf   s2,x1\r
+       ucvtf   s2,x1,5\r
+       ucvtf   v1.2d,v2.2d\r
+       ucvtf   v1.2d,v2.2d,5\r
+       ucvtf   v1.2s,v2.2s\r
+       ucvtf   v1.2s,v2.2s,5\r
+       ucvtf   v1.4s,v2.4s\r
+       ucvtf   v1.4s,v2.4s,5\r
+\r
+       urecpe  v1.2s,v2.2s\r
+       urecpe  v1.4s,v2.4s\r
+\r
+       ursqrte v1.2s,v2.2s\r
+       ursqrte v1.4s,v2.4s\r
+\r
+processor CPU64_SIMD\r
+\r
+       abs     d1,d2\r
+       abs     v1.16b,v2.16b\r
+       abs     v1.2d,v2.2d\r
+       abs     v1.2s,v2.2s\r
+       abs     v1.4h,v2.4h\r
+       abs     v1.4s,v2.4s\r
+       abs     v1.8b,v2.8b\r
+       abs     v1.8h,v2.8h\r
+\r
+       add     d1,d2,d3\r
+       add     v1.16b,v2.16b,v3.16b\r
+       add     v1.2d,v2.2d,v3.2d\r
+       add     v1.2s,v2.2s,v3.2s\r
+       add     v1.4h,v2.4h,v3.4h\r
+       add     v1.4s,v2.4s,v3.4s\r
+       add     v1.8b,v2.8b,v3.8b\r
+       add     v1.8h,v2.8h,v3.8h\r
+\r
+       addhn   v1.2s,v2.2d,v3.2d\r
+       addhn   v1.4h,v2.4s,v3.4s\r
+       addhn   v1.8b,v2.8h,v3.8h\r
+\r
+       addhn2  v1.16b,v2.8h,v3.8h\r
+       addhn2  v1.4s,v2.2d,v3.2d\r
+       addhn2  v1.8h,v2.4s,v3.4s\r
+\r
+       addp    d1,v2.2d\r
+       addp    v1.16b,v2.16b,v3.16b\r
+       addp    v1.2d,v2.2d,v3.2d\r
+       addp    v1.2s,v2.2s,v3.2s\r
+       addp    v1.4h,v2.4h,v3.4h\r
+       addp    v1.4s,v2.4s,v3.4s\r
+       addp    v1.8b,v2.8b,v3.8b\r
+       addp    v1.8h,v2.8h,v3.8h\r
+\r
+       addv    b1,v2.16b\r
+       addv    b1,v2.8b\r
+       addv    h1,v2.4h\r
+       addv    h1,v2.8h\r
+       addv    s1,v2.4s\r
+\r
+       and     v1.16b,v2.16b,v3.16b\r
+       and     v1.8b,v2.8b,v3.8b\r
+\r
+       bic     v1.16b,v2.16b,v3.16b\r
+       bic     v1.2s,0xFF\r
+       bic     v1.2s,0xFF,lsl 0\r
+       bic     v1.2s,0xFF,lsl 8\r
+       bic     v1.2s,0xFF,lsl 16\r
+       bic     v1.2s,0xFF,lsl 24\r
+       bic     v1.4h,0xFE\r
+       bic     v1.4h,0xFE,lsl 0\r
+       bic     v1.4h,0xFF,lsl 8\r
+       bic     v1.4s,0xFF\r
+       bic     v1.4s,0xFF,lsl 0\r
+       bic     v1.4s,0xFF,lsl 8\r
+       bic     v1.4s,0xFF,lsl 16\r
+       bic     v1.4s,0xFF,lsl 24\r
+       bic     v1.8b,v2.8b,v3.8b\r
+       bic     v1.8h,0xFF\r
+       bic     v1.8h,0xFF,lsl 0\r
+       bic     v1.8h,0xFF,lsl 8\r
+\r
+       bif     v1.16b,v2.16b,v3.16b\r
+       bif     v1.8b,v2.8b,v3.8b\r
+\r
+       bit     v1.16b,v2.16b,v3.16b\r
+       bit     v1.8b,v2.8b,v3.8b\r
+\r
+       bsl     v1.16b,v2.16b,v3.16b\r
+       bsl     v1.8b,v2.8b,v3.8b\r
+\r
+       cls     v1.16b,v2.16b\r
+       cls     v1.2s,v2.2s\r
+       cls     v1.4h,v2.4h\r
+       cls     v1.4s,v2.4s\r
+       cls     v1.8b,v2.8b\r
+       cls     v1.8h,v2.8h\r
+\r
+       clz     v1.16b,v2.16b\r
+       clz     v1.2s,v2.2s\r
+       clz     v1.4h,v2.4h\r
+       clz     v1.4s,v2.4s\r
+       clz     v1.8b,v2.8b\r
+       clz     v1.8h,v2.8h\r
+\r
+       cmeq    d1,d2,0\r
+       cmeq    d1,d2,d3\r
+       cmeq    v1.16b,v2.16b,0\r
+       cmeq    v1.16b,v2.16b,v3.16b\r
+       cmeq    v1.2d,v2.2d,0\r
+       cmeq    v1.2d,v2.2d,v3.2d\r
+       cmeq    v1.2s,v2.2s,0\r
+       cmeq    v1.2s,v2.2s,v3.2s\r
+       cmeq    v1.4h,v2.4h,0\r
+       cmeq    v1.4h,v2.4h,v3.4h\r
+       cmeq    v1.4s,v2.4s,0\r
+       cmeq    v1.4s,v2.4s,v3.4s\r
+       cmeq    v1.8b,v2.8b,0\r
+       cmeq    v1.8b,v2.8b,v3.8b\r
+       cmeq    v1.8h,v2.8h,0\r
+       cmeq    v1.8h,v2.8h,v3.8h\r
+\r
+       cmge    d1,d2,0\r
+       cmge    d1,d2,d3\r
+       cmge    v1.16b,v2.16b,0\r
+       cmge    v1.16b,v2.16b,v3.16b\r
+       cmge    v1.2d,v2.2d,0\r
+       cmge    v1.2d,v2.2d,v3.2d\r
+       cmge    v1.2s,v2.2s,0\r
+       cmge    v1.2s,v2.2s,v3.2s\r
+       cmge    v1.4h,v2.4h,0\r
+       cmge    v1.4h,v2.4h,v3.4h\r
+       cmge    v1.4s,v2.4s,0\r
+       cmge    v1.4s,v2.4s,v3.4s\r
+       cmge    v1.8b,v2.8b,0\r
+       cmge    v1.8b,v2.8b,v3.8b\r
+       cmge    v1.8h,v2.8h,0\r
+       cmge    v1.8h,v2.8h,v3.8h\r
+\r
+       cmgt    d1,d2,0\r
+       cmgt    d1,d2,d3\r
+       cmgt    v1.16b,v2.16b,0\r
+       cmgt    v1.16b,v2.16b,v3.16b\r
+       cmgt    v1.2d,v2.2d,0\r
+       cmgt    v1.2d,v2.2d,v3.2d\r
+       cmgt    v1.2s,v2.2s,0\r
+       cmgt    v1.2s,v2.2s,v3.2s\r
+       cmgt    v1.4h,v2.4h,0\r
+       cmgt    v1.4h,v2.4h,v3.4h\r
+       cmgt    v1.4s,v2.4s,0\r
+       cmgt    v1.4s,v2.4s,v3.4s\r
+       cmgt    v1.8b,v2.8b,0\r
+       cmgt    v1.8b,v2.8b,v3.8b\r
+       cmgt    v1.8h,v2.8h,0\r
+       cmgt    v1.8h,v2.8h,v3.8h\r
+\r
+       cmhi    d1,d2,d3\r
+       cmhi    v1.16b,v2.16b,v3.16b\r
+       cmhi    v1.2d,v2.2d,v3.2d\r
+       cmhi    v1.2s,v2.2s,v3.2s\r
+       cmhi    v1.4h,v2.4h,v3.4h\r
+       cmhi    v1.4s,v2.4s,v3.4s\r
+       cmhi    v1.8b,v2.8b,v3.8b\r
+       cmhi    v1.8h,v2.8h,v3.8h\r
+\r
+       cmhs    d1,d2,d3\r
+       cmhs    v1.16b,v2.16b,v3.16b\r
+       cmhs    v1.2d,v2.2d,v3.2d\r
+       cmhs    v1.2s,v2.2s,v3.2s\r
+       cmhs    v1.4h,v2.4h,v3.4h\r
+       cmhs    v1.4s,v2.4s,v3.4s\r
+       cmhs    v1.8b,v2.8b,v3.8b\r
+       cmhs    v1.8h,v2.8h,v3.8h\r
+\r
+       cmle    d1,d2,0\r
+       cmle    v1.16b,v2.16b,0\r
+       cmle    v1.2d,v2.2d,0\r
+       cmle    v1.2s,v2.2s,0\r
+       cmle    v1.4h,v2.4h,0\r
+       cmle    v1.4s,v2.4s,0\r
+       cmle    v1.8b,v2.8b,0\r
+       cmle    v1.8h,v2.8h,0\r
+\r
+       cmlt    d1,d2,0\r
+       cmlt    v1.16b,v2.16b,0\r
+       cmlt    v1.2d,v2.2d,0\r
+       cmlt    v1.2s,v2.2s,0\r
+       cmlt    v1.4h,v2.4h,0\r
+       cmlt    v1.4s,v2.4s,0\r
+       cmlt    v1.8b,v2.8b,0\r
+       cmlt    v1.8h,v2.8h,0\r
+\r
+       cmtst   d1,d2,d3\r
+       cmtst   v1.16b,v2.16b,v3.16b\r
+       cmtst   v1.2d,v2.2d,v3.2d\r
+       cmtst   v1.2s,v2.2s,v3.2s\r
+       cmtst   v1.4h,v2.4h,v3.4h\r
+       cmtst   v1.4s,v2.4s,v3.4s\r
+       cmtst   v1.8b,v2.8b,v3.8b\r
+       cmtst   v1.8h,v2.8h,v3.8h\r
+\r
+       cnt     v1.16b,v2.16b\r
+       cnt     v1.8b,v2.8b\r
+\r
+       dup     v1.16b,v2.b[15]\r
+       dup     v1.16b,w2\r
+       dup     v1.2d,v2.d[1]\r
+       dup     v1.2d,x2\r
+       dup     v1.2s,v2.s[1]\r
+       dup     v1.2s,w2\r
+       dup     v1.4h,v2.h[1]\r
+       dup     v1.4h,w2\r
+       dup     v1.4s,v2.s[3]\r
+       dup     v1.4s,w2\r
+       dup     v1.8b,v2.b[1]\r
+       dup     v1.8b,w2\r
+       dup     v1.8h,v2.h[7]\r
+       dup     v1.8h,w2\r
+\r
+       eor     v1.16b,v2.16b,v3.16b\r
+       eor     v1.8b,v2.8b,v3.8b\r
+\r
+       ext     v1.16b,v2.16b,v3.16b,15\r
+       ext     v1.8b,v2.8b,v3.8b,7\r
+\r
+       ins     v2.b[15],w1\r
+       ins     v2.h[7],w1\r
+       ins     v2.s[3],w1\r
+       ins     v2.d[1],x1\r
+\r
+       ins     v1.b[15],v2.b[1]\r
+       ins     v1.b[1],v2.b[15]\r
+       ins     v1.h[7],v2.h[1]\r
+       ins     v1.h[1],v2.h[7]\r
+       ins     v1.s[3],v2.s[1]\r
+       ins     v1.s[1],v2.s[3]\r
+       ins     v1.d[1],v2.d[0]\r
+       ins     v1.d[0],v2.d[1]\r
+\r
+       ld1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp]\r
+       ld1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp],64\r
+       ld1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp],x6\r
+       ld1     {v1.16b,v2.16b,v3.16b},[x4]\r
+       ld1     {v1.16b,v2.16b,v3.16b},[x4],48\r
+       ld1     {v1.16b,v2.16b,v3.16b},[x4],x5\r
+       ld1     {v1.16b,v2.16b},[x3]\r
+       ld1     {v1.16b,v2.16b},[x3],32\r
+       ld1     {v1.16b,v2.16b},[x3],x4\r
+       ld1     {v1.16b},[x2]\r
+       ld1     {v1.16b},[x2],16\r
+       ld1     {v1.16b},[x2],x3\r
+       ld1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp]\r
+       ld1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp],32\r
+       ld1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp],x6\r
+       ld1     {v1.1d,v2.1d,v3.1d},[x4]\r
+       ld1     {v1.1d,v2.1d,v3.1d},[x4],24\r
+       ld1     {v1.1d,v2.1d,v3.1d},[x4],x5\r
+       ld1     {v1.1d,v2.1d},[x3]\r
+       ld1     {v1.1d,v2.1d},[x3],16\r
+       ld1     {v1.1d,v2.1d},[x3],x4\r
+       ld1     {v1.1d},[x2]\r
+       ld1     {v1.1d},[x2],8\r
+       ld1     {v1.1d},[x2],x3\r
+       ld1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp]\r
+       ld1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp],64\r
+       ld1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp],x6\r
+       ld1     {v1.2d,v2.2d,v3.2d},[x4]\r
+       ld1     {v1.2d,v2.2d,v3.2d},[x4],48\r
+       ld1     {v1.2d,v2.2d,v3.2d},[x4],x5\r
+       ld1     {v1.2d,v2.2d},[x3]\r
+       ld1     {v1.2d,v2.2d},[x3],32\r
+       ld1     {v1.2d,v2.2d},[x3],x4\r
+       ld1     {v1.2d},[x2]\r
+       ld1     {v1.2d},[x2],16\r
+       ld1     {v1.2d},[x2],x3\r
+       ld1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp]\r
+       ld1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp],32\r
+       ld1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp],x6\r
+       ld1     {v1.2s,v2.2s,v3.2s},[x4]\r
+       ld1     {v1.2s,v2.2s,v3.2s},[x4],24\r
+       ld1     {v1.2s,v2.2s,v3.2s},[x4],x5\r
+       ld1     {v1.2s,v2.2s},[x3]\r
+       ld1     {v1.2s,v2.2s},[x3],16\r
+       ld1     {v1.2s,v2.2s},[x3],x4\r
+       ld1     {v1.2s},[x2]\r
+       ld1     {v1.2s},[x2],8\r
+       ld1     {v1.2s},[x2],x3\r
+       ld1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp]\r
+       ld1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp],32\r
+       ld1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp],x6\r
+       ld1     {v1.4h,v2.4h,v3.4h},[x4]\r
+       ld1     {v1.4h,v2.4h,v3.4h},[x4],24\r
+       ld1     {v1.4h,v2.4h,v3.4h},[x4],x5\r
+       ld1     {v1.4h,v2.4h},[x3]\r
+       ld1     {v1.4h,v2.4h},[x3],16\r
+       ld1     {v1.4h,v2.4h},[x3],x4\r
+       ld1     {v1.4h},[x2]\r
+       ld1     {v1.4h},[x2],8\r
+       ld1     {v1.4h},[x2],x3\r
+       ld1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp]\r
+       ld1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp],64\r
+       ld1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp],x6\r
+       ld1     {v1.4s,v2.4s,v3.4s},[x4]\r
+       ld1     {v1.4s,v2.4s,v3.4s},[x4],48\r
+       ld1     {v1.4s,v2.4s,v3.4s},[x4],x5\r
+       ld1     {v1.4s,v2.4s},[x3]\r
+       ld1     {v1.4s,v2.4s},[x3],32\r
+       ld1     {v1.4s,v2.4s},[x3],x4\r
+       ld1     {v1.4s},[x2]\r
+       ld1     {v1.4s},[x2],16\r
+       ld1     {v1.4s},[x2],x3\r
+       ld1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp]\r
+       ld1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp],32\r
+       ld1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp],x6\r
+       ld1     {v1.8b,v2.8b,v3.8b},[x4]\r
+       ld1     {v1.8b,v2.8b,v3.8b},[x4],24\r
+       ld1     {v1.8b,v2.8b,v3.8b},[x4],x5\r
+       ld1     {v1.8b,v2.8b},[x3]\r
+       ld1     {v1.8b,v2.8b},[x3],16\r
+       ld1     {v1.8b,v2.8b},[x3],x4\r
+       ld1     {v1.8b},[x2]\r
+       ld1     {v1.8b},[x2],8\r
+       ld1     {v1.8b},[x2],x3\r
+       ld1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp]\r
+       ld1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp],64\r
+       ld1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp],x6\r
+       ld1     {v1.8h,v2.8h,v3.8h},[x4]\r
+       ld1     {v1.8h,v2.8h,v3.8h},[x4],48\r
+       ld1     {v1.8h,v2.8h,v3.8h},[x4],x5\r
+       ld1     {v1.8h,v2.8h},[x3]\r
+       ld1     {v1.8h,v2.8h},[x3],32\r
+       ld1     {v1.8h,v2.8h},[x3],x4\r
+       ld1     {v1.8h},[x2]\r
+       ld1     {v1.8h},[x2],16\r
+       ld1     {v1.8h},[x2],x3\r
+       ld1     {v1.b}[2],[x3]\r
+       ld1     {v1.b}[2],[x3],1\r
+       ld1     {v1.b}[2],[x3],x4\r
+       ld1     {v1.d}[1],[x3]\r
+       ld1     {v1.d}[1],[x3],8\r
+       ld1     {v1.d}[1],[x3],x4\r
+       ld1     {v1.h}[2],[x3]\r
+       ld1     {v1.h}[2],[x3],2\r
+       ld1     {v1.h}[2],[x3],x4\r
+       ld1     {v1.s}[2],[x3]\r
+       ld1     {v1.s}[2],[x3],4\r
+       ld1     {v1.s}[2],[x3],x4\r
+\r
+       ld1r    {v1.16b},[x2]\r
+       ld1r    {v1.16b},[x2],1\r
+       ld1r    {v1.16b},[x2],x3\r
+       ld1r    {v1.1d},[x2]\r
+       ld1r    {v1.1d},[x2],8\r
+       ld1r    {v1.1d},[x2],x3\r
+       ld1r    {v1.2d},[x2]\r
+       ld1r    {v1.2d},[x2],8\r
+       ld1r    {v1.2d},[x2],x3\r
+       ld1r    {v1.2s},[x2]\r
+       ld1r    {v1.2s},[x2],4\r
+       ld1r    {v1.2s},[x2],x3\r
+       ld1r    {v1.4h},[x2]\r
+       ld1r    {v1.4h},[x2],2\r
+       ld1r    {v1.4h},[x2],x3\r
+       ld1r    {v1.4s},[x2]\r
+       ld1r    {v1.4s},[x2],4\r
+       ld1r    {v1.4s},[x2],x3\r
+       ld1r    {v1.8b},[x2]\r
+       ld1r    {v1.8b},[x2],1\r
+       ld1r    {v1.8b},[x2],x3\r
+       ld1r    {v1.8h},[x2]\r
+       ld1r    {v1.8h},[x2],2\r
+       ld1r    {v1.8h},[x2],x3\r
+\r
+       ld2     {v1.16b,v2.16b},[x3]\r
+       ld2     {v1.16b,v2.16b},[x3],32\r
+       ld2     {v1.16b,v2.16b},[x3],x4\r
+       ld2     {v1.2d,v2.2d},[x3]\r
+       ld2     {v1.2d,v2.2d},[x3],32\r
+       ld2     {v1.2d,v2.2d},[x3],x4\r
+       ld2     {v1.2s,v2.2s},[x3]\r
+       ld2     {v1.2s,v2.2s},[x3],16\r
+       ld2     {v1.2s,v2.2s},[x3],x4\r
+       ld2     {v1.4h,v2.4h},[x3]\r
+       ld2     {v1.4h,v2.4h},[x3],16\r
+       ld2     {v1.4h,v2.4h},[x3],x4\r
+       ld2     {v1.4s,v2.4s},[x3]\r
+       ld2     {v1.4s,v2.4s},[x3],32\r
+       ld2     {v1.4s,v2.4s},[x3],x4\r
+       ld2     {v1.8b,v2.8b},[x3]\r
+       ld2     {v1.8b,v2.8b},[x3],16\r
+       ld2     {v1.8b,v2.8b},[x3],x4\r
+       ld2     {v1.8h,v2.8h},[x3]\r
+       ld2     {v1.8h,v2.8h},[x3],32\r
+       ld2     {v1.8h,v2.8h},[x3],x4\r
+       ld2     {v1.b,v2.b}[15],[x3]\r
+       ld2     {v1.b,v2.b}[2],[x3],2\r
+       ld2     {v1.b,v2.b}[2],[x3],x4\r
+       ld2     {v1.d,v2.d}[1],[x3]\r
+       ld2     {v1.d,v2.d}[1],[x3],16\r
+       ld2     {v1.d,v2.d}[1],[x3],x4\r
+       ld2     {v1.h,v2.h}[2],[x3]\r
+       ld2     {v1.h,v2.h}[2],[x3],4\r
+       ld2     {v1.h,v2.h}[2],[x3],x4\r
+       ld2     {v1.s,v2.s}[2],[x3]\r
+       ld2     {v1.s,v2.s}[2],[x3],8\r
+       ld2     {v1.s,v2.s}[2],[x3],x4\r
+\r
+       ld2r    {v1.16b,v2.16b},[x2]\r
+       ld2r    {v1.16b,v2.16b},[x2],2\r
+       ld2r    {v1.16b,v2.16b},[x2],x3\r
+       ld2r    {v1.1d,v2.1d},[x2]\r
+       ld2r    {v1.1d,v2.1d},[x2],16\r
+       ld2r    {v1.1d,v2.1d},[x2],x3\r
+       ld2r    {v1.2d,v2.2d},[x2]\r
+       ld2r    {v1.2d,v2.2d},[x2],16\r
+       ld2r    {v1.2d,v2.2d},[x2],x3\r
+       ld2r    {v1.2s,v2.2s},[x2]\r
+       ld2r    {v1.2s,v2.2s},[x2],8\r
+       ld2r    {v1.2s,v2.2s},[x2],x3\r
+       ld2r    {v1.4h,v2.4h},[x2]\r
+       ld2r    {v1.4h,v2.4h},[x2],4\r
+       ld2r    {v1.4h,v2.4h},[x2],x3\r
+       ld2r    {v1.4s,v2.4s},[x2]\r
+       ld2r    {v1.4s,v2.4s},[x2],8\r
+       ld2r    {v1.4s,v2.4s},[x2],x3\r
+       ld2r    {v1.8b,v2.8b},[x2]\r
+       ld2r    {v1.8b,v2.8b},[x2],2\r
+       ld2r    {v1.8b,v2.8b},[x2],x3\r
+       ld2r    {v1.8h,v2.8h},[x2]\r
+       ld2r    {v1.8h,v2.8h},[x2],4\r
+       ld2r    {v1.8h,v2.8h},[x2],x3\r
+\r
+       ld3     {v1.16b,v2.16b,v3.16b},[x3]\r
+       ld3     {v1.16b,v2.16b,v3.16b},[x3],48\r
+       ld3     {v1.16b,v2.16b,v3.16b},[x3],x4\r
+       ld3     {v1.2d,v2.2d,v3.2d},[x3]\r
+       ld3     {v1.2d,v2.2d,v3.2d},[x3],48\r
+       ld3     {v1.2d,v2.2d,v3.2d},[x3],x4\r
+       ld3     {v1.2s,v2.2s,v3.2s},[x3]\r
+       ld3     {v1.2s,v2.2s,v3.2s},[x3],24\r
+       ld3     {v1.2s,v2.2s,v3.2s},[x3],x4\r
+       ld3     {v1.4h,v2.4h,v3.4h},[x3]\r
+       ld3     {v1.4h,v2.4h,v3.4h},[x3],24\r
+       ld3     {v1.4h,v2.4h,v3.4h},[x3],x4\r
+       ld3     {v1.4s,v2.4s,v3.4s},[x3]\r
+       ld3     {v1.4s,v2.4s,v3.4s},[x3],48\r
+       ld3     {v1.4s,v2.4s,v3.4s},[x3],x4\r
+       ld3     {v1.8b,v2.8b,v3.8b},[x3]\r
+       ld3     {v1.8b,v2.8b,v3.8b},[x3],24\r
+       ld3     {v1.8b,v2.8b,v3.8b},[x3],x4\r
+       ld3     {v1.8h,v2.8h,v3.8h},[x3]\r
+       ld3     {v1.8h,v2.8h,v3.8h},[x3],48\r
+       ld3     {v1.8h,v2.8h,v3.8h},[x3],x4\r
+       ld3     {v1.b,v2.b,v3.b}[15],[x3]\r
+       ld3     {v1.b,v2.b,v3.b}[2],[x3],3\r
+       ld3     {v1.b,v2.b,v3.b}[2],[x3],x4\r
+       ld3     {v1.d,v2.d,v3.d}[1],[x3]\r
+       ld3     {v1.d,v2.d,v3.d}[1],[x3],24\r
+       ld3     {v1.d,v2.d,v3.d}[1],[x3],x4\r
+       ld3     {v1.h,v2.h,v3.h}[2],[x3]\r
+       ld3     {v1.h,v2.h,v3.h}[2],[x3],6\r
+       ld3     {v1.h,v2.h,v3.h}[2],[x3],x4\r
+       ld3     {v1.s,v2.s,v3.s}[2],[x3]\r
+       ld3     {v1.s,v2.s,v3.s}[2],[x3],12\r
+       ld3     {v1.s,v2.s,v3.s}[2],[x3],x4\r
+\r
+       ld3r    {v1.16b,v2.16b,v3.16b},[x2]\r
+       ld3r    {v1.16b,v2.16b,v3.16b},[x2],3\r
+       ld3r    {v1.16b,v2.16b,v3.16b},[x2],x3\r
+       ld3r    {v1.1d,v2.1d,v3.1d},[x2]\r
+       ld3r    {v1.1d,v2.1d,v3.1d},[x2],24\r
+       ld3r    {v1.1d,v2.1d,v3.1d},[x2],x3\r
+       ld3r    {v1.2d,v2.2d,v3.2d},[x2]\r
+       ld3r    {v1.2d,v2.2d,v3.2d},[x2],24\r
+       ld3r    {v1.2d,v2.2d,v3.2d},[x2],x3\r
+       ld3r    {v1.2s,v2.2s,v3.2s},[x2]\r
+       ld3r    {v1.2s,v2.2s,v3.2s},[x2],12\r
+       ld3r    {v1.2s,v2.2s,v3.2s},[x2],x3\r
+       ld3r    {v1.4h,v2.4h,v3.4h},[x2]\r
+       ld3r    {v1.4h,v2.4h,v3.4h},[x2],6\r
+       ld3r    {v1.4h,v2.4h,v3.4h},[x2],x3\r
+       ld3r    {v1.4s,v2.4s,v3.4s},[x2]\r
+       ld3r    {v1.4s,v2.4s,v3.4s},[x2],12\r
+       ld3r    {v1.4s,v2.4s,v3.4s},[x2],x3\r
+       ld3r    {v1.8b,v2.8b,v3.8b},[x2]\r
+       ld3r    {v1.8b,v2.8b,v3.8b},[x2],3\r
+       ld3r    {v1.8b,v2.8b,v3.8b},[x2],x3\r
+       ld3r    {v1.8h,v2.8h,v3.8h},[x2]\r
+       ld3r    {v1.8h,v2.8h,v3.8h},[x2],6\r
+       ld3r    {v1.8h,v2.8h,v3.8h},[x2],x3\r
+\r
+       ld4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3]\r
+       ld4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3],64\r
+       ld4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3],x4\r
+       ld4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3]\r
+       ld4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3],64\r
+       ld4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3],x4\r
+       ld4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3]\r
+       ld4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3],32\r
+       ld4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3],x4\r
+       ld4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3]\r
+       ld4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3],32\r
+       ld4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3],x4\r
+       ld4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3]\r
+       ld4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3],64\r
+       ld4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3],x4\r
+       ld4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3]\r
+       ld4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3],32\r
+       ld4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3],x4\r
+       ld4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3]\r
+       ld4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3],64\r
+       ld4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3],x4\r
+       ld4     {v1.b,v2.b,v3.b,v4.b}[15],[x3]\r
+       ld4     {v1.b,v2.b,v3.b,v4.b}[2],[x3],4\r
+       ld4     {v1.b,v2.b,v3.b,v4.b}[2],[x3],x4\r
+       ld4     {v1.d,v2.d,v3.d,v4.d}[1],[x3]\r
+       ld4     {v1.d,v2.d,v3.d,v4.d}[1],[x3],32\r
+       ld4     {v1.d,v2.d,v3.d,v4.d}[1],[x3],x4\r
+       ld4     {v1.h,v2.h,v3.h,v4.h}[2],[x3]\r
+       ld4     {v1.h,v2.h,v3.h,v4.h}[2],[x3],8\r
+       ld4     {v1.h,v2.h,v3.h,v4.h}[2],[x3],x4\r
+       ld4     {v1.s,v2.s,v3.s,v4.s}[2],[x3]\r
+       ld4     {v1.s,v2.s,v3.s,v4.s}[2],[x3],16\r
+       ld4     {v1.s,v2.s,v3.s,v4.s}[2],[x3],x4\r
+\r
+       ld4r    {v1.16b,v2.16b,v3.16b,v4.16b},[x2]\r
+       ld4r    {v1.16b,v2.16b,v3.16b,v4.16b},[x2],4\r
+       ld4r    {v1.16b,v2.16b,v3.16b,v4.16b},[x2],x3\r
+       ld4r    {v1.1d,v2.1d,v3.1d,v4.1d},[x2]\r
+       ld4r    {v1.1d,v2.1d,v3.1d,v4.1d},[x2],32\r
+       ld4r    {v1.1d,v2.1d,v3.1d,v4.1d},[x2],x3\r
+       ld4r    {v1.2d,v2.2d,v3.2d,v4.2d},[x2]\r
+       ld4r    {v1.2d,v2.2d,v3.2d,v4.2d},[x2],32\r
+       ld4r    {v1.2d,v2.2d,v3.2d,v4.2d},[x2],x3\r
+       ld4r    {v1.2s,v2.2s,v3.2s,v4.2s},[x2]\r
+       ld4r    {v1.2s,v2.2s,v3.2s,v4.2s},[x2],16\r
+       ld4r    {v1.2s,v2.2s,v3.2s,v4.2s},[x2],x3\r
+       ld4r    {v1.4h,v2.4h,v3.4h,v4.4h},[x2]\r
+       ld4r    {v1.4h,v2.4h,v3.4h,v4.4h},[x2],8\r
+       ld4r    {v1.4h,v2.4h,v3.4h,v4.4h},[x2],x3\r
+       ld4r    {v1.4s,v2.4s,v3.4s,v4.4s},[x2]\r
+       ld4r    {v1.4s,v2.4s,v3.4s,v4.4s},[x2],16\r
+       ld4r    {v1.4s,v2.4s,v3.4s,v4.4s},[x2],x3\r
+       ld4r    {v1.8b,v2.8b,v3.8b,v4.8b},[x2]\r
+       ld4r    {v1.8b,v2.8b,v3.8b,v4.8b},[x2],4\r
+       ld4r    {v1.8b,v2.8b,v3.8b,v4.8b},[x2],x3\r
+       ld4r    {v1.8h,v2.8h,v3.8h,v4.8h},[x2]\r
+       ld4r    {v1.8h,v2.8h,v3.8h,v4.8h},[x2],8\r
+       ld4r    {v1.8h,v2.8h,v3.8h,v4.8h},[x2],x3\r
+\r
+       ldnp    d0,d1,[x2]\r
+       ldnp    d0,d1,[x2,+0x8]\r
+       ldnp    d0,d1,[expression.qword]\r
+       ldnp    q0,q1,[x2]\r
+       ldnp    q0,q1,[x2,+0x20]\r
+       ldnp    q0,q1,[expression.dqword]\r
+       ldnp    s0,s1,[x2]\r
+       ldnp    s0,s1,[x2,+0x8]\r
+       ldnp    s0,s1,[expression.dword]\r
+\r
+       ldp     d0,d1,[x2]\r
+       ldp     d0,d1,[x2,+0x8]\r
+       ldp     d0,d1,[expression.qword]\r
+       ldp     d0,d1,[x2,+0x8]!\r
+       ldp     d0,d1,[expression.qword]!\r
+       ldp     d0,d1,[x2],+0x8\r
+       ldp     q0,q1,[x2]\r
+       ldp     q0,q1,[x2,+0x10]\r
+       ldp     q0,q1,[expression.dqword]\r
+       ldp     q0,q1,[x2,+0x10]!\r
+       ldp     q0,q1,[expression.dqword]!\r
+       ldp     q0,q1,[x2],+0x10\r
+       ldp     s0,s1,[x2]\r
+       ldp     s0,s1,[x2,+0x8]\r
+       ldp     s0,s1,[expression.dword]\r
+       ldp     s0,s1,[x2,+0x8]!\r
+       ldp     s0,s1,[expression.dword]!\r
+       ldp     s0,s1,[x2],+0x8\r
+\r
+       ldr     b0,[x2]\r
+       ldr     b0,[x2,+0x8]\r
+       ldr     b0,[expression.byte]\r
+       ldr     b0,[x2,+0x8]!\r
+       ldr     b0,[expression.byte]!\r
+       ldr     b0,[x2],+0x8\r
+       ldr     b0,[x2,w3,sxtw]\r
+       ldr     b0,[x2,w3,sxtw 0]\r
+       ldr     b0,[x2,w3,uxtw]\r
+       ldr     b0,[x2,w3,uxtw 0]\r
+       ldr     b0,[x2,x3]\r
+       ldr     b0,[x2,x3,lsl 0]\r
+       ldr     b0,[x2,x3,sxtx]\r
+       ldr     b0,[x2,x3,sxtx 0]\r
+       ldr     h0,[x2]\r
+       ldr     h0,[x2,+0x8]\r
+       ldr     h0,[expression.hword]\r
+       ldr     h0,[x2,+0x8]!\r
+       ldr     h0,[expression.hword]!\r
+       ldr     h0,[x2],+0x8\r
+       ldr     h0,[x2,w3,sxtw]\r
+       ldr     h0,[x2,w3,sxtw 1]\r
+       ldr     h0,[x2,w3,uxtw]\r
+       ldr     h0,[x2,w3,uxtw 1]\r
+       ldr     h0,[x2,x3]\r
+       ldr     h0,[x2,x3,lsl 1]\r
+       ldr     h0,[x2,x3,sxtx]\r
+       ldr     h0,[x2,x3,sxtx 1]\r
+       ldr     s0,[x2,+0x8]\r
+       ldr     s0,[expression.word]\r
+       ldr     s0,[x2,+0x8]!\r
+       ldr     s0,[expression.word]!\r
+       ldr     s0,[x2],+0x8\r
+       ldr     s0,[x2,w3,sxtw]\r
+       ldr     s0,[x2,w3,sxtw 2]\r
+       ldr     s0,[x2,w3,uxtw]\r
+       ldr     s0,[x2,w3,uxtw 2]\r
+       ldr     s0,[x2,x3]\r
+       ldr     s0,[x2,x3,lsl 2]\r
+       ldr     s0,[x2,x3,sxtx]\r
+       ldr     s0,[x2,x3,sxtx 2]\r
+       ldr     s0,label_ldr\r
+       ldr     s0,[label_ldr]\r
+       ldr     d0,[x2,+0x8]\r
+       ldr     d0,[expression.dword]\r
+       ldr     d0,[x2,+0x8]!\r
+       ldr     d0,[expression.dword]!\r
+       ldr     d0,[x2],+0x8\r
+       ldr     d0,[x2,w3,sxtw]\r
+       ldr     d0,[x2,w3,sxtw 3]\r
+       ldr     d0,[x2,w3,uxtw]\r
+       ldr     d0,[x2,w3,uxtw 3]\r
+       ldr     d0,[x2,x3]\r
+       ldr     d0,[x2,x3,lsl 3]\r
+       ldr     d0,[x2,x3,sxtx]\r
+       ldr     d0,[x2,x3,sxtx 3]\r
+       ldr     d0,label_ldr\r
+       ldr     d0,[label_ldr]\r
+       ldr     q0,[x2,+0x8]\r
+       ldr     q0,[expression.qword]\r
+       ldr     q0,[x2,+0x8]!\r
+       ldr     q0,[expression.qword]!\r
+       ldr     q0,[x2],+0x8\r
+       ldr     q0,[x2,w3,sxtw]\r
+       ldr     q0,[x2,w3,sxtw 4]\r
+       ldr     q0,[x2,w3,uxtw]\r
+       ldr     q0,[x2,w3,uxtw 4]\r
+       ldr     q0,[x2,x3]\r
+       ldr     q0,[x2,x3,lsl 4]\r
+       ldr     q0,[x2,x3,sxtx]\r
+       ldr     q0,[x2,x3,sxtx 4]\r
+       ldr     q0,label_ldr\r
+       ldr     q0,[label_ldr]\r
+\r
+       ldur    b0,[x2]\r
+       ldur    b0,[x2,+0x8]\r
+       ldur    b0,[expression.byte]\r
+       ldur    h0,[x2]\r
+       ldur    h0,[x2,+0x8]\r
+       ldur    h0,[expression.hword]\r
+       ldur    s0,[x2]\r
+       ldur    s0,[x2,+0x8]\r
+       ldur    s0,[expression.word]\r
+       ldur    d0,[x2]\r
+       ldur    d0,[x2,+0x8]\r
+       ldur    d0,[expression.dword]\r
+       ldur    q0,[x2]\r
+       ldur    q0,[x2,+0x8]\r
+       ldur    q0,[expression.qword]\r
+\r
+       mla     v1.16b,v2.16b,v3.16b\r
+       mla     v1.2s,v2.2s,v3.2s\r
+       mla     v1.2s,v2.2s,v3.s[0]\r
+       mla     v1.4h,v2.4h,v3.4h\r
+       mla     v1.4h,v2.4h,v3.h[0]\r
+       mla     v1.4s,v2.4s,v3.4s\r
+       mla     v1.4s,v2.4s,v3.s[3]\r
+       mla     v1.8b,v2.8b,v3.8b\r
+       mla     v1.8h,v2.8h,v3.8h\r
+       mla     v1.8h,v2.8h,v3.h[7]\r
+\r
+       mls     v1.16b,v2.16b,v3.16b\r
+       mls     v1.2s,v2.2s,v3.2s\r
+       mls     v1.2s,v2.2s,v3.s[0]\r
+       mls     v1.4h,v2.4h,v3.4h\r
+       mls     v1.4h,v2.4h,v3.h[0]\r
+       mls     v1.4s,v2.4s,v3.4s\r
+       mls     v1.4s,v2.4s,v3.s[3]\r
+       mls     v1.8b,v2.8b,v3.8b\r
+       mls     v1.8h,v2.8h,v3.8h\r
+       mls     v1.8h,v2.8h,v3.h[7]\r
+\r
+       mov     b1,v2.b[0]\r
+       mov     h1,v2.h[7]\r
+       mov     s1,v2.s[3]\r
+       mov     d1,v2.d[1]\r
+\r
+       mov     v1.16b,v2.16b\r
+       mov     v1.8b,v2.8b\r
+       mov     v1.b[1],v2.b[15]\r
+       mov     v1.d[0],v2.d[1]\r
+       mov     v1.h[1],v2.h[7]\r
+       mov     v1.s[1],v2.s[3]\r
+       mov     v2.b[15],w1\r
+       mov     v2.d[1],x1\r
+       mov     v2.h[7],w1\r
+       mov     v2.s[3],w1\r
+       mov     w1,v2.s[0]\r
+       mov     x1,v2.d[0]\r
+\r
+       movi    d1,0xFFFFFFFF00FF00FF\r
+       movi    v1.16b,0xAA\r
+       movi    v1.2d,0x00FF00FF00FF00FF\r
+       movi    v1.2s,0xAA,lsl 0\r
+       movi    v1.2s,0xAA,lsl 8\r
+       movi    v1.2s,0xAA,lsl 16\r
+       movi    v1.2s,0xAA,lsl 24\r
+       movi    v1.2s,0xAA,msl 8\r
+       movi    v1.2s,0xAA,msl 16\r
+       movi    v1.4h,0xAA,lsl 0\r
+       movi    v1.4h,0xAA,lsl 8\r
+       movi    v1.4s,0xAA,lsl 0\r
+       movi    v1.4s,0xAA,lsl 8\r
+       movi    v1.4s,0xAA,lsl 16\r
+       movi    v1.4s,0xAA,lsl 24\r
+       movi    v1.4s,0xAA,msl 8\r
+       movi    v1.4s,0xAA,msl 16\r
+       movi    v1.8b,0xAA\r
+       movi    v1.8h,0xAA,lsl 0\r
+       movi    v1.8h,0xAA,lsl 8\r
+\r
+       mul     v1.16b,v2.16b,v3.16b\r
+       mul     v1.2s,v2.2s,v3.2s\r
+       mul     v1.2s,v2.2s,v3.s[0]\r
+       mul     v1.4h,v2.4h,v3.4h\r
+       mul     v1.4h,v2.4h,v3.h[0]\r
+       mul     v1.4s,v2.4s,v3.4s\r
+       mul     v1.4s,v2.4s,v3.s[3]\r
+       mul     v1.8b,v2.8b,v3.8b\r
+       mul     v1.8h,v2.8h,v3.8h\r
+       mul     v1.8h,v2.8h,v3.h[7]\r
+\r
+       mvn     v1.16b,v2.16b\r
+       mvn     v1.8b,v2.8b\r
+\r
+       mvni    v1.2s,0xAA\r
+       mvni    v1.2s,0xAA,lsl 0\r
+       mvni    v1.2s,0xAA,lsl 8\r
+       mvni    v1.2s,0xAA,lsl 16\r
+       mvni    v1.2s,0xAA,lsl 24\r
+       mvni    v1.2s,0xAA,msl 8\r
+       mvni    v1.2s,0xAA,msl 16\r
+       mvni    v1.4h,0xAA\r
+       mvni    v1.4h,0xAA,lsl 0\r
+       mvni    v1.4h,0xAA,lsl 8\r
+       mvni    v1.4s,0xAA\r
+       mvni    v1.4s,0xAA,lsl 0\r
+       mvni    v1.4s,0xAA,lsl 8\r
+       mvni    v1.4s,0xAA,lsl 16\r
+       mvni    v1.4s,0xAA,lsl 24\r
+       mvni    v1.4s,0xAA,msl 8\r
+       mvni    v1.4s,0xAA,msl 16\r
+       mvni    v1.8h,0xAA\r
+       mvni    v1.8h,0xAA,lsl 0\r
+       mvni    v1.8h,0xAA,lsl 8\r
+\r
+       neg     d1,d2\r
+       neg     v1.16b,v2.16b\r
+       neg     v1.2d,v2.2d\r
+       neg     v1.2s,v2.2s\r
+       neg     v1.4h,v2.4h\r
+       neg     v1.4s,v2.4s\r
+       neg     v1.8b,v2.8b\r
+       neg     v1.8h,v2.8h\r
+\r
+       not     v1.8b,v2.8b\r
+       not     v1.16b,v2.16b\r
+\r
+       orn     v1.16b,v2.16b,v3.16b\r
+       orn     v1.8b,v2.8b,v3.8b\r
+\r
+       orr     v1.16b,v2.16b,v3.16b\r
+       orr     v1.8b,v2.8b,v3.8b\r
+       orr     v1.4h,0xFE\r
+       orr     v1.4h,0xFE,lsl 0\r
+       orr     v3.8h,0xFB\r
+       orr     v3.8h,0xFB,lsl 0\r
+       orr     v4.8h,0xF7,lsl 8\r
+       orr     v5.2s,0xEF\r
+       orr     v5.2s,0xEF,lsl 0\r
+       orr     v6.2s,0xDF,lsl 16\r
+       orr     v7.4s,0xBF\r
+       orr     v7.4s,0xBF,lsl 0\r
+       orr     v8.4s,0x80,lsl 24\r
+\r
+       pmul    v1.16b,v2.16b,v3.16b\r
+       pmul    v1.8b,v2.8b,v3.8b\r
+\r
+       pmull   v1.8h,v2.8b,v3.8b\r
+\r
+       pmull2  v1.8h,v2.16b,v3.16b\r
+\r
+       raddhn  v1.2s,v2.2d,v3.2d\r
+       raddhn  v1.4h,v2.4s,v3.4s\r
+       raddhn  v1.8b,v2.8h,v3.8h\r
+\r
+       raddhn2 v1.16b,v2.8h,v3.8h\r
+       raddhn2 v1.4s,v2.2d,v3.2d\r
+       raddhn2 v1.8h,v2.4s,v3.4s\r
+\r
+       rbit    v1.16b,v2.16b\r
+       rbit    v1.8b,v2.8b\r
+\r
+       rev16   v1.16b,v2.16b\r
+       rev16   v1.8b,v2.8b\r
+\r
+       rev32   v1.16b,v2.16b\r
+       rev32   v1.4h,v2.4h\r
+       rev32   v1.8b,v2.8b\r
+       rev32   v1.8h,v2.8h\r
+\r
+       rev64   v1.16b,v2.16b\r
+       rev64   v1.2s,v2.2s\r
+       rev64   v1.4h,v2.4h\r
+       rev64   v1.4s,v2.4s\r
+       rev64   v1.8b,v2.8b\r
+       rev64   v1.8h,v2.8h\r
+\r
+       rshrn   v1.2s,v2.2d,32\r
+       rshrn   v1.4h,v2.4s,16\r
+       rshrn   v1.8b,v2.8h,8\r
+\r
+       rshrn2  v1.16b,v2.8h,8\r
+       rshrn2  v1.4s,v2.2d,32\r
+       rshrn2  v1.8h,v2.4s,16\r
+\r
+       rsubhn  v1.2s,v2.2d,v3.2d\r
+       rsubhn  v1.4h,v2.4s,v3.4s\r
+       rsubhn  v1.8b,v2.8h,v3.8h\r
+\r
+       rsubhn2 v1.16b,v2.8h,v3.8h\r
+       rsubhn2 v1.4s,v2.2d,v3.2d\r
+       rsubhn2 v1.8h,v2.4s,v3.4s\r
+\r
+       saba    v1.16b,v2.16b,v3.16b\r
+       saba    v1.2s,v2.2s,v3.2s\r
+       saba    v1.4h,v2.4h,v3.4h\r
+       saba    v1.4s,v2.4s,v3.4s\r
+       saba    v1.8b,v2.8b,v3.8b\r
+       saba    v1.8h,v2.8h,v3.8h\r
+\r
+       sabal   v1.2d,v2.2s,v3.2s\r
+       sabal   v1.4s,v2.4h,v3.4h\r
+       sabal   v1.8h,v2.8b,v3.8b\r
+\r
+       sabal2  v1.2d,v2.4s,v3.4s\r
+       sabal2  v1.4s,v2.8h,v3.8h\r
+       sabal2  v1.8h,v2.16b,v3.16b\r
+\r
+       sabd    v1.16b,v2.16b,v3.16b\r
+       sabd    v1.2s,v2.2s,v3.2s\r
+       sabd    v1.4h,v2.4h,v3.4h\r
+       sabd    v1.4s,v2.4s,v3.4s\r
+       sabd    v1.8b,v2.8b,v3.8b\r
+       sabd    v1.8h,v2.8h,v3.8h\r
+\r
+       sabdl   v1.2d,v2.2s,v3.2s\r
+       sabdl   v1.4s,v2.4h,v3.4h\r
+       sabdl   v1.8h,v2.8b,v3.8b\r
+\r
+       sabdl2  v1.2d,v2.4s,v3.4s\r
+       sabdl2  v1.4s,v2.8h,v3.8h\r
+       sabdl2  v1.8h,v2.16b,v3.16b\r
+\r
+       sadalp  v1.1d,v2.2s\r
+       sadalp  v1.2d,v2.4s\r
+       sadalp  v1.2s,v2.4h\r
+       sadalp  v1.4h,v2.8b\r
+       sadalp  v1.4s,v2.8h\r
+       sadalp  v1.8h,v2.16b\r
+\r
+       saddl   v1.2d,v2.2s,v3.2s\r
+       saddl   v1.4s,v2.4h,v3.4h\r
+       saddl   v1.8h,v2.8b,v3.8b\r
+\r
+       saddl2  v1.2d,v2.4s,v3.4s\r
+       saddl2  v1.4s,v2.8h,v3.8h\r
+       saddl2  v1.8h,v2.16b,v3.16b\r
+\r
+       saddlp  v1.1d,v2.2s\r
+       saddlp  v1.2d,v2.4s\r
+       saddlp  v1.2s,v2.4h\r
+       saddlp  v1.4h,v2.8b\r
+       saddlp  v1.4s,v2.8h\r
+       saddlp  v1.8h,v2.16b\r
+\r
+       saddlv  d1,v2.4s\r
+       saddlv  h1,v2.16b\r
+       saddlv  h1,v2.8b\r
+       saddlv  s1,v2.4h\r
+       saddlv  s1,v2.8h\r
+\r
+       saddw   v1.2d,v2.2d,v3.2s\r
+       saddw   v1.4s,v2.4s,v3.4h\r
+       saddw   v1.8h,v2.8h,v3.8b\r
+\r
+       saddw2  v1.2d,v2.2d,v3.4s\r
+       saddw2  v1.4s,v2.4s,v3.8h\r
+       saddw2  v1.8h,v2.8h,v3.16b\r
+\r
+       shadd   v1.16b,v2.16b,v3.16b\r
+       shadd   v1.2s,v2.2s,v3.2s\r
+       shadd   v1.4h,v2.4h,v3.4h\r
+       shadd   v1.4s,v2.4s,v3.4s\r
+       shadd   v1.8b,v2.8b,v3.8b\r
+       shadd   v1.8h,v2.8h,v3.8h\r
+\r
+       shl     d1,d2,1\r
+       shl     v1.16b,v2.16b,7\r
+       shl     v1.2d,v2.2d,63\r
+       shl     v1.2s,v2.2s,1\r
+       shl     v1.4h,v2.4h,1\r
+       shl     v1.4s,v2.4s,31\r
+       shl     v1.8b,v2.8b,1\r
+       shl     v1.8h,v2.8h,15\r
+\r
+       shll    v1.2d,v2.2s,32\r
+       shll    v1.4s,v2.4h,16\r
+       shll    v1.8h,v2.8b,8\r
+\r
+       shll2   v1.2d,v2.4s,32\r
+       shll2   v1.4s,v2.8h,16\r
+       shll2   v1.8h,v2.16b,8\r
+\r
+       shrn    v1.2s,v2.2d,3\r
+       shrn    v1.4h,v2.4s,2\r
+       shrn    v1.8b,v2.8h,1\r
+\r
+       shrn2   v1.16b,v2.8h,1\r
+       shrn2   v1.4s,v2.2d,3\r
+       shrn2   v1.8h,v2.4s,2\r
+\r
+       shsub   v1.16b,v2.16b,v3.16b\r
+       shsub   v1.2s,v2.2s,v3.2s\r
+       shsub   v1.4h,v2.4h,v3.4h\r
+       shsub   v1.4s,v2.4s,v3.4s\r
+       shsub   v1.8b,v2.8b,v3.8b\r
+       shsub   v1.8h,v2.8h,v3.8h\r
+\r
+       sli     d1,d2,1\r
+       sli     v1.16b,v2.16b,7\r
+       sli     v1.2d,v2.2d,63\r
+       sli     v1.2s,v2.2s,1\r
+       sli     v1.4h,v2.4h,1\r
+       sli     v1.4s,v2.4s,31\r
+       sli     v1.8b,v2.8b,1\r
+       sli     v1.8h,v2.8h,15\r
+\r
+       smax    v1.16b,v2.16b,v3.16b\r
+       smax    v1.2s,v2.2s,v3.2s\r
+       smax    v1.4h,v2.4h,v3.4h\r
+       smax    v1.4s,v2.4s,v3.4s\r
+       smax    v1.8b,v2.8b,v3.8b\r
+       smax    v1.8h,v2.8h,v3.8h\r
+\r
+       smaxp   v1.16b,v2.16b,v3.16b\r
+       smaxp   v1.2s,v2.2s,v3.2s\r
+       smaxp   v1.4h,v2.4h,v3.4h\r
+       smaxp   v1.4s,v2.4s,v3.4s\r
+       smaxp   v1.8b,v2.8b,v3.8b\r
+       smaxp   v1.8h,v2.8h,v3.8h\r
+\r
+       smaxv   b1,v2.16b\r
+       smaxv   b1,v2.8b\r
+       smaxv   h1,v2.4h\r
+       smaxv   h1,v2.8h\r
+       smaxv   s1,v2.4s\r
+\r
+       smin    v1.16b,v2.16b,v3.16b\r
+       smin    v1.2s,v2.2s,v3.2s\r
+       smin    v1.4h,v2.4h,v3.4h\r
+       smin    v1.4s,v2.4s,v3.4s\r
+       smin    v1.8b,v2.8b,v3.8b\r
+       smin    v1.8h,v2.8h,v3.8h\r
+\r
+       sminp   v1.16b,v2.16b,v3.16b\r
+       sminp   v1.2s,v2.2s,v3.2s\r
+       sminp   v1.4h,v2.4h,v3.4h\r
+       sminp   v1.4s,v2.4s,v3.4s\r
+       sminp   v1.8b,v2.8b,v3.8b\r
+       sminp   v1.8h,v2.8h,v3.8h\r
+\r
+       sminv   b1,v2.16b\r
+       sminv   b1,v2.8b\r
+       sminv   h1,v2.4h\r
+       sminv   h1,v2.8h\r
+       sminv   s1,v2.4s\r
+\r
+       smlal   v1.2d,v2.2s,v3.2s\r
+       smlal   v1.2d,v2.2s,v31.s[3]\r
+       smlal   v1.4s,v2.4h,v15.h[7]\r
+       smlal   v1.4s,v2.4h,v3.4h\r
+       smlal   v1.8h,v2.8b,v3.8b\r
+\r
+       smlal2  v1.2d,v2.4s,v3.4s\r
+       smlal2  v1.2d,v2.4s,v31.s[3]\r
+       smlal2  v1.4s,v2.8h,v15.h[7]\r
+       smlal2  v1.4s,v2.8h,v3.8h\r
+       smlal2  v1.8h,v2.16b,v3.16b\r
+\r
+       smlsl   v1.2d,v2.2s,v3.2s\r
+       smlsl   v1.2d,v2.2s,v31.s[3]\r
+       smlsl   v1.4s,v2.4h,v15.h[7]\r
+       smlsl   v1.4s,v2.4h,v3.4h\r
+       smlsl   v1.8h,v2.8b,v3.8b\r
+\r
+       smlsl2  v1.2d,v2.4s,v3.4s\r
+       smlsl2  v1.2d,v2.4s,v31.s[3]\r
+       smlsl2  v1.4s,v2.8h,v15.h[7]\r
+       smlsl2  v1.4s,v2.8h,v3.8h\r
+       smlsl2  v1.8h,v2.16b,v3.16b\r
+\r
+       smov    w1,v2.b[15]\r
+       smov    w1,v2.h[7]\r
+       smov    x1,v2.b[4]\r
+       smov    x1,v2.h[2]\r
+       smov    x1,v2.s[1]\r
+\r
+       smull   v1.2d,v2.2s,v3.2s\r
+       smull   v1.2d,v2.2s,v3.s[0]\r
+       smull   v1.2d,v2.2s,v31.s[3]\r
+       smull   v1.4s,v2.4h,v15.h[7]\r
+       smull   v1.4s,v2.4h,v3.4h\r
+       smull   v1.4s,v2.4h,v3.h[0]\r
+       smull   v1.8h,v2.8b,v3.8b\r
+\r
+       smull2  v1.2d,v2.4s,v3.4s\r
+       smull2  v1.2d,v2.4s,v31.s[3]\r
+       smull2  v1.4s,v2.8h,v15.h[7]\r
+       smull2  v1.4s,v2.8h,v3.8h\r
+       smull2  v1.8h,v2.16b,v3.16b\r
+\r
+       sqabs   b1,b2\r
+       sqabs   d1,d2\r
+       sqabs   h1,h2\r
+       sqabs   s1,s2\r
+       sqabs   v1.16b,v2.16b\r
+       sqabs   v1.2d,v2.2d\r
+       sqabs   v1.2s,v2.2s\r
+       sqabs   v1.4h,v2.4h\r
+       sqabs   v1.4s,v2.4s\r
+       sqabs   v1.8b,v2.8b\r
+       sqabs   v1.8h,v2.8h\r
+\r
+       sqadd   b1,b2,b3\r
+       sqadd   d1,d2,d3\r
+       sqadd   h1,h2,h3\r
+       sqadd   s1,s2,s3\r
+       sqadd   v1.16b,v2.16b,v3.16b\r
+       sqadd   v1.2d,v2.2d,v3.2d\r
+       sqadd   v1.2s,v2.2s,v3.2s\r
+       sqadd   v1.4h,v2.4h,v3.4h\r
+       sqadd   v1.4s,v2.4s,v3.4s\r
+       sqadd   v1.8b,v2.8b,v3.8b\r
+       sqadd   v1.8h,v2.8h,v3.8h\r
+\r
+       sqdmlal v1.2d,v2.2s,v3.2s\r
+       sqdmlal v1.2d,v2.2s,v31.s[3]\r
+       sqdmlal v1.4s,v2.4h,v15.h[7]\r
+       sqdmlal v1.4s,v2.4h,v3.4h\r
+\r
+       sqdmlal2        v1.2d,v2.4s,v3.4s\r
+       sqdmlal2        v1.2d,v2.4s,v31.s[3]\r
+       sqdmlal2        v1.4s,v2.8h,v15.h[7]\r
+       sqdmlal2        v1.4s,v2.8h,v3.8h\r
+\r
+       sqdmlsl v1.2d,v2.2s,v3.2s\r
+       sqdmlsl v1.2d,v2.2s,v31.s[3]\r
+       sqdmlsl v1.4s,v2.4h,v15.h[7]\r
+       sqdmlsl v1.4s,v2.4h,v3.4h\r
+\r
+       sqdmlsl2        v1.2d,v2.4s,v3.4s\r
+       sqdmlsl2        v1.2d,v2.4s,v31.s[3]\r
+       sqdmlsl2        v1.4s,v2.8h,v15.h[7]\r
+       sqdmlsl2        v1.4s,v2.8h,v3.8h\r
+\r
+       sqdmulh h1,h2,h3\r
+       sqdmulh h1,h2,v3.h[7]\r
+       sqdmulh s1,s2,s3\r
+       sqdmulh s1,s2,v3.s[3]\r
+       sqdmulh v1.2s,v2.2s,v3.2s\r
+       sqdmulh v1.2s,v2.2s,v3.s[0]\r
+       sqdmulh v1.4h,v2.4h,v3.4h\r
+       sqdmulh v1.4h,v2.4h,v3.h[0]\r
+       sqdmulh v1.4s,v2.4s,v3.4s\r
+       sqdmulh v1.4s,v2.4s,v3.s[3]\r
+       sqdmulh v1.8h,v2.8h,v3.8h\r
+       sqdmulh v1.8h,v2.8h,v3.h[7]\r
+\r
+       sqdmull v1.2d,v2.2s,v3.2s\r
+       sqdmull v1.2d,v2.2s,v31.s[3]\r
+       sqdmull v1.4s,v2.4h,v15.h[7]\r
+       sqdmull v1.4s,v2.4h,v3.4h\r
+\r
+       sqdmull2        v1.2d,v2.4s,v3.4s\r
+       sqdmull2        v1.2d,v2.4s,v31.s[3]\r
+       sqdmull2        v1.4s,v2.8h,v15.h[7]\r
+       sqdmull2        v1.4s,v2.8h,v3.8h\r
+\r
+       sqneg   b1,b2\r
+       sqneg   d1,d2\r
+       sqneg   h1,h2\r
+       sqneg   s1,s2\r
+       sqneg   v1.16b,v2.16b\r
+       sqneg   v1.2d,v2.2d\r
+       sqneg   v1.2s,v2.2s\r
+       sqneg   v1.4h,v2.4h\r
+       sqneg   v1.4s,v2.4s\r
+       sqneg   v1.8b,v2.8b\r
+       sqneg   v1.8h,v2.8h\r
+\r
+       sqrdmulh        h1,h2,h3\r
+       sqrdmulh        h1,h2,v3.h[7]\r
+       sqrdmulh        s1,s2,s3\r
+       sqrdmulh        s1,s2,v3.s[3]\r
+       sqrdmulh        v1.2s,v2.2s,v3.2s\r
+       sqrdmulh        v1.2s,v2.2s,v3.s[0]\r
+       sqrdmulh        v1.4h,v2.4h,v3.4h\r
+       sqrdmulh        v1.4h,v2.4h,v3.h[0]\r
+       sqrdmulh        v1.4s,v2.4s,v3.4s\r
+       sqrdmulh        v1.4s,v2.4s,v3.s[3]\r
+       sqrdmulh        v1.8h,v2.8h,v3.8h\r
+       sqrdmulh        v1.8h,v2.8h,v3.h[7]\r
+\r
+       sqrshl  b1,b2,b3\r
+       sqrshl  d1,d2,d3\r
+       sqrshl  h1,h2,h3\r
+       sqrshl  s1,s2,s3\r
+       sqrshl  v1.16b,v2.16b,v3.16b\r
+       sqrshl  v1.2d,v2.2d,v3.2d\r
+       sqrshl  v1.2s,v2.2s,v3.2s\r
+       sqrshl  v1.4h,v2.4h,v3.4h\r
+       sqrshl  v1.4s,v2.4s,v3.4s\r
+       sqrshl  v1.8b,v2.8b,v3.8b\r
+       sqrshl  v1.8h,v2.8h,v3.8h\r
+\r
+       sqrshrn b8,h8,1\r
+       sqrshrn h4,s4,2\r
+       sqrshrn s2,d2,3\r
+       sqrshrn v1.2s,v2.2d,3\r
+       sqrshrn v1.4h,v2.4s,2\r
+       sqrshrn v1.8b,v2.8h,1\r
+\r
+       sqrshrn2        v1.16b,v2.8h,1\r
+       sqrshrn2        v1.4s,v2.2d,3\r
+       sqrshrn2        v1.8h,v2.4s,2\r
+\r
+       sqrshrun        b8,h8,1\r
+       sqrshrun        h4,s4,2\r
+       sqrshrun        s2,d2,3\r
+       sqrshrun        v1.8b,v2.8h,1\r
+       sqrshrun        v1.4h,v2.4s,2\r
+       sqrshrun        v1.2s,v2.2d,3\r
+\r
+       sqrshrun2       v1.16b,v2.8h,1\r
+       sqrshrun2       v1.8h,v2.4s,2\r
+       sqrshrun2       v1.4s,v2.2d,3\r
+\r
+       sqshl   b1,b2,1\r
+       sqshl   b1,b2,b3\r
+       sqshl   d1,d2,1\r
+       sqshl   d1,d2,d3\r
+       sqshl   h1,h2,1\r
+       sqshl   h1,h2,h3\r
+       sqshl   s1,s2,1\r
+       sqshl   s1,s2,s3\r
+       sqshl   v1.16b,v2.16b,7\r
+       sqshl   v1.16b,v2.16b,v3.16b\r
+       sqshl   v1.2d,v2.2d,63\r
+       sqshl   v1.2d,v2.2d,v3.2d\r
+       sqshl   v1.2s,v2.2s,1\r
+       sqshl   v1.2s,v2.2s,v3.2s\r
+       sqshl   v1.4h,v2.4h,1\r
+       sqshl   v1.4h,v2.4h,v3.4h\r
+       sqshl   v1.4s,v2.4s,31\r
+       sqshl   v1.4s,v2.4s,v3.4s\r
+       sqshl   v1.8b,v2.8b,1\r
+       sqshl   v1.8b,v2.8b,v3.8b\r
+       sqshl   v1.8h,v2.8h,15\r
+       sqshl   v1.8h,v2.8h,v3.8h\r
+\r
+       sqshlu  b1,b2,1\r
+       sqshlu  d1,d2,1\r
+       sqshlu  h1,h2,1\r
+       sqshlu  s1,s2,1\r
+       sqshlu  v1.16b,v2.16b,7\r
+       sqshlu  v1.2d,v2.2d,63\r
+       sqshlu  v1.2s,v2.2s,1\r
+       sqshlu  v1.4h,v2.4h,1\r
+       sqshlu  v1.4s,v2.4s,31\r
+       sqshlu  v1.8b,v2.8b,1\r
+       sqshlu  v1.8h,v2.8h,15\r
+\r
+       sqshrn  b8,h8,1\r
+       sqshrn  h4,s4,2\r
+       sqshrn  s2,d2,3\r
+       sqshrn  v1.2s,v2.2d,3\r
+       sqshrn  v1.4h,v2.4s,2\r
+       sqshrn  v1.8b,v2.8h,1\r
+\r
+       sqshrn2 v1.16b,v2.8h,1\r
+       sqshrn2 v1.4s,v2.2d,3\r
+       sqshrn2 v1.8h,v2.4s,2\r
+\r
+       sqshrun b8,h8,1\r
+       sqshrun h4,s4,2\r
+       sqshrun s2,d2,3\r
+       sqshrun v1.8b,v2.8h,1\r
+       sqshrun v1.4h,v2.4s,2\r
+       sqshrun v1.2s,v2.2d,3\r
+\r
+       sqshrun2        v1.16b,v2.8h,1\r
+       sqshrun2        v1.8h,v2.4s,2\r
+       sqshrun2        v1.4s,v2.2d,3\r
+\r
+       sqsub   b1,b2,b3\r
+       sqsub   d1,d2,d3\r
+       sqsub   h1,h2,h3\r
+       sqsub   s1,s2,s3\r
+       sqsub   v1.16b,v2.16b,v3.16b\r
+       sqsub   v1.2d,v2.2d,v3.2d\r
+       sqsub   v1.2s,v2.2s,v3.2s\r
+       sqsub   v1.4h,v2.4h,v3.4h\r
+       sqsub   v1.4s,v2.4s,v3.4s\r
+       sqsub   v1.8b,v2.8b,v3.8b\r
+       sqsub   v1.8h,v2.8h,v3.8h\r
+\r
+       sqxtn   b8,h8\r
+       sqxtn   h4,s4\r
+       sqxtn   s2,d2\r
+       sqxtn   v1.2s,v2.2d\r
+       sqxtn   v1.4h,v2.4s\r
+       sqxtn   v1.8b,v2.8h\r
+\r
+       sqxtn2  v1.16b,v2.8h\r
+       sqxtn2  v1.4s,v2.2d\r
+       sqxtn2  v1.8h,v2.4s\r
+\r
+       sqxtun  b8,h8\r
+       sqxtun  h4,s4\r
+       sqxtun  s2,d2\r
+       sqxtun  v1.2s,v2.2d\r
+       sqxtun  v1.4h,v2.4s\r
+       sqxtun  v1.8b,v2.8h\r
+\r
+       sqxtun2 v1.16b,v2.8h\r
+       sqxtun2 v1.4s,v2.2d\r
+       sqxtun2 v1.8h,v2.4s\r
+\r
+       srhadd  v1.16b,v2.16b,v3.16b\r
+       srhadd  v1.2s,v2.2s,v3.2s\r
+       srhadd  v1.4h,v2.4h,v3.4h\r
+       srhadd  v1.4s,v2.4s,v3.4s\r
+       srhadd  v1.8b,v2.8b,v3.8b\r
+       srhadd  v1.8h,v2.8h,v3.8h\r
+\r
+       sri     d1,d2,1\r
+       sri     v1.16b,v2.16b,8\r
+       sri     v1.2d,v2.2d,64\r
+       sri     v1.2s,v2.2s,1\r
+       sri     v1.4h,v2.4h,1\r
+       sri     v1.4s,v2.4s,32\r
+       sri     v1.8b,v2.8b,1\r
+       sri     v1.8h,v2.8h,16\r
+\r
+       srshl   d1,d2,d3\r
+       srshl   v1.16b,v2.16b,v3.16b\r
+       srshl   v1.2d,v2.2d,v3.2d\r
+       srshl   v1.2s,v2.2s,v3.2s\r
+       srshl   v1.4h,v2.4h,v3.4h\r
+       srshl   v1.4s,v2.4s,v3.4s\r
+       srshl   v1.8b,v2.8b,v3.8b\r
+       srshl   v1.8h,v2.8h,v3.8h\r
+\r
+       srshr   d1,d2,1\r
+       srshr   v1.16b,v2.16b,8\r
+       srshr   v1.2d,v2.2d,64\r
+       srshr   v1.2s,v2.2s,1\r
+       srshr   v1.4h,v2.4h,1\r
+       srshr   v1.4s,v2.4s,32\r
+       srshr   v1.8b,v2.8b,1\r
+       srshr   v1.8h,v2.8h,16\r
+\r
+       srsra   d1,d2,1\r
+       srsra   v1.16b,v2.16b,8\r
+       srsra   v1.2d,v2.2d,64\r
+       srsra   v1.2s,v2.2s,1\r
+       srsra   v1.4h,v2.4h,1\r
+       srsra   v1.4s,v2.4s,32\r
+       srsra   v1.8b,v2.8b,1\r
+       srsra   v1.8h,v2.8h,16\r
+\r
+       sshl    d1,d2,d3\r
+       sshl    v1.16b,v2.16b,v3.16b\r
+       sshl    v1.2d,v2.2d,v3.2d\r
+       sshl    v1.2s,v2.2s,v3.2s\r
+       sshl    v1.4h,v2.4h,v3.4h\r
+       sshl    v1.4s,v2.4s,v3.4s\r
+       sshl    v1.8b,v2.8b,v3.8b\r
+       sshl    v1.8h,v2.8h,v3.8h\r
+\r
+       sshll   v1.2d,v2.2s,3\r
+       sshll   v1.4s,v2.4h,2\r
+       sshll   v1.8h,v2.8b,1\r
+\r
+       sshll2  v1.2d,v2.4s,31\r
+       sshll2  v1.4s,v2.8h,15\r
+       sshll2  v1.8h,v2.16b,7\r
+\r
+       sshr    d1,d2,1\r
+       sshr    v1.16b,v2.16b,8\r
+       sshr    v1.2d,v2.2d,64\r
+       sshr    v1.2s,v2.2s,1\r
+       sshr    v1.4h,v2.4h,1\r
+       sshr    v1.4s,v2.4s,32\r
+       sshr    v1.8b,v2.8b,1\r
+       sshr    v1.8h,v2.8h,16\r
+\r
+       ssra    d1,d2,1\r
+       ssra    v1.16b,v2.16b,8\r
+       ssra    v1.2d,v2.2d,64\r
+       ssra    v1.2s,v2.2s,1\r
+       ssra    v1.4h,v2.4h,1\r
+       ssra    v1.4s,v2.4s,32\r
+       ssra    v1.8b,v2.8b,1\r
+       ssra    v1.8h,v2.8h,16\r
+\r
+       ssubl   v1.2d,v2.2s,v3.2s\r
+       ssubl   v1.4s,v2.4h,v3.4h\r
+       ssubl   v1.8h,v2.8b,v3.8b\r
+\r
+       ssubl2  v1.2d,v2.4s,v3.4s\r
+       ssubl2  v1.4s,v2.8h,v3.8h\r
+       ssubl2  v1.8h,v2.16b,v3.16b\r
+\r
+       ssubw   v1.2d,v2.2d,v3.2s\r
+       ssubw   v1.4s,v2.4s,v3.4h\r
+       ssubw   v1.8h,v2.8h,v3.8b\r
+\r
+       ssubw2  v1.2d,v2.2d,v3.4s\r
+       ssubw2  v1.4s,v2.4s,v3.8h\r
+       ssubw2  v1.8h,v2.8h,v3.16b\r
+\r
+       st1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp]\r
+       st1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp],64\r
+       st1     {v1.16b,v2.16b,v3.16b,v4.16b},[sp],x6\r
+       st1     {v1.16b,v2.16b,v3.16b},[x4]\r
+       st1     {v1.16b,v2.16b,v3.16b},[x4],48\r
+       st1     {v1.16b,v2.16b,v3.16b},[x4],x5\r
+       st1     {v1.16b,v2.16b},[x3]\r
+       st1     {v1.16b,v2.16b},[x3],32\r
+       st1     {v1.16b,v2.16b},[x3],x4\r
+       st1     {v1.16b},[x2]\r
+       st1     {v1.16b},[x2],16\r
+       st1     {v1.16b},[x2],x3\r
+       st1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp]\r
+       st1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp],32\r
+       st1     {v1.1d,v2.1d,v3.1d,v4.1d},[sp],x6\r
+       st1     {v1.1d,v2.1d,v3.1d},[x4]\r
+       st1     {v1.1d,v2.1d,v3.1d},[x4],24\r
+       st1     {v1.1d,v2.1d,v3.1d},[x4],x5\r
+       st1     {v1.1d,v2.1d},[x3]\r
+       st1     {v1.1d,v2.1d},[x3],16\r
+       st1     {v1.1d,v2.1d},[x3],x4\r
+       st1     {v1.1d},[x2]\r
+       st1     {v1.1d},[x2],8\r
+       st1     {v1.1d},[x2],x3\r
+       st1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp]\r
+       st1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp],64\r
+       st1     {v1.2d,v2.2d,v3.2d,v4.2d},[sp],x6\r
+       st1     {v1.2d,v2.2d,v3.2d},[x4]\r
+       st1     {v1.2d,v2.2d,v3.2d},[x4],48\r
+       st1     {v1.2d,v2.2d,v3.2d},[x4],x5\r
+       st1     {v1.2d,v2.2d},[x3]\r
+       st1     {v1.2d,v2.2d},[x3],32\r
+       st1     {v1.2d,v2.2d},[x3],x4\r
+       st1     {v1.2d},[x2]\r
+       st1     {v1.2d},[x2],16\r
+       st1     {v1.2d},[x2],x3\r
+       st1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp]\r
+       st1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp],32\r
+       st1     {v1.2s,v2.2s,v3.2s,v4.2s},[sp],x6\r
+       st1     {v1.2s,v2.2s,v3.2s},[x4]\r
+       st1     {v1.2s,v2.2s,v3.2s},[x4],24\r
+       st1     {v1.2s,v2.2s,v3.2s},[x4],x5\r
+       st1     {v1.2s,v2.2s},[x3]\r
+       st1     {v1.2s,v2.2s},[x3],16\r
+       st1     {v1.2s,v2.2s},[x3],x4\r
+       st1     {v1.2s},[x2]\r
+       st1     {v1.2s},[x2],8\r
+       st1     {v1.2s},[x2],x3\r
+       st1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp]\r
+       st1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp],32\r
+       st1     {v1.4h,v2.4h,v3.4h,v4.4h},[sp],x6\r
+       st1     {v1.4h,v2.4h,v3.4h},[x4]\r
+       st1     {v1.4h,v2.4h,v3.4h},[x4],24\r
+       st1     {v1.4h,v2.4h,v3.4h},[x4],x5\r
+       st1     {v1.4h,v2.4h},[x3]\r
+       st1     {v1.4h,v2.4h},[x3],16\r
+       st1     {v1.4h,v2.4h},[x3],x4\r
+       st1     {v1.4h},[x2]\r
+       st1     {v1.4h},[x2],8\r
+       st1     {v1.4h},[x2],x3\r
+       st1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp]\r
+       st1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp],64\r
+       st1     {v1.4s,v2.4s,v3.4s,v4.4s},[sp],x6\r
+       st1     {v1.4s,v2.4s,v3.4s},[x4]\r
+       st1     {v1.4s,v2.4s,v3.4s},[x4],48\r
+       st1     {v1.4s,v2.4s,v3.4s},[x4],x5\r
+       st1     {v1.4s,v2.4s},[x3]\r
+       st1     {v1.4s,v2.4s},[x3],32\r
+       st1     {v1.4s,v2.4s},[x3],x4\r
+       st1     {v1.4s},[x2]\r
+       st1     {v1.4s},[x2],16\r
+       st1     {v1.4s},[x2],x3\r
+       st1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp]\r
+       st1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp],32\r
+       st1     {v1.8b,v2.8b,v3.8b,v4.8b},[sp],x6\r
+       st1     {v1.8b,v2.8b,v3.8b},[x4]\r
+       st1     {v1.8b,v2.8b,v3.8b},[x4],24\r
+       st1     {v1.8b,v2.8b,v3.8b},[x4],x5\r
+       st1     {v1.8b,v2.8b},[x3]\r
+       st1     {v1.8b,v2.8b},[x3],16\r
+       st1     {v1.8b,v2.8b},[x3],x4\r
+       st1     {v1.8b},[x2]\r
+       st1     {v1.8b},[x2],8\r
+       st1     {v1.8b},[x2],x3\r
+       st1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp]\r
+       st1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp],64\r
+       st1     {v1.8h,v2.8h,v3.8h,v4.8h},[sp],x6\r
+       st1     {v1.8h,v2.8h,v3.8h},[x4]\r
+       st1     {v1.8h,v2.8h,v3.8h},[x4],48\r
+       st1     {v1.8h,v2.8h,v3.8h},[x4],x5\r
+       st1     {v1.8h,v2.8h},[x3]\r
+       st1     {v1.8h,v2.8h},[x3],32\r
+       st1     {v1.8h,v2.8h},[x3],x4\r
+       st1     {v1.8h},[x2]\r
+       st1     {v1.8h},[x2],16\r
+       st1     {v1.8h},[x2],x3\r
+       st1     {v1.b}[2],[x3]\r
+       st1     {v1.b}[2],[x3],1\r
+       st1     {v1.b}[2],[x3],x4\r
+       st1     {v1.d}[1],[x3]\r
+       st1     {v1.d}[1],[x3],8\r
+       st1     {v1.d}[1],[x3],x4\r
+       st1     {v1.h}[2],[x3]\r
+       st1     {v1.h}[2],[x3],2\r
+       st1     {v1.h}[2],[x3],x4\r
+       st1     {v1.s}[2],[x3]\r
+       st1     {v1.s}[2],[x3],4\r
+       st1     {v1.s}[2],[x3],x4\r
+\r
+       st2     {v1.16b,v2.16b},[x3]\r
+       st2     {v1.16b,v2.16b},[x3],32\r
+       st2     {v1.16b,v2.16b},[x3],x4\r
+       st2     {v1.2d,v2.2d},[x3]\r
+       st2     {v1.2d,v2.2d},[x3],32\r
+       st2     {v1.2d,v2.2d},[x3],x4\r
+       st2     {v1.2s,v2.2s},[x3]\r
+       st2     {v1.2s,v2.2s},[x3],16\r
+       st2     {v1.2s,v2.2s},[x3],x4\r
+       st2     {v1.4h,v2.4h},[x3]\r
+       st2     {v1.4h,v2.4h},[x3],16\r
+       st2     {v1.4h,v2.4h},[x3],x4\r
+       st2     {v1.4s,v2.4s},[x3]\r
+       st2     {v1.4s,v2.4s},[x3],32\r
+       st2     {v1.4s,v2.4s},[x3],x4\r
+       st2     {v1.8b,v2.8b},[x3]\r
+       st2     {v1.8b,v2.8b},[x3],16\r
+       st2     {v1.8b,v2.8b},[x3],x4\r
+       st2     {v1.8h,v2.8h},[x3]\r
+       st2     {v1.8h,v2.8h},[x3],32\r
+       st2     {v1.8h,v2.8h},[x3],x4\r
+       st2     {v1.b,v2.b}[15],[x3]\r
+       st2     {v1.b,v2.b}[2],[x3],2\r
+       st2     {v1.b,v2.b}[2],[x3],x4\r
+       st2     {v1.d,v2.d}[1],[x3]\r
+       st2     {v1.d,v2.d}[1],[x3],16\r
+       st2     {v1.d,v2.d}[1],[x3],x4\r
+       st2     {v1.h,v2.h}[2],[x3]\r
+       st2     {v1.h,v2.h}[2],[x3],4\r
+       st2     {v1.h,v2.h}[2],[x3],x4\r
+       st2     {v1.s,v2.s}[2],[x3]\r
+       st2     {v1.s,v2.s}[2],[x3],8\r
+       st2     {v1.s,v2.s}[2],[x3],x4\r
+\r
+       st3     {v1.16b,v2.16b,v3.16b},[x3]\r
+       st3     {v1.16b,v2.16b,v3.16b},[x3],48\r
+       st3     {v1.16b,v2.16b,v3.16b},[x3],x4\r
+       st3     {v1.2d,v2.2d,v3.2d},[x3]\r
+       st3     {v1.2d,v2.2d,v3.2d},[x3],48\r
+       st3     {v1.2d,v2.2d,v3.2d},[x3],x4\r
+       st3     {v1.2s,v2.2s,v3.2s},[x3]\r
+       st3     {v1.2s,v2.2s,v3.2s},[x3],24\r
+       st3     {v1.2s,v2.2s,v3.2s},[x3],x4\r
+       st3     {v1.4h,v2.4h,v3.4h},[x3]\r
+       st3     {v1.4h,v2.4h,v3.4h},[x3],24\r
+       st3     {v1.4h,v2.4h,v3.4h},[x3],x4\r
+       st3     {v1.4s,v2.4s,v3.4s},[x3]\r
+       st3     {v1.4s,v2.4s,v3.4s},[x3],48\r
+       st3     {v1.4s,v2.4s,v3.4s},[x3],x4\r
+       st3     {v1.8b,v2.8b,v3.8b},[x3]\r
+       st3     {v1.8b,v2.8b,v3.8b},[x3],24\r
+       st3     {v1.8b,v2.8b,v3.8b},[x3],x4\r
+       st3     {v1.8h,v2.8h,v3.8h},[x3]\r
+       st3     {v1.8h,v2.8h,v3.8h},[x3],48\r
+       st3     {v1.8h,v2.8h,v3.8h},[x3],x4\r
+       st3     {v1.b,v2.b,v3.b}[15],[x3]\r
+       st3     {v1.b,v2.b,v3.b}[2],[x3],3\r
+       st3     {v1.b,v2.b,v3.b}[2],[x3],x4\r
+       st3     {v1.d,v2.d,v3.d}[1],[x3]\r
+       st3     {v1.d,v2.d,v3.d}[1],[x3],24\r
+       st3     {v1.d,v2.d,v3.d}[1],[x3],x4\r
+       st3     {v1.h,v2.h,v3.h}[2],[x3]\r
+       st3     {v1.h,v2.h,v3.h}[2],[x3],6\r
+       st3     {v1.h,v2.h,v3.h}[2],[x3],x4\r
+       st3     {v1.s,v2.s,v3.s}[2],[x3]\r
+       st3     {v1.s,v2.s,v3.s}[2],[x3],12\r
+       st3     {v1.s,v2.s,v3.s}[2],[x3],x4\r
+\r
+       st4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3]\r
+       st4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3],64\r
+       st4     {v1.16b,v2.16b,v3.16b,v4.16b},[x3],x4\r
+       st4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3]\r
+       st4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3],64\r
+       st4     {v1.2d,v2.2d,v3.2d,v4.2d},[x3],x4\r
+       st4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3]\r
+       st4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3],32\r
+       st4     {v1.2s,v2.2s,v3.2s,v4.2s},[x3],x4\r
+       st4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3]\r
+       st4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3],32\r
+       st4     {v1.4h,v2.4h,v3.4h,v4.4h},[x3],x4\r
+       st4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3]\r
+       st4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3],64\r
+       st4     {v1.4s,v2.4s,v3.4s,v4.4s},[x3],x4\r
+       st4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3]\r
+       st4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3],32\r
+       st4     {v1.8b,v2.8b,v3.8b,v4.8b},[x3],x4\r
+       st4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3]\r
+       st4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3],64\r
+       st4     {v1.8h,v2.8h,v3.8h,v4.8h},[x3],x4\r
+       st4     {v1.b,v2.b,v3.b,v4.b}[15],[x3]\r
+       st4     {v1.b,v2.b,v3.b,v4.b}[2],[x3],4\r
+       st4     {v1.b,v2.b,v3.b,v4.b}[2],[x3],x4\r
+       st4     {v1.d,v2.d,v3.d,v4.d}[1],[x3]\r
+       st4     {v1.d,v2.d,v3.d,v4.d}[1],[x3],32\r
+       st4     {v1.d,v2.d,v3.d,v4.d}[1],[x3],x4\r
+       st4     {v1.h,v2.h,v3.h,v4.h}[2],[x3]\r
+       st4     {v1.h,v2.h,v3.h,v4.h}[2],[x3],8\r
+       st4     {v1.h,v2.h,v3.h,v4.h}[2],[x3],x4\r
+       st4     {v1.s,v2.s,v3.s,v4.s}[2],[x3]\r
+       st4     {v1.s,v2.s,v3.s,v4.s}[2],[x3],16\r
+       st4     {v1.s,v2.s,v3.s,v4.s}[2],[x3],x4\r
+\r
+       stnp    d0,d1,[x2]\r
+       stnp    d0,d1,[x2,+0x8]\r
+       stnp    d0,d1,[expression.qword]\r
+       stnp    q0,q1,[x2]\r
+       stnp    q0,q1,[x2,+0x20]\r
+       stnp    q0,q1,[expression.dqword]\r
+       stnp    s0,s1,[x2]\r
+       stnp    s0,s1,[x2,+0x8]\r
+       stnp    s0,s1,[expression.dword]\r
+\r
+       stp     d0,d1,[x2]\r
+       stp     d0,d1,[x2,+0x8]\r
+       stp     d0,d1,[expression.qword]\r
+       stp     d0,d1,[x2,+0x8]!\r
+       stp     d0,d1,[expression.qword]!\r
+       stp     d0,d1,[x2],+0x8\r
+       stp     q0,q1,[x2]\r
+       stp     q0,q1,[x2,+0x10]\r
+       stp     q0,q1,[expression.dqword]\r
+       stp     q0,q1,[x2,+0x10]!\r
+       stp     q0,q1,[expression.dqword]!\r
+       stp     q0,q1,[x2],+0x10\r
+       stp     s0,s1,[x2]\r
+       stp     s0,s1,[x2,+0x8]\r
+       stp     s0,s1,[expression.dword]\r
+       stp     s0,s1,[x2,+0x8]!\r
+       stp     s0,s1,[expression.dword]!\r
+       stp     s0,s1,[x2],+0x8\r
+\r
+       str     b0,[x2]\r
+       str     b0,[x2,+0x8]\r
+       str     b0,[expression.byte]\r
+       str     b0,[x2,+0x8]!\r
+       str     b0,[expression.byte]!\r
+       str     b0,[x2],+0x8\r
+       str     b0,[x2,w3,sxtw]\r
+       str     b0,[x2,w3,sxtw 0]\r
+       str     b0,[x2,w3,uxtw]\r
+       str     b0,[x2,w3,uxtw 0]\r
+       str     b0,[x2,x3]\r
+       str     b0,[x2,x3,lsl 0]\r
+       str     b0,[x2,x3,sxtx]\r
+       str     b0,[x2,x3,sxtx 0]\r
+       str     h0,[x2]\r
+       str     h0,[x2,+0x8]\r
+       str     h0,[expression.hword]\r
+       str     h0,[x2,+0x8]!\r
+       str     h0,[expression.hword]!\r
+       str     h0,[x2],+0x8\r
+       str     h0,[x2,w3,sxtw]\r
+       str     h0,[x2,w3,sxtw 1]\r
+       str     h0,[x2,w3,uxtw]\r
+       str     h0,[x2,w3,uxtw 1]\r
+       str     h0,[x2,x3]\r
+       str     h0,[x2,x3,lsl 1]\r
+       str     h0,[x2,x3,sxtx]\r
+       str     h0,[x2,x3,sxtx 1]\r
+       str     s0,[x2,+0x8]\r
+       str     s0,[expression.word]\r
+       str     s0,[x2,+0x8]!\r
+       str     s0,[expression.word]!\r
+       str     s0,[x2],+0x8\r
+       str     s0,[x2,w3,sxtw]\r
+       str     s0,[x2,w3,sxtw 2]\r
+       str     s0,[x2,w3,uxtw]\r
+       str     s0,[x2,w3,uxtw 2]\r
+       str     s0,[x2,x3]\r
+       str     s0,[x2,x3,lsl 2]\r
+       str     s0,[x2,x3,sxtx]\r
+       str     s0,[x2,x3,sxtx 2]\r
+       str     d0,[x2,+0x8]\r
+       str     d0,[expression.dword]\r
+       str     d0,[x2,+0x8]!\r
+       str     d0,[expression.dword]!\r
+       str     d0,[x2],+0x8\r
+       str     d0,[x2,w3,sxtw]\r
+       str     d0,[x2,w3,sxtw 3]\r
+       str     d0,[x2,w3,uxtw]\r
+       str     d0,[x2,w3,uxtw 3]\r
+       str     d0,[x2,x3]\r
+       str     d0,[x2,x3,lsl 3]\r
+       str     d0,[x2,x3,sxtx]\r
+       str     d0,[x2,x3,sxtx 3]\r
+       str     q0,[x2,+0x8]\r
+       str     q0,[expression.qword]\r
+       str     q0,[x2,+0x8]!\r
+       str     q0,[expression.qword]!\r
+       str     q0,[x2],+0x8\r
+       str     q0,[x2,w3,sxtw]\r
+       str     q0,[x2,w3,sxtw 4]\r
+       str     q0,[x2,w3,uxtw]\r
+       str     q0,[x2,w3,uxtw 4]\r
+       str     q0,[x2,x3]\r
+       str     q0,[x2,x3,lsl 4]\r
+       str     q0,[x2,x3,sxtx]\r
+       str     q0,[x2,x3,sxtx 4]\r
+\r
+       stur    b0,[x2]\r
+       stur    b0,[x2,+0x8]\r
+       stur    b0,[expression.byte]\r
+       stur    h0,[x2]\r
+       stur    h0,[x2,+0x8]\r
+       stur    h0,[expression.hword]\r
+       stur    s0,[x2]\r
+       stur    s0,[x2,+0x8]\r
+       stur    s0,[expression.word]\r
+       stur    d0,[x2]\r
+       stur    d0,[x2,+0x8]\r
+       stur    d0,[expression.dword]\r
+       stur    q0,[x2]\r
+       stur    q0,[x2,+0x8]\r
+       stur    q0,[expression.qword]\r
+\r
+       sub     d1,d2,d3\r
+       sub     v1.16b,v2.16b,v3.16b\r
+       sub     v1.2d,v2.2d,v3.2d\r
+       sub     v1.2s,v2.2s,v3.2s\r
+       sub     v1.4h,v2.4h,v3.4h\r
+       sub     v1.4s,v2.4s,v3.4s\r
+       sub     v1.8b,v2.8b,v3.8b\r
+       sub     v1.8h,v2.8h,v3.8h\r
+\r
+       subhn   v1.2s,v2.2d,v3.2d\r
+       subhn   v1.4h,v2.4s,v3.4s\r
+       subhn   v1.8b,v2.8h,v3.8h\r
+\r
+       subhn2  v1.16b,v2.8h,v3.8h\r
+       subhn2  v1.4s,v2.2d,v3.2d\r
+       subhn2  v1.8h,v2.4s,v3.4s\r
+\r
+       suqadd  b1,b2\r
+       suqadd  d1,d2\r
+       suqadd  h1,h2\r
+       suqadd  s1,s2\r
+       suqadd  v1.16b,v2.16b\r
+       suqadd  v1.2d,v2.2d\r
+       suqadd  v1.2s,v2.2s\r
+       suqadd  v1.4h,v2.4h\r
+       suqadd  v1.4s,v2.4s\r
+       suqadd  v1.8b,v2.8b\r
+       suqadd  v1.8h,v2.8h\r
+\r
+       sxtl    v1.2d,v2.2s\r
+       sxtl    v1.4s,v2.4h\r
+       sxtl    v1.8h,v2.8b\r
+\r
+       sxtl2   v1.2d,v2.4s\r
+       sxtl2   v1.4s,v2.8h\r
+       sxtl2   v1.8h,v2.16b\r
+\r
+       tbl     v1.8b,{v2.16b},v6.8b\r
+       tbl     v1.8b,{v2.16b,v3.16b},v6.8b\r
+       tbl     v1.8b,{v2.16b,v3.16b,v4.16b},v6.8b\r
+       tbl     v1.8b,{v2.16b,v3.16b,v4.16b,v5.16b},v6.8b\r
+\r
+       tbx     v1.8b,{v2.16b},v6.8b\r
+       tbx     v1.8b,{v2.16b,v3.16b},v6.8b\r
+       tbx     v1.8b,{v2.16b,v3.16b,v4.16b},v6.8b\r
+       tbx     v1.8b,{v2.16b,v3.16b,v4.16b,v5.16b},v6.8b\r
+\r
+       trn1    v1.16b,v2.16b,v3.16b\r
+       trn1    v1.2d,v2.2d,v3.2d\r
+       trn1    v1.2s,v2.2s,v3.2s\r
+       trn1    v1.4h,v2.4h,v3.4h\r
+       trn1    v1.4s,v2.4s,v3.4s\r
+       trn1    v1.8b,v2.8b,v3.8b\r
+       trn1    v1.8h,v2.8h,v3.8h\r
+\r
+       trn2    v1.16b,v2.16b,v3.16b\r
+       trn2    v1.2d,v2.2d,v3.2d\r
+       trn2    v1.2s,v2.2s,v3.2s\r
+       trn2    v1.4h,v2.4h,v3.4h\r
+       trn2    v1.4s,v2.4s,v3.4s\r
+       trn2    v1.8b,v2.8b,v3.8b\r
+       trn2    v1.8h,v2.8h,v3.8h\r
+\r
+       uaba    v1.16b,v2.16b,v3.16b\r
+       uaba    v1.2s,v2.2s,v3.2s\r
+       uaba    v1.4h,v2.4h,v3.4h\r
+       uaba    v1.4s,v2.4s,v3.4s\r
+       uaba    v1.8b,v2.8b,v3.8b\r
+       uaba    v1.8h,v2.8h,v3.8h\r
+\r
+       uabal   v1.2d,v2.2s,v3.2s\r
+       uabal   v1.4s,v2.4h,v3.4h\r
+       uabal   v1.8h,v2.8b,v3.8b\r
+\r
+       uabal2  v1.2d,v2.4s,v3.4s\r
+       uabal2  v1.4s,v2.8h,v3.8h\r
+       uabal2  v1.8h,v2.16b,v3.16b\r
+\r
+       uabd    v1.16b,v2.16b,v3.16b\r
+       uabd    v1.2s,v2.2s,v3.2s\r
+       uabd    v1.4h,v2.4h,v3.4h\r
+       uabd    v1.4s,v2.4s,v3.4s\r
+       uabd    v1.8b,v2.8b,v3.8b\r
+       uabd    v1.8h,v2.8h,v3.8h\r
+\r
+       uabdl   v1.2d,v2.2s,v3.2s\r
+       uabdl   v1.4s,v2.4h,v3.4h\r
+       uabdl   v1.8h,v2.8b,v3.8b\r
+\r
+       uabdl2  v1.2d,v2.4s,v3.4s\r
+       uabdl2  v1.4s,v2.8h,v3.8h\r
+       uabdl2  v1.8h,v2.16b,v3.16b\r
+\r
+       uadalp  v1.1d,v2.2s\r
+       uadalp  v1.2d,v2.4s\r
+       uadalp  v1.2s,v2.4h\r
+       uadalp  v1.4h,v2.8b\r
+       uadalp  v1.4s,v2.8h\r
+       uadalp  v1.8h,v2.16b\r
+\r
+       uaddl   v1.2d,v2.2s,v3.2s\r
+       uaddl   v1.4s,v2.4h,v3.4h\r
+       uaddl   v1.8h,v2.8b,v3.8b\r
+\r
+       uaddl2  v1.2d,v2.4s,v3.4s\r
+       uaddl2  v1.4s,v2.8h,v3.8h\r
+       uaddl2  v1.8h,v2.16b,v3.16b\r
+\r
+       uaddlp  v1.1d,v2.2s\r
+       uaddlp  v1.2d,v2.4s\r
+       uaddlp  v1.2s,v2.4h\r
+       uaddlp  v1.4h,v2.8b\r
+       uaddlp  v1.4s,v2.8h\r
+       uaddlp  v1.8h,v2.16b\r
+\r
+       uaddlv  d1,v2.4s\r
+       uaddlv  h1,v2.16b\r
+       uaddlv  h1,v2.8b\r
+       uaddlv  s1,v2.4h\r
+       uaddlv  s1,v2.8h\r
+\r
+       uaddw   v1.2d,v2.2d,v3.2s\r
+       uaddw   v1.4s,v2.4s,v3.4h\r
+       uaddw   v1.8h,v2.8h,v3.8b\r
+\r
+       uaddw2  v1.2d,v2.2d,v3.4s\r
+       uaddw2  v1.4s,v2.4s,v3.8h\r
+       uaddw2  v1.8h,v2.8h,v3.16b\r
+\r
+       uhadd   v1.16b,v2.16b,v3.16b\r
+       uhadd   v1.2s,v2.2s,v3.2s\r
+       uhadd   v1.4h,v2.4h,v3.4h\r
+       uhadd   v1.4s,v2.4s,v3.4s\r
+       uhadd   v1.8b,v2.8b,v3.8b\r
+       uhadd   v1.8h,v2.8h,v3.8h\r
+\r
+       uhsub   v1.16b,v2.16b,v3.16b\r
+       uhsub   v1.2s,v2.2s,v3.2s\r
+       uhsub   v1.4h,v2.4h,v3.4h\r
+       uhsub   v1.4s,v2.4s,v3.4s\r
+       uhsub   v1.8b,v2.8b,v3.8b\r
+       uhsub   v1.8h,v2.8h,v3.8h\r
+\r
+       umax    v1.16b,v2.16b,v3.16b\r
+       umax    v1.2s,v2.2s,v3.2s\r
+       umax    v1.4h,v2.4h,v3.4h\r
+       umax    v1.4s,v2.4s,v3.4s\r
+       umax    v1.8b,v2.8b,v3.8b\r
+       umax    v1.8h,v2.8h,v3.8h\r
+\r
+       umaxp   v1.16b,v2.16b,v3.16b\r
+       umaxp   v1.2s,v2.2s,v3.2s\r
+       umaxp   v1.4h,v2.4h,v3.4h\r
+       umaxp   v1.4s,v2.4s,v3.4s\r
+       umaxp   v1.8b,v2.8b,v3.8b\r
+       umaxp   v1.8h,v2.8h,v3.8h\r
+\r
+       umaxv   b1,v2.16b\r
+       umaxv   b1,v2.8b\r
+       umaxv   h1,v2.4h\r
+       umaxv   h1,v2.8h\r
+       umaxv   s1,v2.4s\r
+\r
+       umin    v1.16b,v2.16b,v3.16b\r
+       umin    v1.2s,v2.2s,v3.2s\r
+       umin    v1.4h,v2.4h,v3.4h\r
+       umin    v1.4s,v2.4s,v3.4s\r
+       umin    v1.8b,v2.8b,v3.8b\r
+       umin    v1.8h,v2.8h,v3.8h\r
+\r
+       uminp   v1.16b,v2.16b,v3.16b\r
+       uminp   v1.2s,v2.2s,v3.2s\r
+       uminp   v1.4h,v2.4h,v3.4h\r
+       uminp   v1.4s,v2.4s,v3.4s\r
+       uminp   v1.8b,v2.8b,v3.8b\r
+       uminp   v1.8h,v2.8h,v3.8h\r
+\r
+       uminv   b1,v2.16b\r
+       uminv   b1,v2.8b\r
+       uminv   h1,v2.4h\r
+       uminv   h1,v2.8h\r
+       uminv   s1,v2.4s\r
+\r
+       umlal   v1.2d,v2.2s,v3.2s\r
+       umlal   v1.2d,v2.2s,v31.s[3]\r
+       umlal   v1.4s,v2.4h,v15.h[7]\r
+       umlal   v1.4s,v2.4h,v3.4h\r
+       umlal   v1.8h,v2.8b,v3.8b\r
+\r
+       umlal2  v1.2d,v2.4s,v3.4s\r
+       umlal2  v1.2d,v2.4s,v31.s[3]\r
+       umlal2  v1.4s,v2.8h,v15.h[7]\r
+       umlal2  v1.4s,v2.8h,v3.8h\r
+       umlal2  v1.8h,v2.16b,v3.16b\r
+\r
+       umlsl   v1.2d,v2.2s,v3.2s\r
+       umlsl   v1.2d,v2.2s,v31.s[3]\r
+       umlsl   v1.4s,v2.4h,v15.h[7]\r
+       umlsl   v1.4s,v2.4h,v3.4h\r
+       umlsl   v1.8h,v2.8b,v3.8b\r
+\r
+       umlsl2  v1.2d,v2.4s,v3.4s\r
+       umlsl2  v1.2d,v2.4s,v31.s[3]\r
+       umlsl2  v1.4s,v2.8h,v15.h[7]\r
+       umlsl2  v1.4s,v2.8h,v3.8h\r
+       umlsl2  v1.8h,v2.16b,v3.16b\r
+\r
+       umov    w1,v2.b[15]\r
+       umov    w1,v2.h[4]\r
+       umov    w1,v2.s[2]\r
+       umov    x1,v2.d[1]\r
+\r
+       umull   v1.2d,v2.2s,v3.2s\r
+       umull   v1.2d,v2.2s,v3.s[0]\r
+       umull   v1.2d,v2.2s,v3.s[2]\r
+       umull   v1.4s,v2.4h,v3.4h\r
+       umull   v1.4s,v2.4h,v3.h[0]\r
+       umull   v1.4s,v2.4h,v3.h[4]\r
+       umull   v1.8h,v2.8b,v3.8b\r
+\r
+       umull2  v1.2d,v2.4s,v3.4s\r
+       umull2  v1.2d,v2.4s,v31.s[3]\r
+       umull2  v1.4s,v2.8h,v15.h[7]\r
+       umull2  v1.4s,v2.8h,v3.8h\r
+       umull2  v1.8h,v2.16b,v3.16b\r
+\r
+       uqadd   b1,b2,b3\r
+       uqadd   d1,d2,d3\r
+       uqadd   h1,h2,h3\r
+       uqadd   s1,s2,s3\r
+       uqadd   v1.16b,v2.16b,v3.16b\r
+       uqadd   v1.2d,v2.2d,v3.2d\r
+       uqadd   v1.2s,v2.2s,v3.2s\r
+       uqadd   v1.4h,v2.4h,v3.4h\r
+       uqadd   v1.4s,v2.4s,v3.4s\r
+       uqadd   v1.8b,v2.8b,v3.8b\r
+       uqadd   v1.8h,v2.8h,v3.8h\r
+\r
+       uqrshl  b1,b2,b3\r
+       uqrshl  d1,d2,d3\r
+       uqrshl  h1,h2,h3\r
+       uqrshl  s1,s2,s3\r
+       uqrshl  v1.16b,v2.16b,v3.16b\r
+       uqrshl  v1.2d,v2.2d,v3.2d\r
+       uqrshl  v1.2s,v2.2s,v3.2s\r
+       uqrshl  v1.4h,v2.4h,v3.4h\r
+       uqrshl  v1.4s,v2.4s,v3.4s\r
+       uqrshl  v1.8b,v2.8b,v3.8b\r
+       uqrshl  v1.8h,v2.8h,v3.8h\r
+\r
+       uqrshrn b8,h8,1\r
+       uqrshrn h4,s4,2\r
+       uqrshrn s2,d2,3\r
+       uqrshrn v1.2s,v2.2d,3\r
+       uqrshrn v1.4h,v2.4s,2\r
+       uqrshrn v1.8b,v2.8h,1\r
+\r
+       uqrshrn2        v1.16b,v2.8h,1\r
+       uqrshrn2        v1.4s,v2.2d,3\r
+       uqrshrn2        v1.8h,v2.4s,2\r
+\r
+       uqshl   b1,b2,7\r
+       uqshl   b1,b2,b3\r
+       uqshl   d1,d2,63\r
+       uqshl   d1,d2,d3\r
+       uqshl   h1,h2,15\r
+       uqshl   h1,h2,h3\r
+       uqshl   s1,s2,31\r
+       uqshl   s1,s2,s3\r
+       uqshl   v1.16b,v2.16b,7\r
+       uqshl   v1.16b,v2.16b,v3.16b\r
+       uqshl   v1.2d,v2.2d,63\r
+       uqshl   v1.2d,v2.2d,v3.2d\r
+       uqshl   v1.2s,v2.2s,1\r
+       uqshl   v1.2s,v2.2s,v3.2s\r
+       uqshl   v1.4h,v2.4h,1\r
+       uqshl   v1.4h,v2.4h,v3.4h\r
+       uqshl   v1.4s,v2.4s,31\r
+       uqshl   v1.4s,v2.4s,v3.4s\r
+       uqshl   v1.8b,v2.8b,1\r
+       uqshl   v1.8b,v2.8b,v3.8b\r
+       uqshl   v1.8h,v2.8h,15\r
+       uqshl   v1.8h,v2.8h,v3.8h\r
+\r
+       uqshrn  b8,h8,1\r
+       uqshrn  h4,s4,2\r
+       uqshrn  s2,d2,3\r
+       uqshrn  v1.2s,v2.2d,3\r
+       uqshrn  v1.4h,v2.4s,2\r
+       uqshrn  v1.8b,v2.8h,1\r
+\r
+       uqshrn2 v1.16b,v2.8h,1\r
+       uqshrn2 v1.4s,v2.2d,3\r
+       uqshrn2 v1.8h,v2.4s,2\r
+\r
+       uqsub   b1,b2,b3\r
+       uqsub   d1,d2,d3\r
+       uqsub   h1,h2,h3\r
+       uqsub   s1,s2,s3\r
+       uqsub   v1.16b,v2.16b,v3.16b\r
+       uqsub   v1.2d,v2.2d,v3.2d\r
+       uqsub   v1.2s,v2.2s,v3.2s\r
+       uqsub   v1.4h,v2.4h,v3.4h\r
+       uqsub   v1.4s,v2.4s,v3.4s\r
+       uqsub   v1.8b,v2.8b,v3.8b\r
+       uqsub   v1.8h,v2.8h,v3.8h\r
+\r
+       uqxtn   b8,h8\r
+       uqxtn   h4,s4\r
+       uqxtn   s2,d2\r
+       uqxtn   v1.2s,v2.2d\r
+       uqxtn   v1.4h,v2.4s\r
+       uqxtn   v1.8b,v2.8h\r
+\r
+       uqxtn2  v1.16b,v2.8h\r
+       uqxtn2  v1.4s,v2.2d\r
+       uqxtn2  v1.8h,v2.4s\r
+\r
+       urhadd  v1.16b,v2.16b,v3.16b\r
+       urhadd  v1.2s,v2.2s,v3.2s\r
+       urhadd  v1.4h,v2.4h,v3.4h\r
+       urhadd  v1.4s,v2.4s,v3.4s\r
+       urhadd  v1.8b,v2.8b,v3.8b\r
+       urhadd  v1.8h,v2.8h,v3.8h\r
+\r
+       urshl   d1,d2,d3\r
+       urshl   v1.16b,v2.16b,v3.16b\r
+       urshl   v1.2d,v2.2d,v3.2d\r
+       urshl   v1.2s,v2.2s,v3.2s\r
+       urshl   v1.4h,v2.4h,v3.4h\r
+       urshl   v1.4s,v2.4s,v3.4s\r
+       urshl   v1.8b,v2.8b,v3.8b\r
+       urshl   v1.8h,v2.8h,v3.8h\r
+\r
+       urshr   d1,d2,1\r
+       urshr   v1.16b,v2.16b,8\r
+       urshr   v1.2d,v2.2d,64\r
+       urshr   v1.2s,v2.2s,1\r
+       urshr   v1.4h,v2.4h,1\r
+       urshr   v1.4s,v2.4s,32\r
+       urshr   v1.8b,v2.8b,1\r
+       urshr   v1.8h,v2.8h,16\r
+\r
+       ursra   d1,d2,1\r
+       ursra   v1.16b,v2.16b,8\r
+       ursra   v1.2d,v2.2d,64\r
+       ursra   v1.2s,v2.2s,1\r
+       ursra   v1.4h,v2.4h,1\r
+       ursra   v1.4s,v2.4s,32\r
+       ursra   v1.8b,v2.8b,1\r
+       ursra   v1.8h,v2.8h,16\r
+\r
+       ushl    d1,d2,d3\r
+       ushl    v1.16b,v2.16b,v3.16b\r
+       ushl    v1.2d,v2.2d,v3.2d\r
+       ushl    v1.2s,v2.2s,v3.2s\r
+       ushl    v1.4h,v2.4h,v3.4h\r
+       ushl    v1.4s,v2.4s,v3.4s\r
+       ushl    v1.8b,v2.8b,v3.8b\r
+       ushl    v1.8h,v2.8h,v3.8h\r
+\r
+       ushll   v1.2d,v2.2s,3\r
+       ushll   v1.4s,v2.4h,2\r
+       ushll   v1.8h,v2.8b,1\r
+\r
+       ushll2  v1.2d,v2.4s,31\r
+       ushll2  v1.4s,v2.8h,15\r
+       ushll2  v1.8h,v2.16b,7\r
+\r
+       ushr    d1,d2,1\r
+       ushr    v1.16b,v2.16b,8\r
+       ushr    v1.2d,v2.2d,64\r
+       ushr    v1.2s,v2.2s,1\r
+       ushr    v1.4h,v2.4h,1\r
+       ushr    v1.4s,v2.4s,32\r
+       ushr    v1.8b,v2.8b,1\r
+       ushr    v1.8h,v2.8h,16\r
+\r
+       usqadd  b1,b2\r
+       usqadd  d1,d2\r
+       usqadd  h1,h2\r
+       usqadd  s1,s2\r
+       usqadd  v1.16b,v2.16b\r
+       usqadd  v1.2d,v2.2d\r
+       usqadd  v1.2s,v2.2s\r
+       usqadd  v1.4h,v2.4h\r
+       usqadd  v1.4s,v2.4s\r
+       usqadd  v1.8b,v2.8b\r
+       usqadd  v1.8h,v2.8h\r
+\r
+       usra    d1,d2,1\r
+       usra    v1.16b,v2.16b,8\r
+       usra    v1.2d,v2.2d,64\r
+       usra    v1.2s,v2.2s,1\r
+       usra    v1.4h,v2.4h,1\r
+       usra    v1.4s,v2.4s,32\r
+       usra    v1.8b,v2.8b,1\r
+       usra    v1.8h,v2.8h,16\r
+\r
+       usubl   v1.2d,v2.2s,v3.2s\r
+       usubl   v1.4s,v2.4h,v3.4h\r
+       usubl   v1.8h,v2.8b,v3.8b\r
+\r
+       usubl2  v1.2d,v2.4s,v3.4s\r
+       usubl2  v1.4s,v2.8h,v3.8h\r
+       usubl2  v1.8h,v2.16b,v3.16b\r
+\r
+       usubw   v1.2d,v2.2d,v3.2s\r
+       usubw   v1.4s,v2.4s,v3.4h\r
+       usubw   v1.8h,v2.8h,v3.8b\r
+\r
+       usubw2  v1.2d,v2.2d,v3.4s\r
+       usubw2  v1.4s,v2.4s,v3.8h\r
+       usubw2  v1.8h,v2.8h,v3.16b\r
+\r
+       uxtl    v1.2d,v2.2s\r
+       uxtl    v1.4s,v2.4h\r
+       uxtl    v1.8h,v2.8b\r
+\r
+       uxtl2   v1.2d,v2.4s\r
+       uxtl2   v1.4s,v2.8h\r
+       uxtl2   v1.8h,v2.16b\r
+\r
+       uzp1    v1.16b,v2.16b,v3.16b\r
+       uzp1    v1.2d,v2.2d,v3.2d\r
+       uzp1    v1.2s,v2.2s,v3.2s\r
+       uzp1    v1.4h,v2.4h,v3.4h\r
+       uzp1    v1.4s,v2.4s,v3.4s\r
+       uzp1    v1.8b,v2.8b,v3.8b\r
+       uzp1    v1.8h,v2.8h,v3.8h\r
+\r
+       uzp2    v1.16b,v2.16b,v3.16b\r
+       uzp2    v1.2d,v2.2d,v3.2d\r
+       uzp2    v1.2s,v2.2s,v3.2s\r
+       uzp2    v1.4h,v2.4h,v3.4h\r
+       uzp2    v1.4s,v2.4s,v3.4s\r
+       uzp2    v1.8b,v2.8b,v3.8b\r
+       uzp2    v1.8h,v2.8h,v3.8h\r
+\r
+       xtn     v1.8b,v2.8h\r
+       xtn     v1.4h,v2.4s\r
+       xtn     v1.2s,v2.2d\r
+\r
+       xtn2    v1.16b,v2.8h\r
+       xtn2    v1.8h,v2.4s\r
+       xtn2    v1.4s,v2.2d\r
+\r
+       zip1    v1.16b,v2.16b,v3.16b\r
+       zip1    v1.2d,v2.2d,v3.2d\r
+       zip1    v1.2s,v2.2s,v3.2s\r
+       zip1    v1.4h,v2.4h,v3.4h\r
+       zip1    v1.4s,v2.4s,v3.4s\r
+       zip1    v1.8b,v2.8b,v3.8b\r
+       zip1    v1.8h,v2.8h,v3.8h\r
+\r
+       zip2    v1.16b,v2.16b,v3.16b\r
+       zip2    v1.2d,v2.2d,v3.2d\r
+       zip2    v1.2s,v2.2s,v3.2s\r
+       zip2    v1.4h,v2.4h,v3.4h\r
+       zip2    v1.4s,v2.4s,v3.4s\r
+       zip2    v1.8b,v2.8b,v3.8b\r
+       zip2    v1.8h,v2.8h,v3.8h\r
+\r
+processor CPU64_CRC\r
+\r
+       crc32b  w1,w2,w3\r
+\r
+       crc32cb w1,w2,w3\r
+\r
+       crc32ch w1,w2,w3\r
+\r
+       crc32cw w1,w2,w3\r
+\r
+       crc32cx w1,w2,x3\r
+\r
+       crc32h  w1,w2,w3\r
+\r
+       crc32w  w1,w2,w3\r
+\r
+       crc32x  w1,w2,x3\r
+\r
+processor CPU64_CRYPTO\r
+\r
+       aesd    v1.16b,v2.16b\r
+\r
+       aese    v1.16b,v2.16b\r
+\r
+       aesimc  v1.16b,v2.16b\r
+\r
+       aesmc   v1.16b,v2.16b\r
+\r
+       pmull   v1.1q,v2.1d,v3.1d\r
+\r
+       pmull2  v1.1q,v2.2d,v3.2d\r
+\r
+       sha1c   q1,s2,v3.4s\r
+\r
+       sha1h   s1,s2\r
+\r
+       sha1m   q1,s2,v3.4s\r
+\r
+       sha1p   q1,s2,v3.4s\r
+\r
+       sha1su0 v1.4s,v2.4s,v3.4s\r
+\r
+       sha1su1 v1.4s,v2.4s\r
+\r
+       sha256h q1,q2,v3.4s\r
+\r
+       sha256h2        q1,q2,v3.4s\r
+\r
+       sha256su0       v1.4s,v2.4s\r
+\r
+       sha256su1       v1.4s,v2.4s,v3.4s\r
+\r

diff --git a/armdoc/InstructionFormatsFPA.asm b/armdoc/InstructionFormatsFPA.asm
new file mode 100644 (file)
index 0000000..e2df76c
--- /dev/null
+++ b/armdoc/InstructionFormatsFPA.asm
@@ -0,0 +1,1271 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;To avoid unnecessary repetition only ARM mode is used\r
+;here. There is no change needed for THUMB mode except\r
+;to specify that the processor supports version 7M\r
+;architecture instructions.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;All instructions can be conditional. The condition code\r
+;should be added at the end of the main opcode and\r
+;before any size/type specifiers. For example: "addhi"\r
+;and "vaddhi.i16". The syntax also supports the pre-UAL\r
+;style of putting the condition before any modifiers\r
+;like "s" or "fd". For example: "ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;FPA, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_FPA_V1\r
+       absd    f0,1.0\r
+       absd    f0,f1\r
+\r
+       absdm   f0,1.0\r
+       absdm   f0,f1\r
+\r
+       absdp   f0,1.0\r
+       absdp   f0,f1\r
+\r
+       absdz   f0,1.0\r
+       absdz   f0,f1\r
+\r
+       abse    f0,1.0\r
+       abse    f0,f1\r
+\r
+       absem   f0,1.0\r
+       absem   f0,f1\r
+\r
+       absep   f0,1.0\r
+       absep   f0,f1\r
+\r
+       absez   f0,1.0\r
+       absez   f0,f1\r
+\r
+       abss    f0,1.0\r
+       abss    f0,f1\r
+\r
+       abssm   f0,1.0\r
+       abssm   f0,f1\r
+\r
+       abssp   f0,1.0\r
+       abssp   f0,f1\r
+\r
+       abssz   f0,1.0\r
+       abssz   f0,f1\r
+\r
+       acsd    f0,1.0\r
+       acsd    f0,f1\r
+\r
+       acsdm   f0,1.0\r
+       acsdm   f0,f1\r
+\r
+       acsdp   f0,1.0\r
+       acsdp   f0,f1\r
+\r
+       acsdz   f0,1.0\r
+       acsdz   f0,f1\r
+\r
+       acse    f0,1.0\r
+       acse    f0,f1\r
+\r
+       acsem   f0,1.0\r
+       acsem   f0,f1\r
+\r
+       acsep   f0,1.0\r
+       acsep   f0,f1\r
+\r
+       acsez   f0,1.0\r
+       acsez   f0,f1\r
+\r
+       acss    f0,1.0\r
+       acss    f0,f1\r
+\r
+       acssm   f0,1.0\r
+       acssm   f0,f1\r
+\r
+       acssp   f0,1.0\r
+       acssp   f0,f1\r
+\r
+       acssz   f0,1.0\r
+       acssz   f0,f1\r
+\r
+       adfd    f0,f1,2.0\r
+       adfd    f0,f1,f2\r
+\r
+       adfdm   f0,f1,2.0\r
+       adfdm   f0,f1,f2\r
+\r
+       adfdp   f0,f1,2.0\r
+       adfdp   f0,f1,f2\r
+\r
+       adfdz   f0,f1,2.0\r
+       adfdz   f0,f1,f2\r
+\r
+       adfe    f0,f1,2.0\r
+       adfe    f0,f1,f2\r
+\r
+       adfem   f0,f1,2.0\r
+       adfem   f0,f1,f2\r
+\r
+       adfep   f0,f1,2.0\r
+       adfep   f0,f1,f2\r
+\r
+       adfez   f0,f1,2.0\r
+       adfez   f0,f1,f2\r
+\r
+       adfs    f0,f1,2.0\r
+       adfs    f0,f1,f2\r
+\r
+       adfsm   f0,f1,2.0\r
+       adfsm   f0,f1,f2\r
+\r
+       adfsp   f0,f1,2.0\r
+       adfsp   f0,f1,f2\r
+\r
+       adfsz   f0,f1,2.0\r
+       adfsz   f0,f1,f2\r
+\r
+       asnd    f0,1.0\r
+       asnd    f0,f1\r
+\r
+       asndm   f0,1.0\r
+       asndm   f0,f1\r
+\r
+       asndp   f0,1.0\r
+       asndp   f0,f1\r
+\r
+       asndz   f0,1.0\r
+       asndz   f0,f1\r
+\r
+       asne    f0,1.0\r
+       asne    f0,f1\r
+\r
+       asnem   f0,1.0\r
+       asnem   f0,f1\r
+\r
+       asnep   f0,1.0\r
+       asnep   f0,f1\r
+\r
+       asnez   f0,1.0\r
+       asnez   f0,f1\r
+\r
+       asns    f0,1.0\r
+       asns    f0,f1\r
+\r
+       asnsm   f0,1.0\r
+       asnsm   f0,f1\r
+\r
+       asnsp   f0,1.0\r
+       asnsp   f0,f1\r
+\r
+       asnsz   f0,1.0\r
+       asnsz   f0,f1\r
+\r
+       atnd    f0,1.0\r
+       atnd    f0,f1\r
+\r
+       atndm   f0,1.0\r
+       atndm   f0,f1\r
+\r
+       atndp   f0,1.0\r
+       atndp   f0,f1\r
+\r
+       atndz   f0,1.0\r
+       atndz   f0,f1\r
+\r
+       atne    f0,1.0\r
+       atne    f0,f1\r
+\r
+       atnem   f0,1.0\r
+       atnem   f0,f1\r
+\r
+       atnep   f0,1.0\r
+       atnep   f0,f1\r
+\r
+       atnez   f0,1.0\r
+       atnez   f0,f1\r
+\r
+       atns    f0,1.0\r
+       atns    f0,f1\r
+\r
+       atnsm   f0,1.0\r
+       atnsm   f0,f1\r
+\r
+       atnsp   f0,1.0\r
+       atnsp   f0,f1\r
+\r
+       atnsz   f0,1.0\r
+       atnsz   f0,f1\r
+\r
+       cmf     f0,1.0\r
+       cmf     f0,f1\r
+\r
+       cmfe    f0,1.0\r
+       cmfe    f0,f1\r
+\r
+       cnf     f0,1.0\r
+       cnf     f0,f1\r
+\r
+       cnfe    f0,1.0\r
+       cnfe    f0,f1\r
+\r
+       cosd    f0,1.0\r
+       cosd    f0,f1\r
+\r
+       cosdm   f0,1.0\r
+       cosdm   f0,f1\r
+\r
+       cosdp   f0,1.0\r
+       cosdp   f0,f1\r
+\r
+       cosdz   f0,1.0\r
+       cosdz   f0,f1\r
+\r
+       cose    f0,1.0\r
+       cose    f0,f1\r
+\r
+       cosem   f0,1.0\r
+       cosem   f0,f1\r
+\r
+       cosep   f0,1.0\r
+       cosep   f0,f1\r
+\r
+       cosez   f0,1.0\r
+       cosez   f0,f1\r
+\r
+       coss    f0,1.0\r
+       coss    f0,f1\r
+\r
+       cossm   f0,1.0\r
+       cossm   f0,f1\r
+\r
+       cossp   f0,1.0\r
+       cossp   f0,f1\r
+\r
+       cossz   f0,1.0\r
+       cossz   f0,f1\r
+\r
+       dvfd    f0,f1,2.0\r
+       dvfd    f0,f1,f2\r
+\r
+       dvfdm   f0,f1,2.0\r
+       dvfdm   f0,f1,f2\r
+\r
+       dvfdp   f0,f1,2.0\r
+       dvfdp   f0,f1,f2\r
+\r
+       dvfdz   f0,f1,2.0\r
+       dvfdz   f0,f1,f2\r
+\r
+       dvfe    f0,f1,2.0\r
+       dvfe    f0,f1,f2\r
+\r
+       dvfem   f0,f1,2.0\r
+       dvfem   f0,f1,f2\r
+\r
+       dvfep   f0,f1,2.0\r
+       dvfep   f0,f1,f2\r
+\r
+       dvfez   f0,f1,2.0\r
+       dvfez   f0,f1,f2\r
+\r
+       dvfs    f0,f1,2.0\r
+       dvfs    f0,f1,f2\r
+\r
+       dvfsm   f0,f1,2.0\r
+       dvfsm   f0,f1,f2\r
+\r
+       dvfsp   f0,f1,2.0\r
+       dvfsp   f0,f1,f2\r
+\r
+       dvfsz   f0,f1,2.0\r
+       dvfsz   f0,f1,f2\r
+\r
+       expd    f0,1.0\r
+       expd    f0,f1\r
+\r
+       expdm   f0,1.0\r
+       expdm   f0,f1\r
+\r
+       expdp   f0,1.0\r
+       expdp   f0,f1\r
+\r
+       expdz   f0,1.0\r
+       expdz   f0,f1\r
+\r
+       expe    f0,1.0\r
+       expe    f0,f1\r
+\r
+       expem   f0,1.0\r
+       expem   f0,f1\r
+\r
+       expep   f0,1.0\r
+       expep   f0,f1\r
+\r
+       expez   f0,1.0\r
+       expez   f0,f1\r
+\r
+       exps    f0,1.0\r
+       exps    f0,f1\r
+\r
+       expsm   f0,1.0\r
+       expsm   f0,f1\r
+\r
+       expsp   f0,1.0\r
+       expsp   f0,f1\r
+\r
+       expsz   f0,1.0\r
+       expsz   f0,f1\r
+\r
+       fdvd    f0,f1,2.0\r
+       fdvd    f0,f1,f2\r
+\r
+       fdvdm   f0,f1,2.0\r
+       fdvdm   f0,f1,f2\r
+\r
+       fdvdp   f0,f1,2.0\r
+       fdvdp   f0,f1,f2\r
+\r
+       fdvdz   f0,f1,2.0\r
+       fdvdz   f0,f1,f2\r
+\r
+       fdve    f0,f1,2.0\r
+       fdve    f0,f1,f2\r
+\r
+       fdvem   f0,f1,2.0\r
+       fdvem   f0,f1,f2\r
+\r
+       fdvep   f0,f1,2.0\r
+       fdvep   f0,f1,f2\r
+\r
+       fdvez   f0,f1,2.0\r
+       fdvez   f0,f1,f2\r
+\r
+       fdvs    f0,f1,2.0\r
+       fdvs    f0,f1,f2\r
+\r
+       fdvsm   f0,f1,2.0\r
+       fdvsm   f0,f1,f2\r
+\r
+       fdvsp   f0,f1,2.0\r
+       fdvsp   f0,f1,f2\r
+\r
+       fdvsz   f0,f1,2.0\r
+       fdvsz   f0,f1,f2\r
+\r
+       fix     r0,f1\r
+\r
+       fixm    r0,f1\r
+\r
+       fixp    r0,f1\r
+\r
+       fixz    r0,f1\r
+\r
+       fltd    f0,r1\r
+\r
+       fltdm   f0,r1\r
+\r
+       fltdp   f0,r1\r
+\r
+       fltdz   f0,r1\r
+\r
+       flte    f0,r1\r
+\r
+       fltem   f0,r1\r
+\r
+       fltep   f0,r1\r
+\r
+       fltez   f0,r1\r
+\r
+       flts    f0,r1\r
+\r
+       fltsm   f0,r1\r
+\r
+       fltsp   f0,r1\r
+\r
+       fltsz   f0,r1\r
+\r
+       fmld    f0,f1,2.0\r
+       fmld    f0,f1,f2\r
+\r
+       fmldm   f0,f1,2.0\r
+       fmldm   f0,f1,f2\r
+\r
+       fmldp   f0,f1,2.0\r
+       fmldp   f0,f1,f2\r
+\r
+       fmldz   f0,f1,2.0\r
+       fmldz   f0,f1,f2\r
+\r
+       fmle    f0,f1,2.0\r
+       fmle    f0,f1,f2\r
+\r
+       fmlem   f0,f1,2.0\r
+       fmlem   f0,f1,f2\r
+\r
+       fmlep   f0,f1,2.0\r
+       fmlep   f0,f1,f2\r
+\r
+       fmlez   f0,f1,2.0\r
+       fmlez   f0,f1,f2\r
+\r
+       fmls    f0,f1,2.0\r
+       fmls    f0,f1,f2\r
+\r
+       fmlsm   f0,f1,2.0\r
+       fmlsm   f0,f1,f2\r
+\r
+       fmlsp   f0,f1,2.0\r
+       fmlsp   f0,f1,f2\r
+\r
+       fmlsz   f0,f1,2.0\r
+       fmlsz   f0,f1,f2\r
+\r
+       frdd    f0,f1,2.0\r
+       frdd    f0,f1,f2\r
+\r
+       frddm   f0,f1,2.0\r
+       frddm   f0,f1,f2\r
+\r
+       frddp   f0,f1,2.0\r
+       frddp   f0,f1,f2\r
+\r
+       frddz   f0,f1,2.0\r
+       frddz   f0,f1,f2\r
+\r
+       frde    f0,f1,2.0\r
+       frde    f0,f1,f2\r
+\r
+       frdem   f0,f1,2.0\r
+       frdem   f0,f1,f2\r
+\r
+       frdep   f0,f1,2.0\r
+       frdep   f0,f1,f2\r
+\r
+       frdez   f0,f1,2.0\r
+       frdez   f0,f1,f2\r
+\r
+       frds    f0,f1,2.0\r
+       frds    f0,f1,f2\r
+\r
+       frdsm   f0,f1,2.0\r
+       frdsm   f0,f1,f2\r
+\r
+       frdsp   f0,f1,2.0\r
+       frdsp   f0,f1,f2\r
+\r
+       frdsz   f0,f1,2.0\r
+       frdsz   f0,f1,f2\r
+\r
+       label_ldfd:\r
+       ldfd    f0,[r1]\r
+       ldfd    f0,[r1],4\r
+       ldfd    f0,[r1],{2}\r
+       ldfd    f0,[r1,4]\r
+       ldfd    f0,[r1,4]!\r
+       ldfd    f0,[label_ldfd]\r
+       ldfd    f0,[expression.word]\r
+       ldfd    f0,[expression.word]!\r
+\r
+       label_ldfe:\r
+       ldfe    f0,[r1]\r
+       ldfe    f0,[r1],4\r
+       ldfe    f0,[r1],{2}\r
+       ldfe    f0,[r1,4]\r
+       ldfe    f0,[r1,4]!\r
+       ldfe    f0,[label_ldfe]\r
+       ldfe    f0,[expression.word]\r
+       ldfe    f0,[expression.word]!\r
+\r
+       label_ldfp:\r
+       ldfp    f0,[r1]\r
+       ldfp    f0,[r1],4\r
+       ldfp    f0,[r1],{2}\r
+       ldfp    f0,[r1,4]\r
+       ldfp    f0,[r1,4]!\r
+       ldfp    f0,[label_ldfp]\r
+       ldfp    f0,[expression.word]\r
+       ldfp    f0,[expression.word]!\r
+\r
+       label_ldfs:\r
+       ldfs    f0,[r1]\r
+       ldfs    f0,[r1],4\r
+       ldfs    f0,[r1],{2}\r
+       ldfs    f0,[r1,4]\r
+       ldfs    f0,[r1,4]!\r
+       ldfs    f0,[label_ldfs]\r
+       ldfs    f0,[expression.word]\r
+       ldfs    f0,[expression.word]!\r
+\r
+       lgnd    f0,1.0\r
+       lgnd    f0,f1\r
+\r
+       lgndm   f0,1.0\r
+       lgndm   f0,f1\r
+\r
+       lgndp   f0,1.0\r
+       lgndp   f0,f1\r
+\r
+       lgndz   f0,1.0\r
+       lgndz   f0,f1\r
+\r
+       lgne    f0,1.0\r
+       lgne    f0,f1\r
+\r
+       lgnem   f0,1.0\r
+       lgnem   f0,f1\r
+\r
+       lgnep   f0,1.0\r
+       lgnep   f0,f1\r
+\r
+       lgnez   f0,1.0\r
+       lgnez   f0,f1\r
+\r
+       lgns    f0,1.0\r
+       lgns    f0,f1\r
+\r
+       lgnsm   f0,1.0\r
+       lgnsm   f0,f1\r
+\r
+       lgnsp   f0,1.0\r
+       lgnsp   f0,f1\r
+\r
+       lgnsz   f0,1.0\r
+       lgnsz   f0,f1\r
+\r
+       logd    f0,1.0\r
+       logd    f0,f1\r
+\r
+       logdm   f0,1.0\r
+       logdm   f0,f1\r
+\r
+       logdp   f0,1.0\r
+       logdp   f0,f1\r
+\r
+       logdz   f0,1.0\r
+       logdz   f0,f1\r
+\r
+       loge    f0,1.0\r
+       loge    f0,f1\r
+\r
+       logem   f0,1.0\r
+       logem   f0,f1\r
+\r
+       logep   f0,1.0\r
+       logep   f0,f1\r
+\r
+       logez   f0,1.0\r
+       logez   f0,f1\r
+\r
+       logs    f0,1.0\r
+       logs    f0,f1\r
+\r
+       logsm   f0,1.0\r
+       logsm   f0,f1\r
+\r
+       logsp   f0,1.0\r
+       logsp   f0,f1\r
+\r
+       logsz   f0,1.0\r
+       logsz   f0,f1\r
+\r
+       mnfd    f0,1.0\r
+       mnfd    f0,f1\r
+\r
+       mnfdm   f0,1.0\r
+       mnfdm   f0,f1\r
+\r
+       mnfdp   f0,1.0\r
+       mnfdp   f0,f1\r
+\r
+       mnfdz   f0,1.0\r
+       mnfdz   f0,f1\r
+\r
+       mnfe    f0,1.0\r
+       mnfe    f0,f1\r
+\r
+       mnfem   f0,1.0\r
+       mnfem   f0,f1\r
+\r
+       mnfep   f0,1.0\r
+       mnfep   f0,f1\r
+\r
+       mnfez   f0,1.0\r
+       mnfez   f0,f1\r
+\r
+       mnfs    f0,1.0\r
+       mnfs    f0,f1\r
+\r
+       mnfsm   f0,1.0\r
+       mnfsm   f0,f1\r
+\r
+       mnfsp   f0,1.0\r
+       mnfsp   f0,f1\r
+\r
+       mnfsz   f0,1.0\r
+       mnfsz   f0,f1\r
+\r
+       mufd    f0,f1,2.0\r
+       mufd    f0,f1,f2\r
+\r
+       mufdm   f0,f1,2.0\r
+       mufdm   f0,f1,f2\r
+\r
+       mufdp   f0,f1,2.0\r
+       mufdp   f0,f1,f2\r
+\r
+       mufdz   f0,f1,2.0\r
+       mufdz   f0,f1,f2\r
+\r
+       mufe    f0,f1,2.0\r
+       mufe    f0,f1,f2\r
+\r
+       mufem   f0,f1,2.0\r
+       mufem   f0,f1,f2\r
+\r
+       mufep   f0,f1,2.0\r
+       mufep   f0,f1,f2\r
+\r
+       mufez   f0,f1,2.0\r
+       mufez   f0,f1,f2\r
+\r
+       mufs    f0,f1,2.0\r
+       mufs    f0,f1,f2\r
+\r
+       mufsm   f0,f1,2.0\r
+       mufsm   f0,f1,f2\r
+\r
+       mufsp   f0,f1,2.0\r
+       mufsp   f0,f1,f2\r
+\r
+       mufsz   f0,f1,2.0\r
+       mufsz   f0,f1,f2\r
+\r
+       mvfd    f0,1.0\r
+       mvfd    f0,f1\r
+\r
+       mvfdm   f0,1.0\r
+       mvfdm   f0,f1\r
+\r
+       mvfdp   f0,1.0\r
+       mvfdp   f0,f1\r
+\r
+       mvfdz   f0,1.0\r
+       mvfdz   f0,f1\r
+\r
+       mvfe    f0,1.0\r
+       mvfe    f0,f1\r
+\r
+       mvfem   f0,1.0\r
+       mvfem   f0,f1\r
+\r
+       mvfep   f0,1.0\r
+       mvfep   f0,f1\r
+\r
+       mvfez   f0,1.0\r
+       mvfez   f0,f1\r
+\r
+       mvfs    f0,1.0\r
+       mvfs    f0,f1\r
+\r
+       mvfsm   f0,1.0\r
+       mvfsm   f0,f1\r
+\r
+       mvfsp   f0,1.0\r
+       mvfsp   f0,f1\r
+\r
+       mvfsz   f0,1.0\r
+       mvfsz   f0,f1\r
+\r
+       nrmd    f0,1.0\r
+       nrmd    f0,f1\r
+\r
+       nrmdm   f0,1.0\r
+       nrmdm   f0,f1\r
+\r
+       nrmdp   f0,1.0\r
+       nrmdp   f0,f1\r
+\r
+       nrmdz   f0,1.0\r
+       nrmdz   f0,f1\r
+\r
+       nrme    f0,1.0\r
+       nrme    f0,f1\r
+\r
+       nrmem   f0,1.0\r
+       nrmem   f0,f1\r
+\r
+       nrmep   f0,1.0\r
+       nrmep   f0,f1\r
+\r
+       nrmez   f0,1.0\r
+       nrmez   f0,f1\r
+\r
+       nrms    f0,1.0\r
+       nrms    f0,f1\r
+\r
+       nrmsm   f0,1.0\r
+       nrmsm   f0,f1\r
+\r
+       nrmsp   f0,1.0\r
+       nrmsp   f0,f1\r
+\r
+       nrmsz   f0,1.0\r
+       nrmsz   f0,f1\r
+\r
+       pold    f0,f1,2.0\r
+       pold    f0,f1,f2\r
+\r
+       poldm   f0,f1,2.0\r
+       poldm   f0,f1,f2\r
+\r
+       poldp   f0,f1,2.0\r
+       poldp   f0,f1,f2\r
+\r
+       poldz   f0,f1,2.0\r
+       poldz   f0,f1,f2\r
+\r
+       pole    f0,f1,2.0\r
+       pole    f0,f1,f2\r
+\r
+       polem   f0,f1,2.0\r
+       polem   f0,f1,f2\r
+\r
+       polep   f0,f1,2.0\r
+       polep   f0,f1,f2\r
+\r
+       polez   f0,f1,2.0\r
+       polez   f0,f1,f2\r
+\r
+       pols    f0,f1,2.0\r
+       pols    f0,f1,f2\r
+\r
+       polsm   f0,f1,2.0\r
+       polsm   f0,f1,f2\r
+\r
+       polsp   f0,f1,2.0\r
+       polsp   f0,f1,f2\r
+\r
+       polsz   f0,f1,2.0\r
+       polsz   f0,f1,f2\r
+\r
+       powd    f0,f1,2.0\r
+       powd    f0,f1,f2\r
+\r
+       powdm   f0,f1,2.0\r
+       powdm   f0,f1,f2\r
+\r
+       powdp   f0,f1,2.0\r
+       powdp   f0,f1,f2\r
+\r
+       powdz   f0,f1,2.0\r
+       powdz   f0,f1,f2\r
+\r
+       powe    f0,f1,2.0\r
+       powe    f0,f1,f2\r
+\r
+       powem   f0,f1,2.0\r
+       powem   f0,f1,f2\r
+\r
+       powep   f0,f1,2.0\r
+       powep   f0,f1,f2\r
+\r
+       powez   f0,f1,2.0\r
+       powez   f0,f1,f2\r
+\r
+       pows    f0,f1,2.0\r
+       pows    f0,f1,f2\r
+\r
+       powsm   f0,f1,2.0\r
+       powsm   f0,f1,f2\r
+\r
+       powsp   f0,f1,2.0\r
+       powsp   f0,f1,f2\r
+\r
+       powsz   f0,f1,2.0\r
+       powsz   f0,f1,f2\r
+\r
+       rdfd    f0,f1,2.0\r
+       rdfd    f0,f1,f2\r
+\r
+       rdfdm   f0,f1,2.0\r
+       rdfdm   f0,f1,f2\r
+\r
+       rdfdp   f0,f1,2.0\r
+       rdfdp   f0,f1,f2\r
+\r
+       rdfdz   f0,f1,2.0\r
+       rdfdz   f0,f1,f2\r
+\r
+       rdfe    f0,f1,2.0\r
+       rdfe    f0,f1,f2\r
+\r
+       rdfem   f0,f1,2.0\r
+       rdfem   f0,f1,f2\r
+\r
+       rdfep   f0,f1,2.0\r
+       rdfep   f0,f1,f2\r
+\r
+       rdfez   f0,f1,2.0\r
+       rdfez   f0,f1,f2\r
+\r
+       rdfs    f0,f1,2.0\r
+       rdfs    f0,f1,f2\r
+\r
+       rdfsm   f0,f1,2.0\r
+       rdfsm   f0,f1,f2\r
+\r
+       rdfsp   f0,f1,2.0\r
+       rdfsp   f0,f1,f2\r
+\r
+       rdfsz   f0,f1,2.0\r
+       rdfsz   f0,f1,f2\r
+\r
+       rfc     r0\r
+\r
+       rfs     r0\r
+\r
+       rmfd    f0,f1,2.0\r
+       rmfd    f0,f1,f2\r
+\r
+       rmfdm   f0,f1,2.0\r
+       rmfdm   f0,f1,f2\r
+\r
+       rmfdp   f0,f1,2.0\r
+       rmfdp   f0,f1,f2\r
+\r
+       rmfdz   f0,f1,2.0\r
+       rmfdz   f0,f1,f2\r
+\r
+       rmfe    f0,f1,2.0\r
+       rmfe    f0,f1,f2\r
+\r
+       rmfem   f0,f1,2.0\r
+       rmfem   f0,f1,f2\r
+\r
+       rmfep   f0,f1,2.0\r
+       rmfep   f0,f1,f2\r
+\r
+       rmfez   f0,f1,2.0\r
+       rmfez   f0,f1,f2\r
+\r
+       rmfs    f0,f1,2.0\r
+       rmfs    f0,f1,f2\r
+\r
+       rmfsm   f0,f1,2.0\r
+       rmfsm   f0,f1,f2\r
+\r
+       rmfsp   f0,f1,2.0\r
+       rmfsp   f0,f1,f2\r
+\r
+       rmfsz   f0,f1,2.0\r
+       rmfsz   f0,f1,f2\r
+\r
+       rndd    f0,1.0\r
+       rndd    f0,f1\r
+\r
+       rnddm   f0,1.0\r
+       rnddm   f0,f1\r
+\r
+       rnddp   f0,1.0\r
+       rnddp   f0,f1\r
+\r
+       rnddz   f0,1.0\r
+       rnddz   f0,f1\r
+\r
+       rnde    f0,1.0\r
+       rnde    f0,f1\r
+\r
+       rndem   f0,1.0\r
+       rndem   f0,f1\r
+\r
+       rndep   f0,1.0\r
+       rndep   f0,f1\r
+\r
+       rndez   f0,1.0\r
+       rndez   f0,f1\r
+\r
+       rnds    f0,1.0\r
+       rnds    f0,f1\r
+\r
+       rndsm   f0,1.0\r
+       rndsm   f0,f1\r
+\r
+       rndsp   f0,1.0\r
+       rndsp   f0,f1\r
+\r
+       rndsz   f0,1.0\r
+       rndsz   f0,f1\r
+\r
+       rpwd    f0,f1,2.0\r
+       rpwd    f0,f1,f2\r
+\r
+       rpwdm   f0,f1,2.0\r
+       rpwdm   f0,f1,f2\r
+\r
+       rpwdp   f0,f1,2.0\r
+       rpwdp   f0,f1,f2\r
+\r
+       rpwdz   f0,f1,2.0\r
+       rpwdz   f0,f1,f2\r
+\r
+       rpwe    f0,f1,2.0\r
+       rpwe    f0,f1,f2\r
+\r
+       rpwem   f0,f1,2.0\r
+       rpwem   f0,f1,f2\r
+\r
+       rpwep   f0,f1,2.0\r
+       rpwep   f0,f1,f2\r
+\r
+       rpwez   f0,f1,2.0\r
+       rpwez   f0,f1,f2\r
+\r
+       rpws    f0,f1,2.0\r
+       rpws    f0,f1,f2\r
+\r
+       rpwsm   f0,f1,2.0\r
+       rpwsm   f0,f1,f2\r
+\r
+       rpwsp   f0,f1,2.0\r
+       rpwsp   f0,f1,f2\r
+\r
+       rpwsz   f0,f1,2.0\r
+       rpwsz   f0,f1,f2\r
+\r
+       rsfd    f0,f1,2.0\r
+       rsfd    f0,f1,f2\r
+\r
+       rsfdm   f0,f1,2.0\r
+       rsfdm   f0,f1,f2\r
+\r
+       rsfdp   f0,f1,2.0\r
+       rsfdp   f0,f1,f2\r
+\r
+       rsfdz   f0,f1,2.0\r
+       rsfdz   f0,f1,f2\r
+\r
+       rsfe    f0,f1,2.0\r
+       rsfe    f0,f1,f2\r
+\r
+       rsfem   f0,f1,2.0\r
+       rsfem   f0,f1,f2\r
+\r
+       rsfep   f0,f1,2.0\r
+       rsfep   f0,f1,f2\r
+\r
+       rsfez   f0,f1,2.0\r
+       rsfez   f0,f1,f2\r
+\r
+       rsfs    f0,f1,2.0\r
+       rsfs    f0,f1,f2\r
+\r
+       rsfsm   f0,f1,2.0\r
+       rsfsm   f0,f1,f2\r
+\r
+       rsfsp   f0,f1,2.0\r
+       rsfsp   f0,f1,f2\r
+\r
+       rsfsz   f0,f1,2.0\r
+       rsfsz   f0,f1,f2\r
+\r
+       sind    f0,1.0\r
+       sind    f0,f1\r
+\r
+       sindm   f0,1.0\r
+       sindm   f0,f1\r
+\r
+       sindp   f0,1.0\r
+       sindp   f0,f1\r
+\r
+       sindz   f0,1.0\r
+       sindz   f0,f1\r
+\r
+       sine    f0,1.0\r
+       sine    f0,f1\r
+\r
+       sinem   f0,1.0\r
+       sinem   f0,f1\r
+\r
+       sinep   f0,1.0\r
+       sinep   f0,f1\r
+\r
+       sinez   f0,1.0\r
+       sinez   f0,f1\r
+\r
+       sins    f0,1.0\r
+       sins    f0,f1\r
+\r
+       sinsm   f0,1.0\r
+       sinsm   f0,f1\r
+\r
+       sinsp   f0,1.0\r
+       sinsp   f0,f1\r
+\r
+       sinsz   f0,1.0\r
+       sinsz   f0,f1\r
+\r
+       sqtd    f0,1.0\r
+       sqtd    f0,f1\r
+\r
+       sqtdm   f0,1.0\r
+       sqtdm   f0,f1\r
+\r
+       sqtdp   f0,1.0\r
+       sqtdp   f0,f1\r
+\r
+       sqtdz   f0,1.0\r
+       sqtdz   f0,f1\r
+\r
+       sqte    f0,1.0\r
+       sqte    f0,f1\r
+\r
+       sqtem   f0,1.0\r
+       sqtem   f0,f1\r
+\r
+       sqtep   f0,1.0\r
+       sqtep   f0,f1\r
+\r
+       sqtez   f0,1.0\r
+       sqtez   f0,f1\r
+\r
+       sqts    f0,1.0\r
+       sqts    f0,f1\r
+\r
+       sqtsm   f0,1.0\r
+       sqtsm   f0,f1\r
+\r
+       sqtsp   f0,1.0\r
+       sqtsp   f0,f1\r
+\r
+       sqtsz   f0,1.0\r
+       sqtsz   f0,f1\r
+\r
+       label_stfd:\r
+       stfd    f0,[r1]\r
+       stfd    f0,[r1],4\r
+       stfd    f0,[r1],{2}\r
+       stfd    f0,[r1,4]\r
+       stfd    f0,[r1,4]!\r
+       stfd    f0,[label_stfd]\r
+       stfd    f0,[expression.word]\r
+       stfd    f0,[expression.word]!\r
+\r
+       label_stfe:\r
+       stfe    f0,[r1]\r
+       stfe    f0,[r1],4\r
+       stfe    f0,[r1],{2}\r
+       stfe    f0,[r1,4]\r
+       stfe    f0,[r1,4]!\r
+       stfe    f0,[label_stfe]\r
+       stfe    f0,[expression.word]\r
+       stfe    f0,[expression.word]!\r
+\r
+       label_stfp:\r
+       stfp    f0,[r1]\r
+       stfp    f0,[r1],4\r
+       stfp    f0,[r1],{2}\r
+       stfp    f0,[r1,4]\r
+       stfp    f0,[r1,4]!\r
+       stfp    f0,[label_stfp]\r
+       stfp    f0,[expression.word]\r
+       stfp    f0,[expression.word]!\r
+\r
+       label_stfs:\r
+       stfs    f0,[r1]\r
+       stfs    f0,[r1],4\r
+       stfs    f0,[r1],{2}\r
+       stfs    f0,[r1,4]\r
+       stfs    f0,[r1,4]!\r
+       stfs    f0,[label_stfs]\r
+       stfs    f0,[expression.word]\r
+       stfs    f0,[expression.word]!\r
+\r
+       sufd    f0,f1,2.0\r
+       sufd    f0,f1,f2\r
+\r
+       sufdm   f0,f1,2.0\r
+       sufdm   f0,f1,f2\r
+\r
+       sufdp   f0,f1,2.0\r
+       sufdp   f0,f1,f2\r
+\r
+       sufdz   f0,f1,2.0\r
+       sufdz   f0,f1,f2\r
+\r
+       sufe    f0,f1,2.0\r
+       sufe    f0,f1,f2\r
+\r
+       sufem   f0,f1,2.0\r
+       sufem   f0,f1,f2\r
+\r
+       sufep   f0,f1,2.0\r
+       sufep   f0,f1,f2\r
+\r
+       sufez   f0,f1,2.0\r
+       sufez   f0,f1,f2\r
+\r
+       sufs    f0,f1,2.0\r
+       sufs    f0,f1,f2\r
+\r
+       sufsm   f0,f1,2.0\r
+       sufsm   f0,f1,f2\r
+\r
+       sufsp   f0,f1,2.0\r
+       sufsp   f0,f1,f2\r
+\r
+       sufsz   f0,f1,2.0\r
+       sufsz   f0,f1,f2\r
+\r
+       tand    f0,1.0\r
+       tand    f0,f1\r
+\r
+       tandm   f0,1.0\r
+       tandm   f0,f1\r
+\r
+       tandp   f0,1.0\r
+       tandp   f0,f1\r
+\r
+       tandz   f0,1.0\r
+       tandz   f0,f1\r
+\r
+       tane    f0,1.0\r
+       tane    f0,f1\r
+\r
+       tanem   f0,1.0\r
+       tanem   f0,f1\r
+\r
+       tanep   f0,1.0\r
+       tanep   f0,f1\r
+\r
+       tanez   f0,1.0\r
+       tanez   f0,f1\r
+\r
+       tans    f0,1.0\r
+       tans    f0,f1\r
+\r
+       tansm   f0,1.0\r
+       tansm   f0,f1\r
+\r
+       tansp   f0,1.0\r
+       tansp   f0,f1\r
+\r
+       tansz   f0,1.0\r
+       tansz   f0,f1\r
+\r
+       urdd    f0,1.0\r
+       urdd    f0,f1\r
+\r
+       urddm   f0,1.0\r
+       urddm   f0,f1\r
+\r
+       urddp   f0,1.0\r
+       urddp   f0,f1\r
+\r
+       urddz   f0,1.0\r
+       urddz   f0,f1\r
+\r
+       urde    f0,1.0\r
+       urde    f0,f1\r
+\r
+       urdem   f0,1.0\r
+       urdem   f0,f1\r
+\r
+       urdep   f0,1.0\r
+       urdep   f0,f1\r
+\r
+       urdez   f0,1.0\r
+       urdez   f0,f1\r
+\r
+       urds    f0,1.0\r
+       urds    f0,f1\r
+\r
+       urdsm   f0,1.0\r
+       urdsm   f0,f1\r
+\r
+       urdsp   f0,1.0\r
+       urdsp   f0,f1\r
+\r
+       urdsz   f0,1.0\r
+       urdsz   f0,f1\r
+\r
+       wfc     r0\r
+\r
+       wfs     r0\r
+\r
+coprocessor COPRO_FPA_V2\r
+\r
+       label_lfm:\r
+       lfm     f0,1,[r2]\r
+       lfm     f0,1,[r2],4\r
+       lfm     f0,1,[r2],{4}\r
+       lfm     f0,1,[r2,4]\r
+       lfm     f0,1,[r2,4]!\r
+       lfm     f0,1,[label_lfm]\r
+       lfm     f0,1,[expression.word]\r
+       lfm     f0,1,[expression.word]!\r
+\r
+       lfmea   f0,1,[r2]\r
+       lfmea   f0,1,[r2]!\r
+\r
+       lfmfd   f0,1,[r2]\r
+       lfmfd   f0,1,[r2]!\r
+\r
+       label_sfm:\r
+       sfm     f0,1,[r2]\r
+       sfm     f0,1,[r2],4\r
+       sfm     f0,1,[r2],{4}\r
+       sfm     f0,1,[r2,4]\r
+       sfm     f0,1,[r2,4]!\r
+       sfm     f0,1,[label_sfm]\r
+       sfm     f0,1,[expression.word]\r
+       sfm     f0,1,[expression.word]!\r
+\r
+       sfmea   f0,1,[r2]\r
+       sfmea   f0,1,[r2]!\r
+\r
+       sfmfd   f0,1,[r2]\r
+       sfmfd   f0,1,[r2]!\r

diff --git a/armdoc/InstructionFormatsIWMMXT.asm b/armdoc/InstructionFormatsIWMMXT.asm
new file mode 100644 (file)
index 0000000..b407b82
--- /dev/null
+++ b/armdoc/InstructionFormatsIWMMXT.asm
@@ -0,0 +1,630 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;To avoid unnecessary repetition only ARM mode is used\r
+;here. There is no change needed for THUMB mode except\r
+;to specify that the processor supports version 7M\r
+;architecture instructions.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;Almost all instructions can be conditional. The\r
+;condition code should be added at the end of the main\r
+;opcode and before any size/type specifiers. For\r
+;example: "addhi" and "vaddhi.i16". The syntax also\r
+;supports the pre-UAL style of putting the condition\r
+;before any modifiers like "s" or "fd". For example:\r
+;"ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;IWMMXT, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_IWMMXT_V1\r
+\r
+       tandcb  r15\r
+\r
+       tandch  r15\r
+\r
+       tandcw  r15\r
+\r
+       tbcstb  wr0,r1\r
+\r
+       tbcsth  wr0,r1\r
+\r
+       tbcstw  wr0,r1\r
+\r
+       textrcb r15,4\r
+\r
+       textrch r15,2\r
+\r
+       textrcw r15,1\r
+\r
+       textrmsb        r0,wr1,2\r
+\r
+       textrmsh        r0,wr1,2\r
+\r
+       textrmsw        r0,wr1,2\r
+\r
+       textrmub        r0,wr1,2\r
+\r
+       textrmuh        r0,wr1,2\r
+\r
+       textrmuw        r0,wr1,2\r
+\r
+       tinsrb  wr0,r1,2\r
+\r
+       tinsrh  wr0,r1,2\r
+\r
+       tinsrw  wr0,r1,2\r
+\r
+       tmcr    wcgr0,r1\r
+\r
+       tmcrr   wr0,r1,r2\r
+\r
+       tmia    wr0,r1,r2\r
+\r
+       tmiabb  wr0,r1,r2\r
+\r
+       tmiabt  wr0,r1,r2\r
+\r
+       tmiaph  wr0,r1,r2\r
+\r
+       tmiatb  wr0,r1,r2\r
+\r
+       tmiatt  wr0,r1,r2\r
+\r
+       tmovmskb        r0,wr1\r
+\r
+       tmovmskh        r0,wr1\r
+\r
+       tmovmskw        r0,wr1\r
+\r
+       tmrc    r0,wcgr1\r
+\r
+       tmrrc   r0,r1,wr2\r
+\r
+       torcb   r15\r
+\r
+       torch   r15\r
+\r
+       torcw   r15\r
+\r
+       waccb   wr0,wr1\r
+\r
+       wacch   wr0,wr1\r
+\r
+       waccw   wr0,wr1\r
+\r
+       waddb   wr0,wr1,wr2\r
+\r
+       waddbss wr0,wr1,wr2\r
+\r
+       waddbus wr0,wr1,wr2\r
+\r
+       waddh   wr0,wr1,wr2\r
+\r
+       waddhss wr0,wr1,wr2\r
+\r
+       waddhus wr0,wr1,wr2\r
+\r
+       waddw   wr0,wr1,wr2\r
+\r
+       waddwss wr0,wr1,wr2\r
+\r
+       waddwus wr0,wr1,wr2\r
+\r
+       waligni wr0,wr1,wr2,3\r
+\r
+       walignr0        wr1,wr1,wr2\r
+\r
+       walignr1        wr1,wr1,wr2\r
+\r
+       walignr2        wr1,wr1,wr2\r
+\r
+       walignr3        wr1,wr1,wr2\r
+\r
+       wand    wr0,wr1,wr2\r
+\r
+       wandn   wr0,wr1,wr2\r
+\r
+       wavg2b  wr0,wr1,wr2\r
+\r
+       wavg2br wr0,wr1,wr2\r
+\r
+       wavg2h  wr0,wr1,wr2\r
+\r
+       wavg2hr wr0,wr1,wr2\r
+\r
+       wcmpeqb wr0,wr1,wr2\r
+\r
+       wcmpeqh wr0,wr1,wr2\r
+\r
+       wcmpeqw wr0,wr1,wr2\r
+\r
+       wcmpgtsb        wr1,wr1,wr2\r
+\r
+       wcmpgtsh        wr1,wr1,wr2\r
+\r
+       wcmpgtsw        wr1,wr1,wr2\r
+\r
+       wcmpgtub        wr1,wr1,wr2\r
+\r
+       wcmpgtuh        wr1,wr1,wr2\r
+\r
+       wcmpgtuw        wr1,wr1,wr2\r
+\r
+       label_wldrb:\r
+       wldrb   wr0,[r1]\r
+       wldrb   wr0,[r1],4\r
+       wldrb   wr0,[r1],{4}\r
+       wldrb   wr0,[r1,4]\r
+       wldrb   wr0,[r1,4]!\r
+       wldrb   wr0,[label_wldrb]\r
+       wldrb   wr0,[expression.byte]\r
+       wldrb   wr0,[expression.byte]!\r
+\r
+       label_wldrd:\r
+       wldrd   wr0,[r1]\r
+       wldrd   wr0,[r1],4\r
+       wldrd   wr0,[r1],{4}\r
+       wldrd   wr0,[r1,4]\r
+       wldrd   wr0,[r1,4]!\r
+       wldrd   wr0,[label_wldrd]\r
+       wldrd   wr0,[expression.dword]\r
+       wldrd   wr0,[expression.dword]!\r
+\r
+       label_wldrh:\r
+       wldrh   wr0,[r1]\r
+       wldrh   wr0,[r1],4\r
+       wldrh   wr0,[r1],{4}\r
+       wldrh   wr0,[r1,4]\r
+       wldrh   wr0,[r1,4]!\r
+       wldrh   wr0,[label_wldrh]\r
+       wldrh   wr0,[expression.hword]\r
+       wldrh   wr0,[expression.hword]!\r
+\r
+       label_wldrw:\r
+       wldrw   wr0,[r1]\r
+       wldrw   wr0,[r1],4\r
+       wldrw   wr0,[r1],{4}\r
+       wldrw   wr0,[r1,4]\r
+       wldrw   wr0,[r1,4]!\r
+       wldrw   wr0,[label_wldrw]\r
+       wldrw   wr0,[expression.word]\r
+       wldrw   wr0,[expression.word]!\r
+       wldrw   wcgr0,[r1]\r
+       wldrw   wcgr0,[r1],4\r
+       wldrw   wcgr0,[r1],{4}\r
+       wldrw   wcgr0,[r1,4]\r
+       wldrw   wcgr0,[r1,4]!\r
+       wldrw   wcgr0,[label_wldrw]\r
+       wldrw   wcgr0,[expression.word]\r
+       wldrw   wcgr0,[expression.word]!\r
+\r
+       wmacs   wr0,wr1,wr2\r
+\r
+       wmacsz  wr0,wr1,wr2\r
+\r
+       wmacu   wr0,wr1,wr2\r
+\r
+       wmacuz  wr0,wr1,wr2\r
+\r
+       wmadds  wr0,wr1,wr2\r
+\r
+       wmaddu  wr0,wr1,wr2\r
+\r
+       wmaxsb  wr0,wr1,wr2\r
+\r
+       wmaxsh  wr0,wr1,wr2\r
+\r
+       wmaxsw  wr0,wr1,wr2\r
+\r
+       wmaxub  wr0,wr1,wr2\r
+\r
+       wmaxuh  wr0,wr1,wr2\r
+\r
+       wmaxuw  wr0,wr1,wr2\r
+\r
+       wminsb  wr0,wr1,wr2\r
+\r
+       wminsh  wr0,wr1,wr2\r
+\r
+       wminsw  wr0,wr1,wr2\r
+\r
+       wminub  wr0,wr1,wr2\r
+\r
+       wminuh  wr0,wr1,wr2\r
+\r
+       wminuw  wr0,wr1,wr2\r
+\r
+       wmov    wr0,wr1\r
+\r
+       wmulsl  wr0,wr1,wr2\r
+\r
+       wmulsm  wr0,wr1,wr2\r
+\r
+       wmulul  wr0,wr1,wr2\r
+\r
+       wmulum  wr0,wr1,wr2\r
+\r
+       wor     wr0,wr1,wr2\r
+\r
+       wpackdss        wr1,wr1,wr2\r
+\r
+       wpackdus        wr1,wr1,wr2\r
+\r
+       wpackhss        wr1,wr1,wr2\r
+\r
+       wpackhus        wr1,wr1,wr2\r
+\r
+       wpackwss        wr1,wr1,wr2\r
+\r
+       wpackwus        wr1,wr1,wr2\r
+\r
+       wrord   wr0,wr1,wr2\r
+\r
+       wrordg  wr0,wr1,wcgr2\r
+\r
+       wrorh   wr0,wr1,wr2\r
+\r
+       wrorhg  wr0,wr1,wcgr2\r
+\r
+       wrorw   wr0,wr1,wr2\r
+\r
+       wrorwg  wr0,wr1,wcgr2\r
+\r
+       wsadb   wr0,wr1,wr2\r
+\r
+       wsadbz  wr0,wr1,wr2\r
+\r
+       wsadh   wr0,wr1,wr2\r
+\r
+       wsadhz  wr0,wr1,wr2\r
+\r
+       wshufh  wr0,wr1,2\r
+\r
+       wshufh  wr0,wr1,2\r
+\r
+       wslld   wr0,wr1,wr2\r
+\r
+       wslldg  wr0,wr1,wcgr2\r
+\r
+       wsllh   wr0,wr1,wr2\r
+\r
+       wsllhg  wr0,wr1,wcgr2\r
+\r
+       wsllw   wr0,wr1,wr2\r
+\r
+       wsllwg  wr0,wr1,wcgr2\r
+\r
+       wsrad   wr0,wr1,wr2\r
+\r
+       wsradg  wr0,wr1,wcgr2\r
+\r
+       wsrah   wr0,wr1,wr2\r
+\r
+       wsrahg  wr0,wr1,wcgr2\r
+\r
+       wsraw   wr0,wr1,wr2\r
+\r
+       wsrawg  wr0,wr1,wcgr2\r
+\r
+       wsrld   wr0,wr1,wr2\r
+\r
+       wsrldg  wr0,wr1,wcgr2\r
+\r
+       wsrlh   wr0,wr1,wr2\r
+\r
+       wsrlhg  wr0,wr1,wcgr2\r
+\r
+       wsrlw   wr0,wr1,wr2\r
+\r
+       wsrlwg  wr0,wr1,wcgr2\r
+\r
+       label_wstrb:\r
+       wstrb   wr0,[r1]\r
+       wstrb   wr0,[r1],4\r
+       wstrb   wr0,[r1],{4}\r
+       wstrb   wr0,[r1,4]\r
+       wstrb   wr0,[r1,4]!\r
+       wstrb   wr0,[label_wstrb]\r
+       wstrb   wr0,[expression.byte]\r
+       wstrb   wr0,[expression.byte]!\r
+\r
+       label_wstrd:\r
+       wstrd   wr0,[r1]\r
+       wstrd   wr0,[r1],4\r
+       wstrd   wr0,[r1],{4}\r
+       wstrd   wr0,[r1,4]\r
+       wstrd   wr0,[r1,4]!\r
+       wstrd   wr0,[label_wstrd]\r
+       wstrd   wr0,[expression.dword]\r
+       wstrd   wr0,[expression.dword]!\r
+\r
+       label_wstrh:\r
+       wstrh   wr0,[r1]\r
+       wstrh   wr0,[r1],4\r
+       wstrh   wr0,[r1],{4}\r
+       wstrh   wr0,[r1,4]\r
+       wstrh   wr0,[r1,4]!\r
+       wstrh   wr0,[label_wstrh]\r
+       wstrh   wr0,[expression.hword]\r
+       wstrh   wr0,[expression.hword]!\r
+\r
+       label_wstrw:\r
+       wstrw   wr0,[r1]\r
+       wstrw   wr0,[r1],4\r
+       wstrw   wr0,[r1],{4}\r
+       wstrw   wr0,[r1,4]\r
+       wstrw   wr0,[r1,4]!\r
+       wstrw   wr0,[label_wstrw]\r
+       wstrw   wr0,[expression.word]\r
+       wstrw   wr0,[expression.word]!\r
+       wstrw   wcgr0,[r1]\r
+       wstrw   wcgr0,[r1],4\r
+       wstrw   wcgr0,[r1],{4}\r
+       wstrw   wcgr0,[r1,4]\r
+       wstrw   wcgr0,[r1,4]!\r
+       wstrw   wcgr0,[label_wstrw]\r
+       wstrw   wcgr0,[expression.word]\r
+       wstrw   wcgr0,[expression.word]!\r
+\r
+       wsubb   wr0,wr1,wr2\r
+\r
+       wsubbss wr0,wr1,wr2\r
+\r
+       wsubbus wr0,wr1,wr2\r
+\r
+       wsubh   wr0,wr1,wr2\r
+\r
+       wsubhss wr0,wr1,wr2\r
+\r
+       wsubhus wr0,wr1,wr2\r
+\r
+       wsubw   wr0,wr1,wr2\r
+\r
+       wsubwss wr0,wr1,wr2\r
+\r
+       wsubwus wr0,wr1,wr2\r
+\r
+       wunpckehsb      wr0,wr1\r
+\r
+       wunpckehsh      wr0,wr1\r
+\r
+       wunpckehsw      wr0,wr1\r
+\r
+       wunpckehub      wr0,wr1\r
+\r
+       wunpckehuh      wr0,wr1\r
+\r
+       wunpckehuw      wr0,wr1\r
+\r
+       wunpckelsb      wr0,wr1\r
+\r
+       wunpckelsh      wr0,wr1\r
+\r
+       wunpckelsw      wr0,wr1\r
+\r
+       wunpckelub      wr0,wr1\r
+\r
+       wunpckeluh      wr0,wr1\r
+\r
+       wunpckeluw      wr0,wr1\r
+\r
+       wunpckihb       wr0,wr1,wr2\r
+\r
+       wunpckihh       wr0,wr1,wr2\r
+\r
+       wunpckihw       wr0,wr1,wr2\r
+\r
+       wunpckilb       wr0,wr1,wr2\r
+\r
+       wunpckilh       wr0,wr1,wr2\r
+\r
+       wunpckilw       wr0,wr1,wr2\r
+\r
+       wxor    wr0,wr1,wr2\r
+\r
+       wzero   wr0\r
+\r
+coprocessor COPRO_IWMMXT_V2\r
+       torvscb r15\r
+\r
+       torvsch r15\r
+\r
+       torvscw r15\r
+\r
+       wabsb   wr0,wr1\r
+\r
+       wabsdiffb       wr0,wr1,wr2\r
+\r
+       wabsdiffh       wr0,wr1,wr2\r
+\r
+       wabsdiffw       wr0,wr1,wr2\r
+\r
+       wabsh   wr0,wr1\r
+\r
+       wabsw   wr0,wr1\r
+\r
+       waddhc  wr0,wr1,wr2\r
+\r
+       waddsubhx       wr0,wr1,wr2\r
+\r
+       waddwc  wr0,wr1,wr2\r
+\r
+       wavg4   wr0,wr1,wr2\r
+\r
+       wavg4r  wr0,wr1,wr2\r
+\r
+       wldrd   wr0,[r1],r2\r
+       wldrd   wr0,[r1],-r2\r
+       wldrd   wr0,[r1],r2,lsl 2\r
+       wldrd   wr0,[r1],-r2,lsl 2\r
+       wldrd   wr0,[r1,r2]\r
+       wldrd   wr0,[r1,-r2]\r
+       wldrd   wr0,[r1,r2]!\r
+       wldrd   wr0,[r1,-r2]!\r
+       wldrd   wr0,[r1,r2,lsl 2]\r
+       wldrd   wr0,[r1,-r2,lsl 2]\r
+       wldrd   wr0,[r1,r2,lsl 2]!\r
+       wldrd   wr0,[r1,-r2,lsl 2]!\r
+\r
+       wmaddsn wr0,wr1,wr2\r
+\r
+       wmaddsx wr0,wr1,wr2\r
+\r
+       wmaddun wr0,wr1,wr2\r
+\r
+       wmaddux wr0,wr1,wr2\r
+\r
+       wmerge  wr0,wr1,wr2,3\r
+\r
+       wmiabb  wr0,wr1,wr2\r
+\r
+       wmiabbn wr0,wr1,wr2\r
+\r
+       wmiabt  wr0,wr1,wr2\r
+\r
+       wmiabtn wr0,wr1,wr2\r
+\r
+       wmiatb  wr0,wr1,wr2\r
+\r
+       wmiatbn wr0,wr1,wr2\r
+\r
+       wmiatt  wr0,wr1,wr2\r
+\r
+       wmiattn wr0,wr1,wr2\r
+\r
+       wmiawbb wr0,wr1,wr2\r
+\r
+       wmiawbbn        wr0,wr1,wr2\r
+\r
+       wmiawbt wr0,wr1,wr2\r
+\r
+       wmiawbtn        wr0,wr1,wr2\r
+\r
+       wmiawtb wr0,wr1,wr2\r
+\r
+       wmiawtbn        wr0,wr1,wr2\r
+\r
+       wmiawtt wr0,wr1,wr2\r
+\r
+       wmiawttn        wr0,wr1,wr2\r
+\r
+       wmulsmr wr0,wr1,wr2\r
+\r
+       wmulumr wr0,wr1,wr2\r
+\r
+       wmulwl  wr0,wr1,wr2\r
+\r
+       wmulwsm wr0,wr1,wr2\r
+\r
+       wmulwsmr        wr0,wr1,wr2\r
+\r
+       wmulwum wr0,wr1,wr2\r
+\r
+       wmulwumr        wr0,wr1,wr2\r
+\r
+       wqmiabb wr0,wr1,wr2\r
+\r
+       wqmiabbn        wr0,wr1,wr2\r
+\r
+       wqmiabt wr0,wr1,wr2\r
+\r
+       wqmiabtn        wr0,wr1,wr2\r
+\r
+       wqmiatb wr0,wr1,wr2\r
+\r
+       wqmiatbn        wr0,wr1,wr2\r
+\r
+       wqmiatt wr0,wr1,wr2\r
+\r
+       wqmiattn        wr0,wr1,wr2\r
+\r
+       wqmulm  wr0,wr1,wr2\r
+\r
+       wqmulmr wr0,wr1,wr2\r
+\r
+       wqmulwm wr0,wr1,wr2\r
+\r
+       wqmulwmr        wr0,wr1,wr2\r
+\r
+       wrord   wr0,wr1,2\r
+\r
+       wrorh   wr0,wr1,2\r
+\r
+       wrorw   wr0,wr1,2\r
+\r
+       wslld   wr0,wr1,2\r
+\r
+       wsllh   wr0,wr1,2\r
+\r
+       wsllw   wr0,wr1,2\r
+\r
+       wsrad   wr0,wr1,2\r
+\r
+       wsrah   wr0,wr1,2\r
+\r
+       wsraw   wr0,wr1,2\r
+\r
+       wsrld   wr0,wr1,2\r
+\r
+       wsrlh   wr0,wr1,2\r
+\r
+       wsrlw   wr0,wr1,2\r
+\r
+       wstrd   wr0,[r1],r2\r
+       wstrd   wr0,[r1],-r2\r
+       wstrd   wr0,[r1],r2,lsl 2\r
+       wstrd   wr0,[r1],-r2,lsl 2\r
+       wstrd   wr0,[r1,r2]\r
+       wstrd   wr0,[r1,-r2]\r
+       wstrd   wr0,[r1,r2]!\r
+       wstrd   wr0,[r1,-r2]!\r
+       wstrd   wr0,[r1,r2,lsl 2]\r
+       wstrd   wr0,[r1,-r2,lsl 2]\r
+       wstrd   wr0,[r1,r2,lsl 2]!\r
+       wstrd   wr0,[r1,-r2,lsl 2]!\r
+\r
+       wsubaddhx       wr0,wr1,wr2\r

diff --git a/armdoc/InstructionFormatsMAVERICK.asm b/armdoc/InstructionFormatsMAVERICK.asm
new file mode 100644 (file)
index 0000000..e82b768
--- /dev/null
+++ b/armdoc/InstructionFormatsMAVERICK.asm
@@ -0,0 +1,278 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;To avoid unnecessary repetition only ARM mode is used\r
+;here. There is no change needed for THUMB mode except\r
+;to specify that the processor supports version 7M\r
+;architecture instructions.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;All instructions can be conditional. The condition code\r
+;should be added at the end of the main opcode and\r
+;before any size/type specifiers. For example: "addhi"\r
+;and "vaddhi.i16". The syntax also supports the pre-UAL\r
+;style of putting the condition before any modifiers\r
+;like "s" or "fd". For example: "ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;MAVERICK, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_MAVERICK\r
+\r
+       cfabs32 c0,c1\r
+\r
+       cfabs64 c0,c1\r
+\r
+       cfabsd  c0,c1\r
+\r
+       cfabss  c0,c1\r
+\r
+       cfadd32 c0,c1,c2\r
+\r
+       cfadd64 c0,c1,c2\r
+\r
+       cfaddd  c0,c1,c2\r
+\r
+       cfadds  c0,c1,c2\r
+\r
+       cfcmp32 r1,c1,c2\r
+\r
+       cfcmp64 r1,c1,c2\r
+\r
+       cfcmpd  r1,c1,c2\r
+\r
+       cfcmps  r1,c1,c2\r
+\r
+       cfcpyd  c0,c1\r
+\r
+       cfcpys  c0,c1\r
+\r
+       cfcvt32d        c0,c1\r
+\r
+       cfcvt32s        c0,c1\r
+\r
+       cfcvt64d        c0,c1\r
+\r
+       cfcvt64s        c0,c1\r
+\r
+       cfcvtd32        c0,c1\r
+\r
+       cfcvtds c0,c1\r
+\r
+       cfcvts32        c0,c1\r
+\r
+       cfcvtsd c0,c1\r
+\r
+       label_cfldr32:\r
+       cfldr32 c0,[r1]\r
+       cfldr32 c0,[r1],4\r
+       cfldr32 c0,[r1],{4}\r
+       cfldr32 c0,[r1,4]\r
+       cfldr32 c0,[r1,4]!\r
+       cfldr32 c0,[label_cfldr32]\r
+       cfldr32 c0,[expression.word]\r
+       cfldr32 c0,[expression.word]!\r
+\r
+       label_cfldr64:\r
+       cfldr64 c0,[r1]\r
+       cfldr64 c0,[r1],4\r
+       cfldr64 c0,[r1],{4}\r
+       cfldr64 c0,[r1,4]\r
+       cfldr64 c0,[r1,4]!\r
+       cfldr64 c0,[label_cfldr64]\r
+       cfldr64 c0,[expression.word]\r
+       cfldr64 c0,[expression.word]!\r
+\r
+       label_cfldrd:\r
+       cfldrd  c0,[r1]\r
+       cfldrd  c0,[r1],4\r
+       cfldrd  c0,[r1],{4}\r
+       cfldrd  c0,[r1,4]\r
+       cfldrd  c0,[r1,4]!\r
+       cfldrd  c0,[label_cfldrd]\r
+       cfldrd  c0,[expression.word]\r
+       cfldrd  c0,[expression.word]!\r
+\r
+       label_cfldrs:\r
+       cfldrs  c0,[r1]\r
+       cfldrs  c0,[r1],4\r
+       cfldrs  c0,[r1],{4}\r
+       cfldrs  c0,[r1,4]\r
+       cfldrs  c0,[r1,4]!\r
+       cfldrs  c0,[label_cfldrs]\r
+       cfldrs  c0,[expression.word]\r
+       cfldrs  c0,[expression.word]!\r
+\r
+       cfmac32 c0,c1,c2\r
+\r
+       cfmadd32        a0,c1,c2,c3\r
+\r
+       cfmadda32       a0,a1,c2,c4\r
+\r
+       cfmsc32 c0,c1,c2\r
+\r
+       cfmsub32        a0,c1,c2,c4\r
+\r
+       cfmsuba32       a0,a1,c2,c4\r
+\r
+       cfmul32 c0,c1,c2\r
+\r
+       cfmul64 c0,c1,c2\r
+\r
+       cfmuld  c0,c1,c2\r
+\r
+       cfmuls  c0,c1,c2\r
+\r
+       cfmv32a c0,a1\r
+\r
+       cfmv32ah        c0,a1\r
+\r
+       cfmv32al        c0,a1\r
+\r
+       cfmv32am        c0,a1\r
+\r
+       cfmv32sc        c0,dspsc\r
+\r
+       cfmv64a c0,a1\r
+\r
+       cfmv64hr        c0,r1\r
+\r
+       cfmv64lr        c0,r1\r
+\r
+       cfmva32 a0,c1\r
+\r
+       cfmva64 a0,c1\r
+\r
+       cfmvah32        a0,c1\r
+\r
+       cfmval32        a0,c1\r
+\r
+       cfmvam32        a0,c1\r
+\r
+       cfmvdhr c0,r1\r
+\r
+       cfmvdlr c0,r1\r
+\r
+       cfmvr64h        r1,c1\r
+\r
+       cfmvr64l        r1,c1\r
+\r
+       cfmvrdh r1,c1\r
+\r
+       cfmvrdl r1,c1\r
+\r
+       cfmvrs  r1,c1\r
+\r
+       cfmvsc32        dspsc,c0\r
+\r
+       cfmvsr  c0,r1\r
+\r
+       cfneg32 c0,c1\r
+\r
+       cfneg64 c0,c1\r
+\r
+       cfnegd  c0,c1\r
+\r
+       cfnegs  c0,c1\r
+\r
+       cfrshl32        c0,c1,r3\r
+\r
+       cfrshl64        c0,c1,r3\r
+\r
+       cfsh32  c0,c1,2\r
+\r
+       cfsh64  c0,c1,2\r
+\r
+       label_cfstr32:\r
+       cfstr32 c0,[r1]\r
+       cfstr32 c0,[r1],4\r
+       cfstr32 c0,[r1],{4}\r
+       cfstr32 c0,[r1,4]\r
+       cfstr32 c0,[r1,4]!\r
+       cfstr32 c0,[label_cfstr32]\r
+       cfstr32 c0,[expression.word]\r
+       cfstr32 c0,[expression.word]!\r
+\r
+       label_cfstr64:\r
+       cfstr64 c0,[r1]\r
+       cfstr64 c0,[r1],4\r
+       cfstr64 c0,[r1],{4}\r
+       cfstr64 c0,[r1,4]\r
+       cfstr64 c0,[r1,4]!\r
+       cfstr64 c0,[label_cfstr64]\r
+       cfstr64 c0,[expression.word]\r
+       cfstr64 c0,[expression.word]!\r
+\r
+       label_cfstrd:\r
+       cfstrd  c0,[r1]\r
+       cfstrd  c0,[r1],4\r
+       cfstrd  c0,[r1],{4}\r
+       cfstrd  c0,[r1,4]\r
+       cfstrd  c0,[r1,4]!\r
+       cfstrd  c0,[label_cfstrd]\r
+       cfstrd  c0,[expression.word]\r
+       cfstrd  c0,[expression.word]!\r
+\r
+       label_cfstrs:\r
+       cfstrs  c0,[r1]\r
+       cfstrs  c0,[r1],4\r
+       cfstrs  c0,[r1],{4}\r
+       cfstrs  c0,[r1,4]\r
+       cfstrs  c0,[r1,4]!\r
+       cfstrs  c0,[label_cfstrs]\r
+       cfstrs  c0,[expression.word]\r
+       cfstrs  c0,[expression.word]!\r
+\r
+       cfsub32 c0,c1,c2\r
+\r
+       cfsub64 c0,c1,c2\r
+\r
+       cfsubd  c0,c1,c2\r
+\r
+       cfsubs  c0,c1,c2\r
+\r
+       cftruncd32      c0,c1\r
+\r
+       cftruncs32      c0,c1\r

diff --git a/armdoc/InstructionFormatsSIMD.asm b/armdoc/InstructionFormatsSIMD.asm
new file mode 100644 (file)
index 0000000..d24dc0d
--- /dev/null
+++ b/armdoc/InstructionFormatsSIMD.asm
@@ -0,0 +1,3056 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;To avoid unnecessary repetition only ARM mode is used\r
+;here. There is no change needed for THUMB mode except\r
+;to specify that the processor supports version 7M\r
+;architecture instructions.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;In THUMB mode all instructions can be conditional. In\r
+;ARM mode most instructions are unconditional. The\r
+;condition code should be added at the end of the main\r
+;opcode and before any size/type specifiers. For\r
+;example: "addhi" and "vaddhi.i16". The syntax also\r
+;supports the pre-UAL style of putting the condition\r
+;before any modifiers like "s" or "fd". For example:\r
+;"ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;SIMD, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_SIMD_INT\r
+\r
+       vaba.s16        d0,d1,d2\r
+       vaba.s16        q0,q1,q2\r
+\r
+       vaba.s32        d0,d1,d2\r
+       vaba.s32        q0,q1,q2\r
+\r
+       vaba.s8 d0,d1,d2\r
+       vaba.s8 q0,q1,q2\r
+\r
+       vaba.u16        d0,d1,d2\r
+       vaba.u16        q0,q1,q2\r
+\r
+       vaba.u32        d0,d1,d2\r
+       vaba.u32        q0,q1,q2\r
+\r
+       vaba.u8 d0,d1,d2\r
+       vaba.u8 q0,q1,q2\r
+\r
+       vabal.s16       q0,d1,d2\r
+\r
+       vabal.s32       q0,d1,d2\r
+\r
+       vabal.s8        q0,d1,d2\r
+\r
+       vabal.u16       q0,d1,d2\r
+\r
+       vabal.u32       q0,d1,d2\r
+\r
+       vabal.u8        q0,d1,d2\r
+\r
+       vabd.s16        d0,d1\r
+       vabd.s16        d0,d1,d2\r
+       vabd.s16        q0,q1\r
+       vabd.s16        q0,q1,q2\r
+\r
+       vabd.s32        d0,d1\r
+       vabd.s32        d0,d1,d2\r
+       vabd.s32        q0,q1\r
+       vabd.s32        q0,q1,q2\r
+\r
+       vabd.s8 d0,d1\r
+       vabd.s8 d0,d1,d2\r
+       vabd.s8 q0,q1\r
+       vabd.s8 q0,q1,q2\r
+\r
+       vabd.u16        d0,d1\r
+       vabd.u16        d0,d1,d2\r
+       vabd.u16        q0,q1\r
+       vabd.u16        q0,q1,q2\r
+\r
+       vabd.u32        d0,d1\r
+       vabd.u32        d0,d1,d2\r
+       vabd.u32        q0,q1\r
+       vabd.u32        q0,q1,q2\r
+\r
+       vabd.u8 d0,d1\r
+       vabd.u8 d0,d1,d2\r
+       vabd.u8 q0,q1\r
+       vabd.u8 q0,q1,q2\r
+\r
+       vabdl.s16       q0,d1,d2\r
+\r
+       vabdl.s32       q0,d1,d2\r
+\r
+       vabdl.s8        q0,d1,d2\r
+\r
+       vabdl.u16       q0,d1,d2\r
+\r
+       vabdl.u32       q0,d1,d2\r
+\r
+       vabdl.u8        q0,d1,d2\r
+\r
+       vabs.s16        d0,d1\r
+       vabs.s16        q0,q1\r
+\r
+       vabs.s32        d0,d1\r
+       vabs.s32        q0,q1\r
+\r
+       vabs.s8 d0,d1\r
+       vabs.s8 q0,q1\r
+\r
+       vadd.i16        d0,d1\r
+       vadd.i16        d0,d1,d2\r
+       vadd.i16        q0,q1\r
+       vadd.i16        q0,q1,q2\r
+\r
+       vadd.i32        d0,d1\r
+       vadd.i32        d0,d1,d2\r
+       vadd.i32        q0,q1\r
+       vadd.i32        q0,q1,q2\r
+\r
+       vadd.i64        d0,d1\r
+       vadd.i64        d0,d1,d2\r
+       vadd.i64        q0,q1\r
+       vadd.i64        q0,q1,q2\r
+\r
+       vadd.i8 d0,d1\r
+       vadd.i8 d0,d1,d2\r
+       vadd.i8 q0,q1\r
+       vadd.i8 q0,q1,q2\r
+\r
+       vaddhn.i16      d0,q1,q2\r
+\r
+       vaddhn.i32      d0,q1,q2\r
+\r
+       vaddhn.i64      d0,q1,q2\r
+\r
+       vaddl.s16       q0,d1,d2\r
+\r
+       vaddl.s32       q0,d1,d2\r
+\r
+       vaddl.s8        q0,d1,d2\r
+\r
+       vaddl.u16       q0,d1,d2\r
+\r
+       vaddl.u32       q0,d1,d2\r
+\r
+       vaddl.u8        q0,d1,d2\r
+\r
+       vaddw.s16       q0,d1\r
+       vaddw.s16       q0,q1,d2\r
+\r
+       vaddw.s32       q0,d1\r
+       vaddw.s32       q0,q1,d2\r
+\r
+       vaddw.s8        q0,d1\r
+       vaddw.s8        q0,q1,d2\r
+\r
+       vaddw.u16       q0,d1\r
+       vaddw.u16       q0,q1,d2\r
+\r
+       vaddw.u32       q0,d1\r
+       vaddw.u32       q0,q1,d2\r
+\r
+       vaddw.u8        q0,d1\r
+       vaddw.u8        q0,q1,d2\r
+\r
+       vand    d0,d1\r
+       vand    d0,d1,d2\r
+       vand    q0,q1\r
+       vand    q0,q1,q2\r
+\r
+       vand.i16        d0,not 1\r
+       vand.i16        q0,0xfffe\r
+\r
+       vand.i32        d0,not 1\r
+       vand.i32        q0,not 1\r
+\r
+       vbic    d0,d1\r
+       vbic    d0,d1,d2\r
+       vbic    q0,q1\r
+       vbic    q0,q1,q2\r
+\r
+       vbic.i16        d0,1\r
+       vbic.i16        q0,not -2\r
+\r
+       vbic.i32        d0,1\r
+       vbic.i32        q0,1\r
+\r
+       vbif    d0,d1\r
+       vbif    d0,d1,d2\r
+       vbif    q0,q1\r
+       vbif    q0,q1,q2\r
+\r
+       vbit    d0,d1\r
+       vbit    d0,d1,d2\r
+       vbit    q0,q1\r
+       vbit    q0,q1,q2\r
+\r
+       vbsl    d0,d1\r
+       vbsl    d0,d1,d2\r
+       vbsl    q0,q1\r
+       vbsl    q0,q1,q2\r
+\r
+       vceq.i16        d0,0\r
+       vceq.i16        d0,d1\r
+       vceq.i16        d0,d1,0\r
+       vceq.i16        d0,d1,d2\r
+       vceq.i16        q0,0\r
+       vceq.i16        q0,q1\r
+       vceq.i16        q0,q1,0\r
+       vceq.i16        q0,q1,q2\r
+\r
+       vceq.i32        d0,0\r
+       vceq.i32        d0,d1\r
+       vceq.i32        d0,d1,0\r
+       vceq.i32        d0,d1,d2\r
+       vceq.i32        q0,0\r
+       vceq.i32        q0,q1\r
+       vceq.i32        q0,q1,0\r
+       vceq.i32        q0,q1,q2\r
+\r
+       vceq.i8 d0,0\r
+       vceq.i8 d0,d1\r
+       vceq.i8 d0,d1,0\r
+       vceq.i8 d0,d1,d2\r
+       vceq.i8 q0,0\r
+       vceq.i8 q0,q1\r
+       vceq.i8 q0,q1,0\r
+       vceq.i8 q0,q1,q2\r
+\r
+       vcge.s16        d0,0\r
+       vcge.s16        d0,d1\r
+       vcge.s16        d0,d1,0\r
+       vcge.s16        d0,d1,d2\r
+       vcge.s16        q0,0\r
+       vcge.s16        q0,q1\r
+       vcge.s16        q0,q1,0\r
+       vcge.s16        q0,q1,q2\r
+\r
+       vcge.s32        d0,0\r
+       vcge.s32        d0,d1\r
+       vcge.s32        d0,d1,0\r
+       vcge.s32        d0,d1,d2\r
+       vcge.s32        q0,0\r
+       vcge.s32        q0,q1\r
+       vcge.s32        q0,q1,0\r
+       vcge.s32        q0,q1,q2\r
+\r
+       vcge.s8 d0,0\r
+       vcge.s8 d0,d1\r
+       vcge.s8 d0,d1,0\r
+       vcge.s8 d0,d1,d2\r
+       vcge.s8 q0,0\r
+       vcge.s8 q0,q1\r
+       vcge.s8 q0,q1,0\r
+       vcge.s8 q0,q1,q2\r
+\r
+       vcge.u16        d0,d1\r
+       vcge.u16        d0,d1,d2\r
+       vcge.u16        q0,q1\r
+       vcge.u16        q0,q1,q2\r
+\r
+       vcge.u32        d0,d1\r
+       vcge.u32        d0,d1,d2\r
+       vcge.u32        q0,q1\r
+       vcge.u32        q0,q1,q2\r
+\r
+       vcge.u8 d0,d1\r
+       vcge.u8 d0,d1,d2\r
+       vcge.u8 q0,q1\r
+       vcge.u8 q0,q1,q2\r
+\r
+       vcgt.s16        d0,0\r
+       vcgt.s16        d0,d1\r
+       vcgt.s16        d0,d1,0\r
+       vcgt.s16        d0,d1,d2\r
+       vcgt.s16        q0,0\r
+       vcgt.s16        q0,q1\r
+       vcgt.s16        q0,q1,0\r
+       vcgt.s16        q0,q1,q2\r
+\r
+       vcgt.s32        d0,0\r
+       vcgt.s32        d0,d1\r
+       vcgt.s32        d0,d1,0\r
+       vcgt.s32        d0,d1,d2\r
+       vcgt.s32        q0,0\r
+       vcgt.s32        q0,q1\r
+       vcgt.s32        q0,q1,0\r
+       vcgt.s32        q0,q1,q2\r
+\r
+       vcgt.s8 d0,0\r
+       vcgt.s8 d0,d1\r
+       vcgt.s8 d0,d1,0\r
+       vcgt.s8 d0,d1,d2\r
+       vcgt.s8 q0,0\r
+       vcgt.s8 q0,q1\r
+       vcgt.s8 q0,q1,0\r
+       vcgt.s8 q0,q1,q2\r
+\r
+       vcgt.u16        d0,d1\r
+       vcgt.u16        d0,d1,d2\r
+       vcgt.u16        q0,q1\r
+       vcgt.u16        q0,q1,q2\r
+\r
+       vcgt.u32        d0,d1\r
+       vcgt.u32        d0,d1,d2\r
+       vcgt.u32        q0,q1\r
+       vcgt.u32        q0,q1,q2\r
+\r
+       vcgt.u8 d0,d1\r
+       vcgt.u8 d0,d1,d2\r
+       vcgt.u8 q0,q1\r
+       vcgt.u8 q0,q1,q2\r
+\r
+       vcle.s16        d0,0\r
+       vcle.s16        d0,d1\r
+       vcle.s16        d0,d1,0\r
+       vcle.s16        d0,d1,d2\r
+       vcle.s16        q0,0\r
+       vcle.s16        q0,q1\r
+       vcle.s16        q0,q1,0\r
+       vcle.s16        q0,q1,q2\r
+\r
+       vcle.s32        d0,0\r
+       vcle.s32        d0,d1\r
+       vcle.s32        d0,d1,0\r
+       vcle.s32        d0,d1,d2\r
+       vcle.s32        q0,0\r
+       vcle.s32        q0,q1\r
+       vcle.s32        q0,q1,0\r
+       vcle.s32        q0,q1,q2\r
+\r
+       vcle.s8 d0,0\r
+       vcle.s8 d0,d1\r
+       vcle.s8 d0,d1,0\r
+       vcle.s8 d0,d1,d2\r
+       vcle.s8 q0,0\r
+       vcle.s8 q0,q1\r
+       vcle.s8 q0,q1,0\r
+       vcle.s8 q0,q1,q2\r
+\r
+       vcle.u16        d0,d1\r
+       vcle.u16        d0,d1,d2\r
+       vcle.u16        q0,q1\r
+       vcle.u16        q0,q1,q2\r
+\r
+       vcle.u32        d0,d1\r
+       vcle.u32        d0,d1,d2\r
+       vcle.u32        q0,q1\r
+       vcle.u32        q0,q1,q2\r
+\r
+       vcle.u8 d0,d1\r
+       vcle.u8 d0,d1,d2\r
+       vcle.u8 q0,q1\r
+       vcle.u8 q0,q1,q2\r
+\r
+       vcls.s16        d0,d1\r
+       vcls.s16        q0,q1\r
+\r
+       vcls.s32        d0,d1\r
+       vcls.s32        q0,q1\r
+\r
+       vcls.s8 d0,d1\r
+       vcls.s8 q0,q1\r
+\r
+       vclt.s16        d0,0\r
+       vclt.s16        d0,d1\r
+       vclt.s16        d0,d1,0\r
+       vclt.s16        d0,d1,d2\r
+       vclt.s16        q0,0\r
+       vclt.s16        q0,q1\r
+       vclt.s16        q0,q1,0\r
+       vclt.s16        q0,q1,q2\r
+\r
+       vclt.s32        d0,0\r
+       vclt.s32        d0,d1\r
+       vclt.s32        d0,d1,0\r
+       vclt.s32        d0,d1,d2\r
+       vclt.s32        q0,0\r
+       vclt.s32        q0,q1\r
+       vclt.s32        q0,q1,0\r
+       vclt.s32        q0,q1,q2\r
+\r
+       vclt.s8 d0,0\r
+       vclt.s8 d0,d1\r
+       vclt.s8 d0,d1,0\r
+       vclt.s8 d0,d1,d2\r
+       vclt.s8 q0,0\r
+       vclt.s8 q0,q1\r
+       vclt.s8 q0,q1,0\r
+       vclt.s8 q0,q1,q2\r
+\r
+       vclt.u16        d0,d1\r
+       vclt.u16        d0,d1,d2\r
+       vclt.u16        q0,q1\r
+       vclt.u16        q0,q1,q2\r
+\r
+       vclt.u32        d0,d1\r
+       vclt.u32        d0,d1,d2\r
+       vclt.u32        q0,q1\r
+       vclt.u32        q0,q1,q2\r
+\r
+       vclt.u8 d0,d1\r
+       vclt.u8 d0,d1,d2\r
+       vclt.u8 q0,q1\r
+       vclt.u8 q0,q1,q2\r
+\r
+       vclz.i16        d0,d1\r
+       vclz.i16        q0,q1\r
+\r
+       vclz.i32        d0,d1\r
+       vclz.i32        q0,q1\r
+\r
+       vclz.i8 d0,d1\r
+       vclz.i8 q0,q1\r
+\r
+       vcnt.8  d0,d1\r
+       vcnt.8  q0,q1\r
+\r
+       vdup.16 d0,d1[0]\r
+       vdup.16 d0,r1\r
+       vdup.16 q0,d1[1]\r
+       vdup.16 q0,r1\r
+\r
+       vdup.32 d0,d1[0]\r
+       vdup.32 d0,r1\r
+       vdup.32 q0,d1[1]\r
+       vdup.32 q0,r1\r
+\r
+       vdup.8  d0,d1[0]\r
+       vdup.8  d0,r1\r
+       vdup.8  q0,d1[1]\r
+       vdup.8  q0,r1\r
+\r
+       veor    d0,d1\r
+       veor    d0,d1,d2\r
+       veor    q0,q1\r
+       veor    q0,q1,q2\r
+\r
+       vext.16 d0,d1,1\r
+       vext.16 d0,d1,d2,1\r
+       vext.16 q0,q1,1\r
+       vext.16 q0,q1,q2,1\r
+\r
+       vext.32 d0,d1,1\r
+       vext.32 d0,d1,d2,1\r
+       vext.32 q0,q1,1\r
+       vext.32 q0,q1,q2,1\r
+\r
+       vext.64 d0,d1,0\r
+       vext.64 d0,d1,d2,0\r
+       vext.64 q0,q1,1\r
+       vext.64 q0,q1,q2,1\r
+\r
+       vext.8  d0,d1,2\r
+       vext.8  d0,d1,d2,1\r
+       vext.8  q0,q1,2\r
+       vext.8  q0,q1,q2,1\r
+\r
+       vhadd.s16       d0,d1\r
+       vhadd.s16       d0,d1,d2\r
+       vhadd.s16       q0,q1\r
+       vhadd.s16       q0,q1,q2\r
+\r
+       vhadd.s32       d0,d1\r
+       vhadd.s32       d0,d1,d2\r
+       vhadd.s32       q0,q1\r
+       vhadd.s32       q0,q1,q2\r
+\r
+       vhadd.s8        d0,d1\r
+       vhadd.s8        d0,d1,d2\r
+       vhadd.s8        q0,q1\r
+       vhadd.s8        q0,q1,q2\r
+\r
+       vhadd.u16       d0,d1\r
+       vhadd.u16       d0,d1,d2\r
+       vhadd.u16       q0,q1\r
+       vhadd.u16       q0,q1,q2\r
+\r
+       vhadd.u32       d0,d1\r
+       vhadd.u32       d0,d1,d2\r
+       vhadd.u32       q0,q1\r
+       vhadd.u32       q0,q1,q2\r
+\r
+       vhadd.u8        d0,d1\r
+       vhadd.u8        d0,d1,d2\r
+       vhadd.u8        q0,q1\r
+       vhadd.u8        q0,q1,q2\r
+\r
+       vhsub.s16       d0,d1\r
+       vhsub.s16       d0,d1,d2\r
+       vhsub.s16       q0,q1\r
+       vhsub.s16       q0,q1,q2\r
+\r
+       vhsub.s32       d0,d1\r
+       vhsub.s32       d0,d1,d2\r
+       vhsub.s32       q0,q1\r
+       vhsub.s32       q0,q1,q2\r
+\r
+       vhsub.s8        d0,d1\r
+       vhsub.s8        d0,d1,d2\r
+       vhsub.s8        q0,q1\r
+       vhsub.s8        q0,q1,q2\r
+\r
+       vhsub.u16       d0,d1\r
+       vhsub.u16       d0,d1,d2\r
+       vhsub.u16       q0,q1\r
+       vhsub.u16       q0,q1,q2\r
+\r
+       vhsub.u32       d0,d1\r
+       vhsub.u32       d0,d1,d2\r
+       vhsub.u32       q0,q1\r
+       vhsub.u32       q0,q1,q2\r
+\r
+       vhsub.u8        d0,d1\r
+       vhsub.u8        d0,d1,d2\r
+       vhsub.u8        q0,q1\r
+       vhsub.u8        q0,q1,q2\r
+\r
+       vld1.16 {d0},[r1]\r
+       vld1.16 {d0},[r1]!\r
+       vld1.16 {d0},[r1],8\r
+       vld1.16 {d0},[r1],r2\r
+       vld1.16 {d0},[r1@64]\r
+       vld1.16 {d0},[r1@64]!\r
+       vld1.16 {d0},[r1@64],8\r
+       vld1.16 {d0},[r1@64],r2\r
+       vld1.16 {d0,d1},[r2]\r
+       vld1.16 {d0,d1},[r2]!\r
+       vld1.16 {d0,d1},[r2],16\r
+       vld1.16 {d0,d1},[r2],r3\r
+       vld1.16 {d0,d1},[r2@64]\r
+       vld1.16 {d0,d1},[r2@64]!\r
+       vld1.16 {d0,d1},[r2@64],16\r
+       vld1.16 {d0,d1},[r2@64],r3\r
+       vld1.16 {d0,d1,d2},[r3]\r
+       vld1.16 {d0,d1,d2},[r3]!\r
+       vld1.16 {d0,d1,d2},[r3],24\r
+       vld1.16 {d0,d1,d2},[r3],r4\r
+       vld1.16 {d0,d1,d2},[r3@64]\r
+       vld1.16 {d0,d1,d2},[r3@64]!\r
+       vld1.16 {d0,d1,d2},[r3@64],24\r
+       vld1.16 {d0,d1,d2},[r3@64],r4\r
+       vld1.16 {d0,d1,d2,d3},[r4]\r
+       vld1.16 {d0,d1,d2,d3},[r4]!\r
+       vld1.16 {d0,d1,d2,d3},[r4],32\r
+       vld1.16 {d0,d1,d2,d3},[r4],r5\r
+       vld1.16 {d0,d1,d2,d3},[r4@64]\r
+       vld1.16 {d0,d1,d2,d3},[r4@64]!\r
+       vld1.16 {d0,d1,d2,d3},[r4@64],32\r
+       vld1.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vld1.16 {d0[1]},[r2]\r
+       vld1.16 {d0[1]},[r2]!\r
+       vld1.16 {d0[1]},[r2],2\r
+       vld1.16 {d0[1]},[r2],r3\r
+       vld1.16 {d0[1]},[r2@16]\r
+       vld1.16 {d0[1]},[r2@16]!\r
+       vld1.16 {d0[1]},[r2@16],2\r
+       vld1.16 {d0[1]},[r2@16],r3\r
+       vld1.16 {d0[]},[r1]\r
+       vld1.16 {d0[]},[r1]!\r
+       vld1.16 {d0[]},[r1],2\r
+       vld1.16 {d0[]},[r1],r2\r
+       vld1.16 {d0[]},[r1@16]\r
+       vld1.16 {d0[]},[r1@16]!\r
+       vld1.16 {d0[]},[r1@16],2\r
+       vld1.16 {d0[]},[r1@16],r2\r
+       vld1.16 {d0[],d1[]},[r2]\r
+       vld1.16 {d0[],d1[]},[r2]!\r
+       vld1.16 {d0[],d1[]},[r2],2\r
+       vld1.16 {d0[],d1[]},[r2],r3\r
+       vld1.16 {d0[],d1[]},[r2@16]\r
+       vld1.16 {d0[],d1[]},[r2@16]!\r
+       vld1.16 {d0[],d1[]},[r2@16],2\r
+       vld1.16 {d0[],d1[]},[r2@16],r3\r
+\r
+       vld1.32 {d0},[r1]\r
+       vld1.32 {d0},[r1]!\r
+       vld1.32 {d0},[r1],8\r
+       vld1.32 {d0},[r1],r2\r
+       vld1.32 {d0},[r1@64]\r
+       vld1.32 {d0},[r1@64]!\r
+       vld1.32 {d0},[r1@64],8\r
+       vld1.32 {d0},[r1@64],r2\r
+       vld1.32 {d0,d1},[r2]\r
+       vld1.32 {d0,d1},[r2]!\r
+       vld1.32 {d0,d1},[r2],16\r
+       vld1.32 {d0,d1},[r2],r3\r
+       vld1.32 {d0,d1},[r2@64]\r
+       vld1.32 {d0,d1},[r2@64]!\r
+       vld1.32 {d0,d1},[r2@64],16\r
+       vld1.32 {d0,d1},[r2@64],r3\r
+       vld1.32 {d0,d1,d2},[r3]\r
+       vld1.32 {d0,d1,d2},[r3]!\r
+       vld1.32 {d0,d1,d2},[r3],24\r
+       vld1.32 {d0,d1,d2},[r3],r4\r
+       vld1.32 {d0,d1,d2},[r3@64]\r
+       vld1.32 {d0,d1,d2},[r3@64]!\r
+       vld1.32 {d0,d1,d2},[r3@64],24\r
+       vld1.32 {d0,d1,d2},[r3@64],r4\r
+       vld1.32 {d0,d1,d2,d3},[r4]\r
+       vld1.32 {d0,d1,d2,d3},[r4]!\r
+       vld1.32 {d0,d1,d2,d3},[r4],32\r
+       vld1.32 {d0,d1,d2,d3},[r4],r5\r
+       vld1.32 {d0,d1,d2,d3},[r4@64]\r
+       vld1.32 {d0,d1,d2,d3},[r4@64]!\r
+       vld1.32 {d0,d1,d2,d3},[r4@64],32\r
+       vld1.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vld1.32 {d0[1]},[r2]\r
+       vld1.32 {d0[1]},[r2]!\r
+       vld1.32 {d0[1]},[r2],4\r
+       vld1.32 {d0[1]},[r2],r3\r
+       vld1.32 {d0[1]},[r2@32]\r
+       vld1.32 {d0[1]},[r2@32]!\r
+       vld1.32 {d0[1]},[r2@32],4\r
+       vld1.32 {d0[1]},[r2@32],r3\r
+       vld1.32 {d0[]},[r1]\r
+       vld1.32 {d0[]},[r1]!\r
+       vld1.32 {d0[]},[r1],4\r
+       vld1.32 {d0[]},[r1],r2\r
+       vld1.32 {d0[]},[r1@32]\r
+       vld1.32 {d0[]},[r1@32]!\r
+       vld1.32 {d0[]},[r1@32],4\r
+       vld1.32 {d0[]},[r1@32],r2\r
+       vld1.32 {d0[],d1[]},[r2]\r
+       vld1.32 {d0[],d1[]},[r2]!\r
+       vld1.32 {d0[],d1[]},[r2],4\r
+       vld1.32 {d0[],d1[]},[r2],r3\r
+       vld1.32 {d0[],d1[]},[r2@32]\r
+       vld1.32 {d0[],d1[]},[r2@32]!\r
+       vld1.32 {d0[],d1[]},[r2@32],4\r
+       vld1.32 {d0[],d1[]},[r2@32],r3\r
+\r
+       vld1.64 {d0},[r1]\r
+       vld1.64 {d0},[r1]!\r
+       vld1.64 {d0},[r1],8\r
+       vld1.64 {d0},[r1],r2\r
+       vld1.64 {d0},[r1@64]\r
+       vld1.64 {d0},[r1@64]!\r
+       vld1.64 {d0},[r1@64],8\r
+       vld1.64 {d0},[r1@64],r2\r
+       vld1.64 {d0,d1},[r2]\r
+       vld1.64 {d0,d1},[r2]!\r
+       vld1.64 {d0,d1},[r2],16\r
+       vld1.64 {d0,d1},[r2],r3\r
+       vld1.64 {d0,d1},[r2@64]\r
+       vld1.64 {d0,d1},[r2@64]!\r
+       vld1.64 {d0,d1},[r2@64],16\r
+       vld1.64 {d0,d1},[r2@64],r3\r
+       vld1.64 {d0,d1,d2},[r3]\r
+       vld1.64 {d0,d1,d2},[r3]!\r
+       vld1.64 {d0,d1,d2},[r3],24\r
+       vld1.64 {d0,d1,d2},[r3],r4\r
+       vld1.64 {d0,d1,d2},[r3@64]\r
+       vld1.64 {d0,d1,d2},[r3@64]!\r
+       vld1.64 {d0,d1,d2},[r3@64],24\r
+       vld1.64 {d0,d1,d2},[r3@64],r4\r
+       vld1.64 {d0,d1,d2,d3},[r4]\r
+       vld1.64 {d0,d1,d2,d3},[r4]!\r
+       vld1.64 {d0,d1,d2,d3},[r4],32\r
+       vld1.64 {d0,d1,d2,d3},[r4],r5\r
+       vld1.64 {d0,d1,d2,d3},[r4@64]\r
+       vld1.64 {d0,d1,d2,d3},[r4@64]!\r
+       vld1.64 {d0,d1,d2,d3},[r4@64],32\r
+       vld1.64 {d0,d1,d2,d3},[r4@64],r5\r
+\r
+       vld1.8  {d0},[r1]\r
+       vld1.8  {d0},[r1]!\r
+       vld1.8  {d0},[r1],8\r
+       vld1.8  {d0},[r1],r2\r
+       vld1.8  {d0},[r1@64]\r
+       vld1.8  {d0},[r1@64]!\r
+       vld1.8  {d0},[r1@64],8\r
+       vld1.8  {d0},[r1@64],r2\r
+       vld1.8  {d0,d1},[r2]\r
+       vld1.8  {d0,d1},[r2]!\r
+       vld1.8  {d0,d1},[r2],16\r
+       vld1.8  {d0,d1},[r2],r3\r
+       vld1.8  {d0,d1},[r2@64]\r
+       vld1.8  {d0,d1},[r2@64]!\r
+       vld1.8  {d0,d1},[r2@64],16\r
+       vld1.8  {d0,d1},[r2@64],r3\r
+       vld1.8  {d0,d1,d2},[r3]\r
+       vld1.8  {d0,d1,d2},[r3]!\r
+       vld1.8  {d0,d1,d2},[r3],24\r
+       vld1.8  {d0,d1,d2},[r3],r4\r
+       vld1.8  {d0,d1,d2},[r3@64]\r
+       vld1.8  {d0,d1,d2},[r3@64]!\r
+       vld1.8  {d0,d1,d2},[r3@64],24\r
+       vld1.8  {d0,d1,d2},[r3@64],r4\r
+       vld1.8  {d0,d1,d2,d3},[r4]\r
+       vld1.8  {d0,d1,d2,d3},[r4]!\r
+       vld1.8  {d0,d1,d2,d3},[r4],32\r
+       vld1.8  {d0,d1,d2,d3},[r4],r5\r
+       vld1.8  {d0,d1,d2,d3},[r4@64]\r
+       vld1.8  {d0,d1,d2,d3},[r4@64]!\r
+       vld1.8  {d0,d1,d2,d3},[r4@64],32\r
+       vld1.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vld1.8  {d0[1]},[r2]\r
+       vld1.8  {d0[1]},[r2]!\r
+       vld1.8  {d0[1]},[r2],1\r
+       vld1.8  {d0[1]},[r2],r3\r
+       vld1.8  {d0[]},[r1]\r
+       vld1.8  {d0[]},[r1]!\r
+       vld1.8  {d0[]},[r1],1\r
+       vld1.8  {d0[]},[r1],r2\r
+       vld1.8  {d0[],d1[]},[r2]\r
+       vld1.8  {d0[],d1[]},[r2]!\r
+       vld1.8  {d0[],d1[]},[r2],1\r
+       vld1.8  {d0[],d1[]},[r2],r3\r
+\r
+       vld2.16 {d0,d1},[r2]\r
+       vld2.16 {d0,d1},[r2]!\r
+       vld2.16 {d0,d1},[r2],16\r
+       vld2.16 {d0,d1},[r2],r3\r
+       vld2.16 {d0,d1},[r2@64]\r
+       vld2.16 {d0,d1},[r2@64]!\r
+       vld2.16 {d0,d1},[r2@64],16\r
+       vld2.16 {d0,d1},[r2@64],r3\r
+       vld2.16 {d0,d2},[r3]\r
+       vld2.16 {d0,d2},[r3]!\r
+       vld2.16 {d0,d2},[r3],16\r
+       vld2.16 {d0,d2},[r3],r4\r
+       vld2.16 {d0,d2},[r3@64]\r
+       vld2.16 {d0,d2},[r3@64]!\r
+       vld2.16 {d0,d2},[r3@64],16\r
+       vld2.16 {d0,d2},[r3@64],r4\r
+       vld2.16 {d0,d1,d2,d3},[r4]\r
+       vld2.16 {d0,d1,d2,d3},[r4]!\r
+       vld2.16 {d0,d1,d2,d3},[r4],32\r
+       vld2.16 {d0,d1,d2,d3},[r4],r5\r
+       vld2.16 {d0,d1,d2,d3},[r4@64]\r
+       vld2.16 {d0,d1,d2,d3},[r4@64]!\r
+       vld2.16 {d0,d1,d2,d3},[r4@64],32\r
+       vld2.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vld2.16 {d0[1],d1[1]},[r2]\r
+       vld2.16 {d0[1],d1[1]},[r2]!\r
+       vld2.16 {d0[1],d1[1]},[r2],4\r
+       vld2.16 {d0[1],d1[1]},[r2],r3\r
+       vld2.16 {d0[1],d1[1]},[r2@32]\r
+       vld2.16 {d0[1],d1[1]},[r2@32]!\r
+       vld2.16 {d0[1],d1[1]},[r2@32],4\r
+       vld2.16 {d0[1],d1[1]},[r2@32],r3\r
+       vld2.16 {d0[1],d2[1]},[r2]\r
+       vld2.16 {d0[1],d2[1]},[r2]!\r
+       vld2.16 {d0[1],d2[1]},[r2],4\r
+       vld2.16 {d0[1],d2[1]},[r2],r3\r
+       vld2.16 {d0[1],d2[1]},[r2@32]\r
+       vld2.16 {d0[1],d2[1]},[r2@32]!\r
+       vld2.16 {d0[1],d2[1]},[r2@32],4\r
+       vld2.16 {d0[1],d2[1]},[r2@32],r3\r
+       vld2.16 {d0[],d1[]},[r2]\r
+       vld2.16 {d0[],d1[]},[r2]!\r
+       vld2.16 {d0[],d1[]},[r2],4\r
+       vld2.16 {d0[],d1[]},[r2],r3\r
+       vld2.16 {d0[],d1[]},[r2@32]\r
+       vld2.16 {d0[],d1[]},[r2@32]!\r
+       vld2.16 {d0[],d1[]},[r2@32],4\r
+       vld2.16 {d0[],d1[]},[r2@32],r3\r
+       vld2.16 {d0[],d2[]},[r2]\r
+       vld2.16 {d0[],d2[]},[r2]!\r
+       vld2.16 {d0[],d2[]},[r2],4\r
+       vld2.16 {d0[],d2[]},[r2],r3\r
+       vld2.16 {d0[],d2[]},[r2@32]\r
+       vld2.16 {d0[],d2[]},[r2@32]!\r
+       vld2.16 {d0[],d2[]},[r2@32],4\r
+       vld2.16 {d0[],d2[]},[r2@32],r3\r
+\r
+       vld2.32 {d0,d1},[r2]\r
+       vld2.32 {d0,d1},[r2]!\r
+       vld2.32 {d0,d1},[r2],16\r
+       vld2.32 {d0,d1},[r2],r3\r
+       vld2.32 {d0,d1},[r2@64]\r
+       vld2.32 {d0,d1},[r2@64]!\r
+       vld2.32 {d0,d1},[r2@64],16\r
+       vld2.32 {d0,d1},[r2@64],r3\r
+       vld2.32 {d0,d2},[r3]\r
+       vld2.32 {d0,d2},[r3]!\r
+       vld2.32 {d0,d2},[r3],16\r
+       vld2.32 {d0,d2},[r3],r4\r
+       vld2.32 {d0,d2},[r3@64]\r
+       vld2.32 {d0,d2},[r3@64]!\r
+       vld2.32 {d0,d2},[r3@64],16\r
+       vld2.32 {d0,d2},[r3@64],r4\r
+       vld2.32 {d0,d1,d2,d3},[r4]\r
+       vld2.32 {d0,d1,d2,d3},[r4]!\r
+       vld2.32 {d0,d1,d2,d3},[r4],32\r
+       vld2.32 {d0,d1,d2,d3},[r4],r5\r
+       vld2.32 {d0,d1,d2,d3},[r4@64]\r
+       vld2.32 {d0,d1,d2,d3},[r4@64]!\r
+       vld2.32 {d0,d1,d2,d3},[r4@64],32\r
+       vld2.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vld2.32 {d0[1],d1[1]},[r2]\r
+       vld2.32 {d0[1],d1[1]},[r2]!\r
+       vld2.32 {d0[1],d1[1]},[r2],8\r
+       vld2.32 {d0[1],d1[1]},[r2],r3\r
+       vld2.32 {d0[1],d1[1]},[r2@64]\r
+       vld2.32 {d0[1],d1[1]},[r2@64]!\r
+       vld2.32 {d0[1],d1[1]},[r2@64],8\r
+       vld2.32 {d0[1],d1[1]},[r2@64],r3\r
+       vld2.32 {d0[1],d2[1]},[r2]\r
+       vld2.32 {d0[1],d2[1]},[r2]!\r
+       vld2.32 {d0[1],d2[1]},[r2],8\r
+       vld2.32 {d0[1],d2[1]},[r2],r3\r
+       vld2.32 {d0[1],d2[1]},[r2@64]\r
+       vld2.32 {d0[1],d2[1]},[r2@64]!\r
+       vld2.32 {d0[1],d2[1]},[r2@64],8\r
+       vld2.32 {d0[1],d2[1]},[r2@64],r3\r
+       vld2.32 {d0[],d1[]},[r2]\r
+       vld2.32 {d0[],d1[]},[r2]!\r
+       vld2.32 {d0[],d1[]},[r2],8\r
+       vld2.32 {d0[],d1[]},[r2],r3\r
+       vld2.32 {d0[],d1[]},[r2@64]\r
+       vld2.32 {d0[],d1[]},[r2@64]!\r
+       vld2.32 {d0[],d1[]},[r2@64],8\r
+       vld2.32 {d0[],d1[]},[r2@64],r3\r
+       vld2.32 {d0[],d2[]},[r2]\r
+       vld2.32 {d0[],d2[]},[r2]!\r
+       vld2.32 {d0[],d2[]},[r2],8\r
+       vld2.32 {d0[],d2[]},[r2],r3\r
+       vld2.32 {d0[],d2[]},[r2@64]\r
+       vld2.32 {d0[],d2[]},[r2@64]!\r
+       vld2.32 {d0[],d2[]},[r2@64],8\r
+       vld2.32 {d0[],d2[]},[r2@64],r3\r
+\r
+       vld2.8  {d0,d1},[r2]\r
+       vld2.8  {d0,d1},[r2]!\r
+       vld2.8  {d0,d1},[r2],16\r
+       vld2.8  {d0,d1},[r2],r3\r
+       vld2.8  {d0,d1},[r2@64]\r
+       vld2.8  {d0,d1},[r2@64]!\r
+       vld2.8  {d0,d1},[r2@64],16\r
+       vld2.8  {d0,d1},[r2@64],r3\r
+       vld2.8  {d0,d2},[r3]\r
+       vld2.8  {d0,d2},[r3]!\r
+       vld2.8  {d0,d2},[r3],16\r
+       vld2.8  {d0,d2},[r3],r4\r
+       vld2.8  {d0,d2},[r3@64]\r
+       vld2.8  {d0,d2},[r3@64]!\r
+       vld2.8  {d0,d2},[r3@64],16\r
+       vld2.8  {d0,d2},[r3@64],r4\r
+       vld2.8  {d0,d1,d2,d3},[r4]\r
+       vld2.8  {d0,d1,d2,d3},[r4]!\r
+       vld2.8  {d0,d1,d2,d3},[r4],32\r
+       vld2.8  {d0,d1,d2,d3},[r4],r5\r
+       vld2.8  {d0,d1,d2,d3},[r4@64]\r
+       vld2.8  {d0,d1,d2,d3},[r4@64]!\r
+       vld2.8  {d0,d1,d2,d3},[r4@64],32\r
+       vld2.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vld2.8  {d0[1],d1[1]},[r2]\r
+       vld2.8  {d0[1],d1[1]},[r2]!\r
+       vld2.8  {d0[1],d1[1]},[r2],2\r
+       vld2.8  {d0[1],d1[1]},[r2],r3\r
+       vld2.8  {d0[1],d1[1]},[r2@16]\r
+       vld2.8  {d0[1],d1[1]},[r2@16]!\r
+       vld2.8  {d0[1],d1[1]},[r2@16],2\r
+       vld2.8  {d0[1],d1[1]},[r2@16],r3\r
+       vld2.8  {d0[],d1[]},[r2]\r
+       vld2.8  {d0[],d1[]},[r2]!\r
+       vld2.8  {d0[],d1[]},[r2],2\r
+       vld2.8  {d0[],d1[]},[r2],r3\r
+       vld2.8  {d0[],d1[]},[r2@16]\r
+       vld2.8  {d0[],d1[]},[r2@16]!\r
+       vld2.8  {d0[],d1[]},[r2@16],2\r
+       vld2.8  {d0[],d1[]},[r2@16],r3\r
+       vld2.8  {d0[],d2[]},[r2]\r
+       vld2.8  {d0[],d2[]},[r2]!\r
+       vld2.8  {d0[],d2[]},[r2],2\r
+       vld2.8  {d0[],d2[]},[r2],r3\r
+       vld2.8  {d0[],d2[]},[r2@16]\r
+       vld2.8  {d0[],d2[]},[r2@16]!\r
+       vld2.8  {d0[],d2[]},[r2@16],2\r
+       vld2.8  {d0[],d2[]},[r2@16],r3\r
+\r
+       vld3.16 {d0,d1,d2},[r2]\r
+       vld3.16 {d0,d1,d2},[r2]!\r
+       vld3.16 {d0,d1,d2},[r2],24\r
+       vld3.16 {d0,d1,d2},[r2],r3\r
+       vld3.16 {d0,d1,d2},[r2@64]\r
+       vld3.16 {d0,d1,d2},[r2@64]!\r
+       vld3.16 {d0,d1,d2},[r2@64],24\r
+       vld3.16 {d0,d1,d2},[r2@64],r3\r
+       vld3.16 {d0,d2,d4},[r3]\r
+       vld3.16 {d0,d2,d4},[r3]!\r
+       vld3.16 {d0,d2,d4},[r3],24\r
+       vld3.16 {d0,d2,d4},[r3],r4\r
+       vld3.16 {d0,d2,d4},[r3@64]\r
+       vld3.16 {d0,d2,d4},[r3@64]!\r
+       vld3.16 {d0,d2,d4},[r3@64],24\r
+       vld3.16 {d0,d2,d4},[r3@64],r4\r
+       vld3.16 {d0[1],d1[1],d2[1]},[r2]\r
+       vld3.16 {d0[1],d1[1],d2[1]},[r2]!\r
+       vld3.16 {d0[1],d1[1],d2[1]},[r2],6\r
+       vld3.16 {d0[1],d1[1],d2[1]},[r2],r3\r
+       vld3.16 {d0[1],d2[1],d4[1]},[r2]\r
+       vld3.16 {d0[1],d2[1],d4[1]},[r2]!\r
+       vld3.16 {d0[1],d2[1],d4[1]},[r2],6\r
+       vld3.16 {d0[1],d2[1],d4[1]},[r2],r3\r
+       vld3.16 {d0[],d1[],d2[]},[r2]\r
+       vld3.16 {d0[],d1[],d2[]},[r2]!\r
+       vld3.16 {d0[],d1[],d2[]},[r2],6\r
+       vld3.16 {d0[],d1[],d2[]},[r2],r3\r
+       vld3.16 {d0[],d2[],d4[]},[r2]\r
+       vld3.16 {d0[],d2[],d4[]},[r2]!\r
+       vld3.16 {d0[],d2[],d4[]},[r2],6\r
+       vld3.16 {d0[],d2[],d4[]},[r2],r3\r
+\r
+       vld3.32 {d0,d1,d2},[r2]\r
+       vld3.32 {d0,d1,d2},[r2]!\r
+       vld3.32 {d0,d1,d2},[r2],24\r
+       vld3.32 {d0,d1,d2},[r2],r3\r
+       vld3.32 {d0,d1,d2},[r2@64]\r
+       vld3.32 {d0,d1,d2},[r2@64]!\r
+       vld3.32 {d0,d1,d2},[r2@64],24\r
+       vld3.32 {d0,d1,d2},[r2@64],r3\r
+       vld3.32 {d0,d2,d4},[r3]\r
+       vld3.32 {d0,d2,d4},[r3]!\r
+       vld3.32 {d0,d2,d4},[r3],24\r
+       vld3.32 {d0,d2,d4},[r3],r4\r
+       vld3.32 {d0,d2,d4},[r3@64]\r
+       vld3.32 {d0,d2,d4},[r3@64]!\r
+       vld3.32 {d0,d2,d4},[r3@64],24\r
+       vld3.32 {d0,d2,d4},[r3@64],r4\r
+       vld3.32 {d0[1],d1[1],d2[1]},[r2]\r
+       vld3.32 {d0[1],d1[1],d2[1]},[r2]!\r
+       vld3.32 {d0[1],d1[1],d2[1]},[r2],12\r
+       vld3.32 {d0[1],d1[1],d2[1]},[r2],r3\r
+       vld3.32 {d0[1],d2[1],d4[1]},[r2]\r
+       vld3.32 {d0[1],d2[1],d4[1]},[r2]!\r
+       vld3.32 {d0[1],d2[1],d4[1]},[r2],12\r
+       vld3.32 {d0[1],d2[1],d4[1]},[r2],r3\r
+       vld3.32 {d0[],d1[],d2[]},[r2]\r
+       vld3.32 {d0[],d1[],d2[]},[r2]!\r
+       vld3.32 {d0[],d1[],d2[]},[r2],12\r
+       vld3.32 {d0[],d1[],d2[]},[r2],r3\r
+       vld3.32 {d0[],d2[],d4[]},[r2]\r
+       vld3.32 {d0[],d2[],d4[]},[r2]!\r
+       vld3.32 {d0[],d2[],d4[]},[r2],12\r
+       vld3.32 {d0[],d2[],d4[]},[r2],r3\r
+\r
+       vld3.8  {d0,d1,d2},[r2]\r
+       vld3.8  {d0,d1,d2},[r2]!\r
+       vld3.8  {d0,d1,d2},[r2],24\r
+       vld3.8  {d0,d1,d2},[r2],r3\r
+       vld3.8  {d0,d1,d2},[r2@64]\r
+       vld3.8  {d0,d1,d2},[r2@64]!\r
+       vld3.8  {d0,d1,d2},[r2@64],24\r
+       vld3.8  {d0,d1,d2},[r2@64],r3\r
+       vld3.8  {d0,d2,d4},[r3]\r
+       vld3.8  {d0,d2,d4},[r3]!\r
+       vld3.8  {d0,d2,d4},[r3],24\r
+       vld3.8  {d0,d2,d4},[r3],r4\r
+       vld3.8  {d0,d2,d4},[r3@64]\r
+       vld3.8  {d0,d2,d4},[r3@64]!\r
+       vld3.8  {d0,d2,d4},[r3@64],24\r
+       vld3.8  {d0,d2,d4},[r3@64],r4\r
+       vld3.8  {d0[1],d1[1],d2[1]},[r2]\r
+       vld3.8  {d0[1],d1[1],d2[1]},[r2]!\r
+       vld3.8  {d0[1],d1[1],d2[1]},[r2],3\r
+       vld3.8  {d0[1],d1[1],d2[1]},[r2],r3\r
+       vld3.8  {d0[],d1[],d2[]},[r2]\r
+       vld3.8  {d0[],d1[],d2[]},[r2]!\r
+       vld3.8  {d0[],d1[],d2[]},[r2],3\r
+       vld3.8  {d0[],d1[],d2[]},[r2],r3\r
+       vld3.8  {d0[],d2[],d4[]},[r2]\r
+       vld3.8  {d0[],d2[],d4[]},[r2]!\r
+       vld3.8  {d0[],d2[],d4[]},[r2],3\r
+       vld3.8  {d0[],d2[],d4[]},[r2],r3\r
+\r
+       vld4.16 {d0,d1,d2,d3},[r4]\r
+       vld4.16 {d0,d1,d2,d3},[r4]!\r
+       vld4.16 {d0,d1,d2,d3},[r4],32\r
+       vld4.16 {d0,d1,d2,d3},[r4],r5\r
+       vld4.16 {d0,d1,d2,d3},[r4@64]\r
+       vld4.16 {d0,d1,d2,d3},[r4@64]!\r
+       vld4.16 {d0,d1,d2,d3},[r4@64],32\r
+       vld4.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vld4.16 {d0,d2,d4,d6},[r4]\r
+       vld4.16 {d0,d2,d4,d6},[r4]!\r
+       vld4.16 {d0,d2,d4,d6},[r4],32\r
+       vld4.16 {d0,d2,d4,d6},[r4],r5\r
+       vld4.16 {d0,d2,d4,d6},[r4@64]\r
+       vld4.16 {d0,d2,d4,d6},[r4@64]!\r
+       vld4.16 {d0,d2,d4,d6},[r4@64],32\r
+       vld4.16 {d0,d2,d4,d6},[r4@64],r5\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],8\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]!\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],8\r
+       vld4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]!\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],8\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],r3\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]!\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],8\r
+       vld4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2]\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2]!\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2],8\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2],r3\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2@64]\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2@64]!\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2@64],8\r
+       vld4.16 {d0[],d1[],d2[],d3[]},[r2@64],r3\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2]\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2]!\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2],8\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2],r3\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2@64]\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2@64]!\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2@64],8\r
+       vld4.16 {d0[],d2[],d4[],d6[]},[r2@64],r3\r
+\r
+       vld4.32 {d0,d1,d2,d3},[r4]\r
+       vld4.32 {d0,d1,d2,d3},[r4]!\r
+       vld4.32 {d0,d1,d2,d3},[r4],32\r
+       vld4.32 {d0,d1,d2,d3},[r4],r5\r
+       vld4.32 {d0,d1,d2,d3},[r4@64]\r
+       vld4.32 {d0,d1,d2,d3},[r4@64]!\r
+       vld4.32 {d0,d1,d2,d3},[r4@64],32\r
+       vld4.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vld4.32 {d0,d2,d4,d6},[r4]\r
+       vld4.32 {d0,d2,d4,d6},[r4]!\r
+       vld4.32 {d0,d2,d4,d6},[r4],32\r
+       vld4.32 {d0,d2,d4,d6},[r4],r5\r
+       vld4.32 {d0,d2,d4,d6},[r4@64]\r
+       vld4.32 {d0,d2,d4,d6},[r4@64]!\r
+       vld4.32 {d0,d2,d4,d6},[r4@64],32\r
+       vld4.32 {d0,d2,d4,d6},[r4@64],r5\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],16\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]!\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],16\r
+       vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]!\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],16\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],r3\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]!\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],16\r
+       vld4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2]\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2]!\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2],16\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2],r3\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2@64]\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2@64]!\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2@64],16\r
+       vld4.32 {d0[],d1[],d2[],d3[]},[r2@64],r3\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2]\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2]!\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2],16\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2],r3\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2@64]\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2@64]!\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2@64],16\r
+       vld4.32 {d0[],d2[],d4[],d6[]},[r2@64],r3\r
+\r
+       vld4.8  {d0,d1,d2,d3},[r4]\r
+       vld4.8  {d0,d1,d2,d3},[r4]!\r
+       vld4.8  {d0,d1,d2,d3},[r4],32\r
+       vld4.8  {d0,d1,d2,d3},[r4],r5\r
+       vld4.8  {d0,d1,d2,d3},[r4@64]\r
+       vld4.8  {d0,d1,d2,d3},[r4@64]!\r
+       vld4.8  {d0,d1,d2,d3},[r4@64],32\r
+       vld4.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vld4.8  {d0,d2,d4,d6},[r4]\r
+       vld4.8  {d0,d2,d4,d6},[r4]!\r
+       vld4.8  {d0,d2,d4,d6},[r4],32\r
+       vld4.8  {d0,d2,d4,d6},[r4],r5\r
+       vld4.8  {d0,d2,d4,d6},[r4@64]\r
+       vld4.8  {d0,d2,d4,d6},[r4@64]!\r
+       vld4.8  {d0,d2,d4,d6},[r4@64],32\r
+       vld4.8  {d0,d2,d4,d6},[r4@64],r5\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2],4\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32]\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32]!\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32],4\r
+       vld4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32],r3\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2]\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2]!\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2],4\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2],r3\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2@32]\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2@32]!\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2@32],4\r
+       vld4.8  {d0[],d1[],d2[],d3[]},[r2@32],r3\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2]\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2]!\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2],4\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2],r3\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2@32]\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2@32]!\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2@32],4\r
+       vld4.8  {d0[],d2[],d4[],d6[]},[r2@32],r3\r
+\r
+       vmax.s16        d0,d1\r
+       vmax.s16        d0,d1,d2\r
+       vmax.s16        q0,q1\r
+       vmax.s16        q0,q1,q2\r
+\r
+       vmax.s32        d0,d1\r
+       vmax.s32        d0,d1,d2\r
+       vmax.s32        q0,q1\r
+       vmax.s32        q0,q1,q2\r
+\r
+       vmax.s8 d0,d1\r
+       vmax.s8 d0,d1,d2\r
+       vmax.s8 q0,q1\r
+       vmax.s8 q0,q1,q2\r
+\r
+       vmax.u16        d0,d1\r
+       vmax.u16        d0,d1,d2\r
+       vmax.u16        q0,q1\r
+       vmax.u16        q0,q1,q2\r
+\r
+       vmax.u32        d0,d1\r
+       vmax.u32        d0,d1,d2\r
+       vmax.u32        q0,q1\r
+       vmax.u32        q0,q1,q2\r
+\r
+       vmax.u8 d0,d1\r
+       vmax.u8 d0,d1,d2\r
+       vmax.u8 q0,q1\r
+       vmax.u8 q0,q1,q2\r
+\r
+       vmin.s16        d0,d1\r
+       vmin.s16        d0,d1,d2\r
+       vmin.s16        q0,q1\r
+       vmin.s16        q0,q1,q2\r
+\r
+       vmin.s32        d0,d1\r
+       vmin.s32        d0,d1,d2\r
+       vmin.s32        q0,q1\r
+       vmin.s32        q0,q1,q2\r
+\r
+       vmin.s8 d0,d1\r
+       vmin.s8 d0,d1,d2\r
+       vmin.s8 q0,q1\r
+       vmin.s8 q0,q1,q2\r
+\r
+       vmin.u16        d0,d1\r
+       vmin.u16        d0,d1,d2\r
+       vmin.u16        q0,q1\r
+       vmin.u16        q0,q1,q2\r
+\r
+       vmin.u32        d0,d1\r
+       vmin.u32        d0,d1,d2\r
+       vmin.u32        q0,q1\r
+       vmin.u32        q0,q1,q2\r
+\r
+       vmin.u8 d0,d1\r
+       vmin.u8 d0,d1,d2\r
+       vmin.u8 q0,q1\r
+       vmin.u8 q0,q1,q2\r
+\r
+       vmla.i16        d0,d1,d2\r
+       vmla.i16        d0,d1,d2[0]\r
+       vmla.i16        q0,q1,q2\r
+       vmla.i16        q0,q1,d2[1]\r
+\r
+       vmla.i32        d0,d1,d2\r
+       vmla.i32        d0,d1,d2[0]\r
+       vmla.i32        q0,q1,q2\r
+       vmla.i32        q0,q1,d2[1]\r
+\r
+       vmla.i8 d0,d1,d2\r
+       vmla.i8 q0,q1,q2\r
+\r
+       vmla.s16        d0,d1,d2\r
+       vmla.s16        q0,q1,q2\r
+\r
+       vmla.s32        d0,d1,d2\r
+       vmla.s32        q0,q1,q2\r
+\r
+       vmla.s8 d0,d1,d2\r
+       vmla.s8 q0,q1,q2\r
+\r
+       vmla.u16        d0,d1,d2\r
+       vmla.u16        q0,q1,q2\r
+\r
+       vmla.u32        d0,d1,d2\r
+       vmla.u32        q0,q1,q2\r
+\r
+       vmla.u8 d0,d1,d2\r
+       vmla.u8 q0,q1,q2\r
+\r
+       vmlal.s16       q0,d1,d2\r
+       vmlal.s16       q0,d1,d2[0]\r
+\r
+       vmlal.s32       q0,d1,d2\r
+       vmlal.s32       q0,d1,d2[0]\r
+\r
+       vmlal.s8        q0,d1,d2\r
+\r
+       vmlal.u16       q0,d1,d2\r
+       vmlal.u16       q0,d1,d2[1]\r
+\r
+       vmlal.u32       q0,d1,d2\r
+       vmlal.u32       q0,d1,d2[0]\r
+\r
+       vmlal.u8        q0,d1,d2\r
+\r
+       vmls.i16        d0,d1,d2\r
+       vmls.i16        d0,d1,d2[0]\r
+       vmls.i16        q0,q1,q2\r
+       vmls.i16        q0,q1,d2[1]\r
+\r
+       vmls.i32        d0,d1,d2\r
+       vmls.i32        d0,d1,d2[0]\r
+       vmls.i32        q0,q1,q2\r
+       vmls.i32        q0,q1,d2[1]\r
+\r
+       vmls.i8 d0,d1,d2\r
+       vmls.i8 q0,q1,q2\r
+\r
+       vmls.s16        d0,d1,d2\r
+       vmls.s16        q0,q1,q2\r
+\r
+       vmls.s32        d0,d1,d2\r
+       vmls.s32        q0,q1,q2\r
+\r
+       vmls.s8 d0,d1,d2\r
+       vmls.s8 q0,q1,q2\r
+\r
+       vmls.u16        d0,d1,d2\r
+       vmls.u16        q0,q1,q2\r
+\r
+       vmls.u32        d0,d1,d2\r
+       vmls.u32        q0,q1,q2\r
+\r
+       vmls.u8 d0,d1,d2\r
+       vmls.u8 q0,q1,q2\r
+\r
+       vmlsl.s16       q0,d1,d2\r
+       vmlsl.s16       q0,d1,d2[1]\r
+\r
+       vmlsl.s32       q0,d1,d2\r
+       vmlsl.s32       q0,d1,d2[0]\r
+\r
+       vmlsl.s8        q0,d1,d2\r
+\r
+       vmlsl.u16       q0,d1,d2\r
+       vmlsl.u16       q0,d1,d2[1]\r
+\r
+       vmlsl.u32       q0,d1,d2\r
+       vmlsl.u32       q0,d1,d2[0]\r
+\r
+       vmlsl.u8        q0,d1,d2\r
+\r
+       vmov    d0,d1\r
+       vmov    q0,q1\r
+\r
+       vmov.16 d0[1],r1\r
+\r
+       vmov.8  d0[1],r1\r
+\r
+       vmov.i16        d0,1\r
+       vmov.i16        q0,1\r
+\r
+       vmov.i32        d0,1\r
+       vmov.i32        q0,1\r
+\r
+       vmov.i64        d0,1\r
+       vmov.i64        q0,1\r
+\r
+       vmov.i8 d0,1\r
+       vmov.i8 q0,1\r
+\r
+       vmov.s16        r0,d1[1]\r
+\r
+       vmov.s8 r0,d1[1]\r
+\r
+       vmov.u16        r0,d1[1]\r
+\r
+       vmov.u8 r0,d1[1]\r
+\r
+       vmovl.s16       q0,d1\r
+\r
+       vmovl.s32       q0,d1\r
+\r
+       vmovl.s8        q0,d1\r
+\r
+       vmovl.u16       q0,d1\r
+\r
+       vmovl.u32       q0,d1\r
+\r
+       vmovl.u8        q0,d1\r
+\r
+       vmovn.i16       d0,q1\r
+\r
+       vmovn.i32       d0,q1\r
+\r
+       vmovn.i8        d0,q1\r
+\r
+       vmul.i16        d0,d1\r
+       vmul.i16        d0,d1,d2\r
+       vmul.i16        d0,d1[1]\r
+       vmul.i16        d0,d1,d2[1]\r
+       vmul.i16        q0,q1\r
+       vmul.i16        q0,q1,q2\r
+       vmul.i16        q0,d1[1]\r
+       vmul.i16        q0,q1,d2[1]\r
+\r
+       vmul.i32        d0,d1\r
+       vmul.i32        d0,d1,d2\r
+       vmul.i32        d0,d1[0]\r
+       vmul.i32        d0,d1,d2[0]\r
+       vmul.i32        q0,q1\r
+       vmul.i32        q0,q1,q2\r
+       vmul.i32        q0,d1[0]\r
+       vmul.i32        q0,q1,d2[0]\r
+\r
+       vmul.i8 d0,d1\r
+       vmul.i8 d0,d1,d2\r
+       vmul.i8 q0,q1\r
+       vmul.i8 q0,q1,q2\r
+\r
+       vmul.p8 d0,d1\r
+       vmul.p8 d0,d1,d2\r
+\r
+       vmul.s16        d0,d1\r
+       vmul.s16        d0,d1,d2\r
+\r
+       vmul.s32        d0,d1\r
+       vmul.s32        d0,d1,d2\r
+\r
+       vmul.s8 d0,d1\r
+       vmul.s8 d0,d1,d2\r
+       vmul.s8 q0,q1\r
+       vmul.s8 q0,q1,q2\r
+\r
+       vmul.u16        d0,d1\r
+       vmul.u16        d0,d1,d2\r
+\r
+       vmul.u32        d0,d1\r
+       vmul.u32        d0,d1,d2\r
+\r
+       vmul.u8 d0,d1\r
+       vmul.u8 d0,d1,d2\r
+       vmul.u8 q0,q1\r
+       vmul.u8 q0,q1,q2\r
+\r
+       vmull.p8        q0,d1,d2\r
+\r
+       vmull.s16       q0,d1,d2\r
+       vmull.s16       q0,d1,d2[0]\r
+\r
+       vmull.s32       q0,d1,d2\r
+       vmull.s32       q0,d1,d2[0]\r
+\r
+       vmull.s8        q0,d1,d2\r
+\r
+       vmull.u16       q0,d1,d2\r
+       vmull.u16       q0,d1,d2[1]\r
+\r
+       vmull.u32       q0,d1,d2\r
+       vmull.u32       q0,d1,d2[0]\r
+\r
+       vmull.u8        q0,d1,d2\r
+\r
+       vmvn    d0,d1\r
+       vmvn    q0,q1\r
+\r
+       vmvn.i16        d0,1\r
+       vmvn.i16        q0,1\r
+\r
+       vmvn.i32        d0,1\r
+       vmvn.i32        q0,1\r
+\r
+       vneg.s16        d0,d1\r
+       vneg.s16        q0,q1\r
+\r
+       vneg.s32        d0,d1\r
+       vneg.s32        q0,q1\r
+\r
+       vneg.s8 d0,d1\r
+       vneg.s8 q0,q1\r
+\r
+       vorn    d0,d1\r
+       vorn    d0,d1,d2\r
+       vorn    q0,q1\r
+       vorn    q0,q1,q2\r
+\r
+       vorn.i16        d0,not 1\r
+       vorn.i16        q0,0xfffe\r
+\r
+       vorn.i32        d0,not 1\r
+       vorn.i32        q0,not 1\r
+\r
+       vorr    d0,d1\r
+       vorr    d0,d1,d2\r
+       vorr    q0,q1\r
+       vorr    q0,q1,q2\r
+\r
+       vorr.i16        d0,1\r
+       vorr.i16        q0,not -2\r
+\r
+       vorr.i32        d0,1\r
+       vorr.i32        q0,1\r
+\r
+       vpadal.s16      d0,d1\r
+       vpadal.s16      q0,q1\r
+\r
+       vpadal.s32      d0,d1\r
+       vpadal.s32      q0,q1\r
+\r
+       vpadal.s8       d0,d1\r
+       vpadal.s8       q0,q1\r
+\r
+       vpadal.u16      d0,d1\r
+       vpadal.u16      q0,q1\r
+\r
+       vpadal.u32      d0,d1\r
+       vpadal.u32      q0,q1\r
+\r
+       vpadal.u8       d0,d1\r
+       vpadal.u8       q0,q1\r
+\r
+       vpadd.i16       d0,d1\r
+       vpadd.i16       d0,d1,d2\r
+\r
+       vpadd.i32       d0,d1\r
+       vpadd.i32       d0,d1,d2\r
+\r
+       vpadd.i8        d0,d1\r
+       vpadd.i8        d0,d1,d2\r
+\r
+       vpaddl.s16      d0,d1\r
+       vpaddl.s16      q0,q1\r
+\r
+       vpaddl.s32      d0,d1\r
+       vpaddl.s32      q0,q1\r
+\r
+       vpaddl.s8       d0,d1\r
+       vpaddl.s8       q0,q1\r
+\r
+       vpaddl.u16      d0,d1\r
+       vpaddl.u16      q0,q1\r
+\r
+       vpaddl.u32      d0,d1\r
+       vpaddl.u32      q0,q1\r
+\r
+       vpaddl.u8       d0,d1\r
+       vpaddl.u8       q0,q1\r
+\r
+       vpmax.s16       d0,d1\r
+       vpmax.s16       d0,d1,d2\r
+\r
+       vpmax.s32       d0,d1\r
+       vpmax.s32       d0,d1,d2\r
+\r
+       vpmax.s8        d0,d1\r
+       vpmax.s8        d0,d1,d2\r
+\r
+       vpmax.u16       d0,d1\r
+       vpmax.u16       d0,d1,d2\r
+\r
+       vpmax.u32       d0,d1\r
+       vpmax.u32       d0,d1,d2\r
+\r
+       vpmax.u8        d0,d1\r
+       vpmax.u8        d0,d1,d2\r
+\r
+       vpmin.s16       d0,d1\r
+       vpmin.s16       d0,d1,d2\r
+\r
+       vpmin.s32       d0,d1\r
+       vpmin.s32       d0,d1,d2\r
+\r
+       vpmin.s8        d0,d1\r
+       vpmin.s8        d0,d1,d2\r
+\r
+       vpmin.u16       d0,d1\r
+       vpmin.u16       d0,d1,d2\r
+\r
+       vpmin.u32       d0,d1\r
+       vpmin.u32       d0,d1,d2\r
+\r
+       vpmin.u8        d0,d1\r
+       vpmin.u8        d0,d1,d2\r
+\r
+       vqabs.s16       d0,d1\r
+       vqabs.s16       q0,q1\r
+\r
+       vqabs.s32       d0,d1\r
+       vqabs.s32       q0,q1\r
+\r
+       vqabs.s8        d0,d1\r
+       vqabs.s8        q0,q1\r
+\r
+       vqadd.s16       d0,d1\r
+       vqadd.s16       d0,d1,d2\r
+       vqadd.s16       q0,q1\r
+       vqadd.s16       q0,q1,q2\r
+\r
+       vqadd.s32       d0,d1\r
+       vqadd.s32       d0,d1,d2\r
+       vqadd.s32       q0,q1\r
+       vqadd.s32       q0,q1,q2\r
+\r
+       vqadd.s64       d0,d1\r
+       vqadd.s64       d0,d1,d2\r
+       vqadd.s64       q0,q1\r
+       vqadd.s64       q0,q1,q2\r
+\r
+       vqadd.s8        d0,d1\r
+       vqadd.s8        d0,d1,d2\r
+       vqadd.s8        q0,q1\r
+       vqadd.s8        q0,q1,q2\r
+\r
+       vqadd.u16       d0,d1\r
+       vqadd.u16       d0,d1,d2\r
+       vqadd.u16       q0,q1\r
+       vqadd.u16       q0,q1,q2\r
+\r
+       vqadd.u32       d0,d1\r
+       vqadd.u32       d0,d1,d2\r
+       vqadd.u32       q0,q1\r
+       vqadd.u32       q0,q1,q2\r
+\r
+       vqadd.u64       d0,d1\r
+       vqadd.u64       d0,d1,d2\r
+       vqadd.u64       q0,q1\r
+       vqadd.u64       q0,q1,q2\r
+\r
+       vqadd.u8        d0,d1\r
+       vqadd.u8        d0,d1,d2\r
+       vqadd.u8        q0,q1\r
+       vqadd.u8        q0,q1,q2\r
+\r
+       vqdmlal.s16     q0,d1,d2\r
+       vqdmlal.s16     q0,d1,d2[0]\r
+\r
+       vqdmlal.s32     q0,d1,d2\r
+       vqdmlal.s32     q0,d1,d2[0]\r
+\r
+       vqdmlsl.s16     q0,d1,d2\r
+       vqdmlsl.s16     q0,d1,d2[0]\r
+\r
+       vqdmlsl.s32     q0,d1,d2\r
+       vqdmlsl.s32     q0,d1,d2[0]\r
+\r
+       vqdmulh.s16     d0,d1\r
+       vqdmulh.s16     d0,d1,d2\r
+       vqdmulh.s16     d0,d1[1]\r
+       vqdmulh.s16     d0,d1,d2[1]\r
+       vqdmulh.s16     q0,q1\r
+       vqdmulh.s16     q0,q1,q2\r
+       vqdmulh.s16     q0,d1[1]\r
+       vqdmulh.s16     q0,q1,d2[1]\r
+\r
+       vqdmulh.s32     d0,d1\r
+       vqdmulh.s32     d0,d1,d2\r
+       vqdmulh.s32     d0,d1[0]\r
+       vqdmulh.s32     d0,d1,d2[0]\r
+       vqdmulh.s32     q0,q1\r
+       vqdmulh.s32     q0,q1,q2\r
+       vqdmulh.s32     q0,d1[0]\r
+       vqdmulh.s32     q0,q1,d2[0]\r
+\r
+       vqdmull.s16     q0,d1,d2\r
+       vqdmull.s16     q0,d1,d2[0]\r
+\r
+       vqdmull.s32     q0,d1,d2\r
+       vqdmull.s32     q0,d1,d2[0]\r
+\r
+       vqmovn.s16      d0,q1\r
+\r
+       vqmovn.s32      d0,q1\r
+\r
+       vqmovn.s64      d0,q1\r
+\r
+       vqmovn.u16      d0,q1\r
+\r
+       vqmovn.u32      d0,q1\r
+\r
+       vqmovn.u64      d0,q1\r
+\r
+       vqmovun.s16     d0,q1\r
+\r
+       vqmovun.s32     d0,q1\r
+\r
+       vqmovun.s64     d0,q1\r
+\r
+       vqneg.s16       d0,d1\r
+       vqneg.s16       q0,q1\r
+\r
+       vqneg.s32       d0,d1\r
+       vqneg.s32       q0,q1\r
+\r
+       vqneg.s8        d0,d1\r
+       vqneg.s8        q0,q1\r
+\r
+       vqrdmulh.s16    d0,d1\r
+       vqrdmulh.s16    d0,d1,d2\r
+       vqrdmulh.s16    d0,d1[1]\r
+       vqrdmulh.s16    d0,d1,d2[1]\r
+       vqrdmulh.s16    q0,q1\r
+       vqrdmulh.s16    q0,q1,q2\r
+       vqrdmulh.s16    q0,d1[1]\r
+       vqrdmulh.s16    q0,q1,d2[1]\r
+\r
+       vqrdmulh.s32    d0,d1\r
+       vqrdmulh.s32    d0,d1,d2\r
+       vqrdmulh.s32    d0,d1[0]\r
+       vqrdmulh.s32    d0,d1,d2[0]\r
+       vqrdmulh.s32    q0,q1\r
+       vqrdmulh.s32    q0,q1,q2\r
+       vqrdmulh.s32    q0,d1[0]\r
+       vqrdmulh.s32    q0,q1,d1[0]\r
+\r
+       vqrshl.s16      d0,d1\r
+       vqrshl.s16      d0,d1,d2\r
+       vqrshl.s16      q0,q1\r
+       vqrshl.s16      q0,q1,q2\r
+\r
+       vqrshl.s32      d0,d1\r
+       vqrshl.s32      d0,d1,d2\r
+       vqrshl.s32      q0,q1\r
+       vqrshl.s32      q0,q1,q2\r
+\r
+       vqrshl.s64      d0,d1\r
+       vqrshl.s64      d0,d1,d2\r
+       vqrshl.s64      q0,q1\r
+       vqrshl.s64      q0,q1,q2\r
+\r
+       vqrshl.s8       d0,d1\r
+       vqrshl.s8       d0,d1,d2\r
+       vqrshl.s8       q0,q1\r
+       vqrshl.s8       q0,q1,q2\r
+\r
+       vqrshl.u16      d0,d1\r
+       vqrshl.u16      d0,d1,d2\r
+       vqrshl.u16      q0,q1\r
+       vqrshl.u16      q0,q1,q2\r
+\r
+       vqrshl.u32      d0,d1\r
+       vqrshl.u32      d0,d1,d2\r
+       vqrshl.u32      q0,q1\r
+       vqrshl.u32      q0,q1,q2\r
+\r
+       vqrshl.u64      d0,d1\r
+       vqrshl.u64      d0,d1,d2\r
+       vqrshl.u64      q0,q1\r
+       vqrshl.u64      q0,q1,q2\r
+\r
+       vqrshl.u8       d0,d1\r
+       vqrshl.u8       d0,d1,d2\r
+       vqrshl.u8       q0,q1\r
+       vqrshl.u8       q0,q1,q2\r
+\r
+       vqrshrn.s16     d0,q1,1\r
+\r
+       vqrshrn.s32     d0,q1,1\r
+\r
+       vqrshrn.s64     d0,q1,1\r
+\r
+       vqrshrn.u16     d0,q1,1\r
+\r
+       vqrshrn.u32     d0,q1,1\r
+\r
+       vqrshrn.u64     d0,q1,1\r
+\r
+       vqrshrun.s16    d0,q1,1\r
+\r
+       vqrshrun.s32    d0,q1,1\r
+\r
+       vqrshrun.s64    d0,q1,1\r
+\r
+       vqshl.s16       d0,1\r
+       vqshl.s16       d0,d1\r
+       vqshl.s16       d0,d1,1\r
+       vqshl.s16       d0,d1,d2\r
+       vqshl.s16       q0,1\r
+       vqshl.s16       q0,q1\r
+       vqshl.s16       q0,q1,1\r
+       vqshl.s16       q0,q1,q2\r
+\r
+       vqshl.s32       d0,1\r
+       vqshl.s32       d0,d1\r
+       vqshl.s32       d0,d1,1\r
+       vqshl.s32       d0,d1,d2\r
+       vqshl.s32       q0,1\r
+       vqshl.s32       q0,q1\r
+       vqshl.s32       q0,q1,1\r
+       vqshl.s32       q0,q1,q2\r
+\r
+       vqshl.s64       d0,1\r
+       vqshl.s64       d0,d1\r
+       vqshl.s64       d0,d1,1\r
+       vqshl.s64       d0,d1,d2\r
+       vqshl.s64       q0,1\r
+       vqshl.s64       q0,q1\r
+       vqshl.s64       q0,q1,1\r
+       vqshl.s64       q0,q1,q2\r
+\r
+       vqshl.s8        d0,1\r
+       vqshl.s8        d0,d1\r
+       vqshl.s8        d0,d1,1\r
+       vqshl.s8        d0,d1,d2\r
+       vqshl.s8        q0,1\r
+       vqshl.s8        q0,q1\r
+       vqshl.s8        q0,q1,1\r
+       vqshl.s8        q0,q1,q2\r
+\r
+       vqshl.u16       d0,1\r
+       vqshl.u16       d0,d1\r
+       vqshl.u16       d0,d1,1\r
+       vqshl.u16       d0,d1,d2\r
+       vqshl.u16       q0,1\r
+       vqshl.u16       q0,q1\r
+       vqshl.u16       q0,q1,1\r
+       vqshl.u16       q0,q1,q2\r
+\r
+       vqshl.u32       d0,1\r
+       vqshl.u32       d0,d1\r
+       vqshl.u32       d0,d1,1\r
+       vqshl.u32       d0,d1,d2\r
+       vqshl.u32       q0,1\r
+       vqshl.u32       q0,q1\r
+       vqshl.u32       q0,q1,1\r
+       vqshl.u32       q0,q1,q2\r
+\r
+       vqshl.u64       d0,1\r
+       vqshl.u64       d0,d1\r
+       vqshl.u64       d0,d1,1\r
+       vqshl.u64       d0,d1,d2\r
+       vqshl.u64       q0,1\r
+       vqshl.u64       q0,q1\r
+       vqshl.u64       q0,q1,1\r
+       vqshl.u64       q0,q1,q2\r
+\r
+       vqshl.u8        d0,1\r
+       vqshl.u8        d0,d1\r
+       vqshl.u8        d0,d1,1\r
+       vqshl.u8        d0,d1,d2\r
+       vqshl.u8        q0,1\r
+       vqshl.u8        q0,q1\r
+       vqshl.u8        q0,q1,1\r
+       vqshl.u8        q0,q1,q2\r
+\r
+       vqshlu.s16      d0,1\r
+       vqshlu.s16      d0,d1,1\r
+       vqshlu.s16      q0,1\r
+       vqshlu.s16      q0,q1,1\r
+\r
+       vqshlu.s32      d0,1\r
+       vqshlu.s32      d0,d1,1\r
+       vqshlu.s32      q0,1\r
+       vqshlu.s32      q0,q1,1\r
+\r
+       vqshlu.s64      d0,1\r
+       vqshlu.s64      d0,d1,1\r
+       vqshlu.s64      q0,1\r
+       vqshlu.s64      q0,q1,1\r
+\r
+       vqshlu.s8       d0,1\r
+       vqshlu.s8       d0,d1,1\r
+       vqshlu.s8       q0,1\r
+       vqshlu.s8       q0,q1,1\r
+\r
+       vqshrn.s16      d0,q1,1\r
+\r
+       vqshrn.s32      d0,q1,1\r
+\r
+       vqshrn.s64      d0,q1,1\r
+\r
+       vqshrn.u16      d0,q1,1\r
+\r
+       vqshrn.u32      d0,q1,1\r
+\r
+       vqshrn.u64      d0,q1,1\r
+\r
+       vqshrun.s16     d0,q1,1\r
+\r
+       vqshrun.s32     d0,q1,1\r
+\r
+       vqshrun.s64     d0,q1,1\r
+\r
+       vqsub.s16       d0,d1\r
+       vqsub.s16       d0,d1,d2\r
+       vqsub.s16       q0,q1\r
+       vqsub.s16       q0,q1,q2\r
+\r
+       vqsub.s32       d0,d1\r
+       vqsub.s32       d0,d1,d2\r
+       vqsub.s32       q0,q1\r
+       vqsub.s32       q0,q1,q2\r
+\r
+       vqsub.s64       d0,d1\r
+       vqsub.s64       d0,d1,d2\r
+       vqsub.s64       q0,q1\r
+       vqsub.s64       q0,q1,q2\r
+\r
+       vqsub.s8        d0,d1\r
+       vqsub.s8        d0,d1,d2\r
+       vqsub.s8        q0,q1\r
+       vqsub.s8        q0,q1,q2\r
+\r
+       vqsub.u16       d0,d1\r
+       vqsub.u16       d0,d1,d2\r
+       vqsub.u16       q0,q1\r
+       vqsub.u16       q0,q1,q2\r
+\r
+       vqsub.u32       d0,d1\r
+       vqsub.u32       d0,d1,d2\r
+       vqsub.u32       q0,q1\r
+       vqsub.u32       q0,q1,q2\r
+\r
+       vqsub.u64       d0,d1\r
+       vqsub.u64       d0,d1,d2\r
+       vqsub.u64       q0,q1\r
+       vqsub.u64       q0,q1,q2\r
+\r
+       vqsub.u8        d0,d1\r
+       vqsub.u8        d0,d1,d2\r
+       vqsub.u8        q0,q1\r
+       vqsub.u8        q0,q1,q2\r
+\r
+       vraddhn.i16     d0,q1,q2\r
+\r
+       vraddhn.i32     d0,q1,q2\r
+\r
+       vraddhn.i64     d0,q1,q2\r
+\r
+       vrecpe.u32      d0,d1\r
+       vrecpe.u32      q0,q1\r
+\r
+       vrev16.8        d0,d1\r
+       vrev16.8        q0,q1\r
+\r
+       vrev32.16       d0,d1\r
+       vrev32.16       q0,q1\r
+\r
+       vrev32.8        d0,d1\r
+       vrev32.8        q0,q1\r
+\r
+       vrev64.16       d0,d1\r
+       vrev64.16       q0,q1\r
+\r
+       vrev64.32       d0,d1\r
+       vrev64.32       q0,q1\r
+\r
+       vrev64.8        d0,d1\r
+       vrev64.8        q0,q1\r
+\r
+       vrhadd.s16      d0,d1\r
+       vrhadd.s16      d0,d1,d2\r
+       vrhadd.s16      q0,q1\r
+       vrhadd.s16      q0,q1,q2\r
+\r
+       vrhadd.s32      d0,d1\r
+       vrhadd.s32      d0,d1,d2\r
+       vrhadd.s32      q0,q1\r
+       vrhadd.s32      q0,q1,q2\r
+\r
+       vrhadd.s8       d0,d1\r
+       vrhadd.s8       d0,d1,d2\r
+       vrhadd.s8       q0,q1\r
+       vrhadd.s8       q0,q1,q2\r
+\r
+       vrhadd.u16      d0,d1\r
+       vrhadd.u16      d0,d1,d2\r
+       vrhadd.u16      q0,q1\r
+       vrhadd.u16      q0,q1,q2\r
+\r
+       vrhadd.u32      d0,d1\r
+       vrhadd.u32      d0,d1,d2\r
+       vrhadd.u32      q0,q1\r
+       vrhadd.u32      q0,q1,q2\r
+\r
+       vrhadd.u8       d0,d1\r
+       vrhadd.u8       d0,d1,d2\r
+       vrhadd.u8       q0,q1\r
+       vrhadd.u8       q0,q1,q2\r
+\r
+       vrshl.s16       d0,d1\r
+       vrshl.s16       d0,d1,d2\r
+       vrshl.s16       q0,q1\r
+       vrshl.s16       q0,q1,q2\r
+\r
+       vrshl.s32       d0,d1\r
+       vrshl.s32       d0,d1,d2\r
+       vrshl.s32       q0,q1\r
+       vrshl.s32       q0,q1,q2\r
+\r
+       vrshl.s64       d0,d1\r
+       vrshl.s64       d0,d1,d2\r
+       vrshl.s64       q0,q1\r
+       vrshl.s64       q0,q1,q2\r
+\r
+       vrshl.s8        d0,d1\r
+       vrshl.s8        d0,d1,d2\r
+       vrshl.s8        q0,q1\r
+       vrshl.s8        q0,q1,q2\r
+\r
+       vrshl.u16       d0,d1\r
+       vrshl.u16       d0,d1,d2\r
+       vrshl.u16       q0,q1\r
+       vrshl.u16       q0,q1,q2\r
+\r
+       vrshl.u32       d0,d1\r
+       vrshl.u32       d0,d1,d2\r
+       vrshl.u32       q0,q1\r
+       vrshl.u32       q0,q1,q2\r
+\r
+       vrshl.u64       d0,d1\r
+       vrshl.u64       d0,d1,d2\r
+       vrshl.u64       q0,q1\r
+       vrshl.u64       q0,q1,q2\r
+\r
+       vrshl.u8        d0,d1\r
+       vrshl.u8        d0,d1,d2\r
+       vrshl.u8        q0,q1\r
+       vrshl.u8        q0,q1,q2\r
+\r
+       vrshr.s16       d0,1\r
+       vrshr.s16       d0,d1,1\r
+       vrshr.s16       q0,1\r
+       vrshr.s16       q0,q1,1\r
+\r
+       vrshr.s32       d0,1\r
+       vrshr.s32       d0,d1,1\r
+       vrshr.s32       q0,1\r
+       vrshr.s32       q0,q1,1\r
+\r
+       vrshr.s64       d0,1\r
+       vrshr.s64       d0,d1,1\r
+       vrshr.s64       q0,1\r
+       vrshr.s64       q0,q1,1\r
+\r
+       vrshr.s8        d0,1\r
+       vrshr.s8        d0,d1,1\r
+       vrshr.s8        q0,1\r
+       vrshr.s8        q0,q1,1\r
+\r
+       vrshr.u16       d0,1\r
+       vrshr.u16       d0,d1,1\r
+       vrshr.u16       q0,1\r
+       vrshr.u16       q0,q1,1\r
+\r
+       vrshr.u32       d0,1\r
+       vrshr.u32       d0,d1,1\r
+       vrshr.u32       q0,1\r
+       vrshr.u32       q0,q1,1\r
+\r
+       vrshr.u64       d0,1\r
+       vrshr.u64       d0,d1,1\r
+       vrshr.u64       q0,1\r
+       vrshr.u64       q0,q1,1\r
+\r
+       vrshr.u8        d0,1\r
+       vrshr.u8        d0,d1,1\r
+       vrshr.u8        q0,1\r
+       vrshr.u8        q0,q1,1\r
+\r
+       vrshrn.i16      d0,q1,1\r
+\r
+       vrshrn.i32      d0,q1,1\r
+\r
+       vrshrn.i64      d0,q1,1\r
+\r
+       vrsqrte.u32     d0,d1\r
+       vrsqrte.u32     q0,q1\r
+\r
+       vrsra.s16       d0,1\r
+       vrsra.s16       d0,d1,1\r
+       vrsra.s16       q0,1\r
+       vrsra.s16       q0,q1,1\r
+\r
+       vrsra.s32       d0,1\r
+       vrsra.s32       d0,d1,1\r
+       vrsra.s32       q0,1\r
+       vrsra.s32       q0,q1,1\r
+\r
+       vrsra.s64       d0,1\r
+       vrsra.s64       d0,d1,1\r
+       vrsra.s64       q0,1\r
+       vrsra.s64       q0,q1,1\r
+\r
+       vrsra.s8        d0,1\r
+       vrsra.s8        d0,d1,1\r
+       vrsra.s8        q0,1\r
+       vrsra.s8        q0,q1,1\r
+\r
+       vrsra.u16       d0,1\r
+       vrsra.u16       d0,d1,1\r
+       vrsra.u16       q0,1\r
+       vrsra.u16       q0,q1,1\r
+\r
+       vrsra.u32       d0,1\r
+       vrsra.u32       d0,d1,1\r
+       vrsra.u32       q0,1\r
+       vrsra.u32       q0,q1,1\r
+\r
+       vrsra.u64       d0,1\r
+       vrsra.u64       d0,d1,1\r
+       vrsra.u64       q0,1\r
+       vrsra.u64       q0,q1,1\r
+\r
+       vrsra.u8        d0,1\r
+       vrsra.u8        d0,d1,1\r
+       vrsra.u8        q0,1\r
+       vrsra.u8        q0,q1,1\r
+\r
+       vrsubhn.i16     d0,q1,q2\r
+\r
+       vrsubhn.i32     d0,q1,q2\r
+\r
+       vrsubhn.i64     d0,q1,q2\r
+\r
+       vshl.i16        d0,1\r
+       vshl.i16        d0,d1,1\r
+       vshl.i16        q0,1\r
+       vshl.i16        q0,q1,1\r
+\r
+       vshl.i32        d0,1\r
+       vshl.i32        d0,d1,1\r
+       vshl.i32        q0,1\r
+       vshl.i32        q0,q1,1\r
+\r
+       vshl.i64        d0,1\r
+       vshl.i64        d0,d1,1\r
+       vshl.i64        q0,1\r
+       vshl.i64        q0,q1,1\r
+\r
+       vshl.i8 d0,1\r
+       vshl.i8 d0,d1,1\r
+       vshl.i8 q0,1\r
+       vshl.i8 q0,q1,1\r
+\r
+       vshl.s16        d0,d1\r
+       vshl.s16        d0,d1,d2\r
+       vshl.s16        q0,q1\r
+       vshl.s16        q0,q1,q2\r
+\r
+       vshl.s32        d0,d1\r
+       vshl.s32        d0,d1,d2\r
+       vshl.s32        q0,q1\r
+       vshl.s32        q0,q1,q2\r
+\r
+       vshl.s64        d0,d1\r
+       vshl.s64        d0,d1,d2\r
+       vshl.s64        q0,q1\r
+       vshl.s64        q0,q1,q2\r
+\r
+       vshl.s8 d0,d1\r
+       vshl.s8 d0,d1,d2\r
+       vshl.s8 q0,q1\r
+       vshl.s8 q0,q1,q2\r
+\r
+       vshl.u16        d0,d1\r
+       vshl.u16        d0,d1,d2\r
+       vshl.u16        q0,q1\r
+       vshl.u16        q0,q1,q2\r
+\r
+       vshl.u32        d0,d1\r
+       vshl.u32        d0,d1,d2\r
+       vshl.u32        q0,q1\r
+       vshl.u32        q0,q1,q2\r
+\r
+       vshl.u64        d0,d1\r
+       vshl.u64        d0,d1,d2\r
+       vshl.u64        q0,q1\r
+       vshl.u64        q0,q1,q2\r
+\r
+       vshl.u8 d0,d1\r
+       vshl.u8 d0,d1,d2\r
+       vshl.u8 q0,q1\r
+       vshl.u8 q0,q1,q2\r
+\r
+       vshll.i16       q0,d1,16\r
+\r
+       vshll.i32       q0,d1,32\r
+\r
+       vshll.i8        q0,d1,8\r
+\r
+       vshll.s16       q0,d1,1\r
+       vshll.s16       q0,d1,16\r
+\r
+       vshll.s32       q0,d1,1\r
+       vshll.s32       q0,d1,32\r
+\r
+       vshll.s8        q0,d1,1\r
+       vshll.s8        q0,d1,8\r
+\r
+       vshll.u16       q0,d1,1\r
+       vshll.u16       q0,d1,16\r
+\r
+       vshll.u32       q0,d1,1\r
+       vshll.u32       q0,d1,32\r
+\r
+       vshll.u8        q0,d1,1\r
+       vshll.u8        q0,d1,8\r
+\r
+       vshr.s16        d0,1\r
+       vshr.s16        d0,d1,1\r
+       vshr.s16        q0,1\r
+       vshr.s16        q0,q1,1\r
+\r
+       vshr.s32        d0,1\r
+       vshr.s32        d0,d1,1\r
+       vshr.s32        q0,1\r
+       vshr.s32        q0,q1,1\r
+\r
+       vshr.s64        d0,1\r
+       vshr.s64        d0,d1,1\r
+       vshr.s64        q0,1\r
+       vshr.s64        q0,q1,1\r
+\r
+       vshr.s8 d0,1\r
+       vshr.s8 d0,d1,1\r
+       vshr.s8 q0,1\r
+       vshr.s8 q0,q1,1\r
+\r
+       vshr.u16        d0,1\r
+       vshr.u16        d0,d1,1\r
+       vshr.u16        q0,1\r
+       vshr.u16        q0,q1,1\r
+\r
+       vshr.u32        d0,1\r
+       vshr.u32        d0,d1,1\r
+       vshr.u32        q0,1\r
+       vshr.u32        q0,q1,1\r
+\r
+       vshr.u64        d0,1\r
+       vshr.u64        d0,d1,1\r
+       vshr.u64        q0,1\r
+       vshr.u64        q0,q1,1\r
+\r
+       vshr.u8 d0,1\r
+       vshr.u8 d0,d1,1\r
+       vshr.u8 q0,1\r
+       vshr.u8 q0,q1,1\r
+\r
+       vshrn.i16       d0,q1,1\r
+\r
+       vshrn.i32       d0,q1,1\r
+\r
+       vshrn.i64       d0,q1,1\r
+\r
+       vsli.16 d0,1\r
+       vsli.16 d0,d1,1\r
+       vsli.16 q0,1\r
+       vsli.16 q0,q1,1\r
+\r
+       vsli.32 d0,1\r
+       vsli.32 d0,d1,1\r
+       vsli.32 q0,1\r
+       vsli.32 q0,q1,1\r
+\r
+       vsli.64 d0,1\r
+       vsli.64 d0,d1,1\r
+       vsli.64 q0,1\r
+       vsli.64 q0,q1,1\r
+\r
+       vsli.8  d0,1\r
+       vsli.8  d0,d1,1\r
+       vsli.8  q0,1\r
+       vsli.8  q0,q1,1\r
+\r
+       vsra.s16        d0,1\r
+       vsra.s16        d0,d1,1\r
+       vsra.s16        q0,1\r
+       vsra.s16        q0,q1,1\r
+\r
+       vsra.s32        d0,1\r
+       vsra.s32        d0,d1,1\r
+       vsra.s32        q0,1\r
+       vsra.s32        q0,q1,1\r
+\r
+       vsra.s64        d0,1\r
+       vsra.s64        d0,d1,1\r
+       vsra.s64        q0,1\r
+       vsra.s64        q0,q1,1\r
+\r
+       vsra.s8 d0,1\r
+       vsra.s8 d0,d1,1\r
+       vsra.s8 q0,1\r
+       vsra.s8 q0,q1,1\r
+\r
+       vsra.u16        d0,1\r
+       vsra.u16        d0,d1,1\r
+       vsra.u16        q0,1\r
+       vsra.u16        q0,q1,1\r
+\r
+       vsra.u32        d0,1\r
+       vsra.u32        d0,d1,1\r
+       vsra.u32        q0,1\r
+       vsra.u32        q0,q1,1\r
+\r
+       vsra.u64        d0,1\r
+       vsra.u64        d0,d1,1\r
+       vsra.u64        q0,1\r
+       vsra.u64        q0,q1,1\r
+\r
+       vsra.u8 d0,1\r
+       vsra.u8 d0,d1,1\r
+       vsra.u8 q0,1\r
+       vsra.u8 q0,q1,1\r
+\r
+       vsri.16 d0,1\r
+       vsri.16 d0,d1,1\r
+       vsri.16 q0,1\r
+       vsri.16 q0,q1,1\r
+\r
+       vsri.32 d0,1\r
+       vsri.32 d0,d1,1\r
+       vsri.32 q0,1\r
+       vsri.32 q0,q1,1\r
+\r
+       vsri.64 d0,1\r
+       vsri.64 d0,d1,1\r
+       vsri.64 q0,1\r
+       vsri.64 q0,q1,1\r
+\r
+       vsri.8  d0,1\r
+       vsri.8  d0,d1,1\r
+       vsri.8  q0,1\r
+       vsri.8  q0,q1,1\r
+\r
+       vst1.16 {d0},[r1]\r
+       vst1.16 {d0},[r1]!\r
+       vst1.16 {d0},[r1],8\r
+       vst1.16 {d0},[r1],r2\r
+       vst1.16 {d0},[r1@64]\r
+       vst1.16 {d0},[r1@64]!\r
+       vst1.16 {d0},[r1@64],8\r
+       vst1.16 {d0},[r1@64],r2\r
+       vst1.16 {d0,d1},[r2]\r
+       vst1.16 {d0,d1},[r2]!\r
+       vst1.16 {d0,d1},[r2],16\r
+       vst1.16 {d0,d1},[r2],r3\r
+       vst1.16 {d0,d1},[r2@64]\r
+       vst1.16 {d0,d1},[r2@64]!\r
+       vst1.16 {d0,d1},[r2@64],16\r
+       vst1.16 {d0,d1},[r2@64],r3\r
+       vst1.16 {d0,d1,d2},[r3]\r
+       vst1.16 {d0,d1,d2},[r3]!\r
+       vst1.16 {d0,d1,d2},[r3],24\r
+       vst1.16 {d0,d1,d2},[r3],r4\r
+       vst1.16 {d0,d1,d2},[r3@64]\r
+       vst1.16 {d0,d1,d2},[r3@64]!\r
+       vst1.16 {d0,d1,d2},[r3@64],24\r
+       vst1.16 {d0,d1,d2},[r3@64],r4\r
+       vst1.16 {d0,d1,d2,d3},[r4]\r
+       vst1.16 {d0,d1,d2,d3},[r4]!\r
+       vst1.16 {d0,d1,d2,d3},[r4],32\r
+       vst1.16 {d0,d1,d2,d3},[r4],r5\r
+       vst1.16 {d0,d1,d2,d3},[r4@64]\r
+       vst1.16 {d0,d1,d2,d3},[r4@64]!\r
+       vst1.16 {d0,d1,d2,d3},[r4@64],32\r
+       vst1.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vst1.16 {d0[1]},[r2]\r
+       vst1.16 {d0[1]},[r2]!\r
+       vst1.16 {d0[1]},[r2],2\r
+       vst1.16 {d0[1]},[r2],r3\r
+       vst1.16 {d0[1]},[r2@16]\r
+       vst1.16 {d0[1]},[r2@16]!\r
+       vst1.16 {d0[1]},[r2@16],2\r
+       vst1.16 {d0[1]},[r2@16],r3\r
+\r
+       vst1.32 {d0},[r1]\r
+       vst1.32 {d0},[r1]!\r
+       vst1.32 {d0},[r1],8\r
+       vst1.32 {d0},[r1],r2\r
+       vst1.32 {d0},[r1@64]\r
+       vst1.32 {d0},[r1@64]!\r
+       vst1.32 {d0},[r1@64],8\r
+       vst1.32 {d0},[r1@64],r2\r
+       vst1.32 {d0,d1},[r2]\r
+       vst1.32 {d0,d1},[r2]!\r
+       vst1.32 {d0,d1},[r2],16\r
+       vst1.32 {d0,d1},[r2],r3\r
+       vst1.32 {d0,d1},[r2@64]\r
+       vst1.32 {d0,d1},[r2@64]!\r
+       vst1.32 {d0,d1},[r2@64],16\r
+       vst1.32 {d0,d1},[r2@64],r3\r
+       vst1.32 {d0,d1,d2},[r3]\r
+       vst1.32 {d0,d1,d2},[r3]!\r
+       vst1.32 {d0,d1,d2},[r3],24\r
+       vst1.32 {d0,d1,d2},[r3],r4\r
+       vst1.32 {d0,d1,d2},[r3@64]\r
+       vst1.32 {d0,d1,d2},[r3@64]!\r
+       vst1.32 {d0,d1,d2},[r3@64],24\r
+       vst1.32 {d0,d1,d2},[r3@64],r4\r
+       vst1.32 {d0,d1,d2,d3},[r4]\r
+       vst1.32 {d0,d1,d2,d3},[r4]!\r
+       vst1.32 {d0,d1,d2,d3},[r4],32\r
+       vst1.32 {d0,d1,d2,d3},[r4],r5\r
+       vst1.32 {d0,d1,d2,d3},[r4@64]\r
+       vst1.32 {d0,d1,d2,d3},[r4@64]!\r
+       vst1.32 {d0,d1,d2,d3},[r4@64],32\r
+       vst1.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vst1.32 {d0[1]},[r2]\r
+       vst1.32 {d0[1]},[r2]!\r
+       vst1.32 {d0[1]},[r2],4\r
+       vst1.32 {d0[1]},[r2],r3\r
+       vst1.32 {d0[1]},[r2@32]\r
+       vst1.32 {d0[1]},[r2@32]!\r
+       vst1.32 {d0[1]},[r2@32],4\r
+       vst1.32 {d0[1]},[r2@32],r3\r
+\r
+       vst1.64 {d0},[r1]\r
+       vst1.64 {d0},[r1]!\r
+       vst1.64 {d0},[r1],8\r
+       vst1.64 {d0},[r1],r2\r
+       vst1.64 {d0},[r1@64]\r
+       vst1.64 {d0},[r1@64]!\r
+       vst1.64 {d0},[r1@64],8\r
+       vst1.64 {d0},[r1@64],r2\r
+       vst1.64 {d0,d1},[r2]\r
+       vst1.64 {d0,d1},[r2]!\r
+       vst1.64 {d0,d1},[r2],16\r
+       vst1.64 {d0,d1},[r2],r3\r
+       vst1.64 {d0,d1},[r2@64]\r
+       vst1.64 {d0,d1},[r2@64]!\r
+       vst1.64 {d0,d1},[r2@64],16\r
+       vst1.64 {d0,d1},[r2@64],r3\r
+       vst1.64 {d0,d1,d2},[r3]\r
+       vst1.64 {d0,d1,d2},[r3]!\r
+       vst1.64 {d0,d1,d2},[r3],24\r
+       vst1.64 {d0,d1,d2},[r3],r4\r
+       vst1.64 {d0,d1,d2},[r3@64]\r
+       vst1.64 {d0,d1,d2},[r3@64]!\r
+       vst1.64 {d0,d1,d2},[r3@64],24\r
+       vst1.64 {d0,d1,d2},[r3@64],r4\r
+       vst1.64 {d0,d1,d2,d3},[r4]\r
+       vst1.64 {d0,d1,d2,d3},[r4]!\r
+       vst1.64 {d0,d1,d2,d3},[r4],32\r
+       vst1.64 {d0,d1,d2,d3},[r4],r5\r
+       vst1.64 {d0,d1,d2,d3},[r4@64]\r
+       vst1.64 {d0,d1,d2,d3},[r4@64]!\r
+       vst1.64 {d0,d1,d2,d3},[r4@64],32\r
+       vst1.64 {d0,d1,d2,d3},[r4@64],r5\r
+\r
+       vst1.8  {d0},[r1]\r
+       vst1.8  {d0},[r1]!\r
+       vst1.8  {d0},[r1],8\r
+       vst1.8  {d0},[r1],r2\r
+       vst1.8  {d0},[r1@64]\r
+       vst1.8  {d0},[r1@64]!\r
+       vst1.8  {d0},[r1@64],8\r
+       vst1.8  {d0},[r1@64],r2\r
+       vst1.8  {d0,d1},[r2]\r
+       vst1.8  {d0,d1},[r2]!\r
+       vst1.8  {d0,d1},[r2],16\r
+       vst1.8  {d0,d1},[r2],r3\r
+       vst1.8  {d0,d1},[r2@64]\r
+       vst1.8  {d0,d1},[r2@64]!\r
+       vst1.8  {d0,d1},[r2@64],16\r
+       vst1.8  {d0,d1},[r2@64],r3\r
+       vst1.8  {d0,d1,d2},[r3]\r
+       vst1.8  {d0,d1,d2},[r3]!\r
+       vst1.8  {d0,d1,d2},[r3],24\r
+       vst1.8  {d0,d1,d2},[r3],r4\r
+       vst1.8  {d0,d1,d2},[r3@64]\r
+       vst1.8  {d0,d1,d2},[r3@64]!\r
+       vst1.8  {d0,d1,d2},[r3@64],24\r
+       vst1.8  {d0,d1,d2},[r3@64],r4\r
+       vst1.8  {d0,d1,d2,d3},[r4]\r
+       vst1.8  {d0,d1,d2,d3},[r4]!\r
+       vst1.8  {d0,d1,d2,d3},[r4],32\r
+       vst1.8  {d0,d1,d2,d3},[r4],r5\r
+       vst1.8  {d0,d1,d2,d3},[r4@64]\r
+       vst1.8  {d0,d1,d2,d3},[r4@64]!\r
+       vst1.8  {d0,d1,d2,d3},[r4@64],32\r
+       vst1.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vst1.8  {d0[1]},[r2]\r
+       vst1.8  {d0[1]},[r2]!\r
+       vst1.8  {d0[1]},[r2],1\r
+       vst1.8  {d0[1]},[r2],r3\r
+\r
+       vst2.16 {d0,d1},[r2]\r
+       vst2.16 {d0,d1},[r2]!\r
+       vst2.16 {d0,d1},[r2],16\r
+       vst2.16 {d0,d1},[r2],r3\r
+       vst2.16 {d0,d1},[r2@64]\r
+       vst2.16 {d0,d1},[r2@64]!\r
+       vst2.16 {d0,d1},[r2@64],16\r
+       vst2.16 {d0,d1},[r2@64],r3\r
+       vst2.16 {d0,d2},[r3]\r
+       vst2.16 {d0,d2},[r3]!\r
+       vst2.16 {d0,d2},[r3],16\r
+       vst2.16 {d0,d2},[r3],r4\r
+       vst2.16 {d0,d2},[r3@64]\r
+       vst2.16 {d0,d2},[r3@64]!\r
+       vst2.16 {d0,d2},[r3@64],16\r
+       vst2.16 {d0,d2},[r3@64],r4\r
+       vst2.16 {d0,d1,d2,d3},[r4]\r
+       vst2.16 {d0,d1,d2,d3},[r4]!\r
+       vst2.16 {d0,d1,d2,d3},[r4],32\r
+       vst2.16 {d0,d1,d2,d3},[r4],r5\r
+       vst2.16 {d0,d1,d2,d3},[r4@64]\r
+       vst2.16 {d0,d1,d2,d3},[r4@64]!\r
+       vst2.16 {d0,d1,d2,d3},[r4@64],32\r
+       vst2.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vst2.16 {d0[1],d1[1]},[r2]\r
+       vst2.16 {d0[1],d1[1]},[r2]!\r
+       vst2.16 {d0[1],d1[1]},[r2],4\r
+       vst2.16 {d0[1],d1[1]},[r2],r3\r
+       vst2.16 {d0[1],d1[1]},[r2@32]\r
+       vst2.16 {d0[1],d1[1]},[r2@32]!\r
+       vst2.16 {d0[1],d1[1]},[r2@32],4\r
+       vst2.16 {d0[1],d1[1]},[r2@32],r3\r
+       vst2.16 {d0[1],d2[1]},[r2]\r
+       vst2.16 {d0[1],d2[1]},[r2]!\r
+       vst2.16 {d0[1],d2[1]},[r2],4\r
+       vst2.16 {d0[1],d2[1]},[r2],r3\r
+       vst2.16 {d0[1],d2[1]},[r2@32]\r
+       vst2.16 {d0[1],d2[1]},[r2@32]!\r
+       vst2.16 {d0[1],d2[1]},[r2@32],4\r
+       vst2.16 {d0[1],d2[1]},[r2@32],r3\r
+       vst2.32 {d0,d1},[r2]\r
+       vst2.32 {d0,d1},[r2]!\r
+       vst2.32 {d0,d1},[r2],16\r
+       vst2.32 {d0,d1},[r2],r3\r
+       vst2.32 {d0,d1},[r2@64]\r
+       vst2.32 {d0,d1},[r2@64]!\r
+       vst2.32 {d0,d1},[r2@64],16\r
+       vst2.32 {d0,d1},[r2@64],r3\r
+       vst2.32 {d0,d2},[r3]\r
+       vst2.32 {d0,d2},[r3]!\r
+       vst2.32 {d0,d2},[r3],16\r
+       vst2.32 {d0,d2},[r3],r4\r
+       vst2.32 {d0,d2},[r3@64]\r
+       vst2.32 {d0,d2},[r3@64]!\r
+       vst2.32 {d0,d2},[r3@64],16\r
+       vst2.32 {d0,d2},[r3@64],r4\r
+       vst2.32 {d0,d1,d2,d3},[r4]\r
+       vst2.32 {d0,d1,d2,d3},[r4]!\r
+       vst2.32 {d0,d1,d2,d3},[r4],32\r
+       vst2.32 {d0,d1,d2,d3},[r4],r5\r
+       vst2.32 {d0,d1,d2,d3},[r4@64]\r
+       vst2.32 {d0,d1,d2,d3},[r4@64]!\r
+       vst2.32 {d0,d1,d2,d3},[r4@64],32\r
+       vst2.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vst2.32 {d0[1],d1[1]},[r2]\r
+       vst2.32 {d0[1],d1[1]},[r2]!\r
+       vst2.32 {d0[1],d1[1]},[r2],8\r
+       vst2.32 {d0[1],d1[1]},[r2],r3\r
+       vst2.32 {d0[1],d1[1]},[r2@64]\r
+       vst2.32 {d0[1],d1[1]},[r2@64]!\r
+       vst2.32 {d0[1],d1[1]},[r2@64],8\r
+       vst2.32 {d0[1],d1[1]},[r2@64],r3\r
+       vst2.32 {d0[1],d2[1]},[r2]\r
+       vst2.32 {d0[1],d2[1]},[r2]!\r
+       vst2.32 {d0[1],d2[1]},[r2],8\r
+       vst2.32 {d0[1],d2[1]},[r2],r3\r
+       vst2.32 {d0[1],d2[1]},[r2@64]\r
+       vst2.32 {d0[1],d2[1]},[r2@64]!\r
+       vst2.32 {d0[1],d2[1]},[r2@64],8\r
+       vst2.32 {d0[1],d2[1]},[r2@64],r3\r
+\r
+       vst2.8  {d0,d1},[r2]\r
+       vst2.8  {d0,d1},[r2]!\r
+       vst2.8  {d0,d1},[r2],16\r
+       vst2.8  {d0,d1},[r2],r3\r
+       vst2.8  {d0,d1},[r2@64]\r
+       vst2.8  {d0,d1},[r2@64]!\r
+       vst2.8  {d0,d1},[r2@64],16\r
+       vst2.8  {d0,d1},[r2@64],r3\r
+       vst2.8  {d0,d2},[r3]\r
+       vst2.8  {d0,d2},[r3]!\r
+       vst2.8  {d0,d2},[r3],16\r
+       vst2.8  {d0,d2},[r3],r4\r
+       vst2.8  {d0,d2},[r3@64]\r
+       vst2.8  {d0,d2},[r3@64]!\r
+       vst2.8  {d0,d2},[r3@64],16\r
+       vst2.8  {d0,d2},[r3@64],r4\r
+       vst2.8  {d0,d1,d2,d3},[r4]\r
+       vst2.8  {d0,d1,d2,d3},[r4]!\r
+       vst2.8  {d0,d1,d2,d3},[r4],32\r
+       vst2.8  {d0,d1,d2,d3},[r4],r5\r
+       vst2.8  {d0,d1,d2,d3},[r4@64]\r
+       vst2.8  {d0,d1,d2,d3},[r4@64]!\r
+       vst2.8  {d0,d1,d2,d3},[r4@64],32\r
+       vst2.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vst2.8  {d0[1],d1[1]},[r2]\r
+       vst2.8  {d0[1],d1[1]},[r2]!\r
+       vst2.8  {d0[1],d1[1]},[r2],2\r
+       vst2.8  {d0[1],d1[1]},[r2],r3\r
+       vst2.8  {d0[1],d1[1]},[r2@16]\r
+       vst2.8  {d0[1],d1[1]},[r2@16]!\r
+       vst2.8  {d0[1],d1[1]},[r2@16],2\r
+       vst2.8  {d0[1],d1[1]},[r2@16],r3\r
+\r
+       vst3.16 {d0,d1,d2},[r2]\r
+       vst3.16 {d0,d1,d2},[r2]!\r
+       vst3.16 {d0,d1,d2},[r2],24\r
+       vst3.16 {d0,d1,d2},[r2],r3\r
+       vst3.16 {d0,d1,d2},[r2@64]\r
+       vst3.16 {d0,d1,d2},[r2@64]!\r
+       vst3.16 {d0,d1,d2},[r2@64],24\r
+       vst3.16 {d0,d1,d2},[r2@64],r3\r
+       vst3.16 {d0,d2,d4},[r3]\r
+       vst3.16 {d0,d2,d4},[r3]!\r
+       vst3.16 {d0,d2,d4},[r3],24\r
+       vst3.16 {d0,d2,d4},[r3],r4\r
+       vst3.16 {d0,d2,d4},[r3@64]\r
+       vst3.16 {d0,d2,d4},[r3@64]!\r
+       vst3.16 {d0,d2,d4},[r3@64],24\r
+       vst3.16 {d0,d2,d4},[r3@64],r4\r
+       vst3.16 {d0[1],d1[1],d2[1]},[r2]\r
+       vst3.16 {d0[1],d1[1],d2[1]},[r2]!\r
+       vst3.16 {d0[1],d1[1],d2[1]},[r2],6\r
+       vst3.16 {d0[1],d1[1],d2[1]},[r2],r3\r
+       vst3.16 {d0[1],d2[1],d4[1]},[r2]\r
+       vst3.16 {d0[1],d2[1],d4[1]},[r2]!\r
+       vst3.16 {d0[1],d2[1],d4[1]},[r2],6\r
+       vst3.16 {d0[1],d2[1],d4[1]},[r2],r3\r
+\r
+       vst3.32 {d0,d1,d2},[r2]\r
+       vst3.32 {d0,d1,d2},[r2]!\r
+       vst3.32 {d0,d1,d2},[r2],24\r
+       vst3.32 {d0,d1,d2},[r2],r3\r
+       vst3.32 {d0,d1,d2},[r2@64]\r
+       vst3.32 {d0,d1,d2},[r2@64]!\r
+       vst3.32 {d0,d1,d2},[r2@64],24\r
+       vst3.32 {d0,d1,d2},[r2@64],r3\r
+       vst3.32 {d0,d2,d4},[r3]\r
+       vst3.32 {d0,d2,d4},[r3]!\r
+       vst3.32 {d0,d2,d4},[r3],24\r
+       vst3.32 {d0,d2,d4},[r3],r4\r
+       vst3.32 {d0,d2,d4},[r3@64]\r
+       vst3.32 {d0,d2,d4},[r3@64]!\r
+       vst3.32 {d0,d2,d4},[r3@64],24\r
+       vst3.32 {d0,d2,d4},[r3@64],r4\r
+       vst3.32 {d0[1],d1[1],d2[1]},[r2]\r
+       vst3.32 {d0[1],d1[1],d2[1]},[r2]!\r
+       vst3.32 {d0[1],d1[1],d2[1]},[r2],12\r
+       vst3.32 {d0[1],d1[1],d2[1]},[r2],r3\r
+       vst3.32 {d0[1],d2[1],d4[1]},[r2]\r
+       vst3.32 {d0[1],d2[1],d4[1]},[r2]!\r
+       vst3.32 {d0[1],d2[1],d4[1]},[r2],12\r
+       vst3.32 {d0[1],d2[1],d4[1]},[r2],r3\r
+\r
+       vst3.8  {d0,d1,d2},[r2]\r
+       vst3.8  {d0,d1,d2},[r2]!\r
+       vst3.8  {d0,d1,d2},[r2],24\r
+       vst3.8  {d0,d1,d2},[r2],r3\r
+       vst3.8  {d0,d1,d2},[r2@64]\r
+       vst3.8  {d0,d1,d2},[r2@64]!\r
+       vst3.8  {d0,d1,d2},[r2@64],24\r
+       vst3.8  {d0,d1,d2},[r2@64],r3\r
+       vst3.8  {d0,d2,d4},[r3]\r
+       vst3.8  {d0,d2,d4},[r3]!\r
+       vst3.8  {d0,d2,d4},[r3],24\r
+       vst3.8  {d0,d2,d4},[r3],r4\r
+       vst3.8  {d0,d2,d4},[r3@64]\r
+       vst3.8  {d0,d2,d4},[r3@64]!\r
+       vst3.8  {d0,d2,d4},[r3@64],24\r
+       vst3.8  {d0,d2,d4},[r3@64],r4\r
+       vst3.8  {d0[1],d1[1],d2[1]},[r2]\r
+       vst3.8  {d0[1],d1[1],d2[1]},[r2]!\r
+       vst3.8  {d0[1],d1[1],d2[1]},[r2],3\r
+       vst3.8  {d0[1],d1[1],d2[1]},[r2],r3\r
+\r
+       vst4.16 {d0,d1,d2,d3},[r4]\r
+       vst4.16 {d0,d1,d2,d3},[r4]!\r
+       vst4.16 {d0,d1,d2,d3},[r4],32\r
+       vst4.16 {d0,d1,d2,d3},[r4],r5\r
+       vst4.16 {d0,d1,d2,d3},[r4@64]\r
+       vst4.16 {d0,d1,d2,d3},[r4@64]!\r
+       vst4.16 {d0,d1,d2,d3},[r4@64],32\r
+       vst4.16 {d0,d1,d2,d3},[r4@64],r5\r
+       vst4.16 {d0,d2,d4,d6},[r4]\r
+       vst4.16 {d0,d2,d4,d6},[r4]!\r
+       vst4.16 {d0,d2,d4,d6},[r4],32\r
+       vst4.16 {d0,d2,d4,d6},[r4],r5\r
+       vst4.16 {d0,d2,d4,d6},[r4@64]\r
+       vst4.16 {d0,d2,d4,d6},[r4@64]!\r
+       vst4.16 {d0,d2,d4,d6},[r4@64],32\r
+       vst4.16 {d0,d2,d4,d6},[r4@64],r5\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],8\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64]!\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],8\r
+       vst4.16 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2]!\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],8\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2],r3\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64]!\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],8\r
+       vst4.16 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3\r
+\r
+       vst4.32 {d0,d1,d2,d3},[r4]\r
+       vst4.32 {d0,d1,d2,d3},[r4]!\r
+       vst4.32 {d0,d1,d2,d3},[r4],32\r
+       vst4.32 {d0,d1,d2,d3},[r4],r5\r
+       vst4.32 {d0,d1,d2,d3},[r4@64]\r
+       vst4.32 {d0,d1,d2,d3},[r4@64]!\r
+       vst4.32 {d0,d1,d2,d3},[r4@64],32\r
+       vst4.32 {d0,d1,d2,d3},[r4@64],r5\r
+       vst4.32 {d0,d2,d4,d6},[r4]\r
+       vst4.32 {d0,d2,d4,d6},[r4]!\r
+       vst4.32 {d0,d2,d4,d6},[r4],32\r
+       vst4.32 {d0,d2,d4,d6},[r4],r5\r
+       vst4.32 {d0,d2,d4,d6},[r4@64]\r
+       vst4.32 {d0,d2,d4,d6},[r4@64]!\r
+       vst4.32 {d0,d2,d4,d6},[r4@64],32\r
+       vst4.32 {d0,d2,d4,d6},[r4@64],r5\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],16\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64]!\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],16\r
+       vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r2@64],r3\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2]!\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],16\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2],r3\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64]!\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],16\r
+       vst4.32 {d0[1],d2[1],d4[1],d6[1]},[r2@64],r3\r
+\r
+       vst4.8  {d0,d1,d2,d3},[r4]\r
+       vst4.8  {d0,d1,d2,d3},[r4]!\r
+       vst4.8  {d0,d1,d2,d3},[r4],32\r
+       vst4.8  {d0,d1,d2,d3},[r4],r5\r
+       vst4.8  {d0,d1,d2,d3},[r4@64]\r
+       vst4.8  {d0,d1,d2,d3},[r4@64]!\r
+       vst4.8  {d0,d1,d2,d3},[r4@64],32\r
+       vst4.8  {d0,d1,d2,d3},[r4@64],r5\r
+       vst4.8  {d0,d2,d4,d6},[r4]\r
+       vst4.8  {d0,d2,d4,d6},[r4]!\r
+       vst4.8  {d0,d2,d4,d6},[r4],32\r
+       vst4.8  {d0,d2,d4,d6},[r4],r5\r
+       vst4.8  {d0,d2,d4,d6},[r4@64]\r
+       vst4.8  {d0,d2,d4,d6},[r4@64]!\r
+       vst4.8  {d0,d2,d4,d6},[r4@64],32\r
+       vst4.8  {d0,d2,d4,d6},[r4@64],r5\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2]\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2]!\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2],4\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2],r3\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32]\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32]!\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32],4\r
+       vst4.8  {d0[1],d1[1],d2[1],d3[1]},[r2@32],r3\r
+\r
+       vsub.i16        d0,d1\r
+       vsub.i16        d0,d1,d2\r
+       vsub.i16        q0,q1\r
+       vsub.i16        q0,q1,q2\r
+\r
+       vsub.i32        d0,d1\r
+       vsub.i32        d0,d1,d2\r
+       vsub.i32        q0,q1\r
+       vsub.i32        q0,q1,q2\r
+\r
+       vsub.i64        d0,d1\r
+       vsub.i64        d0,d1,d2\r
+       vsub.i64        q0,q1\r
+       vsub.i64        q0,q1,q2\r
+\r
+       vsub.i8 d0,d1\r
+       vsub.i8 d0,d1,d2\r
+       vsub.i8 q0,q1\r
+       vsub.i8 q0,q1,q2\r
+\r
+       vsubhn.i16      d0,q1,q2\r
+\r
+       vsubhn.i32      d0,q1,q2\r
+\r
+       vsubhn.i64      d0,q1,q2\r
+\r
+       vsubl.s16       q0,d1,d2\r
+\r
+       vsubl.s32       q0,d1,d2\r
+\r
+       vsubl.s8        q0,d1,d2\r
+\r
+       vsubl.u16       q0,d1,d2\r
+\r
+       vsubl.u32       q0,d1,d2\r
+\r
+       vsubl.u8        q0,d1,d2\r
+\r
+       vsubw.s16       q0,d1\r
+       vsubw.s16       q0,q1,d2\r
+\r
+       vsubw.s32       q0,d1\r
+       vsubw.s32       q0,q1,d2\r
+\r
+       vsubw.s8        q0,d1\r
+       vsubw.s8        q0,q1,d2\r
+\r
+       vsubw.u16       q0,d1\r
+       vsubw.u16       q0,q1,d2\r
+\r
+       vsubw.u32       q0,d1\r
+       vsubw.u32       q0,q1,d2\r
+\r
+       vsubw.u8        q0,d1\r
+       vsubw.u8        q0,q1,d2\r
+\r
+       vswp    d0,d1\r
+       vswp    q0,q1\r
+\r
+       vtbl.8  d0,{d1},d2\r
+       vtbl.8  d0,{d1,d2},d3\r
+       vtbl.8  d0,{d1,d2,d3},d4\r
+       vtbl.8  d0,{d1,d2,d3,d4},d5\r
+\r
+       vtbx.8  d0,{d1},d2\r
+       vtbx.8  d0,{d1,d2},d3\r
+       vtbx.8  d0,{d1,d2,d3},d4\r
+       vtbx.8  d0,{d1,d2,d3,d4},d5\r
+\r
+       vtrn.16 d0,d1\r
+       vtrn.16 q0,q1\r
+\r
+       vtrn.32 d0,d1\r
+       vtrn.32 q0,q1\r
+\r
+       vtrn.8  d0,d1\r
+       vtrn.8  q0,q1\r
+\r
+       vtst.16 d0,d1\r
+       vtst.16 d0,d1,d2\r
+       vtst.16 q0,q1\r
+       vtst.16 q0,q1,q2\r
+\r
+       vtst.32 d0,d1\r
+       vtst.32 d0,d1,d2\r
+       vtst.32 q0,q1\r
+       vtst.32 q0,q1,q2\r
+\r
+       vtst.8  d0,d1\r
+       vtst.8  d0,d1,d2\r
+       vtst.8  q0,q1\r
+       vtst.8  q0,q1,q2\r
+\r
+       vuzp.16 d0,d1\r
+       vuzp.16 q0,q1\r
+\r
+       vuzp.32 d0,d1\r
+       vuzp.32 q0,q1\r
+\r
+       vuzp.8  d0,d1\r
+       vuzp.8  q0,q1\r
+\r
+       vzip.16 d0,d1\r
+       vzip.16 q0,q1\r
+\r
+       vzip.32 d0,d1\r
+       vzip.32 q0,q1\r
+\r
+       vzip.8  d0,d1\r
+       vzip.8  q0,q1\r
+\r
+coprocessor COPRO_SIMD_FLOAT\r
+\r
+       vabd.f32        d0,d1\r
+       vabd.f32        d0,d1,d2\r
+       vabd.f32        q0,q1\r
+       vabd.f32        q0,q1,q2\r
+\r
+       vabs.f32        d0,d1\r
+       vabs.f32        q0,q1\r
+\r
+       vacge.f32       d0,d1\r
+       vacge.f32       d0,d1,d2\r
+       vacge.f32       q0,q1\r
+       vacge.f32       q0,q1,q2\r
+\r
+       vacgt.f32       d0,d1\r
+       vacgt.f32       d0,d1,d2\r
+       vacgt.f32       q0,q1\r
+       vacgt.f32       q0,q1,q2\r
+\r
+       vacle.f32       d0,d1\r
+       vacle.f32       d0,d1,d2\r
+       vacle.f32       q0,q1\r
+       vacle.f32       q0,q1,q2\r
+\r
+       vaclt.f32       d0,d1\r
+       vaclt.f32       d0,d1,d2\r
+       vaclt.f32       q0,q1\r
+       vaclt.f32       q0,q1,q2\r
+\r
+       vadd.f32        d0,d1\r
+       vadd.f32        d0,d1,d2\r
+       vadd.f32        q0,q1\r
+       vadd.f32        q0,q1,q2\r
+\r
+       vceq.f32        d0,0\r
+       vceq.f32        d0,d1\r
+       vceq.f32        d0,d1,0\r
+       vceq.f32        d0,d1,d2\r
+       vceq.f32        q0,0\r
+       vceq.f32        q0,q1\r
+       vceq.f32        q0,q1,0\r
+       vceq.f32        q0,q1,q2\r
+\r
+       vcge.f32        d0,0\r
+       vcge.f32        d0,d1\r
+       vcge.f32        d0,d1,0\r
+       vcge.f32        d0,d1,d2\r
+       vcge.f32        q0,0\r
+       vcge.f32        q0,q1\r
+       vcge.f32        q0,q1,0\r
+       vcge.f32        q0,q1,q2\r
+\r
+       vcgt.f32        d0,0\r
+       vcgt.f32        d0,d1\r
+       vcgt.f32        d0,d1,0\r
+       vcgt.f32        d0,d1,d2\r
+       vcgt.f32        q0,0\r
+       vcgt.f32        q0,q1\r
+       vcgt.f32        q0,q1,0\r
+       vcgt.f32        q0,q1,q2\r
+\r
+       vcle.f32        d0,0\r
+       vcle.f32        d0,d1\r
+       vcle.f32        d0,d1,0\r
+       vcle.f32        d0,d1,d2\r
+       vcle.f32        q0,0\r
+       vcle.f32        q0,q1\r
+       vcle.f32        q0,q1,0\r
+       vcle.f32        q0,q1,q2\r
+\r
+       vclt.f32        d0,0\r
+       vclt.f32        d0,d1\r
+       vclt.f32        d0,d1,0\r
+       vclt.f32        d0,d1,d2\r
+       vclt.f32        q0,0\r
+       vclt.f32        q0,q1\r
+       vclt.f32        q0,q1,0\r
+       vclt.f32        q0,q1,q2\r
+\r
+       vcvt.f32.s32    d0,d1\r
+       vcvt.f32.s32    d0,d1,2\r
+       vcvt.f32.s32    q0,q1\r
+       vcvt.f32.s32    q0,q1,2\r
+\r
+       vcvt.f32.u32    d0,d1\r
+       vcvt.f32.u32    d0,d1,2\r
+       vcvt.f32.u32    q0,q1\r
+       vcvt.f32.u32    q0,q1,2\r
+\r
+       vcvt.s32.f32    d0,d1\r
+       vcvt.s32.f32    d0,d1,2\r
+       vcvt.s32.f32    q0,q1\r
+       vcvt.s32.f32    q0,q1,2\r
+\r
+       vcvt.u32.f32    d0,d1\r
+       vcvt.u32.f32    d0,d1,2\r
+       vcvt.u32.f32    q0,q1\r
+       vcvt.u32.f32    q0,q1,2\r
+\r
+       vmax.f32        d0,d1\r
+       vmax.f32        d0,d1,d2\r
+       vmax.f32        q0,q1\r
+       vmax.f32        q0,q1,q2\r
+\r
+       vmin.f32        d0,d1\r
+       vmin.f32        d0,d1,d2\r
+       vmin.f32        q0,q1\r
+       vmin.f32        q0,q1,q2\r
+\r
+       vmla.f32        d0,d1,d2\r
+       vmla.f32        d0,d1,d2[0]\r
+       vmla.f32        q0,q1,q2\r
+       vmla.f32        q0,q1,d2[1]\r
+\r
+       vmls.f32        d0,d1,d2\r
+       vmls.f32        d0,d1,d2[0]\r
+       vmls.f32        q0,q1,q2\r
+       vmls.f32        q0,q1,d2[1]\r
+\r
+       vmov.f32        d0,1\r
+       vmov.f32        d0,1.0\r
+       vmov.f32        q0,1\r
+       vmov.f32        q0,1.0\r
+\r
+       vmul.f32        d0,d1\r
+       vmul.f32        d0,d1,d2\r
+       vmul.f32        d0,d1[0]\r
+       vmul.f32        d0,d1,d2[0]\r
+       vmul.f32        q0,q1\r
+       vmul.f32        q0,q1,q2\r
+       vmul.f32        q0,d1[0]\r
+       vmul.f32        q0,q1,d1[0]\r
+\r
+       vneg.f32        d0,d1\r
+       vneg.f32        q0,q1\r
+\r
+       vpadd.f32       d0,d1\r
+       vpadd.f32       d0,d1,d2\r
+\r
+       vpmax.f32       d0,d1\r
+       vpmax.f32       d0,d1,d2\r
+\r
+       vpmin.f32       d0,d1\r
+       vpmin.f32       d0,d1,d2\r
+\r
+       vrecpe.f32      d0,d1\r
+       vrecpe.f32      q0,q1\r
+\r
+       vrecps.f32      d0,d1\r
+       vrecps.f32      d0,d1,d2\r
+       vrecps.f32      q0,q1\r
+       vrecps.f32      q0,q1,q2\r
+\r
+       vrsqrte.f32     d0,d1\r
+       vrsqrte.f32     q0,q1\r
+\r
+       vrsqrts.f32     d0,d1\r
+       vrsqrts.f32     d0,d1,d2\r
+       vrsqrts.f32     q0,q1\r
+       vrsqrts.f32     q0,q1,q2\r
+\r
+       vsub.f32        d0,d1\r
+       vsub.f32        d0,d1,d2\r
+       vsub.f32        q0,q1\r
+       vsub.f32        q0,q1,q2\r
+\r
+coprocessor COPRO_SIMD_HP\r
+\r
+       vcvt.f32.f16    q0,d1\r
+\r
+       vcvt.f16.f32    d0,q1\r
+\r
+coprocessor COPRO_SIMD_V2\r
+\r
+       vfma.f32        q0,q1,q2\r
+       vfma.f32        d0,d1,d2\r
+\r
+       vfms.f32        q0,q1,q2\r
+       vfms.f32        d0,d1,d2\r
+\r
+coprocessor COPRO_SIMD_V8\r
+\r
+       vcvtm.s32.f32   d0,d1\r
+       vcvtm.u32.f32   d0,d1\r
+       vcvtm.s32.f32   q0,q1\r
+       vcvtm.u32.f32   q0,q1\r
+\r
+       vcvtp.s32.f32   d0,d1\r
+       vcvtp.u32.f32   d0,d1\r
+       vcvtp.s32.f32   q0,q1\r
+       vcvtp.u32.f32   q0,q1\r
+\r
+       vcvtn.s32.f32   d0,d1\r
+       vcvtn.u32.f32   d0,d1\r
+       vcvtn.s32.f32   q0,q1\r
+       vcvtn.u32.f32   q0,q1\r
+\r
+       vcvta.s32.f32   d0,d1\r
+       vcvta.u32.f32   d0,d1\r
+       vcvta.s32.f32   q0,q1\r
+       vcvta.u32.f32   q0,q1\r
+\r
+       vmaxnm.f32      d0,d1,d2\r
+       vmaxnm.f32      q0,q1,q2\r
+\r
+       vminnm.f32      d0,d1,d2\r
+       vminnm.f32      q0,q1,q2\r
+\r
+       vrintm.f32.f32  d0,d1\r
+       vrintm.f32.f32  q0,q1\r
+\r
+       vrintp.f32.f32  d0,d1\r
+       vrintp.f32.f32  q0,q1\r
+\r
+       vrintn.f32.f32  d0,d1\r
+       vrintn.f32.f32  q0,q1\r
+\r
+       vrinta.f32.f32  d0,d1\r
+       vrinta.f32.f32  q0,q1\r
+\r
+       vrintx.f32.f32  d0,d1\r
+       vrintx.f32.f32  q0,q1\r
+\r
+       vrintz.f32.f32  d0,d1\r
+       vrintz.f32.f32  q0,q1\r
+\r
+coprocessor COPRO_SIMD_CRYPTO\r
+\r
+       aese.8  q0,q1\r
+       aesd.8  q0,q1\r
+       aesmc.8 q0,q1\r
+       aesimc.8        q0,q1\r
+\r
+       sha1h.32        q0,q1\r
+       sha1c.32        q0,q1,q2\r
+       sha1p.32        q0,q1,q2\r
+       sha1m.32        q0,q1,q2\r
+       sha1su0.32      q0,q1,q2\r
+       sha1su1.32      q0,q1\r
+\r
+       sha256h.32      q0,q1,q2\r
+       sha256h2.32     q0,q1,q2\r
+       sha256su0.32    q0,q1\r
+       sha256su1.32    q0,q1,q2\r
+\r
+       vmull.p64       q0,d1,d2\r

diff --git a/armdoc/InstructionFormatsTHUMB16.asm b/armdoc/InstructionFormatsTHUMB16.asm
new file mode 100644 (file)
index 0000000..42f492a
--- /dev/null
+++ b/armdoc/InstructionFormatsTHUMB16.asm
@@ -0,0 +1,477 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition or flag\r
+;writeback ("s") syntaxes. Almost all instructions can\r
+;be conditional. The condition code should be added at\r
+;the end of the main opcode and before any size/type\r
+;specifiers. For example: "addhi" and "vaddhi.i16". The\r
+;syntax also supports the pre-UAL style of putting the\r
+;condition before any modifiers like "s" or "fd". For\r
+;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;THUMB mode, pre-UAL 16-bit instructions\r
+       ;***********************************************\r
+\r
+       code16                                          ;pre-UAL syntax, the 's' is otional\r
+\r
+macro align {times(($ and 2)shr 1)dh 0xde_00}\r
+\r
+processor CPU32_V4T\r
+\r
+       adc     r0,r1\r
+       adc     r0,r0,r1\r
+\r
+       add     r0,r1,2\r
+       add     r0,1\r
+       add     r0,r1,r2\r
+       add     r0,r0,3\r
+\r
+       and     r0,r1\r
+       and     r0,r0,r1\r
+\r
+       asr     r0,1\r
+       asr     r0,r1,2\r
+       asr     r0,r1\r
+       asr     r0,r0,r1\r
+\r
+       bic     r0,r1\r
+       bic     r0,r0,r1\r
+\r
+       eor     r0,r1\r
+       eor     r0,r0,r1\r
+\r
+       ldm     r0!,{r1}\r
+       ldm     r0!,{r0}\r
+\r
+       ldmia   r0!,{r1}\r
+       ldmia   r0!,{r0}\r
+\r
+       lsl     r0,1\r
+       lsl     r0,r1,2\r
+       lsl     r0,r1\r
+       lsl     r0,r0,r1\r
+\r
+       lsr     r0,1\r
+       lsr     r0,r1,2\r
+       lsr     r0,r1\r
+       lsr     r0,r0,r1\r
+\r
+       mov     r0,1\r
+       mov     r0,r1\r
+       mov     r0,expression.dword\r
+\r
+       mul     r0,r1\r
+       mul     r0,r1,r0\r
+       mul     r0,r0,r1\r
+\r
+       mvn     r0,r1\r
+\r
+       neg     r0\r
+       neg     r0,r1\r
+\r
+       orr     r0,r1\r
+       orr     r0,r0,r1\r
+\r
+       ror     r0,r1\r
+       ror     r0,r0,r1\r
+\r
+       rsb     r0,0\r
+       rsb     r0,r1,0\r
+\r
+       sbc     r0,r1\r
+       sbc     r0,r0,r1\r
+\r
+       sub     r0,r1,2\r
+       sub     r0,1\r
+       sub     r0,r1,r2\r
+       sub     r0,r0,3\r
+\r
+       ;***********************************************\r
+       ;THUMB mode, UAL 16-bit instructions\r
+       ;***********************************************\r
+\r
+       thumb                                           ;UAL syntax, the 's', if given, is mandatory\r
+\r
+       adcs    r0,r1\r
+       adcs    r0,r0,r1\r
+\r
+       adds    r0,r1,2\r
+       adds    r0,1\r
+       adds    r0,r1,r2\r
+\r
+       ands    r0,r1\r
+       ands    r0,r0,r1\r
+\r
+       asrs    r0,1\r
+       asrs    r0,r1,2\r
+       asrs    r0,r1\r
+       asrs    r0,r0,r1\r
+\r
+       bics    r0,r1\r
+       bics    r0,r0,r1\r
+\r
+       eors    r0,r1\r
+       eors    r0,r0,r1\r
+\r
+       ldm     r0!,{r1}\r
+       ldm     r0,{r0}\r
+\r
+       ldmia   r0!,{r1}\r
+       ldmia   r0,{r0}\r
+\r
+       lsls    r0,1\r
+       lsls    r0,r1,2\r
+       lsls    r0,r1\r
+       lsls    r0,r0,r1\r
+\r
+       lsrs    r0,1\r
+       lsrs    r0,r1,2\r
+       lsrs    r0,r1\r
+       lsrs    r0,r0,r1\r
+\r
+       movs    r0,1\r
+       movs    r0,r1\r
+       movs    r0,expression.dword\r
+\r
+       muls    r0,r1\r
+       muls    r0,r1,r0\r
+       muls    r0,r0,r1\r
+\r
+       mvns    r0,r1\r
+\r
+       negs    r0\r
+       negs    r0,r1\r
+\r
+       orrs    r0,r1\r
+       orrs    r0,r0,r1\r
+\r
+       rors    r0,r1\r
+       rors    r0,r0,r1\r
+\r
+       rsbs    r0,0\r
+       rsbs    r0,r1,0\r
+\r
+       sbcs    r0,r1\r
+       sbcs    r0,r0,r1\r
+\r
+       subs    r0,r1,2\r
+       subs    r0,1\r
+       subs    r0,r1,r2\r
+\r
+       ;both pre-UAL and UAL syntaxes, no 's' is allowed\r
+\r
+       add     r8,r9\r
+       add     r0,sp,4\r
+       add     sp,4\r
+       add     sp,sp,4\r
+       add     r0,pc,4\r
+\r
+       adr     r0,label_adr_t16\r
+       align\r
+       label_adr_t16:\r
+\r
+       bx      r0\r
+\r
+       cmn     r0,r1\r
+\r
+       cmp     r0,1\r
+       cmp     r0,r1\r
+       cmp     r8,r9\r
+\r
+       ldr     r0,[r1]\r
+       ldr     r0,[r1,4]\r
+       ldr     r0,[sp]\r
+       ldr     r0,[sp,4]\r
+       ldr     r0,[label_ldr_t16]\r
+       ldr     r0,[pc]\r
+       ldr     r0,[pc,4]\r
+       ldr     r0,[r1,r2]\r
+       ldr     r1,[sp],4\r
+       ldr     r15,[sp],4\r
+       align\r
+       label_ldr_t16:\r
+\r
+       ldrb    r0,[r1]\r
+       ldrb    r0,[r1,2]\r
+       ldrb    r0,[r1,r2]\r
+\r
+       ldrh    r0,[r1]\r
+       ldrh    r0,[r1,2]\r
+       ldrh    r0,[r1,r2]\r
+\r
+       ldrsb   r0,[r1,r2]\r
+\r
+       ldrsh   r0,[r1,r2]\r
+\r
+       mov     r8,r9\r
+\r
+       nop\r
+\r
+       pop     {r0}\r
+       pop     {r0,r15}\r
+\r
+       push    {r0}\r
+       push    {r0,r14}\r
+\r
+       stm     r0!,{r1}\r
+       stm     r0!,{r1,r2}\r
+\r
+       stmia   r0!,{r1}\r
+       stmia   r0!,{r1,r2}\r
+\r
+       str     r0,[r1]\r
+       str     r0,[r1,4]\r
+       str     r0,[sp]\r
+       str     r0,[sp,4]\r
+       str     r0,[r1,r2]\r
+       str     r1,[sp,-4]!\r
+       str     r14,[sp,-4]!\r
+\r
+       strb    r0,[r1]\r
+       strb    r0,[r1,4]\r
+       strb    r0,[r1,r2]\r
+\r
+       strh    r0,[r1]\r
+       strh    r0,[r1,4]\r
+       strb    r0,[r1,r2]\r
+\r
+       sub     sp,4\r
+       sub     sp,sp,4\r
+\r
+       svc     0\r
+\r
+       swi     0\r
+\r
+       tst     r0,r1\r
+\r
+       bcc     label_bcc_t16\r
+       label_bcc_t16:\r
+\r
+       b       label_b_t16\r
+       label_b_t16:\r
+\r
+processor CPU32_V5T\r
+\r
+       bkpt    0\r
+\r
+       blx     r0\r
+\r
+processor CPU32_V6T\r
+\r
+       cpy     r0,r1\r
+\r
+       rev     r0,r1\r
+\r
+       rev16   r0,r1\r
+\r
+       revsh   r0,r1\r
+\r
+       sxtb    r0\r
+       sxtb    r0,r1\r
+\r
+       sxth    r0\r
+       sxth    r0,r1\r
+\r
+       uxtb    r0\r
+       uxtb    r0,r1\r
+\r
+       uxth    r0\r
+       uxth    r0,r1\r
+\r
+processor CPU32_ALIGN\r
+\r
+       cpsie   iflags_a\r
+\r
+       cpsid   iflags_a\r
+\r
+       setend  le\r
+\r
+processor CPU32_6M\r
+\r
+       add     r0,r1\r
+\r
+       yield\r
+\r
+       wfe\r
+\r
+       wfi\r
+\r
+       sev\r
+\r
+processor CPU32_7M\r
+\r
+       cbnz    r0,label_cbnz_t16\r
+       dh      0xde00\r
+       label_cbnz_t16:\r
+\r
+       cbz     r0,label_cbz_t16\r
+       dh      0xde00\r
+       label_cbz_t16:\r
+\r
+processor CPU32_7M + CPU32_V5T\r
+\r
+       it      cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ite     cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itee    cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       iteee   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       iteet   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itet    cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itete   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itett   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itt     cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itte    cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ittee   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ittet   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ittt    cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ittte   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       itttt   cc\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+       bkpt    0       ;dummy fill to satisfy IT checks\r
+\r
+       ;***********************************************\r
+       ;THUMBEE mode, 16-bit instructions\r
+       ;***********************************************\r
+\r
+       thumbee\r
+\r
+processor CPU32_T2EE\r
+\r
+       chka    r0,r1\r
+\r
+       hb      0\r
+       hbl     0\r
+       hblp    0,0\r
+       hbp     0,0\r
+\r
+       ldr     r0,[r1,r2,lsl 2]\r
+       ldr     r0,[r1,-4]\r
+       ldr     r0,[r9]\r
+       ldr     r0,[r9,4]\r
+       ldr     r0,[r10]\r
+       ldr     r0,[r10,4]\r
+\r
+       ldrb    r0,[r1,r2]\r
+\r
+       ldrh    r0,[r1,r2,lsl 1]\r
+\r
+       ldrsb   r0,[r1,r2]\r
+\r
+       ldrsh   r0,[r1,r2,lsl 1]\r
+\r
+       str     r0,[r1,r2,lsl 2]\r
+       str     r0,[r9]\r
+       str     r0,[r9,4]\r
+\r
+       strb    r0,[r1,r2]\r
+\r
+       strh    r0,[r1,r2,lsl 1]\r
+\r
+processor CPU32_V8\r
+\r
+       hlt     0\r
+\r
+       sevl\r
+       sevl.n\r
+\r
+processor 0    ;16-bit UND is always encodable, it ignores the processor directive\r
+\r
+       und\r
+       und     0\r

diff --git a/armdoc/InstructionFormatsTHUMB32.asm b/armdoc/InstructionFormatsTHUMB32.asm
new file mode 100644 (file)
index 0000000..67b0ba3
--- /dev/null
+++ b/armdoc/InstructionFormatsTHUMB32.asm
@@ -0,0 +1,1226 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition or flag\r
+;writeback ("s") syntaxes. Almost all instructions can\r
+;be conditional. The condition code should be added at\r
+;the end of the main opcode and before any size/type\r
+;specifiers. For example: "addhi" and "vaddhi.i16". The\r
+;syntax also supports the pre-UAL style of putting the\r
+;condition before any modifiers like "s" or "fd". For\r
+;example: "ldmhifd", "ldmfdhi" and "addhis", "addshi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;THUMB mode, 32-bit instructions\r
+       ;***********************************************\r
+\r
+       thumb\r
+\r
+processor CPU32_V4T\r
+\r
+       label_bl_t32:\r
+       bl      label_bl_t32\r
+\r
+processor CPU32_X\r
+\r
+       label_blx_t32:\r
+       blx     label_blx_t32\r
+\r
+processor CPU32_Z\r
+\r
+       smc     0\r
+\r
+       smi     0\r
+\r
+processor CPU32_6M\r
+\r
+       dmb\r
+       dmb     sy\r
+\r
+       dsb\r
+       dsb     sy\r
+\r
+       isb\r
+       isb     sy\r
+\r
+       mrs     r0,primask\r
+\r
+       msr     primask,r0\r
+\r
+processor CPU32_7M\r
+\r
+       adc     r0,1\r
+       adc     r0,r1\r
+       adc     r0,r1,rrx\r
+       adc     r0,r1,lsl 2\r
+       adc     r0,r1,lsr 2\r
+       adc     r0,r1,asr 2\r
+       adc     r0,r1,ror 2\r
+       adc     r0,r1,2\r
+       adc     r0,r1,r2\r
+       adc     r0,r1,r2,rrx\r
+       adc     r0,r1,r2,lsl 3\r
+       adc     r0,r1,r2,lsr 3\r
+       adc     r0,r1,r2,asr 3\r
+       adc     r0,r1,r2,ror 3\r
+\r
+       add     r0,1\r
+       add     r0,r1\r
+       add     r0,r1,rrx\r
+       add     r0,r1,lsl 2\r
+       add     r0,r1,lsr 2\r
+       add     r0,r1,asr 2\r
+       add     r0,r1,ror 2\r
+       add     r0,r1,2\r
+       add     r0,r1,r2\r
+       add     r0,r1,r2,rrx\r
+       add     r0,r1,r2,lsl 3\r
+       add     r0,r1,r2,lsr 3\r
+       add     r0,r1,r2,asr 3\r
+       add     r0,r1,r2,ror 3\r
+\r
+       addw    r0,1\r
+       addw    r0,r1,2\r
+\r
+       label_adr_t32:\r
+       adr     r0,label_adr_t32\r
+\r
+       and     r0,1\r
+       and     r0,r1\r
+       and     r0,r1,rrx\r
+       and     r0,r1,lsl 2\r
+       and     r0,r1,lsr 2\r
+       and     r0,r1,asr 2\r
+       and     r0,r1,ror 2\r
+       and     r0,r1,2\r
+       and     r0,r1,r2\r
+       and     r0,r1,r2,rrx\r
+       and     r0,r1,r2,lsl 3\r
+       and     r0,r1,r2,lsr 3\r
+       and     r0,r1,r2,asr 3\r
+       and     r0,r1,r2,ror 3\r
+\r
+       asr     r0,1\r
+       asr     r0,r1\r
+       asr     r0,r1,2\r
+       asr     r0,r1,r2\r
+\r
+       label_b_t32:\r
+       b       label_b_t32\r
+\r
+       label_bcc_t32:\r
+       bcc     label_bcc_t32\r
+\r
+       bfc     r0,1,2\r
+\r
+       bfi     r0,r1,2,3\r
+\r
+       bic     r0,1\r
+       bic     r0,r1\r
+       bic     r0,r1,rrx\r
+       bic     r0,r1,lsl 2\r
+       bic     r0,r1,lsr 2\r
+       bic     r0,r1,asr 2\r
+       bic     r0,r1,ror 2\r
+       bic     r0,r1,2\r
+       bic     r0,r1,r2\r
+       bic     r0,r1,r2,rrx\r
+       bic     r0,r1,r2,lsl 3\r
+       bic     r0,r1,r2,lsr 3\r
+       bic     r0,r1,r2,asr 3\r
+       bic     r0,r1,r2,ror 3\r
+\r
+       cdp     p9,1,c2,c3,c4\r
+       cdp     p9,1,c2,c3,c4,5\r
+\r
+       cdp2    p9,1,c2,c3,c4\r
+       cdp2    p9,1,c2,c3,c4,5\r
+\r
+       clrex\r
+\r
+       clz     r0,r1\r
+\r
+       cmn     r0,1\r
+       cmn     r0,r1\r
+       cmn     r0,r1,rrx\r
+       cmn     r0,r1,lsl 2\r
+       cmn     r0,r1,lsr 2\r
+       cmn     r0,r1,asr 2\r
+       cmn     r0,r1,ror 2\r
+\r
+       cmp     r0,1\r
+       cmp     r0,r1\r
+       cmp     r0,r1,rrx\r
+       cmp     r0,r1,lsl 2\r
+       cmp     r0,r1,lsr 2\r
+       cmp     r0,r1,asr 2\r
+       cmp     r0,r1,ror 2\r
+\r
+       cpy     r0,r1\r
+\r
+       dbg     0\r
+\r
+       eor     r0,1\r
+       eor     r0,r1\r
+       eor     r0,r1,rrx\r
+       eor     r0,r1,lsl 2\r
+       eor     r0,r1,lsr 2\r
+       eor     r0,r1,asr 2\r
+       eor     r0,r1,ror 2\r
+       eor     r0,r1,2\r
+       eor     r0,r1,r2\r
+       eor     r0,r1,r2,rrx\r
+       eor     r0,r1,r2,lsl 3\r
+       eor     r0,r1,r2,lsr 3\r
+       eor     r0,r1,r2,asr 3\r
+       eor     r0,r1,r2,ror 3\r
+\r
+       label_ldc_t32:\r
+       ldc     p9,c1,[r2]\r
+       ldc     p9,c1,[r2],4\r
+       ldc     p9,c1,[r2],{4}\r
+       ldc     p9,c1,[r2,4]\r
+       ldc     p9,c1,[r2,4]!\r
+       ldc     p9,c1,[label_ldc_t32]\r
+       ldc     p9,c1,[expression.word]\r
+       ldc     p9,c1,[expression.word]!\r
+\r
+       label_ldc2_t32:\r
+       ldc2    p9,c1,[r2]\r
+       ldc2    p9,c1,[r2],4\r
+       ldc2    p9,c1,[r2],{4}\r
+       ldc2    p9,c1,[r2,4]\r
+       ldc2    p9,c1,[r2,4]!\r
+       ldc2    p9,c1,[label_ldc2_t32]\r
+       ldc2    p9,c1,[expression.word]\r
+       ldc2    p9,c1,[expression.word]!\r
+\r
+       label_ldc2l_t32:\r
+       ldc2l   p9,c1,[r2]\r
+       ldc2l   p9,c1,[r2],4\r
+       ldc2l   p9,c1,[r2],{4}\r
+       ldc2l   p9,c1,[r2,4]\r
+       ldc2l   p9,c1,[r2,4]!\r
+       ldc2l   p9,c1,[label_ldc2l_t32]\r
+       ldc2l   p9,c1,[expression.word]\r
+       ldc2l   p9,c1,[expression.word]!\r
+\r
+       label_ldcl_t32:\r
+       ldcl    p9,c1,[r2]\r
+       ldcl    p9,c1,[r2],4\r
+       ldcl    p9,c1,[r2],{4}\r
+       ldcl    p9,c1,[r2,4]\r
+       ldcl    p9,c1,[r2,4]!\r
+       ldcl    p9,c1,[label_ldcl_t32]\r
+       ldcl    p9,c1,[expression.word]\r
+       ldcl    p9,c1,[expression.word]!\r
+\r
+       ldm     r0,{r1}\r
+       ldm     r0,{r1,r2}\r
+       ldm     r0,{r1-r3}\r
+       ldm     r0,{r1-r3,r5}\r
+       ldm     r0!,{r1}\r
+       ldm     r0!,{r1,r2}\r
+       ldm     r0!,{r1-r3}\r
+       ldm     r0!,{r1-r3,r5}\r
+\r
+       ldmia   r0,{r1}\r
+       ldmia   r0,{r1,r2}\r
+       ldmia   r0,{r1-r3}\r
+       ldmia   r0,{r1-r3,r5}\r
+       ldmia   r0!,{r1}\r
+       ldmia   r0!,{r1,r2}\r
+       ldmia   r0!,{r1-r3}\r
+       ldmia   r0!,{r1-r3,r5}\r
+\r
+       ldmdb   r0,{r1}\r
+       ldmdb   r0,{r1,r2}\r
+       ldmdb   r0,{r1-r3}\r
+       ldmdb   r0,{r1-r3,r5}\r
+       ldmdb   r0!,{r1}\r
+       ldmdb   r0!,{r1,r2}\r
+       ldmdb   r0!,{r1-r3}\r
+       ldmdb   r0!,{r1-r3,r5}\r
+\r
+       ldmea   r0,{r1}\r
+       ldmea   r0,{r1,r2}\r
+       ldmea   r0,{r1-r3}\r
+       ldmea   r0,{r1-r3,r5}\r
+       ldmea   r0!,{r1}\r
+       ldmea   r0!,{r1,r2}\r
+       ldmea   r0!,{r1-r3}\r
+       ldmea   r0!,{r1-r3,r5}\r
+\r
+       ldmfd   r0,{r1}\r
+       ldmfd   r0,{r1,r2}\r
+       ldmfd   r0,{r1-r3}\r
+       ldmfd   r0,{r1-r3,r5}\r
+       ldmfd   r0!,{r1}\r
+       ldmfd   r0!,{r1,r2}\r
+       ldmfd   r0!,{r1-r3}\r
+       ldmfd   r0!,{r1-r3,r5}\r
+\r
+       label_ldr_t32:\r
+       ldr     r0,[r1]\r
+       ldr     r0,[r1],2\r
+       ldr     r0,[r1],4\r
+       ldr     r0,[r1,2]\r
+       ldr     r0,[r1,2]!\r
+       ldr     r0,[r1,r2]\r
+       ldr     r0,[r1,r2,lsl 3]\r
+       ldr     r0,[label_ldr_t32]\r
+       ldr     r0,[expression.word]\r
+       ldr     r0,[expression.word]!\r
+\r
+       label_ldrb_t32:\r
+       ldrb    r0,[r1]\r
+       ldrb    r0,[r1],2\r
+       ldrb    r0,[r1],4\r
+       ldrb    r0,[r1,2]\r
+       ldrb    r0,[r1,2]!\r
+       ldrb    r0,[r1,r2]\r
+       ldrb    r0,[r1,r2,lsl 3]\r
+       ldrb    r0,[label_ldrb_t32]\r
+       ldrb    r0,[expression.byte]\r
+       ldrb    r0,[expression.byte]!\r
+\r
+       ldrb    r0,[r13]\r
+       ldrb    r0,[r13,2]\r
+       ldrb    r0,[r13,r2]\r
+\r
+       ldrbt   r0,[r1]\r
+       ldrbt   r0,[r1,2]\r
+       ldrbt   r0,[expression.byte]\r
+\r
+       label_ldrd_t32:\r
+       ldrd    r0,[r1]\r
+       ldrd    r0,[r2],4\r
+       ldrd    r0,[r1,4]\r
+       ldrd    r0,[r2,4]!\r
+       ldrd    r0,[label_ldrd_t32]\r
+       ldrd    r2,[expression.dword]\r
+       ldrd    r2,[expression.dword]!\r
+       ldrd    r0,r1,[r2]\r
+       ldrd    r0,r1,[r2],4\r
+       ldrd    r0,r1,[r2,4]\r
+       ldrd    r0,r1,[r2,4]!\r
+       ldrd    r0,r1,[label_ldrd_t32]\r
+       ldrd    r0,r2,[expression.dword]\r
+       ldrd    r0,r2,[expression.dword]!\r
+\r
+       ldrex   r0,[r1]\r
+       ldrex   r0,[r1,4]\r
+       ldrex   r0,[expression.word]\r
+\r
+       label_ldrh_t32:\r
+       ldrh    r0,[r1]\r
+       ldrh    r0,[r1],2\r
+       ldrh    r0,[r1],4\r
+       ldrh    r0,[r1,2]\r
+       ldrh    r0,[r1,2]!\r
+       ldrh    r0,[r1,r2]\r
+       ldrh    r0,[r1,r2,lsl 3]\r
+       ldrh    r0,[label_ldrh_t32]\r
+       ldrh    r0,[expression.hword]\r
+       ldrh    r0,[expression.hword]!\r
+\r
+       ldrh    r0,[r13]\r
+       ldrh    r0,[r13,2]\r
+       ldrh    r0,[r13,r2]\r
+\r
+       ldrht   r0,[r1]\r
+       ldrht   r0,[r1,2]\r
+       ldrht   r0,[expression.hword]\r
+\r
+       label_ldrsb_t32:\r
+       ldrsb   r0,[r1]\r
+       ldrsb   r0,[r1],2\r
+       ldrsb   r0,[r1],4\r
+       ldrsb   r0,[r1,2]\r
+       ldrsb   r0,[r1,2]!\r
+       ldrsb   r0,[r1,r2]\r
+       ldrsb   r0,[r1,r2,lsl 3]\r
+       ldrsb   r0,[label_ldrsb_t32]\r
+       ldrsb   r0,[expression.byte]\r
+       ldrsb   r0,[expression.byte]!\r
+\r
+       ldrsbt  r0,[r1]\r
+       ldrsbt  r0,[r1,2]\r
+       ldrsbt  r0,[expression.byte]\r
+\r
+       label_ldrsh_t32:\r
+       ldrsh   r0,[r1]\r
+       ldrsh   r0,[r1],2\r
+       ldrsh   r0,[r1],4\r
+       ldrsh   r0,[r1,2]\r
+       ldrsh   r0,[r1,2]!\r
+       ldrsh   r0,[r1,r2]\r
+       ldrsh   r0,[r1,r2,lsl 3]\r
+       ldrsh   r0,[label_ldrsh_t32]\r
+       ldrsh   r0,[expression.hword]\r
+       ldrsh   r0,[expression.hword]!\r
+\r
+       ldrsht  r0,[r1]\r
+       ldrsht  r0,[r1,2]\r
+       ldrsht  r0,[expression.hword]\r
+\r
+       ldrt    r0,[r1]\r
+       ldrt    r0,[r1,2]\r
+       ldrt    r0,[expression.word]\r
+\r
+       lsl     r0,1\r
+       lsl     r0,r1\r
+       lsl     r0,r1,2\r
+       lsl     r0,r1,r2\r
+\r
+       lsr     r0,1\r
+       lsr     r0,r1\r
+       lsr     r0,r1,2\r
+       lsr     r0,r1,r2\r
+\r
+       mcr     p9,1,r2,c3,c4\r
+       mcr     p9,1,r2,c3,c4,5\r
+\r
+       mcr2    p9,1,r2,c3,c4\r
+       mcr2    p9,1,r2,c3,c4,5\r
+\r
+       mcrr    p9,1,r2,r3,c4\r
+\r
+       mcrr2   p9,1,r2,r3,c4\r
+\r
+       mla     r0,r1,r2,r3\r
+\r
+       mls     r0,r1,r2,r3\r
+\r
+       mov     r0,1\r
+       mov     r0,r1\r
+       mov     r0,r1,rrx\r
+       mov     r0,r1,lsl 2\r
+       mov     r0,r1,lsr 2\r
+       mov     r0,r1,asr 2\r
+       mov     r0,r1,ror 2\r
+       mov     r0,r1,lsl r2\r
+       mov     r0,r1,lsr r2\r
+       mov     r0,r1,asr r2\r
+       mov     r0,r1,ror r2\r
+       mov     r0,expression.word\r
+\r
+       movt    r0,1\r
+\r
+       movw    r0,1\r
+\r
+       mrc     p9,1,r2,c3,c4\r
+       mrc     p9,1,r15,c3,c4,5\r
+\r
+       mrc2    p9,1,r2,c3,c4\r
+       mrc2    p9,1,r15,c3,c4,5\r
+\r
+       mrrc    p9,1,r2,r3,c4\r
+\r
+       mrrc2   p9,1,r2,r3,c4\r
+\r
+       mrs     r0,basepri\r
+\r
+       msr     basepri,r0\r
+\r
+       mul     r0,r1\r
+       mul     r0,r1,r2\r
+\r
+       mvn     r0,1\r
+       mvn     r0,r1\r
+       mvn     r0,r1,rrx\r
+       mvn     r0,r1,lsl 2\r
+       mvn     r0,r1,lsr 2\r
+       mvn     r0,r1,asr 2\r
+       mvn     r0,r1,ror 2\r
+\r
+       neg     r0\r
+       neg     r0,r1\r
+\r
+       nop\r
+\r
+       orn     r0,1\r
+       orn     r0,r1\r
+       orn     r0,r1,rrx\r
+       orn     r0,r1,lsl 2\r
+       orn     r0,r1,lsr 2\r
+       orn     r0,r1,asr 2\r
+       orn     r0,r1,ror 2\r
+       orn     r0,r1,2\r
+       orn     r0,r1,r2\r
+       orn     r0,r1,r2,rrx\r
+       orn     r0,r1,r2,lsl 3\r
+       orn     r0,r1,r2,lsr 3\r
+       orn     r0,r1,r2,asr 3\r
+       orn     r0,r1,r2,ror 3\r
+\r
+       orr     r0,1\r
+       orr     r0,r1\r
+       orr     r0,r1,rrx\r
+       orr     r0,r1,lsl 2\r
+       orr     r0,r1,lsr 2\r
+       orr     r0,r1,asr 2\r
+       orr     r0,r1,ror 2\r
+       orr     r0,r1,2\r
+       orr     r0,r1,r2\r
+       orr     r0,r1,r2,rrx\r
+       orr     r0,r1,r2,lsl 3\r
+       orr     r0,r1,r2,lsr 3\r
+       orr     r0,r1,r2,asr 3\r
+       orr     r0,r1,r2,ror 3\r
+\r
+       label_pld_t32:\r
+       pld     [r1]\r
+       pld     [r1,2]\r
+       pld     [r1,r2]\r
+       pld     [r1,r2,lsl 3]\r
+       pld     [label_pld_t32]\r
+       pld     [expression.byte]\r
+\r
+       pop     {r0}\r
+       pop     {r0,r1}\r
+       pop     {r0-r2}\r
+       pop     {r0-r2,r4}\r
+\r
+       push    {r0}\r
+       push    {r0,r1}\r
+       push    {r0-r2}\r
+       push    {r0-r2,r4}\r
+\r
+       rbit    r0,r1\r
+\r
+       rev     r0,r1\r
+\r
+       rev16   r0,r1\r
+\r
+       revsh   r0,r1\r
+\r
+       ror     r0,1\r
+       ror     r0,r1\r
+       ror     r0,r1,2\r
+       ror     r0,r1,r2\r
+\r
+       rrx     r0\r
+       rrx     r0,r1\r
+\r
+       rsb     r0,1\r
+       rsb     r0,r1\r
+       rsb     r0,r1,rrx\r
+       rsb     r0,r1,lsl 2\r
+       rsb     r0,r1,lsr 2\r
+       rsb     r0,r1,asr 2\r
+       rsb     r0,r1,ror 2\r
+       rsb     r0,r1,2\r
+       rsb     r0,r1,r2\r
+       rsb     r0,r1,r2,rrx\r
+       rsb     r0,r1,r2,lsl 3\r
+       rsb     r0,r1,r2,lsr 3\r
+       rsb     r0,r1,r2,asr 3\r
+       rsb     r0,r1,r2,ror 3\r
+\r
+       sbc     r0,1\r
+       sbc     r0,r1\r
+       sbc     r0,r1,rrx\r
+       sbc     r0,r1,lsl 2\r
+       sbc     r0,r1,lsr 2\r
+       sbc     r0,r1,asr 2\r
+       sbc     r0,r1,ror 2\r
+       sbc     r0,r1,2\r
+       sbc     r0,r1,r2\r
+       sbc     r0,r1,r2,rrx\r
+       sbc     r0,r1,r2,lsl 3\r
+       sbc     r0,r1,r2,lsr 3\r
+       sbc     r0,r1,r2,asr 3\r
+       sbc     r0,r1,r2,ror 3\r
+\r
+       sbfx    r0,r1,2,3\r
+\r
+       sev\r
+\r
+       smlal   r0,r1,r2,r3\r
+\r
+       smull   r0,r1,r2,r3\r
+\r
+       label_stc_t32:\r
+       stc     p9,c1,[r2]\r
+       stc     p9,c1,[r2],4\r
+       stc     p9,c1,[r2],{4}\r
+       stc     p9,c1,[r2,4]\r
+       stc     p9,c1,[r2,4]!\r
+       stc     p9,c1,[label_stc_t32]\r
+       stc     p9,c1,[expression.word]\r
+       stc     p9,c1,[expression.word]!\r
+\r
+       label_stc2_t32:\r
+       stc2    p9,c1,[r2]\r
+       stc2    p9,c1,[r2],4\r
+       stc2    p9,c1,[r2],{4}\r
+       stc2    p9,c1,[r2,4]\r
+       stc2    p9,c1,[r2,4]!\r
+       stc2    p9,c1,[label_stc2_t32]\r
+       stc2    p9,c1,[expression.word]\r
+       stc2    p9,c1,[expression.word]!\r
+\r
+       label_stc2l_t32:\r
+       stc2l   p9,c1,[r2]\r
+       stc2l   p9,c1,[r2],4\r
+       stc2l   p9,c1,[r2],{4}\r
+       stc2l   p9,c1,[r2,4]\r
+       stc2l   p9,c1,[r2,4]!\r
+       stc2l   p9,c1,[label_stc2l_t32]\r
+       stc2l   p9,c1,[expression.word]\r
+       stc2l   p9,c1,[expression.word]!\r
+\r
+       label_stcl_t32:\r
+       stcl    p9,c1,[r2]\r
+       stcl    p9,c1,[r2],4\r
+       stcl    p9,c1,[r2],{4}\r
+       stcl    p9,c1,[r2,4]\r
+       stcl    p9,c1,[r2,4]!\r
+       stcl    p9,c1,[label_stcl_t32]\r
+       stcl    p9,c1,[expression.word]\r
+       stcl    p9,c1,[expression.word]!\r
+\r
+       stm     r0,{r1}\r
+       stm     r0,{r1,r2}\r
+       stm     r0,{r1-r3}\r
+       stm     r0,{r1-r3,r5}\r
+       stm     r0!,{r1}\r
+       stm     r0!,{r1,r2}\r
+       stm     r0!,{r1-r3}\r
+       stm     r0!,{r1-r3,r5}\r
+\r
+       stmia   r0,{r1}\r
+       stmia   r0,{r1,r2}\r
+       stmia   r0,{r1-r3}\r
+       stmia   r0,{r1-r3,r5}\r
+       stmia   r0!,{r1}\r
+       stmia   r0!,{r1,r2}\r
+       stmia   r0!,{r1-r3}\r
+       stmia   r0!,{r1-r3,r5}\r
+\r
+       stmdb   r0,{r1}\r
+       stmdb   r0,{r1,r2}\r
+       stmdb   r0,{r1-r3}\r
+       stmdb   r0,{r1-r3,r5}\r
+       stmdb   r0!,{r1}\r
+       stmdb   r0!,{r1,r2}\r
+       stmdb   r0!,{r1-r3}\r
+       stmdb   r0!,{r1-r3,r5}\r
+\r
+       stmea   r0,{r1}\r
+       stmea   r0,{r1,r2}\r
+       stmea   r0,{r1-r3}\r
+       stmea   r0,{r1-r3,r5}\r
+       stmea   r0!,{r1}\r
+       stmea   r0!,{r1,r2}\r
+       stmea   r0!,{r1-r3}\r
+       stmea   r0!,{r1-r3,r5}\r
+\r
+       stmfd   r0,{r1}\r
+       stmfd   r0,{r1,r2}\r
+       stmfd   r0,{r1-r3}\r
+       stmfd   r0,{r1-r3,r5}\r
+       stmfd   r0!,{r1}\r
+       stmfd   r0!,{r1,r2}\r
+       stmfd   r0!,{r1-r3}\r
+       stmfd   r0!,{r1-r3,r5}\r
+\r
+       str     r0,[r1]\r
+       str     r0,[r1],2\r
+       str     r0,[r1,2]\r
+       str     r0,[r1,2]!\r
+       str     r0,[r1,r2]\r
+       str     r0,[r1,r2,lsl 3]\r
+       str     r0,[expression.word]\r
+       str     r0,[expression.word]!\r
+\r
+       strb    r0,[r1]\r
+       strb    r0,[r1],2\r
+       strb    r0,[r1,2]\r
+       strb    r0,[r1,2]!\r
+       strb    r0,[r1,r2]\r
+       strb    r0,[r1,r2,lsl 3]\r
+       strb    r0,[expression.byte]\r
+       strb    r0,[expression.byte]!\r
+\r
+       strbt   r0,[r1]\r
+       strbt   r0,[r1,2]\r
+       strbt   r0,[expression.byte]\r
+\r
+       strd    r0,[r1]\r
+       strd    r0,[r2],4\r
+       strd    r0,[r1,4]\r
+       strd    r0,[r2,4]!\r
+       strd    r2,[expression.dword]\r
+       strd    r2,[expression.dword]!\r
+       strd    r0,r1,[r2]\r
+       strd    r0,r1,[r2],4\r
+       strd    r0,r1,[r2,4]\r
+       strd    r0,r1,[r2,4]!\r
+       strd    r0,r2,[expression.dword]\r
+       strd    r0,r2,[expression.dword]!\r
+\r
+       strex   r0,r1,[r2]\r
+       strex   r0,r1,[r2,4]\r
+       strex   r2,r4,[expression.word]\r
+\r
+       strh    r0,[r1]\r
+       strh    r0,[r1],2\r
+       strh    r0,[r1,2]\r
+       strh    r0,[r1,2]!\r
+       strh    r0,[r1,r2]\r
+       strh    r0,[r1,r2,lsl 3]\r
+       strh    r0,[expression.hword]\r
+       strh    r0,[expression.hword]!\r
+\r
+       strht   r0,[r1]\r
+       strht   r0,[r1,2]\r
+       strht   r0,[expression.hword]\r
+\r
+       strt    r0,[r1]\r
+       strt    r0,[r1,2]\r
+       strt    r0,[expression.word]\r
+\r
+       sub     r0,1\r
+       sub     r0,r1\r
+       sub     r0,r1,rrx\r
+       sub     r0,r1,lsl 2\r
+       sub     r0,r1,lsr 2\r
+       sub     r0,r1,asr 2\r
+       sub     r0,r1,ror 2\r
+       sub     r0,r1,2\r
+       sub     r0,r1,r2\r
+       sub     r0,r1,r2,rrx\r
+       sub     r0,r1,r2,lsl 3\r
+       sub     r0,r1,r2,lsr 3\r
+       sub     r0,r1,r2,asr 3\r
+       sub     r0,r1,r2,ror 3\r
+\r
+       subw    r0,1\r
+       subw    r0,r1,2\r
+\r
+       sxtb    r0,r1\r
+       sxtb    r0,r1,ror 8\r
+\r
+       sxth    r0,r1\r
+       sxth    r0,r1,ror 8\r
+\r
+       tbb     [r0,r1]\r
+\r
+       tbh     [r0,r1,lsl 1]\r
+\r
+       teq     r0,1\r
+       teq     r0,r1\r
+       teq     r0,r1,rrx\r
+       teq     r0,r1,lsl 2\r
+       teq     r0,r1,lsr 2\r
+       teq     r0,r1,asr 2\r
+       teq     r0,r1,ror 2\r
+\r
+       tst     r0,1\r
+       tst     r0,r1\r
+       tst     r0,r1,rrx\r
+       tst     r0,r1,lsl 2\r
+       tst     r0,r1,lsr 2\r
+       tst     r0,r1,asr 2\r
+       tst     r0,r1,ror 2\r
+\r
+       ubfx    r0,r1,2,3\r
+\r
+       umlal   r0,r1,r2,r3\r
+\r
+       umull   r0,r1,r2,r3\r
+\r
+       und.w\r
+       und     0x100\r
+\r
+       uxtb    r0,r1\r
+       uxtb    r0,r1,ror 8\r
+\r
+       uxth    r0,r1\r
+       uxth    r0,r1,ror 8\r
+\r
+       wfe\r
+\r
+       wfi\r
+\r
+       yield\r
+\r
+processor CPU32_T2\r
+\r
+       bxj     r0\r
+\r
+       cps     0\r
+\r
+       cpsid   iflags_a\r
+       cpsid   iflags_a,0\r
+\r
+       cpsie   iflags_a\r
+       cpsie   iflags_a,0\r
+\r
+       mrs     r0,cpsr\r
+       mrs     r0,spsr\r
+\r
+       msr     cpsr,r1\r
+       msr     cpsr_fsxc,r1\r
+\r
+       pkhbt   r0,r1\r
+       pkhbt   r0,r1,lsl 3\r
+       pkhbt   r0,r1,r2\r
+       pkhbt   r0,r1,r2,lsl 3\r
+\r
+       pkhtb   r0,r1\r
+       pkhtb   r0,r1,asr 3\r
+       pkhtb   r0,r1,r2\r
+       pkhtb   r0,r1,r2,asr 3\r
+\r
+       qadd    r0,r1\r
+       qadd    r0,r1,r2\r
+\r
+       qadd16  r0,r1\r
+       qadd16  r0,r1,r2\r
+\r
+       qadd8   r0,r1\r
+       qadd8   r0,r1,r2\r
+\r
+       qaddsubx        r0,r1\r
+       qaddsubx        r0,r1,r2\r
+\r
+       qasx    r0,r1\r
+       qasx    r0,r1,r2\r
+\r
+       qdadd   r0,r1\r
+       qdadd   r0,r1,r2\r
+\r
+       qdsub   r0,r1\r
+       qdsub   r0,r1,r2\r
+\r
+       qsub    r0,r1\r
+       qsub    r0,r1,r2\r
+\r
+       qsax    r0,r1\r
+       qsax    r0,r1,r2\r
+\r
+       qsub16  r0,r1\r
+       qsub16  r0,r1,r2\r
+\r
+       qsub8   r0,r1\r
+       qsub8   r0,r1,r2\r
+\r
+       qsubaddx        r0,r1\r
+       qsubaddx        r0,r1,r2\r
+\r
+       rfe     r0\r
+       rfe     r0!\r
+\r
+       rfedb   r0\r
+       rfedb   r0!\r
+\r
+       rfeea   r0\r
+       rfeea   r0!\r
+\r
+       rfefd   r0\r
+       rfefd   r0!\r
+\r
+       rfeia   r0\r
+       rfeia   r0!\r
+\r
+       sadd16  r0,r1\r
+       sadd16  r0,r1,r2\r
+\r
+       sadd8   r0,r1\r
+       sadd8   r0,r1,r2\r
+\r
+       saddsubx        r0,r1\r
+       saddsubx        r0,r1,r2\r
+\r
+       sasx    r0,r1\r
+       sasx    r0,r1,r2\r
+\r
+       sel     r0,r1\r
+       sel     r0,r1,r2\r
+\r
+       shadd16 r0,r1\r
+       shadd16 r0,r1,r2\r
+\r
+       shadd8  r0,r1\r
+       shadd8  r0,r1,r2\r
+\r
+       shaddsubx       r0,r1\r
+       shaddsubx       r0,r1,r2\r
+\r
+       shasx   r0,r1\r
+       shasx   r0,r1,r2\r
+\r
+       shsax   r0,r1\r
+       shsax   r0,r1,r2\r
+\r
+       shsub16 r0,r1\r
+       shsub16 r0,r1,r2\r
+\r
+       shsub8  r0,r1\r
+       shsub8  r0,r1,r2\r
+\r
+       shsubaddx       r0,r1\r
+       shsubaddx       r0,r1,r2\r
+\r
+       smlad   r0,r1,r2,r3\r
+\r
+       smladx  r0,r1,r2,r3\r
+\r
+       smlabb  r0,r1,r2,r3\r
+\r
+       smlabt  r0,r1,r2,r3\r
+\r
+       smlalbb r0,r1,r2,r3\r
+\r
+       smlalbt r0,r1,r2,r3\r
+\r
+       smlald  r0,r1,r2,r3\r
+\r
+       smlaldx r0,r1,r2,r3\r
+\r
+       smlaltb r0,r1,r2,r3\r
+\r
+       smlaltt r0,r1,r2,r3\r
+\r
+       smlatb  r0,r1,r2,r3\r
+\r
+       smlatt  r0,r1,r2,r3\r
+\r
+       smlawb  r0,r1,r2,r3\r
+\r
+       smlawt  r0,r1,r2,r3\r
+\r
+       smlsd   r0,r1,r2,r3\r
+\r
+       smlsdx  r0,r1,r2,r3\r
+\r
+       smlsld  r0,r1,r2,r3\r
+\r
+       smlsldx r0,r1,r2,r3\r
+\r
+       smmla   r0,r1,r2,r3\r
+\r
+       smmlar  r0,r1,r2,r3\r
+\r
+       smmls   r0,r1,r2,r3\r
+\r
+       smmlsr  r0,r1,r2,r3\r
+\r
+       smmul   r0,r1\r
+       smmul   r0,r1,r2\r
+\r
+       smmulr  r0,r1\r
+       smmulr  r0,r1,r2\r
+\r
+       smuad   r0,r1\r
+       smuad   r0,r1,r2\r
+\r
+       smuadx  r0,r1\r
+       smuadx  r0,r1,r2\r
+\r
+       smulbb  r0,r1\r
+       smulbb  r0,r1,r2\r
+\r
+       smulbt  r0,r1\r
+       smulbt  r0,r1,r2\r
+\r
+       smultb  r0,r1\r
+       smultb  r0,r1,r2\r
+\r
+       smultt  r0,r1\r
+       smultt  r0,r1,r2\r
+\r
+       smulwb  r0,r1\r
+       smulwb  r0,r1,r2\r
+\r
+       smulwt  r0,r1\r
+       smulwt  r0,r1,r2\r
+\r
+       smusd   r0,r1\r
+       smusd   r0,r1,r2\r
+\r
+       smusdx  r0,r1\r
+       smusdx  r0,r1,r2\r
+\r
+       srs     0\r
+       srs     0 !\r
+       srs     sp,0\r
+       srs     sp!,0\r
+\r
+       srsdb   0\r
+       srsdb   0 !\r
+       srsdb   sp,0\r
+       srsdb   sp!,0\r
+\r
+       srsea   0\r
+       srsea   0 !\r
+       srsea   sp,0\r
+       srsea   sp!,0\r
+\r
+       srsfd   0\r
+       srsfd   0 !\r
+       srsfd   sp,0\r
+       srsfd   sp!,0\r
+\r
+       srsia   0\r
+       srsia   0 !\r
+       srsia   sp,0\r
+       srsia   sp!,0\r
+\r
+       ssat    r0,1,r2\r
+       ssat    r0,1,r2,lsl 3\r
+       ssat    r0,1,r2,asr 3\r
+\r
+       ssat16  r0,1,r2\r
+\r
+       ssax    r0,r1\r
+       ssax    r0,r1,r2\r
+\r
+       ssub16  r0,r1\r
+       ssub16  r0,r1,r2\r
+\r
+       ssub8   r0,r1\r
+       ssub8   r0,r1,r2\r
+\r
+       ssubaddx        r0,r1\r
+       ssubaddx        r0,r1,r2\r
+\r
+       sxtab   r0,r1,r2\r
+       sxtab   r0,r1,r2,ror 8\r
+\r
+       sxtab16 r0,r1,r2\r
+       sxtab16 r0,r1,r2,ror 8\r
+\r
+       sxtah   r0,r1,r2\r
+       sxtah   r0,r1,r2,ror 8\r
+\r
+       sxtb16  r0,r1\r
+       sxtb16  r0,r1,ror 8\r
+\r
+       uadd16  r0,r1\r
+       uadd16  r0,r1,r2\r
+\r
+       uadd8   r0,r1\r
+       uadd8   r0,r1,r2\r
+\r
+       uaddsubx        r0,r1\r
+       uaddsubx        r0,r1,r2\r
+\r
+       uasx    r0,r1\r
+       uasx    r0,r1,r2\r
+\r
+       uhadd16 r0,r1\r
+       uhadd16 r0,r1,r2\r
+\r
+       uhadd8  r0,r1\r
+       uhadd8  r0,r1,r2\r
+\r
+       uhaddsubx       r0,r1\r
+       uhaddsubx       r0,r1,r2\r
+\r
+       uhasx   r0,r1\r
+       uhasx   r0,r1,r2\r
+\r
+       uhsax   r0,r1\r
+       uhsax   r0,r1,r2\r
+\r
+       uhsub16 r0,r1\r
+       uhsub16 r0,r1,r2\r
+\r
+       uhsub8  r0,r1\r
+       uhsub8  r0,r1,r2\r
+\r
+       uhsubaddx       r0,r1\r
+       uhsubaddx       r0,r1,r2\r
+\r
+       umaal   r0,r1,r2,r3\r
+\r
+       uqadd16 r0,r1\r
+       uqadd16 r0,r1,r2\r
+\r
+       uqadd8  r0,r1\r
+       uqadd8  r0,r1,r2\r
+\r
+       uqaddsubx       r0,r1\r
+       uqaddsubx       r0,r1,r2\r
+\r
+       uqasx   r0,r1\r
+       uqasx   r0,r1,r2\r
+\r
+       uqsax   r0,r1\r
+       uqsax   r0,r1,r2\r
+\r
+       uqsub16 r0,r1\r
+       uqsub16 r0,r1,r2\r
+\r
+       uqsub8  r0,r1\r
+       uqsub8  r0,r1,r2\r
+\r
+       uqsubaddx       r0,r1\r
+       uqsubaddx       r0,r1,r2\r
+\r
+       usad8   r0,r1,r2\r
+\r
+       usada8  r0,r1,r2,r3\r
+\r
+       usat    r0,1,r2\r
+       usat    r0,1,r2,lsl 3\r
+       usat    r0,1,r2,asr 3\r
+\r
+       usat16  r0,1,r2\r
+\r
+       usax    r0,r1\r
+       usax    r0,r1,r2\r
+\r
+       usub16  r0,r1\r
+       usub16  r0,r1,r2\r
+\r
+       usub8   r0,r1\r
+       usub8   r0,r1,r2\r
+\r
+       usubaddx        r0,r1\r
+       usubaddx        r0,r1,r2\r
+\r
+       uxtab   r0,r1,r2\r
+       uxtab   r0,r1,r2,ror 8\r
+\r
+       uxtab16 r0,r1,r2\r
+       uxtab16 r0,r1,r2,ror 8\r
+\r
+       uxtah   r0,r1,r2\r
+       uxtah   r0,r1,r2,ror 8\r
+\r
+       uxtb16  r0,r1\r
+       uxtb16  r0,r1,ror 8\r
+\r
+processor CPU32_V7\r
+\r
+       ldrexd  r0,[r2]\r
+       ldrexd  r0,r1,[r2]\r
+\r
+       label_pli_t32:\r
+       pli     [r1]\r
+       pli     [r1,2]\r
+       pli     [r1,r2]\r
+       pli     [r1,r2,lsl 3]\r
+       pli     [label_pli_t32]\r
+       pli     [expression.byte]\r
+\r
+       strexd  r0,r1,[r3]\r
+       strexd  r0,r1,r2,[r3]\r
+\r
+processor CPU32_SYNC\r
+\r
+       ldrexb  r0,[r1]\r
+       ldrexb  r0,[r1,0]\r
+       ldrexb  r0,byte[expression.dword]\r
+\r
+       ldrexh  r0,[r1]\r
+       ldrexh  r0,[r1,0]\r
+       ldrexh  r0,hword[expression.dword]\r
+\r
+       strexb  r0,r1,[r2]\r
+       strexb  r0,r1,[r2,0]\r
+       strexb  r0,r1,byte[expression.dword]\r
+\r
+       strexh  r0,r1,[r2]\r
+       strexh  r0,r1,[r2,0]\r
+       strexh  r0,r1,hword[expression.dword]\r
+\r
+processor CPU32_DIV\r
+\r
+       sdiv    r0,r1\r
+       sdiv    r0,r1,r2\r
+\r
+       udiv    r0,r1\r
+       udiv    r0,r1,r2\r
+\r
+processor CPU32_T2EE\r
+\r
+       enterx\r
+\r
+       leavex\r
+\r
+processor CPU32_MP\r
+\r
+       pldw    [r1]\r
+       pldw    [r1,2]\r
+       pldw    [r1,r2]\r
+       pldw    [r1,r2,lsl 3]\r
+       pldw    [expression.byte]\r
+\r
+processor CPU32_V8\r
+\r
+       dcps1\r
+       dcps2\r
+       dcps3\r
+\r
+       lda     r0,[r1]\r
+       ldab    r0,[r1]\r
+       ldah    r0,[r1]\r
+\r
+       ldaex   r0,[r1]\r
+       ldaexb  r0,[r1]\r
+       ldaexh  r0,[r1]\r
+       ldaexd  r0,[r2]\r
+       ldaexd  r0,r1,[r2]\r
+\r
+       sevl.w\r
+\r
+       stl     r0,[r1]\r
+       stlb    r0,[r1]\r
+       stlh    r0,[r1]\r
+\r
+       stlex   r2,r0,[r3]\r
+       stlexb  r2,r0,[r3]\r
+       stlexh  r2,r0,[r3]\r
+       stlexd  r2,r0,[r3]\r
+       stlexd  r2,r0,r1,[r3]\r
+\r
+processor CPU32_CRC\r
+\r
+       crc32b  r0,r1,r2\r
+       crc32h  r0,r1,r2\r
+       crc32w  r0,r1,r2\r
+\r
+       crc32cb r0,r1,r2\r
+       crc32ch r0,r1,r2\r
+       crc32cw r0,r1,r2\r

diff --git a/armdoc/InstructionFormatsVFP.asm b/armdoc/InstructionFormatsVFP.asm
new file mode 100644 (file)
index 0000000..1cb7b40
--- /dev/null
+++ b/armdoc/InstructionFormatsVFP.asm
@@ -0,0 +1,1120 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;To avoid unnecessary repetition only ARM mode is used\r
+;here. There is no change needed for THUMB mode except\r
+;to specify that the processor supports version 7M\r
+;architecture instructions.\r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;All instructions can be conditional. The condition code\r
+;should be added at the end of the main opcode and\r
+;before any size/type specifiers. For example: "addhi"\r
+;and "vaddhi.i16". The syntax also supports the pre-UAL\r
+;style of putting the condition before any modifiers\r
+;like "s" or "fd". For example: "ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;VFP, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_VFP_V1xD\r
+\r
+       fabss   s0,s1\r
+\r
+       fadds   s0,s1\r
+       fadds   s0,s1,s2\r
+\r
+       fcmpes  s0,s1\r
+       fcmpes  s0,0.0\r
+\r
+       fcmpezs s0\r
+\r
+       fcmps   s0,s1\r
+       fcmps   s0,0.0\r
+\r
+       fcmpzs  s0\r
+\r
+       fcpys   s0,s1\r
+\r
+       fdivs   s0,s1\r
+       fdivs   s0,s1,s2\r
+\r
+       label_fldd:\r
+       fldd    d0,[r1]\r
+       fldd    d0,[r1,4]\r
+       fldd    d0,[label_fldd]\r
+       fldd    d0,[expression.word]\r
+\r
+       fldmdbd r0!,{d0-d3}\r
+\r
+       fldmdbs r0!,{s0-s3}\r
+\r
+       fldmdbx r0!,{d0-d3}\r
+\r
+       fldmead r0!,{d0-d3}\r
+\r
+       fldmeas r0!,{s0-s3}\r
+\r
+       fldmeax r0!,{d0-d3}\r
+\r
+       fldmfdd r0,{d0-d3}\r
+       fldmfdd r0!,{d0-d3}\r
+\r
+       fldmfds r0,{s0-s3}\r
+       fldmfds r0!,{s0-s3}\r
+\r
+       fldmfdx r0,{d0-d3}\r
+       fldmfdx r0!,{d0-d3}\r
+\r
+       fldmiad r0,{d0-d3}\r
+       fldmiad r0!,{d0-d3}\r
+\r
+       fldmias r0,{s0-s3}\r
+       fldmias r0!,{s0-s3}\r
+\r
+       fldmiax r0,{d0-d3}\r
+       fldmiax r0!,{d0-d3}\r
+\r
+       fldmd   r0,{d0-d3}\r
+       fldmd   r0!,{d0-d3}\r
+\r
+       fldms   r0,{s0-s3}\r
+       fldms   r0!,{s0-s3}\r
+\r
+       fldmx   r0,{d0-d3}\r
+       fldmx   r0!,{d0-d3}\r
+\r
+       label_flds:\r
+       flds    s0,[r1]\r
+       flds    s0,[r1,4]\r
+       flds    s0,[label_flds]\r
+       flds    s0,[expression.word]\r
+\r
+       fmacs   s0,s1,s2\r
+\r
+       fmdhr   d0,r1\r
+\r
+       fmdlr   d0,r1\r
+\r
+       fmrdh   r0,d1\r
+\r
+       fmrdl   r0,d1\r
+\r
+       fmrs    r0,s1\r
+\r
+       fmrx    r0,fpscr\r
+\r
+       fmscs   s0,s1,s2\r
+\r
+       fmsr    s0,r1\r
+\r
+       fmstat\r
+\r
+       fmuls   s0,s1\r
+       fmuls   s0,s1,s2\r
+\r
+       fmxr    fpscr,r1\r
+\r
+       fnegs   s0,s1\r
+\r
+       fnmacs  s0,s1,s2\r
+\r
+       fnmscs  s0,s1,s2\r
+\r
+       fnmuls  s0,s1\r
+       fnmuls  s0,s1,s2\r
+\r
+       fsqrts  s0,s1\r
+\r
+       fstmdbd r0!,{d0-d3}\r
+\r
+       fstmdbs r0!,{s0-s3}\r
+\r
+       fstmdbx r0!,{d0-d3}\r
+\r
+       fstmead r0,{d0-d3}\r
+       fstmead r0!,{d0-d3}\r
+\r
+       fstmeas r0,{s0-s3}\r
+       fstmeas r0!,{s0-s3}\r
+\r
+       fstmeax r0,{d0-d3}\r
+       fstmeax r0!,{d0-d3}\r
+\r
+       fstmfdd r0!,{d0-d3}\r
+\r
+       fstmfds r0!,{s0-s3}\r
+\r
+       fstmfdx r0!,{d0-d3}\r
+\r
+       fstmiad r0,{d0-d3}\r
+       fstmiad r0!,{d0-d3}\r
+\r
+       fstmias r0,{s0-s3}\r
+       fstmias r0!,{s0-s3}\r
+\r
+       fstmiax r0,{d0-d3}\r
+       fstmiax r0!,{d0-d3}\r
+\r
+       fstmd   r0,{d0-d3}\r
+       fstmd   r0!,{d0-d3}\r
+\r
+       fstms   r0,{s0-s3}\r
+       fstms   r0!,{s0-s3}\r
+\r
+       fstmx   r0,{d0-d3}\r
+       fstmx   r0!,{d0-d3}\r
+\r
+       label_fstd:\r
+       fstd    d0,[r1]\r
+       fstd    d0,[r1,4]\r
+       fstd    d0,[label_fstd]\r
+       fstd    d0,[expression.word]\r
+\r
+       label_fsts:\r
+       fsts    s0,[r1]\r
+       fsts    s0,[r1,4]\r
+       fsts    s0,[label_fsts]\r
+       fsts    s0,[expression.word]\r
+\r
+       fsubs   s0,s1\r
+       fsubs   s0,s1,s2\r
+\r
+       fsitos  s0,s1\r
+\r
+       ftosis  s0,s1\r
+\r
+       ftosizs s0,s1\r
+\r
+       ftouis  s0,s1\r
+\r
+       ftouizs s0,s1\r
+\r
+       fuitos  s0,s1\r
+\r
+       vabs.f32        s0,s1\r
+\r
+       vadd.f32        s0,s1\r
+       vadd.f32        s0,s1,s2\r
+\r
+       vcmp.f32        s0,0.0\r
+       vcmp.f32        s0,s1\r
+\r
+       vcmpe.f32       s0,0.0\r
+       vcmpe.f32       s0,s1\r
+\r
+       vcvt.f32.s32    s0,s1\r
+\r
+       vcvt.f32.u32    s0,s1\r
+\r
+       vcvt.s32.f32    s0,s1\r
+\r
+       vcvt.u32.f32    s0,s1\r
+\r
+       vcvtr.s32.f32   s0,s1\r
+\r
+       vcvtr.u32.f32   s0,s1\r
+\r
+       vdiv.f32        s0,s1\r
+       vdiv.f32        s0,s1,s2\r
+\r
+       vldm    r0!,{d0-d3}\r
+       vldm    r0!,{s0-s3}\r
+       vldm    r0,{d0-d3}\r
+       vldm    r0,{s0-s3}\r
+\r
+       vldm.32 r0!,{s0-s3}\r
+       vldm.32 r0,{s0-s3}\r
+\r
+       vldm.64 r0!,{d0-d3}\r
+       vldm.64 r0,{d0-d3}\r
+\r
+       vldmdb  r0!,{d0-d3}\r
+       vldmdb  r0!,{s0-s3}\r
+\r
+       vldmdb.32       r0!,{s0-s3}\r
+\r
+       vldmdb.64       r0!,{d0-d3}\r
+\r
+       vldmea  r0!,{d0-d3}\r
+       vldmea  r0!,{s0-s3}\r
+\r
+       vldmea.32       r0!,{s0-s3}\r
+\r
+       vldmea.64       r0!,{d0-d3}\r
+\r
+       vldmfd  r0!,{d0-d3}\r
+       vldmfd  r0!,{s0-s3}\r
+       vldmfd  r0,{d0-d3}\r
+       vldmfd  r0,{s0-s3}\r
+\r
+       vldmfd.32       r0!,{s0-s3}\r
+       vldmfd.32       r0,{s0-s3}\r
+\r
+       vldmfd.64       r0!,{d0-d3}\r
+       vldmfd.64       r0,{d0-d3}\r
+\r
+       vldmia  r0!,{d0-d3}\r
+       vldmia  r0!,{s0-s3}\r
+       vldmia  r0,{d0-d3}\r
+       vldmia  r0,{s0-s3}\r
+\r
+       vldmia.32       r0!,{s0-s3}\r
+       vldmia.32       r0,{s0-s3}\r
+\r
+       vldmia.64       r0!,{d0-d3}\r
+       vldmia.64       r0,{d0-d3}\r
+\r
+       label_vldr:\r
+       vldr    d0,[expression.word]\r
+       vldr    d0,[label_vldr]\r
+       vldr    d0,[r1,4]\r
+       vldr    d0,[r1]\r
+       vldr    s0,[expression.word]\r
+       vldr    s0,[label_vldr]\r
+       vldr    s0,[r1,4]\r
+       vldr    s0,[r1]\r
+\r
+       label_vldr.32:\r
+       vldr.32 s0,[expression.word]\r
+       vldr.32 s0,[label_vldr.32]\r
+       vldr.32 s0,[r1,4]\r
+       vldr.32 s0,[r1]\r
+\r
+       label_vldr.64:\r
+       vldr.64 d0,[expression.word]\r
+       vldr.64 d0,[label_vldr.64]\r
+       vldr.64 d0,[r1,4]\r
+       vldr.64 d0,[r1]\r
+\r
+       vmla.f32        s0,s1,s2\r
+\r
+       vmls.f32        s0,s1,s2\r
+\r
+       vmov    d0[1],r1\r
+       vmov    r0,d1[1]\r
+       vmov    r0,s1\r
+       vmov    s0,r1\r
+\r
+       vmov.32 d0[1],r1\r
+       vmov.32 r0,d1[1]\r
+\r
+       vmov.f32        s0,s1\r
+\r
+       vmrs    r0,fpscr\r
+       vmrs    apsr_nzcv,fpscr\r
+\r
+       vmsr    fpscr,r1\r
+\r
+       vmul.f32        s0,s1\r
+       vmul.f32        s0,s1,s2\r
+\r
+       vneg.f32        s0,s1\r
+\r
+       vnmla.f32       s0,s1,s2\r
+\r
+       vnmls.f32       s0,s1,s2\r
+\r
+       vnmul.f32       s0,s1\r
+       vnmul.f32       s0,s1,s2\r
+\r
+       vpop    {d0,d2,d1}\r
+       vpop    {s0,s2,s1}\r
+\r
+       vpush   {d0,d2,d1}\r
+       vpush   {s0,s2,s1}\r
+\r
+       vsqrt.f32       s0,s1\r
+\r
+       vstm    r0!,{d0-d3}\r
+       vstm    r0!,{s0-s3}\r
+       vstm    r0,{d0-d3}\r
+       vstm    r0,{s0-s3}\r
+\r
+       vstm.32 r0!,{s0-s3}\r
+       vstm.32 r0,{s0-s3}\r
+\r
+       vstm.64 r0!,{d0-d3}\r
+       vstm.64 r0,{d0-d3}\r
+\r
+       vstmdb  r0!,{d0-d3}\r
+       vstmdb  r0!,{s0-s3}\r
+\r
+       vstmdb.32       r0!,{s0-s3}\r
+\r
+       vstmdb.64       r0!,{d0-d3}\r
+\r
+       vstmea  r0!,{d0-d3}\r
+       vstmea  r0!,{s0-s3}\r
+       vstmea  r0,{d0-d3}\r
+       vstmea  r0,{s0-s3}\r
+\r
+       vstmea.32       r0!,{s0-s3}\r
+       vstmea.32       r0,{s0-s3}\r
+\r
+       vstmea.64       r0!,{d0-d3}\r
+       vstmea.64       r0,{d0-d3}\r
+\r
+       vstmfd  r0!,{d0-d3}\r
+       vstmfd  r0!,{s0-s3}\r
+\r
+       vstmfd.32       r0!,{s0-s3}\r
+\r
+       vstmfd.64       r0!,{d0-d3}\r
+\r
+       vstmia  r0!,{d0-d3}\r
+       vstmia  r0!,{s0-s3}\r
+       vstmia  r0,{d0-d3}\r
+       vstmia  r0,{s0-s3}\r
+\r
+       vstmia.32       r0!,{s0-s3}\r
+       vstmia.32       r0,{s0-s3}\r
+\r
+       vstmia.64       r0!,{d0-d3}\r
+       vstmia.64       r0,{d0-d3}\r
+\r
+       label_vstr:\r
+       vstr    d0,[expression.word]\r
+       vstr    d0,[label_vstr]\r
+       vstr    d0,[r1,4]\r
+       vstr    d0,[r1]\r
+       vstr    s0,[expression.word]\r
+       vstr    s0,[label_vstr]\r
+       vstr    s0,[r1,4]\r
+       vstr    s0,[r1]\r
+\r
+       label_vstr.32:\r
+       vstr.32 s0,[expression.word]\r
+       vstr.32 s0,[label_vstr.32]\r
+       vstr.32 s0,[r1,4]\r
+       vstr.32 s0,[r1]\r
+\r
+       label_vstr.64:\r
+       vstr.64 d0,[expression.word]\r
+       vstr.64 d0,[label_vstr.64]\r
+       vstr.64 d0,[r1,4]\r
+       vstr.64 d0,[r1]\r
+\r
+       vsub.f32        s0,s1\r
+       vsub.f32        s0,s1,s2\r
+\r
+coprocessor COPRO_VFP_V1xD + COPRO_VFP_D32\r
+\r
+       label_fldd_d32:\r
+       fldd    d20,[r1]\r
+       fldd    d20,[r1,4]\r
+       fldd    d20,[label_fldd_d32]\r
+       fldd    d20,[expression.word]\r
+\r
+       fldmdbd r0!,{d20-d23}\r
+\r
+       fldmdbx r0!,{d20-d23}\r
+\r
+       fldmead r0!,{d20-d23}\r
+\r
+       fldmeax r0!,{d20-d23}\r
+\r
+       fldmfdd r0,{d20-d23}\r
+       fldmfdd r0!,{d20-d23}\r
+\r
+       fldmfdx r0,{d20-d23}\r
+       fldmfdx r0!,{d20-d23}\r
+\r
+       fldmiad r0,{d20-d23}\r
+       fldmiad r0!,{d20-d23}\r
+\r
+       fldmiax r0,{d20-d23}\r
+       fldmiax r0!,{d20-d23}\r
+\r
+       fldmd   r0,{d20-d23}\r
+       fldmd   r0!,{d20-d23}\r
+\r
+       fldmx   r0,{d20-d23}\r
+       fldmx   r0!,{d20-d23}\r
+\r
+       fmdhr   d20,r1\r
+\r
+       fmdlr   d20,r1\r
+\r
+       fmrdh   r0,d21\r
+\r
+       fmrdl   r0,d21\r
+\r
+       fstmdbd r0!,{d20-d23}\r
+\r
+       fstmdbx r0!,{d20-d23}\r
+\r
+       fstmead r0,{d20-d23}\r
+       fstmead r0!,{d20-d23}\r
+\r
+       fstmeax r0,{d20-d23}\r
+       fstmeax r0!,{d20-d23}\r
+\r
+       fstmfdd r0!,{d20-d23}\r
+\r
+       fstmfdx r0!,{d20-d23}\r
+\r
+       fstmiad r0,{d20-d23}\r
+       fstmiad r0!,{d20-d23}\r
+\r
+       fstmiax r0,{d20-d23}\r
+       fstmiax r0!,{d20-d23}\r
+\r
+       fstmd   r0,{d20-d23}\r
+       fstmd   r0!,{d20-d23}\r
+\r
+       fstmx   r0,{d20-d23}\r
+       fstmx   r0!,{d20-d23}\r
+\r
+       label_fstd_d32:\r
+       fstd    d20,[r1]\r
+       fstd    d20,[r1,4]\r
+       fstd    d20,[label_fstd_d32]\r
+       fstd    d20,[expression.word]\r
+\r
+       vldm    r0!,{d20-d23}\r
+       vldm    r0,{d20-d23}\r
+\r
+       vldm.64 r0!,{d20-d23}\r
+       vldm.64 r0,{d20-d23}\r
+\r
+       vldmdb  r0!,{d20-d23}\r
+\r
+       vldmdb.64       r0!,{d20-d23}\r
+\r
+       vldmea  r0!,{d20-d23}\r
+\r
+       vldmea.64       r0!,{d20-d23}\r
+\r
+       vldmfd  r0!,{d20-d23}\r
+       vldmfd  r0,{d20-d23}\r
+\r
+       vldmfd.64       r0!,{d20-d23}\r
+       vldmfd.64       r0,{d20-d23}\r
+\r
+       vldmia  r0!,{d20-d23}\r
+       vldmia  r0,{d20-d23}\r
+\r
+       vldmia.64       r0!,{d20-d23}\r
+       vldmia.64       r0,{d20-d23}\r
+\r
+       label_vldr_d32:\r
+       vldr    d20,[expression.word]\r
+       vldr    d20,[label_vldr_d32]\r
+       vldr    d20,[r1,4]\r
+       vldr    d20,[r1]\r
+\r
+       label_vldr.64_d32:\r
+       vldr.64 d20,[expression.word]\r
+       vldr.64 d20,[label_vldr.64_d32]\r
+       vldr.64 d20,[r1,4]\r
+       vldr.64 d20,[r1]\r
+\r
+       vmov    d20[0],r1\r
+       vmov    r0,d21[0]\r
+\r
+       vmov.32 d20[0],r1\r
+       vmov.32 r0,d21[0]\r
+\r
+       vpop    {d5-d20}\r
+\r
+       vpush   {d5-d20}\r
+\r
+       vstm    r0!,{d20-d23}\r
+       vstm    r0,{d20-d23}\r
+\r
+       vstm.64 r0!,{d20-d23}\r
+       vstm.64 r0,{d20-d23}\r
+\r
+       vstmdb  r0!,{d20-d23}\r
+\r
+       vstmdb.64       r0!,{d20-d23}\r
+\r
+       vstmea  r0!,{d20-d23}\r
+       vstmea  r0,{d20-d23}\r
+\r
+       vstmea.64       r0!,{d20-d23}\r
+       vstmea.64       r0,{d20-d23}\r
+\r
+       vstmfd  r0!,{d20-d23}\r
+\r
+       vstmfd.64       r0!,{d20-d23}\r
+\r
+       vstmia  r0!,{d20-d23}\r
+       vstmia  r0,{d20-d23}\r
+\r
+       vstmia.64       r0!,{d20-d23}\r
+       vstmia.64       r0,{d20-d23}\r
+\r
+       label_vstr_d32:\r
+       vstr    d20,[expression.word]\r
+       vstr    d20,[label_vstr_d32]\r
+       vstr    d20,[r1,4]\r
+       vstr    d20,[r1]\r
+\r
+       label_vstr.64_d32:\r
+       vstr.64 d20,[expression.word]\r
+       vstr.64 d20,[label_vstr.64_d32]\r
+       vstr.64 d20,[r1,4]\r
+       vstr.64 d20,[r1]\r
+\r
+coprocessor COPRO_VFP_V1\r
+\r
+       fabsd   d0,d1\r
+\r
+       faddd   d0,d1\r
+       faddd   d0,d1,d2\r
+\r
+       fcmpd   d0,d1\r
+       fcmpd   d0,0.0\r
+\r
+       fcmped  d0,d1\r
+       fcmped  d0,0.0\r
+\r
+       fcmpezd d0\r
+\r
+       fcmpzd  d0\r
+\r
+       fcpyd   d0,d1\r
+\r
+       fcvtds  d0,s1\r
+\r
+       fcvtsd  s0,d1\r
+\r
+       fdivd   d0,d1\r
+       fdivd   d0,d1,d2\r
+\r
+       fmacd   d0,d1,d2\r
+\r
+       fmscd   d0,d1,d2\r
+\r
+       fmuld   d0,d1\r
+       fmuld   d0,d1,d2\r
+\r
+       fnegd   d0,d1\r
+\r
+       fnmacd  d0,d1,d2\r
+\r
+       fnmscd  d0,d1,d2\r
+\r
+       fnmuld  d0,d1\r
+       fnmuld  d0,d1,d2\r
+\r
+       fsitod  d0,s1\r
+\r
+       fsqrtd  d0,d1\r
+\r
+       fsubd   d0,d1\r
+       fsubd   d0,d1,d2\r
+\r
+       ftosid  s0,d1\r
+\r
+       ftosizd s0,d1\r
+\r
+       ftouid  s0,d1\r
+\r
+       ftouizd s0,d1\r
+\r
+       fuitod  d0,s0\r
+\r
+       vabs.f64        d0,d1\r
+\r
+       vadd.f64        d0,d1\r
+       vadd.f64        d0,d1,d2\r
+\r
+       vcmp.f64        d0,0.0\r
+       vcmp.f64        d0,d1\r
+\r
+       vcmpe.f64       d0,0.0\r
+       vcmpe.f64       d0,d1\r
+\r
+       vcvt.f32.f64    s0,d1\r
+\r
+       vcvt.f64.f32    d0,s1\r
+\r
+       vcvt.f64.s32    d0,s1\r
+\r
+       vcvt.f64.u32    d0,s0\r
+\r
+       vcvt.s32.f64    s0,d1\r
+\r
+       vcvt.u32.f64    s0,d1\r
+\r
+       vcvtr.s32.f64   s0,d1\r
+\r
+       vcvtr.u32.f64   s0,d1\r
+\r
+       vdiv.f64        d0,d1\r
+       vdiv.f64        d0,d1,d2\r
+\r
+       vmla.f64        d0,d1,d2\r
+\r
+       vmls.f64        d0,d1,d2\r
+\r
+       vmov.f64        d0,d1\r
+\r
+       vmul.f64        d0,d1\r
+       vmul.f64        d0,d1,d2\r
+\r
+       vneg.f64        d0,d1\r
+\r
+       vnmla.f64       d0,d1,d2\r
+\r
+       vnmls.f64       d0,d1,d2\r
+\r
+       vnmul.f64       d0,d1\r
+       vnmul.f64       d0,d1,d2\r
+\r
+       vsqrt.f64       d0,d1\r
+\r
+       vsub.f64        d0,d1\r
+       vsub.f64        d0,d1,d2\r
+\r
+coprocessor COPRO_VFP_V1 + COPRO_VFP_D32\r
+\r
+       fabsd   d20,d21\r
+\r
+       faddd   d20,d21\r
+       faddd   d20,d21,d22\r
+\r
+       fcmpd   d20,d21\r
+       fcmpd   d20,0.0\r
+\r
+       fcmped  d20,d21\r
+       fcmped  d20,0.0\r
+\r
+       fcmpezd d20\r
+\r
+       fcmpzd  d20\r
+\r
+       fcpyd   d20,d21\r
+\r
+       fcvtds  d20,s1\r
+\r
+       fcvtsd  s0,d21\r
+\r
+       fdivd   d20,d21\r
+       fdivd   d20,d21,d22\r
+\r
+       fmacd   d20,d21,d22\r
+\r
+       fmscd   d20,d21,d22\r
+\r
+       fmuld   d20,d21\r
+       fmuld   d20,d21,d22\r
+\r
+       fnegd   d20,d21\r
+\r
+       fnmacd  d20,d21,d22\r
+\r
+       fnmscd  d20,d21,d22\r
+\r
+       fnmuld  d20,d21\r
+       fnmuld  d20,d21,d22\r
+\r
+       fsitod  d20,s1\r
+\r
+       fsqrtd  d20,d21\r
+\r
+       fsubd   d20,d21\r
+       fsubd   d20,d21,d22\r
+\r
+       ftosid  s0,d21\r
+\r
+       ftosizd s0,d21\r
+\r
+       ftouid  s0,d21\r
+\r
+       ftouizd s0,d21\r
+\r
+       fuitod  d20,s0\r
+\r
+       vabs.f64        d20,d21\r
+\r
+       vadd.f64        d20,d21\r
+       vadd.f64        d20,d21,d22\r
+\r
+       vcmp.f64        d20,0.0\r
+       vcmp.f64        d20,d21\r
+\r
+       vcmpe.f64       d20,0.0\r
+       vcmpe.f64       d20,d21\r
+\r
+       vcvt.f32.f64    s0,d21\r
+\r
+       vcvt.f64.f32    d20,s1\r
+\r
+       vcvt.f64.s32    d20,s1\r
+\r
+       vcvt.f64.u32    d20,s0\r
+\r
+       vcvt.s32.f64    s0,d21\r
+\r
+       vcvt.u32.f64    s0,d21\r
+\r
+       vcvtr.s32.f64   s0,d21\r
+\r
+       vcvtr.u32.f64   s0,d21\r
+\r
+       vdiv.f64        d20,d21\r
+       vdiv.f64        d20,d21,d22\r
+\r
+       vmla.f64        d20,d21,d22\r
+\r
+       vmls.f64        d20,d21,d22\r
+\r
+       vmov.f64        d20,d21\r
+\r
+       vmul.f64        d20,d21\r
+       vmul.f64        d20,d21,d22\r
+\r
+       vneg.f64        d20,d21\r
+\r
+       vnmla.f64       d20,d21,d22\r
+\r
+       vnmls.f64       d20,d21,d22\r
+\r
+       vnmul.f64       d20,d21\r
+       vnmul.f64       d20,d21,d22\r
+\r
+       vsqrt.f64       d20,d21\r
+\r
+       vsub.f64        d20,d21\r
+       vsub.f64        d20,d21,d22\r
+\r
+coprocessor COPRO_VFP_V2\r
+\r
+       fmdrr   d0,r1,r2\r
+\r
+       fmrrd   r0,r1,d2\r
+\r
+       fmrrs   r0,r1,{s2,s3}\r
+\r
+       fmsrr   {s0,s1},r2,r3\r
+\r
+       vmov    d0,r1,r2\r
+       vmov    r0,r1,d2\r
+       vmov    r0,r1,s2,s3\r
+       vmov    s0,s1,r2,r3\r
+\r
+coprocessor COPRO_VFP_V2 + COPRO_VFP_D32\r
+\r
+       fmdrr   d20,r1,r2\r
+\r
+       fmrrd   r0,r1,d22\r
+\r
+       vmov    d20,r1,r2\r
+       vmov    r0,r1,d22\r
+\r
+coprocessor COPRO_VFP_V3\r
+\r
+       fconsts s0,1.0\r
+       fconsts s0,1\r
+\r
+       fconstd d0,1.0\r
+       fconstd d0,1\r
+\r
+       fshtod  d0,1\r
+       fshtod  d0,d0,1\r
+\r
+       fshtos  s0,1\r
+       fshtos  s0,s0,1\r
+\r
+       fsltod  d0,1\r
+       fsltod  d0,d0,1\r
+\r
+       fsltos  s0,1\r
+       fsltos  s0,s0,1\r
+\r
+       ftoshd  d0,1\r
+       ftoshd  d0,d0,1\r
+\r
+       ftoshs  s0,1\r
+       ftoshs  s0,s0,1\r
+\r
+       ftosld  d0,1\r
+       ftosld  d0,d0,1\r
+\r
+       ftosls  s0,1\r
+       ftosls  s0,s0,1\r
+\r
+       ftouhd  d0,1\r
+       ftouhd  d0,d0,1\r
+\r
+       ftouhs  s0,1\r
+       ftouhs  s0,s0,1\r
+\r
+       ftould  d0,1\r
+       ftould  d0,d0,1\r
+\r
+       ftouls  s0,1\r
+       ftouls  s0,s0,1\r
+\r
+       fuhtod  d0,1\r
+       fuhtod  d0,d0,1\r
+\r
+       fuhtos  s0,1\r
+       fuhtos  s0,s0,1\r
+\r
+       fultod  d0,1\r
+       fultod  d0,d0,1\r
+\r
+       fultos  s0,1\r
+       fultos  s0,s0,1\r
+\r
+       vcvt.f32.s16    s0,1\r
+       vcvt.f32.s16    s0,s0,1\r
+\r
+       vcvt.f32.s32    s0,1\r
+       vcvt.f32.s32    s0,s0,1\r
+\r
+       vcvt.f32.u16    s0,1\r
+       vcvt.f32.u16    s0,s0,1\r
+\r
+       vcvt.f32.u32    s0,1\r
+       vcvt.f32.u32    s0,s0,1\r
+\r
+       vcvt.f64.s16    d0,1\r
+       vcvt.f64.s16    d0,d0,1\r
+\r
+       vcvt.f64.s32    d0,3\r
+       vcvt.f64.s32    d0,d0,3\r
+\r
+       vcvt.f64.u16    d0,1\r
+       vcvt.f64.u16    d0,d0,1\r
+\r
+       vcvt.f64.u32    d0,3\r
+       vcvt.f64.u32    d0,d0,3\r
+\r
+       vcvt.s16.f32    s0,1\r
+       vcvt.s16.f32    s0,s0,1\r
+\r
+       vcvt.s16.f64    d0,1\r
+       vcvt.s16.f64    d0,d0,1\r
+\r
+       vcvt.s32.f32    s0,1\r
+       vcvt.s32.f32    s0,s0,1\r
+\r
+       vcvt.s32.f64    d0,3\r
+       vcvt.s32.f64    d0,d0,3\r
+\r
+       vcvt.u16.f32    s0,1\r
+       vcvt.u16.f32    s0,s0,1\r
+\r
+       vcvt.u16.f64    d0,1\r
+       vcvt.u16.f64    d0,d0,1\r
+\r
+       vcvt.u32.f32    s0,1\r
+       vcvt.u32.f32    s0,s0,1\r
+\r
+       vcvt.u32.f64    d0,3\r
+       vcvt.u32.f64    d0,d0,3\r
+\r
+       vmov.f32        s0,1\r
+       vmov.f32        s0,1.0\r
+\r
+       vmov.f64        d0,1\r
+       vmov.f64        d0,1.0\r
+\r
+coprocessor COPRO_VFP_V3 + COPRO_VFP_D32\r
+\r
+       fconstd d20,1.0\r
+       fconstd d20,1\r
+\r
+       fshtod  d20,1\r
+       fshtod  d20,d20,1\r
+\r
+       fsltod  d20,1\r
+       fsltod  d20,d20,1\r
+\r
+       ftoshd  d20,1\r
+       ftoshd  d20,d20,1\r
+\r
+       ftosld  d20,1\r
+       ftosld  d20,d20,1\r
+\r
+       ftouhd  d20,1\r
+       ftouhd  d20,d20,1\r
+\r
+       ftould  d20,1\r
+       ftould  d20,d20,1\r
+\r
+       fuhtod  d20,1\r
+       fuhtod  d20,d20,1\r
+\r
+       fultod  d20,1\r
+       fultod  d20,d20,1\r
+\r
+       vcvt.f64.s16    d20,1\r
+       vcvt.f64.s16    d20,d20,1\r
+\r
+       vcvt.f64.s32    d20,1\r
+       vcvt.f64.s32    d20,d20,1\r
+\r
+       vcvt.f64.u16    d20,1\r
+       vcvt.f64.u16    d20,d20,1\r
+\r
+       vcvt.f64.u32    d20,1\r
+       vcvt.f64.u32    d20,d20,1\r
+\r
+       vcvt.s16.f64    d20,1\r
+       vcvt.s16.f64    d20,d20,1\r
+\r
+       vcvt.s32.f64    d20,1\r
+       vcvt.s32.f64    d20,d20,1\r
+\r
+       vcvt.u16.f64    d20,1\r
+       vcvt.u16.f64    d20,d20,1\r
+\r
+       vcvt.u32.f64    d20,1\r
+       vcvt.u32.f64    d20,d20,1\r
+\r
+       vmov.f64        d20,1\r
+       vmov.f64        d20,1.0\r
+\r
+coprocessor COPRO_VFP_HP\r
+\r
+       vcvtb.f32.f16   s0,s1\r
+\r
+       vcvtb.f16.f32   s0,s1\r
+\r
+       vcvtt.f32.f16   s0,s1\r
+\r
+       vcvtt.f16.f32   s0,s1\r
+\r
+coprocessor COPRO_VFP_V4\r
+\r
+       vfma.f32        s0,s1,s2\r
+\r
+       vfma.f64        d0,d1,d2\r
+\r
+       vfms.f32        s0,s1,s2\r
+\r
+       vfms.f64        d0,d1,d2\r
+\r
+       vfnma.f32       s0,s1,s2\r
+\r
+       vfnma.f64       d0,d1,d2\r
+\r
+       vfnms.f32       s0,s1,s2\r
+\r
+       vfnms.f64       d0,d1,d2\r
+\r
+coprocessor COPRO_VFP_V4 + COPRO_VFP_D32\r
+\r
+       vfma.f64        d20,d21,d22\r
+\r
+       vfnma.f64       d20,d21,d22\r
+\r
+       vfms.f64        d20,d21,d22\r
+\r
+       vfnms.f64       d20,d21,d22\r
+\r
+coprocessor COPRO_SIMD_V8\r
+\r
+       vcvtm.s32.f32   s0,s1\r
+       vcvtm.u32.f32   s0,s1\r
+       vcvtm.s32.f64   s0,d1\r
+       vcvtm.u32.f64   s0,d1\r
+\r
+       vcvtp.s32.f32   s0,s1\r
+       vcvtp.u32.f32   s0,s1\r
+       vcvtp.s32.f64   s0,d1\r
+       vcvtp.u32.f64   s0,d1\r
+\r
+       vcvtn.s32.f32   s0,s1\r
+       vcvtn.u32.f32   s0,s1\r
+       vcvtn.s32.f64   s0,d1\r
+       vcvtn.u32.f64   s0,d1\r
+\r
+       vcvta.s32.f32   s0,s1\r
+       vcvta.u32.f32   s0,s1\r
+       vcvta.s32.f64   s0,d1\r
+       vcvta.u32.f64   s0,d1\r
+\r
+       vcvtb.f16.f64   s0,d1\r
+       vcvtb.f64.f16   d0,s1\r
+\r
+       vcvtt.f16.f64   s0,d1\r
+       vcvtt.f64.f16   d0,s1\r
+\r
+       vmaxnm.f32      s0,s1,s2\r
+       vmaxnm.f64      d0,d1,d2\r
+\r
+       vminnm.f32      s0,s1,s2\r
+       vminnm.f64      d0,d1,d2\r
+\r
+       vrintm.f32.f32  s0,s1\r
+       vrintm.f64.f64  d0,d1\r
+\r
+       vrintp.f32.f32  s0,s1\r
+       vrintp.f64.f64  d0,d1\r
+\r
+       vrintn.f32.f32  s0,s1\r
+       vrintn.f64.f64  d0,d1\r
+\r
+       vrinta.f32.f32  s0,s1\r
+       vrinta.f64.f64  d0,d1\r
+\r
+       vrintx.f32.f32  s0,s1\r
+       vrintx.f64.f64  d0,d1\r
+\r
+       vrintz.f32.f32  s0,s1\r
+       vrintz.f64.f64  d0,d1\r
+\r
+       vrintr.f32.f32  s0,s1\r
+       vrintr.f64.f64  d0,d1\r
+\r
+       vseleq.f32      s0,s1,s2\r
+       vseleq.f64      d0,d1,d2\r
+\r
+       vselvs.f32      s0,s1,s2\r
+       vselvs.f64      d0,d1,d2\r
+\r
+       vselge.f32      s0,s1,s2\r
+       vselge.f64      d0,d1,d2\r
+\r
+       vselgt.f32      s0,s1,s2\r
+       vselgt.f64      d0,d1,d2\r

diff --git a/armdoc/InstructionFormatsXSCALE.asm b/armdoc/InstructionFormatsXSCALE.asm
new file mode 100644 (file)
index 0000000..0338e3e
--- /dev/null
+++ b/armdoc/InstructionFormatsXSCALE.asm
@@ -0,0 +1,101 @@
+;This document is intended to show the basic formats for\r
+;all of the instructions supported by fasmarm.\r
+\r
+;These formats are divided into sections showing the CPU\r
+;processor directive needed to enable the instruction.\r
+\r
+;Opcodes are listed in alphabetical order within each\r
+;section. A blank line separates each opcode from the\r
+;next.\r
+\r
+;Instructions can appear in many places. Different\r
+;versions of the instruction set can allow for different\r
+;sets of available parameters so be sure to check for\r
+;instructions listed in more than one place. If you are\r
+;having trouble working out what format fasmarm is\r
+;expecting then you can search through here for all\r
+;instances to find the situation that matches your code.\r
+\r
+;Coprocessor formats are divided firstly by the\r
+;coprocessor type and secondly by the implementation\r
+;version. Coprocessor instructions are available in both\r
+;ARM and THUMB modes and use the same format for both.\r
+;There is no change needed for THUMB mode except to\r
+;specify that the processor supports version 7M\r
+;architecture instructions. \r
+\r
+;The example codes given here are merely indicative of\r
+;which parameters go where. They are not intended as an\r
+;enumeration of all possible allowed values of the\r
+;parameters. Usually only one register or one immediate\r
+;value for each parameter is given so as to show what\r
+;type of parameter is expected at each position. If you\r
+;try to assemble a value that is undefined,\r
+;unpredictable or not encodable fasmarm will give a\r
+;short error message complaining that the parameter is\r
+;invalid.\r
+\r
+;These instructions do not show any condition syntax.\r
+;All instructions can be conditional. The condition code\r
+;should be added at the end of the main opcode and\r
+;before any size/type specifiers. For example: "addhi"\r
+;and "vaddhi.i16". The syntax also supports the pre-UAL\r
+;style of putting the condition before any modifiers\r
+;like "s" or "fd". For example: "ldmhifd", "ldmfdhi".\r
+\r
+;This file can be assembled by fasmarm.\r
+\r
+virtual at r1\r
+       expression.dword        rd 1\r
+       expression.word         rw 1\r
+       expression.hword        rh 1\r
+       expression.byte         rb 1\r
+end virtual\r
+\r
+       ;***********************************************\r
+       ;xScale, ARM mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+       code32\r
+\r
+coprocessor COPRO_XSCALE\r
+\r
+       mia     acc0,r1,r2\r
+\r
+       miaph   acc0,r1,r2\r
+\r
+       miabb   acc0,r1,r2\r
+\r
+       miabt   acc0,r1,r2\r
+\r
+       miatb   acc0,r1,r2\r
+\r
+       miatt   acc0,r1,r2\r
+\r
+       mar     acc0,r1,r2\r
+\r
+       mra     r0,r1,acc0\r
+\r
+       ;***********************************************\r
+       ;xScale, THUMB mode, all instructions are 32-bit\r
+       ;***********************************************\r
+\r
+processor CPU32_7M\r
+\r
+       thumb\r
+\r
+       mia     acc0,r1,r2\r
+\r
+       miaph   acc0,r1,r2\r
+\r
+       miabb   acc0,r1,r2\r
+\r
+       miabt   acc0,r1,r2\r
+\r
+       miatb   acc0,r1,r2\r
+\r
+       miatt   acc0,r1,r2\r
+\r
+       mar     acc0,r1,r2\r
+\r
+       mra     r0,r1,acc0\r

diff --git a/examples/arm64/armpe64.asm b/examples/arm64/armpe64.asm
new file mode 100644 (file)
index 0000000..e1ae1a6
--- /dev/null
+++ b/examples/arm64/armpe64.asm
@@ -0,0 +1,40 @@
+format pe64 gui nx at 0x140000000
+processor cpu64_v8
+
+section '.text' code executable
+
+entry $
+       mov     x0,xzr
+       adr     x1,hello
+       adr     x2,title
+       mov     x3,xzr
+       ldr     x8,[MessageBox]
+       blr     x8
+       mov     x0,xzr
+       ldr     x8,[ExitProcess]
+       blr     x8
+
+section '.data' data readable
+
+       hello   db      'Hello, Win64 ARM world!',0
+       title   db      'Win64 ARM',0
+
+section '.idata' import data readable
+
+       dw      0,0,0,rva user_name,rva user_table
+       dw      0,0,0,rva kernel_name,rva kernel_table
+       dw      0,0,0,0,0
+
+       user_name       db 'user32.dll',0
+       kernel_name     db 'kernel32.dll',0
+
+       sMessageBox     db 0,0,'MessageBoxA',0
+       sExitProcess    db 0,0,'ExitProcess',0
+
+       align 8
+       user_table:
+       MessageBox      dd rva sMessageBox
+                       dd 0
+       kernel_table:
+       ExitProcess     dd rva sExitProcess
+                       dd 0

diff --git a/examples/arm64/armpe64.exe b/examples/arm64/armpe64.exe
new file mode 100644 (file)
index 0000000..700afa7
Binary files /dev/null and b/examples/arm64/armpe64.exe differ

diff --git a/examples/arm64/semihosting.asm b/examples/arm64/semihosting.asm
new file mode 100644 (file)
index 0000000..7f9bb71
--- /dev/null
+++ b/examples/arm64/semihosting.asm
@@ -0,0 +1,68 @@
+SemiHosting                    = 0xf000\r
+SYS_WRITEC                     = 3\r
+SYS_WRITE0                     = 4\r
+ADP_Stopped_ApplicationExit    = 0x20026\r
+angel_SWIreason_ReportException        = 0x18\r
+\r
+       processor cpu64_v8\r
+       code64\r
+\r
+       adr     x0,stack_base\r
+       mov     sp,x0\r
+       adr     x1,hello_world\r
+       bl      show_string\r
+\r
+       adr     x1,running_at\r
+       bl      show_string\r
+       adr     x0,$$\r
+       bl      show_hex\r
+\r
+       adr     x1,exec_level\r
+       bl      show_string\r
+       mrs     x0,CurrentEL\r
+       ubfx    x0,x0,2,2\r
+       bl      show_hex\r
+\r
+       movz    x1,ADP_Stopped_ApplicationExit and 0xffff\r
+       movk    x1,ADP_Stopped_ApplicationExit and 0xffff shl 16\r
+       stp     x1,xzr,[sp,-16]!\r
+       mov     x1,sp\r
+       mov     x0,angel_SWIreason_ReportException\r
+       hlt     SemiHosting\r
+\r
+show_hex:\r
+       ;x0 = the value\r
+       clz     x2,x0\r
+       bic     x2,x2,3\r
+       lslv    x3,x0,x2\r
+       sub     sp,sp,16\r
+    .loop:\r
+       ror     x3,x3,64-4\r
+       and     x1,x3,0xf\r
+       cmp     x1,9\r
+       add     x0,x1,'A'-10\r
+       add     x1,x1,'0'\r
+       csel    x1,x1,x0,ls\r
+       strb    w1,[sp]\r
+       mov     x1,sp\r
+       mov     x0,SYS_WRITEC\r
+       hlt     SemiHosting\r
+       add     x2,x2,4\r
+       tbz     x2,6,.loop\r
+       add     sp,sp,16\r
+show_crlf:\r
+       adr     x1,crlf\r
+show_string:\r
+       ;x1 = the string\r
+       mov     x0,SYS_WRITE0\r
+       hlt     SemiHosting\r
+       ret\r
+\r
+hello_world:   db 'Hello World!',13,10\r
+crlf:          db 13,10,0\r
+running_at:    db '  Start address: 0x',0\r
+exec_level:    db 'Execution level: ',0\r
+\r
+       align   16\r
+       rb      0x20\r
+stack_base:\r

diff --git a/examples/arm64/semihosting.bin b/examples/arm64/semihosting.bin
new file mode 100644 (file)
index 0000000..d3dc692
Binary files /dev/null and b/examples/arm64/semihosting.bin differ

diff --git a/examples/armdwarf/armdwarf.asm b/examples/armdwarf/armdwarf.asm
new file mode 100644 (file)
index 0000000..cdad5f8
--- /dev/null
+++ b/examples/armdwarf/armdwarf.asm
@@ -0,0 +1,13 @@
+       format ELF dwarf executable at 0\r
+       entry start\r
+       section 'one' executable readable writeable align 020h\r
+\r
+start: mov     r1,string_hello\r
+       mov     r0,4            ;SYS_WRITE0\r
+       swi     0x123456        ;Multi-ICE DCC semihosting\r
+       mov     r0,18h          ;angel_SWIreason_ReportException\r
+       mov     r1,20000h       ;Software reason code\r
+       orr     r1,r1,26h       ;ADP_Stopped_ApplicationExit\r
+       swi     0x123456        ;Multi-ICE DCC semihosting\r
+\r
+string_hello   db      'Hello ARM semi-hosting world',13,10,0\r

diff --git a/examples/armdwarf/armdwarf.axf b/examples/armdwarf/armdwarf.axf
new file mode 100755 (executable)
index 0000000..dfc5920
Binary files /dev/null and b/examples/armdwarf/armdwarf.axf differ

diff --git a/examples/armelf/armelf b/examples/armelf/armelf
new file mode 100755 (executable)
index 0000000..cf1ead1
Binary files /dev/null and b/examples/armelf/armelf differ

diff --git a/examples/armelf/armelf.asm b/examples/armelf/armelf.asm
new file mode 100644 (file)
index 0000000..adf397c
--- /dev/null
+++ b/examples/armelf/armelf.asm
@@ -0,0 +1,17 @@
+       format ELF executable\r
+       entry start\r
+\r
+       segment readable executable\r
+\r
+start: mov     r0,0\r
+       add     r1,pc,hello-$-8\r
+       mov     r2,hello_len\r
+       swi     0x900004\r
+       mov     r0,6\r
+       swi     0x900001\r
+\r
+hello: db      'Hello world',10\r
+hello_len=$-hello\r
+\r
+       ;dummy section for bss, see http://board.flatassembler.net/topic.php?t=3689\r
+       segment writeable\r

diff --git a/examples/armpe/armpe.asm b/examples/armpe/armpe.asm
new file mode 100644 (file)
index 0000000..0a84be9
--- /dev/null
+++ b/examples/armpe/armpe.asm
@@ -0,0 +1,34 @@
+\r
+; Example of building a WinCE executable using direct coding\r
+\r
+       format  PE GUI\r
+       entry   Start\r
+\r
+section '.text' data code readable writeable executable\r
+\r
+Start:\r
+       mov     r0,0                    ;window owner (NULL)\r
+       adr     r1,Text                 ;the text\r
+       adr     r2,Caption              ;the caption\r
+       mov     r3,0                    ;style (MB_OK)\r
+       ldr     pc,[MessageBoxW]        ;display message and exit\r
+\r
+Text   du      'Hello WinCE world',0\r
+Caption        du      'ARM small PE',0\r
+\r
+       align   4\r
+\r
+data import\r
+\r
+       dw      RVA core_imports,0,0,RVA core_name,RVA core_imports\r
+       rw      5\r
+\r
+       core_imports:\r
+       MessageBoxW     dw      0x8000035A\r
+                       dw      0\r
+\r
+       core_name       db      'COREDLL.DLL',0\r
+\r
+       align   4\r
+\r
+end data\r

diff --git a/examples/armpe/armpe.exe b/examples/armpe/armpe.exe
new file mode 100644 (file)
index 0000000..3c5dc60
Binary files /dev/null and b/examples/armpe/armpe.exe differ

diff --git a/examples/armpe/armpe2.asm b/examples/armpe/armpe2.asm
new file mode 100644 (file)
index 0000000..23dd036
--- /dev/null
+++ b/examples/armpe/armpe2.asm
@@ -0,0 +1,21 @@
+\r
+; Example of building a WinCE executable using medium level macros\r
+\r
+       include 'wince.inc'\r
+       format  PE GUI\r
+       entry   Start\r
+\r
+section '.text' code readable executable\r
+\r
+proc Start uses[lr]\r
+       apscall MessageBoxW,0,addr Text,addr Caption,0\r
+       ret\r
+endp\r
+\r
+Caption        du      'ARM example MLI macros',0\r
+Text   du      'Hello ArmCE world',0\r
+\r
+section '.idata' import readable writeable\r
+\r
+       library coredll,'COREDLL.DLL'\r
+       include 'apice\coredll.inc'\r

diff --git a/examples/armpe/armpe2.exe b/examples/armpe/armpe2.exe
new file mode 100644 (file)
index 0000000..d9b9754
Binary files /dev/null and b/examples/armpe/armpe2.exe differ

diff --git a/examples/armpe/armpe3.asm b/examples/armpe/armpe3.asm
new file mode 100644 (file)
index 0000000..55f1aef
--- /dev/null
+++ b/examples/armpe/armpe3.asm
@@ -0,0 +1,13 @@
+\r
+; Example of building a WinCE executable using high level macros\r
+\r
+       include 'wincex.inc'\r
+\r
+.code\r
+\r
+proc Start uses [lr]\r
+       apscall MessageBoxW,0,*'Hello ArmCE world',*'ARM example HLI macros',0\r
+       ret\r
+endp\r
+\r
+.end Start\r

diff --git a/examples/armpe/armpe3.exe b/examples/armpe/armpe3.exe
new file mode 100644 (file)
index 0000000..d904a66
Binary files /dev/null and b/examples/armpe/armpe3.exe differ

diff --git a/examples/armpe/armpe4.asm b/examples/armpe/armpe4.asm
new file mode 100644 (file)
index 0000000..a934201
--- /dev/null
+++ b/examples/armpe/armpe4.asm
@@ -0,0 +1,122 @@
+\r
+; Example of building a simple WinCE application using high level macros\r
+\r
+       include 'wincex.inc'\r
+\r
+.code\r
+\r
+proc Start base sp uses[r0-r12,r14]\r
+  locals\r
+       outbuff rb 0x400\r
+      virtual\r
+       regs    rw 14\r
+       stack   dw ?\r
+      end virtual\r
+  endl\r
+       mov     v7,outbuff\r
+       mov     v1,0\r
+    .again:\r
+       mov     a1,'R'\r
+       strh    a1,[v7],2\r
+       apscall itou32,v7,v1\r
+       sub     v7,a1,2\r
+       apscall string_copy_atou32,v7,'=0x'\r
+       sub     v7,a1,2\r
+       cmp     v1,13\r
+       lealt   v2,[regs]\r
+       ldrlt   v3,[v2,v1,lsl 2]        ;Get registers R0-R12\r
+       leaeq   v3,[stack]              ;Calculate original R13 (SP)\r
+       cmp     v1,14\r
+       ldreq   v3,[regs+13*4]          ;Get register R14\r
+       leahi   v3,[Start]              ;Calculate original R15 (PC)\r
+       apscall htou32,v7,v3,8\r
+       sub     v7,a1,2\r
+       apscall string_copy_atou32,v7,' ('\r
+       sub     v7,a1,2\r
+       apscall itou32,v7,v3\r
+       sub     v7,a1,2\r
+       apscall string_copy_atou32,v7,<')',13,10>\r
+       sub     v7,a1,2\r
+       add     v1,v1,1\r
+       cmp     v1,15\r
+       bls     .again\r
+       apscall MessageBoxW,0,addr outbuff,*'WinCE Start registers',0\r
+       ret\r
+endp\r
+\r
+proc string_copy_atou32 nospill,dest,source\r
+    .again:\r
+       ldrb    a3,[source],1\r
+       strh    a3,[dest],2\r
+       cmp     a3,0\r
+       bne     .again\r
+       ret\r
+endp\r
+\r
+proc itou32 nospill,dest,value\r
+       mov     ip,0xffffffcd\r
+       and     ip,ip,0xffffccff\r
+       mov     a4,0\r
+       add     ip,ip,ip,lsl 16         ;ip=0xcccccccd == int(2^35/10+.5)\r
+    .next:\r
+       strb    a4,[sp,-1]!\r
+       mov     a3,value\r
+       umull   a4,value,ip,value\r
+       movs    value,value,lsr 3       ;value=quotient\r
+       sub     a4,a3,value,lsl 3\r
+       sub     a4,a4,value,lsl 1       ;a4=remainder\r
+       add     a4,a4,'0'\r
+       bne     .next\r
+    .digit:\r
+       strh    a4,[dest],2\r
+       ldrb    a4,[sp],1\r
+       cmp     a4,0\r
+       bne     .digit\r
+       strh    a4,[dest],2\r
+       ret\r
+endp\r
+\r
+proc htou32 nospill,dest,value,nibbles\r
+    ;if "nibbles" is zero then leading zeros are suppressed\r
+       clz     a4,value\r
+       rsb     a4,a4,35\r
+       cmp     nibbles,8\r
+       movhi   nibbles,8\r
+       cmp     nibbles,0\r
+       andeq   nibbles,a4,not 3\r
+       movne   nibbles,nibbles,lsl 2\r
+    .again:\r
+       sub     nibbles,nibbles,4\r
+       mov     a4,value,ror nibbles\r
+       and     a4,a4,0xf\r
+       add     a4,a4,'0'\r
+       cmp     a4,'9'\r
+       addhi   a4,a4,'A'-'9'-1\r
+       strh    a4,[dest],2\r
+       cmp     nibbles,0\r
+       bgt     .again\r
+       mov     a4,0\r
+       strh    a4,[dest],2\r
+       ret\r
+endp\r
+\r
+.end Start\r
+\r
+section '.rsrc' resource data readable\r
+\r
+       RT_VERSION      =16\r
+       LANG_NEUTRAL    =0\r
+       LANG_ENGLISH    =9\r
+       SUBLANG_DEFAULT =400h\r
+       VOS__WINDOWS32  =4\r
+       VFT_APP         =1\r
+       VFT2_UNKNOWN    =0\r
+\r
+       directory       RT_VERSION,versions\r
+       resource        versions,1,LANG_NEUTRAL,version\r
+       versioninfo     version,VOS__WINDOWS32,VFT_APP,VFT2_UNKNOWN,LANG_ENGLISH+SUBLANG_DEFAULT,0,\\r
+                       'FileDescription','Demonstration of FASMARM for WinCE assembly',\\r
+                       'LegalCopyright','Copyright (C) 2006, revolution',\\r
+                       'FileVersion','0.0.0.0',\\r
+                       'ProductVersion','0.0.0.0',\\r
+                       'OriginalFilename','ARMPE4.EXE'\r

diff --git a/examples/armpe/armpe4.exe b/examples/armpe/armpe4.exe
new file mode 100644 (file)
index 0000000..965c9c9
Binary files /dev/null and b/examples/armpe/armpe4.exe differ

diff --git a/fasmarm.exe b/fasmarm.exe
new file mode 100755 (executable)
index 0000000..6d4dbb3
Binary files /dev/null and b/fasmarm.exe differ

diff --git a/fasmarm.o b/fasmarm.o
new file mode 100644 (file)
index 0000000..aa78699
Binary files /dev/null and b/fasmarm.o differ

diff --git a/fasmarm.orig-20250113 b/fasmarm.orig-20250113
new file mode 100755 (executable)
index 0000000..30aa231
Binary files /dev/null and b/fasmarm.orig-20250113 differ

diff --git a/fasmarm.x64 b/fasmarm.x64
new file mode 100755 (executable)
index 0000000..edda42f
Binary files /dev/null and b/fasmarm.x64 differ

diff --git a/fasmwarm.exe b/fasmwarm.exe
new file mode 100644 (file)
index 0000000..5181324
Binary files /dev/null and b/fasmwarm.exe differ

diff --git a/include/apice/coredll.inc b/include/apice/coredll.inc
new file mode 100644 (file)
index 0000000..6e7056b
--- /dev/null
+++ b/include/apice/coredll.inc
@@ -0,0 +1,1231 @@
+\r
+;Define WinCE ordinals for symbolic OS calls.\r
+;By default this file is included from "WINCEX.INC".\r
+\r
+import coredll,\\r
+       __2_YAPAXI_Z,0x80000447,\\r
+       __3_YAXPAX_Z,0x80000446,\\r
+       __addd,0x80000805,\\r
+       __adds,0x80000803,\\r
+       __C_specific_handler,0x80000057,\\r
+       __cmpd,0x80000802,\\r
+       __cmps,0x80000801,\\r
+       __divd,0x80000800,\\r
+       __divs,0x800007FF,\\r
+       __dtoi,0x800007FE,\\r
+       __dtoi64,0x800007FD,\\r
+       __dtos,0x800007FC,\\r
+       __dtou,0x800007FB,\\r
+       __dtou64,0x800007FA,\\r
+       __eqd,0x800007F9,\\r
+       __eqs,0x800007F8,\\r
+       __ged,0x800007F7,\\r
+       __ges,0x800007F6,\\r
+       __gtd,0x800007F5,\\r
+       __gts,0x800007F4,\\r
+       __i64tod,0x800007F3,\\r
+       __i64tos,0x800007F2,\\r
+       __itod,0x800007F1,\\r
+       __itos,0x800007F0,\\r
+       __led,0x800007EF,\\r
+       __les,0x800007EE,\\r
+       __ltd,0x800007ED,\\r
+       __lts,0x800007EC,\\r
+       __muld,0x800007EB,\\r
+       __muls,0x800007EA,\\r
+       __ned,0x800007E9,\\r
+       __negd,0x800007E8,\\r
+       __negs,0x800007E7,\\r
+       __nes,0x800007E6,\\r
+       __rt_div0,0x800007D4,\\r
+       __rt_divtest,0x800007D7,\\r
+       __rt_sdiv,0x800007D5,\\r
+       __rt_sdiv10,0x800007D6,\\r
+       __rt_sdiv64by64,0x800007D0,\\r
+       __rt_srem64by64,0x800007D1,\\r
+       __rt_srsh,0x800007DA,\\r
+       __rt_udiv,0x800007D8,\\r
+       __rt_udiv10,0x800007D9,\\r
+       __rt_udiv64by64,0x800007D2,\\r
+       __rt_urem64by64,0x800007D3,\\r
+       __rt_ursh,0x800007DB,\\r
+       __stod,0x800007E5,\\r
+       __stoi,0x800007E4,\\r
+       __stoi64,0x800007E3,\\r
+       __stou,0x800007E2,\\r
+       __stou64,0x800007E1,\\r
+       __strgtold12,0x80000441,\\r
+       __subd,0x800007E0,\\r
+       __subs,0x800007DF,\\r
+       __u64tod,0x800007DE,\\r
+       __u64tos,0x800007DD,\\r
+       __utod,0x800007DC,\\r
+       __utos,0x80000804,\\r
+       _atodbl,0x800003E4,\\r
+       _atoflt,0x800003E5,\\r
+       _cabs,0x800003E6,\\r
+       _chgsign,0x800003E8,\\r
+       _clearfp,0x800003E9,\\r
+       _controlfp,0x800003EA,\\r
+       _copysign,0x800003EB,\\r
+       _DefaultImcGet__YAKXZ,0x800004C2,\\r
+       _DefaultImeWndGet__YAPAUHWND____XZ,0x800004C3,\\r
+       _ecvt,0x800003F0,\\r
+       _ExitWindowsEx__YAHIK_Z,0x80000127,\\r
+       _fcloseall,0x8000045F,\\r
+       _fcvt,0x800003F3,\\r
+       _fileno,0x80000464,\\r
+       _finite,0x800003F4,\\r
+       _fltused,0x80000445,\\r
+       _flushall,0x80000463,\\r
+       _fpclass,0x800003F7,\\r
+       _fpieee_flt,0x800003F8,\\r
+       _fpreset,0x800003F9,\\r
+       _frnd,0x800003FC,\\r
+       _fsqrt,0x800003FD,\\r
+       _gcvt,0x800003FE,\\r
+       _getstdfilex,0x8000044C,\\r
+       _getws,0x80000472,\\r
+       _HUGE,0x8000049D,\\r
+       _hypot,0x800003FF,\\r
+       _ImmGetUIClassName__YAXPAG_Z,0x800004C7,\\r
+       _ImmProcessKey__YAKPAUHWND____IJKI_Z,0x800004C4,\\r
+       _ImmSetActiveContext__YAHPAUHWND____KH_Z,0x80000326,\\r
+       _ImmTranslateMessage__YAHPAUHWND____IIJHIIPAH_Z,0x800004C5,\\r
+       _InitStdioLib,0x8000047F,\\r
+       _isnan,0x80000400,\\r
+       _itoa,0x80000401,\\r
+       _itow,0x80000402,\\r
+       _j0,0x80000403,\\r
+       _j1,0x80000404,\\r
+       _jn,0x80000405,\\r
+       _ld12tod,0x8000043F,\\r
+       _ld12tof,0x80000440,\\r
+       _logb,0x8000040B,\\r
+       _lrotl,0x8000040D,\\r
+       _lrotr,0x8000040E,\\r
+       _ltoa,0x8000040F,\\r
+       _ltow,0x80000410,\\r
+       _memccpy,0x80000412,\\r
+       _memicmp,0x80000415,\\r
+       _msize,0x80000419,\\r
+       _nextafter,0x8000041A,\\r
+       _purecall,0x80000444,\\r
+       _putws,0x80000473,\\r
+       _rotl,0x8000041F,\\r
+       _rotr,0x80000420,\\r
+       _scalb,0x80000421,\\r
+       _setmode,0x800004A3,\\r
+       _snprintf,0x800002D9,\\r
+       _snwprintf,0x80000448,\\r
+       _statusfp,0x80000426,\\r
+       _swab,0x80000432,\\r
+       _ultoa,0x80000437,\\r
+       _ultow,0x80000438,\\r
+       _vsnprintf,0x8000047B,\\r
+       _vsnwprintf,0x8000046C,\\r
+       _wcsdup,0x8000004A,\\r
+       _wcsicmp,0x800000E6,\\r
+       _wcslwr,0x800000E7,\\r
+       _wcsnicmp,0x800000E5,\\r
+       _wcsnset,0x80000043,\\r
+       _wcsrev,0x80000046,\\r
+       _wcsset,0x80000047,\\r
+       _wcsupr,0x800000E8,\\r
+       _wfdopen,0x8000045D,\\r
+       _wfopen,0x80000479,\\r
+       _wfreopen,0x800004B1,\\r
+       _wtol,0x8000004E,\\r
+       _wtoll,0x8000004F,\\r
+       _y0,0x8000043C,\\r
+       _y1,0x8000043D,\\r
+       _yn,0x8000043E,\\r
+       AbortDoc,0x800003BB,\\r
+       abs_,0x800003DC,\\r
+       acmDriverAdd,0x8000019E,\\r
+       acmDriverClose,0x8000019F,\\r
+       acmDriverDetails,0x800001A0,\\r
+       acmDriverEnum,0x800001A1,\\r
+       acmDriverID,0x800001A2,\\r
+       acmDriverMessage,0x800001A3,\\r
+       acmDriverOpen,0x800001A4,\\r
+       acmDriverPriority,0x800001A5,\\r
+       acmDriverRemove,0x800001A6,\\r
+       acmFilterChoose,0x800001A7,\\r
+       acmFilterDetails,0x800001A8,\\r
+       acmFilterEnum,0x800001A9,\\r
+       acmFilterTagDetails,0x800001AA,\\r
+       acmFilterTagEnum,0x800001AB,\\r
+       acmFormatChoose,0x800001AC,\\r
+       acmFormatDetails,0x800001AD,\\r
+       acmFormatEnum,0x800001AE,\\r
+       acmFormatSuggest,0x800001AF,\\r
+       acmFormatTagDetails,0x800001B0,\\r
+       acmFormatTagEnum,0x800001B1,\\r
+       acmGetVersion,0x800001BA,\\r
+       acmMetrics,0x800001BB,\\r
+       acmStreamClose,0x800001B2,\\r
+       acmStreamConvert,0x800001B3,\\r
+       acmStreamMessage,0x800001B4,\\r
+       acmStreamOpen,0x800001B5,\\r
+       acmStreamPrepareHeader,0x800001B6,\\r
+       acmStreamReset,0x800001B7,\\r
+       acmStreamSize,0x800001B8,\\r
+       acmStreamUnprepareHeader,0x800001B9,\\r
+       acos,0x800003DD,\\r
+       ActivateDevice,0x8000049B,\\r
+       AddEventAccess,0x8000022E,\\r
+       AddFontResourceW,0x8000037D,\\r
+       AddTrackedItem,0x80000242,\\r
+       AdjustWindowRectEx,0x80000377,\\r
+       AFS_CloseAllFileHandles,0x8000028F,\\r
+       AFS_CreateDirectoryW,0x80000284,\\r
+       AFS_CreateFileW,0x80000288,\\r
+       AFS_DeleteFileW,0x80000289,\\r
+       AFS_FindFirstFileW,0x8000028B,\\r
+       AFS_GetDiskFreeSpace,0x80000290,\\r
+       AFS_GetFileAttributesW,0x80000286,\\r
+       AFS_MoveFileW,0x8000028A,\\r
+       AFS_NotifyMountedFS,0x80000291,\\r
+       AFS_PrestoChangoFileName,0x8000028E,\\r
+       AFS_RegisterFileSystemFunction,0x8000028C,\\r
+       AFS_RemoveDirectoryW,0x80000285,\\r
+       AFS_SetFileAttributesW,0x80000287,\\r
+       AFS_Unmount,0x80000283,\\r
+       AppendMenuW,0x8000034A,\\r
+       asin,0x800003DE,\\r
+       atan,0x800003DF,\\r
+       atan2,0x800003E0,\\r
+       atof,0x800003E3,\\r
+       atoi,0x800003E1,\\r
+       atol,0x800003E2,\\r
+       AttachDebugger,0x8000009D,\\r
+       AudioUpdateFromRegistry,0x80000178,\\r
+       BatteryDrvrGetLevels,0x80000129,\\r
+       BatteryDrvrSupportsChangeNotification,0x8000012A,\\r
+       BatteryGetLifeTimeInfo,0x800002C9,\\r
+       BatteryNotifyOfTimeChange,0x800002CA,\\r
+       BeginDeferWindowPos,0x80000485,\\r
+       BeginPaint,0x80000104,\\r
+       BinaryCompress,0x80000251,\\r
+       BinaryDecompress,0x80000252,\\r
+       BitBlt,0x80000387,\\r
+       BringWindowToTop,0x80000113,\\r
+       CacheSync,0x80000241,\\r
+       CallNextHookEx,0x800004B4,\\r
+       CallWindowProcW,0x8000011D,\\r
+       CeChangeDatabaseLCID,0x80000154,\\r
+       CeClearReplChangeBitsEx,0x80000148,\\r
+       CeClearUserNotification,0x800001DA,\\r
+       CeCreateDatabase,0x8000013B,\\r
+       CeCreateDatabaseEx,0x800004A6,\\r
+       CeDeleteDatabase,0x8000013E,\\r
+       CeDeleteDatabaseEx,0x800004A9,\\r
+       CeDeleteRecord,0x80000140,\\r
+       CeEnumDBVolumes,0x8000048D,\\r
+       CeEventHasOccurred,0x800001DF,\\r
+       CeFindFirstDatabase,0x80000139,\\r
+       CeFindFirstDatabaseEx,0x800004AC,\\r
+       CeFindNextDatabase,0x8000013A,\\r
+       CeFindNextDatabaseEx,0x800004A5,\\r
+       CeFlushDBVol,0x800004C1,\\r
+       CeFreeNotification,0x800004CA,\\r
+       CeGetReplChangeBitsEx,0x80000146,\\r
+       CeGetReplChangeMask,0x80000144,\\r
+       CeGetReplOtherBitsEx,0x80000149,\\r
+       CeGetUserNotificationPreferences,0x800001DE,\\r
+       CeHandleAppNotifications,0x800001DD,\\r
+       ceil,0x800003E7,\\r
+       CeMountDBVol,0x8000048C,\\r
+       CeOidGetInfo,0x80000138,\\r
+       CeOidGetInfoEx,0x800004AB,\\r
+       CeOpenDatabase,0x8000013D,\\r
+       CeOpenDatabaseEx,0x800004A8,\\r
+       CeReadRecordProps,0x80000141,\\r
+       CeReadRecordPropsEx,0x800004AA,\\r
+       CeRegisterFileSystemNotification,0x8000014B,\\r
+       CeRegisterReplNotification,0x8000014C,\\r
+       CeRemoveFontResource,0x8000037E,\\r
+       CeRunAppAtEvent,0x800001DC,\\r
+       CeRunAppAtTime,0x800001DB,\\r
+       CeSeekDatabase,0x8000013F,\\r
+       CeSetDatabaseInfo,0x8000013C,\\r
+       CeSetDatabaseInfoEx,0x800004A7,\\r
+       CeSetReplChangeBitsEx,0x80000147,\\r
+       CeSetReplChangeMask,0x80000145,\\r
+       CeSetReplOtherBitsEx,0x8000014A,\\r
+       CeSetUserNotification,0x800001D9,\\r
+       CeUnmountDBVol,0x800004AD,\\r
+       CeWriteRecordProps,0x80000142,\\r
+       CharLowerBuffW,0x800000DE,\\r
+       CharLowerW,0x800000DD,\\r
+       CharNextW,0x800000E2,\\r
+       CharPrevW,0x800000E1,\\r
+       CharUpperBuffW,0x800000DF,\\r
+       CharUpperW,0x800000E0,\\r
+       CheckMenuItem,0x80000350,\\r
+       CheckMenuRadioItem,0x80000351,\\r
+       CheckPassword,0x800000B6,\\r
+       CheckRadioButton,0x800002AC,\\r
+       ChildWindowFromPoint,0x800000FD,\\r
+       ClearCommBreak,0x8000006B,\\r
+       ClearCommError,0x8000006C,\\r
+       clearerr,0x80000467,\\r
+       ClientToScreen,0x800000FE,\\r
+       ClipCursor,0x800002DB,\\r
+       CloseAllDeviceHandles,0x800000F4,\\r
+       CloseAllFileHandles,0x800000F2,\\r
+       CloseClipboard,0x8000029D,\\r
+       CloseEnhMetaFile,0x800003BC,\\r
+       CloseHandle,0x80000229,\\r
+       CloseProcOE,0x8000024D,\\r
+       CombineRgn,0x800003C8,\\r
+       CompactAllHeaps,0x80000036,\\r
+       CompareFileTime,0x80000012,\\r
+       CompareStringW,0x800000C6,\\r
+       ConnectDebugger,0x80000279,\\r
+       ContinueDebugEvent,0x800001F8,\\r
+       ConvertDefaultLocale,0x800000D2,\\r
+       CopyFileW,0x800000A4,\\r
+       CopyRect,0x80000060,\\r
+       cos,0x800003EC,\\r
+       cosh,0x800003ED,\\r
+       CountClipboardFormats,0x800002A2,\\r
+       CreateAcceleratorTableW,0x8000005C,\\r
+       CreateAPIHandle,0x8000027C,\\r
+       CreateAPISet,0x8000022F,\\r
+       CreateBitmap,0x80000385,\\r
+       CreateCaret,0x80000292,\\r
+       CreateCompatibleBitmap,0x80000386,\\r
+       CreateCompatibleDC,0x8000038E,\\r
+       CreateCrit,0x80000268,\\r
+       CreateDCW,0x8000038D,\\r
+       CreateDeviceHandle,0x800000F5,\\r
+       CreateDialogIndirectParamW,0x800002B0,\\r
+       CreateDIBPatternBrushPt,0x800003A1,\\r
+       CreateDIBSection,0x8000005A,\\r
+       CreateDirectoryW,0x800000A0,\\r
+       CreateEnhMetaFileW,0x800003BD,\\r
+       CreateEventW,0x800001EF,\\r
+       CreateFileForMapping,0x80000228,\\r
+       CreateFileForMappingW,0x8000048F,\\r
+       CreateFileMappingW,0x80000224,\\r
+       CreateFileW,0x800000A8,\\r
+       CreateFontIndirectW,0x8000037F,\\r
+       CreateIconIndirect,0x800002D3,\\r
+       CreateMenu,0x80000353,\\r
+       CreateMutexW,0x8000022B,\\r
+       CreatePalette,0x800003B3,\\r
+       CreatePatternBrush,0x8000039D,\\r
+       CreatePen,0x8000039E,\\r
+       CreatePenIndirect,0x800003A2,\\r
+       CreatePopupMenu,0x80000354,\\r
+       CreateProcessW,0x800001ED,\\r
+       CreateRectRgn,0x800003D4,\\r
+       CreateRectRgnIndirect,0x800003C9,\\r
+       CreateSolidBrush,0x800003A3,\\r
+       CreateThread,0x800001EC,\\r
+       CreateWindowExW,0x800000F6,\\r
+       DBCanonicalize,0x800000E9,\\r
+       DeactivateDevice,0x8000049C,\\r
+       DebugActiveProcess,0x800001F9,\\r
+       DebugNotify,0x80000282,\\r
+       DefDlgProcW,0x800002B1,\\r
+       DeferWindowPos,0x80000486,\\r
+       DefWindowProcW,0x80000108,\\r
+       DeleteAndRenameFile,0x800000B7,\\r
+       DeleteCriticalSection,0x80000003,\\r
+       DeleteDC,0x8000038F,\\r
+       DeleteEnhMetaFile,0x800003BE,\\r
+       DeleteFileW,0x800000A5,\\r
+       DeleteMenu,0x80000352,\\r
+       DeleteObject,0x80000390,\\r
+       DeleteTrackedItem,0x80000243,\\r
+       DeregisterAFS,0x8000014F,\\r
+       DeregisterAFSName,0x80000153,\\r
+       DeregisterDevice,0x800000EC,\\r
+       DestroyAcceleratorTable,0x8000005D,\\r
+       DestroyCaret,0x80000293,\\r
+       DestroyIcon,0x800002D5,\\r
+       DestroyMenu,0x8000034C,\\r
+       DestroyWindow,0x80000109,\\r
+       DeviceIoControl,0x800000B3,\\r
+       DialogBoxIndirectParamW,0x800002B2,\\r
+       difftime,0x800003EE,\\r
+       DisableCaretSystemWide,0x8000029A,\\r
+       DispatchMessageW,0x8000035B,\\r
+       div,0x800003EF,\\r
+       DrawEdge,0x800003A4,\\r
+       DrawFocusRect,0x800003A5,\\r
+       DrawFrameControl,0x800003DB,\\r
+       DrawIconEx,0x800002D6,\\r
+       DrawMenuBar,0x80000358,\\r
+       DrawTextW,0x800003B1,\\r
+       DumpFileSystemHeap,0x80000155,\\r
+       DumpKCallProfile,0x800001FE,\\r
+       Ellipse,0x800003A6,\\r
+       EmptyClipboard,0x800002A5,\\r
+       EnableCaretSystemWide,0x8000029B,\\r
+       EnableEUDC,0x800003DA,\\r
+       EnableHardwareKeyboard,0x80000339,\\r
+       EnableMenuItem,0x8000034F,\\r
+       EnableWindow,0x8000011F,\\r
+       EndDeferWindowPos,0x80000487,\\r
+       EndDialog,0x800002B3,\\r
+       EndDoc,0x800003BF,\\r
+       EndPage,0x800003C0,\\r
+       EndPaint,0x80000105,\\r
+       EnterCriticalSection,0x80000004,\\r
+       EnumCalendarInfoW,0x800000CE,\\r
+       EnumClipboardFormats,0x800002A3,\\r
+       EnumDateFormatsW,0x800000D0,\\r
+       EnumDevices,0x8000007C,\\r
+       EnumFontFamiliesW,0x800003C5,\\r
+       EnumFontsW,0x800003C6,\\r
+       EnumPnpIds,0x8000007B,\\r
+       EnumSystemCodePagesW,0x800000DC,\\r
+       EnumSystemLocalesW,0x800000DB,\\r
+       EnumTimeFormatsW,0x800000CF,\\r
+       EnumWindows,0x80000123,\\r
+       EqualRect,0x80000061,\\r
+       EqualRgn,0x8000005B,\\r
+       EscapeCommFunction,0x8000006D,\\r
+       EventModify,0x800001EE,\\r
+       ExcludeClipRect,0x800003CA,\\r
+       ExitThread,0x80000006,\\r
+       exp,0x800003F1,\\r
+       ExtEscape,0x8000049E,\\r
+       ExtractIconExW,0x800002D7,\\r
+       ExtractResource,0x8000023D,\\r
+       ExtTextOutW,0x80000380,\\r
+       fabs_,0x800003F2,\\r
+       fclose,0x8000045E,\\r
+       feof,0x80000465,\\r
+       ferror,0x80000466,\\r
+       fflush,0x80000462,\\r
+       fgetc,0x80000454,\\r
+       fgetpos,0x80000468,\\r
+       fgets,0x80000455,\\r
+       fgetwc,0x80000474,\\r
+       fgetws,0x80000477,\\r
+       FileSystemPowerFunction,0x800000F1,\\r
+       FileTimeToLocalFileTime,0x80000015,\\r
+       FileTimeToSystemTime,0x80000014,\\r
+       FillRect,0x800003A7,\\r
+       FillRgn,0x8000039F,\\r
+       FilterTrackedItem,0x80000249,\\r
+       FindClose,0x800000B4,\\r
+       FindFirstFileW,0x800000A7,\\r
+       FindNextFileW,0x800000B5,\\r
+       FindResource,0x80000213,\\r
+       FindResourceW,0x80000214,\\r
+       FindWindowW,0x8000011E,\\r
+       floor,0x800003F5,\\r
+       FlushFileBuffers,0x800000AF,\\r
+       FlushInstructionCache,0x800001FC,\\r
+       FlushViewOfFile,0x80000227,\\r
+       FlushViewOfFileMaybe,0x800004BF,\\r
+       fmod,0x800003F6,\\r
+       FoldStringW,0x800000DA,\\r
+       fopen,0x80000459,\\r
+       ForcePageout,0x8000021C,\\r
+       FormatMessageW,0x800000EA,\\r
+       fprintf,0x8000045B,\\r
+       fputc,0x80000456,\\r
+       fputs,0x80000457,\\r
+       fputwc,0x80000475,\\r
+       fputws,0x80000478,\\r
+       fread,0x80000460,\\r
+       free,0x800003FA,\\r
+       FreeLibrary,0x80000211,\\r
+       FreeLibraryAndExitThread,0x800004C0,\\r
+       frexp,0x800003FB,\\r
+       fscanf,0x8000045A,\\r
+       fseek,0x8000046A,\\r
+       fsetpos,0x80000469,\\r
+       ftell,0x8000046B,\\r
+       fwprintf,0x80000363,\\r
+       fwrite,0x80000461,\\r
+       fwscanf,0x800002DF,\\r
+       GetACP,0x800000BA,\\r
+       GetActiveWindow,0x800002C2,\\r
+       GetAPIAddress,0x80000020,\\r
+       GetAssociatedMenu,0x8000012C,\\r
+       GetAsyncKeyState,0x8000033A,\\r
+       GetAsyncShiftFlags,0x80000342,\\r
+       GetBkColor,0x80000391,\\r
+       GetBkMode,0x80000392,\\r
+       GetCallerProcess,0x8000025F,\\r
+       GetCallerProcessIndex,0x80000281,\\r
+       GetCapture,0x800002C3,\\r
+       GetCaretBlinkTime,0x80000299,\\r
+       GetCaretPos,0x80000297,\\r
+       getchar,0x80000450,\\r
+       GetClassInfoW,0x8000036E,\\r
+       GetClassLong,0x80000371,\\r
+       GetClassLongW,0x8000036F,\\r
+       GetClassNameW,0x8000011B,\\r
+       GetClientRect,0x800000F9,\\r
+       GetClipboardData,0x800002A0,\\r
+       GetClipboardDataAlloc,0x800002A9,\\r
+       GetClipboardFormatNameW,0x800002A4,\\r
+       GetClipboardOwner,0x8000029E,\\r
+       GetClipBox,0x800003CB,\\r
+       GetClipCursor,0x800002DC,\\r
+       GetClipRgn,0x800003CC,\\r
+       GetCommMask,0x8000006E,\\r
+       GetCommModemStatus,0x8000006F,\\r
+       GetCommProperties,0x80000070,\\r
+       GetCommState,0x80000071,\\r
+       GetCommTimeouts,0x80000072,\\r
+       GetCPInfo,0x800000BC,\\r
+       GetCRTFlags,0x800004CC,\\r
+       GetCRTStorageEx,0x800004CB,\\r
+       GetCurrencyFormatW,0x800000CD,\\r
+       GetCurrentFT,0x8000001D,\\r
+       GetCurrentObject,0x80000393,\\r
+       GetCurrentPermissions,0x80000264,\\r
+       GetCursor,0x800002DD,\\r
+       GetCursorPos,0x800002DE,\\r
+       GetDateFormatW,0x800000CB,\\r
+       GetDC,0x80000106,\\r
+       GetDCEx,0x800004A1,\\r
+       GetDeviceCaps,0x80000394,\\r
+       GetDeviceKeys,0x8000007D,\\r
+       GetDialogBaseUnits,0x800002B6,\\r
+       GetDiskFreeSpaceExW,0x800000B8,\\r
+       GetDlgCtrlID,0x800002B5,\\r
+       GetDlgItem,0x800002B4,\\r
+       GetDlgItemInt,0x800002B7,\\r
+       GetDlgItemTextW,0x800002AF,\\r
+       GetDoubleClickTime,0x80000378,\\r
+       GetExitCodeProcess,0x80000207,\\r
+       GetExitCodeThread,0x80000206,\\r
+       GetFileAttributesW,0x800000A6,\\r
+       GetFileInformationByHandle,0x800000AE,\\r
+       GetFileSize,0x800000AC,\\r
+       GetFileTime,0x800000B0,\\r
+       GetFocus,0x800002C1,\\r
+       GetForegroundInfo,0x800004C8,\\r
+       GetForegroundKeyboardTarget,0x800004C9,\\r
+       GetForegroundWindow,0x800002BD,\\r
+       GetFSHeapInfo,0x8000025B,\\r
+       GetHeapSnapshot,0x80000034,\\r
+       GetIdleTime,0x80000260,\\r
+       GetKeyboardLayout,0x800004CD,\\r
+       GetKeyboardLayoutNameW,0x80000488,\\r
+       GetKeyboardStatus,0x8000033B,\\r
+       GetKeyboardTarget,0x800002C7,\\r
+       GetKeyState,0x8000035C,\\r
+       GetKPhys,0x80000245,\\r
+       GetLastError,0x80000204,\\r
+       GetLocaleInfoW,0x800000C8,\\r
+       GetLocalTime,0x80000017,\\r
+       GetMenuItemInfoW,0x80000356,\\r
+       GetMessagePos,0x8000035E,\\r
+       GetMessageSource,0x80000368,\\r
+       GetMessageW,0x8000035D,\\r
+       GetMessageWNoWait,0x8000035F,\\r
+       GetModuleFileNameW,0x80000219,\\r
+       GetModuleHandleW,0x80000499,\\r
+       GetMouseMovePoints,0x80000334,\\r
+       GetNearestColor,0x800003B8,\\r
+       GetNearestPaletteIndex,0x800003B4,\\r
+       GetNextDlgGroupItem,0x800002B9,\\r
+       GetNextDlgTabItem,0x800002B8,\\r
+       GetNumberFormatW,0x800000CC,\\r
+       GetObjectType,0x80000395,\\r
+       GetObjectW,0x80000396,\\r
+       GetOEMCP,0x800000BB,\\r
+       GetOpenClipboardWindow,0x800002A8,\\r
+       GetOpenFileNameW,0x800001E8,\\r
+       GetOwnerProcess,0x8000025E,\\r
+       GetPaletteEntries,0x800003B5,\\r
+       GetParent,0x8000010D,\\r
+       GetPasswordActive,0x800000EF,\\r
+       GetPixel,0x800003A8,\\r
+       GetPriorityClipboardFormat,0x800002A7,\\r
+       GetProcAddrBits,0x8000025A,\\r
+       GetProcAddressW,0x80000212,\\r
+       GetProcessHeap,0x80000032,\\r
+       GetProcessIndexFromID,0x80000280,\\r
+       GetProcessVersion,0x80000218,\\r
+       GetProcFromPtr,0x80000258,\\r
+       GetProcName,0x80000270,\\r
+       GetRealTime,0x8000023A,\\r
+       GetRegionData,0x800003CD,\\r
+       GetRgnBox,0x800003CE,\\r
+       GetRomFileBytes,0x80000240,\\r
+       GetRomFileInfo,0x8000023F,\\r
+       gets,0x80000452,\\r
+       GetSaveFileNameW,0x800001E9,\\r
+       GetScrollInfo,0x8000011A,\\r
+       GetStdioPathW,0x8000047D,\\r
+       GetStockObject,0x80000397,\\r
+       GetStoreInformation,0x80000143,\\r
+       GetStringTypeExW,0x800000D9,\\r
+       GetStringTypeW,0x800000D8,\\r
+       GetSubMenu,0x80000357,\\r
+       GetSysColor,0x80000379,\\r
+       GetSysColorBrush,0x800003A9,\\r
+       GetSystemDefaultLangID,0x800000D3,\\r
+       GetSystemDefaultLCID,0x800000D5,\\r
+       GetSystemInfo,0x8000021E,\\r
+       GetSystemMemoryDivision,0x80000150,\\r
+       GetSystemMetrics,0x80000375,\\r
+       GetSystemPaletteEntries,0x800003B6,\\r
+       GetSystemPowerStatusEx,0x800002CB,\\r
+       GetSystemTime,0x80000019,\\r
+       GetTempPathW,0x800000A2,\\r
+       GetTextColor,0x80000398,\\r
+       GetTextExtentExPointW,0x80000381,\\r
+       GetTextFaceW,0x800003C7,\\r
+       GetTextMetricsW,0x80000382,\\r
+       GetThreadContext,0x8000047C,\\r
+       GetThreadPriority,0x80000203,\\r
+       GetThreadTimes,0x800004A2,\\r
+       GetTickCount,0x80000217,\\r
+       GetTimeFormatW,0x800000CA,\\r
+       GetTimeZoneInformation,0x8000001B,\\r
+       GetUpdateRect,0x80000112,\\r
+       GetUpdateRgn,0x80000111,\\r
+       GetUserDefaultLangID,0x800000D4,\\r
+       GetUserDefaultLCID,0x800000D7,\\r
+       GetVersionEx,0x80000011,\\r
+       GetVersionExW,0x800002CD,\\r
+       getwchar,0x80000470,\\r
+       GetWindow,0x800000FB,\\r
+       GetWindowDC,0x8000010E,\\r
+       GetWindowLongW,0x80000103,\\r
+       GetWindowRect,0x800000F8,\\r
+       GetWindowTextLengthW,0x80000114,\\r
+       GetWindowTextW,0x80000101,\\r
+       GetWindowThreadProcessId,0x80000124,\\r
+       GiveKPhys,0x80000246,\\r
+       GlobalMemoryStatus,0x80000058,\\r
+       GwesPowerOffSystem,0x80000128,\\r
+       HeapAlloc,0x8000002E,\\r
+       HeapCreate,0x8000002C,\\r
+       HeapDestroy,0x8000002D,\\r
+       HeapFree,0x80000031,\\r
+       HeapReAlloc,0x8000002F,\\r
+       HeapSize,0x80000030,\\r
+       HeapValidate,0x80000033,\\r
+       HideCaret,0x80000294,\\r
+       ImageList_Add,0x800002E2,\\r
+       ImageList_AddMasked,0x800002E3,\\r
+       ImageList_BeginDrag,0x800002E4,\\r
+       ImageList_Copy,0x800002FF,\\r
+       ImageList_CopyDitherImage,0x800002E5,\\r
+       ImageList_Create,0x800002E6,\\r
+       ImageList_Destroy,0x800002E7,\\r
+       ImageList_DragEnter,0x800002E8,\\r
+       ImageList_DragLeave,0x800002E9,\\r
+       ImageList_DragMove,0x800002EA,\\r
+       ImageList_DragShowNolock,0x800002EB,\\r
+       ImageList_Draw,0x800002EC,\\r
+       ImageList_DrawEx,0x800002ED,\\r
+       ImageList_DrawIndirect,0x800002EE,\\r
+       ImageList_Duplicate,0x80000300,\\r
+       ImageList_EndDrag,0x800002EF,\\r
+       ImageList_GetBkColor,0x800002F0,\\r
+       ImageList_GetDragImage,0x800002F1,\\r
+       ImageList_GetIcon,0x800002F2,\\r
+       ImageList_GetIconSize,0x800002F3,\\r
+       ImageList_GetImageCount,0x800002F4,\\r
+       ImageList_GetImageInfo,0x800002F5,\\r
+       ImageList_LoadImage,0x800002F6,\\r
+       ImageList_Merge,0x800002F7,\\r
+       ImageList_Remove,0x800002F8,\\r
+       ImageList_Replace,0x800002F9,\\r
+       ImageList_ReplaceIcon,0x800002FA,\\r
+       ImageList_SetBkColor,0x800002FB,\\r
+       ImageList_SetDragCursorImage,0x800002FC,\\r
+       ImageList_SetIconSize,0x800002FD,\\r
+       ImageList_SetImageCount,0x80000301,\\r
+       ImageList_SetOverlayImage,0x800002FE,\\r
+       ImmAssociateContext,0x80000302,\\r
+       ImmAssociateContextEx,0x800004B5,\\r
+       ImmConfigureIMEW,0x80000303,\\r
+       ImmCreateContext,0x800004AE,\\r
+       ImmCreateIMCC,0x80000304,\\r
+       ImmDestroyContext,0x800004AF,\\r
+       ImmDestroyIMCC,0x80000305,\\r
+       ImmDisableIME,0x800004B6,\\r
+       ImmEnumRegisterWordW,0x80000306,\\r
+       ImmEscapeW,0x80000307,\\r
+       ImmGenerateMessage,0x80000308,\\r
+       ImmGetCandidateListCountW,0x8000030A,\\r
+       ImmGetCandidateListW,0x80000309,\\r
+       ImmGetCandidateWindow,0x8000030B,\\r
+       ImmGetCompositionFontW,0x8000030C,\\r
+       ImmGetCompositionStringW,0x8000030D,\\r
+       ImmGetCompositionWindow,0x8000030E,\\r
+       ImmGetContext,0x8000030F,\\r
+       ImmGetConversionListW,0x80000310,\\r
+       ImmGetConversionStatus,0x80000311,\\r
+       ImmGetDefaultIMEWnd,0x80000312,\\r
+       ImmGetDescriptionW,0x80000313,\\r
+       ImmGetGuideLineW,0x80000314,\\r
+       ImmGetHotKey,0x8000032D,\\r
+       ImmGetIMCCLockCount,0x80000315,\\r
+       ImmGetIMCCSize,0x80000316,\\r
+       ImmGetIMCLockCount,0x80000317,\\r
+       ImmGetIMEFileNameW,0x800004B7,\\r
+       ImmGetImeMenuItemsW,0x800004BB,\\r
+       ImmGetOpenStatus,0x80000318,\\r
+       ImmGetProperty,0x80000319,\\r
+       ImmGetRegisterWordStyleW,0x8000031A,\\r
+       ImmGetStatusWindowPos,0x800004B0,\\r
+       ImmGetVirtualKey,0x800004BA,\\r
+       ImmIsIME,0x800004B9,\\r
+       ImmIsUIMessageW,0x8000031C,\\r
+       ImmLockIMC,0x8000031D,\\r
+       ImmLockIMCC,0x8000031E,\\r
+       ImmNotifyIME,0x80000320,\\r
+       ImmRegisterWordW,0x80000322,\\r
+       ImmReleaseContext,0x80000323,\\r
+       ImmRequestMessageW,0x800004DA,\\r
+       ImmReSizeIMCC,0x80000321,\\r
+       ImmSetCandidateWindow,0x80000327,\\r
+       ImmSetCompositionFontW,0x80000328,\\r
+       ImmSetCompositionStringW,0x80000329,\\r
+       ImmSetCompositionWindow,0x8000032A,\\r
+       ImmSetConversionStatus,0x8000032B,\\r
+       ImmSetHotKey,0x8000032C,\\r
+       ImmSetImeWndIMC,0x800004C6,\\r
+       ImmSetOpenStatus,0x8000032E,\\r
+       ImmSetStatusWindowPos,0x8000032F,\\r
+       ImmSimulateHotKey,0x80000330,\\r
+       ImmSIPanelState,0x80000324,\\r
+       ImmUnlockIMC,0x80000331,\\r
+       ImmUnlockIMCC,0x80000332,\\r
+       ImmUnregisterWordW,0x80000333,\\r
+       InflateRect,0x80000062,\\r
+       InitializeCriticalSection,0x80000002,\\r
+       InitLocale,0x80000008,\\r
+       InputDebugCharW,0x80000253,\\r
+       InsertMenuW,0x80000349,\\r
+       InterlockedDecrement,0x8000000B,\\r
+       InterlockedExchange,0x8000000C,\\r
+       InterlockedIncrement,0x8000000A,\\r
+       InterlockedTestExchange,0x80000009,\\r
+       InterruptDisable,0x80000275,\\r
+       InterruptDone,0x80000274,\\r
+       InterruptInitialize,0x80000273,\\r
+       IntersectClipRect,0x800003CF,\\r
+       IntersectRect,0x80000063,\\r
+       InvalidateRect,0x800000FA,\\r
+       IsAPIReady,0x8000001E,\\r
+       IsBadCodePtr,0x80000209,\\r
+       IsBadPtr,0x80000259,\\r
+       IsBadReadPtr,0x8000020A,\\r
+       IsBadWritePtr,0x8000020B,\\r
+       IsChild,0x80000115,\\r
+       IsClipboardFormatAvailable,0x800002A6,\\r
+       IsDBCSLeadByte,0x800000BF,\\r
+       IsDBCSLeadByteEx,0x800000C0,\\r
+       IsDialogMessageW,0x800002BA,\\r
+       IsExiting,0x8000009F,\\r
+       IsPrimaryThread,0x80000262,\\r
+       IsProcessDying,0x800004BD,\\r
+       IsRectEmpty,0x80000064,\\r
+       IsValidCodePage,0x800000B9,\\r
+       IsValidLocale,0x800000D1,\\r
+       iswctype,0x800000C1,\\r
+       IsWindow,0x8000010F,\\r
+       IsWindowEnabled,0x80000120,\\r
+       IsWindowVisible,0x80000376,\\r
+       KernelIoControl,0x8000022D,\\r
+       KernExtractIcons,0x8000023E,\\r
+       keybd_event,0x80000341,\\r
+       KeybdGetDeviceInfo,0x8000033C,\\r
+       KeybdInitStates,0x8000033D,\\r
+       KeybdVKeyToUnicode,0x8000033E,\\r
+       KillAllOtherThreads,0x8000025D,\\r
+       KillTimer,0x8000036C,\\r
+       labs,0x80000406,\\r
+       LCMapStringW,0x800000C7,\\r
+       ldexp,0x80000407,\\r
+       ldiv,0x80000408,\\r
+       LeaveCriticalSection,0x80000005,\\r
+       LeaveCritSec,0x80000255,\\r
+       lineAddProvider,0x80000177,\\r
+       lineClose,0x80000166,\\r
+       lineConfigDialogEdit,0x80000176,\\r
+       lineDeallocateCall,0x80000167,\\r
+       lineDrop,0x80000168,\\r
+       lineGetDevCaps,0x80000169,\\r
+       lineGetDevConfig,0x8000016A,\\r
+       lineGetID,0x80000174,\\r
+       lineGetTranslateCaps,0x8000016B,\\r
+       lineInitialize,0x8000016C,\\r
+       lineMakeCall,0x8000016D,\\r
+       lineNegotiateAPIVersion,0x8000016E,\\r
+       lineOpen,0x8000016F,\\r
+       lineSetCurrentLocation,0x80000490,\\r
+       lineSetDevConfig,0x80000170,\\r
+       lineSetStatusMessages,0x80000171,\\r
+       lineShutdown,0x80000172,\\r
+       lineTranslateAddress,0x80000173,\\r
+       lineTranslateDialog,0x80000175,\\r
+       LoadAcceleratorsW,0x8000005E,\\r
+       LoadBitmapW,0x80000369,\\r
+       LoadCursorW,0x800002AB,\\r
+       LoadDriver,0x80000272,\\r
+       LoadFSD,0x800000ED,\\r
+       LoadIconW,0x800002D8,\\r
+       LoadImageW,0x800002DA,\\r
+       LoadLibraryW,0x80000210,\\r
+       LoadMenuW,0x8000034E,\\r
+       LoadResource,0x80000215,\\r
+       LoadStringW,0x8000036A,\\r
+       LocalAlloc,0x80000021,\\r
+       LocalAllocInProcess,0x80000029,\\r
+       LocalFileTimeToFileTime,0x80000016,\\r
+       LocalFree,0x80000024,\\r
+       LocalFreeInProcess,0x8000002A,\\r
+       LocalReAlloc,0x80000022,\\r
+       LocalSize,0x80000023,\\r
+       LocalSizeInProcess,0x8000002B,\\r
+       LockPages,0x80000489,\\r
+       log,0x80000409,\\r
+       log10,0x8000040A,\\r
+       longjmp,0x8000040C,\\r
+       lstrcmpiW,0x800000E4,\\r
+       lstrcmpW,0x800000E3,\\r
+       MainThreadBaseFunc,0x8000000E,\\r
+       malloc,0x80000411,\\r
+       MapDialogRect,0x800002BB,\\r
+       MapPtrToProcess,0x80000256,\\r
+       MapPtrUnsecure,0x80000257,\\r
+       MapUncompressedFileW,0x8000022A,\\r
+       MapViewOfFile,0x80000225,\\r
+       MapVirtualKeyW,0x8000033F,\\r
+       MapWindowPoints,0x8000011C,\\r
+       MaskBlt,0x80000388,\\r
+       mbstowcs,0x8000004C,\\r
+       memchr,0x8000001F,\\r
+       memcmp,0x80000413,\\r
+       memcpy,0x80000414,\\r
+       memmove,0x80000416,\\r
+       memset,0x80000417,\\r
+       MessageBeep,0x80000359,\\r
+       MessageBoxW,0x8000035A,\\r
+       modf,0x80000418,\\r
+       mouse_event,0x80000338,\\r
+       MoveFileW,0x800000A3,\\r
+       MoveWindow,0x80000110,\\r
+       MsgWaitForMultipleObjectsEx,0x80000367,\\r
+       MultiByteToWideChar,0x800000C4,\\r
+       NKDbgPrintfW,0x80000221,\\r
+       NKTerminateThread,0x8000026F,\\r
+       NKvDbgPrintfW,0x80000238,\\r
+       NLedGetDeviceInfo,0x80000347,\\r
+       NLedSetDevice,0x80000348,\\r
+       NotifyForceCleanboot,0x80000201,\\r
+       NotifyWinUserSystem,0x800002CC,\\r
+       OffsetRect,0x80000065,\\r
+       OffsetRgn,0x800003D0,\\r
+       OpenClipboard,0x8000029C,\\r
+       OpenProcess,0x800001FD,\\r
+       OtherThreadsRunning,0x8000025C,\\r
+       OutputDebugStringW,0x8000021D,\\r
+       PatBlt,0x800003AA,\\r
+       PeekMessageW,0x80000360,\\r
+       PegClearUserNotification,0x800001D4,\\r
+       PegCreateDatabase,0x80000130,\\r
+       PegDeleteDatabase,0x80000133,\\r
+       PegDeleteRecord,0x80000135,\\r
+       PegFindFirstDatabase,0x8000012E,\\r
+       PegFindNextDatabase,0x8000012F,\\r
+       PegGetUserNotificationPreferences,0x800001D8,\\r
+       PegHandleAppNotifications,0x800001D7,\\r
+       PegOidGetInfo,0x8000012D,\\r
+       PegOpenDatabase,0x80000132,\\r
+       PegReadRecordProps,0x80000136,\\r
+       PegRemoveFontResource,0x80000383,\\r
+       PegRunAppAtEvent,0x800001D6,\\r
+       PegRunAppAtTime,0x800001D5,\\r
+       PegSeekDatabase,0x80000134,\\r
+       PegSetDatabaseInfo,0x80000131,\\r
+       PegSetUserNotification,0x800001D3,\\r
+       PegWriteRecordProps,0x80000137,\\r
+       PlayEnhMetaFile,0x800003C1,\\r
+       PlaySoundW,0x8000017A,\\r
+       Polygon,0x800003AB,\\r
+       Polyline,0x800003AC,\\r
+       PostKeybdMessage,0x80000340,\\r
+       PostMessageW,0x80000361,\\r
+       PostQuitMessage,0x80000362,\\r
+       PostThreadMessageW,0x80000122,\\r
+       pow,0x8000041B,\\r
+       PowerOffSystem,0x80000269,\\r
+       PPSHRestart,0x8000027E,\\r
+       printf,0x8000044E,\\r
+       PrintTrackedItem,0x80000244,\\r
+       ProcessDetachAllDLLs,0x8000023C,\\r
+       ProfileStart,0x80000052,\\r
+       ProfileStop,0x80000053,\\r
+       ProfileSyscall,0x80000239,\\r
+       PSLNotify,0x80000007,\\r
+       PtInRect,0x80000066,\\r
+       PtInRegion,0x800003D1,\\r
+       PurgeComm,0x80000073,\\r
+       putchar,0x80000451,\\r
+       puts,0x80000453,\\r
+       putwchar,0x80000471,\\r
+       QASetWindowsJournalHook,0x80000335,\\r
+       QAUnhookWindowsJournalHook,0x80000336,\\r
+       qsort,0x8000041C,\\r
+       QueryAPISetID,0x800001EA,\\r
+       QueryPerformanceCounter,0x8000021A,\\r
+       QueryPerformanceFrequency,0x8000021B,\\r
+       RaiseException,0x8000021F,\\r
+       rand,0x8000041D,\\r
+       Random,0x80000050,\\r
+       RasDeleteEntry,0x8000015F,\\r
+       RasDial,0x80000156,\\r
+       RasEnumConnections,0x80000161,\\r
+       RasEnumEntries,0x80000159,\\r
+       RasGetConnectStatus,0x80000162,\\r
+       RasGetEntryDevConfig,0x80000163,\\r
+       RasGetEntryDialParams,0x8000015A,\\r
+       RasGetEntryProperties,0x8000015C,\\r
+       RasHangup,0x80000157,\\r
+       RasHangUp,0x80000158,\\r
+       RasIOControl,0x80000165,\\r
+       RasRenameEntry,0x80000160,\\r
+       RasSetEntryDevConfig,0x80000164,\\r
+       RasSetEntryDialParams,0x8000015B,\\r
+       RasSetEntryProperties,0x8000015D,\\r
+       RasValidateEntryName,0x8000015E,\\r
+       ReadFile,0x800000AA,\\r
+       ReadFileWithSeek,0x800000F3,\\r
+       ReadProcessMemory,0x800001FA,\\r
+       ReadRegistryFromOEM,0x80000481,\\r
+       RealizePalette,0x800003B9,\\r
+       realloc,0x8000041E,\\r
+       Rectangle,0x800003AD,\\r
+       RectangleAnimation,0x80000126,\\r
+       RectInRegion,0x800003D2,\\r
+       RectVisible,0x800003D5,\\r
+       RefreshKernelAlarm,0x8000024B,\\r
+       RegCloseKey,0x800001C7,\\r
+       RegCopyFile,0x800001D1,\\r
+       RegCreateKeyExW,0x800001C8,\\r
+       RegDeleteKeyW,0x800001C9,\\r
+       RegDeleteValueW,0x800001CA,\\r
+       RegEnumKeyExW,0x800001CC,\\r
+       RegEnumValueW,0x800001CB,\\r
+       RegFlushKey,0x80000480,\\r
+       RegisterAFS,0x8000014D,\\r
+       RegisterAFSName,0x80000152,\\r
+       RegisterAPISet,0x8000027B,\\r
+       RegisterClassW,0x8000005F,\\r
+       RegisterClassWStub,0x80000373,\\r
+       RegisterClipboardFormatW,0x800002A1,\\r
+       RegisterDbgZones,0x80000222,\\r
+       RegisterDevice,0x800000EB,\\r
+       RegisterHiddenAFS,0x8000014E,\\r
+       RegisterHotKey,0x80000343,\\r
+       RegisterSIPanel,0x80000125,\\r
+       RegisterTaskBar,0x8000037C,\\r
+       RegisterTrackedItem,0x80000248,\\r
+       RegisterWindowMessageW,0x8000037B,\\r
+       RegOpenKeyExW,0x800001CD,\\r
+       RegQueryInfoKeyW,0x800001CE,\\r
+       RegQueryValueExW,0x800001CF,\\r
+       RegRestoreFile,0x800001D2,\\r
+       RegSetValueExW,0x800001D0,\\r
+       ReleaseCapture,0x800002C5,\\r
+       ReleaseDC,0x80000107,\\r
+       ReleaseMutex,0x8000022C,\\r
+       RemoteLocalAlloc,0x80000025,\\r
+       RemoteLocalFree,0x80000028,\\r
+       RemoteLocalReAlloc,0x80000026,\\r
+       RemoteLocalSize,0x80000027,\\r
+       RemoveDirectoryW,0x800000A1,\\r
+       RemoveFontResourceW,0x80000384,\\r
+       RemoveMenu,0x8000034B,\\r
+       RestoreDC,0x8000038B,\\r
+       ResumeThread,0x800001F4,\\r
+       RoundRect,0x800003AE,\\r
+       SaveDC,0x8000038C,\\r
+       scanf,0x8000044D,\\r
+       ScreenToClient,0x800000FF,\\r
+       ScrollDC,0x800003D9,\\r
+       ScrollWindowEx,0x80000121,\\r
+       SelectClipRgn,0x800003D3,\\r
+       SelectObject,0x80000399,\\r
+       SelectPalette,0x800003BA,\\r
+       SendDlgItemMessageW,0x800002AD,\\r
+       SendInput,0x80000337,\\r
+       SendMessageW,0x80000364,\\r
+       SendNotifyMessageW,0x80000365,\\r
+       SetAbortProc,0x800003C2,\\r
+       SetACP,0x800000BD,\\r
+       SetActiveWindow,0x800002BF,\\r
+       SetAssociatedMenu,0x8000012B,\\r
+       SetBkColor,0x8000039A,\\r
+       SetBkMode,0x8000039B,\\r
+       SetBrushOrgEx,0x800003AF,\\r
+       SetCapture,0x800002C4,\\r
+       SetCaretBlinkTime,0x80000298,\\r
+       SetCaretPos,0x80000296,\\r
+       SetClassLong,0x80000372,\\r
+       SetClassLongW,0x80000370,\\r
+       SetCleanRebootFlag,0x80000267,\\r
+       SetClipboardData,0x8000029F,\\r
+       SetCommBreak,0x80000074,\\r
+       SetCommMask,0x80000075,\\r
+       SetCommState,0x80000076,\\r
+       SetCommTimeouts,0x80000077,\\r
+       SetCursor,0x800002AA,\\r
+       SetCursorPos,0x800002E0,\\r
+       SetDaylightTime,0x80000223,\\r
+       SetDbgZone,0x8000026A,\\r
+       SetDlgItemInt,0x800002BC,\\r
+       SetDlgItemTextW,0x800002AE,\\r
+       SetEndOfFile,0x800000B2,\\r
+       SetExceptionHandler,0x80000247,\\r
+       SetFileAttributesW,0x800000A9,\\r
+       SetFilePointer,0x800000AD,\\r
+       SetFileTime,0x800000B1,\\r
+       SetFocus,0x800002C0,\\r
+       SetForegroundWindow,0x800002BE,\\r
+       SetGwesHeapMark,0x80000265,\\r
+       SetGwesOOMEvent,0x8000024E,\\r
+       SetGwesPowerHandler,0x80000278,\\r
+       SetHandleOwner,0x80000271,\\r
+       SetHardwareWatch,0x8000027A,\\r
+       SetInterruptEvent,0x8000009E,\\r
+       setjmp,0x80000806,\\r
+       SetKernelAlarm,0x8000024A,\\r
+       SetKeyboardTarget,0x800002C6,\\r
+       SetKMode,0x80000276,\\r
+       SetLastError,0x80000205,\\r
+       SetLocaleInfoW,0x800000C9,\\r
+       SetLocalTime,0x80000018,\\r
+       SetLowestScheduledPriority,0x80000261,\\r
+       SetMenuItemInfoW,0x80000355,\\r
+       SetObjectOwner,0x800003D8,\\r
+       SetOEMCP,0x800000BE,\\r
+       SetPaletteEntries,0x800003B7,\\r
+       SetParent,0x8000010C,\\r
+       SetPassword,0x800000EE,\\r
+       SetPasswordActive,0x800000F0,\\r
+       SetPFHandle,0x8000024C,\\r
+       SetPixel,0x800003B0,\\r
+       SetPowerOffHandler,0x80000277,\\r
+       SetProcPermissions,0x80000263,\\r
+       SetRealTime,0x8000023B,\\r
+       SetRect,0x80000067,\\r
+       SetRectEmpty,0x80000068,\\r
+       SetRectRgn,0x800003D6,\\r
+       SetROP2,0x800003A0,\\r
+       SetScrollInfo,0x80000117,\\r
+       SetScrollPos,0x80000118,\\r
+       SetScrollRange,0x80000119,\\r
+       SetStdioPathW,0x8000047E,\\r
+       SetSysColors,0x8000037A,\\r
+       SetSystemDefaultLCID,0x800000D6,\\r
+       SetSystemMemoryDivision,0x80000151,\\r
+       SetSystemTime,0x8000001A,\\r
+       SetTextColor,0x8000039C,\\r
+       SetThreadContext,0x800001F6,\\r
+       SetThreadPriority,0x80000202,\\r
+       SetTimer,0x8000036B,\\r
+       SetTimeZoneBias,0x80000266,\\r
+       SetTimeZoneInformation,0x8000001C,\\r
+       SetupComm,0x80000078,\\r
+       SetViewportOrgEx,0x800003D7,\\r
+       SetWDevicePowerHandler,0x8000049A,\\r
+       SetWindowLongW,0x80000102,\\r
+       SetWindowPos,0x800000F7,\\r
+       SetWindowsHookExW,0x800004B2,\\r
+       SetWindowTextW,0x80000100,\\r
+       SHAddToRecentDocs,0x800001E3,\\r
+       SHCreateExplorerInstance,0x8000048B,\\r
+       SHCreateShortcut,0x800001E4,\\r
+       Shell_NotifyIcon,0x800001E1,\\r
+       ShellExecuteEx,0x800001E0,\\r
+       ShellModalEnd,0x800002C8,\\r
+       SHGetFileInfo,0x800001E2,\\r
+       SHGetShortcutTarget,0x800001E5,\\r
+       SHLoadDIBitmap,0x800001E7,\\r
+       ShowCaret,0x80000295,\\r
+       ShowCursor,0x800002E1,\\r
+       ShowWindow,0x8000010A,\\r
+       SHShowOutOfMemory,0x800001E6,\\r
+       SignalStarted,0x8000027F,\\r
+       sin,0x80000422,\\r
+       sinh,0x80000423,\\r
+       SizeofResource,0x80000216,\\r
+       Sleep,0x800001F0,\\r
+       sndPlaySoundW,0x80000179,\\r
+       sprintf,0x800002CF,\\r
+       sqrt,0x80000424,\\r
+       srand,0x80000425,\\r
+       sscanf,0x8000028D,\\r
+       StartDocW,0x800003C3,\\r
+       StartPage,0x800003C4,\\r
+       strcat,0x80000427,\\r
+       strchr,0x80000428,\\r
+       strcmp,0x80000429,\\r
+       strcpy,0x8000042A,\\r
+       strcspn,0x8000042B,\\r
+       StretchBlt,0x80000389,\\r
+       StringCompress,0x8000024F,\\r
+       StringDecompress,0x80000250,\\r
+       strlen,0x8000042C,\\r
+       strncat,0x8000042D,\\r
+       strncmp,0x8000042E,\\r
+       strncpy,0x8000042F,\\r
+       strstr,0x80000430,\\r
+       strtok,0x80000431,\\r
+       SubtractRect,0x80000069,\\r
+       SuspendThread,0x800001F3,\\r
+       swprintf,0x80000449,\\r
+       swscanf,0x8000044A,\\r
+       SystemIdleTimerReset,0x80000345,\\r
+       SystemMemoryLow,0x800002D0,\\r
+       SystemParametersInfoW,0x80000059,\\r
+       SystemStarted,0x80000001,\\r
+       SystemTimeToFileTime,0x80000013,\\r
+       TakeCritSec,0x80000254,\\r
+       tan,0x80000433,\\r
+       tanh,0x80000434,\\r
+       TerminateProcess,0x80000220,\\r
+       TerminateThread,0x800001EB,\\r
+       THCreateSnapshot,0x800001FF,\\r
+       THGrow,0x80000200,\\r
+       ThisIsGwes,0x80000035,\\r
+       ThreadAttachAllDLLs,0x80000231,\\r
+       ThreadBaseFunc,0x8000000D,\\r
+       ThreadDetachAllDLLs,0x80000232,\\r
+       TlsCall,0x80000208,\\r
+       TlsGetValue,0x8000000F,\\r
+       TlsSetValue,0x80000010,\\r
+       tolower,0x80000442,\\r
+       TouchCalibrate,0x8000036D,\\r
+       toupper,0x80000443,\\r
+       towlower,0x800000C2,\\r
+       towupper,0x800000C3,\\r
+       TrackPopupMenuEx,0x8000034D,\\r
+       TranslateAcceleratorW,0x80000346,\\r
+       TranslateCharsetInfo,0x8000048E,\\r
+       TranslateMessage,0x80000366,\\r
+       TransmitCommChar,0x80000079,\\r
+       TransparentImage,0x8000038A,\\r
+       TurnOffProfiling,0x8000026C,\\r
+       TurnOffSyscallProfiling,0x8000026E,\\r
+       TurnOnProfiling,0x8000026B,\\r
+       TurnOnSyscallProfiling,0x8000026D,\\r
+       U_rclose,0x80000237,\\r
+       U_rlseek,0x80000236,\\r
+       U_ropen,0x80000233,\\r
+       U_rread,0x80000234,\\r
+       U_rwrite,0x80000235,\\r
+       ungetc,0x80000458,\\r
+       ungetwc,0x80000476,\\r
+       UnhookWindowsHookEx,0x800004B3,\\r
+       UnionRect,0x8000006A,\\r
+       UnlockPages,0x8000048A,\\r
+       UnmapViewOfFile,0x80000226,\\r
+       UnregisterClassW,0x80000374,\\r
+       UnregisterFunc1,0x80000484,\\r
+       UnregisterHotKey,0x80000344,\\r
+       UpdateWindow,0x8000010B,\\r
+       ValidateRect,0x80000116,\\r
+       VerifyAPIHandle,0x8000027D,\\r
+       vfprintf,0x8000045C,\\r
+       vfwprintf,0x800002D1,\\r
+       VirtualAlloc,0x8000020C,\\r
+       VirtualCopy,0x80000230,\\r
+       VirtualFree,0x8000020D,\\r
+       VirtualProtect,0x8000020E,\\r
+       VirtualQuery,0x8000020F,\\r
+       vprintf,0x8000044F,\\r
+       vsprintf,0x8000047A,\\r
+       vswprintf,0x8000044B,\\r
+       vwprintf,0x8000046F,\\r
+       WaitCommEvent,0x8000007A,\\r
+       WaitForDebugEvent,0x800001F7,\\r
+       WaitForMultipleObjects,0x800001F2,\\r
+       WaitForSingleObject,0x800001F1,\\r
+       waveInAddBuffer,0x80000196,\\r
+       waveInClose,0x80000193,\\r
+       waveInGetDevCaps,0x80000191,\\r
+       waveInGetErrorText,0x80000192,\\r
+       waveInGetID,0x8000019B,\\r
+       waveInGetNumDevs,0x80000190,\\r
+       waveInGetPosition,0x8000019A,\\r
+       waveInMessage,0x8000019C,\\r
+       waveInOpen,0x8000019D,\\r
+       waveInPrepareHeader,0x80000194,\\r
+       waveInReset,0x80000199,\\r
+       waveInStart,0x80000197,\\r
+       waveInStop,0x80000198,\\r
+       waveInUnprepareHeader,0x80000195,\\r
+       waveOutBreakLoop,0x80000187,\\r
+       waveOutClose,0x80000180,\\r
+       waveOutGetDevCaps,0x8000017C,\\r
+       waveOutGetErrorText,0x8000017F,\\r
+       waveOutGetID,0x8000018D,\\r
+       waveOutGetNumDevs,0x8000017B,\\r
+       waveOutGetPitch,0x80000189,\\r
+       waveOutGetPlaybackRate,0x8000018B,\\r
+       waveOutGetPosition,0x80000188,\\r
+       waveOutGetVolume,0x8000017D,\\r
+       waveOutMessage,0x8000018E,\\r
+       waveOutOpen,0x8000018F,\\r
+       waveOutPause,0x80000184,\\r
+       waveOutPrepareHeader,0x80000181,\\r
+       waveOutReset,0x80000186,\\r
+       waveOutRestart,0x80000185,\\r
+       waveOutSetPitch,0x8000018A,\\r
+       waveOutSetPlaybackRate,0x8000018C,\\r
+       waveOutSetVolume,0x8000017E,\\r
+       waveOutUnprepareHeader,0x80000182,\\r
+       waveOutWrite,0x80000183,\\r
+       wcscat,0x8000003A,\\r
+       wcschr,0x8000003B,\\r
+       wcscmp,0x8000003C,\\r
+       wcscpy,0x8000003D,\\r
+       wcscspn,0x8000003E,\\r
+       wcslen,0x8000003F,\\r
+       wcsncat,0x80000040,\\r
+       wcsncmp,0x80000041,\\r
+       wcsncpy,0x80000042,\\r
+       wcspbrk,0x80000044,\\r
+       wcsrchr,0x80000045,\\r
+       wcsspn,0x80000048,\\r
+       wcsstr,0x80000049,\\r
+       wcstod,0x80000439,\\r
+       wcstok,0x8000004D,\\r
+       wcstol,0x8000043A,\\r
+       wcstombs,0x8000004B,\\r
+       wcstoul,0x8000043B,\\r
+       WideCharToMultiByte,0x800000C5,\\r
+       WindowFromPoint,0x800000FC,\\r
+       WNetAddConnection3W,0x800001BC,\\r
+       WNetCancelConnection2W,0x800001BD,\\r
+       WNetCloseEnum,0x800001C5,\\r
+       WNetConnectionDialog1W,0x800001BE,\\r
+       WNetDisconnectDialog,0x800001BF,\\r
+       WNetDisconnectDialog1W,0x800001C0,\\r
+       WNetEnumResourceW,0x800001C6,\\r
+       WNetGetConnectionW,0x800001C1,\\r
+       WNetGetUniversalNameW,0x800001C2,\\r
+       WNetGetUserW,0x800001C3,\\r
+       WNetOpenEnumW,0x800001C4,\\r
+       wprintf,0x8000046E,\\r
+       WriteDebugLED,0x80000483,\\r
+       WriteFile,0x800000AB,\\r
+       WriteFileWithSeek,0x800002CE,\\r
+       WriteProcessMemory,0x800001FB,\\r
+       WriteRegistryToOEM,0x80000482,\\r
+       wscanf,0x8000046D,\\r
+       wsprintfW,0x80000038,\\r
+       wvsprintfW,0x80000039\r

diff --git a/include/macro/armlitrl.inc b/include/macro/armlitrl.inc
new file mode 100644 (file)
index 0000000..7ed58c2
--- /dev/null
+++ b/include/macro/armlitrl.inc
@@ -0,0 +1,223 @@
+;FASMARM extension macros:\r
+;\r
+;Macros for using large constants directly with data processing and memory instructions\r
+;\r
+;Access to the macros is always with the first three characters as uppercase.\r
+;This is necessary to prevent excess memory usage with normal instructions not requiring this functionality.\r
+;\r
+;NOTE: these macro use R12 (ip) for intermediate values. Don't rely on R12 being preserved.\r
+;\r
+;These macros are NOT compatible with thumb mode\r
+;\r
+;These macros allow you to do things like this:\r
+;\r
+;ADDne r11,r2,0x12345678   ;compiles to "ldrne r11,[pc,..lit?0]" and "addne r11,r2,r11"   with "..lit?0 dw 0x12345678"\r
+;ADD   r11,r11,0x12345678  ;compiles to "ldr r12,[pc,..lit?0]"   and "add r11,r11,r12"\r
+;LDRhi r0,[r0,-0x12345678] ;compiles to "ldrhi r12,[pc,..lit?0]" and "ldrhi r0,[r0,-r12]"\r
+;STRb  r0,[r3,0xcc000000]  ;compiles to "mov r12,0xcc000000"     and "strb r0,[r3,r12]"\r
+;CMP   r2,0x101            ;compiles to "ldr r12,[pc,..lit?1]"   and "cmp r2,r12"         with "..lit?1 dw 0x101"\r
+;CMP   r2,0x100            ;compiles to "cmp r2,0x100"\r
+;\r
+;Notice that the allocation of literals is optimised to reuse values where possible and only allocated when necessary.\r
+;\r
+;You will need to periodically dump the literals to the output before the labels get more than 4Kbytes distant\r
+;from the source instruction. Generally you can do this after an unconditional branch, and usually at the\r
+;end of a procedure. Simply dump at an appropriate place with "literals".\r
+;\r
+;These macros will correctly handle any ARM format the assembler can handle, so you could do all your code by using\r
+;these macros, but this can create excessive demands on memory and increases compilation time. These macros are\r
+;especially useful where you might use symbolic constants and not be sure of the required size. Just put the base\r
+;instruction in uppercase and let the macros decide the best encoding for you.\r
+;\r
+;The PROCAPS.INC macros have ben designed to use these macros also. When you include this file along with PROCAPS.INC\r
+;then they will cooperate to produce easy to program and also optimised output for your project.\r
+;\r
+;By default this file is included from "WINCEX.INC".\r
+\r
+macro make_dp_instr instr,suffix,regs,flag {\r
+ irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{\r
+  match inst,instr\#cond\#suffix\\{\r
+   macro inst regs,[arg] \\\{\r
+    \\\common\r
+    \\\local encoding,..lit,z,c,..pc,arg_pc\r
+    if ~ defined encoding | encoding <> 0xf7ffffff\r
+     inst regs,arg\r
+     load encoding word from $-4\r
+    else\r
+     ..pc=$\r
+     match billg =$ lots,:arg: \\\\{match :a:,billg\\\\#..pc\\\\#lots \\\\\{arg_pc equ a\\\\\}\\\\}\r
+     match =arg_pc,arg_pc \\\\{arg_pc equ arg\\\\}\r
+     match ra=,rb:ld,regs:ldr\#cond \\\\{\r
+      match =pc,rb\\\\\{arg_pc equ arg_pc-4\\\\\}\r
+      match =r15,rb\\\\\{arg_pc equ arg_pc-4\\\\\}\r
+      if ra eq rb\r
+       if ra eq ip\r
+       halt ;cannot use ip,ip,large constant\r
+       end if\r
+       ld ip,[pc,..lit-$-8]\r
+       inst regs,ip\r
+      else\r
+       ld ra,[pc,..lit-$-8]\r
+       inst regs,ra\r
+      end if\r
+     \\\\}\r
+     match =0:ld,flag:ldr\#cond \\\\{\r
+      ld ip,[pc,..lit-$-8]\r
+      instr regs,ip\r
+     \\\\}\r
+     match =1:ld,flag:ldr\#cond \\\\{\r
+      ld regs,[pc,..lit-$-8]\r
+     \\\\}\r
+     if arg eqtype 0\r
+      virtual\r
+       dW arg_pc\r
+       load c word from $-4\r
+      end virtual\r
+      repeat 17\r
+       if %=17\r
+       encoding=0xf7ffffff\r
+       break\r
+       end if\r
+       if (c shl(%*2-2))or(c shr(34-%*2))and 0xffffff00=0\r
+       encoding=0\r
+       break\r
+       end if\r
+      end repeat\r
+     end if\r
+     macro z \\\\{\r
+      if defined encoding & encoding = 0xf7ffffff\r
+       literal@found=0\r
+       repeat ($-literals@start)/4\r
+       load literal@value word from literals@start+(%-1)*4\r
+       if literal@value=c\r
+        label ..lit word at literals@start+(%-1)*4\r
+        literal@found=1\r
+        break\r
+       end if\r
+       end repeat\r
+       if ~ literal@found\r
+       ..lit dW arg_pc\r
+       end if\r
+      end if\r
+     \\\\}\r
+     literal@words equ literal@words,z\r
+    end if\r
+   \\\}\r
+  \\}\r
+ \}\r
+}\r
+\r
+irps instr,ADC ADD AND BIC EOR ORR RSB RSC SBC SUB {\r
+ make_dp_instr instr,,<rd,rn>\r
+ make_dp_instr instr,s,<rd,rn>\r
+}\r
+irps instr,CMN CMP TST TEQ {\r
+ make_dp_instr instr,,rn,0\r
+}\r
+irps instr,MOV MVN {\r
+ make_dp_instr instr,,rd,1\r
+ make_dp_instr instr,s,rd,1\r
+}\r
+purge make_dp_instr\r
+\r
+macro make_mem_instr instr,suffix,limit {\r
+ irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{\r
+  match inst,instr\#cond\#suffix\\{\r
+   macro inst reg,[arg] \\\{\r
+    \\\common\r
+    \\\local off,pre,rn,bru,minus\r
+     minus equ\r
+     off equ\r
+     match [r=,o],arg \\\\{\r
+      rn equ r\r
+      bru equ\r
+      off equ o\r
+      pre equ 1\r
+     \\\\}\r
+     match [r=,o]=!,arg \\\\{\r
+      rn equ r\r
+      bru equ !\r
+      off equ o\r
+      pre equ 1\r
+     \\\\}\r
+     match [r]=,o,arg \\\\{\r
+      rn equ r\r
+      off equ o\r
+      pre equ 0\r
+     \\\\}\r
+     match ,off \\\\{\r
+      inst reg,arg\r
+     \\\\}\r
+     match val:mv,off:MOV\#cond \\\\{\r
+      if off eqtype 0\r
+       if off>=limit | off<=-limit\r
+       match -o,off\\\\\{\r
+        off equ o\r
+        minus equ -\r
+       \\\\\}\r
+       mv ip,off\r
+       match =1,pre\\\\\{inst reg,[rn,minus ip]bru\\\\\}\r
+       match =0,pre\\\\\{inst reg,[rn],minus ip\\\\\}\r
+       else\r
+       inst reg,arg\r
+       end if\r
+      else\r
+       inst reg,arg\r
+      end if\r
+     \\\\}\r
+   \\\}\r
+  \\}\r
+ \}\r
+}\r
+irps instr,LDR STR {\r
+ make_mem_instr instr,,4096\r
+ make_mem_instr instr,b,4096\r
+ make_mem_instr instr,bt,4096\r
+ make_mem_instr instr,t,4096\r
+ make_mem_instr instr,h,256\r
+ make_mem_instr instr,d,256\r
+}\r
+make_mem_instr LDR,sh,256\r
+make_mem_instr LDR,sb,256\r
+\r
+purge make_mem_instr\r
+\r
+macro def_astring labl,[string] {\r
+       common\r
+       local ..db,z\r
+       labl=..db\r
+       macro z \{\r
+               if defined labl\r
+                       ..db dB string\r
+               end if\r
+       \}\r
+       literal@astrings equ literal@astrings,z\r
+}\r
+\r
+macro def_ustring labl,[string] {\r
+       common\r
+       local ..du,z\r
+       labl=..du\r
+       macro z \{\r
+               if defined labl\r
+                       align 2\r
+                       ..du dU string\r
+               end if\r
+       \}\r
+       literal@ustrings equ literal@ustrings,z\r
+}\r
+\r
+literal@words equ align 4,literals@start=$\r
+literal@ustrings equ align 2\r
+literal@astrings equ align 1\r
+\r
+macro literals {\r
+       match j,literal@words,literal@ustrings,literal@astrings\{\r
+               irp i,j\\{\r
+                       i\r
+               \\}\r
+       \}\r
+       literal@words equ align 4,literals@start=$\r
+       literal@ustrings equ align 2\r
+       literal@astrings equ align 1\r
+}\r

diff --git a/include/macro/armresrc.inc b/include/macro/armresrc.inc
new file mode 100644 (file)
index 0000000..2c5028c
--- /dev/null
+++ b/include/macro/armresrc.inc
@@ -0,0 +1,19 @@
+\r
+;Macroinstructions for making resources for WinCE with FASMARM\r
+;By default this file is included from "WINCE.INC".\r
+\r
+       dq fix dd\r
+       dd fix dw\r
+       dw fix dh\r
+       rq fix rd\r
+       rd fix rw\r
+       rw fix rh\r
+\r
+       include 'macro\resource.inc'\r
+\r
+       rw fix rw\r
+       rd fix rd\r
+       rq fix rq\r
+       dw fix dw\r
+       dd fix dd\r
+       dq fix dq\r

diff --git a/include/macro/armstruc.inc b/include/macro/armstruc.inc
new file mode 100644 (file)
index 0000000..b98956f
--- /dev/null
+++ b/include/macro/armstruc.inc
@@ -0,0 +1,199 @@
+\r
+;Macroinstructions for defining data structures with FASMARM\r
+;By default this file is included from "WINCE.INC".\r
+\r
+macro struct name\r
+ { fields@struct equ name\r
+   match child parent, name \{ fields@struct equ child,fields@\#parent \}\r
+   sub@struct equ\r
+   struc db [val] \{ \common define field@struct .,db,<val>\r
+                            fields@struct equ fields@struct,field@struct \}\r
+   struc dh [val] \{ \common define field@struct .,dh,<val>\r
+                            fields@struct equ fields@struct,field@struct \}\r
+   struc du [val] \{ \common define field@struct .,du,<val>\r
+                            fields@struct equ fields@struct,field@struct \}\r
+   struc dw [val] \{ \common define field@struct .,dw,<val>\r
+                            fields@struct equ fields@struct,field@struct \}\r
+   struc dd [val] \{ \common define field@struct .,dd,<val>\r
+                            fields@struct equ fields@struct,field@struct \}\r
+   struc rb count \{ define field@struct .,db,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   struc rh count \{ define field@struct .,dh,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   struc rw count \{ define field@struct .,dw,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   struc rd count \{ define field@struct .,dd,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro db [val] \{ \common \local anonymous\r
+                    define field@struct anonymous,db,<val>\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro dh [val] \{ \common \local anonymous\r
+                    define field@struct anonymous,dh,<val>\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro du [val] \{ \common \local anonymous\r
+                    define field@struct anonymous,du,<val>\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro dw [val] \{ \common \local anonymous\r
+                    define field@struct anonymous,dw,<val>\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro dd [val] \{ \common \local anonymous\r
+                    define field@struct anonymous,dd,<val>\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro rb count \{ \local anonymous\r
+                    define field@struct anonymous,db,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro rh count \{ \local anonymous\r
+                    define field@struct anonymous,dh,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro rw count \{ \local anonymous\r
+                    define field@struct anonymous,dw,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro rd count \{ \local anonymous\r
+                    define field@struct anonymous,dd,count dup (?)\r
+                    fields@struct equ fields@struct,field@struct \}\r
+   macro union \{ fields@struct equ fields@struct,,union,<\r
+                 sub@struct equ union \}\r
+   macro struct \{ fields@struct equ fields@struct,,substruct,<\r
+                 sub@struct equ substruct \}\r
+   virtual at 0 }\r
+\r
+macro ends\r
+ { match , sub@struct \{ restruc db,dh,du,dw,dd\r
+                        restruc rb,rh,rw,rd\r
+                        purge db,dh,du,dw,dd\r
+                        purge rb,rh,rw,rd\r
+                        purge union,struct\r
+                        match name=,fields,fields@struct \\{ fields@struct equ\r
+                                                             make@struct name,fields\r
+                                                             define fields@\\#name fields \\}\r
+                        end virtual \}\r
+   match any, sub@struct \{ fields@struct equ fields@struct> \}\r
+   restore sub@struct }\r
+\r
+macro make@struct name,[field,type,def]\r
+ { common\r
+    if $\r
+     display 'Error: definition of ',`name,' contains illegal instructions.',0Dh,0Ah\r
+     err\r
+    end if\r
+    local define\r
+    define equ name\r
+   forward\r
+    local sub\r
+    match , field \{ make@substruct type,name,sub def\r
+                    define equ define,.,sub, \}\r
+    match any, field \{ define equ define,.#field,type,<def> \}\r
+   common\r
+    match fields, define \{ define@struct fields \} }\r
+\r
+macro define@struct name,[field,type,def]\r
+ { common\r
+    local list\r
+    list equ\r
+   forward\r
+    if ~ field eq .\r
+     name#field type def\r
+     sizeof.#name#field = $ - name#field\r
+    else\r
+     label name#.#type\r
+     rb sizeof.#type\r
+    end if\r
+    local value\r
+    match any, list \{ list equ list, \}\r
+    list equ list <value>\r
+   common\r
+    sizeof.#name = $\r
+    restruc name\r
+    match values, list \{\r
+    struc name value \\{\r
+    match any, fields@struct \\\{ fields@struct equ fields@struct,.,name,<values> \\\}\r
+    match , fields@struct \\\{ label .\r
+   forward\r
+     match , value \\\\{ field type def \\\\}\r
+     match any, value \\\\{ field type value\r
+                           if ~ field eq .\r
+                            rb sizeof.#name#field - ($-field)\r
+                           end if \\\\}\r
+   common \\\} \\}\r
+    macro name value \\{\r
+   forward\r
+     match , value \\\{ type def \\\}\r
+     match any, value \\\{ \\\local ..field\r
+                          ..field: type value\r
+                          if ~ field eq .\r
+                           rb sizeof.#name#field - ($-..field)\r
+                          end if \\\}\r
+   common \\} \} }\r
+macro enable@substruct\r
+ { macro make@substruct substruct,parent,name,[field,type,def]\r
+    \{ \common\r
+       \local define\r
+       define equ parent,name\r
+       \forward\r
+       \local sub\r
+       match , field \\{ match any, type \\\{ enable@substruct\r
+                                              make@substruct type,name,sub def\r
+                                              purge make@substruct\r
+                                              define equ define,.,sub, \\\} \\}\r
+       match any, field \\{ define equ define,.\#field,type,<def> \\}\r
+       \common\r
+       match fields, define \\{ define@\#substruct fields \\} \} }\r
+\r
+enable@substruct\r
+\r
+macro define@union parent,name,[field,type,def]\r
+ { common\r
+    virtual at parent#.#name\r
+   forward\r
+    if ~ field eq .\r
+     virtual at parent#.#name\r
+      parent#field type def\r
+      sizeof.#parent#field = $ - parent#field\r
+     end virtual\r
+     if sizeof.#parent#field > $ - parent#.#name\r
+      rb sizeof.#parent#field - ($ - parent#.#name)\r
+     end if\r
+    else\r
+     label name#.#type at parent#.#name\r
+     if sizeof.#type > $ - parent#.#name\r
+      rb sizeof.#type - ($ - parent#.#name)\r
+     end if\r
+    end if\r
+   common\r
+    sizeof.#name = $ - parent#.#name\r
+    end virtual\r
+    struc name [value] \{ \common\r
+    label .\#name\r
+    last@union equ\r
+   forward\r
+    match any, last@union \\{ virtual at .\#name\r
+                              field type def\r
+                             end virtual \\}\r
+    match , last@union \\{ match , value \\\{ field type def \\\}\r
+                          match any, value \\\{ field type value \\\} \\}\r
+    last@union equ field\r
+   common rb sizeof.#name - ($ - .\#name) \} }\r
+\r
+macro define@substruct parent,name,[field,type,def]\r
+ { common\r
+    virtual at parent#.#name\r
+   forward\r
+    if ~ field eq .\r
+     parent#field type def\r
+     sizeof.#parent#field = $ - parent#field\r
+    else\r
+     label name#.#type\r
+     rb sizeof.#type\r
+    end if\r
+   common\r
+    sizeof.#name = $ - parent#.#name\r
+    end virtual\r
+    struc name value \{\r
+    label .\#name\r
+   forward\r
+     match , value \\{ field type def \\}\r
+     match any, value \\{ field type value\r
+                         if ~ field eq .\r
+                          rb sizeof.#parent#field - ($-field)\r
+                         end if \\}\r
+   common \} }\r

diff --git a/include/macro/importce.inc b/include/macro/importce.inc
new file mode 100644 (file)
index 0000000..e681daf
--- /dev/null
+++ b/include/macro/importce.inc
@@ -0,0 +1,67 @@
+;FASMARM extension macros:\r
+;\r
+;Macros for imports section in PE file generation\r
+;\r
+;LIBRARY:\r
+;\r
+;  Usage: library name1,string1,name2,string2,...\r
+;\r
+;  name   - a prefix for program labels identifying data structures\r
+;  string - a text ascii string identifying the DLL filename\r
+;\r
+;\r
+;IMPORT:\r
+;\r
+;  Usage: import name,function1,ordinal1,function2,ordinal2,...\r
+;\r
+;  name     - a prefix for program labels identifying data structures\r
+;  function - program label for the import\r
+;  ordinal  - the DLL exported ordinal\r
+;\r
+;By default this file is included from "WINCE.INC".\r
+\r
+\r
+macro library [name,string] {\r
+    common\r
+       align 4\r
+   ;;  data import\r
+    forward\r
+       if defined name#_required\r
+           dw RVA name,0,0,RVA name#_name,RVA name\r
+       end if\r
+    common\r
+       rw 5\r
+   ;;  end data\r
+    forward\r
+       if defined name#_required\r
+           name#_name: db string,0\r
+       end if\r
+    common\r
+       align 4\r
+}\r
+\r
+macro import name,[function,ordinal] {\r
+    common\r
+       align 4\r
+       name:\r
+    forward\r
+       if used _#function\r
+           _#function dw ordinal\r
+       end if\r
+    common\r
+       if $-name>0\r
+           name#_required=1\r
+           dw 0\r
+       end if\r
+    forward\r
+       if used function\r
+         function:\r
+         if $+8-_#function<4096\r
+           ldr pc,[pc,_#function-$-8]\r
+         else\r
+           ldr r12,[pc]\r
+           ldr pc,[r12]\r
+           dw _#function\r
+         end if\r
+       end if\r
+}\r

diff --git a/include/macro/procaps.inc b/include/macro/procaps.inc
new file mode 100644 (file)
index 0000000..f71443c
--- /dev/null
+++ b/include/macro/procaps.inc
@@ -0,0 +1,690 @@
+;FASMARM extension macros:\r
+;\r
+;High level procedure macros for APS (ARM Procedure Standard) calling\r
+;\r
+;The APS call standard requires the first four parameters to be passed in registers r0-r3, any remaining\r
+;parameters are placed on the stack and pushed in reverse order. The stack is always full descending.\r
+;Caller always restores the stack. Any return values are in r0-r3.\r
+;\r
+;r4-r11 must always be preserved by procedures.\r
+;r12 is always a scratch register and considered corruptable.\r
+;r13 is always the stack register and is always used in full descending mode.\r
+;r14 is always the return address and considered corruptable.\r
+;\r
+;These macros are NOT compatible with thumb mode\r
+;\r
+;\r
+;APSCALL:\r
+;\r
+;  Usage: apscall name, arg1, size[arg2], addr arg3, [arg4], 'string', *'string', 'A'+0, ...\r
+;\r
+;  name      - required - specifies the name of the target procedure\r
+;  args      - optional - any arguments required by the target procedure\r
+;  addr      - refers to a PC relative address or a frame pointer relative address\r
+;  size      - size override operator, can be byte, sbyte, hword, shword or word\r
+;              byte   - zero extended byte value to 32 bit\r
+;              sbyte  - sign extended byte value to 32 bit\r
+;              hword  - zero extended half word value to 32 bit\r
+;              shword - sign extended half word value to 32 bit\r
+;              word   - 32 bit value\r
+;  [arg]     - value stored at address arg\r
+;  'string'  - literal ascii string placed directly in the code stream. For convenience\r
+;  *'string' - literal unicode string placed directly in the code stream. For convenience\r
+;  'A'+0     - immediate value zero extended to 32 bit, can be 1 through 4 characters in length\r
+;\r
+;  NOTE: "apscall" is safe to use inside an SP frame based procedure. The macro properly allocates the stack.\r
+;\r
+;\r
+;PROC:\r
+;\r
+;  Usage: proc   name   base reg   uses [reg, reg-reg, reg]   nospill  ,arg1, arg2, arg3, ...\r
+;\r
+;  paramters:\r
+;\r
+;  name     - required - specifies the name of the procedure\r
+;  base reg - optional - specifies the base register to use for the stack frame, default is R11 (fp)\r
+;  uses [.] - optional - lists registers to be saved upon entry and restored upon exit. Square brackets are required.\r
+;                        NOTE: if you specify LR to be saved it will be automatically restored to PC upon exit\r
+;  nospill  - optional - specifies the first four parameters are not to be spilled to the stack upon entry\r
+;                        See the "To spill or not to spill?" note\r
+;  args     - optional - input arguments from calling procedure, must be started with and separated by commas\r
+;\r
+;  "name" must be first.\r
+;  "base reg", "uses [.]" and "nospill" can be specified in any order after "name".\r
+;  "args" must be placed last.\r
+;\r
+;  To spill or not to spill?\r
+;\r
+;  By omitting the "nospill" optional the proc macro will spill the first four arguments to the stack upon entry.\r
+;  This creates the most reliable way to access input parameters at the small cost of extra object code.\r
+;  By using the "nospill" option the first four arguments are aliased to the registers r0-r3 directly.\r
+;  "nospill" mode is best suited for leaf and "register light" procedures where using the stack is unneccesary.\r
+;  Accessing the first four parameters is different between the two cases:\r
+;\r
+;  eg1. proc foo nospill, bar1, bar2, bar3, bar4, bar5\r
+;         mov r3,bar2   ;mov r3,r1 - from here on bar4 (r3) has been lost!\r
+;         mov r0,bar2   ;mov r0,r1 - from here on bar1 (r0) has been lost!\r
+;         mov r5,bar1   ;ERROR: bar1 (r0) was destroyed above\r
+;         lea r4,[bar3] ;invalid: bar3 (r2) is not in memory\r
+;         ldr r4,[bar3] ;invalid: bar3 (r2) is not in memory\r
+;         ldr r4,[bar5] ;okay: ldr r0,[fp]\r
+;       endp\r
+;\r
+;  compare to this:\r
+;\r
+;  eg2. proc foo, bar1, bar2, bar3, bar4, bar5\r
+;         mov r3,bar2   ;add r3,fp,4\r
+;         lea r3,[bar2] ;add r3,fp,4\r
+;         ldr r0,[bar2] ;ldr r0,[fp,4]\r
+;         ldr r5,[bar1] ;ldr r5,[fp]\r
+;         lea r4,[bar3] ;add r4,fp,8\r
+;         ldr r4,[bar5] ;ldr r4,[fp,10h]\r
+;       endp\r
+;\r
+;  and also compare to this:\r
+;\r
+;  eg3. proc foo uses[r4-r6, lr], bar1, bar2, bar3, bar4, bar5\r
+;         mov r3,bar2   ;add r3,fp,4\r
+;         ldr r0,[bar2] ;ldr r0,[fp,4]\r
+;         ldr r5,[bar1] ;ldr r5,[fp]\r
+;         lea r4,[bar3] ;add r4,fp,8\r
+;         ldr r4,[bar5] ;ldr r4,[fp,20h] ;note the different offset from above\r
+;       endp\r
+;\r
+;\r
+;  The stack frame:\r
+;\r
+;  eg4. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6",\r
+;       then: "proc MyFunc uses [fp, r4, lr], arg1, ..." creates a stack frame that looks like this:\r
+;\r
+;  arg6             - pushed by calling procedure       higher addresses up here\r
+;  arg5             - pushed by calling procedure  <---------------^------------- FP points here\r
+;  saved reg lr     - pushed by proc                               |\r
+;  saved reg fp     - pushed by proc                               |\r
+;  saved reg r4     - pushed by proc                               |\r
+;  arg4 (reg r3)    - pushed by proc                               |\r
+;  arg3 (reg r2)    - pushed by proc                               |\r
+;  arg2 (reg r1)    - pushed by proc                               v\r
+;  arg1 (reg r0)    - pushed by proc                    lower addresses down here\r
+;  locals data      - uninitialised data <-- SP points here\r
+;\r
+;  NOTE: the order of register saving is always highest (r15) to lowest (r0) regardless of the\r
+;        order they are specified in the "uses" statement.\r
+;\r
+;\r
+;  eg5. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6",\r
+;       then: "proc MyFunc base r4 uses [r4, lr] nospill, arg1, ..." creates a stack frame that looks like this:\r
+;\r
+;  arg6             - pushed by calling procedure       higher addresses up here\r
+;  arg5             - pushed by calling procedure  <---------------^------------- R4 points here\r
+;  saved reg lr     - pushed by proc                               v\r
+;  saved reg r4     - pushed by proc                    lower addresses down here\r
+;  locals data      - uninitialised data <-- SP points here\r
+;\r
+;  NOTE: The first four arguments are still in registers r0-r3 and have not been spilled to the stack\r
+;\r
+;\r
+;  eg6. Assume the calling procedure does this: "apscall MyFunc, arg1, arg2, arg3, arg4, arg5, arg6",\r
+;       then: "proc MyFunc base sp uses [lr] nospill, arg1, ..." creates a stack frame that looks like this:\r
+;\r
+;  arg6             - pushed by calling procedure       higher addresses up here\r
+;  arg5             - pushed by calling procedure                  |\r
+;  saved reg lr     - pushed by proc                    lower addresses down here\r
+;  locals data      - uninitialised data <-- SP points here\r
+;\r
+;  NOTE: Using sp based addressing requires special attention. The "apscall" macro has been\r
+;        designed to properly issue parameters when using sp based variables but your code must\r
+;        always restore sp before executing "apscall" or "ret".\r
+;\r
+;\r
+;LOCALS/ENDL:\r
+;\r
+;  Usage: locals | endl\r
+;\r
+;  Valid inside a proc/endp pair only. Declares uninitialised locally addressable variables.\r
+;  You can use any number of locals/endl pairs, they are all concatenated together on the stack at runtime.\r
+;\r
+;  eg7. proc foo\r
+;         locals\r
+;           varw dw ?\r
+;           varh dh ?\r
+;           varb db 100 dup (?)\r
+;         endl\r
+;           mov  r1,'x'\r
+;           strb r1,[varb+2]\r
+;           lea  r2,[varw]\r
+;           ...\r
+;       endp\r
+;\r
+;\r
+;LOCAL:\r
+;\r
+;  Usage: local name definition | local name:type | local name[count]:type\r
+;\r
+;  Valid inside a proc/endp pair only. Declares uninitialised locally addressable variables.\r
+;  You can use any number of local definitions, they are all concatenated together on the stack at runtime.\r
+;\r
+;  name       - the symbolic name of the variable\r
+;  count      - must be numeric\r
+;  type       - one of BYTE, HWORD, WORD, DWORD or a structure name\r
+;  definition - the variable's definition statement\r
+;\r
+;  eg8. local MyVar1 db ?\r
+;       local MyVar2 rb 8\r
+;       local MyVar3:HWORD\r
+;       local MyVar4[0x100]:BYTE\r
+;\r
+;\r
+;RET:\r
+;\r
+;  Usage: ret(cond)\r
+;\r
+;  Valid inside a proc/endp pair only. Restores the state and returns to the calling procedure.\r
+;\r
+;  The worst case generated code by ret is three instructions for non-sp based procedures, and four\r
+;  instructions plus one literal for sp based precedures.\r
+;\r
+;\r
+;ENDP:\r
+;\r
+;  Usage: endp\r
+;\r
+;  Ends the current "proc", freeing all local scope equates.\r
+;\r
+;\r
+;POP/PUSH:\r
+;\r
+;  Usage: push  reg, reg-reg, reg, ...   |   pop  reg, reg-reg, reg, ...\r
+;\r
+;  At least one reg required in the list. Convience macros for optimal full descending stack operations.\r
+;\r
+;\r
+;LEA:\r
+;\r
+;  Usage: lea(cond) reg, [address]\r
+;\r
+;  Convienience macro to access locations that are PC or local frame based.\r
+;  The macro automatically determines whether the address is a local variable or external variable\r
+;  and generates the appropriate code.\r
+;\r
+;\r
+;  General note: You may notice that some instructions below use uppercase, this is to integrate with the\r
+;                literals macros in ARMLIRTL.INC.\r
+;\r
+;By default this file is included from "WINCE.INC".\r
+\r
+macro def_ustring labl,[string] {common labl dU string}\r
+macro def_astring labl,[string] {common labl dB string}\r
+\r
+macro apscall function,[parameter] {\r
+    common\r
+       local pcount,tempcount,found,.skip,.size,param,last_value,temp,size,instr,i_s,msize\r
+       virtual\r
+               nop\r
+               temp=$-$$\r
+       end virtual\r
+       if temp<>4\r
+               halt ;APSCALL macro NOT usable in thumb mode\r
+       end if\r
+       if ~ parameter eq\r
+               if .size\r
+                   b .skip\r
+               end if\r
+               temp=$\r
+               tempcount=0\r
+    reverse\r
+               local ..arg\r
+               found equ no\r
+               match i[like]za,:parameter: \{ found equ \}\r
+               match =no:*ustring,found:parameter \{\r
+                   def_ustring ..arg,ustring,0\r
+                   found equ \}\r
+               match =no:some=,more,found:parameter \{\r
+                   def_astring ..arg,parameter,0\r
+                   found equ \}\r
+               match =no,found \{\r
+                 if parameter eqtype ''\r
+                   def_astring ..arg,parameter,0\r
+                 end if \}\r
+               tempcount=tempcount+1\r
+    common\r
+               pcount=tempcount\r
+               align 4\r
+               .size=$-temp\r
+               if .size\r
+                   .skip:\r
+               end if\r
+               lastvalue=1 shl 63\r
+               tempcount=0\r
+    reverse\r
+               if tempcount<(pcount-4)\r
+                   found equ no\r
+                   define param parameter\r
+                   match [address],parameter \{\r
+                       LDR lr,[address]\r
+                       lastvalue=1 shl 63\r
+                       str lr,[sp,-tempcount*4-4]\r
+                       found equ yes \}\r
+                   irp i_s,b:byte:byte,sb:sbyte:byte,h:hword:hword,sh:shword:hword,:word:word \{\r
+                    match instr:msize:size,LDR\#i_s \\{\r
+                     match =msize[address],parameter \\\{\r
+                       instr lr,size[address]\r
+                       lastvalue=1 shl 63\r
+                       str lr,[sp,-tempcount*4-4]\r
+                       found equ yes \\\}\\}\}\r
+                   match =addr address,param \{\r
+                       lea lr,[address]\r
+                       lastvalue=1 shl 63\r
+                       str lr,[sp,-tempcount*4-4]\r
+                       found equ yes \}\r
+                   match value =no,parameter found \{\r
+                       if defined ..arg\r
+                           lastvalue=1 shl 63\r
+                           ADD lr,pc,..arg-$-8\r
+                           str lr,[sp,-tempcount*4-4]\r
+                       else if value eqtype r0\r
+                           str value,[sp,-tempcount*4-4]\r
+                       else if value eqtype 0\r
+                           virtual\r
+                               dw value\r
+                               load temp word from $-4\r
+                           end virtual\r
+                           if temp <> lastvalue\r
+                               MOV lr,value\r
+                           end if\r
+                           lastvalue=temp\r
+                           str lr,[sp,-tempcount*4-4]\r
+                       else\r
+                           MOV lr,value\r
+                           lastvalue=1 shl 63\r
+                           str lr,[sp,-tempcount*4-4]\r
+                       end if \}\r
+               end if\r
+           rept 4 p:0 \{\reverse\r
+               if tempcount=pcount-p-1\r
+                   found equ no\r
+                   match [address],parameter \\{\r
+                       LDR r\#p,[address]\r
+                       found equ yes \\}\r
+                   irp i_s,b:byte:byte,sb:sbyte:byte,h:hword:hword,sh:shword:hword,:word:word \\{\r
+                    match instr:msize:size,LDR\\#i_s \\\{\r
+                     match =msize[address],parameter \\\\{\r
+                       instr r\#p,size[address]\r
+                       found equ yes \\\\}\\\}\\}\r
+                   match =addr address,param \\{\r
+                       lea r\#p,[address]\r
+                       found equ yes \\}\r
+                   match value =no,parameter found \\{\r
+                       if ~ defined ..arg & value eqtype 0\r
+                           virtual\r
+                               dw value\r
+                               load temp word from $-4\r
+                           end virtual\r
+                       end if\r
+                       if defined ..arg\r
+                           ADD r\#p,pc,..arg-$-8\r
+                       else if value eqtype 0 & lastvalue = temp\r
+                           MOV r\#p,lr\r
+                       else if ~ r\#p eq value\r
+                           MOV r\#p,value\r
+                       end if \\}\r
+               end if\r
+           \}\r
+               tempcount=tempcount+1\r
+    common\r
+       else\r
+               pcount=0\r
+       end if\r
+       if pcount>4\r
+               sub sp,sp,(pcount-4)*4\r
+       end if\r
+       if defined _#function & _#function-$-8<4096 & _#function-$-8>-4096\r
+               mov lr,pc\r
+               ldr pc,[pc,_#function-$-8]\r
+       else\r
+               bl function\r
+       end if\r
+       if pcount>4\r
+               add sp,sp,(pcount-4)*4\r
+       end if\r
+}\r
+\r
+macro popcount val,result {\r
+       local r\r
+       r=0\r
+       repeat 16\r
+               r=r+(((val)shr(%-1))and 1)\r
+       end repeat\r
+       result=r\r
+}\r
+\r
+macro push [list] {\r
+    common\r
+       local bits,popc\r
+       virtual\r
+               stmdb sp!,{list\}\r
+               load bits hword from $-4\r
+       end virtual\r
+       popcount bits,popc\r
+       if popc=1\r
+               str list,[sp,-4]!\r
+       else\r
+               stmdb sp!,{list\}\r
+       end if\r
+}\r
+\r
+macro pop [list] {\r
+    common\r
+       local bits,popc\r
+       virtual\r
+               ldmia sp!,{list\}\r
+               load bits hword from $-4\r
+       end virtual\r
+       popcount bits,popc\r
+       if popc=1\r
+               ldr list,[sp],+4\r
+       else\r
+               ldmia sp!,{list\}\r
+       end if\r
+}\r
+\r
+irp cond,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo {\r
+  macro push#cond [list] \{\r
+    \common\r
+       \local bits,popc\r
+       virtual\r
+               stm#cond#db sp!,\\{list\\}\r
+               load bits hword from $-4\r
+       end virtual\r
+       popcount bits,popc\r
+       if popc=1\r
+               str#cond list,[sp,-4]!\r
+       else\r
+               stm#cond#db sp!,\\{list\\}\r
+       end if\r
+  \}\r
+  macro pop#cond [list] \{\r
+    \common\r
+       \local bits,popc\r
+       virtual\r
+               ldm#cond#ia sp!,\\{list\\}\r
+               load bits hword from $-4\r
+       end virtual\r
+       popcount bits,popc\r
+       if popc=1\r
+               ldr#cond list,[sp],+4\r
+       else\r
+               ldm#cond#ia sp!,\\{list\\}\r
+       end if\r
+  \}\r
+}\r
+\r
+macro proc [parameter] {\r
+    common\r
+       local use,pname,parg,stack_count,bits,curr_off,locals_size,regbase,locals_names,spill,spill_size,param_count\r
+       match n remaining,parameter: \{pname equ n\}\r
+    if used pname\r
+       use equ\r
+       parg equ\r
+       locals_names equ\r
+       regbase equ fp\r
+       spill equ all\r
+       match junk =uses[u] remaining,parameter: \{use equ u\}\r
+       match junk =base b remaining,parameter: \{regbase equ b\}\r
+       match junk =nospill remaining,parameter: \{spill equ no\}\r
+       match :junk=,remaining,use:parameter \{parg equ remaining\}\r
+       match u:junk]=,remaining,use:parameter \{parg equ remaining\}\r
+       match :u:junk]foo=,remaining,parg:use:parameter \{parg equ remaining\}\r
+       match ,parg \{spill equ no\}\r
+       match =all:p1=,p2=,p3=,more,spill:parg\{spill equ ,r0,r1,r2,r3\}\r
+       match =all:p1=,p2=,p3,spill:parg\{spill equ ,r0,r1,r2\}\r
+       match =all:p1=,p2,spill:parg\{spill equ ,r0,r1\}\r
+       match =all:p1,spill:parg\{spill equ ,r0\}\r
+       match =no:p1=,p2=,p3=,p4=,more,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2,p4 r3\\{match a r,arg\\\{a equ r\\\}\\}spill equ\}\r
+       match =no:p1=,p2=,p3=,p4,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2,p4 r3\\{match a r,arg\\\{a equ r\\\}\\}spill equ\}\r
+       match =no:p1=,p2=,p3,spill:parg\{irp arg,p1 r0,p2 r1,p3 r2\\{match a r,arg\\\{a equ r\\\}\\}spill equ\}\r
+       match =no:p1=,p2,spill:parg\{irp arg,p1 r0,p2 r1\\{match a r,arg\\\{a equ r\\\}\\}spill equ\}\r
+       match =no:p1,spill:parg\{p1 equ r0\}\r
+       match =no,spill\{spill equ\}\r
+       match =,any,spill \{\r
+           virtual at 0\r
+               ldmia sp!,{any\\}\r
+               load bits hword from $-4\r
+               popcount bits,spill_count\r
+           end virtual\r
+       \}\r
+       match ,spill\{spill_count=0\}\r
+       match any,use \{\r
+           virtual at 0\r
+               ldmia sp!,{any\\}\r
+               load bits hword from $-4\r
+               popcount bits,stack_count\r
+           end virtual\r
+       \}\r
+       match ,use\{stack_count=0\}\r
+       curr_off=0\r
+       match =,junk:args,spill:parg \{\r
+           irp arg,args \\{\r
+               \\local ..arg\r
+               arg equ ..arg\r
+               if curr_off<4\r
+                   if regbase eq sp\r
+                       virtual at regbase+curr_off*4+locals_size\r
+                   else if param_count >= 4\r
+                       virtual at regbase-(4-curr_off+stack_count)*4\r
+                   else\r
+                       virtual at regbase-(param_count-curr_off+stack_count)*4\r
+                   end if\r
+                           ..arg dw ?\r
+                       end virtual\r
+               else\r
+                   if regbase eq sp\r
+                       virtual at regbase+stack_count*4+curr_off*4+locals_size\r
+                   else\r
+                       virtual at regbase+(curr_off-4)*4\r
+                   end if\r
+                           ..arg dw ?\r
+                       end virtual\r
+               end if\r
+               curr_off=curr_off+1\r
+           \\}\r
+           param_count=curr_off\r
+       \}\r
+       match :p1=,p2=,p3=,p4=,others,spill:parg \{\r
+         param_count=5\r
+         if regbase eq sp\r
+           virtual at regbase+(stack_count+spill_count)*4+locals_size\r
+         else\r
+           virtual at regbase\r
+         end if\r
+           irp arg,others \\{\r
+               \\local ..arg\r
+               arg equ ..arg\r
+               ..arg dw ?\r
+           \\}\r
+           end virtual\r
+       \}\r
+       align 4\r
+       use32\r
+    pname:\r
+       match :=,regs,use:spill\{push regs\}\r
+       match junk,use\{push use spill\}\r
+       if (~ regbase eq sp) & ((locals_size+spill_count) | (defined param_count & param_count>4))\r
+           add regbase,sp,(stack_count+spill_count)*4\r
+       end if\r
+       if (locals_size)\r
+           SUB sp,sp,locals_size\r
+       end if\r
+    irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{\r
+     match rt:sb1:AD2:ld:ldia:xb,ret\#cond:sub\#cond:ADD\#cond:ldr\#cond:ldm\#cond\#ia:bx\#cond\\{\r
+      macro rt \\\{\r
+       if (~ regbase eq sp) & ((locals_size+spill_count) | (defined param_count & param_count>4))\r
+           sb1 sp,regbase,stack_count*4\r
+       end if\r
+       if (regbase eq sp) & locals_size+spill_count\r
+           AD2 sp,sp,locals_size+spill_count*4\r
+       end if\r
+       if stack_count>1\r
+               ldia sp!,{use\\\\}\r
+               store hword ((bits and 0x3fff)+((bits and 0x4000)shl 1)) at $-4\r
+               if ~ bits and 0x4000\r
+                       xb lr\r
+               end if\r
+       else if stack_count=1\r
+               if use eq lr\r
+                       ld pc,[sp],+4\r
+               else\r
+                       ld use,[sp],+4\r
+                       xb lr\r
+               end if\r
+       else\r
+               xb lr\r
+       end if\r
+      \\\}\r
+     \\}\r
+    \}\r
+    curr_off=0\r
+    local in_locals\r
+    in_locals=0\r
+    macro locals \{\r
+       if in_locals\r
+           halt - locals is not allowed to be recursive\r
+       end if\r
+       if regbase eq sp\r
+           virtual at regbase+curr_off\r
+       else\r
+           virtual at regbase-locals_size+curr_off-((stack_count+spill_count)*4)\r
+       end if\r
+       in_locals=1\r
+    \}\r
+    local ..s,size,reserve,op,def,copy\r
+    macro \local [arg] \{\r
+      \common\r
+       locals\r
+      \forward\r
+       found equ no\r
+       define copy arg\r
+       match name[count]:type,copy \\{\r
+           irp op,BYTE rb,HWORD rh,WORD rw,DWORD rd \\\{\r
+            match size reserve,op \\\\{\r
+             match =size,type \\\\\{\r
+               name reserve count\r
+               found equ \\\\\}\\\\}\\\}\r
+           match =no,found \\\{\r
+               virtual\r
+                   name type\r
+                   ..s=$-$$\r
+               end virtual\r
+               rb count*..s\r
+               found equ \\\}\r
+       \\}\r
+       match =no:name:type,found:copy \\{\r
+           irp op,BYTE db,HWORD dh,WORD dw,DWORD dd \\\{\r
+            match size def,op \\\\{\r
+             match =size,type \\\\\{\r
+               name def ?\r
+               found equ \\\\\}\\\\}\\\}\r
+           match =no,found \\\{\r
+               name type\r
+               found equ \\\}\r
+       \\}\r
+       match =no,found \\{ arg \\}\r
+      \common\r
+       endl\r
+    \}\r
+    macro endl \{\r
+       in_locals=0\r
+       curr_off=curr_off+$-$$\r
+       end virtual\r
+    \}\r
+    macro close_proc \{\r
+       locals_size=(curr_off+3)and not 3\r
+       match a,parg \\{ restore a \\}\r
+       match =,a,locals_names \\{ restore a \\}\r
+       restruc db,dh,du,dw,dd,rb,rh,rw,rd\r
+    \}\r
+    irp op,db 1,dh 2,du 2,dw 4,dd 4,rb 1,rh 2,rw 4,rd 4 \{\r
+       \local already\r
+       match str bytes,op \\{\r
+           struc str [v]\\\{\r
+               \\\common\r
+               \\\local ..arg\r
+               already equ no\r
+               match foo =. bar,:locals_names:\\\\{already equ\\\\}\r
+               match =no,already\\\\{\r
+                       locals_names equ locals_names,.\r
+                       . equ ..arg\r
+               \\\\}\r
+               times ($$-$-curr_off)and(bytes-1) db ?\r
+               . str v\r
+           \\\}\r
+       \\}\r
+    \}\r
+    irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo \{\r
+     \local ad\r
+     match inst,lea\#cond\\{\r
+      macro inst dest,var \\\{\r
+       found equ no\r
+       define copy var\r
+       match [v=+off],copy \\\\{\r
+           match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{\r
+               ad dest,regbase,v-regbase+off\r
+               found equ\r
+           \\\\\}\r
+       \\\\}\r
+       match [v=-off],copy \\\\{\r
+           match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{\r
+               ad dest,regbase,v-regbase-off\r
+               found equ\r
+           \\\\\}\r
+       \\\\}\r
+       match [v=,off],copy \\\\{\r
+           match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{\r
+               ad dest,regbase,v-regbase+off\r
+               found equ\r
+           \\\\\}\r
+       \\\\}\r
+       match [v]:=no,copy:found \\\\{\r
+           match ad:some=,=v=,more , ADD\#cond::,parg locals_names,: \\\\\{\r
+               ad dest,regbase,v-regbase\r
+               found equ\r
+           \\\\\}\r
+       \\\\}\r
+       match ad:[v]:=no,ADD\#cond:copy:found \\\\{\r
+           ad dest,pc,v-$-8\r
+           found equ\r
+       \\\\}\r
+       match =no,found\\\\{\r
+           halt ;malformed expression, use: lea reg,[address]\r
+       \\\\}\r
+      \\\}\r
+     \\}\r
+    \}\r
+}\r
+\r
+macro endp {\r
+    close_proc\r
+    purge locals,endl,close_proc,local\r
+    irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo\{\r
+       purge lea\#cond\r
+       purge ret\#cond\r
+    \}\r
+    end if\r
+}\r
+\r
+irp cond,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,al,hs,lo {\r
+ local found,inst,ad,d,v\r
+ match inst,lea#cond\{\r
+  macro inst dest,var \\{\r
+    found equ no\r
+    match ad:d:[v],ADD#cond:dest:var \\\{\r
+       ad d,pc,v-$-8\r
+       found equ\r
+    \\\}\r
+    match =no,found \\\{\r
+       halt ;malformed expression, use: lea reg,[address]\r
+    \\\}\r
+  \\}\r
+ \}\r
+}\r
+\r

diff --git a/include/wince.inc b/include/wince.inc
new file mode 100644 (file)
index 0000000..58dad25
--- /dev/null
+++ b/include/wince.inc
@@ -0,0 +1,8 @@
+\r
+;WinCE programming headers\r
+;By default this file is included from "WINCEX.INC".\r
+\r
+include 'macro\procaps.inc'\r
+include 'macro\importce.inc'\r
+include        'macro\armresrc.inc'\r
+include        'macro\armstruc.inc'\r

diff --git a/include/wincex.inc b/include/wincex.inc
new file mode 100644 (file)
index 0000000..b34afe3
--- /dev/null
+++ b/include/wincex.inc
@@ -0,0 +1,22 @@
+\r
+;Extended WinCE programming headers\r
+\r
+       format  PE GUI\r
+\r
+       include 'wince.inc'\r
+       include 'macro\armlitrl.inc'\r
+\r
+macro .code {section '.text' code readable executable}\r
+macro .data {section '.data' data readable writeable}\r
+\r
+macro .end begin {\r
+       entry begin\r
+       section '.idata' import readable writeable\r
+       library coredll,'COREDLL.DLL'\r
+       include 'apice\coredll.inc'\r
+}\r
+\r
+macro endp {\r
+       literals\r
+       endp\r
+}\r

diff --git a/source/armtable.inc b/source/armtable.inc
new file mode 100644 (file)
index 0000000..b22ac3e
--- /dev/null
+++ b/source/armtable.inc
@@ -0,0 +1,11321 @@
+; ARMv8 assembler core module v1.44 for flat assembler,\r
+; Copyright (c) 2005-2023, Revolution.\r
+; All rights reserved.\r
+;\r
+; Some portions are Copyright (c) 1999-2016, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+macro dw [value] {\r
+       forward\r
+       assert value >= 0\r
+       dw value\r
+}\r
+\r
+include_variable db 'INCLUDE',0\r
+\r
+symbol_characters db 27\r
+ db 9,0Ah,0Dh,1Ah,20h,'+-/*=<>()[]{}:,|&~#`;\'\r
+\r
+preprocessor_directives:\r
+ db 6,'define'\r
+ dw define_symbolic_constant-directive_handler\r
+ db 7,'include'\r
+ dw include_file-directive_handler\r
+ db 3,'irp'\r
+ dw irp_directive-directive_handler\r
+ db 4,'irps'\r
+ dw irps_directive-directive_handler\r
+ db 4,'irpv'\r
+ dw irpv_directive-directive_handler\r
+ db 5,'macro'\r
+ dw define_macro-directive_handler\r
+ db 5,'match'\r
+ dw match_directive-directive_handler\r
+ db 8,'postpone'\r
+ dw postpone_directive-directive_handler\r
+ db 5,'purge'\r
+ dw purge_macro-directive_handler\r
+ db 4,'rept'\r
+ dw rept_directive-directive_handler\r
+ db 7,'restore'\r
+ dw restore_equ_constant-directive_handler\r
+ db 7,'restruc'\r
+ dw purge_struc-directive_handler\r
+ db 5,'struc'\r
+ dw define_struc-directive_handler\r
+ db 0\r
+\r
+macro_directives:\r
+ db 6,'common'\r
+ dw common_block-directive_handler\r
+ db 7,'forward'\r
+ dw forward_block-directive_handler\r
+ db 5,'local'\r
+ dw local_symbols-directive_handler\r
+ db 7,'reverse'\r
+ dw reverse_block-directive_handler\r
+ db 0\r
+\r
+preprocessor_special_symbols:\r
+ db 4,'file'\r
+ dw preprocessed_file_value-directive_handler\r
+ db 4,'line'\r
+ dw preprocessed_line_value-directive_handler\r
+ db 0\r
+\r
+operators:\r
+ db 1,'+',80h\r
+ db 1,'-',81h\r
+ db 1,'*',90h\r
+ db 1,'/',91h\r
+ db 3,'and',0B0h\r
+ db 3,'mod',0A0h\r
+ db 2,'or',0B1h\r
+ db 3,'shl',0C0h\r
+ db 3,'shr',0C1h\r
+ db 3,'xor',0B2h\r
+ db 0\r
+\r
+single_operand_operators:\r
+ db 1,'+',082h\r
+ db 1,'-',083h\r
+ db 3,'bsf',0E0h\r
+ db 3,'bsr',0E1h\r
+ db 3,'fit',0D1h               ;ARM operator fit\r
+ db 3,'not',0D0h\r
+ db 3,'plt',0F1h\r
+ db 3,'rva',0F0h\r
+ db 0\r
+\r
+directive_operators:\r
+ db 5,'align',8Ch\r
+ db 2,'as',86h\r
+ db 2,'at',80h\r
+ db 11,'coprocessor',08Eh      ;ARM coprocessor instructions selected\r
+ db 7,'defined',88h\r
+ db 8,'definite',8Ah\r
+ db 3,'dup',81h\r
+ db 2,'eq',0F0h\r
+ db 6,'eqtype',0F7h\r
+ db 4,'from',82h\r
+ db 2,'in',0F6h\r
+ db 2,'on',84h\r
+ db 9,'processor',08Fh         ;ARM processor instructions selected\r
+ db 3,'ptr',85h\r
+ db 10,'relativeto',0F8h\r
+ db 4,'used',89h\r
+ db 0\r
+\r
+address_sizes:\r
+       db      0\r
+\r
+symbols:\r
+       dw      symbols_1-symbols,(symbols_2-symbols_1)/(1+2)\r
+       dw      symbols_2-symbols,(symbols_3-symbols_2)/(2+2)\r
+       dw      symbols_3-symbols,(symbols_4-symbols_3)/(3+2)\r
+       dw      symbols_4-symbols,(symbols_5-symbols_4)/(4+2)\r
+       dw      symbols_5-symbols,(symbols_6-symbols_5)/(5+2)\r
+       dw      symbols_6-symbols,(symbols_7-symbols_6)/(6+2)\r
+       dw      symbols_7-symbols,(symbols_8-symbols_7)/(7+2)\r
+       dw      symbols_8-symbols,(symbols_9-symbols_8)/(8+2)\r
+       dw      symbols_9-symbols,(symbols_10-symbols_9)/(9+2)\r
+       dw      symbols_10-symbols,(symbols_11-symbols_10)/(10+2)\r
+       dw      symbols_11-symbols,(symbols_12-symbols_11)/(11+2)\r
+       dw      symbols_12-symbols,(symbols_13-symbols_12)/(12+2)\r
+       dw      symbols_13-symbols,(symbols_14-symbols_13)/(13+2)\r
+       dw      symbols_14-symbols,(symbols_15-symbols_14)/(14+2)\r
+       dw      symbols_15-symbols,(symbols_16-symbols_15)/(15+2)\r
+       dw      symbols_16-symbols,(symbols_17-symbols_16)/(16+2)\r
+       dw      symbols_17-symbols,(symbols_end-symbols_17)/(17+2)\r
+\r
+base_@16       = 0x1010\r
+base_@16.size  = 0x10                          ;r0@16-r15@16\r
+\r
+base_@32       = base_@16+base_@16.size\r
+base_@32.size  = 0x10                          ;r0@32-r15@32\r
+\r
+base_@64       = base_@32+base_@32.size\r
+base_@64.size  = 0x10                          ;r0@64-r15@64\r
+\r
+base_@128      = base_@64+base_@64.size\r
+base_@128.size = 0x10                          ;r0@128-r15@128\r
+\r
+base_@256      = base_@128+base_@128.size\r
+base_@256.size = 0x10                          ;r0@256-r15@256\r
+\r
+base_reg       = base_@256+base_@256.size\r
+base_reg.size  = 0x10                          ;r0-r15\r
+\r
+dword_reg      = base_reg+base_reg.size\r
+dword_reg.size = 0x20                          ;x0-x30,xzr\r
+\r
+size_opr       = 0x1100\r
+size_opr.size  = 33                            ;byte,hword,word,dword,qword,dqword\r
+\r
+sys_at         = 0x1200\r
+sys_at.size    = 12                            ;0-11\r
+\r
+sys_dc         = sys_at+sys_at.size\r
+sys_dc.size    = 8                             ;0-7\r
+\r
+sys_ic         = sys_dc+sys_dc.size\r
+sys_ic.size    = 3                             ;0-2\r
+\r
+sys_tlbi       = sys_ic+sys_ic.size\r
+sys_tlbi.size  = 32                            ;0-31\r
+\r
+sys_msr                = sys_tlbi+sys_tlbi.size\r
+sys_msr.size   = 384                           ;0-383\r
+\r
+sys_pstate     = sys_msr+sys_msr.size\r
+sys_pstate.size        = 2                             ;daifclr, daifset\r
+\r
+base_reg!      = sys_pstate+sys_pstate.size\r
+base_reg!.size = 0x10                          ;r0!-r15!\r
+\r
+vect_breg      = base_reg!+base_reg!.size\r
+vect_breg.size = 0x20                          ;b0-b31\r
+\r
+vect_hreg      = vect_breg+vect_breg.size\r
+vect_hreg.size = 0x20                          ;h0-h31\r
+\r
+vect_sreg      = vect_hreg+vect_hreg.size\r
+vect_sreg.size = 0x20                          ;s0-s31\r
+\r
+vfps_reg       = vect_sreg\r
+vfps_reg.size  = 0x20                          ;s0-s31\r
+\r
+vect_dreg      = vect_sreg+vect_sreg.size\r
+vect_dreg.size = 0x20                          ;d0-d31\r
+\r
+vfpd_reg       = vect_dreg\r
+vfpd_reg.size  = 0x20                          ;d0-d31\r
+\r
+vect_qreg      = vect_dreg+vect_dreg.size\r
+vect_qreg.size = 0x20                          ;q0-q31\r
+\r
+simd_qreg      = vect_qreg\r
+simd_qreg.size = 0x10                          ;q0-q15\r
+\r
+word_reg       = vect_qreg+vect_qreg.size\r
+word_reg.size  = 0x21                          ;w0-w30,wzr,wsp\r
+\r
+banked_reg     = word_reg+word_reg.size\r
+banked_reg.size        = 0x3f                          ;0-62\r
+\r
+vect_v8b       = banked_reg+banked_reg.size\r
+vect_v8b.size  = 0x20                          ;v0.8b-v31.8b\r
+\r
+vect_v16b      = vect_v8b+vect_v8b.size\r
+vect_v16b.size = 0x20                          ;v0.16b-v31.16b\r
+\r
+vect_v4h       = vect_v16b+vect_v16b.size\r
+vect_v4h.size  = 0x20                          ;v0.4h-v31.4h\r
+\r
+vect_v8h       = vect_v4h+vect_v4h.size\r
+vect_v8h.size  = 0x20                          ;v0.8h-v31.8h\r
+\r
+vect_v2s       = vect_v8h+vect_v8h.size\r
+vect_v2s.size  = 0x20                          ;v0.2s-v31.2s\r
+\r
+vect_v4s       = vect_v2s+vect_v2s.size\r
+vect_v4s.size  = 0x20                          ;v0.4s-v31.4s\r
+\r
+vect_v2d       = vect_v4s+vect_v4s.size\r
+vect_v2d.size  = 0x20                          ;v0.2d-v31.2d\r
+\r
+vect_v1d       = vect_v2d+vect_v2d.size\r
+vect_v1d.size  = 0x20                          ;v0.1d-v31.1d\r
+\r
+vect_v1q       = vect_v1d+vect_v1d.size\r
+vect_v1q.size  = 0x20                          ;v0.1q-v31.1q\r
+\r
+vect_vb                = vect_v1q+vect_v1q.size\r
+vect_vb.size   = 0x20                          ;v0.b-v31.b\r
+\r
+vect_vh                = vect_vb+vect_vb.size\r
+vect_vh.size   = 0x20                          ;v0.h-v31.h\r
+\r
+vect_vs                = vect_vh+vect_vh.size\r
+vect_vs.size   = 0x20                          ;v0.s-v31.s\r
+\r
+vect_vd                = vect_vs+vect_vs.size\r
+vect_vd.size   = 0x20                          ;v0.d-v31.d\r
+\r
+cpro_sel       = vect_vd+vect_vd.size\r
+cpro_sel.size  = 0x10                          ;p0-p15\r
+\r
+cpro_reg       = cpro_sel+cpro_sel.size\r
+cpro_reg.size  = 0x10                          ;c0-c15\r
+\r
+shift_op       = cpro_reg+cpro_reg.size\r
+shift_op.size  = 4                             ;asr, lsl, lsr, ror\r
+\r
+rrx_op         = shift_op+shift_op.size\r
+rrx_op.size    = 1                             ;rrx\r
+\r
+msl_op         = rrx_op+rrx_op.size\r
+msl_op.size    = 1                             ;msl\r
+\r
+endian         = msl_op+msl_op.size\r
+endian.size    = 2                             ;be, le\r
+\r
+modifier       = endian+endian.size\r
+modifier.size  = 2                             ;!, ^\r
+\r
+psr_reg                = modifier+modifier.size\r
+psr_reg.size   = 16+16+3                       ;cpse, spsr\r
+\r
+iflags         = psr_reg+psr_reg.size\r
+iflags.size    = 8                             ;a, i, f\r
+\r
+vfp_syst       = iflags+iflags.size\r
+vfp_syst.size  = 11                            ;\r
+\r
+acc_40bt       = vfp_syst+vfp_syst.size\r
+acc_40bt.size  = 8                             ;acc0-acc7\r
+\r
+iwmmx_wreg     = acc_40bt+acc_40bt.size\r
+iwmmx_wreg.size        = 0x10                          ;wr0-wr15\r
+\r
+iwmmx_creg     = iwmmx_wreg+iwmmx_wreg.size\r
+iwmmx_creg.size        = 12                            ;\r
+\r
+mvrk_areg      = iwmmx_creg+iwmmx_creg.size\r
+mvrk_areg.size = 1                             ;a0\r
+\r
+mvrk_psc       = mvrk_areg+mvrk_areg.size\r
+mvrk_psc.size  = 1                             ;dspsc\r
+\r
+fpa_freg       = mvrk_psc+mvrk_psc.size\r
+fpa_freg.size  = 8                             ;f0-f7\r
+\r
+barrier                = fpa_freg+fpa_freg.size\r
+barrier.size   = 0x10                          ;\r
+\r
+condition      = barrier+barrier.size\r
+condition.size = 16                            ;\r
+\r
+sysm_reg       = condition+condition.size\r
+sysm_reg.size  = 21                            ;\r
+\r
+xtnd_op                = sysm_reg+sysm_reg.size\r
+xtnd_op.size   = 8                             ;\r
+\r
+prf_op         = xtnd_op+xtnd_op.size\r
+prf_op.size    = 2*8+2*2+1 + 1                 ;\r
+\r
+assert prf_op+prf_op.size <= 0x1800\r
+\r
+               ; 0x18  mz, pe, elf, coff, pe64, elf64, binary\r
+               ; 0x19  code, data, dwarf, linkinfo, readable, writable, shareable, writeable, executable, linkremove, discardable, notpageable\r
+               ; 0x1a  export, fixups, import, resource\r
+               ; 0x1b  nx, dll, efi, gui, wdm, large, native, console, efiboot, efiruntime\r
+               ; 0x1c  ms, ms64\r
+               ; 0x1d  static\r
+               ; 0x1e  note, dynamic, interpreter\r
+               ; 0x1f  cpu_sel, copro_sel\r
+\r
+cpu_sel.all32  = 0x1f00\r
+cpu_sel.all64  = 0x1f01\r
+copro_sel.all  = 0x1f02\r
+\r
+cpu_sel                = 0x1f03\r
+cpu_sel.size   = 37\r
+\r
+copro_sel      = cpu_sel+cpu_sel.size\r
+copro_sel.size = 19\r
+\r
+macro symbol_maker symbol,value {db symbol,(value) shr 8,(value) and 0xff}\r
+\r
+symbols_1:\r
+       symbol_maker    '!',modifier+0\r
+       symbol_maker    '^',modifier+1\r
+symbols_2:\r
+       symbol_maker    'a0',mvrk_areg\r
+       symbol_maker    'a1',base_reg+0\r
+       symbol_maker    'a2',base_reg+1\r
+       symbol_maker    'a3',base_reg+2\r
+       symbol_maker    'a4',base_reg+3\r
+       symbol_maker    'al',condition+0xe\r
+       symbol_maker    'b0',vect_breg+0\r
+       symbol_maker    'b1',vect_breg+1\r
+       symbol_maker    'b2',vect_breg+2\r
+       symbol_maker    'b3',vect_breg+3\r
+       symbol_maker    'b4',vect_breg+4\r
+       symbol_maker    'b5',vect_breg+5\r
+       symbol_maker    'b6',vect_breg+6\r
+       symbol_maker    'b7',vect_breg+7\r
+       symbol_maker    'b8',vect_breg+8\r
+       symbol_maker    'b9',vect_breg+9\r
+       symbol_maker    'be',endian+1\r
+       symbol_maker    'c0',cpro_reg+0\r
+       symbol_maker    'c1',cpro_reg+1\r
+       symbol_maker    'c2',cpro_reg+2\r
+       symbol_maker    'c3',cpro_reg+3\r
+       symbol_maker    'c4',cpro_reg+4\r
+       symbol_maker    'c5',cpro_reg+5\r
+       symbol_maker    'c6',cpro_reg+6\r
+       symbol_maker    'c7',cpro_reg+7\r
+       symbol_maker    'c8',cpro_reg+8\r
+       symbol_maker    'c9',cpro_reg+9\r
+       symbol_maker    'cc',condition+0x3\r
+       symbol_maker    'cs',condition+0x2\r
+       symbol_maker    'd0',vect_dreg+0\r
+       symbol_maker    'd1',vect_dreg+1\r
+       symbol_maker    'd2',vect_dreg+2\r
+       symbol_maker    'd3',vect_dreg+3\r
+       symbol_maker    'd4',vect_dreg+4\r
+       symbol_maker    'd5',vect_dreg+5\r
+       symbol_maker    'd6',vect_dreg+6\r
+       symbol_maker    'd7',vect_dreg+7\r
+       symbol_maker    'd8',vect_dreg+8\r
+       symbol_maker    'd9',vect_dreg+9\r
+;;     symbol_maker    'eq',condition+0x0\r
+       symbol_maker    'f0',fpa_freg+0\r
+       symbol_maker    'f1',fpa_freg+1\r
+       symbol_maker    'f2',fpa_freg+2\r
+       symbol_maker    'f3',fpa_freg+3\r
+       symbol_maker    'f4',fpa_freg+4\r
+       symbol_maker    'f5',fpa_freg+5\r
+       symbol_maker    'f6',fpa_freg+6\r
+       symbol_maker    'f7',fpa_freg+7\r
+       symbol_maker    'fp',base_reg+11\r
+       symbol_maker    'ge',condition+0xa\r
+       symbol_maker    'gt',condition+0xc\r
+       symbol_maker    'h0',vect_hreg+0\r
+       symbol_maker    'h1',vect_hreg+1\r
+       symbol_maker    'h2',vect_hreg+2\r
+       symbol_maker    'h3',vect_hreg+3\r
+       symbol_maker    'h4',vect_hreg+4\r
+       symbol_maker    'h5',vect_hreg+5\r
+       symbol_maker    'h6',vect_hreg+6\r
+       symbol_maker    'h7',vect_hreg+7\r
+       symbol_maker    'h8',vect_hreg+8\r
+       symbol_maker    'h9',vect_hreg+9\r
+       symbol_maker    'hi',condition+0x8\r
+       symbol_maker    'hs',condition+0x2\r
+       symbol_maker    'ip',base_reg+12\r
+       symbol_maker    'ld',barrier+1101b\r
+       symbol_maker    'le',endian+0\r
+;;     symbol_maker    'le',condition+0xd\r
+       symbol_maker    'lo',condition+0x3\r
+       symbol_maker    'lr',base_reg+14\r
+       symbol_maker    'ls',condition+0x9\r
+       symbol_maker    'lt',condition+0xb\r
+       symbol_maker    'mi',condition+0x4\r
+       symbol_maker    'ms',1Ch shl 8 + 41h\r
+       symbol_maker    'mz',18h shl 8 + 20h\r
+       symbol_maker    'ne',condition+0x1\r
+       symbol_maker    'nv',condition+0xf\r
+       symbol_maker    'nx',1Bh shl 8 + 83h\r
+       symbol_maker    'p0',cpro_sel+0\r
+       symbol_maker    'p1',cpro_sel+1\r
+       symbol_maker    'p2',cpro_sel+2\r
+       symbol_maker    'p3',cpro_sel+3\r
+       symbol_maker    'p4',cpro_sel+4\r
+       symbol_maker    'p5',cpro_sel+5\r
+       symbol_maker    'p6',cpro_sel+6\r
+       symbol_maker    'p7',cpro_sel+7\r
+       symbol_maker    'p8',cpro_sel+8\r
+       symbol_maker    'p9',cpro_sel+9\r
+       symbol_maker    'pc',base_reg+15\r
+       symbol_maker    'pe',18h shl 8 + 30h\r
+       symbol_maker    'pl',condition+0x5\r
+       symbol_maker    'q0',vect_qreg+0\r
+       symbol_maker    'q1',vect_qreg+1\r
+       symbol_maker    'q2',vect_qreg+2\r
+       symbol_maker    'q3',vect_qreg+3\r
+       symbol_maker    'q4',vect_qreg+4\r
+       symbol_maker    'q5',vect_qreg+5\r
+       symbol_maker    'q6',vect_qreg+6\r
+       symbol_maker    'q7',vect_qreg+7\r
+       symbol_maker    'q8',vect_qreg+8\r
+       symbol_maker    'q9',vect_qreg+9\r
+       symbol_maker    'r0',base_reg+0\r
+       symbol_maker    'r1',base_reg+1\r
+       symbol_maker    'r2',base_reg+2\r
+       symbol_maker    'r3',base_reg+3\r
+       symbol_maker    'r4',base_reg+4\r
+       symbol_maker    'r5',base_reg+5\r
+       symbol_maker    'r6',base_reg+6\r
+       symbol_maker    'r7',base_reg+7\r
+       symbol_maker    'r8',base_reg+8\r
+       symbol_maker    'r9',base_reg+9\r
+       symbol_maker    's0',vect_sreg+0\r
+       symbol_maker    's1',vect_sreg+1\r
+       symbol_maker    's2',vect_sreg+2\r
+       symbol_maker    's3',vect_sreg+3\r
+       symbol_maker    's4',vect_sreg+4\r
+       symbol_maker    's5',vect_sreg+5\r
+       symbol_maker    's6',vect_sreg+6\r
+       symbol_maker    's7',vect_sreg+7\r
+       symbol_maker    's8',vect_sreg+8\r
+       symbol_maker    's9',vect_sreg+9\r
+       symbol_maker    'sb',base_reg+9\r
+       symbol_maker    'sl',base_reg+10\r
+       symbol_maker    'sp',base_reg+13\r
+       symbol_maker    'st',barrier+1110b\r
+       symbol_maker    'sy',barrier+1111b\r
+       symbol_maker    'v1',base_reg+4\r
+       symbol_maker    'v2',base_reg+5\r
+       symbol_maker    'v3',base_reg+6\r
+       symbol_maker    'v4',base_reg+7\r
+       symbol_maker    'v5',base_reg+8\r
+       symbol_maker    'v6',base_reg+9\r
+       symbol_maker    'v7',base_reg+10\r
+       symbol_maker    'v8',base_reg+11\r
+       symbol_maker    'vc',condition+0x7\r
+       symbol_maker    'vs',condition+0x6\r
+       symbol_maker    'w0',word_reg+0\r
+       symbol_maker    'w1',word_reg+1\r
+       symbol_maker    'w2',word_reg+2\r
+       symbol_maker    'w3',word_reg+3\r
+       symbol_maker    'w4',word_reg+4\r
+       symbol_maker    'w5',word_reg+5\r
+       symbol_maker    'w6',word_reg+6\r
+       symbol_maker    'w7',word_reg+7\r
+       symbol_maker    'w8',word_reg+8\r
+       symbol_maker    'w9',word_reg+9\r
+       symbol_maker    'x0',dword_reg+0\r
+       symbol_maker    'x1',dword_reg+1\r
+       symbol_maker    'x2',dword_reg+2\r
+       symbol_maker    'x3',dword_reg+3\r
+       symbol_maker    'x4',dword_reg+4\r
+       symbol_maker    'x5',dword_reg+5\r
+       symbol_maker    'x6',dword_reg+6\r
+       symbol_maker    'x7',dword_reg+7\r
+       symbol_maker    'x8',dword_reg+8\r
+       symbol_maker    'x9',dword_reg+9\r
+symbols_3:\r
+       symbol_maker    'a1!',base_reg!+0\r
+       symbol_maker    'a2!',base_reg!+1\r
+       symbol_maker    'a3!',base_reg!+2\r
+       symbol_maker    'a4!',base_reg!+3\r
+       symbol_maker    'asr',shift_op+2\r
+       symbol_maker    'b10',vect_breg+10\r
+       symbol_maker    'b11',vect_breg+11\r
+       symbol_maker    'b12',vect_breg+12\r
+       symbol_maker    'b13',vect_breg+13\r
+       symbol_maker    'b14',vect_breg+14\r
+       symbol_maker    'b15',vect_breg+15\r
+       symbol_maker    'b16',vect_breg+16\r
+       symbol_maker    'b17',vect_breg+17\r
+       symbol_maker    'b18',vect_breg+18\r
+       symbol_maker    'b19',vect_breg+19\r
+       symbol_maker    'b20',vect_breg+20\r
+       symbol_maker    'b21',vect_breg+21\r
+       symbol_maker    'b22',vect_breg+22\r
+       symbol_maker    'b23',vect_breg+23\r
+       symbol_maker    'b24',vect_breg+24\r
+       symbol_maker    'b25',vect_breg+25\r
+       symbol_maker    'b26',vect_breg+26\r
+       symbol_maker    'b27',vect_breg+27\r
+       symbol_maker    'b28',vect_breg+28\r
+       symbol_maker    'b29',vect_breg+29\r
+       symbol_maker    'b30',vect_breg+30\r
+       symbol_maker    'b31',vect_breg+31\r
+       symbol_maker    'c10',cpro_reg+10\r
+       symbol_maker    'c11',cpro_reg+11\r
+       symbol_maker    'c12',cpro_reg+12\r
+       symbol_maker    'c13',cpro_reg+13\r
+       symbol_maker    'c14',cpro_reg+14\r
+       symbol_maker    'c15',cpro_reg+15\r
+       symbol_maker    'csw',sys_dc+(sys_encode_csw-sys_encode_table_dc) shr 1\r
+       symbol_maker    'd10',vect_dreg+10\r
+       symbol_maker    'd11',vect_dreg+11\r
+       symbol_maker    'd12',vect_dreg+12\r
+       symbol_maker    'd13',vect_dreg+13\r
+       symbol_maker    'd14',vect_dreg+14\r
+       symbol_maker    'd15',vect_dreg+15\r
+       symbol_maker    'd16',vect_dreg+16\r
+       symbol_maker    'd17',vect_dreg+17\r
+       symbol_maker    'd18',vect_dreg+18\r
+       symbol_maker    'd19',vect_dreg+19\r
+       symbol_maker    'd20',vect_dreg+20\r
+       symbol_maker    'd21',vect_dreg+21\r
+       symbol_maker    'd22',vect_dreg+22\r
+       symbol_maker    'd23',vect_dreg+23\r
+       symbol_maker    'd24',vect_dreg+24\r
+       symbol_maker    'd25',vect_dreg+25\r
+       symbol_maker    'd26',vect_dreg+26\r
+       symbol_maker    'd27',vect_dreg+27\r
+       symbol_maker    'd28',vect_dreg+28\r
+       symbol_maker    'd29',vect_dreg+29\r
+       symbol_maker    'd30',vect_dreg+30\r
+       symbol_maker    'd31',vect_dreg+31\r
+       symbol_maker    'dll',1Bh shl 8 + 80h\r
+       symbol_maker    'efi',1Bh shl 10\r
+       symbol_maker    'elf',18h shl 8 + 50h\r
+       symbol_maker    'fp!',base_reg!+11\r
+       symbol_maker    'gui',1Bh shl 8 + 2\r
+       symbol_maker    'h10',vect_hreg+10\r
+       symbol_maker    'h11',vect_hreg+11\r
+       symbol_maker    'h12',vect_hreg+12\r
+       symbol_maker    'h13',vect_hreg+13\r
+       symbol_maker    'h14',vect_hreg+14\r
+       symbol_maker    'h15',vect_hreg+15\r
+       symbol_maker    'h16',vect_hreg+16\r
+       symbol_maker    'h17',vect_hreg+17\r
+       symbol_maker    'h18',vect_hreg+18\r
+       symbol_maker    'h19',vect_hreg+19\r
+       symbol_maker    'h20',vect_hreg+20\r
+       symbol_maker    'h21',vect_hreg+21\r
+       symbol_maker    'h22',vect_hreg+22\r
+       symbol_maker    'h23',vect_hreg+23\r
+       symbol_maker    'h24',vect_hreg+24\r
+       symbol_maker    'h25',vect_hreg+25\r
+       symbol_maker    'h26',vect_hreg+26\r
+       symbol_maker    'h27',vect_hreg+27\r
+       symbol_maker    'h28',vect_hreg+28\r
+       symbol_maker    'h29',vect_hreg+29\r
+       symbol_maker    'h30',vect_hreg+30\r
+       symbol_maker    'h31',vect_hreg+31\r
+       symbol_maker    'ip!',base_reg!+12\r
+       symbol_maker    'ish',barrier+1011b\r
+       symbol_maker    'isw',sys_dc+(sys_encode_isw-sys_encode_table_dc) shr 1\r
+       symbol_maker    'lr!',base_reg!+14\r
+       symbol_maker    'lsl',shift_op+0\r
+       symbol_maker    'lsr',shift_op+1\r
+       symbol_maker    'msl',msl_op+0\r
+       symbol_maker    'msp',sysm_reg+8\r
+       symbol_maker    'nsh',barrier+0111b\r
+       symbol_maker    'osh',barrier+0011b\r
+       symbol_maker    'p10',cpro_sel+10\r
+       symbol_maker    'p11',cpro_sel+11\r
+       symbol_maker    'p12',cpro_sel+12\r
+       symbol_maker    'p13',cpro_sel+13\r
+       symbol_maker    'p14',cpro_sel+14\r
+       symbol_maker    'p15',cpro_sel+15\r
+       symbol_maker    'pc!',base_reg!+15\r
+       symbol_maker    'psp',sysm_reg+9\r
+       symbol_maker    'q10',vect_qreg+10\r
+       symbol_maker    'q11',vect_qreg+11\r
+       symbol_maker    'q12',vect_qreg+12\r
+       symbol_maker    'q13',vect_qreg+13\r
+       symbol_maker    'q14',vect_qreg+14\r
+       symbol_maker    'q15',vect_qreg+15\r
+       symbol_maker    'q16',vect_qreg+16\r
+       symbol_maker    'q17',vect_qreg+17\r
+       symbol_maker    'q18',vect_qreg+18\r
+       symbol_maker    'q19',vect_qreg+19\r
+       symbol_maker    'q20',vect_qreg+20\r
+       symbol_maker    'q21',vect_qreg+21\r
+       symbol_maker    'q22',vect_qreg+22\r
+       symbol_maker    'q23',vect_qreg+23\r
+       symbol_maker    'q24',vect_qreg+24\r
+       symbol_maker    'q25',vect_qreg+25\r
+       symbol_maker    'q26',vect_qreg+26\r
+       symbol_maker    'q27',vect_qreg+27\r
+       symbol_maker    'q28',vect_qreg+28\r
+       symbol_maker    'q29',vect_qreg+29\r
+       symbol_maker    'q30',vect_qreg+30\r
+       symbol_maker    'q31',vect_qreg+31\r
+       symbol_maker    'r0!',base_reg!+0\r
+       symbol_maker    'r1!',base_reg!+1\r
+       symbol_maker    'r10',base_reg+10\r
+       symbol_maker    'r11',base_reg+11\r
+       symbol_maker    'r12',base_reg+12\r
+       symbol_maker    'r13',base_reg+13\r
+       symbol_maker    'r14',base_reg+14\r
+       symbol_maker    'r15',base_reg+15\r
+       symbol_maker    'r2!',base_reg!+2\r
+       symbol_maker    'r3!',base_reg!+3\r
+       symbol_maker    'r4!',base_reg!+4\r
+       symbol_maker    'r5!',base_reg!+5\r
+       symbol_maker    'r6!',base_reg!+6\r
+       symbol_maker    'r7!',base_reg!+7\r
+       symbol_maker    'r8!',base_reg!+8\r
+       symbol_maker    'r9!',base_reg!+9\r
+       symbol_maker    'ror',shift_op+3\r
+       symbol_maker    'rrx',rrx_op+0\r
+       symbol_maker    's10',vect_sreg+10\r
+       symbol_maker    's11',vect_sreg+11\r
+       symbol_maker    's12',vect_sreg+12\r
+       symbol_maker    's13',vect_sreg+13\r
+       symbol_maker    's14',vect_sreg+14\r
+       symbol_maker    's15',vect_sreg+15\r
+       symbol_maker    's16',vect_sreg+16\r
+       symbol_maker    's17',vect_sreg+17\r
+       symbol_maker    's18',vect_sreg+18\r
+       symbol_maker    's19',vect_sreg+19\r
+       symbol_maker    's20',vect_sreg+20\r
+       symbol_maker    's21',vect_sreg+21\r
+       symbol_maker    's22',vect_sreg+22\r
+       symbol_maker    's23',vect_sreg+23\r
+       symbol_maker    's24',vect_sreg+24\r
+       symbol_maker    's25',vect_sreg+25\r
+       symbol_maker    's26',vect_sreg+26\r
+       symbol_maker    's27',vect_sreg+27\r
+       symbol_maker    's28',vect_sreg+28\r
+       symbol_maker    's29',vect_sreg+29\r
+       symbol_maker    's30',vect_sreg+30\r
+       symbol_maker    's31',vect_sreg+31\r
+       symbol_maker    'sb!',base_reg!+9\r
+       symbol_maker    'sl!',base_reg!+10\r
+       symbol_maker    'sp!',base_reg!+13\r
+       symbol_maker    'v1!',base_reg!+4\r
+       symbol_maker    'v2!',base_reg!+5\r
+       symbol_maker    'v3!',base_reg!+6\r
+       symbol_maker    'v4!',base_reg!+7\r
+       symbol_maker    'v5!',base_reg!+8\r
+       symbol_maker    'v6!',base_reg!+9\r
+       symbol_maker    'v7!',base_reg!+10\r
+       symbol_maker    'v8!',base_reg!+11\r
+       symbol_maker    'w10',word_reg+10\r
+       symbol_maker    'w11',word_reg+11\r
+       symbol_maker    'w12',word_reg+12\r
+       symbol_maker    'w13',word_reg+13\r
+       symbol_maker    'w14',word_reg+14\r
+       symbol_maker    'w15',word_reg+15\r
+       symbol_maker    'w16',word_reg+16\r
+       symbol_maker    'w17',word_reg+17\r
+       symbol_maker    'w18',word_reg+18\r
+       symbol_maker    'w19',word_reg+19\r
+       symbol_maker    'w20',word_reg+20\r
+       symbol_maker    'w21',word_reg+21\r
+       symbol_maker    'w22',word_reg+22\r
+       symbol_maker    'w23',word_reg+23\r
+       symbol_maker    'w24',word_reg+24\r
+       symbol_maker    'w25',word_reg+25\r
+       symbol_maker    'w26',word_reg+26\r
+       symbol_maker    'w27',word_reg+27\r
+       symbol_maker    'w28',word_reg+28\r
+       symbol_maker    'w29',word_reg+29\r
+       symbol_maker    'w30',word_reg+30\r
+       symbol_maker    'wdm',1Bh shl 8 + 81h\r
+       symbol_maker    'wr0',iwmmx_wreg+0\r
+       symbol_maker    'wr1',iwmmx_wreg+1\r
+       symbol_maker    'wr2',iwmmx_wreg+2\r
+       symbol_maker    'wr3',iwmmx_wreg+3\r
+       symbol_maker    'wr4',iwmmx_wreg+4\r
+       symbol_maker    'wr5',iwmmx_wreg+5\r
+       symbol_maker    'wr6',iwmmx_wreg+6\r
+       symbol_maker    'wr7',iwmmx_wreg+7\r
+       symbol_maker    'wr8',iwmmx_wreg+8\r
+       symbol_maker    'wr9',iwmmx_wreg+9\r
+       symbol_maker    'wsp',word_reg+32\r
+       symbol_maker    'wzr',word_reg+31\r
+       symbol_maker    'x10',dword_reg+10\r
+       symbol_maker    'x11',dword_reg+11\r
+       symbol_maker    'x12',dword_reg+12\r
+       symbol_maker    'x13',dword_reg+13\r
+       symbol_maker    'x14',dword_reg+14\r
+       symbol_maker    'x15',dword_reg+15\r
+       symbol_maker    'x16',dword_reg+16\r
+       symbol_maker    'x17',dword_reg+17\r
+       symbol_maker    'x18',dword_reg+18\r
+       symbol_maker    'x19',dword_reg+19\r
+       symbol_maker    'x20',dword_reg+20\r
+       symbol_maker    'x21',dword_reg+21\r
+       symbol_maker    'x22',dword_reg+22\r
+       symbol_maker    'x23',dword_reg+23\r
+       symbol_maker    'x24',dword_reg+24\r
+       symbol_maker    'x25',dword_reg+25\r
+       symbol_maker    'x26',dword_reg+26\r
+       symbol_maker    'x27',dword_reg+27\r
+       symbol_maker    'x28',dword_reg+28\r
+       symbol_maker    'x29',dword_reg+29\r
+       symbol_maker    'x30',dword_reg+30\r
+       symbol_maker    'xzr',dword_reg+31\r
+       symbol_maker    'zva',sys_dc+(sys_encode_zva-sys_encode_table_dc) shr 1\r
+symbols_4:\r
+       symbol_maker    'acc0',acc_40bt+0\r
+       symbol_maker    'acc1',acc_40bt+1\r
+       symbol_maker    'acc2',acc_40bt+2\r
+       symbol_maker    'acc3',acc_40bt+3\r
+       symbol_maker    'acc4',acc_40bt+4\r
+       symbol_maker    'acc5',acc_40bt+5\r
+       symbol_maker    'acc6',acc_40bt+6\r
+       symbol_maker    'acc7',acc_40bt+7\r
+       symbol_maker    'apsr',psr_reg+34\r
+       symbol_maker    'byte',size_opr+1\r
+       symbol_maker    'cisw',sys_dc+(sys_encode_cisw-sys_encode_table_dc) shr 1\r
+       symbol_maker    'code',19h shl 8 + 5\r
+       symbol_maker    'coff',18h shl 8 + 40h\r
+       symbol_maker    'cpsr',psr_reg+32\r
+       symbol_maker    'cvac',sys_dc+(sys_encode_cvac-sys_encode_table_dc) shr 1\r
+       symbol_maker    'cvau',sys_dc+(sys_encode_cvau-sys_encode_table_dc) shr 1\r
+       symbol_maker    'daif',sys_msr+(sys_encode_daif-sys_encode_table_msr) shr 1\r
+       symbol_maker    'data',19h shl 8 + 6\r
+       symbol_maker    'epsr',sysm_reg+6\r
+       symbol_maker    'fpcr',sys_msr+(sys_encode_fpcr-sys_encode_table_msr) shr 1\r
+       symbol_maker    'fpsr',sys_msr+(sys_encode_fpsr-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ipsr',sysm_reg+5\r
+       symbol_maker    'ivac',sys_dc+(sys_encode_ivac-sys_encode_table_dc) shr 1\r
+       symbol_maker    'ivau',sys_ic+(sys_encode_ivau-sys_encode_table_ic) shr 1\r
+       symbol_maker    'ms64',1Ch shl 8 + 49h\r
+       symbol_maker    'note',1Eh shl 8 + 4\r
+       symbol_maker    'nzcv',sys_msr+(sys_encode_nzcv-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pe64',18h shl 8 + 3ch\r
+       symbol_maker    'r10!',base_reg!+10\r
+       symbol_maker    'r11!',base_reg!+11\r
+       symbol_maker    'r12!',base_reg!+12\r
+       symbol_maker    'r13!',base_reg!+13\r
+       symbol_maker    'r14!',base_reg!+14\r
+       symbol_maker    'r15!',base_reg!+15\r
+       symbol_maker    'spsr',psr_reg+33\r
+       symbol_maker    'sxtb',xtnd_op+4\r
+       symbol_maker    'sxth',xtnd_op+5\r
+       symbol_maker    'sxtw',xtnd_op+6\r
+       symbol_maker    'sxtx',xtnd_op+7\r
+       symbol_maker    'syst',barrier+1110b\r
+       symbol_maker    'uxtb',xtnd_op+0\r
+       symbol_maker    'uxth',xtnd_op+1\r
+       symbol_maker    'uxtw',xtnd_op+2\r
+       symbol_maker    'uxtx',xtnd_op+3\r
+       symbol_maker    'v0.b',vect_vb+0\r
+       symbol_maker    'v0.d',vect_vd+0\r
+       symbol_maker    'v0.h',vect_vh+0\r
+       symbol_maker    'v0.s',vect_vs+0\r
+       symbol_maker    'v1.b',vect_vb+1\r
+       symbol_maker    'v1.d',vect_vd+1\r
+       symbol_maker    'v1.h',vect_vh+1\r
+       symbol_maker    'v1.s',vect_vs+1\r
+       symbol_maker    'v2.b',vect_vb+2\r
+       symbol_maker    'v2.d',vect_vd+2\r
+       symbol_maker    'v2.h',vect_vh+2\r
+       symbol_maker    'v2.s',vect_vs+2\r
+       symbol_maker    'v3.b',vect_vb+3\r
+       symbol_maker    'v3.d',vect_vd+3\r
+       symbol_maker    'v3.h',vect_vh+3\r
+       symbol_maker    'v3.s',vect_vs+3\r
+       symbol_maker    'v4.b',vect_vb+4\r
+       symbol_maker    'v4.d',vect_vd+4\r
+       symbol_maker    'v4.h',vect_vh+4\r
+       symbol_maker    'v4.s',vect_vs+4\r
+       symbol_maker    'v5.b',vect_vb+5\r
+       symbol_maker    'v5.d',vect_vd+5\r
+       symbol_maker    'v5.h',vect_vh+5\r
+       symbol_maker    'v5.s',vect_vs+5\r
+       symbol_maker    'v6.b',vect_vb+6\r
+       symbol_maker    'v6.d',vect_vd+6\r
+       symbol_maker    'v6.h',vect_vh+6\r
+       symbol_maker    'v6.s',vect_vs+6\r
+       symbol_maker    'v7.b',vect_vb+7\r
+       symbol_maker    'v7.d',vect_vd+7\r
+       symbol_maker    'v7.h',vect_vh+7\r
+       symbol_maker    'v7.s',vect_vs+7\r
+       symbol_maker    'v8.b',vect_vb+8\r
+       symbol_maker    'v8.d',vect_vd+8\r
+       symbol_maker    'v8.h',vect_vh+8\r
+       symbol_maker    'v8.s',vect_vs+8\r
+       symbol_maker    'v9.b',vect_vb+9\r
+       symbol_maker    'v9.d',vect_vd+9\r
+       symbol_maker    'v9.h',vect_vh+9\r
+       symbol_maker    'v9.s',vect_vs+9\r
+       symbol_maker    'vae1',sys_tlbi+(sys_encode_vae1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vae2',sys_tlbi+(sys_encode_vae2-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vae3',sys_tlbi+(sys_encode_vae3-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'wcid',iwmmx_creg+0\r
+       symbol_maker    'wcon',iwmmx_creg+1\r
+       symbol_maker    'word',size_opr+4\r
+       symbol_maker    'wr10',iwmmx_wreg+10\r
+       symbol_maker    'wr11',iwmmx_wreg+11\r
+       symbol_maker    'wr12',iwmmx_wreg+12\r
+       symbol_maker    'wr13',iwmmx_wreg+13\r
+       symbol_maker    'wr14',iwmmx_wreg+14\r
+       symbol_maker    'wr15',iwmmx_wreg+15\r
+       symbol_maker    'xpsr',sysm_reg+3\r
+symbols_5:\r
+       symbol_maker    'alle1',sys_tlbi+(sys_encode_alle1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'alle2',sys_tlbi+(sys_encode_alle2-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'alle3',sys_tlbi+(sys_encode_alle3-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'civac',sys_dc+(sys_encode_civac-sys_encode_table_dc) shr 1\r
+       symbol_maker    'dspsc',mvrk_psc+0\r
+       symbol_maker    'dwarf',19h shl 8 + 0C0h\r
+       symbol_maker    'dword',size_opr+8\r
+       symbol_maker    'eapsr',sysm_reg+2\r
+       symbol_maker    'elf64',18h shl 8 + 58h\r
+       symbol_maker    'fpexc',vfp_syst+8\r
+       symbol_maker    'fpscr',vfp_syst+1\r
+       symbol_maker    'fpsid',vfp_syst+0\r
+       symbol_maker    'hword',size_opr+2\r
+       symbol_maker    'iallu',sys_ic+(sys_encode_iallu-sys_encode_table_ic) shr 1\r
+       symbol_maker    'iapsr',sysm_reg+1\r
+       symbol_maker    'iepsr',sysm_reg+7\r
+       symbol_maker    'ishld',barrier+1001b\r
+       symbol_maker    'ishst',barrier+1010b\r
+       symbol_maker    'large',1Bh shl 8 + 82h\r
+       symbol_maker    'mvfr0',vfp_syst+7\r
+       symbol_maker    'mvfr1',vfp_syst+6\r
+       symbol_maker    'nshld',barrier+0101b\r
+       symbol_maker    'nshst',barrier+0110b\r
+       symbol_maker    'oshld',barrier+0001b\r
+       symbol_maker    'oshst',barrier+0010b\r
+       symbol_maker    'qword',size_opr+16\r
+       symbol_maker    'r0@16',base_@16+0\r
+       symbol_maker    'r0@32',base_@32+0\r
+       symbol_maker    'r0@64',base_@64+0\r
+       symbol_maker    'r1@16',base_@16+1\r
+       symbol_maker    'r1@32',base_@32+1\r
+       symbol_maker    'r1@64',base_@64+1\r
+       symbol_maker    'r2@16',base_@16+2\r
+       symbol_maker    'r2@32',base_@32+2\r
+       symbol_maker    'r2@64',base_@64+2\r
+       symbol_maker    'r3@16',base_@16+3\r
+       symbol_maker    'r3@32',base_@32+3\r
+       symbol_maker    'r3@64',base_@64+3\r
+       symbol_maker    'r4@16',base_@16+4\r
+       symbol_maker    'r4@32',base_@32+4\r
+       symbol_maker    'r4@64',base_@64+4\r
+       symbol_maker    'r5@16',base_@16+5\r
+       symbol_maker    'r5@32',base_@32+5\r
+       symbol_maker    'r5@64',base_@64+5\r
+       symbol_maker    'r6@16',base_@16+6\r
+       symbol_maker    'r6@32',base_@32+6\r
+       symbol_maker    'r6@64',base_@64+6\r
+       symbol_maker    'r7@16',base_@16+7\r
+       symbol_maker    'r7@32',base_@32+7\r
+       symbol_maker    'r7@64',base_@64+7\r
+       symbol_maker    'r8@16',base_@16+8\r
+       symbol_maker    'r8@32',base_@32+8\r
+       symbol_maker    'r8@64',base_@64+8\r
+       symbol_maker    'r9@16',base_@16+9\r
+       symbol_maker    'r9@32',base_@32+9\r
+       symbol_maker    'r9@64',base_@64+9\r
+       symbol_maker    's1e0r',sys_at+(sys_encode_s1e0r-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e0w',sys_at+(sys_encode_s1e0w-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e1r',sys_at+(sys_encode_s1e1r-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e1w',sys_at+(sys_encode_s1e1w-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e2r',sys_at+(sys_encode_s1e2r-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e2w',sys_at+(sys_encode_s1e2w-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e3r',sys_at+(sys_encode_s1e3r-sys_encode_table_at) shr 1\r
+       symbol_maker    's1e3w',sys_at+(sys_encode_s1e3w-sys_encode_table_at) shr 1\r
+       symbol_maker    'spsel',sys_msr+(sys_encode_spsel-sys_encode_table_msr) shr 1\r
+;;     symbol_maker    'spsel',sys_pstate+(sys_pencode_spsel-sys_encode_table_pstate) shr 1\r
+       symbol_maker    'v0.1d',vect_v1d+0\r
+       symbol_maker    'v0.1q',vect_v1q+0\r
+       symbol_maker    'v0.2d',vect_v2d+0\r
+       symbol_maker    'v0.2s',vect_v2s+0\r
+       symbol_maker    'v0.4h',vect_v4h+0\r
+       symbol_maker    'v0.4s',vect_v4s+0\r
+       symbol_maker    'v0.8b',vect_v8b+0\r
+       symbol_maker    'v0.8h',vect_v8h+0\r
+       symbol_maker    'v1.1d',vect_v1d+1\r
+       symbol_maker    'v1.1q',vect_v1q+1\r
+       symbol_maker    'v1.2d',vect_v2d+1\r
+       symbol_maker    'v1.2s',vect_v2s+1\r
+       symbol_maker    'v1.4h',vect_v4h+1\r
+       symbol_maker    'v1.4s',vect_v4s+1\r
+       symbol_maker    'v1.8b',vect_v8b+1\r
+       symbol_maker    'v1.8h',vect_v8h+1\r
+       symbol_maker    'v10.b',vect_vb+10\r
+       symbol_maker    'v10.d',vect_vd+10\r
+       symbol_maker    'v10.h',vect_vh+10\r
+       symbol_maker    'v10.s',vect_vs+10\r
+       symbol_maker    'v11.b',vect_vb+11\r
+       symbol_maker    'v11.d',vect_vd+11\r
+       symbol_maker    'v11.h',vect_vh+11\r
+       symbol_maker    'v11.s',vect_vs+11\r
+       symbol_maker    'v12.b',vect_vb+12\r
+       symbol_maker    'v12.d',vect_vd+12\r
+       symbol_maker    'v12.h',vect_vh+12\r
+       symbol_maker    'v12.s',vect_vs+12\r
+       symbol_maker    'v13.b',vect_vb+13\r
+       symbol_maker    'v13.d',vect_vd+13\r
+       symbol_maker    'v13.h',vect_vh+13\r
+       symbol_maker    'v13.s',vect_vs+13\r
+       symbol_maker    'v14.b',vect_vb+14\r
+       symbol_maker    'v14.d',vect_vd+14\r
+       symbol_maker    'v14.h',vect_vh+14\r
+       symbol_maker    'v14.s',vect_vs+14\r
+       symbol_maker    'v15.b',vect_vb+15\r
+       symbol_maker    'v15.d',vect_vd+15\r
+       symbol_maker    'v15.h',vect_vh+15\r
+       symbol_maker    'v15.s',vect_vs+15\r
+       symbol_maker    'v16.b',vect_vb+16\r
+       symbol_maker    'v16.d',vect_vd+16\r
+       symbol_maker    'v16.h',vect_vh+16\r
+       symbol_maker    'v16.s',vect_vs+16\r
+       symbol_maker    'v17.b',vect_vb+17\r
+       symbol_maker    'v17.d',vect_vd+17\r
+       symbol_maker    'v17.h',vect_vh+17\r
+       symbol_maker    'v17.s',vect_vs+17\r
+       symbol_maker    'v18.b',vect_vb+18\r
+       symbol_maker    'v18.d',vect_vd+18\r
+       symbol_maker    'v18.h',vect_vh+18\r
+       symbol_maker    'v18.s',vect_vs+18\r
+       symbol_maker    'v19.b',vect_vb+19\r
+       symbol_maker    'v19.d',vect_vd+19\r
+       symbol_maker    'v19.h',vect_vh+19\r
+       symbol_maker    'v19.s',vect_vs+19\r
+       symbol_maker    'v2.1d',vect_v1d+2\r
+       symbol_maker    'v2.1q',vect_v1q+2\r
+       symbol_maker    'v2.2d',vect_v2d+2\r
+       symbol_maker    'v2.2s',vect_v2s+2\r
+       symbol_maker    'v2.4h',vect_v4h+2\r
+       symbol_maker    'v2.4s',vect_v4s+2\r
+       symbol_maker    'v2.8b',vect_v8b+2\r
+       symbol_maker    'v2.8h',vect_v8h+2\r
+       symbol_maker    'v20.b',vect_vb+20\r
+       symbol_maker    'v20.d',vect_vd+20\r
+       symbol_maker    'v20.h',vect_vh+20\r
+       symbol_maker    'v20.s',vect_vs+20\r
+       symbol_maker    'v21.b',vect_vb+21\r
+       symbol_maker    'v21.d',vect_vd+21\r
+       symbol_maker    'v21.h',vect_vh+21\r
+       symbol_maker    'v21.s',vect_vs+21\r
+       symbol_maker    'v22.b',vect_vb+22\r
+       symbol_maker    'v22.d',vect_vd+22\r
+       symbol_maker    'v22.h',vect_vh+22\r
+       symbol_maker    'v22.s',vect_vs+22\r
+       symbol_maker    'v23.b',vect_vb+23\r
+       symbol_maker    'v23.d',vect_vd+23\r
+       symbol_maker    'v23.h',vect_vh+23\r
+       symbol_maker    'v23.s',vect_vs+23\r
+       symbol_maker    'v24.b',vect_vb+24\r
+       symbol_maker    'v24.d',vect_vd+24\r
+       symbol_maker    'v24.h',vect_vh+24\r
+       symbol_maker    'v24.s',vect_vs+24\r
+       symbol_maker    'v25.b',vect_vb+25\r
+       symbol_maker    'v25.d',vect_vd+25\r
+       symbol_maker    'v25.h',vect_vh+25\r
+       symbol_maker    'v25.s',vect_vs+25\r
+       symbol_maker    'v26.b',vect_vb+26\r
+       symbol_maker    'v26.d',vect_vd+26\r
+       symbol_maker    'v26.h',vect_vh+26\r
+       symbol_maker    'v26.s',vect_vs+26\r
+       symbol_maker    'v27.b',vect_vb+27\r
+       symbol_maker    'v27.d',vect_vd+27\r
+       symbol_maker    'v27.h',vect_vh+27\r
+       symbol_maker    'v27.s',vect_vs+27\r
+       symbol_maker    'v28.b',vect_vb+28\r
+       symbol_maker    'v28.d',vect_vd+28\r
+       symbol_maker    'v28.h',vect_vh+28\r
+       symbol_maker    'v28.s',vect_vs+28\r
+       symbol_maker    'v29.b',vect_vb+29\r
+       symbol_maker    'v29.d',vect_vd+29\r
+       symbol_maker    'v29.h',vect_vh+29\r
+       symbol_maker    'v29.s',vect_vs+29\r
+       symbol_maker    'v3.1d',vect_v1d+3\r
+       symbol_maker    'v3.1q',vect_v1q+3\r
+       symbol_maker    'v3.2d',vect_v2d+3\r
+       symbol_maker    'v3.2s',vect_v2s+3\r
+       symbol_maker    'v3.4h',vect_v4h+3\r
+       symbol_maker    'v3.4s',vect_v4s+3\r
+       symbol_maker    'v3.8b',vect_v8b+3\r
+       symbol_maker    'v3.8h',vect_v8h+3\r
+       symbol_maker    'v30.b',vect_vb+30\r
+       symbol_maker    'v30.d',vect_vd+30\r
+       symbol_maker    'v30.h',vect_vh+30\r
+       symbol_maker    'v30.s',vect_vs+30\r
+       symbol_maker    'v31.b',vect_vb+31\r
+       symbol_maker    'v31.d',vect_vd+31\r
+       symbol_maker    'v31.h',vect_vh+31\r
+       symbol_maker    'v31.s',vect_vs+31\r
+       symbol_maker    'v4.1d',vect_v1d+4\r
+       symbol_maker    'v4.1q',vect_v1q+4\r
+       symbol_maker    'v4.2d',vect_v2d+4\r
+       symbol_maker    'v4.2s',vect_v2s+4\r
+       symbol_maker    'v4.4h',vect_v4h+4\r
+       symbol_maker    'v4.4s',vect_v4s+4\r
+       symbol_maker    'v4.8b',vect_v8b+4\r
+       symbol_maker    'v4.8h',vect_v8h+4\r
+       symbol_maker    'v5.1d',vect_v1d+5\r
+       symbol_maker    'v5.1q',vect_v1q+5\r
+       symbol_maker    'v5.2d',vect_v2d+5\r
+       symbol_maker    'v5.2s',vect_v2s+5\r
+       symbol_maker    'v5.4h',vect_v4h+5\r
+       symbol_maker    'v5.4s',vect_v4s+5\r
+       symbol_maker    'v5.8b',vect_v8b+5\r
+       symbol_maker    'v5.8h',vect_v8h+5\r
+       symbol_maker    'v6.1d',vect_v1d+6\r
+       symbol_maker    'v6.1q',vect_v1q+6\r
+       symbol_maker    'v6.2d',vect_v2d+6\r
+       symbol_maker    'v6.2s',vect_v2s+6\r
+       symbol_maker    'v6.4h',vect_v4h+6\r
+       symbol_maker    'v6.4s',vect_v4s+6\r
+       symbol_maker    'v6.8b',vect_v8b+6\r
+       symbol_maker    'v6.8h',vect_v8h+6\r
+       symbol_maker    'v7.1d',vect_v1d+7\r
+       symbol_maker    'v7.1q',vect_v1q+7\r
+       symbol_maker    'v7.2d',vect_v2d+7\r
+       symbol_maker    'v7.2s',vect_v2s+7\r
+       symbol_maker    'v7.4h',vect_v4h+7\r
+       symbol_maker    'v7.4s',vect_v4s+7\r
+       symbol_maker    'v7.8b',vect_v8b+7\r
+       symbol_maker    'v7.8h',vect_v8h+7\r
+       symbol_maker    'v8.1d',vect_v1d+8\r
+       symbol_maker    'v8.1q',vect_v1q+8\r
+       symbol_maker    'v8.2d',vect_v2d+8\r
+       symbol_maker    'v8.2s',vect_v2s+8\r
+       symbol_maker    'v8.4h',vect_v4h+8\r
+       symbol_maker    'v8.4s',vect_v4s+8\r
+       symbol_maker    'v8.8b',vect_v8b+8\r
+       symbol_maker    'v8.8h',vect_v8h+8\r
+       symbol_maker    'v9.1d',vect_v1d+9\r
+       symbol_maker    'v9.1q',vect_v1q+9\r
+       symbol_maker    'v9.2d',vect_v2d+9\r
+       symbol_maker    'v9.2s',vect_v2s+9\r
+       symbol_maker    'v9.4h',vect_v4h+9\r
+       symbol_maker    'v9.4s',vect_v4s+9\r
+       symbol_maker    'v9.8b',vect_v8b+9\r
+       symbol_maker    'v9.8h',vect_v8h+9\r
+       symbol_maker    'vaae1',sys_tlbi+(sys_encode_vaae1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale1',sys_tlbi+(sys_encode_vale1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale2',sys_tlbi+(sys_encode_vale2-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale3',sys_tlbi+(sys_encode_vale3-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'wcasf',iwmmx_creg+3\r
+       symbol_maker    'wcgr0',iwmmx_creg+8\r
+       symbol_maker    'wcgr1',iwmmx_creg+9\r
+       symbol_maker    'wcgr2',iwmmx_creg+10\r
+       symbol_maker    'wcgr3',iwmmx_creg+11\r
+       symbol_maker    'wcssf',iwmmx_creg+2\r
+symbols_6:\r
+       symbol_maker    'apsr_g',psr_reg+4\r
+       symbol_maker    'aside1',sys_tlbi+(sys_encode_aside1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'binary',18h shl 8 + 10h\r
+       symbol_maker    'cpsr_c',psr_reg+1\r
+       symbol_maker    'cpsr_f',psr_reg+8\r
+       symbol_maker    'cpsr_s',psr_reg+4\r
+       symbol_maker    'cpsr_x',psr_reg+2\r
+       symbol_maker    'dqword',size_opr+32\r
+       symbol_maker    'export',1Ah shl 8 + 0\r
+       symbol_maker    'fixups',1Ah shl 8 + 5\r
+       symbol_maker    'fpinst',vfp_syst+9\r
+       symbol_maker    'import',1Ah shl 8 + 1\r
+       symbol_maker    'lr_abt',banked_reg+20\r
+       symbol_maker    'lr_fiq',banked_reg+14\r
+       symbol_maker    'lr_irq',banked_reg+16\r
+       symbol_maker    'lr_mon',banked_reg+28\r
+       symbol_maker    'lr_svc',banked_reg+18\r
+       symbol_maker    'lr_und',banked_reg+22\r
+       symbol_maker    'lr_usr',banked_reg+6\r
+       symbol_maker    'native',1Bh shl 8 + 1\r
+       symbol_maker    'r0@128',base_@128+0\r
+       symbol_maker    'r0@256',base_@256+0\r
+       symbol_maker    'r10@16',base_@16+10\r
+       symbol_maker    'r10@32',base_@32+10\r
+       symbol_maker    'r10@64',base_@64+10\r
+       symbol_maker    'r11@16',base_@16+11\r
+       symbol_maker    'r11@32',base_@32+11\r
+       symbol_maker    'r11@64',base_@64+11\r
+       symbol_maker    'r12@16',base_@16+12\r
+       symbol_maker    'r12@32',base_@32+12\r
+       symbol_maker    'r12@64',base_@64+12\r
+       symbol_maker    'r13@16',base_@16+13\r
+       symbol_maker    'r13@32',base_@32+13\r
+       symbol_maker    'r13@64',base_@64+13\r
+       symbol_maker    'r14@16',base_@16+14\r
+       symbol_maker    'r14@32',base_@32+14\r
+       symbol_maker    'r14@64',base_@64+14\r
+       symbol_maker    'r15@16',base_@16+15\r
+       symbol_maker    'r15@32',base_@32+15\r
+       symbol_maker    'r15@64',base_@64+15\r
+       symbol_maker    'r1@128',base_@128+1\r
+       symbol_maker    'r1@256',base_@256+1\r
+       symbol_maker    'r2@128',base_@128+2\r
+       symbol_maker    'r2@256',base_@256+2\r
+       symbol_maker    'r3@128',base_@128+3\r
+       symbol_maker    'r3@256',base_@256+3\r
+       symbol_maker    'r4@128',base_@128+4\r
+       symbol_maker    'r4@256',base_@256+4\r
+       symbol_maker    'r5@128',base_@128+5\r
+       symbol_maker    'r5@256',base_@256+5\r
+       symbol_maker    'r6@128',base_@128+6\r
+       symbol_maker    'r6@256',base_@256+6\r
+       symbol_maker    'r7@128',base_@128+7\r
+       symbol_maker    'r7@256',base_@256+7\r
+       symbol_maker    'r8@128',base_@128+8\r
+       symbol_maker    'r8@256',base_@256+8\r
+       symbol_maker    'r8_fiq',banked_reg+8\r
+       symbol_maker    'r8_usr',banked_reg+0\r
+       symbol_maker    'r9@128',base_@128+9\r
+       symbol_maker    'r9@256',base_@256+9\r
+       symbol_maker    'r9_fiq',banked_reg+9\r
+       symbol_maker    'r9_usr',banked_reg+1\r
+       symbol_maker    's12e0r',sys_at+(sys_encode_s12e0r-sys_encode_table_at) shr 1\r
+       symbol_maker    's12e0w',sys_at+(sys_encode_s12e0w-sys_encode_table_at) shr 1\r
+       symbol_maker    's12e1r',sys_at+(sys_encode_s12e1r-sys_encode_table_at) shr 1\r
+       symbol_maker    's12e1w',sys_at+(sys_encode_s12e1w-sys_encode_table_at) shr 1\r
+       symbol_maker    'sp_abt',banked_reg+21\r
+       symbol_maker    'sp_el0',sys_msr+(sys_encode_sp_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sp_el1',sys_msr+(sys_encode_sp_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sp_el2',sys_msr+(sys_encode_sp_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sp_fiq',banked_reg+13\r
+       symbol_maker    'sp_hyp',banked_reg+31\r
+       symbol_maker    'sp_irq',banked_reg+17\r
+       symbol_maker    'sp_mon',banked_reg+29\r
+       symbol_maker    'sp_svc',banked_reg+19\r
+       symbol_maker    'sp_und',banked_reg+23\r
+       symbol_maker    'sp_usr',banked_reg+5\r
+       symbol_maker    'spsr_c',psr_reg+1\r
+       symbol_maker    'spsr_f',psr_reg+8\r
+       symbol_maker    'spsr_s',psr_reg+4\r
+       symbol_maker    'spsr_x',psr_reg+2\r
+       symbol_maker    'static',1Dh shl 8 + 1\r
+       symbol_maker    'v0.16b',vect_v16b+0\r
+       symbol_maker    'v1.16b',vect_v16b+1\r
+       symbol_maker    'v10.1d',vect_v1d+10\r
+       symbol_maker    'v10.1q',vect_v1q+20\r
+       symbol_maker    'v10.2d',vect_v2d+10\r
+       symbol_maker    'v10.2s',vect_v2s+10\r
+       symbol_maker    'v10.4h',vect_v4h+10\r
+       symbol_maker    'v10.4s',vect_v4s+10\r
+       symbol_maker    'v10.8b',vect_v8b+10\r
+       symbol_maker    'v10.8h',vect_v8h+10\r
+       symbol_maker    'v11.1d',vect_v1d+11\r
+       symbol_maker    'v11.1q',vect_v1q+21\r
+       symbol_maker    'v11.2d',vect_v2d+11\r
+       symbol_maker    'v11.2s',vect_v2s+11\r
+       symbol_maker    'v11.4h',vect_v4h+11\r
+       symbol_maker    'v11.4s',vect_v4s+11\r
+       symbol_maker    'v11.8b',vect_v8b+11\r
+       symbol_maker    'v11.8h',vect_v8h+11\r
+       symbol_maker    'v12.1d',vect_v1d+12\r
+       symbol_maker    'v12.1q',vect_v1q+22\r
+       symbol_maker    'v12.2d',vect_v2d+12\r
+       symbol_maker    'v12.2s',vect_v2s+12\r
+       symbol_maker    'v12.4h',vect_v4h+12\r
+       symbol_maker    'v12.4s',vect_v4s+12\r
+       symbol_maker    'v12.8b',vect_v8b+12\r
+       symbol_maker    'v12.8h',vect_v8h+12\r
+       symbol_maker    'v13.1d',vect_v1d+13\r
+       symbol_maker    'v13.1q',vect_v1q+23\r
+       symbol_maker    'v13.2d',vect_v2d+13\r
+       symbol_maker    'v13.2s',vect_v2s+13\r
+       symbol_maker    'v13.4h',vect_v4h+13\r
+       symbol_maker    'v13.4s',vect_v4s+13\r
+       symbol_maker    'v13.8b',vect_v8b+13\r
+       symbol_maker    'v13.8h',vect_v8h+13\r
+       symbol_maker    'v14.1d',vect_v1d+14\r
+       symbol_maker    'v14.1q',vect_v1q+24\r
+       symbol_maker    'v14.2d',vect_v2d+14\r
+       symbol_maker    'v14.2s',vect_v2s+14\r
+       symbol_maker    'v14.4h',vect_v4h+14\r
+       symbol_maker    'v14.4s',vect_v4s+14\r
+       symbol_maker    'v14.8b',vect_v8b+14\r
+       symbol_maker    'v14.8h',vect_v8h+14\r
+       symbol_maker    'v15.1d',vect_v1d+15\r
+       symbol_maker    'v15.1q',vect_v1q+25\r
+       symbol_maker    'v15.2d',vect_v2d+15\r
+       symbol_maker    'v15.2s',vect_v2s+15\r
+       symbol_maker    'v15.4h',vect_v4h+15\r
+       symbol_maker    'v15.4s',vect_v4s+15\r
+       symbol_maker    'v15.8b',vect_v8b+15\r
+       symbol_maker    'v15.8h',vect_v8h+15\r
+       symbol_maker    'v16.1d',vect_v1d+16\r
+       symbol_maker    'v16.1q',vect_v1q+26\r
+       symbol_maker    'v16.2d',vect_v2d+16\r
+       symbol_maker    'v16.2s',vect_v2s+16\r
+       symbol_maker    'v16.4h',vect_v4h+16\r
+       symbol_maker    'v16.4s',vect_v4s+16\r
+       symbol_maker    'v16.8b',vect_v8b+16\r
+       symbol_maker    'v16.8h',vect_v8h+16\r
+       symbol_maker    'v17.1d',vect_v1d+17\r
+       symbol_maker    'v17.1q',vect_v1q+27\r
+       symbol_maker    'v17.2d',vect_v2d+17\r
+       symbol_maker    'v17.2s',vect_v2s+17\r
+       symbol_maker    'v17.4h',vect_v4h+17\r
+       symbol_maker    'v17.4s',vect_v4s+17\r
+       symbol_maker    'v17.8b',vect_v8b+17\r
+       symbol_maker    'v17.8h',vect_v8h+17\r
+       symbol_maker    'v18.1d',vect_v1d+18\r
+       symbol_maker    'v18.1q',vect_v1q+28\r
+       symbol_maker    'v18.2d',vect_v2d+18\r
+       symbol_maker    'v18.2s',vect_v2s+18\r
+       symbol_maker    'v18.4h',vect_v4h+18\r
+       symbol_maker    'v18.4s',vect_v4s+18\r
+       symbol_maker    'v18.8b',vect_v8b+18\r
+       symbol_maker    'v18.8h',vect_v8h+18\r
+       symbol_maker    'v19.1d',vect_v1d+19\r
+       symbol_maker    'v19.1q',vect_v1q+29\r
+       symbol_maker    'v19.2d',vect_v2d+19\r
+       symbol_maker    'v19.2s',vect_v2s+19\r
+       symbol_maker    'v19.4h',vect_v4h+19\r
+       symbol_maker    'v19.4s',vect_v4s+19\r
+       symbol_maker    'v19.8b',vect_v8b+19\r
+       symbol_maker    'v19.8h',vect_v8h+19\r
+       symbol_maker    'v2.16b',vect_v16b+2\r
+       symbol_maker    'v20.1d',vect_v1d+20\r
+       symbol_maker    'v20.1q',vect_v1q+20\r
+       symbol_maker    'v20.2d',vect_v2d+20\r
+       symbol_maker    'v20.2s',vect_v2s+20\r
+       symbol_maker    'v20.4h',vect_v4h+20\r
+       symbol_maker    'v20.4s',vect_v4s+20\r
+       symbol_maker    'v20.8b',vect_v8b+20\r
+       symbol_maker    'v20.8h',vect_v8h+20\r
+       symbol_maker    'v21.1d',vect_v1d+21\r
+       symbol_maker    'v21.1q',vect_v1q+21\r
+       symbol_maker    'v21.2d',vect_v2d+21\r
+       symbol_maker    'v21.2s',vect_v2s+21\r
+       symbol_maker    'v21.4h',vect_v4h+21\r
+       symbol_maker    'v21.4s',vect_v4s+21\r
+       symbol_maker    'v21.8b',vect_v8b+21\r
+       symbol_maker    'v21.8h',vect_v8h+21\r
+       symbol_maker    'v22.1d',vect_v1d+22\r
+       symbol_maker    'v22.1q',vect_v1q+22\r
+       symbol_maker    'v22.2d',vect_v2d+22\r
+       symbol_maker    'v22.2s',vect_v2s+22\r
+       symbol_maker    'v22.4h',vect_v4h+22\r
+       symbol_maker    'v22.4s',vect_v4s+22\r
+       symbol_maker    'v22.8b',vect_v8b+22\r
+       symbol_maker    'v22.8h',vect_v8h+22\r
+       symbol_maker    'v23.1d',vect_v1d+23\r
+       symbol_maker    'v23.1q',vect_v1q+23\r
+       symbol_maker    'v23.2d',vect_v2d+23\r
+       symbol_maker    'v23.2s',vect_v2s+23\r
+       symbol_maker    'v23.4h',vect_v4h+23\r
+       symbol_maker    'v23.4s',vect_v4s+23\r
+       symbol_maker    'v23.8b',vect_v8b+23\r
+       symbol_maker    'v23.8h',vect_v8h+23\r
+       symbol_maker    'v24.1d',vect_v1d+24\r
+       symbol_maker    'v24.1q',vect_v1q+24\r
+       symbol_maker    'v24.2d',vect_v2d+24\r
+       symbol_maker    'v24.2s',vect_v2s+24\r
+       symbol_maker    'v24.4h',vect_v4h+24\r
+       symbol_maker    'v24.4s',vect_v4s+24\r
+       symbol_maker    'v24.8b',vect_v8b+24\r
+       symbol_maker    'v24.8h',vect_v8h+24\r
+       symbol_maker    'v25.1d',vect_v1d+25\r
+       symbol_maker    'v25.1q',vect_v1q+25\r
+       symbol_maker    'v25.2d',vect_v2d+25\r
+       symbol_maker    'v25.2s',vect_v2s+25\r
+       symbol_maker    'v25.4h',vect_v4h+25\r
+       symbol_maker    'v25.4s',vect_v4s+25\r
+       symbol_maker    'v25.8b',vect_v8b+25\r
+       symbol_maker    'v25.8h',vect_v8h+25\r
+       symbol_maker    'v26.1d',vect_v1d+26\r
+       symbol_maker    'v26.1q',vect_v1q+26\r
+       symbol_maker    'v26.2d',vect_v2d+26\r
+       symbol_maker    'v26.2s',vect_v2s+26\r
+       symbol_maker    'v26.4h',vect_v4h+26\r
+       symbol_maker    'v26.4s',vect_v4s+26\r
+       symbol_maker    'v26.8b',vect_v8b+26\r
+       symbol_maker    'v26.8h',vect_v8h+26\r
+       symbol_maker    'v27.1d',vect_v1d+27\r
+       symbol_maker    'v27.1q',vect_v1q+27\r
+       symbol_maker    'v27.2d',vect_v2d+27\r
+       symbol_maker    'v27.2s',vect_v2s+27\r
+       symbol_maker    'v27.4h',vect_v4h+27\r
+       symbol_maker    'v27.4s',vect_v4s+27\r
+       symbol_maker    'v27.8b',vect_v8b+27\r
+       symbol_maker    'v27.8h',vect_v8h+27\r
+       symbol_maker    'v28.1d',vect_v1d+28\r
+       symbol_maker    'v28.1q',vect_v1q+28\r
+       symbol_maker    'v28.2d',vect_v2d+28\r
+       symbol_maker    'v28.2s',vect_v2s+28\r
+       symbol_maker    'v28.4h',vect_v4h+28\r
+       symbol_maker    'v28.4s',vect_v4s+28\r
+       symbol_maker    'v28.8b',vect_v8b+28\r
+       symbol_maker    'v28.8h',vect_v8h+28\r
+       symbol_maker    'v29.1d',vect_v1d+29\r
+       symbol_maker    'v29.1q',vect_v1q+29\r
+       symbol_maker    'v29.2d',vect_v2d+29\r
+       symbol_maker    'v29.2s',vect_v2s+29\r
+       symbol_maker    'v29.4h',vect_v4h+29\r
+       symbol_maker    'v29.4s',vect_v4s+29\r
+       symbol_maker    'v29.8b',vect_v8b+29\r
+       symbol_maker    'v29.8h',vect_v8h+29\r
+       symbol_maker    'v3.16b',vect_v16b+3\r
+       symbol_maker    'v30.1d',vect_v1d+30\r
+       symbol_maker    'v30.1q',vect_v1q+30\r
+       symbol_maker    'v30.2d',vect_v2d+30\r
+       symbol_maker    'v30.2s',vect_v2s+30\r
+       symbol_maker    'v30.4h',vect_v4h+30\r
+       symbol_maker    'v30.4s',vect_v4s+30\r
+       symbol_maker    'v30.8b',vect_v8b+30\r
+       symbol_maker    'v30.8h',vect_v8h+30\r
+       symbol_maker    'v31.1d',vect_v1d+31\r
+       symbol_maker    'v31.1q',vect_v1q+31\r
+       symbol_maker    'v31.2d',vect_v2d+31\r
+       symbol_maker    'v31.2s',vect_v2s+31\r
+       symbol_maker    'v31.4h',vect_v4h+31\r
+       symbol_maker    'v31.4s',vect_v4s+31\r
+       symbol_maker    'v31.8b',vect_v8b+31\r
+       symbol_maker    'v31.8h',vect_v8h+31\r
+       symbol_maker    'v4.16b',vect_v16b+4\r
+       symbol_maker    'v5.16b',vect_v16b+5\r
+       symbol_maker    'v6.16b',vect_v16b+6\r
+       symbol_maker    'v7.16b',vect_v16b+7\r
+       symbol_maker    'v8.16b',vect_v16b+8\r
+       symbol_maker    'v9.16b',vect_v16b+9\r
+       symbol_maker    'vaale1',sys_tlbi+(sys_encode_vaale1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vae1is',sys_tlbi+(sys_encode_vae1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vae2is',sys_tlbi+(sys_encode_vae2is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vae3is',sys_tlbi+(sys_encode_vae3is-sys_encode_table_tlbi) shr 1\r
+symbols_7:\r
+       symbol_maker    'alle1is',sys_tlbi+(sys_encode_alle1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'alle2is',sys_tlbi+(sys_encode_alle2is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'alle3is',sys_tlbi+(sys_encode_alle3is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'basepri',sysm_reg+17\r
+       symbol_maker    'console',1Bh shl 8 + 3\r
+       symbol_maker    'control',sysm_reg+20\r
+       symbol_maker    'cpsr_cf',psr_reg+1\r
+       symbol_maker    'cpsr_cs',psr_reg+1\r
+       symbol_maker    'cpsr_cx',psr_reg+1\r
+       symbol_maker    'cpsr_fc',psr_reg+8\r
+       symbol_maker    'cpsr_fs',psr_reg+8\r
+       symbol_maker    'cpsr_fx',psr_reg+8\r
+       symbol_maker    'cpsr_sc',psr_reg+4\r
+       symbol_maker    'cpsr_sf',psr_reg+4\r
+       symbol_maker    'cpsr_sx',psr_reg+4\r
+       symbol_maker    'cpsr_xc',psr_reg+2\r
+       symbol_maker    'cpsr_xf',psr_reg+2\r
+       symbol_maker    'cpsr_xs',psr_reg+2\r
+       symbol_maker    'cpu32_a',cpu_sel+CPU32_CAPABILITY_A\r
+       symbol_maker    'cpu32_e',cpu_sel+CPU32_CAPABILITY_E\r
+       symbol_maker    'cpu32_j',cpu_sel+CPU32_CAPABILITY_J\r
+       symbol_maker    'cpu32_k',cpu_sel+CPU32_CAPABILITY_K\r
+       symbol_maker    'cpu32_m',cpu_sel+CPU32_CAPABILITY_M\r
+       symbol_maker    'cpu32_p',cpu_sel+CPU32_CAPABILITY_P\r
+       symbol_maker    'cpu32_x',cpu_sel+CPU32_CAPABILITY_X\r
+       symbol_maker    'cpu32_z',cpu_sel+CPU32_CAPABILITY_Z\r
+       symbol_maker    'ctr_el0',sys_msr+(sys_encode_ctr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'daifclr',sys_pstate+(sys_pencode_daifclr-sys_encode_table_pstate) shr 1\r
+       symbol_maker    'daifset',sys_pstate+(sys_pencode_daifset-sys_encode_table_pstate) shr 1\r
+       symbol_maker    'dlr_el0',sys_msr+(sys_encode_dlr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dynamic',1Eh shl 8 + 2\r
+       symbol_maker    'efiboot',1Bh shl 8 + 11\r
+       symbol_maker    'elr_el1',sys_msr+(sys_encode_elr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'elr_el2',sys_msr+(sys_encode_elr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'elr_el3',sys_msr+(sys_encode_elr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'elr_hyp',banked_reg+30\r
+       symbol_maker    'esr_el1',sys_msr+(sys_encode_esr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'esr_el2',sys_msr+(sys_encode_esr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'esr_el3',sys_msr+(sys_encode_esr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'far_el1',sys_msr+(sys_encode_far_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'far_el2',sys_msr+(sys_encode_far_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'far_el3',sys_msr+(sys_encode_far_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'fpinst2',vfp_syst+10\r
+       symbol_maker    'hcr_el2',sys_msr+(sys_encode_hcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ialluis',sys_ic+(sys_encode_ialluis-sys_encode_table_ic) shr 1\r
+       symbol_maker    'ipas2e1',sys_tlbi+(sys_encode_ipas2e1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'isr_el1',sys_msr+(sys_encode_isr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'par_el1',sys_msr+(sys_encode_par_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'primask',sysm_reg+16\r
+       symbol_maker    'r10@128',base_@128+10\r
+       symbol_maker    'r10@256',base_@256+10\r
+       symbol_maker    'r10_fiq',banked_reg+10\r
+       symbol_maker    'r10_usr',banked_reg+2\r
+       symbol_maker    'r11@128',base_@128+11\r
+       symbol_maker    'r11@256',base_@256+11\r
+       symbol_maker    'r11_fiq',banked_reg+11\r
+       symbol_maker    'r11_usr',banked_reg+3\r
+       symbol_maker    'r12@128',base_@128+12\r
+       symbol_maker    'r12@256',base_@256+12\r
+       symbol_maker    'r12_fiq',banked_reg+12\r
+       symbol_maker    'r12_usr',banked_reg+4\r
+       symbol_maker    'r13@128',base_@128+13\r
+       symbol_maker    'r13@256',base_@256+13\r
+       symbol_maker    'r14@128',base_@128+14\r
+       symbol_maker    'r14@256',base_@256+14\r
+       symbol_maker    'r15@128',base_@128+15\r
+       symbol_maker    'r15@256',base_@256+15\r
+       symbol_maker    'rmr_el1',sys_msr+(sys_encode_rmr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'rmr_el2',sys_msr+(sys_encode_rmr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'rmr_el3',sys_msr+(sys_encode_rmr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'scr_el3',sys_msr+(sys_encode_scr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_cf',psr_reg+16+8+1\r
+       symbol_maker    'spsr_cs',psr_reg+16+4+1\r
+       symbol_maker    'spsr_cx',psr_reg+16+2+1\r
+       symbol_maker    'spsr_fc',psr_reg+16+1+8\r
+       symbol_maker    'spsr_fs',psr_reg+16+4+8\r
+       symbol_maker    'spsr_fx',psr_reg+16+2+8\r
+       symbol_maker    'spsr_sc',psr_reg+16+1+4\r
+       symbol_maker    'spsr_sf',psr_reg+16+8+4\r
+       symbol_maker    'spsr_sx',psr_reg+16+2+4\r
+       symbol_maker    'spsr_xc',psr_reg+16+1+2\r
+       symbol_maker    'spsr_xf',psr_reg+16+8+2\r
+       symbol_maker    'spsr_xs',psr_reg+16+4+2\r
+       symbol_maker    'tcr_el1',sys_msr+(sys_encode_tcr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tcr_el2',sys_msr+(sys_encode_tcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tcr_el3',sys_msr+(sys_encode_tcr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'v10.16b',vect_v16b+10\r
+       symbol_maker    'v11.16b',vect_v16b+11\r
+       symbol_maker    'v12.16b',vect_v16b+12\r
+       symbol_maker    'v13.16b',vect_v16b+13\r
+       symbol_maker    'v14.16b',vect_v16b+14\r
+       symbol_maker    'v15.16b',vect_v16b+15\r
+       symbol_maker    'v16.16b',vect_v16b+16\r
+       symbol_maker    'v17.16b',vect_v16b+17\r
+       symbol_maker    'v18.16b',vect_v16b+18\r
+       symbol_maker    'v19.16b',vect_v16b+19\r
+       symbol_maker    'v20.16b',vect_v16b+20\r
+       symbol_maker    'v21.16b',vect_v16b+21\r
+       symbol_maker    'v22.16b',vect_v16b+22\r
+       symbol_maker    'v23.16b',vect_v16b+23\r
+       symbol_maker    'v24.16b',vect_v16b+24\r
+       symbol_maker    'v25.16b',vect_v16b+25\r
+       symbol_maker    'v26.16b',vect_v16b+26\r
+       symbol_maker    'v27.16b',vect_v16b+27\r
+       symbol_maker    'v28.16b',vect_v16b+28\r
+       symbol_maker    'v29.16b',vect_v16b+29\r
+       symbol_maker    'v30.16b',vect_v16b+30\r
+       symbol_maker    'v31.16b',vect_v16b+31\r
+       symbol_maker    'vaae1is',sys_tlbi+(sys_encode_vaae1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale1is',sys_tlbi+(sys_encode_vale1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale2is',sys_tlbi+(sys_encode_vale2is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vale3is',sys_tlbi+(sys_encode_vale3is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vmalle1',sys_tlbi+(sys_encode_vmalle1-sys_encode_table_tlbi) shr 1\r
+symbols_8:\r
+       symbol_maker    'aidr_el1',sys_msr+(sys_encode_aidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'aside1is',sys_tlbi+(sys_encode_aside1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'cpsr_all',psr_reg+8+1\r
+       symbol_maker    'cpsr_cfs',psr_reg+8+4+1\r
+       symbol_maker    'cpsr_cfx',psr_reg+8+2+1\r
+       symbol_maker    'cpsr_csf',psr_reg+8+4+1\r
+       symbol_maker    'cpsr_csx',psr_reg+4+2+1\r
+       symbol_maker    'cpsr_ctl',psr_reg+1\r
+       symbol_maker    'cpsr_cxf',psr_reg+8+2+1\r
+       symbol_maker    'cpsr_cxs',psr_reg+4+2+1\r
+       symbol_maker    'cpsr_fcs',psr_reg+1+4+8\r
+       symbol_maker    'cpsr_fcx',psr_reg+1+2+8\r
+       symbol_maker    'cpsr_flg',psr_reg+8\r
+       symbol_maker    'cpsr_fsc',psr_reg+1+4+8\r
+       symbol_maker    'cpsr_fsx',psr_reg+4+2+8\r
+       symbol_maker    'cpsr_fxc',psr_reg+1+2+8\r
+       symbol_maker    'cpsr_fxs',psr_reg+4+2+8\r
+       symbol_maker    'cpsr_scf',psr_reg+8+1+4\r
+       symbol_maker    'cpsr_scx',psr_reg+1+2+4\r
+       symbol_maker    'cpsr_sfc',psr_reg+8+1+4\r
+       symbol_maker    'cpsr_sfx',psr_reg+8+2+4\r
+       symbol_maker    'cpsr_sxc',psr_reg+1+2+4\r
+       symbol_maker    'cpsr_sxf',psr_reg+8+2+4\r
+       symbol_maker    'cpsr_xcf',psr_reg+8+1+2\r
+       symbol_maker    'cpsr_xcs',psr_reg+4+1+2\r
+       symbol_maker    'cpsr_xfc',psr_reg+8+1+2\r
+       symbol_maker    'cpsr_xfs',psr_reg+8+4+2\r
+       symbol_maker    'cpsr_xsc',psr_reg+4+1+2\r
+       symbol_maker    'cpsr_xsf',psr_reg+8+4+2\r
+       symbol_maker    'cptr_el2',sys_msr+(sys_encode_cptr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cptr_el3',sys_msr+(sys_encode_cptr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cpu32_6m',cpu_sel+CPU32_CAPABILITY_6M\r
+       symbol_maker    'cpu32_7m',cpu_sel+CPU32_CAPABILITY_7M\r
+       symbol_maker    'cpu32_mp',cpu_sel+CPU32_CAPABILITY_MP\r
+       symbol_maker    'cpu32_t2',cpu_sel+CPU32_CAPABILITY_T2\r
+       symbol_maker    'cpu32_v1',cpu_sel+CPU32_CAPABILITY_V1\r
+       symbol_maker    'cpu32_v2',cpu_sel+CPU32_CAPABILITY_V2\r
+       symbol_maker    'cpu32_v3',cpu_sel+CPU32_CAPABILITY_V3\r
+       symbol_maker    'cpu32_v4',cpu_sel+CPU32_CAPABILITY_V4\r
+       symbol_maker    'cpu32_v5',cpu_sel+CPU32_CAPABILITY_V5\r
+       symbol_maker    'cpu32_v6',cpu_sel+CPU32_CAPABILITY_V6\r
+       symbol_maker    'cpu32_v7',cpu_sel+CPU32_CAPABILITY_V7\r
+       symbol_maker    'cpu32_v8',cpu_sel+CPU32_CAPABILITY_V8\r
+       symbol_maker    'cpu32_ve',cpu_sel+CPU32_CAPABILITY_VE\r
+       symbol_maker    'cpu64_fp',cpu_sel+CPU64_CAPABILITY_FP\r
+       symbol_maker    'cpu64_v8',cpu_sel+CPU64_CAPABILITY_V8\r
+       symbol_maker    'hacr_el2',sys_msr+(sys_encode_hacr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'hstr_el2',sys_msr+(sys_encode_hstr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'iflags_a',iflags+4\r
+       symbol_maker    'iflags_f',iflags+1\r
+       symbol_maker    'iflags_i',iflags+2\r
+       symbol_maker    'ipas2le1',sys_tlbi+(sys_encode_ipas2le1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'linkinfo',19h shl 8 + 9\r
+       symbol_maker    'mair_el1',sys_msr+(sys_encode_mair_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mair_el2',sys_msr+(sys_encode_mair_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mair_el3',sys_msr+(sys_encode_mair_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mdcr_el2',sys_msr+(sys_encode_mdcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mdcr_el3',sys_msr+(sys_encode_mdcr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'midr_el1',sys_msr+(sys_encode_midr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmcr_el0',sys_msr+(sys_encode_pmcr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'readable',19h shl 8 + 30\r
+       symbol_maker    'resource',1Ah shl 8 + 2\r
+       symbol_maker    'spsr_abt',banked_reg+32+20\r
+;;     symbol_maker    'spsr_abt',sys_msr+(sys_encode_spsr_abt-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_all',psr_reg+16+8+1\r
+       symbol_maker    'spsr_cfs',psr_reg+16+8+4+1\r
+       symbol_maker    'spsr_cfx',psr_reg+16+8+2+1\r
+       symbol_maker    'spsr_csf',psr_reg+16+8+4+1\r
+       symbol_maker    'spsr_csx',psr_reg+16+4+2+1\r
+       symbol_maker    'spsr_ctl',psr_reg+16+1\r
+       symbol_maker    'spsr_cxf',psr_reg+16+8+2+1\r
+       symbol_maker    'spsr_cxs',psr_reg+16+4+2+1\r
+       symbol_maker    'spsr_el1',sys_msr+(sys_encode_spsr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_el2',sys_msr+(sys_encode_spsr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_el3',sys_msr+(sys_encode_spsr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_fcs',psr_reg+16+1+4+8\r
+       symbol_maker    'spsr_fcx',psr_reg+16+1+2+8\r
+       symbol_maker    'spsr_fiq',banked_reg+32+14\r
+;;     symbol_maker    'spsr_fiq',sys_msr+(sys_encode_spsr_fiq-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_flg',psr_reg+16+8\r
+       symbol_maker    'spsr_fsc',psr_reg+16+1+4+8\r
+       symbol_maker    'spsr_fsx',psr_reg+16+4+2+8\r
+       symbol_maker    'spsr_fxc',psr_reg+16+1+2+8\r
+       symbol_maker    'spsr_fxs',psr_reg+16+4+2+8\r
+       symbol_maker    'spsr_hyp',banked_reg+32+30\r
+       symbol_maker    'spsr_irq',banked_reg+32+16\r
+;;     symbol_maker    'spsr_irq',sys_msr+(sys_encode_spsr_irq-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_mon',banked_reg+32+28\r
+       symbol_maker    'spsr_scf',psr_reg+16+8+1+4\r
+       symbol_maker    'spsr_scx',psr_reg+16+1+2+4\r
+       symbol_maker    'spsr_sfc',psr_reg+16+8+1+4\r
+       symbol_maker    'spsr_sfx',psr_reg+16+8+2+4\r
+       symbol_maker    'spsr_svc',banked_reg+32+18\r
+       symbol_maker    'spsr_sxc',psr_reg+16+1+2+4\r
+       symbol_maker    'spsr_sxf',psr_reg+16+8+2+4\r
+       symbol_maker    'spsr_und',banked_reg+32+22\r
+;;     symbol_maker    'spsr_und',sys_msr+(sys_encode_spsr_und-sys_encode_table_msr) shr 1\r
+       symbol_maker    'spsr_xcf',psr_reg+16+8+1+2\r
+       symbol_maker    'spsr_xcs',psr_reg+16+4+1+2\r
+       symbol_maker    'spsr_xfc',psr_reg+16+8+1+2\r
+       symbol_maker    'spsr_xfs',psr_reg+16+8+4+2\r
+       symbol_maker    'spsr_xsc',psr_reg+16+4+1+2\r
+       symbol_maker    'spsr_xsf',psr_reg+16+8+4+2\r
+       symbol_maker    'vaale1is',sys_tlbi+(sys_encode_vaale1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vbar_el1',sys_msr+(sys_encode_vbar_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vbar_el2',sys_msr+(sys_encode_vbar_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vbar_el3',sys_msr+(sys_encode_vbar_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vtcr_el2',sys_msr+(sys_encode_vtcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'writable',19h shl 8 + 31\r
+symbols_9:\r
+       symbol_maker    'actlr_el1',sys_msr+(sys_encode_actlr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'actlr_el2',sys_msr+(sys_encode_actlr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'actlr_el3',sys_msr+(sys_encode_actlr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr0_el1',sys_msr+(sys_encode_afsr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr0_el2',sys_msr+(sys_encode_afsr0_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr0_el3',sys_msr+(sys_encode_afsr0_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr1_el1',sys_msr+(sys_encode_afsr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr1_el2',sys_msr+(sys_encode_afsr1_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'afsr1_el3',sys_msr+(sys_encode_afsr1_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'amair_el1',sys_msr+(sys_encode_amair_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'amair_el2',sys_msr+(sys_encode_amair_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'amair_el3',sys_msr+(sys_encode_amair_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'apsr_nzcv',psr_reg+34\r
+       symbol_maker    'clidr_el1',sys_msr+(sys_encode_clidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'copro_all',copro_sel.all\r
+       symbol_maker    'cpacr_el1',sys_msr+(sys_encode_cpacr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cpsr_cfsx',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_cfxs',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_csfx',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_csxf',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_cxfs',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_cxsf',psr_reg+8+4+2+1\r
+       symbol_maker    'cpsr_fcsx',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_fcxs',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_fscx',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_fsxc',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_fxcs',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_fxsc',psr_reg+1+4+2+8\r
+       symbol_maker    'cpsr_scfx',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_scxf',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_sfcx',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_sfxc',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_sxcf',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_sxfc',psr_reg+8+1+2+4\r
+       symbol_maker    'cpsr_xcfs',psr_reg+8+4+1+2\r
+       symbol_maker    'cpsr_xcsf',psr_reg+8+4+1+2\r
+       symbol_maker    'cpsr_xfcs',psr_reg+8+4+1+2\r
+       symbol_maker    'cpsr_xfsc',psr_reg+8+4+1+2\r
+       symbol_maker    'cpsr_xscf',psr_reg+8+4+1+2\r
+       symbol_maker    'cpsr_xsfc',psr_reg+8+4+1+2\r
+       symbol_maker    'cpu32_all',cpu_sel.all32\r
+       symbol_maker    'cpu32_crc',cpu_sel+CPU32_CAPABILITY_CRC\r
+       symbol_maker    'cpu32_div',cpu_sel+CPU32_CAPABILITY_DIV\r
+       symbol_maker    'cpu32_v4t',cpu_sel+CPU32_CAPABILITY_V4T\r
+       symbol_maker    'cpu32_v5t',cpu_sel+CPU32_CAPABILITY_V5T\r
+       symbol_maker    'cpu32_v6t',cpu_sel+CPU32_CAPABILITY_V6T\r
+       symbol_maker    'cpu64_all',cpu_sel.all64\r
+       symbol_maker    'cpu64_crc',cpu_sel+CPU64_CAPABILITY_CRC\r
+       symbol_maker    'currentel',sys_msr+(sys_encode_currentel-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dczid_el0',sys_msr+(sys_encode_dczid_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dspsr_el0',sys_msr+(sys_encode_dspsr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'faultmask',sysm_reg+19\r
+       symbol_maker    'hpfar_el2',sys_msr+(sys_encode_hpfar_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'iflags_af',iflags+4+1\r
+       symbol_maker    'iflags_ai',iflags+4+2\r
+       symbol_maker    'iflags_fa',iflags+1+4\r
+       symbol_maker    'iflags_fi',iflags+1+2\r
+       symbol_maker    'iflags_ia',iflags+2+4\r
+       symbol_maker    'iflags_if',iflags+2+1\r
+       symbol_maker    'ipas2e1is',sys_tlbi+(sys_encode_ipas2e1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'mdrar_el1',sys_msr+(sys_encode_mdrar_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mdscr_el1',sys_msr+(sys_encode_mdscr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mpidr_el1',sys_msr+(sys_encode_mpidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mvfr0_el1',sys_msr+(sys_encode_mvfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mvfr1_el1',sys_msr+(sys_encode_mvfr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'mvfr2_el1',sys_msr+(sys_encode_mvfr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'osdlr_el1',sys_msr+(sys_encode_osdlr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'oslar_el1',sys_msr+(sys_encode_oslar_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'oslsr_el1',sys_msr+(sys_encode_oslsr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pldl1keep',prf_op+0*8+0*2+0\r
+       symbol_maker    'pldl1strm',prf_op+0*8+0*2+1\r
+       symbol_maker    'pldl2keep',prf_op+0*8+1*2+0\r
+       symbol_maker    'pldl2strm',prf_op+0*8+1*2+1\r
+       symbol_maker    'pldl3keep',prf_op+0*8+2*2+0\r
+       symbol_maker    'pldl3strm',prf_op+0*8+2*2+1\r
+       symbol_maker    'plil1keep',prf_op+1*8+0*2+0\r
+       symbol_maker    'plil1strm',prf_op+1*8+0*2+1\r
+       symbol_maker    'plil2keep',prf_op+1*8+1*2+0\r
+       symbol_maker    'plil2strm',prf_op+1*8+1*2+1\r
+       symbol_maker    'plil3keep',prf_op+1*8+2*2+0\r
+       symbol_maker    'plil3strm',prf_op+1*8+2*2+1\r
+       symbol_maker    'pstl1keep',prf_op+2*8+0*2+0\r
+       symbol_maker    'pstl1strm',prf_op+2*8+0*2+1\r
+       symbol_maker    'pstl2keep',prf_op+2*8+1*2+0\r
+       symbol_maker    'pstl2strm',prf_op+2*8+1*2+1\r
+       symbol_maker    'pstl3keep',prf_op+2*8+2*2+0\r
+       symbol_maker    'pstl3strm',prf_op+2*8+2*2+1\r
+       symbol_maker    'rvbar_el1',sys_msr+(sys_encode_rvbar_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'rvbar_el2',sys_msr+(sys_encode_rvbar_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'rvbar_el3',sys_msr+(sys_encode_rvbar_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sctlr_el1',sys_msr+(sys_encode_sctlr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sctlr_el2',sys_msr+(sys_encode_sctlr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sctlr_el3',sys_msr+(sys_encode_sctlr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'shareable',19h shl 8 + 28\r
+       symbol_maker    'spsr_cfsx',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_cfxs',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_csfx',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_csxf',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_cxfs',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_cxsf',psr_reg+16+8+4+2+1\r
+       symbol_maker    'spsr_fcsx',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_fcxs',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_fscx',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_fsxc',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_fxcs',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_fxsc',psr_reg+16+1+4+2+8\r
+       symbol_maker    'spsr_scfx',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_scxf',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_sfcx',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_sfxc',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_sxcf',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_sxfc',psr_reg+16+8+1+2+4\r
+       symbol_maker    'spsr_xcfs',psr_reg+16+8+4+1+2\r
+       symbol_maker    'spsr_xcsf',psr_reg+16+8+4+1+2\r
+       symbol_maker    'spsr_xfcs',psr_reg+16+8+4+1+2\r
+       symbol_maker    'spsr_xfsc',psr_reg+16+8+4+1+2\r
+       symbol_maker    'spsr_xscf',psr_reg+16+8+4+1+2\r
+       symbol_maker    'spsr_xsfc',psr_reg+16+8+4+1+2\r
+       symbol_maker    'tpidr_el0',sys_msr+(sys_encode_tpidr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tpidr_el1',sys_msr+(sys_encode_tpidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tpidr_el2',sys_msr+(sys_encode_tpidr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tpidr_el3',sys_msr+(sys_encode_tpidr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ttbr0_el1',sys_msr+(sys_encode_ttbr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ttbr0_el2',sys_msr+(sys_encode_ttbr0_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ttbr0_el3',sys_msr+(sys_encode_ttbr0_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ttbr1_el1',sys_msr+(sys_encode_ttbr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vmalle1is',sys_tlbi+(sys_encode_vmalle1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vpidr_el2',sys_msr+(sys_encode_vpidr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vttbr_el2',sys_msr+(sys_encode_vttbr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'writeable',19h shl 8 + 31\r
+symbols_10:\r
+       symbol_maker    'apsr_nzcvq',psr_reg+8\r
+       symbol_maker    'ccsidr_el1',sys_msr+(sys_encode_ccsidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntfrq_el0',sys_msr+(sys_encode_cntfrq_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntpct_el0',sys_msr+(sys_encode_cntpct_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntvct_el0',sys_msr+(sys_encode_cntvct_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cpu32_sync',cpu_sel+CPU32_CAPABILITY_SYNC\r
+       symbol_maker    'cpu32_t2ee',cpu_sel+CPU32_CAPABILITY_T2EE\r
+       symbol_maker    'cpu64_simd',cpu_sel+CPU64_CAPABILITY_SIMD\r
+       symbol_maker    'csselr_el1',sys_msr+(sys_encode_csselr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dacr32_el2',sys_msr+(sys_encode_dacr32_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgdtr_el0',sys_msr+(sys_encode_dbgdtr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'efiruntime',1Bh shl 8 + 12\r
+       symbol_maker    'executable',19h shl 8 + 29\r
+       symbol_maker    'iflags_afi',iflags+4+1+2\r
+       symbol_maker    'iflags_aif',iflags+4+2+1\r
+       symbol_maker    'iflags_fai',iflags+1+4+2\r
+       symbol_maker    'iflags_fia',iflags+1+2+4\r
+       symbol_maker    'iflags_iaf',iflags+2+4+1\r
+       symbol_maker    'iflags_ifa',iflags+2+1+4\r
+       symbol_maker    'ifsr32_el2',sys_msr+(sys_encode_ifsr32_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ipas2le1is',sys_tlbi+(sys_encode_ipas2le1is-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'linkremove',19h shl 8 + 11\r
+       symbol_maker    'mdccsr_el0',sys_msr+(sys_encode_mdccsr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'oseccr_el1',sys_msr+(sys_encode_oseccr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmselr_el0',sys_msr+(sys_encode_pmselr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'revidr_el1',sys_msr+(sys_encode_revidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'sder32_el3',sys_msr+(sys_encode_sder32_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vmalls12e1',sys_tlbi+(sys_encode_vmalls12e1-sys_encode_table_tlbi) shr 1\r
+       symbol_maker    'vmpidr_el2',sys_msr+(sys_encode_vmpidr_el2-sys_encode_table_msr) shr 1\r
+symbols_11:\r
+       symbol_maker    'apsr_nzcvqg',psr_reg+8+4\r
+       symbol_maker    'basepri_max',sysm_reg+18\r
+       symbol_maker    'cnthctl_el2',sys_msr+(sys_encode_cnthctl_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntkctl_el1',sys_msr+(sys_encode_cntkctl_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntvoff_el2',sys_msr+(sys_encode_cntvoff_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cpu32_26bit',cpu_sel+CPU32_CAPABILITY_26BIT\r
+       symbol_maker    'cpu32_align',cpu_sel+CPU32_CAPABILITY_ALIGN\r
+       symbol_maker    'dbgbcr0_el1',sys_msr+(sys_encode_dbgbcr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr1_el1',sys_msr+(sys_encode_dbgbcr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr2_el1',sys_msr+(sys_encode_dbgbcr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr3_el1',sys_msr+(sys_encode_dbgbcr3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr4_el1',sys_msr+(sys_encode_dbgbcr4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr5_el1',sys_msr+(sys_encode_dbgbcr5_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr6_el1',sys_msr+(sys_encode_dbgbcr6_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr7_el1',sys_msr+(sys_encode_dbgbcr7_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr8_el1',sys_msr+(sys_encode_dbgbcr8_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr9_el1',sys_msr+(sys_encode_dbgbcr9_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr0_el1',sys_msr+(sys_encode_dbgbvr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr1_el1',sys_msr+(sys_encode_dbgbvr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr2_el1',sys_msr+(sys_encode_dbgbvr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr3_el1',sys_msr+(sys_encode_dbgbvr3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr4_el1',sys_msr+(sys_encode_dbgbvr4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr5_el1',sys_msr+(sys_encode_dbgbvr5_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr6_el1',sys_msr+(sys_encode_dbgbvr6_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr7_el1',sys_msr+(sys_encode_dbgbvr7_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr8_el1',sys_msr+(sys_encode_dbgbvr8_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr9_el1',sys_msr+(sys_encode_dbgbvr9_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgprcr_el1',sys_msr+(sys_encode_dbgprcr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr0_el1',sys_msr+(sys_encode_dbgwcr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr1_el1',sys_msr+(sys_encode_dbgwcr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr2_el1',sys_msr+(sys_encode_dbgwcr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr3_el1',sys_msr+(sys_encode_dbgwcr3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr4_el1',sys_msr+(sys_encode_dbgwcr4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr5_el1',sys_msr+(sys_encode_dbgwcr5_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr6_el1',sys_msr+(sys_encode_dbgwcr6_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr7_el1',sys_msr+(sys_encode_dbgwcr7_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr8_el1',sys_msr+(sys_encode_dbgwcr8_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr9_el1',sys_msr+(sys_encode_dbgwcr9_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr0_el1',sys_msr+(sys_encode_dbgwvr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr1_el1',sys_msr+(sys_encode_dbgwvr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr2_el1',sys_msr+(sys_encode_dbgwvr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr3_el1',sys_msr+(sys_encode_dbgwvr3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr4_el1',sys_msr+(sys_encode_dbgwvr4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr5_el1',sys_msr+(sys_encode_dbgwvr5_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr6_el1',sys_msr+(sys_encode_dbgwvr6_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr7_el1',sys_msr+(sys_encode_dbgwvr7_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr8_el1',sys_msr+(sys_encode_dbgwvr8_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr9_el1',sys_msr+(sys_encode_dbgwvr9_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'discardable',19h shl 8 + 25\r
+       symbol_maker    'fpexc32_el2',sys_msr+(sys_encode_fpexc32_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_dir_el1',sys_msr+(sys_encode_icc_dir_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_pmr_el1',sys_msr+(sys_encode_icc_pmr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_rpr_el1',sys_msr+(sys_encode_icc_rpr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_sre_el1',sys_msr+(sys_encode_icc_sre_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_sre_el2',sys_msr+(sys_encode_icc_sre_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_sre_el3',sys_msr+(sys_encode_icc_sre_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_hcr_el2',sys_msr+(sys_encode_ich_hcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr0_el2',sys_msr+(sys_encode_ich_lr0_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr1_el2',sys_msr+(sys_encode_ich_lr1_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr2_el2',sys_msr+(sys_encode_ich_lr2_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr3_el2',sys_msr+(sys_encode_ich_lr3_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr4_el2',sys_msr+(sys_encode_ich_lr4_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr5_el2',sys_msr+(sys_encode_ich_lr5_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr6_el2',sys_msr+(sys_encode_ich_lr6_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr7_el2',sys_msr+(sys_encode_ich_lr7_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr8_el2',sys_msr+(sys_encode_ich_lr8_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr9_el2',sys_msr+(sys_encode_ich_lr9_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_vtr_el2',sys_msr+(sys_encode_ich_vtr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_dir_el1',sys_msr+(sys_encode_icv_dir_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_pmr_el1',sys_msr+(sys_encode_icv_pmr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_rpr_el1',sys_msr+(sys_encode_icv_rpr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_afr0_el1',sys_msr+(sys_encode_id_afr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_dfr0_el1',sys_msr+(sys_encode_id_dfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_pfr0_el1',sys_msr+(sys_encode_id_pfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_pfr1_el1',sys_msr+(sys_encode_id_pfr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'interpreter',1Eh shl 8 + 3\r
+       symbol_maker    'mdccint_el1',sys_msr+(sys_encode_mdccint_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'notpageable',19h shl 8 + 27\r
+       symbol_maker    'osdtrrx_el1',sys_msr+(sys_encode_osdtrrx_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'osdtrtx_el1',sys_msr+(sys_encode_osdtrtx_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmccntr_el0',sys_msr+(sys_encode_pmccntr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmceid0_el0',sys_msr+(sys_encode_pmceid0_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmceid1_el0',sys_msr+(sys_encode_pmceid1_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmswinc_el0',sys_msr+(sys_encode_pmswinc_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'tpidrro_el0',sys_msr+(sys_encode_tpidrro_el0-sys_encode_table_msr) shr 1\r
+symbols_12:\r
+       symbol_maker    'cntp_ctl_el0',sys_msr+(sys_encode_cntp_ctl_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntv_ctl_el0',sys_msr+(sys_encode_cntv_ctl_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'copro_fpa_v1',copro_sel+COPRO_CAPABILITY_FPA_V1\r
+       symbol_maker    'copro_fpa_v2',copro_sel+COPRO_CAPABILITY_FPA_V2\r
+       symbol_maker    'copro_vfp_hp',copro_sel+COPRO_CAPABILITY_VFP_HP\r
+       symbol_maker    'copro_vfp_v1',copro_sel+COPRO_CAPABILITY_VFP_V1\r
+       symbol_maker    'copro_vfp_v2',copro_sel+COPRO_CAPABILITY_VFP_V2\r
+       symbol_maker    'copro_vfp_v3',copro_sel+COPRO_CAPABILITY_VFP_V3\r
+       symbol_maker    'copro_vfp_v4',copro_sel+COPRO_CAPABILITY_VFP_V4\r
+       symbol_maker    'copro_xscale',copro_sel+COPRO_CAPABILITY_XSCALE\r
+       symbol_maker    'cpu64_crypto',cpu_sel+CPU64_CAPABILITY_CRYPTO\r
+       symbol_maker    'dbgbcr10_el1',sys_msr+(sys_encode_dbgbcr10_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr11_el1',sys_msr+(sys_encode_dbgbcr11_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr12_el1',sys_msr+(sys_encode_dbgbcr12_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr13_el1',sys_msr+(sys_encode_dbgbcr13_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr14_el1',sys_msr+(sys_encode_dbgbcr14_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbcr15_el1',sys_msr+(sys_encode_dbgbcr15_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr10_el1',sys_msr+(sys_encode_dbgbvr10_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr11_el1',sys_msr+(sys_encode_dbgbvr11_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr12_el1',sys_msr+(sys_encode_dbgbvr12_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr13_el1',sys_msr+(sys_encode_dbgbvr13_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr14_el1',sys_msr+(sys_encode_dbgbvr14_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgbvr15_el1',sys_msr+(sys_encode_dbgbvr15_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgdtrrx_el0',sys_msr+(sys_encode_dbgdtrrx_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgdtrtx_el0',sys_msr+(sys_encode_dbgdtrtx_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgvcr32_el2',sys_msr+(sys_encode_dbgvcr32_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr10_el1',sys_msr+(sys_encode_dbgwcr10_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr11_el1',sys_msr+(sys_encode_dbgwcr11_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr12_el1',sys_msr+(sys_encode_dbgwcr12_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr13_el1',sys_msr+(sys_encode_dbgwcr13_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr14_el1',sys_msr+(sys_encode_dbgwcr14_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwcr15_el1',sys_msr+(sys_encode_dbgwcr15_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr10_el1',sys_msr+(sys_encode_dbgwvr10_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr11_el1',sys_msr+(sys_encode_dbgwvr11_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr12_el1',sys_msr+(sys_encode_dbgwvr12_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr13_el1',sys_msr+(sys_encode_dbgwvr13_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr14_el1',sys_msr+(sys_encode_dbgwvr14_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgwvr15_el1',sys_msr+(sys_encode_dbgwvr15_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_bpr0_el1',sys_msr+(sys_encode_icc_bpr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_bpr1_el1',sys_msr+(sys_encode_icc_bpr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ctlr_el1',sys_msr+(sys_encode_icc_ctlr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ctlr_el3',sys_msr+(sys_encode_icc_ctlr_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_iar0_el1',sys_msr+(sys_encode_icc_iar0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_iar1_el1',sys_msr+(sys_encode_icc_iar1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_eisr_el2',sys_msr+(sys_encode_ich_eisr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr10_el2',sys_msr+(sys_encode_ich_lr10_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr11_el2',sys_msr+(sys_encode_ich_lr11_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr12_el2',sys_msr+(sys_encode_ich_lr12_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr13_el2',sys_msr+(sys_encode_ich_lr13_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr14_el2',sys_msr+(sys_encode_ich_lr14_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_lr15_el2',sys_msr+(sys_encode_ich_lr15_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_misr_el2',sys_msr+(sys_encode_ich_misr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_vmcr_el2',sys_msr+(sys_encode_ich_vmcr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_bpr0_el1',sys_msr+(sys_encode_icv_bpr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_bpr1_el1',sys_msr+(sys_encode_icv_bpr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ctlr_el1',sys_msr+(sys_encode_icv_ctlr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_iar0_el1',sys_msr+(sys_encode_icv_iar0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_iar1_el1',sys_msr+(sys_encode_icv_iar1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar0_el1',sys_msr+(sys_encode_id_isar0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar1_el1',sys_msr+(sys_encode_id_isar1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar2_el1',sys_msr+(sys_encode_id_isar2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar3_el1',sys_msr+(sys_encode_id_isar3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar4_el1',sys_msr+(sys_encode_id_isar4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_isar5_el1',sys_msr+(sys_encode_id_isar5_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_mmfr0_el1',sys_msr+(sys_encode_id_mmfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_mmfr1_el1',sys_msr+(sys_encode_id_mmfr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_mmfr2_el1',sys_msr+(sys_encode_id_mmfr2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_mmfr3_el1',sys_msr+(sys_encode_id_mmfr3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_mmfr4_el1',sys_msr+(sys_encode_id_mmfr4_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmovsclr_el0',sys_msr+(sys_encode_pmovsclr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmovsset_el0',sys_msr+(sys_encode_pmovsset_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'vmalls12e1is',sys_tlbi+(sys_encode_vmalls12e1is-sys_encode_table_tlbi) shr 1\r
+symbols_13:\r
+       symbol_maker    'cnthp_ctl_el2',sys_msr+(sys_encode_cnthp_ctl_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntp_cval_el0',sys_msr+(sys_encode_cntp_cval_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntp_tval_el0',sys_msr+(sys_encode_cntp_tval_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntps_ctl_el1',sys_msr+(sys_encode_cntps_ctl_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntv_cval_el0',sys_msr+(sys_encode_cntv_cval_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntv_tval_el0',sys_msr+(sys_encode_cntv_tval_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'copro_simd_hp',copro_sel+COPRO_CAPABILITY_SIMD_HP\r
+       symbol_maker    'copro_simd_v2',copro_sel+COPRO_CAPABILITY_SIMD_V2\r
+       symbol_maker    'copro_simd_v8',copro_sel+COPRO_CAPABILITY_SIMD_V8\r
+       symbol_maker    'copro_vfp_d32',copro_sel+COPRO_CAPABILITY_VFP_D32\r
+       symbol_maker    'icc_ap0r0_el1',sys_msr+(sys_encode_icc_ap0r0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap0r1_el1',sys_msr+(sys_encode_icc_ap0r1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap0r2_el1',sys_msr+(sys_encode_icc_ap0r2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap0r3_el1',sys_msr+(sys_encode_icc_ap0r3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap1r0_el1',sys_msr+(sys_encode_icc_ap1r0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap1r1_el1',sys_msr+(sys_encode_icc_ap1r1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap1r2_el1',sys_msr+(sys_encode_icc_ap1r2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_ap1r3_el1',sys_msr+(sys_encode_icc_ap1r3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_eoir0_el1',sys_msr+(sys_encode_icc_eoir0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_eoir1_el1',sys_msr+(sys_encode_icc_eoir1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_sgi0r_el1',sys_msr+(sys_encode_icc_sgi0r_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_sgi1r_el1',sys_msr+(sys_encode_icc_sgi1r_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap0r0_el2',sys_msr+(sys_encode_ich_ap0r0_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap0r1_el2',sys_msr+(sys_encode_ich_ap0r1_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap0r2_el2',sys_msr+(sys_encode_ich_ap0r2_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap0r3_el2',sys_msr+(sys_encode_ich_ap0r3_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap1r0_el2',sys_msr+(sys_encode_ich_ap1r0_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap1r1_el2',sys_msr+(sys_encode_ich_ap1r1_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap1r2_el2',sys_msr+(sys_encode_ich_ap1r2_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_ap1r3_el2',sys_msr+(sys_encode_ich_ap1r3_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'ich_elrsr_el2',sys_msr+(sys_encode_ich_elrsr_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap0r0_el1',sys_msr+(sys_encode_icv_ap0r0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap0r1_el1',sys_msr+(sys_encode_icv_ap0r1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap0r2_el1',sys_msr+(sys_encode_icv_ap0r2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap0r3_el1',sys_msr+(sys_encode_icv_ap0r3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap1r0_el1',sys_msr+(sys_encode_icv_ap1r0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap1r1_el1',sys_msr+(sys_encode_icv_ap1r1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap1r2_el1',sys_msr+(sys_encode_icv_ap1r2_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_ap1r3_el1',sys_msr+(sys_encode_icv_ap1r3_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_eoir0_el1',sys_msr+(sys_encode_icv_eoir0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_eoir1_el1',sys_msr+(sys_encode_icv_eoir1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmccfiltr_el0',sys_msr+(sys_encode_pmccfiltr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr0_el0',sys_msr+(sys_encode_pmevcntr0_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr1_el0',sys_msr+(sys_encode_pmevcntr1_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr2_el0',sys_msr+(sys_encode_pmevcntr2_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr3_el0',sys_msr+(sys_encode_pmevcntr3_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr4_el0',sys_msr+(sys_encode_pmevcntr4_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr5_el0',sys_msr+(sys_encode_pmevcntr5_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr6_el0',sys_msr+(sys_encode_pmevcntr6_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr7_el0',sys_msr+(sys_encode_pmevcntr7_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr8_el0',sys_msr+(sys_encode_pmevcntr8_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr9_el0',sys_msr+(sys_encode_pmevcntr9_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmuserenr_el0',sys_msr+(sys_encode_pmuserenr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmxevcntr_el0',sys_msr+(sys_encode_pmxevcntr_el0-sys_encode_table_msr) shr 1\r
+symbols_14:\r
+       symbol_maker    'cnthp_cval_el2',sys_msr+(sys_encode_cnthp_cval_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cnthp_tval_el2',sys_msr+(sys_encode_cnthp_tval_el2-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntps_cval_el1',sys_msr+(sys_encode_cntps_cval_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'cntps_tval_el1',sys_msr+(sys_encode_cntps_tval_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'contextidr_el1',sys_msr+(sys_encode_contextidr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'copro_maverick',copro_sel+COPRO_CAPABILITY_MAVERICK\r
+       symbol_maker    'copro_simd_int',copro_sel+COPRO_CAPABILITY_SIMD_INT\r
+       symbol_maker    'copro_vfp_v1xd',copro_sel+COPRO_CAPABILITY_VFP_V1xD\r
+       symbol_maker    'icc_asgi1r_el1',sys_msr+(sys_encode_icc_asgi1r_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_hppir0_el1',sys_msr+(sys_encode_icc_hppir0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_hppir1_el1',sys_msr+(sys_encode_icc_hppir1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_hppir0_el1',sys_msr+(sys_encode_icv_hppir0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_hppir1_el1',sys_msr+(sys_encode_icv_hppir1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmcntenclr_el0',sys_msr+(sys_encode_pmcntenclr_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmcntenset_el0',sys_msr+(sys_encode_pmcntenset_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr10_el0',sys_msr+(sys_encode_pmevcntr10_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr11_el0',sys_msr+(sys_encode_pmevcntr11_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr12_el0',sys_msr+(sys_encode_pmevcntr12_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr13_el0',sys_msr+(sys_encode_pmevcntr13_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr14_el0',sys_msr+(sys_encode_pmevcntr14_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr15_el0',sys_msr+(sys_encode_pmevcntr15_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr16_el0',sys_msr+(sys_encode_pmevcntr16_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr17_el0',sys_msr+(sys_encode_pmevcntr17_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr18_el0',sys_msr+(sys_encode_pmevcntr18_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr19_el0',sys_msr+(sys_encode_pmevcntr19_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr20_el0',sys_msr+(sys_encode_pmevcntr20_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr21_el0',sys_msr+(sys_encode_pmevcntr21_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr22_el0',sys_msr+(sys_encode_pmevcntr22_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr23_el0',sys_msr+(sys_encode_pmevcntr23_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr24_el0',sys_msr+(sys_encode_pmevcntr24_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr25_el0',sys_msr+(sys_encode_pmevcntr25_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr26_el0',sys_msr+(sys_encode_pmevcntr26_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr27_el0',sys_msr+(sys_encode_pmevcntr27_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr28_el0',sys_msr+(sys_encode_pmevcntr28_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr29_el0',sys_msr+(sys_encode_pmevcntr29_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevcntr30_el0',sys_msr+(sys_encode_pmevcntr30_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper0_el0',sys_msr+(sys_encode_pmevtyper0_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper1_el0',sys_msr+(sys_encode_pmevtyper1_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper2_el0',sys_msr+(sys_encode_pmevtyper2_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper3_el0',sys_msr+(sys_encode_pmevtyper3_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper4_el0',sys_msr+(sys_encode_pmevtyper4_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper5_el0',sys_msr+(sys_encode_pmevtyper5_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper6_el0',sys_msr+(sys_encode_pmevtyper6_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper7_el0',sys_msr+(sys_encode_pmevtyper7_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper8_el0',sys_msr+(sys_encode_pmevtyper8_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper9_el0',sys_msr+(sys_encode_pmevtyper9_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmintenclr_el1',sys_msr+(sys_encode_pmintenclr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmintenset_el1',sys_msr+(sys_encode_pmintenset_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmxevtyper_el0',sys_msr+(sys_encode_pmxevtyper_el0-sys_encode_table_msr) shr 1\r
+symbols_15:\r
+       symbol_maker    'copro_iwmmxt_v1',copro_sel+COPRO_CAPABILITY_IWMMXT_V1\r
+       symbol_maker    'copro_iwmmxt_v2',copro_sel+COPRO_CAPABILITY_IWMMXT_V2\r
+       symbol_maker    'dbgclaimclr_el1',sys_msr+(sys_encode_dbgclaimclr_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'dbgclaimset_el1',sys_msr+(sys_encode_dbgclaimset_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_igrpen0_el1',sys_msr+(sys_encode_icc_igrpen0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_igrpen1_el1',sys_msr+(sys_encode_icc_igrpen1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icc_igrpen1_el3',sys_msr+(sys_encode_icc_igrpen1_el3-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_igrpen0_el1',sys_msr+(sys_encode_icv_igrpen0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'icv_igrpen1_el1',sys_msr+(sys_encode_icv_igrpen1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64afr0_el1',sys_msr+(sys_encode_id_aa64afr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64afr1_el1',sys_msr+(sys_encode_id_aa64afr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64dfr0_el1',sys_msr+(sys_encode_id_aa64dfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64dfr1_el1',sys_msr+(sys_encode_id_aa64dfr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64pfr0_el1',sys_msr+(sys_encode_id_aa64pfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64pfr1_el1',sys_msr+(sys_encode_id_aa64pfr1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper10_el0',sys_msr+(sys_encode_pmevtyper10_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper11_el0',sys_msr+(sys_encode_pmevtyper11_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper12_el0',sys_msr+(sys_encode_pmevtyper12_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper13_el0',sys_msr+(sys_encode_pmevtyper13_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper14_el0',sys_msr+(sys_encode_pmevtyper14_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper15_el0',sys_msr+(sys_encode_pmevtyper15_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper16_el0',sys_msr+(sys_encode_pmevtyper16_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper17_el0',sys_msr+(sys_encode_pmevtyper17_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper18_el0',sys_msr+(sys_encode_pmevtyper18_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper19_el0',sys_msr+(sys_encode_pmevtyper19_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper20_el0',sys_msr+(sys_encode_pmevtyper20_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper21_el0',sys_msr+(sys_encode_pmevtyper21_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper22_el0',sys_msr+(sys_encode_pmevtyper22_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper23_el0',sys_msr+(sys_encode_pmevtyper23_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper24_el0',sys_msr+(sys_encode_pmevtyper24_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper25_el0',sys_msr+(sys_encode_pmevtyper25_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper26_el0',sys_msr+(sys_encode_pmevtyper26_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper27_el0',sys_msr+(sys_encode_pmevtyper27_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper28_el0',sys_msr+(sys_encode_pmevtyper28_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper29_el0',sys_msr+(sys_encode_pmevtyper29_el0-sys_encode_table_msr) shr 1\r
+       symbol_maker    'pmevtyper30_el0',sys_msr+(sys_encode_pmevtyper30_el0-sys_encode_table_msr) shr 1\r
+symbols_16:\r
+       symbol_maker    'copro_simd_float',copro_sel+COPRO_CAPABILITY_SIMD_FLOAT\r
+       symbol_maker    'id_aa64isar0_el1',sys_msr+(sys_encode_id_aa64isar0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64isar1_el1',sys_msr+(sys_encode_id_aa64isar1_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64mmfr0_el1',sys_msr+(sys_encode_id_aa64mmfr0_el1-sys_encode_table_msr) shr 1\r
+       symbol_maker    'id_aa64mmfr1_el1',sys_msr+(sys_encode_id_aa64mmfr1_el1-sys_encode_table_msr) shr 1\r
+symbols_17:\r
+       symbol_maker    'copro_simd_crypto',copro_sel+COPRO_CAPABILITY_SIMD_CRYPTO\r
+       symbol_maker    'dbgauthstatus_el1',sys_msr+(sys_encode_dbgauthstatus_el1-sys_encode_table_msr) shr 1\r
+symbols_end:\r
+\r
+purge symbol_maker\r
+\r
+       align 2\r
+sys_encode_table_at:\r
+       ;at                                     op0           op1            crn            crm            op2\r
+       sys_encode_s12e0r:              dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_s12e0w:              dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0111b\r
+       sys_encode_s12e1r:              dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0100b\r
+       sys_encode_s12e1w:              dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0101b\r
+       sys_encode_s1e0r:               dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0010b\r
+       sys_encode_s1e0w:               dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0011b\r
+       sys_encode_s1e1r:               dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_s1e1w:               dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_s1e2r:               dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_s1e2w:               dw      001b shl 14 + 0100b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_s1e3r:               dw      001b shl 14 + 0110b shl 11 + 00111b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_s1e3w:               dw      001b shl 14 + 0110b shl 11 + 00111b shl 7 + 01000b shl 3 + 0001b\r
+sys_encode_table_dc:\r
+       ;dc                                     op0           op1            crn            crm            op2\r
+       sys_encode_cisw:                dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01110b shl 3 + 0010b\r
+       sys_encode_civac:               dw      001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01110b shl 3 + 0001b\r
+       sys_encode_csw:                 dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 01010b shl 3 + 0010b\r
+       sys_encode_cvac:                dw      001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01010b shl 3 + 0001b\r
+       sys_encode_cvau:                dw      001b shl 14 + 0011b shl 11 + 00111b shl 7 + 01011b shl 3 + 0001b\r
+       sys_encode_isw:                 dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00110b shl 3 + 0010b\r
+       sys_encode_ivac:                dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00110b shl 3 + 0001b\r
+       sys_encode_zva:                 dw      001b shl 14 + 0011b shl 11 + 00111b shl 7 + 00100b shl 3 + 0001b\r
+sys_encode_table_ic:\r
+       ;ic                                     op0           op1            crn            crm            op2\r
+       sys_encode_iallu:               dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00101b shl 3 + 0000b\r
+       sys_encode_ialluis:             dw      001b shl 14 + 0000b shl 11 + 00111b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_ivau:                dw      001b shl 14 + 0011b shl 11 + 00111b shl 7 + 00101b shl 3 + 0001b\r
+sys_encode_table_tlbi:\r
+       ;tlbi                                   op0           op1            crn            crm            op2\r
+       sys_encode_alle1:               dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0100b\r
+       sys_encode_alle1is:             dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0100b\r
+       sys_encode_alle2:               dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b\r
+       sys_encode_alle2is:             dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_alle3:               dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b\r
+       sys_encode_alle3is:             dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_aside1:              dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0010b\r
+       sys_encode_aside1is:            dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0010b\r
+       sys_encode_ipas2e1:             dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00100b shl 3 + 0001b\r
+       sys_encode_ipas2e1is:           dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_ipas2le1:            dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00100b shl 3 + 0101b\r
+       sys_encode_ipas2le1is:          dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00000b shl 3 + 0101b\r
+       sys_encode_vaae1:               dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0011b\r
+       sys_encode_vaae1is:             dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0011b\r
+       sys_encode_vaale1:              dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0111b\r
+       sys_encode_vaale1is:            dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0111b\r
+       sys_encode_vae1:                dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b\r
+       sys_encode_vae1is:              dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_vae2:                dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b\r
+       sys_encode_vae2is:              dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_vae3:                dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0001b\r
+       sys_encode_vae3is:              dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_vale1:               dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b\r
+       sys_encode_vale1is:             dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b\r
+       sys_encode_vale2:               dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b\r
+       sys_encode_vale2is:             dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b\r
+       sys_encode_vale3:               dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00111b shl 3 + 0101b\r
+       sys_encode_vale3is:             dw      001b shl 14 + 0110b shl 11 + 01000b shl 7 + 00011b shl 3 + 0101b\r
+       sys_encode_vmalle1:             dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00111b shl 3 + 0000b\r
+       sys_encode_vmalle1is:           dw      001b shl 14 + 0000b shl 11 + 01000b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_vmalls12e1:          dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00111b shl 3 + 0110b\r
+       sys_encode_vmalls12e1is:        dw      001b shl 14 + 0100b shl 11 + 01000b shl 7 + 00011b shl 3 + 0110b\r
+sys_encode_table_msr:\r
+       ;msr/mrs                                op0           op1            crn            crm            op2\r
+       sys_encode_actlr_el1:           dw      011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_actlr_el2:           dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_actlr_el3:           dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_afsr0_el1:           dw      011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_afsr0_el2:           dw      011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_afsr0_el3:           dw      011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_afsr1_el1:           dw      011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_afsr1_el2:           dw      011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_afsr1_el3:           dw      011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_aidr_el1:            dw      011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b\r
+       sys_encode_amair_el1:           dw      011b shl 14 + 0000b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_amair_el2:           dw      011b shl 14 + 0100b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_amair_el3:           dw      011b shl 14 + 0110b shl 11 + 01010b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_ccsidr_el1:          dw      011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_clidr_el1:           dw      011b shl 14 + 0001b shl 11 + 00000b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_cntfrq_el0:          dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_cnthctl_el2:         dw      011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_cnthp_ctl_el2:       dw      011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b\r
+       sys_encode_cnthp_cval_el2:      dw      011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_cnthp_tval_el2:      dw      011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_cntkctl_el1:         dw      011b shl 14 + 0000b shl 11 + 01110b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_cntp_ctl_el0:        dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b\r
+       sys_encode_cntp_cval_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_cntp_tval_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_cntpct_el0:          dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_cntps_ctl_el1:       dw      011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0001b\r
+       sys_encode_cntps_cval_el1:      dw      011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_cntps_tval_el1:      dw      011b shl 14 + 0111b shl 11 + 01110b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_cntv_ctl_el0:        dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_cntv_cval_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0010b\r
+       sys_encode_cntv_tval_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_cntvct_el0:          dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_cntvoff_el2:         dw      011b shl 14 + 0100b shl 11 + 01110b shl 7 + 00000b shl 3 + 0011b\r
+       sys_encode_contextidr_el1:      dw      011b shl 14 + 0000b shl 11 + 01101b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_cpacr_el1:           dw      011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_cptr_el2:            dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0010b\r
+       sys_encode_cptr_el3:            dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0010b\r
+       sys_encode_csselr_el1:          dw      011b shl 14 + 0010b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_ctr_el0:             dw      011b shl 14 + 0011b shl 11 + 00000b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_currentel:           dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_dacr32_el2:          dw      011b shl 14 + 0100b shl 11 + 00011b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_daif:                dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00010b shl 3 + 0001b\r
+       sys_encode_dbgauthstatus_el1:   dw      010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01110b shl 3 + 0110b\r
+       sys_encode_dbgbcr0_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b\r
+       sys_encode_dbgbcr1_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0101b\r
+       sys_encode_dbgbcr10_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0101b\r
+       sys_encode_dbgbcr11_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0101b\r
+       sys_encode_dbgbcr12_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_dbgbcr13_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0101b\r
+       sys_encode_dbgbcr14_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0101b\r
+       sys_encode_dbgbcr15_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0101b\r
+       sys_encode_dbgbcr2_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0101b\r
+       sys_encode_dbgbcr3_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0101b\r
+       sys_encode_dbgbcr4_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0101b\r
+       sys_encode_dbgbcr5_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0101b\r
+       sys_encode_dbgbcr6_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0101b\r
+       sys_encode_dbgbcr7_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0101b\r
+       sys_encode_dbgbcr8_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0101b\r
+       sys_encode_dbgbcr9_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0101b\r
+       sys_encode_dbgbvr0_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0100b\r
+       sys_encode_dbgbvr1_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0100b\r
+       sys_encode_dbgbvr10_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0100b\r
+       sys_encode_dbgbvr11_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0100b\r
+       sys_encode_dbgbvr12_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_dbgbvr13_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0100b\r
+       sys_encode_dbgbvr14_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0100b\r
+       sys_encode_dbgbvr15_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0100b\r
+       sys_encode_dbgbvr2_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0100b\r
+       sys_encode_dbgbvr3_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0100b\r
+       sys_encode_dbgbvr4_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0100b\r
+       sys_encode_dbgbvr5_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0100b\r
+       sys_encode_dbgbvr6_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0100b\r
+       sys_encode_dbgbvr7_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0100b\r
+       sys_encode_dbgbvr8_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0100b\r
+       sys_encode_dbgbvr9_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0100b\r
+       sys_encode_dbgclaimclr_el1:     dw      010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01001b shl 3 + 0110b\r
+       sys_encode_dbgclaimset_el1:     dw      010b shl 14 + 0000b shl 11 + 00111b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_dbgdtr_el0:          dw      010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00100b shl 3 + 0000b\r
+       sys_encode_dbgdtrrx_el0:        dw      010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b\r
+       sys_encode_dbgdtrtx_el0:        dw      010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b\r
+       sys_encode_dbgprcr_el1:         dw      010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00100b shl 3 + 0100b\r
+       sys_encode_dbgvcr32_el2:        dw      010b shl 14 + 0100b shl 11 + 00000b shl 7 + 00111b shl 3 + 0000b\r
+       sys_encode_dbgwcr0_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b\r
+       sys_encode_dbgwcr1_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0111b\r
+       sys_encode_dbgwcr10_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0111b\r
+       sys_encode_dbgwcr11_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0111b\r
+       sys_encode_dbgwcr12_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_dbgwcr13_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0111b\r
+       sys_encode_dbgwcr14_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0111b\r
+       sys_encode_dbgwcr15_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0111b\r
+       sys_encode_dbgwcr2_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0111b\r
+       sys_encode_dbgwcr3_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0111b\r
+       sys_encode_dbgwcr4_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0111b\r
+       sys_encode_dbgwcr5_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0111b\r
+       sys_encode_dbgwcr6_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0111b\r
+       sys_encode_dbgwcr7_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0111b\r
+       sys_encode_dbgwcr8_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0111b\r
+       sys_encode_dbgwcr9_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0111b\r
+       sys_encode_dbgwvr0_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0110b\r
+       sys_encode_dbgwvr1_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0110b\r
+       sys_encode_dbgwvr10_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01010b shl 3 + 0110b\r
+       sys_encode_dbgwvr11_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01011b shl 3 + 0110b\r
+       sys_encode_dbgwvr12_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_dbgwvr13_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01101b shl 3 + 0110b\r
+       sys_encode_dbgwvr14_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01110b shl 3 + 0110b\r
+       sys_encode_dbgwvr15_el1:        dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01111b shl 3 + 0110b\r
+       sys_encode_dbgwvr2_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0110b\r
+       sys_encode_dbgwvr3_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0110b\r
+       sys_encode_dbgwvr4_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0110b\r
+       sys_encode_dbgwvr5_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0110b\r
+       sys_encode_dbgwvr6_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0110b\r
+       sys_encode_dbgwvr7_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0110b\r
+       sys_encode_dbgwvr8_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_dbgwvr9_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 01001b shl 3 + 0110b\r
+       sys_encode_dczid_el0:           dw      011b shl 14 + 0011b shl 11 + 00000b shl 7 + 00000b shl 3 + 0111b\r
+       sys_encode_dlr_el0:             dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00101b shl 3 + 0001b\r
+       sys_encode_dspsr_el0:           dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00101b shl 3 + 0000b\r
+       sys_encode_elr_el1:             dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_elr_el2:             dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_elr_el3:             dw      011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_esr_el1:             dw      011b shl 14 + 0000b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_esr_el2:             dw      011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_esr_el3:             dw      011b shl 14 + 0110b shl 11 + 00101b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_far_el1:             dw      011b shl 14 + 0000b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_far_el2:             dw      011b shl 14 + 0100b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_far_el3:             dw      011b shl 14 + 0110b shl 11 + 00110b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_fpcr:                dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00100b shl 3 + 0000b\r
+       sys_encode_fpexc32_el2:         dw      011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_fpsr:                dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00100b shl 3 + 0001b\r
+       sys_encode_hacr_el2:            dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0111b\r
+       sys_encode_hcr_el2:             dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_hpfar_el2:           dw      011b shl 14 + 0100b shl 11 + 00110b shl 7 + 00000b shl 3 + 0100b\r
+       sys_encode_hstr_el2:            dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0011b\r
+       sys_encode_icc_ap0r0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0100b\r
+       sys_encode_icc_ap0r1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0101b\r
+       sys_encode_icc_ap0r2_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_icc_ap0r3_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0111b\r
+       sys_encode_icc_ap1r0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b\r
+       sys_encode_icc_ap1r1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b\r
+       sys_encode_icc_ap1r2_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b\r
+       sys_encode_icc_ap1r3_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b\r
+       sys_encode_icc_asgi1r_el1:      dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0110b\r
+       sys_encode_icc_bpr0_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b\r
+       sys_encode_icc_bpr1_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b\r
+       sys_encode_icc_ctlr_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_icc_ctlr_el3:        dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_icc_dir_el1:         dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b\r
+       sys_encode_icc_eoir0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_icc_eoir1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b\r
+       sys_encode_icc_hppir0_el1:      dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b\r
+       sys_encode_icc_hppir1_el1:      dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b\r
+       sys_encode_icc_iar0_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_icc_iar1_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b\r
+       sys_encode_icc_igrpen0_el1:     dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_icc_igrpen1_el1:     dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_icc_igrpen1_el3:     dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_icc_pmr_el1:         dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00110b shl 3 + 0000b\r
+       sys_encode_icc_rpr_el1:         dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b\r
+       sys_encode_icc_sgi0r_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0111b\r
+       sys_encode_icc_sgi1r_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0101b\r
+       sys_encode_icc_sre_el1:         dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_icc_sre_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0101b\r
+       sys_encode_icc_sre_el3:         dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_ich_ap0r0_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_ich_ap0r1_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_ich_ap0r2_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b\r
+       sys_encode_ich_ap0r3_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b\r
+       sys_encode_ich_ap1r0_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b\r
+       sys_encode_ich_ap1r1_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b\r
+       sys_encode_ich_ap1r2_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b\r
+       sys_encode_ich_ap1r3_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b\r
+       sys_encode_ich_eisr_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b\r
+       sys_encode_ich_elrsr_el2:       dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0101b\r
+       sys_encode_ich_hcr_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0000b\r
+       sys_encode_ich_lr0_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b\r
+       sys_encode_ich_lr1_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b\r
+       sys_encode_ich_lr10_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0010b\r
+       sys_encode_ich_lr11_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0011b\r
+       sys_encode_ich_lr12_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0100b\r
+       sys_encode_ich_lr13_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0101b\r
+       sys_encode_ich_lr14_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0110b\r
+       sys_encode_ich_lr15_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0111b\r
+       sys_encode_ich_lr2_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b\r
+       sys_encode_ich_lr3_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b\r
+       sys_encode_ich_lr4_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_ich_lr5_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_ich_lr6_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_ich_lr7_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_ich_lr8_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0000b\r
+       sys_encode_ich_lr9_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01101b shl 3 + 0001b\r
+       sys_encode_ich_misr_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0010b\r
+       sys_encode_ich_vmcr_el2:        dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0111b\r
+       sys_encode_ich_vtr_el2:         dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b\r
+       sys_encode_icv_ap0r0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0100b\r
+       sys_encode_icv_ap0r1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0101b\r
+       sys_encode_icv_ap0r2_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_icv_ap0r3_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0111b\r
+       sys_encode_icv_ap1r0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0000b\r
+       sys_encode_icv_ap1r1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0001b\r
+       sys_encode_icv_ap1r2_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0010b\r
+       sys_encode_icv_ap1r3_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01001b shl 3 + 0011b\r
+       sys_encode_icv_bpr0_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0011b\r
+       sys_encode_icv_bpr1_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0011b\r
+       sys_encode_icv_ctlr_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_icv_dir_el1:         dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0001b\r
+       sys_encode_icv_eoir0_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_icv_eoir1_el1:       dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0001b\r
+       sys_encode_icv_hppir0_el1:      dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0010b\r
+       sys_encode_icv_hppir1_el1:      dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0010b\r
+       sys_encode_icv_iar0_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_icv_iar1_el1:        dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0000b\r
+       sys_encode_icv_igrpen0_el1:     dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_icv_igrpen1_el1:     dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_icv_pmr_el1:         dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00110b shl 3 + 0000b\r
+       sys_encode_icv_rpr_el1:         dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 01011b shl 3 + 0011b\r
+       sys_encode_id_aa64afr0_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0100b\r
+       sys_encode_id_aa64afr1_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0101b\r
+       sys_encode_id_aa64dfr0_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0000b\r
+       sys_encode_id_aa64dfr1_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00101b shl 3 + 0001b\r
+       sys_encode_id_aa64isar0_el1:    dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0000b\r
+       sys_encode_id_aa64isar1_el1:    dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0001b\r
+       sys_encode_id_aa64mmfr0_el1:    dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0000b\r
+       sys_encode_id_aa64mmfr1_el1:    dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00111b shl 3 + 0001b\r
+       sys_encode_id_aa64pfr0_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0000b\r
+       sys_encode_id_aa64pfr1_el1:     dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00100b shl 3 + 0001b\r
+       sys_encode_id_afr0_el1:         dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0011b\r
+       sys_encode_id_dfr0_el1:         dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0010b\r
+       sys_encode_id_isar0_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_id_isar1_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0001b\r
+       sys_encode_id_isar2_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_id_isar3_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0011b\r
+       sys_encode_id_isar4_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0100b\r
+       sys_encode_id_isar5_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0101b\r
+       sys_encode_id_mmfr0_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0100b\r
+       sys_encode_id_mmfr1_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0101b\r
+       sys_encode_id_mmfr2_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0110b\r
+       sys_encode_id_mmfr3_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0111b\r
+       sys_encode_id_mmfr4_el1:        dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0110b\r
+       sys_encode_id_pfr0_el1:         dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_id_pfr1_el1:         dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_ifsr32_el2:          dw      011b shl 14 + 0100b shl 11 + 00101b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_isr_el1:             dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_mair_el1:            dw      011b shl 14 + 0000b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_mair_el2:            dw      011b shl 14 + 0100b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_mair_el3:            dw      011b shl 14 + 0110b shl 11 + 01010b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_mdccint_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_mdccsr_el0:          dw      010b shl 14 + 0011b shl 11 + 00000b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_mdcr_el2:            dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_mdcr_el3:            dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_mdrar_el1:           dw      010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_mdscr_el1:           dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00010b shl 3 + 0010b\r
+       sys_encode_midr_el1:            dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_mpidr_el1:           dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b\r
+       sys_encode_mvfr0_el1:           dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_mvfr1_el1:           dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_mvfr2_el1:           dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0010b\r
+       sys_encode_nzcv:                dw      011b shl 14 + 0011b shl 11 + 00100b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_osdlr_el1:           dw      010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00011b shl 3 + 0100b\r
+       sys_encode_osdtrrx_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_osdtrtx_el1:         dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00011b shl 3 + 0010b\r
+       sys_encode_oseccr_el1:          dw      010b shl 14 + 0000b shl 11 + 00000b shl 7 + 00110b shl 3 + 0010b\r
+       sys_encode_oslar_el1:           dw      010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0100b\r
+       sys_encode_oslsr_el1:           dw      010b shl 14 + 0000b shl 11 + 00001b shl 7 + 00001b shl 3 + 0100b\r
+       sys_encode_par_el1:             dw      011b shl 14 + 0000b shl 11 + 00111b shl 7 + 00100b shl 3 + 0000b\r
+       sys_encode_pmccfiltr_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0111b\r
+       sys_encode_pmccntr_el0:         dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0000b\r
+       sys_encode_pmceid0_el0:         dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_pmceid1_el0:         dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_pmcntenclr_el0:      dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0010b\r
+       sys_encode_pmcntenset_el0:      dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0001b\r
+       sys_encode_pmcr_el0:            dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0000b\r
+       sys_encode_pmevcntr0_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0000b\r
+       sys_encode_pmevcntr1_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0001b\r
+       sys_encode_pmevcntr10_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0010b\r
+       sys_encode_pmevcntr11_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0011b\r
+       sys_encode_pmevcntr12_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0100b\r
+       sys_encode_pmevcntr13_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0101b\r
+       sys_encode_pmevcntr14_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0110b\r
+       sys_encode_pmevcntr15_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0111b\r
+       sys_encode_pmevcntr16_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0000b\r
+       sys_encode_pmevcntr17_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0001b\r
+       sys_encode_pmevcntr18_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0010b\r
+       sys_encode_pmevcntr19_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0011b\r
+       sys_encode_pmevcntr2_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0010b\r
+       sys_encode_pmevcntr20_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0100b\r
+       sys_encode_pmevcntr21_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0101b\r
+       sys_encode_pmevcntr22_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0110b\r
+       sys_encode_pmevcntr23_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01010b shl 3 + 0111b\r
+       sys_encode_pmevcntr24_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0000b\r
+       sys_encode_pmevcntr25_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0001b\r
+       sys_encode_pmevcntr26_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0010b\r
+       sys_encode_pmevcntr27_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0011b\r
+       sys_encode_pmevcntr28_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0100b\r
+       sys_encode_pmevcntr29_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0101b\r
+       sys_encode_pmevcntr3_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0011b\r
+       sys_encode_pmevcntr30_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01011b shl 3 + 0110b\r
+       sys_encode_pmevcntr4_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0100b\r
+       sys_encode_pmevcntr5_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0101b\r
+       sys_encode_pmevcntr6_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0110b\r
+       sys_encode_pmevcntr7_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01000b shl 3 + 0111b\r
+       sys_encode_pmevcntr8_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0000b\r
+       sys_encode_pmevcntr9_el0:       dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01001b shl 3 + 0001b\r
+       sys_encode_pmevtyper0_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0000b\r
+       sys_encode_pmevtyper1_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0001b\r
+       sys_encode_pmevtyper10_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0010b\r
+       sys_encode_pmevtyper11_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0011b\r
+       sys_encode_pmevtyper12_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0100b\r
+       sys_encode_pmevtyper13_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0101b\r
+       sys_encode_pmevtyper14_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0110b\r
+       sys_encode_pmevtyper15_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0111b\r
+       sys_encode_pmevtyper16_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0000b\r
+       sys_encode_pmevtyper17_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0001b\r
+       sys_encode_pmevtyper18_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0010b\r
+       sys_encode_pmevtyper19_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0011b\r
+       sys_encode_pmevtyper2_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0010b\r
+       sys_encode_pmevtyper20_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0100b\r
+       sys_encode_pmevtyper21_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0101b\r
+       sys_encode_pmevtyper22_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0110b\r
+       sys_encode_pmevtyper23_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01110b shl 3 + 0111b\r
+       sys_encode_pmevtyper24_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0000b\r
+       sys_encode_pmevtyper25_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0001b\r
+       sys_encode_pmevtyper26_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0010b\r
+       sys_encode_pmevtyper27_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0011b\r
+       sys_encode_pmevtyper28_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0100b\r
+       sys_encode_pmevtyper29_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0101b\r
+       sys_encode_pmevtyper3_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0011b\r
+       sys_encode_pmevtyper30_el0:     dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01111b shl 3 + 0110b\r
+       sys_encode_pmevtyper4_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_pmevtyper5_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_pmevtyper6_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0110b\r
+       sys_encode_pmevtyper7_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01100b shl 3 + 0111b\r
+       sys_encode_pmevtyper8_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0000b\r
+       sys_encode_pmevtyper9_el0:      dw      011b shl 14 + 0011b shl 11 + 01110b shl 7 + 01101b shl 3 + 0001b\r
+       sys_encode_pmintenclr_el1:      dw      011b shl 14 + 0000b shl 11 + 01001b shl 7 + 01110b shl 3 + 0010b\r
+       sys_encode_pmintenset_el1:      dw      011b shl 14 + 0000b shl 11 + 01001b shl 7 + 01110b shl 3 + 0001b\r
+       sys_encode_pmovsclr_el0:        dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0011b\r
+       sys_encode_pmovsset_el0:        dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01110b shl 3 + 0011b\r
+       sys_encode_pmselr_el0:          dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0101b\r
+       sys_encode_pmswinc_el0:         dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01100b shl 3 + 0100b\r
+       sys_encode_pmuserenr_el0:       dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01110b shl 3 + 0000b\r
+       sys_encode_pmxevcntr_el0:       dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0010b\r
+       sys_encode_pmxevtyper_el0:      dw      011b shl 14 + 0011b shl 11 + 01001b shl 7 + 01101b shl 3 + 0001b\r
+       sys_encode_revidr_el1:          dw      011b shl 14 + 0000b shl 11 + 00000b shl 7 + 00000b shl 3 + 0110b\r
+       sys_encode_rmr_el1:             dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_rmr_el2:             dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_rmr_el3:             dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_rvbar_el1:           dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_rvbar_el2:           dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_rvbar_el3:           dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_scr_el3:             dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_sctlr_el1:           dw      011b shl 14 + 0000b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_sctlr_el2:           dw      011b shl 14 + 0100b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_sctlr_el3:           dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_sder32_el3:          dw      011b shl 14 + 0110b shl 11 + 00001b shl 7 + 00001b shl 3 + 0001b\r
+       sys_encode_sp_el0:              dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_sp_el1:              dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_sp_el2:              dw      011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00001b shl 3 + 0000b\r
+       sys_encode_spsel:               dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00010b shl 3 + 0000b\r
+       sys_encode_spsr_abt:            dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0001b\r
+       sys_encode_spsr_el1:            dw      011b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_spsr_el2:            dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_spsr_el3:            dw      011b shl 14 + 0110b shl 11 + 00100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_spsr_fiq:            dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0011b\r
+       sys_encode_spsr_irq:            dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0000b\r
+       sys_encode_spsr_und:            dw      011b shl 14 + 0100b shl 11 + 00100b shl 7 + 00011b shl 3 + 0010b\r
+       sys_encode_tcr_el1:             dw      011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tcr_el2:             dw      011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tcr_el3:             dw      011b shl 14 + 0110b shl 11 + 00010b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tpidr_el0:           dw      011b shl 14 + 0011b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tpidr_el1:           dw      011b shl 14 + 0000b shl 11 + 01101b shl 7 + 00000b shl 3 + 0100b\r
+       sys_encode_tpidr_el2:           dw      011b shl 14 + 0100b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tpidr_el3:           dw      011b shl 14 + 0110b shl 11 + 01101b shl 7 + 00000b shl 3 + 0010b\r
+       sys_encode_tpidrro_el0:         dw      011b shl 14 + 0011b shl 11 + 01101b shl 7 + 00000b shl 3 + 0011b\r
+       sys_encode_ttbr0_el1:           dw      011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_ttbr0_el2:           dw      011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_ttbr0_el3:           dw      011b shl 14 + 0110b shl 11 + 00010b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_ttbr1_el1:           dw      011b shl 14 + 0000b shl 11 + 00010b shl 7 + 00000b shl 3 + 0001b\r
+       sys_encode_vbar_el1:            dw      011b shl 14 + 0000b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_vbar_el2:            dw      011b shl 14 + 0100b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_vbar_el3:            dw      011b shl 14 + 0110b shl 11 + 01100b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_vmpidr_el2:          dw      011b shl 14 + 0100b shl 11 + 00000b shl 7 + 00000b shl 3 + 0101b\r
+       sys_encode_vpidr_el2:           dw      011b shl 14 + 0100b shl 11 + 00000b shl 7 + 00000b shl 3 + 0000b\r
+       sys_encode_vtcr_el2:            dw      011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00001b shl 3 + 0010b\r
+       sys_encode_vttbr_el2:           dw      011b shl 14 + 0100b shl 11 + 00010b shl 7 + 00001b shl 3 + 0000b\r
+sys_encode_table_pstate:\r
+       ;msr imm                                op0           op1            crn            crm            op2\r
+       sys_pencode_daifclr:            dw      000b shl 14 + 0011b shl 11 + 00100b shl 7 + 00000b shl 3 + 0111b\r
+       sys_pencode_daifset:            dw      000b shl 14 + 0011b shl 11 + 00100b shl 7 + 00000b shl 3 + 0110b\r
+       sys_pencode_spsel:              dw      000b shl 14 + 0000b shl 11 + 00100b shl 7 + 00000b shl 3 + 0101b\r
+\r
+data_directives:\r
+       dw      data_directives_2-data_directives,(data_directives_3-data_directives_2)/(2+3)\r
+       dw      data_directives_3-data_directives,(data_directives_4-data_directives_3)/(3+3)\r
+       dw      data_directives_4-data_directives,(data_directives_end-data_directives_4)/(4+3)\r
+\r
+data_directives_2:\r
+       db      'db',1\r
+       dw      data_bytes-instruction_handler\r
+       db      'dd',8\r
+       dw      data_qwords-instruction_handler         ;ARM dwords\r
+       db      'dh',2\r
+       dw      data_words-instruction_handler          ;ARM hwords\r
+       db      'du',2\r
+       dw      data_unicode-instruction_handler\r
+       db      'dw',4\r
+       dw      data_dwords-instruction_handler         ;ARM words\r
+       db      'rb',1\r
+       dw      reserve_bytes-instruction_handler\r
+       db      'rd',8\r
+       dw      reserve_qwords-instruction_handler      ;ARM dwords\r
+       db      'rh',2\r
+       dw      reserve_words-instruction_handler       ;ARM hwords\r
+       db      'rw',4\r
+       dw      reserve_dwords-instruction_handler      ;ARM words\r
+data_directives_3:\r
+data_directives_4:\r
+       db      'file',1\r
+       dw      data_file-instruction_handler\r
+data_directives_end:\r
+\r
+instructions:\r
+       dd      instructions_1-instructions,(instructions_2-instructions_1)/(1+3)\r
+       dd      instructions_2-instructions,(instructions_3-instructions_2)/(2+3)\r
+       dd      instructions_3-instructions,(instructions_4-instructions_3)/(3+3)\r
+       dd      instructions_4-instructions,(instructions_5-instructions_4)/(4+3)\r
+       dd      instructions_5-instructions,(instructions_6-instructions_5)/(5+3)\r
+       dd      instructions_6-instructions,(instructions_7-instructions_6)/(6+3)\r
+       dd      instructions_7-instructions,(instructions_8-instructions_7)/(7+3)\r
+       dd      instructions_8-instructions,(instructions_9-instructions_8)/(8+3)\r
+       dd      instructions_9-instructions,(instructions_10-instructions_9)/(9+3)\r
+       dd      instructions_10-instructions,(instructions_11-instructions_10)/(10+3)\r
+       dd      instructions_11-instructions,(instructions_12-instructions_11)/(11+3)\r
+       dd      instructions_12-instructions,(instructions_13-instructions_12)/(12+3)\r
+       dd      instructions_13-instructions,(instructions_14-instructions_13)/(13+3)\r
+       dd      instructions_14-instructions,(instructions_15-instructions_14)/(14+3)\r
+       dd      instructions_15-instructions,(instructions_16-instructions_15)/(15+3)\r
+       dd      instructions_16-instructions,(instructions_end-instructions_16)/(16+3)\r
+instructions_1:\r
+       db      'b',0xe0\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      0\r
+instructions_2:\r
+       db      'at',0xf0\r
+       dw      ARM_instruction_at-instruction_handler\r
+       db      'bl',0xe0\r
+       dw      ARM_instruction_bl-instruction_handler\r
+       db      'br',0xf0\r
+       dw      ARM_instruction_br-instruction_handler\r
+       db      'bx',0xe0\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'dc',0xf0\r
+       dw      ARM_instruction_dc-instruction_handler\r
+       db      'hb',0xe0\r
+       dw      ARM_instruction_hb-instruction_handler\r
+       db      'ic',0xf0\r
+       dw      ARM_instruction_ic-instruction_handler\r
+       db      'if',0x00\r
+       dw      if_directive-instruction_handler\r
+       db      'it',0xf0\r
+       dw      ARM_instruction_it-instruction_handler\r
+       db      0\r
+instructions_3:\r
+       db      'abs',0xf0\r
+       dw      ARM_instruction_abs-instruction_handler\r
+       db      'adc',0xe0\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'add',0xe0\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adr',0xe0\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'and',0xe0\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asr',0xe0\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'b.n',0xe4\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      'b.w',0xe2\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      'bfc',0xe0\r
+       dw      ARM_instruction_bfc-instruction_handler\r
+       db      'bfi',0xe0\r
+       dw      ARM_instruction_bfi-instruction_handler\r
+       db      'bfm',0xf0\r
+       dw      ARM_instruction_bfm-instruction_handler\r
+       db      'bic',0xe0\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bif',0xf0\r
+       dw      ARM_instruction_bif-instruction_handler\r
+       db      'bit',0xf0\r
+       dw      ARM_instruction_bit-instruction_handler\r
+       db      'blr',0xf0\r
+       dw      ARM_instruction_blr-instruction_handler\r
+       db      'blx',0xe0\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'brk',0xf0\r
+       dw      ARM_instruction_brk-instruction_handler\r
+       db      'bsl',0xf0\r
+       dw      ARM_instruction_bsl-instruction_handler\r
+       db      'bxj',0xe0\r
+       dw      ARM_instruction_bxj-instruction_handler\r
+       db      'b~~',0x00\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      'cbz',0xf0\r
+       dw      ARM_instruction_cbz-instruction_handler\r
+       db      'cdp',0xe0\r
+       dw      ARM_instruction_cdp-instruction_handler\r
+       db      'cls',0xf0\r
+       dw      ARM_instruction_cls-instruction_handler\r
+       db      'clz',0xe0\r
+       dw      ARM_instruction_clz-instruction_handler\r
+       db      'cmf',0xe0\r
+       dw      ARM_instruction_cmf-instruction_handler\r
+       db      'cmn',0xe0\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmp',0xe0\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cnf',0xe0\r
+       dw      ARM_instruction_cnf-instruction_handler\r
+       db      'cnt',0xf0\r
+       dw      ARM_instruction_cnt-instruction_handler\r
+       db      'cps',0xf0\r
+       dw      ARM_instruction_cps-instruction_handler\r
+       db      'cpy',0xe0\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'dbg',0xe0\r
+       dw      ARM_instruction_dbg-instruction_handler\r
+       db      'dmb',0xf0\r
+       dw      ARM_instruction_dmb-instruction_handler\r
+       db      'dsb',0xf0\r
+       dw      ARM_instruction_dsb-instruction_handler\r
+       db      'dup',0xf0\r
+       dw      ARM_instruction_dup-instruction_handler\r
+       db      'end',0x00\r
+       dw      end_directive-instruction_handler\r
+       db      'eon',0xf0\r
+       dw      ARM_instruction_eon-instruction_handler\r
+       db      'eor',0xe0\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'err',0x00\r
+       dw      err_directive-instruction_handler\r
+       db      'ext',0xf0\r
+       dw      ARM_instruction_ext-instruction_handler\r
+       db      'fix',0xe0\r
+       dw      ARM_instruction_fix-instruction_handler\r
+       db      'hbl',0xe0\r
+       dw      ARM_instruction_hbl-instruction_handler\r
+       db      'hbp',0xe0\r
+       dw      ARM_instruction_hbp-instruction_handler\r
+       db      'hlt',0xe0\r
+       dw      ARM_instruction_hlt-instruction_handler\r
+       db      'hvc',0xe0\r
+       dw      ARM_instruction_hvc-instruction_handler\r
+       db      'ins',0xf0\r
+       dw      ARM_instruction_ins-instruction_handler\r
+       db      'isb',0xf0\r
+       dw      ARM_instruction_isb-instruction_handler\r
+       db      'ite',0xf0\r
+       dw      ARM_instruction_ite-instruction_handler\r
+       db      'itt',0xf0\r
+       dw      ARM_instruction_itt-instruction_handler\r
+       db      'ld1',0xf0\r
+       dw      ARM_instruction_ld1-instruction_handler\r
+       db      'ld2',0xf0\r
+       dw      ARM_instruction_ld2-instruction_handler\r
+       db      'ld3',0xf0\r
+       dw      ARM_instruction_ld3-instruction_handler\r
+       db      'ld4',0xf0\r
+       dw      ARM_instruction_ld4-instruction_handler\r
+       db      'lda',0xe0\r
+       dw      ARM_instruction_lda-instruction_handler\r
+       db      'ldc',0xe0\r
+       dw      ARM_instruction_ldc-instruction_handler\r
+       db      'ldm',0xe0\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldp',0xf0\r
+       dw      ARM_instruction_ldp-instruction_handler\r
+       db      'ldr',0xe0\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'lfm',0xe0\r
+       dw      ARM_instruction_lfm-instruction_handler\r
+       db      'lsl',0xe0\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsr',0xe0\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'mar',0xe0\r
+       dw      ARM_instruction_mar-instruction_handler\r
+       db      'mcr',0xe0\r
+       dw      ARM_instruction_mcr-instruction_handler\r
+       db      'mia',0xe0\r
+       dw      ARM_instruction_mia-instruction_handler\r
+       db      'mla',0xe0\r
+       dw      ARM_instruction_mla-instruction_handler\r
+       db      'mls',0xe0\r
+       dw      ARM_instruction_mls-instruction_handler\r
+       db      'mov',0xe0\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mra',0xe0\r
+       dw      ARM_instruction_mra-instruction_handler\r
+       db      'mrc',0xe0\r
+       dw      ARM_instruction_mrc-instruction_handler\r
+       db      'mrs',0xe0\r
+       dw      ARM_instruction_mrs-instruction_handler\r
+       db      'msr',0xe0\r
+       dw      ARM_instruction_msr-instruction_handler\r
+       db      'mul',0xe0\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvn',0xe0\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'neg',0xe0\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'ngc',0xf0\r
+       dw      ARM_instruction_ngc-instruction_handler\r
+       db      'nop',0xe0\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'not',0xf0\r
+       dw      ARM_instruction_not-instruction_handler\r
+       db      'org',0x00\r
+       dw      ARM_org_directive-instruction_handler\r
+       db      'orn',0xe0\r
+       dw      ARM_instruction_orn-instruction_handler\r
+       db      'orr',0xe0\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'pld',0xe0\r
+       dw      ARM_instruction_pld-instruction_handler\r
+       db      'pli',0xe0\r
+       dw      ARM_instruction_pli-instruction_handler\r
+       db      'pop',0xe0\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'ret',0xf0\r
+       dw      ARM_instruction_ret-instruction_handler\r
+       db      'rev',0xe0\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rfc',0xe0\r
+       dw      ARM_instruction_rfc-instruction_handler\r
+       db      'rfe',0xf0\r
+       dw      ARM_instruction_rfe-instruction_handler\r
+       db      'rfs',0xe0\r
+       dw      ARM_instruction_rfs-instruction_handler\r
+       db      'ror',0xe0\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rrx',0xe0\r
+       dw      ARM_instruction_rrx-instruction_handler\r
+       db      'rsb',0xe0\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsc',0xe0\r
+       dw      ARM_instruction_rsc-instruction_handler\r
+       db      'sbc',0xe0\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sel',0xe0\r
+       dw      ARM_instruction_sel-instruction_handler\r
+       db      'sev',0xe0\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sfm',0xe0\r
+       dw      ARM_instruction_sfm-instruction_handler\r
+       db      'shl',0xf0\r
+       dw      ARM_instruction_shl-instruction_handler\r
+       db      'sli',0xf0\r
+       dw      ARM_instruction_sli-instruction_handler\r
+       db      'smc',0xe0\r
+       dw      ARM_instruction_smc-instruction_handler\r
+       db      'smi',0xe0\r
+       dw      ARM_instruction_smi-instruction_handler\r
+       db      'sri',0xf0\r
+       dw      ARM_instruction_sri-instruction_handler\r
+       db      'srs',0xf0\r
+       dw      ARM_instruction_srs-instruction_handler\r
+       db      'st1',0xf0\r
+       dw      ARM_instruction_st1-instruction_handler\r
+       db      'st2',0xf0\r
+       dw      ARM_instruction_st2-instruction_handler\r
+       db      'st3',0xf0\r
+       dw      ARM_instruction_st3-instruction_handler\r
+       db      'st4',0xf0\r
+       dw      ARM_instruction_st4-instruction_handler\r
+       db      'stc',0xe0\r
+       dw      ARM_instruction_stc-instruction_handler\r
+       db      'stl',0xe0\r
+       dw      ARM_instruction_stl-instruction_handler\r
+       db      'stm',0xe0\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'stp',0xf0\r
+       dw      ARM_instruction_stp-instruction_handler\r
+       db      'str',0xe0\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'sub',0xe0\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'svc',0xe0\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'swi',0xe0\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'swp',0xe0\r
+       dw      ARM_instruction_swp-instruction_handler\r
+       db      'sys',0xf0\r
+       dw      ARM_instruction_sys-instruction_handler\r
+       db      'tbb',0xe0\r
+       dw      ARM_instruction_tbb-instruction_handler\r
+       db      'tbh',0xe0\r
+       dw      ARM_instruction_tbh-instruction_handler\r
+       db      'tbl',0xf0\r
+       dw      ARM_instruction_tbl-instruction_handler\r
+       db      'tbx',0xf0\r
+       dw      ARM_instruction_tbx-instruction_handler\r
+       db      'tbz',0xf0\r
+       dw      ARM_instruction_tbz-instruction_handler\r
+       db      'teq',0xe0\r
+       dw      ARM_instruction_teq-instruction_handler\r
+       db      'tst',0xe0\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'und',0xe0\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'wfc',0xe0\r
+       dw      ARM_instruction_wfc-instruction_handler\r
+       db      'wfe',0xe0\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfi',0xe0\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wfs',0xe0\r
+       dw      ARM_instruction_wfs-instruction_handler\r
+       db      'wor',0xe0\r
+       dw      ARM_instruction_wor-instruction_handler\r
+       db      'xtn',0xf0\r
+       dw      ARM_instruction_xtn-instruction_handler\r
+       db      0\r
+instructions_4:\r
+       db      'absd',0xe0\r
+       dw      ARM_instruction_absd-instruction_handler\r
+       db      'abse',0xe0\r
+       dw      ARM_instruction_abse-instruction_handler\r
+       db      'abss',0xe0\r
+       dw      ARM_instruction_abss-instruction_handler\r
+       db      'acsd',0xe0\r
+       dw      ARM_instruction_acsd-instruction_handler\r
+       db      'acse',0xe0\r
+       dw      ARM_instruction_acse-instruction_handler\r
+       db      'acss',0xe0\r
+       dw      ARM_instruction_acss-instruction_handler\r
+       db      'adcs',0xe1\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'addp',0xf0\r
+       dw      ARM_instruction_addp-instruction_handler\r
+       db      'adds',0xe1\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'addv',0xf0\r
+       dw      ARM_instruction_addv-instruction_handler\r
+       db      'addw',0xe0\r
+       dw      ARM_instruction_addw-instruction_handler\r
+       db      'adfd',0xe0\r
+       dw      ARM_instruction_adfd-instruction_handler\r
+       db      'adfe',0xe0\r
+       dw      ARM_instruction_adfe-instruction_handler\r
+       db      'adfs',0xe0\r
+       dw      ARM_instruction_adfs-instruction_handler\r
+       db      'adrp',0xf0\r
+       dw      ARM_instruction_adrp-instruction_handler\r
+       db      'aesd',0xf0\r
+       dw      ARM_instruction_aesd-instruction_handler\r
+       db      'aese',0xf0\r
+       dw      ARM_instruction_aese-instruction_handler\r
+       db      'ands',0xe1\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asnd',0xe0\r
+       dw      ARM_instruction_asnd-instruction_handler\r
+       db      'asne',0xe0\r
+       dw      ARM_instruction_asne-instruction_handler\r
+       db      'asns',0xe0\r
+       dw      ARM_instruction_asns-instruction_handler\r
+       db      'asrs',0xe1\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asrv',0xf0\r
+       dw      ARM_instruction_asrv-instruction_handler\r
+       db      'atnd',0xe0\r
+       dw      ARM_instruction_atnd-instruction_handler\r
+       db      'atne',0xe0\r
+       dw      ARM_instruction_atne-instruction_handler\r
+       db      'atns',0xe0\r
+       dw      ARM_instruction_atns-instruction_handler\r
+       db      'b.al',0xf0\r
+       dw      ARM_instruction_b.al-instruction_handler\r
+       db      'b.cc',0xf0\r
+       dw      ARM_instruction_b.cc-instruction_handler\r
+       db      'b.cs',0xf0\r
+       dw      ARM_instruction_b.cs-instruction_handler\r
+       db      'b.eq',0xf0\r
+       dw      ARM_instruction_b.eq-instruction_handler\r
+       db      'b.ge',0xf0\r
+       dw      ARM_instruction_b.ge-instruction_handler\r
+       db      'b.gt',0xf0\r
+       dw      ARM_instruction_b.gt-instruction_handler\r
+       db      'b.hi',0xf0\r
+       dw      ARM_instruction_b.hi-instruction_handler\r
+       db      'b.hs',0xf0\r
+       dw      ARM_instruction_b.hs-instruction_handler\r
+       db      'b.le',0xf0\r
+       dw      ARM_instruction_b.le-instruction_handler\r
+       db      'b.lo',0xf0\r
+       dw      ARM_instruction_b.lo-instruction_handler\r
+       db      'b.ls',0xf0\r
+       dw      ARM_instruction_b.ls-instruction_handler\r
+       db      'b.lt',0xf0\r
+       dw      ARM_instruction_b.lt-instruction_handler\r
+       db      'b.mi',0xf0\r
+       dw      ARM_instruction_b.mi-instruction_handler\r
+       db      'b.ne',0xf0\r
+       dw      ARM_instruction_b.ne-instruction_handler\r
+       db      'b.nv',0xf0\r
+       dw      ARM_instruction_b.nv-instruction_handler\r
+       db      'b.pl',0xf0\r
+       dw      ARM_instruction_b.pl-instruction_handler\r
+       db      'b.vc',0xf0\r
+       dw      ARM_instruction_b.vc-instruction_handler\r
+       db      'b.vs',0xf0\r
+       dw      ARM_instruction_b.vs-instruction_handler\r
+       db      'bics',0xe1\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bkpt',0xe0\r
+       dw      ARM_instruction_bkpt-instruction_handler\r
+       db      'bl~~',0x00\r
+       dw      ARM_instruction_bl-instruction_handler\r
+       db      'bx.n',0xe4\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'bx.w',0xe2\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'bx~~',0x00\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'cbnz',0xf0\r
+       dw      ARM_instruction_cbnz-instruction_handler\r
+       db      'ccmn',0xf0\r
+       dw      ARM_instruction_ccmn-instruction_handler\r
+       db      'ccmp',0xf0\r
+       dw      ARM_instruction_ccmp-instruction_handler\r
+       db      'cdp2',0xe0\r
+       dw      ARM_instruction_cdp2-instruction_handler\r
+       db      'chka',0xe0\r
+       dw      ARM_instruction_chka-instruction_handler\r
+       db      'cinc',0xf0\r
+       dw      ARM_instruction_cinc-instruction_handler\r
+       db      'cinv',0xf0\r
+       dw      ARM_instruction_cinv-instruction_handler\r
+       db      'cmeq',0xf0\r
+       dw      ARM_instruction_cmeq-instruction_handler\r
+       db      'cmfe',0xe0\r
+       dw      ARM_instruction_cmfe-instruction_handler\r
+       db      'cmge',0xf0\r
+       dw      ARM_instruction_cmge-instruction_handler\r
+       db      'cmgt',0xf0\r
+       dw      ARM_instruction_cmgt-instruction_handler\r
+       db      'cmhi',0xf0\r
+       dw      ARM_instruction_cmhi-instruction_handler\r
+       db      'cmhs',0xf0\r
+       dw      ARM_instruction_cmhs-instruction_handler\r
+       db      'cmle',0xf0\r
+       dw      ARM_instruction_cmle-instruction_handler\r
+       db      'cmlt',0xf0\r
+       dw      ARM_instruction_cmlt-instruction_handler\r
+       db      'cmnp',0xe0\r
+       dw      ARM_instruction_cmnp-instruction_handler\r
+       db      'cmpp',0xe0\r
+       dw      ARM_instruction_cmpp-instruction_handler\r
+       db      'cneg',0xf0\r
+       dw      ARM_instruction_cneg-instruction_handler\r
+       db      'cnfe',0xe0\r
+       dw      ARM_instruction_cnfe-instruction_handler\r
+       db      'cosd',0xe0\r
+       dw      ARM_instruction_cosd-instruction_handler\r
+       db      'cose',0xe0\r
+       dw      ARM_instruction_cose-instruction_handler\r
+       db      'coss',0xe0\r
+       dw      ARM_instruction_coss-instruction_handler\r
+       db      'csel',0xf0\r
+       dw      ARM_instruction_csel-instruction_handler\r
+       db      'cset',0xf0\r
+       dw      ARM_instruction_cset-instruction_handler\r
+       db      'data',0x00\r
+       dw      data_directive-instruction_handler\r
+       db      'drps',0xf0\r
+       dw      ARM_instruction_drps-instruction_handler\r
+       db      'dvfd',0xe0\r
+       dw      ARM_instruction_dvfd-instruction_handler\r
+       db      'dvfe',0xe0\r
+       dw      ARM_instruction_dvfe-instruction_handler\r
+       db      'dvfs',0xe0\r
+       dw      ARM_instruction_dvfs-instruction_handler\r
+       db      'else',0x00\r
+       dw      else_directive-instruction_handler\r
+       db      'eors',0xe1\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eret',0xe0\r
+       dw      ARM_instruction_eret-instruction_handler\r
+       db      'expd',0xe0\r
+       dw      ARM_instruction_expd-instruction_handler\r
+       db      'expe',0xe0\r
+       dw      ARM_instruction_expe-instruction_handler\r
+       db      'exps',0xe0\r
+       dw      ARM_instruction_exps-instruction_handler\r
+       db      'extr',0xf0\r
+       dw      ARM_instruction_extr-instruction_handler\r
+       db      'fabd',0xf0\r
+       dw      ARM_instruction_fabd-instruction_handler\r
+       db      'fabs',0xf0\r
+       dw      ARM_instruction_fabs-instruction_handler\r
+       db      'fadd',0xf0\r
+       dw      ARM_instruction_fadd-instruction_handler\r
+       db      'fcmp',0xf0\r
+       dw      ARM_instruction_fcmp-instruction_handler\r
+       db      'fcvt',0xf0\r
+       dw      ARM_instruction_fcvt-instruction_handler\r
+       db      'fdiv',0xf0\r
+       dw      ARM_instruction_fdiv-instruction_handler\r
+       db      'fdvd',0xe0\r
+       dw      ARM_instruction_fdvd-instruction_handler\r
+       db      'fdve',0xe0\r
+       dw      ARM_instruction_fdve-instruction_handler\r
+       db      'fdvs',0xe0\r
+       dw      ARM_instruction_fdvs-instruction_handler\r
+       db      'fixm',0xe0\r
+       dw      ARM_instruction_fixm-instruction_handler\r
+       db      'fixp',0xe0\r
+       dw      ARM_instruction_fixp-instruction_handler\r
+       db      'fixz',0xe0\r
+       dw      ARM_instruction_fixz-instruction_handler\r
+       db      'fldd',0xe0\r
+       dw      ARM_instruction_fldd-instruction_handler\r
+       db      'flds',0xe0\r
+       dw      ARM_instruction_flds-instruction_handler\r
+       db      'fltd',0xe0\r
+       dw      ARM_instruction_fltd-instruction_handler\r
+       db      'flte',0xe0\r
+       dw      ARM_instruction_flte-instruction_handler\r
+       db      'flts',0xe0\r
+       dw      ARM_instruction_flts-instruction_handler\r
+       db      'fmax',0xf0\r
+       dw      ARM_instruction_fmax-instruction_handler\r
+       db      'fmin',0xf0\r
+       dw      ARM_instruction_fmin-instruction_handler\r
+       db      'fmla',0xf0\r
+       dw      ARM_instruction_fmla-instruction_handler\r
+       db      'fmld',0xe0\r
+       dw      ARM_instruction_fmld-instruction_handler\r
+       db      'fmle',0xe0\r
+       dw      ARM_instruction_fmle-instruction_handler\r
+       db      'fmls',0xe0\r
+       dw      ARM_instruction_fmls-instruction_handler\r
+       db      'fmov',0xf0\r
+       dw      ARM_instruction_fmov-instruction_handler\r
+       db      'fmrs',0xe0\r
+       dw      ARM_instruction_fmrs-instruction_handler\r
+       db      'fmrx',0xe0\r
+       dw      ARM_instruction_fmrx-instruction_handler\r
+       db      'fmsr',0xe0\r
+       dw      ARM_instruction_fmsr-instruction_handler\r
+       db      'fmul',0xf0\r
+       dw      ARM_instruction_fmul-instruction_handler\r
+       db      'fmxr',0xe0\r
+       dw      ARM_instruction_fmxr-instruction_handler\r
+       db      'fneg',0xf0\r
+       dw      ARM_instruction_fneg-instruction_handler\r
+       db      'frdd',0xe0\r
+       dw      ARM_instruction_frdd-instruction_handler\r
+       db      'frde',0xe0\r
+       dw      ARM_instruction_frde-instruction_handler\r
+       db      'frds',0xe0\r
+       dw      ARM_instruction_frds-instruction_handler\r
+       db      'fstd',0xe0\r
+       dw      ARM_instruction_fstd-instruction_handler\r
+       db      'fsts',0xe0\r
+       dw      ARM_instruction_fsts-instruction_handler\r
+       db      'fsub',0xf0\r
+       dw      ARM_instruction_fsub-instruction_handler\r
+       db      'hblp',0xe0\r
+       dw      ARM_instruction_hblp-instruction_handler\r
+       db      'hb~~',0x00\r
+       dw      ARM_instruction_hb-instruction_handler\r
+       db      'heap',0x00\r
+       dw      heap_directive-instruction_handler\r
+       db      'hint',0xf0\r
+       dw      ARM_instruction_hint-instruction_handler\r
+       db      'itee',0xf0\r
+       dw      ARM_instruction_itee-instruction_handler\r
+       db      'itet',0xf0\r
+       dw      ARM_instruction_itet-instruction_handler\r
+       db      'itte',0xf0\r
+       dw      ARM_instruction_itte-instruction_handler\r
+       db      'ittt',0xf0\r
+       dw      ARM_instruction_ittt-instruction_handler\r
+       db      'ld1r',0xf0\r
+       dw      ARM_instruction_ld1r-instruction_handler\r
+       db      'ld2r',0xf0\r
+       dw      ARM_instruction_ld2r-instruction_handler\r
+       db      'ld3r',0xf0\r
+       dw      ARM_instruction_ld3r-instruction_handler\r
+       db      'ld4r',0xf0\r
+       dw      ARM_instruction_ld4r-instruction_handler\r
+       db      'ldab',0xe0\r
+       dw      ARM_instruction_ldab-instruction_handler\r
+       db      'ldah',0xe0\r
+       dw      ARM_instruction_ldah-instruction_handler\r
+       db      'ldar',0xf0\r
+       dw      ARM_instruction_ldar-instruction_handler\r
+       db      'ldc2',0xe0\r
+       dw      ARM_instruction_ldc2-instruction_handler\r
+       db      'ldcl',0xe0\r
+       dw      ARM_instruction_ldcl-instruction_handler\r
+       db      'ldfd',0xe0\r
+       dw      ARM_instruction_ldfd-instruction_handler\r
+       db      'ldfe',0xe0\r
+       dw      ARM_instruction_ldfe-instruction_handler\r
+       db      'ldfp',0xe0\r
+       dw      ARM_instruction_ldfp-instruction_handler\r
+       db      'ldfs',0xe0\r
+       dw      ARM_instruction_ldfs-instruction_handler\r
+       db      'ldnp',0xf0\r
+       dw      ARM_instruction_ldnp-instruction_handler\r
+       db      'ldrb',0xe0\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrd',0xe0\r
+       dw      ARM_instruction_ldrd-instruction_handler\r
+       db      'ldrh',0xe0\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrt',0xe0\r
+       dw      ARM_instruction_ldrt-instruction_handler\r
+       db      'ldtr',0xf0\r
+       dw      ARM_instruction_ldtr-instruction_handler\r
+       db      'ldur',0xf0\r
+       dw      ARM_instruction_ldur-instruction_handler\r
+       db      'ldxp',0xf0\r
+       dw      ARM_instruction_ldxp-instruction_handler\r
+       db      'ldxr',0xf0\r
+       dw      ARM_instruction_ldxr-instruction_handler\r
+       db      'lgnd',0xe0\r
+       dw      ARM_instruction_lgnd-instruction_handler\r
+       db      'lgne',0xe0\r
+       dw      ARM_instruction_lgne-instruction_handler\r
+       db      'lgns',0xe0\r
+       dw      ARM_instruction_lgns-instruction_handler\r
+       db      'load',0x00\r
+       dw      load_directive-instruction_handler\r
+       db      'logd',0xe0\r
+       dw      ARM_instruction_logd-instruction_handler\r
+       db      'loge',0xe0\r
+       dw      ARM_instruction_loge-instruction_handler\r
+       db      'logs',0xe0\r
+       dw      ARM_instruction_logs-instruction_handler\r
+       db      'lsls',0xe1\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lslv',0xf0\r
+       dw      ARM_instruction_lslv-instruction_handler\r
+       db      'lsrs',0xe1\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsrv',0xf0\r
+       dw      ARM_instruction_lsrv-instruction_handler\r
+       db      'madd',0xf0\r
+       dw      ARM_instruction_madd-instruction_handler\r
+       db      'mcr2',0xe0\r
+       dw      ARM_instruction_mcr2-instruction_handler\r
+       db      'mcrr',0xe0\r
+       dw      ARM_instruction_mcrr-instruction_handler\r
+       db      'mlas',0xe1\r
+       dw      ARM_instruction_mla-instruction_handler\r
+       db      'mneg',0xf0\r
+       dw      ARM_instruction_mneg-instruction_handler\r
+       db      'mnfd',0xe0\r
+       dw      ARM_instruction_mnfd-instruction_handler\r
+       db      'mnfe',0xe0\r
+       dw      ARM_instruction_mnfe-instruction_handler\r
+       db      'mnfs',0xe0\r
+       dw      ARM_instruction_mnfs-instruction_handler\r
+       db      'movi',0xf0\r
+       dw      ARM_instruction_movi-instruction_handler\r
+       db      'movk',0xf0\r
+       dw      ARM_instruction_movk-instruction_handler\r
+       db      'movn',0xf0\r
+       dw      ARM_instruction_movn-instruction_handler\r
+       db      'movs',0xe1\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'movt',0xe0\r
+       dw      ARM_instruction_movt-instruction_handler\r
+       db      'movw',0xe0\r
+       dw      ARM_instruction_movw-instruction_handler\r
+       db      'movz',0xf0\r
+       dw      ARM_instruction_movz-instruction_handler\r
+       db      'mrc2',0xe0\r
+       dw      ARM_instruction_mrc2-instruction_handler\r
+       db      'mrrc',0xe0\r
+       dw      ARM_instruction_mrrc-instruction_handler\r
+       db      'msub',0xf0\r
+       dw      ARM_instruction_msub-instruction_handler\r
+       db      'mufd',0xe0\r
+       dw      ARM_instruction_mufd-instruction_handler\r
+       db      'mufe',0xe0\r
+       dw      ARM_instruction_mufe-instruction_handler\r
+       db      'mufs',0xe0\r
+       dw      ARM_instruction_mufs-instruction_handler\r
+       db      'muls',0xe1\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvfd',0xe0\r
+       dw      ARM_instruction_mvfd-instruction_handler\r
+       db      'mvfe',0xe0\r
+       dw      ARM_instruction_mvfe-instruction_handler\r
+       db      'mvfs',0xe0\r
+       dw      ARM_instruction_mvfs-instruction_handler\r
+       db      'mvni',0xf0\r
+       dw      ARM_instruction_mvni-instruction_handler\r
+       db      'mvns',0xe1\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'negs',0xe1\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'ngcs',0xf1\r
+       dw      ARM_instruction_ngc-instruction_handler\r
+       db      'nrmd',0xe0\r
+       dw      ARM_instruction_nrmd-instruction_handler\r
+       db      'nrme',0xe0\r
+       dw      ARM_instruction_nrme-instruction_handler\r
+       db      'nrms',0xe0\r
+       dw      ARM_instruction_nrms-instruction_handler\r
+       db      'orns',0xe1\r
+       dw      ARM_instruction_orn-instruction_handler\r
+       db      'orrs',0xe1\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'pldw',0xe0\r
+       dw      ARM_instruction_pldw-instruction_handler\r
+       db      'pmul',0xf0\r
+       dw      ARM_instruction_pmul-instruction_handler\r
+       db      'pold',0xe0\r
+       dw      ARM_instruction_pold-instruction_handler\r
+       db      'pole',0xe0\r
+       dw      ARM_instruction_pole-instruction_handler\r
+       db      'pols',0xe0\r
+       dw      ARM_instruction_pols-instruction_handler\r
+       db      'powd',0xe0\r
+       dw      ARM_instruction_powd-instruction_handler\r
+       db      'powe',0xe0\r
+       dw      ARM_instruction_powe-instruction_handler\r
+       db      'pows',0xe0\r
+       dw      ARM_instruction_pows-instruction_handler\r
+       db      'prfm',0xf0\r
+       dw      ARM_instruction_prfm-instruction_handler\r
+       db      'push',0xe0\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'qadd',0xe0\r
+       dw      ARM_instruction_qadd-instruction_handler\r
+       db      'qasx',0xe0\r
+       dw      ARM_instruction_qasx-instruction_handler\r
+       db      'qsax',0xe0\r
+       dw      ARM_instruction_qsax-instruction_handler\r
+       db      'qsub',0xe0\r
+       dw      ARM_instruction_qsub-instruction_handler\r
+       db      'rbit',0xe0\r
+       dw      ARM_instruction_rbit-instruction_handler\r
+       db      'rdfd',0xe0\r
+       dw      ARM_instruction_rdfd-instruction_handler\r
+       db      'rdfe',0xe0\r
+       dw      ARM_instruction_rdfe-instruction_handler\r
+       db      'rdfs',0xe0\r
+       dw      ARM_instruction_rdfs-instruction_handler\r
+       db      'rmfd',0xe0\r
+       dw      ARM_instruction_rmfd-instruction_handler\r
+       db      'rmfe',0xe0\r
+       dw      ARM_instruction_rmfe-instruction_handler\r
+       db      'rmfs',0xe0\r
+       dw      ARM_instruction_rmfs-instruction_handler\r
+       db      'rndd',0xe0\r
+       dw      ARM_instruction_rndd-instruction_handler\r
+       db      'rnde',0xe0\r
+       dw      ARM_instruction_rnde-instruction_handler\r
+       db      'rnds',0xe0\r
+       dw      ARM_instruction_rnds-instruction_handler\r
+       db      'rors',0xe1\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rorv',0xf0\r
+       dw      ARM_instruction_rorv-instruction_handler\r
+       db      'rpwd',0xe0\r
+       dw      ARM_instruction_rpwd-instruction_handler\r
+       db      'rpwe',0xe0\r
+       dw      ARM_instruction_rpwe-instruction_handler\r
+       db      'rpws',0xe0\r
+       dw      ARM_instruction_rpws-instruction_handler\r
+       db      'rrxs',0xe1\r
+       dw      ARM_instruction_rrx-instruction_handler\r
+       db      'rsbs',0xe1\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rscs',0xe1\r
+       dw      ARM_instruction_rsc-instruction_handler\r
+       db      'rsfd',0xe0\r
+       dw      ARM_instruction_rsfd-instruction_handler\r
+       db      'rsfe',0xe0\r
+       dw      ARM_instruction_rsfe-instruction_handler\r
+       db      'rsfs',0xe0\r
+       dw      ARM_instruction_rsfs-instruction_handler\r
+       db      'saba',0xf0\r
+       dw      ARM_instruction_saba-instruction_handler\r
+       db      'sabd',0xf0\r
+       dw      ARM_instruction_sabd-instruction_handler\r
+       db      'sasx',0xe0\r
+       dw      ARM_instruction_sasx-instruction_handler\r
+       db      'sbcs',0xe1\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbfm',0xf0\r
+       dw      ARM_instruction_sbfm-instruction_handler\r
+       db      'sbfx',0xe0\r
+       dw      ARM_instruction_sbfx-instruction_handler\r
+       db      'sdiv',0xe0\r
+       dw      ARM_instruction_sdiv-instruction_handler\r
+       db      'sevl',0xe0\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'shll',0xf0\r
+       dw      ARM_instruction_shll-instruction_handler\r
+       db      'shrn',0xf0\r
+       dw      ARM_instruction_shrn-instruction_handler\r
+       db      'sind',0xe0\r
+       dw      ARM_instruction_sind-instruction_handler\r
+       db      'sine',0xe0\r
+       dw      ARM_instruction_sine-instruction_handler\r
+       db      'sins',0xe0\r
+       dw      ARM_instruction_sins-instruction_handler\r
+       db      'smax',0xf0\r
+       dw      ARM_instruction_smax-instruction_handler\r
+       db      'smin',0xf0\r
+       dw      ARM_instruction_smin-instruction_handler\r
+       db      'smov',0xf0\r
+       dw      ARM_instruction_smov-instruction_handler\r
+       db      'sqtd',0xe0\r
+       dw      ARM_instruction_sqtd-instruction_handler\r
+       db      'sqte',0xe0\r
+       dw      ARM_instruction_sqte-instruction_handler\r
+       db      'sqts',0xe0\r
+       dw      ARM_instruction_sqts-instruction_handler\r
+       db      'ssat',0xe0\r
+       dw      ARM_instruction_ssat-instruction_handler\r
+       db      'ssax',0xe0\r
+       dw      ARM_instruction_ssax-instruction_handler\r
+       db      'sshl',0xf0\r
+       dw      ARM_instruction_sshl-instruction_handler\r
+       db      'sshr',0xf0\r
+       dw      ARM_instruction_sshr-instruction_handler\r
+       db      'ssra',0xf0\r
+       dw      ARM_instruction_ssra-instruction_handler\r
+       db      'stc2',0xe0\r
+       dw      ARM_instruction_stc2-instruction_handler\r
+       db      'stcl',0xe0\r
+       dw      ARM_instruction_stcl-instruction_handler\r
+       db      'stfd',0xe0\r
+       dw      ARM_instruction_stfd-instruction_handler\r
+       db      'stfe',0xe0\r
+       dw      ARM_instruction_stfe-instruction_handler\r
+       db      'stfp',0xe0\r
+       dw      ARM_instruction_stfp-instruction_handler\r
+       db      'stfs',0xe0\r
+       dw      ARM_instruction_stfs-instruction_handler\r
+       db      'stlb',0xe0\r
+       dw      ARM_instruction_stlb-instruction_handler\r
+       db      'stlh',0xe0\r
+       dw      ARM_instruction_stlh-instruction_handler\r
+       db      'stlr',0xf0\r
+       dw      ARM_instruction_stlr-instruction_handler\r
+       db      'stnp',0xf0\r
+       dw      ARM_instruction_stnp-instruction_handler\r
+       db      'strb',0xe0\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strd',0xe0\r
+       dw      ARM_instruction_strd-instruction_handler\r
+       db      'strh',0xe0\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'strt',0xe0\r
+       dw      ARM_instruction_strt-instruction_handler\r
+       db      'sttr',0xf0\r
+       dw      ARM_instruction_sttr-instruction_handler\r
+       db      'stur',0xf0\r
+       dw      ARM_instruction_stur-instruction_handler\r
+       db      'stxp',0xf0\r
+       dw      ARM_instruction_stxp-instruction_handler\r
+       db      'stxr',0xf0\r
+       dw      ARM_instruction_stxr-instruction_handler\r
+       db      'subs',0xe1\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subw',0xe0\r
+       dw      ARM_instruction_subw-instruction_handler\r
+       db      'sufd',0xe0\r
+       dw      ARM_instruction_sufd-instruction_handler\r
+       db      'sufe',0xe0\r
+       dw      ARM_instruction_sufe-instruction_handler\r
+       db      'sufs',0xe0\r
+       dw      ARM_instruction_sufs-instruction_handler\r
+       db      'swpb',0xe0\r
+       dw      ARM_instruction_swpb-instruction_handler\r
+       db      'sxtb',0xe0\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxth',0xe0\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'sxtl',0xf0\r
+       dw      ARM_instruction_sxtl-instruction_handler\r
+       db      'sxtw',0xf0\r
+       dw      ARM_instruction_sxtw-instruction_handler\r
+       db      'sysl',0xf0\r
+       dw      ARM_instruction_sysl-instruction_handler\r
+       db      'tand',0xe0\r
+       dw      ARM_instruction_tand-instruction_handler\r
+       db      'tane',0xe0\r
+       dw      ARM_instruction_tane-instruction_handler\r
+       db      'tans',0xe0\r
+       dw      ARM_instruction_tans-instruction_handler\r
+       db      'tbnz',0xf0\r
+       dw      ARM_instruction_tbnz-instruction_handler\r
+       db      'teqp',0xe0\r
+       dw      ARM_instruction_teqp-instruction_handler\r
+       db      'tlbi',0xf0\r
+       dw      ARM_instruction_tlbi-instruction_handler\r
+       db      'tmcr',0xe0\r
+       dw      ARM_instruction_tmcr-instruction_handler\r
+       db      'tmia',0xe0\r
+       dw      ARM_instruction_tmia-instruction_handler\r
+       db      'tmrc',0xe0\r
+       dw      ARM_instruction_tmrc-instruction_handler\r
+       db      'trn1',0xf0\r
+       dw      ARM_instruction_trn1-instruction_handler\r
+       db      'trn2',0xf0\r
+       dw      ARM_instruction_trn2-instruction_handler\r
+       db      'tstp',0xe0\r
+       dw      ARM_instruction_tstp-instruction_handler\r
+       db      'uaba',0xf0\r
+       dw      ARM_instruction_uaba-instruction_handler\r
+       db      'uabd',0xf0\r
+       dw      ARM_instruction_uabd-instruction_handler\r
+       db      'uasx',0xe0\r
+       dw      ARM_instruction_uasx-instruction_handler\r
+       db      'ubfm',0xf0\r
+       dw      ARM_instruction_ubfm-instruction_handler\r
+       db      'ubfx',0xe0\r
+       dw      ARM_instruction_ubfx-instruction_handler\r
+       db      'udiv',0xe0\r
+       dw      ARM_instruction_udiv-instruction_handler\r
+       db      'umax',0xf0\r
+       dw      ARM_instruction_umax-instruction_handler\r
+       db      'umin',0xf0\r
+       dw      ARM_instruction_umin-instruction_handler\r
+       db      'umov',0xf0\r
+       dw      ARM_instruction_umov-instruction_handler\r
+       db      'urdd',0xe0\r
+       dw      ARM_instruction_urdd-instruction_handler\r
+       db      'urde',0xe0\r
+       dw      ARM_instruction_urde-instruction_handler\r
+       db      'urds',0xe0\r
+       dw      ARM_instruction_urds-instruction_handler\r
+       db      'usat',0xe0\r
+       dw      ARM_instruction_usat-instruction_handler\r
+       db      'usax',0xe0\r
+       dw      ARM_instruction_usax-instruction_handler\r
+       db      'ushl',0xf0\r
+       dw      ARM_instruction_ushl-instruction_handler\r
+       db      'ushr',0xf0\r
+       dw      ARM_instruction_ushr-instruction_handler\r
+       db      'usra',0xf0\r
+       dw      ARM_instruction_usra-instruction_handler\r
+       db      'uxtb',0xe0\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxth',0xe0\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'uxtl',0xf0\r
+       dw      ARM_instruction_uxtl-instruction_handler\r
+       db      'uzp1',0xf0\r
+       dw      ARM_instruction_uzp1-instruction_handler\r
+       db      'uzp2',0xf0\r
+       dw      ARM_instruction_uzp2-instruction_handler\r
+       db      'vand',0xe0\r
+       dw      ARM_instruction_vand-instruction_handler\r
+       db      'vbic',0xe0\r
+       dw      ARM_instruction_vbic-instruction_handler\r
+       db      'vbif',0xe0\r
+       dw      ARM_instruction_vbif-instruction_handler\r
+       db      'vbit',0xe0\r
+       dw      ARM_instruction_vbit-instruction_handler\r
+       db      'vbsl',0xe0\r
+       dw      ARM_instruction_vbsl-instruction_handler\r
+       db      'veor',0xe0\r
+       dw      ARM_instruction_veor-instruction_handler\r
+       db      'vldm',0xe0\r
+       dw      ARM_instruction_vldm-instruction_handler\r
+       db      'vldr',0xe0\r
+       dw      ARM_instruction_vldr-instruction_handler\r
+       db      'vmov',0xe0\r
+       dw      ARM_instruction_vmov-instruction_handler\r
+       db      'vmrs',0xe0\r
+       dw      ARM_instruction_vmrs-instruction_handler\r
+       db      'vmsr',0xe0\r
+       dw      ARM_instruction_vmsr-instruction_handler\r
+       db      'vmvn',0xe0\r
+       dw      ARM_instruction_vmvn-instruction_handler\r
+       db      'vorn',0xe0\r
+       dw      ARM_instruction_vorn-instruction_handler\r
+       db      'vorr',0xe0\r
+       dw      ARM_instruction_vorr-instruction_handler\r
+       db      'vpop',0xe0\r
+       dw      ARM_instruction_vpop-instruction_handler\r
+       db      'vstm',0xe0\r
+       dw      ARM_instruction_vstm-instruction_handler\r
+       db      'vstr',0xe0\r
+       dw      ARM_instruction_vstr-instruction_handler\r
+       db      'vswp',0xe0\r
+       dw      ARM_instruction_vswp-instruction_handler\r
+       db      'wand',0xe0\r
+       dw      ARM_instruction_wand-instruction_handler\r
+       db      'wmov',0xe0\r
+       dw      ARM_instruction_wmov-instruction_handler\r
+       db      'wxor',0xe0\r
+       dw      ARM_instruction_wxor-instruction_handler\r
+       db      'xtn2',0xf0\r
+       dw      ARM_instruction_xtn2-instruction_handler\r
+       db      'zip1',0xf0\r
+       dw      ARM_instruction_zip1-instruction_handler\r
+       db      'zip2',0xf0\r
+       dw      ARM_instruction_zip2-instruction_handler\r
+       db      0\r
+instructions_5:\r
+       db      'absdm',0xe0\r
+       dw      ARM_instruction_absdm-instruction_handler\r
+       db      'absdp',0xe0\r
+       dw      ARM_instruction_absdp-instruction_handler\r
+       db      'absdz',0xe0\r
+       dw      ARM_instruction_absdz-instruction_handler\r
+       db      'absem',0xe0\r
+       dw      ARM_instruction_absem-instruction_handler\r
+       db      'absep',0xe0\r
+       dw      ARM_instruction_absep-instruction_handler\r
+       db      'absez',0xe0\r
+       dw      ARM_instruction_absez-instruction_handler\r
+       db      'abssm',0xe0\r
+       dw      ARM_instruction_abssm-instruction_handler\r
+       db      'abssp',0xe0\r
+       dw      ARM_instruction_abssp-instruction_handler\r
+       db      'abssz',0xe0\r
+       dw      ARM_instruction_abssz-instruction_handler\r
+       db      'acsdm',0xe0\r
+       dw      ARM_instruction_acsdm-instruction_handler\r
+       db      'acsdp',0xe0\r
+       dw      ARM_instruction_acsdp-instruction_handler\r
+       db      'acsdz',0xe0\r
+       dw      ARM_instruction_acsdz-instruction_handler\r
+       db      'acsem',0xe0\r
+       dw      ARM_instruction_acsem-instruction_handler\r
+       db      'acsep',0xe0\r
+       dw      ARM_instruction_acsep-instruction_handler\r
+       db      'acsez',0xe0\r
+       dw      ARM_instruction_acsez-instruction_handler\r
+       db      'acssm',0xe0\r
+       dw      ARM_instruction_acssm-instruction_handler\r
+       db      'acssp',0xe0\r
+       dw      ARM_instruction_acssp-instruction_handler\r
+       db      'acssz',0xe0\r
+       dw      ARM_instruction_acssz-instruction_handler\r
+       db      'adc.n',0xe4\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc.w',0xe2\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc~~',0x00\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'add.n',0xe4\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'add.w',0xe2\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'addhn',0xf0\r
+       dw      ARM_instruction_addhn-instruction_handler\r
+       db      'add~~',0x00\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adfdm',0xe0\r
+       dw      ARM_instruction_adfdm-instruction_handler\r
+       db      'adfdp',0xe0\r
+       dw      ARM_instruction_adfdp-instruction_handler\r
+       db      'adfdz',0xe0\r
+       dw      ARM_instruction_adfdz-instruction_handler\r
+       db      'adfem',0xe0\r
+       dw      ARM_instruction_adfem-instruction_handler\r
+       db      'adfep',0xe0\r
+       dw      ARM_instruction_adfep-instruction_handler\r
+       db      'adfez',0xe0\r
+       dw      ARM_instruction_adfez-instruction_handler\r
+       db      'adfsm',0xe0\r
+       dw      ARM_instruction_adfsm-instruction_handler\r
+       db      'adfsp',0xe0\r
+       dw      ARM_instruction_adfsp-instruction_handler\r
+       db      'adfsz',0xe0\r
+       dw      ARM_instruction_adfsz-instruction_handler\r
+       db      'adr.n',0xe4\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'adr.w',0xe2\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'adr~~',0x00\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'aesmc',0xf0\r
+       dw      ARM_instruction_aesmc-instruction_handler\r
+       db      'align',0x00\r
+       dw      align_directive-instruction_handler\r
+       db      'and.n',0xe4\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and.w',0xe2\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and~~',0x00\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asndm',0xe0\r
+       dw      ARM_instruction_asndm-instruction_handler\r
+       db      'asndp',0xe0\r
+       dw      ARM_instruction_asndp-instruction_handler\r
+       db      'asndz',0xe0\r
+       dw      ARM_instruction_asndz-instruction_handler\r
+       db      'asnem',0xe0\r
+       dw      ARM_instruction_asnem-instruction_handler\r
+       db      'asnep',0xe0\r
+       dw      ARM_instruction_asnep-instruction_handler\r
+       db      'asnez',0xe0\r
+       dw      ARM_instruction_asnez-instruction_handler\r
+       db      'asnsm',0xe0\r
+       dw      ARM_instruction_asnsm-instruction_handler\r
+       db      'asnsp',0xe0\r
+       dw      ARM_instruction_asnsp-instruction_handler\r
+       db      'asnsz',0xe0\r
+       dw      ARM_instruction_asnsz-instruction_handler\r
+       db      'asr.n',0xe4\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr.w',0xe2\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr~~',0x00\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'atndm',0xe0\r
+       dw      ARM_instruction_atndm-instruction_handler\r
+       db      'atndp',0xe0\r
+       dw      ARM_instruction_atndp-instruction_handler\r
+       db      'atndz',0xe0\r
+       dw      ARM_instruction_atndz-instruction_handler\r
+       db      'atnem',0xe0\r
+       dw      ARM_instruction_atnem-instruction_handler\r
+       db      'atnep',0xe0\r
+       dw      ARM_instruction_atnep-instruction_handler\r
+       db      'atnez',0xe0\r
+       dw      ARM_instruction_atnez-instruction_handler\r
+       db      'atnsm',0xe0\r
+       dw      ARM_instruction_atnsm-instruction_handler\r
+       db      'atnsp',0xe0\r
+       dw      ARM_instruction_atnsp-instruction_handler\r
+       db      'atnsz',0xe0\r
+       dw      ARM_instruction_atnsz-instruction_handler\r
+       db      'bfc~~',0x00\r
+       dw      ARM_instruction_bfc-instruction_handler\r
+       db      'bfi~~',0x00\r
+       dw      ARM_instruction_bfi-instruction_handler\r
+       db      'bfxil',0xf0\r
+       dw      ARM_instruction_bfxil-instruction_handler\r
+       db      'bic.n',0xe4\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic.w',0xe2\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic~~',0x00\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'blx.n',0xe4\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'blx.w',0xe2\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'blx~~',0x00\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'break',0x00\r
+       dw      break_directive-instruction_handler\r
+       db      'bxj~~',0x00\r
+       dw      ARM_instruction_bxj-instruction_handler\r
+       db      'b~~.n',0x04\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      'b~~.w',0x02\r
+       dw      ARM_instruction_b-instruction_handler\r
+       db      'cbz.n',0xf4\r
+       dw      ARM_instruction_cbz-instruction_handler\r
+       db      'cbz.w',0xf2\r
+       dw      ARM_instruction_cbz-instruction_handler\r
+       db      'cdp~~',0x00\r
+       dw      ARM_instruction_cdp-instruction_handler\r
+       db      'clrex',0xe0\r
+       dw      ARM_instruction_clrex-instruction_handler\r
+       db      'clz~~',0x00\r
+       dw      ARM_instruction_clz-instruction_handler\r
+       db      'cmf~~',0x00\r
+       dw      ARM_instruction_cmf-instruction_handler\r
+       db      'cmn.n',0xe4\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmn.w',0xe2\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmn~~',0x00\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmp.n',0xe4\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cmp.w',0xe2\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cmp~~',0x00\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cmtst',0xf0\r
+       dw      ARM_instruction_cmtst-instruction_handler\r
+       db      'cnf~~',0x00\r
+       dw      ARM_instruction_cnf-instruction_handler\r
+       db      'cosdm',0xe0\r
+       dw      ARM_instruction_cosdm-instruction_handler\r
+       db      'cosdp',0xe0\r
+       dw      ARM_instruction_cosdp-instruction_handler\r
+       db      'cosdz',0xe0\r
+       dw      ARM_instruction_cosdz-instruction_handler\r
+       db      'cosem',0xe0\r
+       dw      ARM_instruction_cosem-instruction_handler\r
+       db      'cosep',0xe0\r
+       dw      ARM_instruction_cosep-instruction_handler\r
+       db      'cosez',0xe0\r
+       dw      ARM_instruction_cosez-instruction_handler\r
+       db      'cossm',0xe0\r
+       dw      ARM_instruction_cossm-instruction_handler\r
+       db      'cossp',0xe0\r
+       dw      ARM_instruction_cossp-instruction_handler\r
+       db      'cossz',0xe0\r
+       dw      ARM_instruction_cossz-instruction_handler\r
+       db      'cps.n',0xf4\r
+       dw      ARM_instruction_cps-instruction_handler\r
+       db      'cps.w',0xf2\r
+       dw      ARM_instruction_cps-instruction_handler\r
+       db      'cpsid',0xf0\r
+       dw      ARM_instruction_cpsid-instruction_handler\r
+       db      'cpsie',0xf0\r
+       dw      ARM_instruction_cpsie-instruction_handler\r
+       db      'cpy.n',0xe4\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'cpy.w',0xe2\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'cpy~~',0x00\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'crc32',0xf0\r
+       dw      ARM_instruction_crc32-instruction_handler\r
+       db      'csetm',0xf0\r
+       dw      ARM_instruction_csetm-instruction_handler\r
+       db      'csinc',0xf0\r
+       dw      ARM_instruction_csinc-instruction_handler\r
+       db      'csinv',0xf0\r
+       dw      ARM_instruction_csinv-instruction_handler\r
+       db      'csneg',0xf0\r
+       dw      ARM_instruction_csneg-instruction_handler\r
+       db      'dbg~~',0x00\r
+       dw      ARM_instruction_dbg-instruction_handler\r
+       db      'dcps1',0xe0\r
+       dw      ARM_instruction_dcps1-instruction_handler\r
+       db      'dcps2',0xe0\r
+       dw      ARM_instruction_dcps2-instruction_handler\r
+       db      'dcps3',0xe0\r
+       dw      ARM_instruction_dcps3-instruction_handler\r
+       db      'dvfdm',0xe0\r
+       dw      ARM_instruction_dvfdm-instruction_handler\r
+       db      'dvfdp',0xe0\r
+       dw      ARM_instruction_dvfdp-instruction_handler\r
+       db      'dvfdz',0xe0\r
+       dw      ARM_instruction_dvfdz-instruction_handler\r
+       db      'dvfem',0xe0\r
+       dw      ARM_instruction_dvfem-instruction_handler\r
+       db      'dvfep',0xe0\r
+       dw      ARM_instruction_dvfep-instruction_handler\r
+       db      'dvfez',0xe0\r
+       dw      ARM_instruction_dvfez-instruction_handler\r
+       db      'dvfsm',0xe0\r
+       dw      ARM_instruction_dvfsm-instruction_handler\r
+       db      'dvfsp',0xe0\r
+       dw      ARM_instruction_dvfsp-instruction_handler\r
+       db      'dvfsz',0xe0\r
+       dw      ARM_instruction_dvfsz-instruction_handler\r
+       db      'entry',0x00\r
+       dw      entry_directive-instruction_handler\r
+       db      'eor.n',0xe4\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor.w',0xe2\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor~~',0x00\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'expdm',0xe0\r
+       dw      ARM_instruction_expdm-instruction_handler\r
+       db      'expdp',0xe0\r
+       dw      ARM_instruction_expdp-instruction_handler\r
+       db      'expdz',0xe0\r
+       dw      ARM_instruction_expdz-instruction_handler\r
+       db      'expem',0xe0\r
+       dw      ARM_instruction_expem-instruction_handler\r
+       db      'expep',0xe0\r
+       dw      ARM_instruction_expep-instruction_handler\r
+       db      'expez',0xe0\r
+       dw      ARM_instruction_expez-instruction_handler\r
+       db      'expsm',0xe0\r
+       dw      ARM_instruction_expsm-instruction_handler\r
+       db      'expsp',0xe0\r
+       dw      ARM_instruction_expsp-instruction_handler\r
+       db      'expsz',0xe0\r
+       dw      ARM_instruction_expsz-instruction_handler\r
+       db      'extrn',0x00\r
+       dw      extrn_directive-instruction_handler\r
+       db      'fabsd',0xe0\r
+       dw      ARM_instruction_fabsd-instruction_handler\r
+       db      'fabss',0xe0\r
+       dw      ARM_instruction_fabss-instruction_handler\r
+       db      'facge',0xf0\r
+       dw      ARM_instruction_facge-instruction_handler\r
+       db      'facgt',0xf0\r
+       dw      ARM_instruction_facgt-instruction_handler\r
+       db      'faddd',0xe0\r
+       dw      ARM_instruction_faddd-instruction_handler\r
+       db      'faddp',0xf0\r
+       dw      ARM_instruction_faddp-instruction_handler\r
+       db      'fadds',0xe0\r
+       dw      ARM_instruction_fadds-instruction_handler\r
+       db      'fccmp',0xf0\r
+       dw      ARM_instruction_fccmp-instruction_handler\r
+       db      'fcmeq',0xf0\r
+       dw      ARM_instruction_fcmeq-instruction_handler\r
+       db      'fcmge',0xf0\r
+       dw      ARM_instruction_fcmge-instruction_handler\r
+       db      'fcmgt',0xf0\r
+       dw      ARM_instruction_fcmgt-instruction_handler\r
+       db      'fcmle',0xf0\r
+       dw      ARM_instruction_fcmle-instruction_handler\r
+       db      'fcmlt',0xf0\r
+       dw      ARM_instruction_fcmlt-instruction_handler\r
+       db      'fcmpd',0xe0\r
+       dw      ARM_instruction_fcmpd-instruction_handler\r
+       db      'fcmpe',0xf0\r
+       dw      ARM_instruction_fcmpe-instruction_handler\r
+       db      'fcmps',0xe0\r
+       dw      ARM_instruction_fcmps-instruction_handler\r
+       db      'fcpyd',0xe0\r
+       dw      ARM_instruction_fcpyd-instruction_handler\r
+       db      'fcpys',0xe0\r
+       dw      ARM_instruction_fcpys-instruction_handler\r
+       db      'fcsel',0xf0\r
+       dw      ARM_instruction_fcsel-instruction_handler\r
+       db      'fcvtl',0xf0\r
+       dw      ARM_instruction_fcvtl-instruction_handler\r
+       db      'fcvtn',0xf0\r
+       dw      ARM_instruction_fcvtn-instruction_handler\r
+       db      'fdivd',0xe0\r
+       dw      ARM_instruction_fdivd-instruction_handler\r
+       db      'fdivs',0xe0\r
+       dw      ARM_instruction_fdivs-instruction_handler\r
+       db      'fdvdm',0xe0\r
+       dw      ARM_instruction_fdvdm-instruction_handler\r
+       db      'fdvdp',0xe0\r
+       dw      ARM_instruction_fdvdp-instruction_handler\r
+       db      'fdvdz',0xe0\r
+       dw      ARM_instruction_fdvdz-instruction_handler\r
+       db      'fdvem',0xe0\r
+       dw      ARM_instruction_fdvem-instruction_handler\r
+       db      'fdvep',0xe0\r
+       dw      ARM_instruction_fdvep-instruction_handler\r
+       db      'fdvez',0xe0\r
+       dw      ARM_instruction_fdvez-instruction_handler\r
+       db      'fdvsm',0xe0\r
+       dw      ARM_instruction_fdvsm-instruction_handler\r
+       db      'fdvsp',0xe0\r
+       dw      ARM_instruction_fdvsp-instruction_handler\r
+       db      'fdvsz',0xe0\r
+       dw      ARM_instruction_fdvsz-instruction_handler\r
+       db      'fix~~',0x00\r
+       dw      ARM_instruction_fix-instruction_handler\r
+       db      'fldmd',0xe0\r
+       dw      ARM_instruction_fldmd-instruction_handler\r
+       db      'fldms',0xe0\r
+       dw      ARM_instruction_fldms-instruction_handler\r
+       db      'fldmx',0xe0\r
+       dw      ARM_instruction_fldmx-instruction_handler\r
+       db      'fltdm',0xe0\r
+       dw      ARM_instruction_fltdm-instruction_handler\r
+       db      'fltdp',0xe0\r
+       dw      ARM_instruction_fltdp-instruction_handler\r
+       db      'fltdz',0xe0\r
+       dw      ARM_instruction_fltdz-instruction_handler\r
+       db      'fltem',0xe0\r
+       dw      ARM_instruction_fltem-instruction_handler\r
+       db      'fltep',0xe0\r
+       dw      ARM_instruction_fltep-instruction_handler\r
+       db      'fltez',0xe0\r
+       dw      ARM_instruction_fltez-instruction_handler\r
+       db      'fltsm',0xe0\r
+       dw      ARM_instruction_fltsm-instruction_handler\r
+       db      'fltsp',0xe0\r
+       dw      ARM_instruction_fltsp-instruction_handler\r
+       db      'fltsz',0xe0\r
+       dw      ARM_instruction_fltsz-instruction_handler\r
+       db      'fmacd',0xe0\r
+       dw      ARM_instruction_fmacd-instruction_handler\r
+       db      'fmacs',0xe0\r
+       dw      ARM_instruction_fmacs-instruction_handler\r
+       db      'fmadd',0xf0\r
+       dw      ARM_instruction_fmadd-instruction_handler\r
+       db      'fmaxp',0xf0\r
+       dw      ARM_instruction_fmaxp-instruction_handler\r
+       db      'fmaxv',0xf0\r
+       dw      ARM_instruction_fmaxv-instruction_handler\r
+       db      'fmdhr',0xe0\r
+       dw      ARM_instruction_fmdhr-instruction_handler\r
+       db      'fmdlr',0xe0\r
+       dw      ARM_instruction_fmdlr-instruction_handler\r
+       db      'fmdrr',0xe0\r
+       dw      ARM_instruction_fmdrr-instruction_handler\r
+       db      'fminp',0xf0\r
+       dw      ARM_instruction_fminp-instruction_handler\r
+       db      'fminv',0xf0\r
+       dw      ARM_instruction_fminv-instruction_handler\r
+       db      'fmldm',0xe0\r
+       dw      ARM_instruction_fmldm-instruction_handler\r
+       db      'fmldp',0xe0\r
+       dw      ARM_instruction_fmldp-instruction_handler\r
+       db      'fmldz',0xe0\r
+       dw      ARM_instruction_fmldz-instruction_handler\r
+       db      'fmlem',0xe0\r
+       dw      ARM_instruction_fmlem-instruction_handler\r
+       db      'fmlep',0xe0\r
+       dw      ARM_instruction_fmlep-instruction_handler\r
+       db      'fmlez',0xe0\r
+       dw      ARM_instruction_fmlez-instruction_handler\r
+       db      'fmlsm',0xe0\r
+       dw      ARM_instruction_fmlsm-instruction_handler\r
+       db      'fmlsp',0xe0\r
+       dw      ARM_instruction_fmlsp-instruction_handler\r
+       db      'fmlsz',0xe0\r
+       dw      ARM_instruction_fmlsz-instruction_handler\r
+       db      'fmrdh',0xe0\r
+       dw      ARM_instruction_fmrdh-instruction_handler\r
+       db      'fmrdl',0xe0\r
+       dw      ARM_instruction_fmrdl-instruction_handler\r
+       db      'fmrrd',0xe0\r
+       dw      ARM_instruction_fmrrd-instruction_handler\r
+       db      'fmrrs',0xe0\r
+       dw      ARM_instruction_fmrrs-instruction_handler\r
+       db      'fmscd',0xe0\r
+       dw      ARM_instruction_fmscd-instruction_handler\r
+       db      'fmscs',0xe0\r
+       dw      ARM_instruction_fmscs-instruction_handler\r
+       db      'fmsrr',0xe0\r
+       dw      ARM_instruction_fmsrr-instruction_handler\r
+       db      'fmsub',0xf0\r
+       dw      ARM_instruction_fmsub-instruction_handler\r
+       db      'fmuld',0xe0\r
+       dw      ARM_instruction_fmuld-instruction_handler\r
+       db      'fmuls',0xe0\r
+       dw      ARM_instruction_fmuls-instruction_handler\r
+       db      'fmulx',0xf0\r
+       dw      ARM_instruction_fmulx-instruction_handler\r
+       db      'fnegd',0xe0\r
+       dw      ARM_instruction_fnegd-instruction_handler\r
+       db      'fnegs',0xe0\r
+       dw      ARM_instruction_fnegs-instruction_handler\r
+       db      'fnmul',0xf0\r
+       dw      ARM_instruction_fnmul-instruction_handler\r
+       db      'frddm',0xe0\r
+       dw      ARM_instruction_frddm-instruction_handler\r
+       db      'frddp',0xe0\r
+       dw      ARM_instruction_frddp-instruction_handler\r
+       db      'frddz',0xe0\r
+       dw      ARM_instruction_frddz-instruction_handler\r
+       db      'frdem',0xe0\r
+       dw      ARM_instruction_frdem-instruction_handler\r
+       db      'frdep',0xe0\r
+       dw      ARM_instruction_frdep-instruction_handler\r
+       db      'frdez',0xe0\r
+       dw      ARM_instruction_frdez-instruction_handler\r
+       db      'frdsm',0xe0\r
+       dw      ARM_instruction_frdsm-instruction_handler\r
+       db      'frdsp',0xe0\r
+       dw      ARM_instruction_frdsp-instruction_handler\r
+       db      'frdsz',0xe0\r
+       dw      ARM_instruction_frdsz-instruction_handler\r
+       db      'fsqrt',0xf0\r
+       dw      ARM_instruction_fsqrt-instruction_handler\r
+       db      'fstmd',0xe0\r
+       dw      ARM_instruction_fstmd-instruction_handler\r
+       db      'fstms',0xe0\r
+       dw      ARM_instruction_fstms-instruction_handler\r
+       db      'fstmx',0xe0\r
+       dw      ARM_instruction_fstmx-instruction_handler\r
+       db      'fsubd',0xe0\r
+       dw      ARM_instruction_fsubd-instruction_handler\r
+       db      'fsubs',0xe0\r
+       dw      ARM_instruction_fsubs-instruction_handler\r
+       db      'hbl~~',0x00\r
+       dw      ARM_instruction_hbl-instruction_handler\r
+       db      'hbp~~',0x00\r
+       dw      ARM_instruction_hbp-instruction_handler\r
+       db      'iteee',0xf0\r
+       dw      ARM_instruction_iteee-instruction_handler\r
+       db      'iteet',0xf0\r
+       dw      ARM_instruction_iteet-instruction_handler\r
+       db      'itete',0xf0\r
+       dw      ARM_instruction_itete-instruction_handler\r
+       db      'itett',0xf0\r
+       dw      ARM_instruction_itett-instruction_handler\r
+       db      'ittee',0xf0\r
+       dw      ARM_instruction_ittee-instruction_handler\r
+       db      'ittet',0xf0\r
+       dw      ARM_instruction_ittet-instruction_handler\r
+       db      'ittte',0xf0\r
+       dw      ARM_instruction_ittte-instruction_handler\r
+       db      'itttt',0xf0\r
+       dw      ARM_instruction_itttt-instruction_handler\r
+       db      'label',0x00\r
+       dw      label_directive-instruction_handler\r
+       db      'ldaex',0xe0\r
+       dw      ARM_instruction_ldaex-instruction_handler\r
+       db      'ldarb',0xf0\r
+       dw      ARM_instruction_ldarb-instruction_handler\r
+       db      'ldarh',0xf0\r
+       dw      ARM_instruction_ldarh-instruction_handler\r
+       db      'ldaxp',0xf0\r
+       dw      ARM_instruction_ldaxp-instruction_handler\r
+       db      'ldaxr',0xf0\r
+       dw      ARM_instruction_ldaxr-instruction_handler\r
+       db      'lda~~',0x00\r
+       dw      ARM_instruction_lda-instruction_handler\r
+       db      'ldc2l',0xe0\r
+       dw      ARM_instruction_ldc2l-instruction_handler\r
+       db      'ldc~~',0x00\r
+       dw      ARM_instruction_ldc-instruction_handler\r
+       db      'ldm.n',0xe4\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldm.w',0xe2\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldmda',0xe0\r
+       dw      ARM_instruction_ldmda-instruction_handler\r
+       db      'ldmdb',0xe0\r
+       dw      ARM_instruction_ldmdb-instruction_handler\r
+       db      'ldmea',0xe0\r
+       dw      ARM_instruction_ldmea-instruction_handler\r
+       db      'ldmed',0xe0\r
+       dw      ARM_instruction_ldmed-instruction_handler\r
+       db      'ldmfa',0xe0\r
+       dw      ARM_instruction_ldmfa-instruction_handler\r
+       db      'ldmfd',0xe0\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmia',0xe0\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldmib',0xe0\r
+       dw      ARM_instruction_ldmib-instruction_handler\r
+       db      'ldm~~',0x00\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldpsw',0xf0\r
+       dw      ARM_instruction_ldpsw-instruction_handler\r
+       db      'ldr.n',0xe4\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'ldr.w',0xe2\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'ldrbt',0xe0\r
+       dw      ARM_instruction_ldrbt-instruction_handler\r
+       db      'ldrex',0xe0\r
+       dw      ARM_instruction_ldrex-instruction_handler\r
+       db      'ldrht',0xe0\r
+       dw      ARM_instruction_ldrht-instruction_handler\r
+       db      'ldrsb',0xe0\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsh',0xe0\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldrsw',0xf0\r
+       dw      ARM_instruction_ldrsw-instruction_handler\r
+       db      'ldr~~',0x00\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'ldtrb',0xf0\r
+       dw      ARM_instruction_ldtrb-instruction_handler\r
+       db      'ldtrh',0xf0\r
+       dw      ARM_instruction_ldtrh-instruction_handler\r
+       db      'ldurb',0xf0\r
+       dw      ARM_instruction_ldurb-instruction_handler\r
+       db      'ldurh',0xf0\r
+       dw      ARM_instruction_ldurh-instruction_handler\r
+       db      'ldxrb',0xf0\r
+       dw      ARM_instruction_ldxrb-instruction_handler\r
+       db      'ldxrh',0xf0\r
+       dw      ARM_instruction_ldxrh-instruction_handler\r
+       db      'lfmea',0xe0\r
+       dw      ARM_instruction_lfmea-instruction_handler\r
+       db      'lfmfd',0xe0\r
+       dw      ARM_instruction_lfmfd-instruction_handler\r
+       db      'lfm~~',0x00\r
+       dw      ARM_instruction_lfm-instruction_handler\r
+       db      'lgndm',0xe0\r
+       dw      ARM_instruction_lgndm-instruction_handler\r
+       db      'lgndp',0xe0\r
+       dw      ARM_instruction_lgndp-instruction_handler\r
+       db      'lgndz',0xe0\r
+       dw      ARM_instruction_lgndz-instruction_handler\r
+       db      'lgnem',0xe0\r
+       dw      ARM_instruction_lgnem-instruction_handler\r
+       db      'lgnep',0xe0\r
+       dw      ARM_instruction_lgnep-instruction_handler\r
+       db      'lgnez',0xe0\r
+       dw      ARM_instruction_lgnez-instruction_handler\r
+       db      'lgnsm',0xe0\r
+       dw      ARM_instruction_lgnsm-instruction_handler\r
+       db      'lgnsp',0xe0\r
+       dw      ARM_instruction_lgnsp-instruction_handler\r
+       db      'lgnsz',0xe0\r
+       dw      ARM_instruction_lgnsz-instruction_handler\r
+       db      'logdm',0xe0\r
+       dw      ARM_instruction_logdm-instruction_handler\r
+       db      'logdp',0xe0\r
+       dw      ARM_instruction_logdp-instruction_handler\r
+       db      'logdz',0xe0\r
+       dw      ARM_instruction_logdz-instruction_handler\r
+       db      'logem',0xe0\r
+       dw      ARM_instruction_logem-instruction_handler\r
+       db      'logep',0xe0\r
+       dw      ARM_instruction_logep-instruction_handler\r
+       db      'logez',0xe0\r
+       dw      ARM_instruction_logez-instruction_handler\r
+       db      'logsm',0xe0\r
+       dw      ARM_instruction_logsm-instruction_handler\r
+       db      'logsp',0xe0\r
+       dw      ARM_instruction_logsp-instruction_handler\r
+       db      'logsz',0xe0\r
+       dw      ARM_instruction_logsz-instruction_handler\r
+       db      'lsl.n',0xe4\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl.w',0xe2\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl~~',0x00\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsr.n',0xe4\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr.w',0xe2\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr~~',0x00\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'mar~~',0x00\r
+       dw      ARM_instruction_mar-instruction_handler\r
+       db      'mcrr2',0xe0\r
+       dw      ARM_instruction_mcrr2-instruction_handler\r
+       db      'mcr~~',0x00\r
+       dw      ARM_instruction_mcr-instruction_handler\r
+       db      'miabb',0xe0\r
+       dw      ARM_instruction_miabb-instruction_handler\r
+       db      'miabt',0xe0\r
+       dw      ARM_instruction_miabt-instruction_handler\r
+       db      'miaph',0xe0\r
+       dw      ARM_instruction_miaph-instruction_handler\r
+       db      'miatb',0xe0\r
+       dw      ARM_instruction_miatb-instruction_handler\r
+       db      'miatt',0xe0\r
+       dw      ARM_instruction_miatt-instruction_handler\r
+       db      'mia~~',0x00\r
+       dw      ARM_instruction_mia-instruction_handler\r
+       db      'mla~~',0x00\r
+       dw      ARM_instruction_mla-instruction_handler\r
+       db      'mls~~',0x00\r
+       dw      ARM_instruction_mls-instruction_handler\r
+       db      'mnfdm',0xe0\r
+       dw      ARM_instruction_mnfdm-instruction_handler\r
+       db      'mnfdp',0xe0\r
+       dw      ARM_instruction_mnfdp-instruction_handler\r
+       db      'mnfdz',0xe0\r
+       dw      ARM_instruction_mnfdz-instruction_handler\r
+       db      'mnfem',0xe0\r
+       dw      ARM_instruction_mnfem-instruction_handler\r
+       db      'mnfep',0xe0\r
+       dw      ARM_instruction_mnfep-instruction_handler\r
+       db      'mnfez',0xe0\r
+       dw      ARM_instruction_mnfez-instruction_handler\r
+       db      'mnfsm',0xe0\r
+       dw      ARM_instruction_mnfsm-instruction_handler\r
+       db      'mnfsp',0xe0\r
+       dw      ARM_instruction_mnfsp-instruction_handler\r
+       db      'mnfsz',0xe0\r
+       dw      ARM_instruction_mnfsz-instruction_handler\r
+       db      'mov.n',0xe4\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mov.w',0xe2\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mov~~',0x00\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mra~~',0x00\r
+       dw      ARM_instruction_mra-instruction_handler\r
+       db      'mrc~~',0x00\r
+       dw      ARM_instruction_mrc-instruction_handler\r
+       db      'mrrc2',0xe0\r
+       dw      ARM_instruction_mrrc2-instruction_handler\r
+       db      'mrs~~',0x00\r
+       dw      ARM_instruction_mrs-instruction_handler\r
+       db      'msr~~',0x00\r
+       dw      ARM_instruction_msr-instruction_handler\r
+       db      'mufdm',0xe0\r
+       dw      ARM_instruction_mufdm-instruction_handler\r
+       db      'mufdp',0xe0\r
+       dw      ARM_instruction_mufdp-instruction_handler\r
+       db      'mufdz',0xe0\r
+       dw      ARM_instruction_mufdz-instruction_handler\r
+       db      'mufem',0xe0\r
+       dw      ARM_instruction_mufem-instruction_handler\r
+       db      'mufep',0xe0\r
+       dw      ARM_instruction_mufep-instruction_handler\r
+       db      'mufez',0xe0\r
+       dw      ARM_instruction_mufez-instruction_handler\r
+       db      'mufsm',0xe0\r
+       dw      ARM_instruction_mufsm-instruction_handler\r
+       db      'mufsp',0xe0\r
+       dw      ARM_instruction_mufsp-instruction_handler\r
+       db      'mufsz',0xe0\r
+       dw      ARM_instruction_mufsz-instruction_handler\r
+       db      'mul.n',0xe4\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul.w',0xe2\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul~~',0x00\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvfdm',0xe0\r
+       dw      ARM_instruction_mvfdm-instruction_handler\r
+       db      'mvfdp',0xe0\r
+       dw      ARM_instruction_mvfdp-instruction_handler\r
+       db      'mvfdz',0xe0\r
+       dw      ARM_instruction_mvfdz-instruction_handler\r
+       db      'mvfem',0xe0\r
+       dw      ARM_instruction_mvfem-instruction_handler\r
+       db      'mvfep',0xe0\r
+       dw      ARM_instruction_mvfep-instruction_handler\r
+       db      'mvfez',0xe0\r
+       dw      ARM_instruction_mvfez-instruction_handler\r
+       db      'mvfsm',0xe0\r
+       dw      ARM_instruction_mvfsm-instruction_handler\r
+       db      'mvfsp',0xe0\r
+       dw      ARM_instruction_mvfsp-instruction_handler\r
+       db      'mvfsz',0xe0\r
+       dw      ARM_instruction_mvfsz-instruction_handler\r
+       db      'mvn.n',0xe4\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn.w',0xe2\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn~~',0x00\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'neg.n',0xe4\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg.w',0xe2\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg~~',0x00\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'nop.n',0xe4\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'nop.w',0xe2\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'nop~~',0x00\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'nrmdm',0xe0\r
+       dw      ARM_instruction_nrmdm-instruction_handler\r
+       db      'nrmdp',0xe0\r
+       dw      ARM_instruction_nrmdp-instruction_handler\r
+       db      'nrmdz',0xe0\r
+       dw      ARM_instruction_nrmdz-instruction_handler\r
+       db      'nrmem',0xe0\r
+       dw      ARM_instruction_nrmem-instruction_handler\r
+       db      'nrmep',0xe0\r
+       dw      ARM_instruction_nrmep-instruction_handler\r
+       db      'nrmez',0xe0\r
+       dw      ARM_instruction_nrmez-instruction_handler\r
+       db      'nrmsm',0xe0\r
+       dw      ARM_instruction_nrmsm-instruction_handler\r
+       db      'nrmsp',0xe0\r
+       dw      ARM_instruction_nrmsp-instruction_handler\r
+       db      'nrmsz',0xe0\r
+       dw      ARM_instruction_nrmsz-instruction_handler\r
+       db      'orn~~',0x00\r
+       dw      ARM_instruction_orn-instruction_handler\r
+       db      'orr.n',0xe4\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr.w',0xe2\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr~~',0x00\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'pkhbt',0xe0\r
+       dw      ARM_instruction_pkhbt-instruction_handler\r
+       db      'pkhtb',0xe0\r
+       dw      ARM_instruction_pkhtb-instruction_handler\r
+       db      'pld~~',0x00\r
+       dw      ARM_instruction_pld-instruction_handler\r
+       db      'pli~~',0x00\r
+       dw      ARM_instruction_pli-instruction_handler\r
+       db      'pmull',0xf0\r
+       dw      ARM_instruction_pmull-instruction_handler\r
+       db      'poldm',0xe0\r
+       dw      ARM_instruction_poldm-instruction_handler\r
+       db      'poldp',0xe0\r
+       dw      ARM_instruction_poldp-instruction_handler\r
+       db      'poldz',0xe0\r
+       dw      ARM_instruction_poldz-instruction_handler\r
+       db      'polem',0xe0\r
+       dw      ARM_instruction_polem-instruction_handler\r
+       db      'polep',0xe0\r
+       dw      ARM_instruction_polep-instruction_handler\r
+       db      'polez',0xe0\r
+       dw      ARM_instruction_polez-instruction_handler\r
+       db      'polsm',0xe0\r
+       dw      ARM_instruction_polsm-instruction_handler\r
+       db      'polsp',0xe0\r
+       dw      ARM_instruction_polsp-instruction_handler\r
+       db      'polsz',0xe0\r
+       dw      ARM_instruction_polsz-instruction_handler\r
+       db      'pop.n',0xe4\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'pop.w',0xe2\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'pop~~',0x00\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'powdm',0xe0\r
+       dw      ARM_instruction_powdm-instruction_handler\r
+       db      'powdp',0xe0\r
+       dw      ARM_instruction_powdp-instruction_handler\r
+       db      'powdz',0xe0\r
+       dw      ARM_instruction_powdz-instruction_handler\r
+       db      'powem',0xe0\r
+       dw      ARM_instruction_powem-instruction_handler\r
+       db      'powep',0xe0\r
+       dw      ARM_instruction_powep-instruction_handler\r
+       db      'powez',0xe0\r
+       dw      ARM_instruction_powez-instruction_handler\r
+       db      'powsm',0xe0\r
+       dw      ARM_instruction_powsm-instruction_handler\r
+       db      'powsp',0xe0\r
+       dw      ARM_instruction_powsp-instruction_handler\r
+       db      'powsz',0xe0\r
+       dw      ARM_instruction_powsz-instruction_handler\r
+       db      'qadd8',0xe0\r
+       dw      ARM_instruction_qadd8-instruction_handler\r
+       db      'qdadd',0xe0\r
+       dw      ARM_instruction_qdadd-instruction_handler\r
+       db      'qdsub',0xe0\r
+       dw      ARM_instruction_qdsub-instruction_handler\r
+       db      'qsub8',0xe0\r
+       dw      ARM_instruction_qsub8-instruction_handler\r
+       db      'rdfdm',0xe0\r
+       dw      ARM_instruction_rdfdm-instruction_handler\r
+       db      'rdfdp',0xe0\r
+       dw      ARM_instruction_rdfdp-instruction_handler\r
+       db      'rdfdz',0xe0\r
+       dw      ARM_instruction_rdfdz-instruction_handler\r
+       db      'rdfem',0xe0\r
+       dw      ARM_instruction_rdfem-instruction_handler\r
+       db      'rdfep',0xe0\r
+       dw      ARM_instruction_rdfep-instruction_handler\r
+       db      'rdfez',0xe0\r
+       dw      ARM_instruction_rdfez-instruction_handler\r
+       db      'rdfsm',0xe0\r
+       dw      ARM_instruction_rdfsm-instruction_handler\r
+       db      'rdfsp',0xe0\r
+       dw      ARM_instruction_rdfsp-instruction_handler\r
+       db      'rdfsz',0xe0\r
+       dw      ARM_instruction_rdfsz-instruction_handler\r
+       db      'rev.n',0xe4\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rev.w',0xe2\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rev16',0xe0\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'rev32',0xf0\r
+       dw      ARM_instruction_rev32-instruction_handler\r
+       db      'rev64',0xf0\r
+       dw      ARM_instruction_rev64-instruction_handler\r
+       db      'revsh',0xe0\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'rev~~',0x00\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rfc~~',0x00\r
+       dw      ARM_instruction_rfc-instruction_handler\r
+       db      'rfeda',0xf0\r
+       dw      ARM_instruction_rfeda-instruction_handler\r
+       db      'rfedb',0xf0\r
+       dw      ARM_instruction_rfedb-instruction_handler\r
+       db      'rfeea',0xf0\r
+       dw      ARM_instruction_rfeea-instruction_handler\r
+       db      'rfeed',0xf0\r
+       dw      ARM_instruction_rfeed-instruction_handler\r
+       db      'rfefa',0xf0\r
+       dw      ARM_instruction_rfefa-instruction_handler\r
+       db      'rfefd',0xf0\r
+       dw      ARM_instruction_rfefd-instruction_handler\r
+       db      'rfeia',0xf0\r
+       dw      ARM_instruction_rfeia-instruction_handler\r
+       db      'rfeib',0xf0\r
+       dw      ARM_instruction_rfeib-instruction_handler\r
+       db      'rfs~~',0x00\r
+       dw      ARM_instruction_rfs-instruction_handler\r
+       db      'rmfdm',0xe0\r
+       dw      ARM_instruction_rmfdm-instruction_handler\r
+       db      'rmfdp',0xe0\r
+       dw      ARM_instruction_rmfdp-instruction_handler\r
+       db      'rmfdz',0xe0\r
+       dw      ARM_instruction_rmfdz-instruction_handler\r
+       db      'rmfem',0xe0\r
+       dw      ARM_instruction_rmfem-instruction_handler\r
+       db      'rmfep',0xe0\r
+       dw      ARM_instruction_rmfep-instruction_handler\r
+       db      'rmfez',0xe0\r
+       dw      ARM_instruction_rmfez-instruction_handler\r
+       db      'rmfsm',0xe0\r
+       dw      ARM_instruction_rmfsm-instruction_handler\r
+       db      'rmfsp',0xe0\r
+       dw      ARM_instruction_rmfsp-instruction_handler\r
+       db      'rmfsz',0xe0\r
+       dw      ARM_instruction_rmfsz-instruction_handler\r
+       db      'rnddm',0xe0\r
+       dw      ARM_instruction_rnddm-instruction_handler\r
+       db      'rnddp',0xe0\r
+       dw      ARM_instruction_rnddp-instruction_handler\r
+       db      'rnddz',0xe0\r
+       dw      ARM_instruction_rnddz-instruction_handler\r
+       db      'rndem',0xe0\r
+       dw      ARM_instruction_rndem-instruction_handler\r
+       db      'rndep',0xe0\r
+       dw      ARM_instruction_rndep-instruction_handler\r
+       db      'rndez',0xe0\r
+       dw      ARM_instruction_rndez-instruction_handler\r
+       db      'rndsm',0xe0\r
+       dw      ARM_instruction_rndsm-instruction_handler\r
+       db      'rndsp',0xe0\r
+       dw      ARM_instruction_rndsp-instruction_handler\r
+       db      'rndsz',0xe0\r
+       dw      ARM_instruction_rndsz-instruction_handler\r
+       db      'ror.n',0xe4\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror.w',0xe2\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror~~',0x00\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rpwdm',0xe0\r
+       dw      ARM_instruction_rpwdm-instruction_handler\r
+       db      'rpwdp',0xe0\r
+       dw      ARM_instruction_rpwdp-instruction_handler\r
+       db      'rpwdz',0xe0\r
+       dw      ARM_instruction_rpwdz-instruction_handler\r
+       db      'rpwem',0xe0\r
+       dw      ARM_instruction_rpwem-instruction_handler\r
+       db      'rpwep',0xe0\r
+       dw      ARM_instruction_rpwep-instruction_handler\r
+       db      'rpwez',0xe0\r
+       dw      ARM_instruction_rpwez-instruction_handler\r
+       db      'rpwsm',0xe0\r
+       dw      ARM_instruction_rpwsm-instruction_handler\r
+       db      'rpwsp',0xe0\r
+       dw      ARM_instruction_rpwsp-instruction_handler\r
+       db      'rpwsz',0xe0\r
+       dw      ARM_instruction_rpwsz-instruction_handler\r
+       db      'rrx~~',0x00\r
+       dw      ARM_instruction_rrx-instruction_handler\r
+       db      'rsb.n',0xe4\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb.w',0xe2\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb~~',0x00\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsc~~',0x00\r
+       dw      ARM_instruction_rsc-instruction_handler\r
+       db      'rsfdm',0xe0\r
+       dw      ARM_instruction_rsfdm-instruction_handler\r
+       db      'rsfdp',0xe0\r
+       dw      ARM_instruction_rsfdp-instruction_handler\r
+       db      'rsfdz',0xe0\r
+       dw      ARM_instruction_rsfdz-instruction_handler\r
+       db      'rsfem',0xe0\r
+       dw      ARM_instruction_rsfem-instruction_handler\r
+       db      'rsfep',0xe0\r
+       dw      ARM_instruction_rsfep-instruction_handler\r
+       db      'rsfez',0xe0\r
+       dw      ARM_instruction_rsfez-instruction_handler\r
+       db      'rsfsm',0xe0\r
+       dw      ARM_instruction_rsfsm-instruction_handler\r
+       db      'rsfsp',0xe0\r
+       dw      ARM_instruction_rsfsp-instruction_handler\r
+       db      'rsfsz',0xe0\r
+       dw      ARM_instruction_rsfsz-instruction_handler\r
+       db      'rshrn',0xf0\r
+       dw      ARM_instruction_rshrn-instruction_handler\r
+       db      'sabal',0xf0\r
+       dw      ARM_instruction_sabal-instruction_handler\r
+       db      'sabdl',0xf0\r
+       dw      ARM_instruction_sabdl-instruction_handler\r
+       db      'sadd8',0xe0\r
+       dw      ARM_instruction_sadd8-instruction_handler\r
+       db      'saddl',0xf0\r
+       dw      ARM_instruction_saddl-instruction_handler\r
+       db      'saddw',0xf0\r
+       dw      ARM_instruction_saddw-instruction_handler\r
+       db      'sbc.n',0xe4\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc.w',0xe2\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc~~',0x00\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbfiz',0xf0\r
+       dw      ARM_instruction_sbfiz-instruction_handler\r
+       db      'scvtf',0xf0\r
+       dw      ARM_instruction_scvtf-instruction_handler\r
+       db      'sel~~',0x00\r
+       dw      ARM_instruction_sel-instruction_handler\r
+       db      'sev.n',0xe4\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sev.w',0xe2\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sev~~',0x00\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sfmea',0xe0\r
+       dw      ARM_instruction_sfmea-instruction_handler\r
+       db      'sfmfd',0xe0\r
+       dw      ARM_instruction_sfmfd-instruction_handler\r
+       db      'sfm~~',0x00\r
+       dw      ARM_instruction_sfm-instruction_handler\r
+       db      'sha1c',0xf0\r
+       dw      ARM_instruction_sha1c-instruction_handler\r
+       db      'sha1h',0xf0\r
+       dw      ARM_instruction_sha1h-instruction_handler\r
+       db      'sha1m',0xf0\r
+       dw      ARM_instruction_sha1m-instruction_handler\r
+       db      'sha1p',0xf0\r
+       dw      ARM_instruction_sha1p-instruction_handler\r
+       db      'shadd',0xf0\r
+       dw      ARM_instruction_shadd-instruction_handler\r
+       db      'shasx',0xe0\r
+       dw      ARM_instruction_shasx-instruction_handler\r
+       db      'shll2',0xf0\r
+       dw      ARM_instruction_shll2-instruction_handler\r
+       db      'shrn2',0xf0\r
+       dw      ARM_instruction_shrn2-instruction_handler\r
+       db      'shsax',0xe0\r
+       dw      ARM_instruction_shsax-instruction_handler\r
+       db      'shsub',0xf0\r
+       dw      ARM_instruction_shsub-instruction_handler\r
+       db      'sindm',0xe0\r
+       dw      ARM_instruction_sindm-instruction_handler\r
+       db      'sindp',0xe0\r
+       dw      ARM_instruction_sindp-instruction_handler\r
+       db      'sindz',0xe0\r
+       dw      ARM_instruction_sindz-instruction_handler\r
+       db      'sinem',0xe0\r
+       dw      ARM_instruction_sinem-instruction_handler\r
+       db      'sinep',0xe0\r
+       dw      ARM_instruction_sinep-instruction_handler\r
+       db      'sinez',0xe0\r
+       dw      ARM_instruction_sinez-instruction_handler\r
+       db      'sinsm',0xe0\r
+       dw      ARM_instruction_sinsm-instruction_handler\r
+       db      'sinsp',0xe0\r
+       dw      ARM_instruction_sinsp-instruction_handler\r
+       db      'sinsz',0xe0\r
+       dw      ARM_instruction_sinsz-instruction_handler\r
+       db      'smaxp',0xf0\r
+       dw      ARM_instruction_smaxp-instruction_handler\r
+       db      'smaxv',0xf0\r
+       dw      ARM_instruction_smaxv-instruction_handler\r
+       db      'smc~~',0x00\r
+       dw      ARM_instruction_smc-instruction_handler\r
+       db      'sminp',0xf0\r
+       dw      ARM_instruction_sminp-instruction_handler\r
+       db      'sminv',0xf0\r
+       dw      ARM_instruction_sminv-instruction_handler\r
+       db      'smi~~',0x00\r
+       dw      ARM_instruction_smi-instruction_handler\r
+       db      'smlad',0xe0\r
+       dw      ARM_instruction_smlad-instruction_handler\r
+       db      'smlal',0xe0\r
+       dw      ARM_instruction_smlal-instruction_handler\r
+       db      'smlsd',0xe0\r
+       dw      ARM_instruction_smlsd-instruction_handler\r
+       db      'smlsl',0xf0\r
+       dw      ARM_instruction_smlsl-instruction_handler\r
+       db      'smmla',0xe0\r
+       dw      ARM_instruction_smmla-instruction_handler\r
+       db      'smmls',0xe0\r
+       dw      ARM_instruction_smmls-instruction_handler\r
+       db      'smmul',0xe0\r
+       dw      ARM_instruction_smmul-instruction_handler\r
+       db      'smuad',0xe0\r
+       dw      ARM_instruction_smuad-instruction_handler\r
+       db      'smulh',0xf0\r
+       dw      ARM_instruction_smulh-instruction_handler\r
+       db      'smull',0xe0\r
+       dw      ARM_instruction_smull-instruction_handler\r
+       db      'smusd',0xe0\r
+       dw      ARM_instruction_smusd-instruction_handler\r
+       db      'sqabs',0xf0\r
+       dw      ARM_instruction_sqabs-instruction_handler\r
+       db      'sqadd',0xf0\r
+       dw      ARM_instruction_sqadd-instruction_handler\r
+       db      'sqneg',0xf0\r
+       dw      ARM_instruction_sqneg-instruction_handler\r
+       db      'sqshl',0xf0\r
+       dw      ARM_instruction_sqshl-instruction_handler\r
+       db      'sqsub',0xf0\r
+       dw      ARM_instruction_sqsub-instruction_handler\r
+       db      'sqtdm',0xe0\r
+       dw      ARM_instruction_sqtdm-instruction_handler\r
+       db      'sqtdp',0xe0\r
+       dw      ARM_instruction_sqtdp-instruction_handler\r
+       db      'sqtdz',0xe0\r
+       dw      ARM_instruction_sqtdz-instruction_handler\r
+       db      'sqtem',0xe0\r
+       dw      ARM_instruction_sqtem-instruction_handler\r
+       db      'sqtep',0xe0\r
+       dw      ARM_instruction_sqtep-instruction_handler\r
+       db      'sqtez',0xe0\r
+       dw      ARM_instruction_sqtez-instruction_handler\r
+       db      'sqtsm',0xe0\r
+       dw      ARM_instruction_sqtsm-instruction_handler\r
+       db      'sqtsp',0xe0\r
+       dw      ARM_instruction_sqtsp-instruction_handler\r
+       db      'sqtsz',0xe0\r
+       dw      ARM_instruction_sqtsz-instruction_handler\r
+       db      'sqxtn',0xf0\r
+       dw      ARM_instruction_sqxtn-instruction_handler\r
+       db      'srsda',0xf0\r
+       dw      ARM_instruction_srsda-instruction_handler\r
+       db      'srsdb',0xf0\r
+       dw      ARM_instruction_srsdb-instruction_handler\r
+       db      'srsea',0xf0\r
+       dw      ARM_instruction_srsea-instruction_handler\r
+       db      'srsed',0xf0\r
+       dw      ARM_instruction_srsed-instruction_handler\r
+       db      'srsfa',0xf0\r
+       dw      ARM_instruction_srsfa-instruction_handler\r
+       db      'srsfd',0xf0\r
+       dw      ARM_instruction_srsfd-instruction_handler\r
+       db      'srshl',0xf0\r
+       dw      ARM_instruction_srshl-instruction_handler\r
+       db      'srshr',0xf0\r
+       dw      ARM_instruction_srshr-instruction_handler\r
+       db      'srsia',0xf0\r
+       dw      ARM_instruction_srsia-instruction_handler\r
+       db      'srsib',0xf0\r
+       dw      ARM_instruction_srsib-instruction_handler\r
+       db      'srsra',0xf0\r
+       dw      ARM_instruction_srsra-instruction_handler\r
+       db      'sshll',0xf0\r
+       dw      ARM_instruction_sshll-instruction_handler\r
+       db      'ssub8',0xe0\r
+       dw      ARM_instruction_ssub8-instruction_handler\r
+       db      'ssubl',0xf0\r
+       dw      ARM_instruction_ssubl-instruction_handler\r
+       db      'ssubw',0xf0\r
+       dw      ARM_instruction_ssubw-instruction_handler\r
+       db      'stack',0x00\r
+       dw      stack_directive-instruction_handler\r
+       db      'stc2l',0xe0\r
+       dw      ARM_instruction_stc2l-instruction_handler\r
+       db      'stc~~',0x00\r
+       dw      ARM_instruction_stc-instruction_handler\r
+       db      'stlex',0xe0\r
+       dw      ARM_instruction_stlex-instruction_handler\r
+       db      'stlrb',0xf0\r
+       dw      ARM_instruction_stlrb-instruction_handler\r
+       db      'stlrh',0xf0\r
+       dw      ARM_instruction_stlrh-instruction_handler\r
+       db      'stlxp',0xf0\r
+       dw      ARM_instruction_stlxp-instruction_handler\r
+       db      'stlxr',0xf0\r
+       dw      ARM_instruction_stlxr-instruction_handler\r
+       db      'stl~~',0x00\r
+       dw      ARM_instruction_stl-instruction_handler\r
+       db      'stm.n',0xe4\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'stm.w',0xe2\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'stmda',0xe0\r
+       dw      ARM_instruction_stmda-instruction_handler\r
+       db      'stmdb',0xe0\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmea',0xe0\r
+       dw      ARM_instruction_stmea-instruction_handler\r
+       db      'stmed',0xe0\r
+       dw      ARM_instruction_stmed-instruction_handler\r
+       db      'stmfa',0xe0\r
+       dw      ARM_instruction_stmfa-instruction_handler\r
+       db      'stmfd',0xe0\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmia',0xe0\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stmib',0xe0\r
+       dw      ARM_instruction_stmib-instruction_handler\r
+       db      'stm~~',0x00\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'store',0x00\r
+       dw      store_directive-instruction_handler\r
+       db      'str.n',0xe4\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'str.w',0xe2\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'strbt',0xe0\r
+       dw      ARM_instruction_strbt-instruction_handler\r
+       db      'strex',0xe0\r
+       dw      ARM_instruction_strex-instruction_handler\r
+       db      'strht',0xe0\r
+       dw      ARM_instruction_strht-instruction_handler\r
+       db      'str~~',0x00\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'sttrb',0xf0\r
+       dw      ARM_instruction_sttrb-instruction_handler\r
+       db      'sttrh',0xf0\r
+       dw      ARM_instruction_sttrh-instruction_handler\r
+       db      'sturb',0xf0\r
+       dw      ARM_instruction_sturb-instruction_handler\r
+       db      'sturh',0xf0\r
+       dw      ARM_instruction_sturh-instruction_handler\r
+       db      'stxrb',0xf0\r
+       dw      ARM_instruction_stxrb-instruction_handler\r
+       db      'stxrh',0xf0\r
+       dw      ARM_instruction_stxrh-instruction_handler\r
+       db      'sub.n',0xe4\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sub.w',0xe2\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subhn',0xf0\r
+       dw      ARM_instruction_subhn-instruction_handler\r
+       db      'sub~~',0x00\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sufdm',0xe0\r
+       dw      ARM_instruction_sufdm-instruction_handler\r
+       db      'sufdp',0xe0\r
+       dw      ARM_instruction_sufdp-instruction_handler\r
+       db      'sufdz',0xe0\r
+       dw      ARM_instruction_sufdz-instruction_handler\r
+       db      'sufem',0xe0\r
+       dw      ARM_instruction_sufem-instruction_handler\r
+       db      'sufep',0xe0\r
+       dw      ARM_instruction_sufep-instruction_handler\r
+       db      'sufez',0xe0\r
+       dw      ARM_instruction_sufez-instruction_handler\r
+       db      'sufsm',0xe0\r
+       dw      ARM_instruction_sufsm-instruction_handler\r
+       db      'sufsp',0xe0\r
+       dw      ARM_instruction_sufsp-instruction_handler\r
+       db      'sufsz',0xe0\r
+       dw      ARM_instruction_sufsz-instruction_handler\r
+       db      'svc.n',0xe4\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'svc.w',0xe2\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'svc~~',0x00\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'swi.n',0xe4\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'swi.w',0xe2\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'swi~~',0x00\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'swp~~',0x00\r
+       dw      ARM_instruction_swp-instruction_handler\r
+       db      'sxtab',0xe0\r
+       dw      ARM_instruction_sxtab-instruction_handler\r
+       db      'sxtah',0xe0\r
+       dw      ARM_instruction_sxtah-instruction_handler\r
+       db      'sxtl2',0xf0\r
+       dw      ARM_instruction_sxtl2-instruction_handler\r
+       db      'tandm',0xe0\r
+       dw      ARM_instruction_tandm-instruction_handler\r
+       db      'tandp',0xe0\r
+       dw      ARM_instruction_tandp-instruction_handler\r
+       db      'tandz',0xe0\r
+       dw      ARM_instruction_tandz-instruction_handler\r
+       db      'tanem',0xe0\r
+       dw      ARM_instruction_tanem-instruction_handler\r
+       db      'tanep',0xe0\r
+       dw      ARM_instruction_tanep-instruction_handler\r
+       db      'tanez',0xe0\r
+       dw      ARM_instruction_tanez-instruction_handler\r
+       db      'tansm',0xe0\r
+       dw      ARM_instruction_tansm-instruction_handler\r
+       db      'tansp',0xe0\r
+       dw      ARM_instruction_tansp-instruction_handler\r
+       db      'tansz',0xe0\r
+       dw      ARM_instruction_tansz-instruction_handler\r
+       db      'tbb~~',0x00\r
+       dw      ARM_instruction_tbb-instruction_handler\r
+       db      'tbh~~',0x00\r
+       dw      ARM_instruction_tbh-instruction_handler\r
+       db      'teq~~',0x00\r
+       dw      ARM_instruction_teq-instruction_handler\r
+       db      'thumb',0x00\r
+       dw      ARM_thumb_directive-instruction_handler\r
+       db      'times',0x00\r
+       dw      times_directive-instruction_handler\r
+       db      'tmcrr',0xe0\r
+       dw      ARM_instruction_tmcrr-instruction_handler\r
+       db      'tmrrc',0xe0\r
+       dw      ARM_instruction_tmrrc-instruction_handler\r
+       db      'torcb',0xe0\r
+       dw      ARM_instruction_torcb-instruction_handler\r
+       db      'torch',0xe0\r
+       dw      ARM_instruction_torch-instruction_handler\r
+       db      'torcw',0xe0\r
+       dw      ARM_instruction_torcw-instruction_handler\r
+       db      'tst.n',0xe4\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'tst.w',0xe2\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'tst~~',0x00\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'uabal',0xf0\r
+       dw      ARM_instruction_uabal-instruction_handler\r
+       db      'uabdl',0xf0\r
+       dw      ARM_instruction_uabdl-instruction_handler\r
+       db      'uadd8',0xe0\r
+       dw      ARM_instruction_uadd8-instruction_handler\r
+       db      'uaddl',0xf0\r
+       dw      ARM_instruction_uaddl-instruction_handler\r
+       db      'uaddw',0xf0\r
+       dw      ARM_instruction_uaddw-instruction_handler\r
+       db      'ubfiz',0xf0\r
+       dw      ARM_instruction_ubfiz-instruction_handler\r
+       db      'ucvtf',0xf0\r
+       dw      ARM_instruction_ucvtf-instruction_handler\r
+       db      'uhadd',0xf0\r
+       dw      ARM_instruction_uhadd-instruction_handler\r
+       db      'uhasx',0xe0\r
+       dw      ARM_instruction_uhasx-instruction_handler\r
+       db      'uhsax',0xe0\r
+       dw      ARM_instruction_uhsax-instruction_handler\r
+       db      'uhsub',0xf0\r
+       dw      ARM_instruction_uhsub-instruction_handler\r
+       db      'umaal',0xe0\r
+       dw      ARM_instruction_umaal-instruction_handler\r
+       db      'umaxp',0xf0\r
+       dw      ARM_instruction_umaxp-instruction_handler\r
+       db      'umaxv',0xf0\r
+       dw      ARM_instruction_umaxv-instruction_handler\r
+       db      'uminp',0xf0\r
+       dw      ARM_instruction_uminp-instruction_handler\r
+       db      'uminv',0xf0\r
+       dw      ARM_instruction_uminv-instruction_handler\r
+       db      'umlal',0xe0\r
+       dw      ARM_instruction_umlal-instruction_handler\r
+       db      'umlsl',0xf0\r
+       dw      ARM_instruction_umlsl-instruction_handler\r
+       db      'umulh',0xf0\r
+       dw      ARM_instruction_umulh-instruction_handler\r
+       db      'umull',0xe0\r
+       dw      ARM_instruction_umull-instruction_handler\r
+       db      'und.n',0xe4\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'und.w',0xe2\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'und~~',0x00\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'uqadd',0xf0\r
+       dw      ARM_instruction_uqadd-instruction_handler\r
+       db      'uqasx',0xe0\r
+       dw      ARM_instruction_uqasx-instruction_handler\r
+       db      'uqsax',0xe0\r
+       dw      ARM_instruction_uqsax-instruction_handler\r
+       db      'uqshl',0xf0\r
+       dw      ARM_instruction_uqshl-instruction_handler\r
+       db      'uqsub',0xf0\r
+       dw      ARM_instruction_uqsub-instruction_handler\r
+       db      'uqxtn',0xf0\r
+       dw      ARM_instruction_uqxtn-instruction_handler\r
+       db      'urddm',0xe0\r
+       dw      ARM_instruction_urddm-instruction_handler\r
+       db      'urddp',0xe0\r
+       dw      ARM_instruction_urddp-instruction_handler\r
+       db      'urddz',0xe0\r
+       dw      ARM_instruction_urddz-instruction_handler\r
+       db      'urdem',0xe0\r
+       dw      ARM_instruction_urdem-instruction_handler\r
+       db      'urdep',0xe0\r
+       dw      ARM_instruction_urdep-instruction_handler\r
+       db      'urdez',0xe0\r
+       dw      ARM_instruction_urdez-instruction_handler\r
+       db      'urdsm',0xe0\r
+       dw      ARM_instruction_urdsm-instruction_handler\r
+       db      'urdsp',0xe0\r
+       dw      ARM_instruction_urdsp-instruction_handler\r
+       db      'urdsz',0xe0\r
+       dw      ARM_instruction_urdsz-instruction_handler\r
+       db      'urshl',0xf0\r
+       dw      ARM_instruction_urshl-instruction_handler\r
+       db      'urshr',0xf0\r
+       dw      ARM_instruction_urshr-instruction_handler\r
+       db      'ursra',0xf0\r
+       dw      ARM_instruction_ursra-instruction_handler\r
+       db      'usad8',0xe0\r
+       dw      ARM_instruction_usad8-instruction_handler\r
+       db      'use16',0x00\r
+       dw      ARM_code16_directive-instruction_handler\r
+       db      'use32',0x00\r
+       dw      ARM_code32_directive-instruction_handler\r
+       db      'use64',0x00\r
+       dw      ARM_code64_directive-instruction_handler\r
+       db      'ushll',0xf0\r
+       dw      ARM_instruction_ushll-instruction_handler\r
+       db      'usub8',0xe0\r
+       dw      ARM_instruction_usub8-instruction_handler\r
+       db      'usubl',0xf0\r
+       dw      ARM_instruction_usubl-instruction_handler\r
+       db      'usubw',0xf0\r
+       dw      ARM_instruction_usubw-instruction_handler\r
+       db      'uxtab',0xe0\r
+       dw      ARM_instruction_uxtab-instruction_handler\r
+       db      'uxtah',0xe0\r
+       dw      ARM_instruction_uxtah-instruction_handler\r
+       db      'uxtl2',0xf0\r
+       dw      ARM_instruction_uxtl2-instruction_handler\r
+       db      'vpush',0xe0\r
+       dw      ARM_instruction_vpush-instruction_handler\r
+       db      'wabsb',0xe0\r
+       dw      ARM_instruction_wabsb-instruction_handler\r
+       db      'wabsh',0xe0\r
+       dw      ARM_instruction_wabsh-instruction_handler\r
+       db      'wabsw',0xe0\r
+       dw      ARM_instruction_wabsw-instruction_handler\r
+       db      'waccb',0xe0\r
+       dw      ARM_instruction_waccb-instruction_handler\r
+       db      'wacch',0xe0\r
+       dw      ARM_instruction_wacch-instruction_handler\r
+       db      'waccw',0xe0\r
+       dw      ARM_instruction_waccw-instruction_handler\r
+       db      'waddb',0xe0\r
+       dw      ARM_instruction_waddb-instruction_handler\r
+       db      'waddh',0xe0\r
+       dw      ARM_instruction_waddh-instruction_handler\r
+       db      'waddw',0xe0\r
+       dw      ARM_instruction_waddw-instruction_handler\r
+       db      'wandn',0xe0\r
+       dw      ARM_instruction_wandn-instruction_handler\r
+       db      'wavg4',0xe0\r
+       dw      ARM_instruction_wavg4-instruction_handler\r
+       db      'wfc~~',0x00\r
+       dw      ARM_instruction_wfc-instruction_handler\r
+       db      'wfe.n',0xe4\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfe.w',0xe2\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfe~~',0x00\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfi.n',0xe4\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wfi.w',0xe2\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wfi~~',0x00\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wfs~~',0x00\r
+       dw      ARM_instruction_wfs-instruction_handler\r
+       db      'while',0x00\r
+       dw      while_directive-instruction_handler\r
+       db      'wldrb',0xe0\r
+       dw      ARM_instruction_wldrb-instruction_handler\r
+       db      'wldrd',0xe0\r
+       dw      ARM_instruction_wldrd-instruction_handler\r
+       db      'wldrh',0xe0\r
+       dw      ARM_instruction_wldrh-instruction_handler\r
+       db      'wldrw',0xe0\r
+       dw      ARM_instruction_wldrw-instruction_handler\r
+       db      'wmacs',0xe0\r
+       dw      ARM_instruction_wmacs-instruction_handler\r
+       db      'wmacu',0xe0\r
+       dw      ARM_instruction_wmacu-instruction_handler\r
+       db      'wor~~',0x00\r
+       dw      ARM_instruction_wor-instruction_handler\r
+       db      'wrord',0xe0\r
+       dw      ARM_instruction_wrord-instruction_handler\r
+       db      'wrorh',0xe0\r
+       dw      ARM_instruction_wrorh-instruction_handler\r
+       db      'wrorw',0xe0\r
+       dw      ARM_instruction_wrorw-instruction_handler\r
+       db      'wsadb',0xe0\r
+       dw      ARM_instruction_wsadb-instruction_handler\r
+       db      'wsadh',0xe0\r
+       dw      ARM_instruction_wsadh-instruction_handler\r
+       db      'wslld',0xe0\r
+       dw      ARM_instruction_wslld-instruction_handler\r
+       db      'wsllh',0xe0\r
+       dw      ARM_instruction_wsllh-instruction_handler\r
+       db      'wsllw',0xe0\r
+       dw      ARM_instruction_wsllw-instruction_handler\r
+       db      'wsrad',0xe0\r
+       dw      ARM_instruction_wsrad-instruction_handler\r
+       db      'wsrah',0xe0\r
+       dw      ARM_instruction_wsrah-instruction_handler\r
+       db      'wsraw',0xe0\r
+       dw      ARM_instruction_wsraw-instruction_handler\r
+       db      'wsrld',0xe0\r
+       dw      ARM_instruction_wsrld-instruction_handler\r
+       db      'wsrlh',0xe0\r
+       dw      ARM_instruction_wsrlh-instruction_handler\r
+       db      'wsrlw',0xe0\r
+       dw      ARM_instruction_wsrlw-instruction_handler\r
+       db      'wstrb',0xe0\r
+       dw      ARM_instruction_wstrb-instruction_handler\r
+       db      'wstrd',0xe0\r
+       dw      ARM_instruction_wstrd-instruction_handler\r
+       db      'wstrh',0xe0\r
+       dw      ARM_instruction_wstrh-instruction_handler\r
+       db      'wstrw',0xe0\r
+       dw      ARM_instruction_wstrw-instruction_handler\r
+       db      'wsubb',0xe0\r
+       dw      ARM_instruction_wsubb-instruction_handler\r
+       db      'wsubh',0xe0\r
+       dw      ARM_instruction_wsubh-instruction_handler\r
+       db      'wsubw',0xe0\r
+       dw      ARM_instruction_wsubw-instruction_handler\r
+       db      'wzero',0xe0\r
+       dw      ARM_instruction_wzero-instruction_handler\r
+       db      'yield',0xe0\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      0\r
+instructions_6:\r
+       db      'abs~~d',0x00\r
+       dw      ARM_instruction_absd-instruction_handler\r
+       db      'abs~~e',0x00\r
+       dw      ARM_instruction_abse-instruction_handler\r
+       db      'abs~~s',0x00\r
+       dw      ARM_instruction_abss-instruction_handler\r
+       db      'acs~~d',0x00\r
+       dw      ARM_instruction_acsd-instruction_handler\r
+       db      'acs~~e',0x00\r
+       dw      ARM_instruction_acse-instruction_handler\r
+       db      'acs~~s',0x00\r
+       dw      ARM_instruction_acss-instruction_handler\r
+       db      'adcs.n',0xe5\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adcs.w',0xe3\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adcs~~',0x01\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc~~s',0x01\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'addhn2',0xf0\r
+       dw      ARM_instruction_addhn2-instruction_handler\r
+       db      'adds.n',0xe5\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adds.w',0xe3\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adds~~',0x01\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'addw~~',0x00\r
+       dw      ARM_instruction_addw-instruction_handler\r
+       db      'add~~s',0x01\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adf~~d',0x00\r
+       dw      ARM_instruction_adfd-instruction_handler\r
+       db      'adf~~e',0x00\r
+       dw      ARM_instruction_adfe-instruction_handler\r
+       db      'adf~~s',0x00\r
+       dw      ARM_instruction_adfs-instruction_handler\r
+       db      'aesd.8',0xf0\r
+       dw      ARM_instruction_aesd.8-instruction_handler\r
+       db      'aese.8',0xf0\r
+       dw      ARM_instruction_aese.8-instruction_handler\r
+       db      'aesimc',0xf0\r
+       dw      ARM_instruction_aesimc-instruction_handler\r
+       db      'ands.n',0xe5\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'ands.w',0xe3\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'ands~~',0x01\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and~~s',0x01\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asn~~d',0x00\r
+       dw      ARM_instruction_asnd-instruction_handler\r
+       db      'asn~~e',0x00\r
+       dw      ARM_instruction_asne-instruction_handler\r
+       db      'asn~~s',0x00\r
+       dw      ARM_instruction_asns-instruction_handler\r
+       db      'asrs.n',0xe5\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asrs.w',0xe3\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asrs~~',0x01\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr~~s',0x01\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'assert',0x00\r
+       dw      assert_directive-instruction_handler\r
+       db      'atn~~d',0x00\r
+       dw      ARM_instruction_atnd-instruction_handler\r
+       db      'atn~~e',0x00\r
+       dw      ARM_instruction_atne-instruction_handler\r
+       db      'atn~~s',0x00\r
+       dw      ARM_instruction_atns-instruction_handler\r
+       db      'bics.n',0xe5\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bics.w',0xe3\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bics~~',0x01\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic~~s',0x01\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bx~~.n',0x04\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'bx~~.w',0x02\r
+       dw      ARM_instruction_bx-instruction_handler\r
+       db      'cbnz.n',0xf4\r
+       dw      ARM_instruction_cbnz-instruction_handler\r
+       db      'cbnz.w',0xf2\r
+       dw      ARM_instruction_cbnz-instruction_handler\r
+       db      'cdp2~~',0x00\r
+       dw      ARM_instruction_cdp2-instruction_handler\r
+       db      'cfabsd',0xe0\r
+       dw      ARM_instruction_cfabsd-instruction_handler\r
+       db      'cfabss',0xe0\r
+       dw      ARM_instruction_cfabss-instruction_handler\r
+       db      'cfaddd',0xe0\r
+       dw      ARM_instruction_cfaddd-instruction_handler\r
+       db      'cfadds',0xe0\r
+       dw      ARM_instruction_cfadds-instruction_handler\r
+       db      'cfcmpd',0xe0\r
+       dw      ARM_instruction_cfcmpd-instruction_handler\r
+       db      'cfcmps',0xe0\r
+       dw      ARM_instruction_cfcmps-instruction_handler\r
+       db      'cfcpyd',0xe0\r
+       dw      ARM_instruction_cfcpyd-instruction_handler\r
+       db      'cfcpys',0xe0\r
+       dw      ARM_instruction_cfcpys-instruction_handler\r
+       db      'cfldrd',0xe0\r
+       dw      ARM_instruction_cfldrd-instruction_handler\r
+       db      'cfldrs',0xe0\r
+       dw      ARM_instruction_cfldrs-instruction_handler\r
+       db      'cfmuld',0xe0\r
+       dw      ARM_instruction_cfmuld-instruction_handler\r
+       db      'cfmuls',0xe0\r
+       dw      ARM_instruction_cfmuls-instruction_handler\r
+       db      'cfmvrs',0xe0\r
+       dw      ARM_instruction_cfmvrs-instruction_handler\r
+       db      'cfmvsr',0xe0\r
+       dw      ARM_instruction_cfmvsr-instruction_handler\r
+       db      'cfnegd',0xe0\r
+       dw      ARM_instruction_cfnegd-instruction_handler\r
+       db      'cfnegs',0xe0\r
+       dw      ARM_instruction_cfnegs-instruction_handler\r
+       db      'cfsh32',0xe0\r
+       dw      ARM_instruction_cfsh32-instruction_handler\r
+       db      'cfsh64',0xe0\r
+       dw      ARM_instruction_cfsh64-instruction_handler\r
+       db      'cfstrd',0xe0\r
+       dw      ARM_instruction_cfstrd-instruction_handler\r
+       db      'cfstrs',0xe0\r
+       dw      ARM_instruction_cfstrs-instruction_handler\r
+       db      'cfsubd',0xe0\r
+       dw      ARM_instruction_cfsubd-instruction_handler\r
+       db      'cfsubs',0xe0\r
+       dw      ARM_instruction_cfsubs-instruction_handler\r
+       db      'chka~~',0x00\r
+       dw      ARM_instruction_chka-instruction_handler\r
+       db      'cmfe~~',0x00\r
+       dw      ARM_instruction_cmfe-instruction_handler\r
+       db      'cmnp~~',0x00\r
+       dw      ARM_instruction_cmnp-instruction_handler\r
+       db      'cmn~~p',0x00\r
+       dw      ARM_instruction_cmnp-instruction_handler\r
+       db      'cmpp~~',0x00\r
+       dw      ARM_instruction_cmpp-instruction_handler\r
+       db      'cmp~~p',0x00\r
+       dw      ARM_instruction_cmpp-instruction_handler\r
+       db      'cnfe~~',0x00\r
+       dw      ARM_instruction_cnfe-instruction_handler\r
+       db      'code16',0x00\r
+       dw      ARM_code16_directive-instruction_handler\r
+       db      'code32',0x00\r
+       dw      ARM_code32_directive-instruction_handler\r
+       db      'code64',0x00\r
+       dw      ARM_code64_directive-instruction_handler\r
+       db      'cos~~d',0x00\r
+       dw      ARM_instruction_cosd-instruction_handler\r
+       db      'cos~~e',0x00\r
+       dw      ARM_instruction_cose-instruction_handler\r
+       db      'cos~~s',0x00\r
+       dw      ARM_instruction_coss-instruction_handler\r
+       db      'crc32b',0xf0\r
+       dw      ARM_instruction_crc32b-instruction_handler\r
+       db      'crc32h',0xf0\r
+       dw      ARM_instruction_crc32h-instruction_handler\r
+       db      'crc32w',0xf0\r
+       dw      ARM_instruction_crc32w-instruction_handler\r
+       db      'crc32x',0xf0\r
+       dw      ARM_instruction_crc32x-instruction_handler\r
+       db      'dvf~~d',0x00\r
+       dw      ARM_instruction_dvfd-instruction_handler\r
+       db      'dvf~~e',0x00\r
+       dw      ARM_instruction_dvfe-instruction_handler\r
+       db      'dvf~~s',0x00\r
+       dw      ARM_instruction_dvfs-instruction_handler\r
+       db      'enterx',0xf0\r
+       dw      ARM_instruction_enterx-instruction_handler\r
+       db      'eors.n',0xe5\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eors.w',0xe3\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eors~~',0x01\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor~~s',0x01\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eret~~',0x00\r
+       dw      ARM_instruction_eret-instruction_handler\r
+       db      'exp~~d',0x00\r
+       dw      ARM_instruction_expd-instruction_handler\r
+       db      'exp~~e',0x00\r
+       dw      ARM_instruction_expe-instruction_handler\r
+       db      'exp~~s',0x00\r
+       dw      ARM_instruction_exps-instruction_handler\r
+       db      'fccmpe',0xf0\r
+       dw      ARM_instruction_fccmpe-instruction_handler\r
+       db      'fcmped',0xe0\r
+       dw      ARM_instruction_fcmped-instruction_handler\r
+       db      'fcmpes',0xe0\r
+       dw      ARM_instruction_fcmpes-instruction_handler\r
+       db      'fcmpzd',0xe0\r
+       dw      ARM_instruction_fcmpzd-instruction_handler\r
+       db      'fcmpzs',0xe0\r
+       dw      ARM_instruction_fcmpzs-instruction_handler\r
+       db      'fcvtas',0xf0\r
+       dw      ARM_instruction_fcvtas-instruction_handler\r
+       db      'fcvtau',0xf0\r
+       dw      ARM_instruction_fcvtau-instruction_handler\r
+       db      'fcvtds',0xe0\r
+       dw      ARM_instruction_fcvtds-instruction_handler\r
+       db      'fcvtl2',0xf0\r
+       dw      ARM_instruction_fcvtl2-instruction_handler\r
+       db      'fcvtms',0xf0\r
+       dw      ARM_instruction_fcvtms-instruction_handler\r
+       db      'fcvtmu',0xf0\r
+       dw      ARM_instruction_fcvtmu-instruction_handler\r
+       db      'fcvtn2',0xf0\r
+       dw      ARM_instruction_fcvtn2-instruction_handler\r
+       db      'fcvtns',0xf0\r
+       dw      ARM_instruction_fcvtns-instruction_handler\r
+       db      'fcvtnu',0xf0\r
+       dw      ARM_instruction_fcvtnu-instruction_handler\r
+       db      'fcvtps',0xf0\r
+       dw      ARM_instruction_fcvtps-instruction_handler\r
+       db      'fcvtpu',0xf0\r
+       dw      ARM_instruction_fcvtpu-instruction_handler\r
+       db      'fcvtsd',0xe0\r
+       dw      ARM_instruction_fcvtsd-instruction_handler\r
+       db      'fcvtxn',0xf0\r
+       dw      ARM_instruction_fcvtxn-instruction_handler\r
+       db      'fcvtzs',0xf0\r
+       dw      ARM_instruction_fcvtzs-instruction_handler\r
+       db      'fcvtzu',0xf0\r
+       dw      ARM_instruction_fcvtzu-instruction_handler\r
+       db      'fdv~~d',0x00\r
+       dw      ARM_instruction_fdvd-instruction_handler\r
+       db      'fdv~~e',0x00\r
+       dw      ARM_instruction_fdve-instruction_handler\r
+       db      'fdv~~s',0x00\r
+       dw      ARM_instruction_fdvs-instruction_handler\r
+       db      'fix~~m',0x00\r
+       dw      ARM_instruction_fixm-instruction_handler\r
+       db      'fix~~p',0x00\r
+       dw      ARM_instruction_fixp-instruction_handler\r
+       db      'fix~~z',0x00\r
+       dw      ARM_instruction_fixz-instruction_handler\r
+       db      'fldd~~',0x00\r
+       dw      ARM_instruction_fldd-instruction_handler\r
+       db      'flds~~',0x00\r
+       dw      ARM_instruction_flds-instruction_handler\r
+       db      'flt~~d',0x00\r
+       dw      ARM_instruction_fltd-instruction_handler\r
+       db      'flt~~e',0x00\r
+       dw      ARM_instruction_flte-instruction_handler\r
+       db      'flt~~s',0x00\r
+       dw      ARM_instruction_flts-instruction_handler\r
+       db      'fmaxnm',0xf0\r
+       dw      ARM_instruction_fmaxnm-instruction_handler\r
+       db      'fminnm',0xf0\r
+       dw      ARM_instruction_fminnm-instruction_handler\r
+       db      'fml~~d',0x00\r
+       dw      ARM_instruction_fmld-instruction_handler\r
+       db      'fml~~e',0x00\r
+       dw      ARM_instruction_fmle-instruction_handler\r
+       db      'fml~~s',0x00\r
+       dw      ARM_instruction_fmls-instruction_handler\r
+       db      'fmrs~~',0x00\r
+       dw      ARM_instruction_fmrs-instruction_handler\r
+       db      'fmrx~~',0x00\r
+       dw      ARM_instruction_fmrx-instruction_handler\r
+       db      'fmsr~~',0x00\r
+       dw      ARM_instruction_fmsr-instruction_handler\r
+       db      'fmstat',0xe0\r
+       dw      ARM_instruction_fmstat-instruction_handler\r
+       db      'fmxr~~',0x00\r
+       dw      ARM_instruction_fmxr-instruction_handler\r
+       db      'fnmacd',0xe0\r
+       dw      ARM_instruction_fnmacd-instruction_handler\r
+       db      'fnmacs',0xe0\r
+       dw      ARM_instruction_fnmacs-instruction_handler\r
+       db      'fnmadd',0xf0\r
+       dw      ARM_instruction_fnmadd-instruction_handler\r
+       db      'fnmscd',0xe0\r
+       dw      ARM_instruction_fnmscd-instruction_handler\r
+       db      'fnmscs',0xe0\r
+       dw      ARM_instruction_fnmscs-instruction_handler\r
+       db      'fnmsub',0xf0\r
+       dw      ARM_instruction_fnmsub-instruction_handler\r
+       db      'fnmuld',0xe0\r
+       dw      ARM_instruction_fnmuld-instruction_handler\r
+       db      'fnmuls',0xe0\r
+       dw      ARM_instruction_fnmuls-instruction_handler\r
+       db      'format',0x00\r
+       dw      ARM_format_directive-instruction_handler\r
+       db      'frd~~d',0x00\r
+       dw      ARM_instruction_frdd-instruction_handler\r
+       db      'frd~~e',0x00\r
+       dw      ARM_instruction_frde-instruction_handler\r
+       db      'frd~~s',0x00\r
+       dw      ARM_instruction_frds-instruction_handler\r
+       db      'frecpe',0xf0\r
+       dw      ARM_instruction_frecpe-instruction_handler\r
+       db      'frecps',0xf0\r
+       dw      ARM_instruction_frecps-instruction_handler\r
+       db      'frecpx',0xf0\r
+       dw      ARM_instruction_frecpx-instruction_handler\r
+       db      'frinta',0xf0\r
+       dw      ARM_instruction_frinta-instruction_handler\r
+       db      'frinti',0xf0\r
+       dw      ARM_instruction_frinti-instruction_handler\r
+       db      'frintm',0xf0\r
+       dw      ARM_instruction_frintm-instruction_handler\r
+       db      'frintn',0xf0\r
+       dw      ARM_instruction_frintn-instruction_handler\r
+       db      'frintp',0xf0\r
+       dw      ARM_instruction_frintp-instruction_handler\r
+       db      'frintx',0xf0\r
+       dw      ARM_instruction_frintx-instruction_handler\r
+       db      'frintz',0xf0\r
+       dw      ARM_instruction_frintz-instruction_handler\r
+       db      'fshtod',0xe0\r
+       dw      ARM_instruction_fshtod-instruction_handler\r
+       db      'fshtos',0xe0\r
+       dw      ARM_instruction_fshtos-instruction_handler\r
+       db      'fsitod',0xe0\r
+       dw      ARM_instruction_fsitod-instruction_handler\r
+       db      'fsitos',0xe0\r
+       dw      ARM_instruction_fsitos-instruction_handler\r
+       db      'fsltod',0xe0\r
+       dw      ARM_instruction_fsltod-instruction_handler\r
+       db      'fsltos',0xe0\r
+       dw      ARM_instruction_fsltos-instruction_handler\r
+       db      'fsqrtd',0xe0\r
+       dw      ARM_instruction_fsqrtd-instruction_handler\r
+       db      'fsqrts',0xe0\r
+       dw      ARM_instruction_fsqrts-instruction_handler\r
+       db      'fstd~~',0x00\r
+       dw      ARM_instruction_fstd-instruction_handler\r
+       db      'fsts~~',0x00\r
+       dw      ARM_instruction_fsts-instruction_handler\r
+       db      'ftoshd',0xe0\r
+       dw      ARM_instruction_ftoshd-instruction_handler\r
+       db      'ftoshs',0xe0\r
+       dw      ARM_instruction_ftoshs-instruction_handler\r
+       db      'ftosid',0xe0\r
+       dw      ARM_instruction_ftosid-instruction_handler\r
+       db      'ftosis',0xe0\r
+       dw      ARM_instruction_ftosis-instruction_handler\r
+       db      'ftosld',0xe0\r
+       dw      ARM_instruction_ftosld-instruction_handler\r
+       db      'ftosls',0xe0\r
+       dw      ARM_instruction_ftosls-instruction_handler\r
+       db      'ftouhd',0xe0\r
+       dw      ARM_instruction_ftouhd-instruction_handler\r
+       db      'ftouhs',0xe0\r
+       dw      ARM_instruction_ftouhs-instruction_handler\r
+       db      'ftouid',0xe0\r
+       dw      ARM_instruction_ftouid-instruction_handler\r
+       db      'ftouis',0xe0\r
+       dw      ARM_instruction_ftouis-instruction_handler\r
+       db      'ftould',0xe0\r
+       dw      ARM_instruction_ftould-instruction_handler\r
+       db      'ftouls',0xe0\r
+       dw      ARM_instruction_ftouls-instruction_handler\r
+       db      'fuhtod',0xe0\r
+       dw      ARM_instruction_fuhtod-instruction_handler\r
+       db      'fuhtos',0xe0\r
+       dw      ARM_instruction_fuhtos-instruction_handler\r
+       db      'fuitod',0xe0\r
+       dw      ARM_instruction_fuitod-instruction_handler\r
+       db      'fuitos',0xe0\r
+       dw      ARM_instruction_fuitos-instruction_handler\r
+       db      'fultod',0xe0\r
+       dw      ARM_instruction_fultod-instruction_handler\r
+       db      'fultos',0xe0\r
+       dw      ARM_instruction_fultos-instruction_handler\r
+       db      'hblp~~',0x00\r
+       dw      ARM_instruction_hblp-instruction_handler\r
+       db      'itauto',0x00\r
+       dw      ARM_itauto_directive-instruction_handler\r
+       db      'ldab~~',0x00\r
+       dw      ARM_instruction_ldab-instruction_handler\r
+       db      'ldaexb',0xe0\r
+       dw      ARM_instruction_ldaexb-instruction_handler\r
+       db      'ldaexd',0xe0\r
+       dw      ARM_instruction_ldaexd-instruction_handler\r
+       db      'ldaexh',0xe0\r
+       dw      ARM_instruction_ldaexh-instruction_handler\r
+       db      'ldah~~',0x00\r
+       dw      ARM_instruction_ldah-instruction_handler\r
+       db      'ldaxrb',0xf0\r
+       dw      ARM_instruction_ldaxrb-instruction_handler\r
+       db      'ldaxrh',0xf0\r
+       dw      ARM_instruction_ldaxrh-instruction_handler\r
+       db      'lda~~b',0x00\r
+       dw      ARM_instruction_ldab-instruction_handler\r
+       db      'lda~~h',0x00\r
+       dw      ARM_instruction_ldah-instruction_handler\r
+       db      'ldc2~~',0x00\r
+       dw      ARM_instruction_ldc2-instruction_handler\r
+       db      'ldcl~~',0x00\r
+       dw      ARM_instruction_ldcl-instruction_handler\r
+       db      'ldc~~l',0x00\r
+       dw      ARM_instruction_ldcl-instruction_handler\r
+       db      'ldf~~d',0x00\r
+       dw      ARM_instruction_ldfd-instruction_handler\r
+       db      'ldf~~e',0x00\r
+       dw      ARM_instruction_ldfe-instruction_handler\r
+       db      'ldf~~p',0x00\r
+       dw      ARM_instruction_ldfp-instruction_handler\r
+       db      'ldf~~s',0x00\r
+       dw      ARM_instruction_ldfs-instruction_handler\r
+       db      'ldrb.n',0xe4\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrb.w',0xe2\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrb~~',0x00\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrd~~',0x00\r
+       dw      ARM_instruction_ldrd-instruction_handler\r
+       db      'ldrexb',0xe0\r
+       dw      ARM_instruction_ldrexb-instruction_handler\r
+       db      'ldrexd',0xe0\r
+       dw      ARM_instruction_ldrexd-instruction_handler\r
+       db      'ldrexh',0xe0\r
+       dw      ARM_instruction_ldrexh-instruction_handler\r
+       db      'ldrh.n',0xe4\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrh.w',0xe2\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrh~~',0x00\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrsbt',0xe0\r
+       dw      ARM_instruction_ldrsbt-instruction_handler\r
+       db      'ldrsht',0xe0\r
+       dw      ARM_instruction_ldrsht-instruction_handler\r
+       db      'ldrt~~',0x00\r
+       dw      ARM_instruction_ldrt-instruction_handler\r
+       db      'ldr~~b',0x00\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldr~~d',0x00\r
+       dw      ARM_instruction_ldrd-instruction_handler\r
+       db      'ldr~~h',0x00\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldr~~t',0x00\r
+       dw      ARM_instruction_ldrt-instruction_handler\r
+       db      'ldtrsb',0xf0\r
+       dw      ARM_instruction_ldtrsb-instruction_handler\r
+       db      'ldtrsh',0xf0\r
+       dw      ARM_instruction_ldtrsh-instruction_handler\r
+       db      'ldtrsw',0xf0\r
+       dw      ARM_instruction_ldtrsw-instruction_handler\r
+       db      'ldursb',0xf0\r
+       dw      ARM_instruction_ldursb-instruction_handler\r
+       db      'ldursh',0xf0\r
+       dw      ARM_instruction_ldursh-instruction_handler\r
+       db      'ldursw',0xf0\r
+       dw      ARM_instruction_ldursw-instruction_handler\r
+       db      'leavex',0xf0\r
+       dw      ARM_instruction_leavex-instruction_handler\r
+       db      'lgn~~d',0x00\r
+       dw      ARM_instruction_lgnd-instruction_handler\r
+       db      'lgn~~e',0x00\r
+       dw      ARM_instruction_lgne-instruction_handler\r
+       db      'lgn~~s',0x00\r
+       dw      ARM_instruction_lgns-instruction_handler\r
+       db      'log~~d',0x00\r
+       dw      ARM_instruction_logd-instruction_handler\r
+       db      'log~~e',0x00\r
+       dw      ARM_instruction_loge-instruction_handler\r
+       db      'log~~s',0x00\r
+       dw      ARM_instruction_logs-instruction_handler\r
+       db      'lsls.n',0xe5\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsls.w',0xe3\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsls~~',0x01\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl~~s',0x01\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsrs.n',0xe5\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsrs.w',0xe3\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsrs~~',0x01\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr~~s',0x01\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'mcr2~~',0x00\r
+       dw      ARM_instruction_mcr2-instruction_handler\r
+       db      'mcrr~~',0x00\r
+       dw      ARM_instruction_mcrr-instruction_handler\r
+       db      'mlas~~',0x01\r
+       dw      ARM_instruction_mla-instruction_handler\r
+       db      'mla~~s',0x01\r
+       dw      ARM_instruction_mla-instruction_handler\r
+       db      'mnf~~d',0x00\r
+       dw      ARM_instruction_mnfd-instruction_handler\r
+       db      'mnf~~e',0x00\r
+       dw      ARM_instruction_mnfe-instruction_handler\r
+       db      'mnf~~s',0x00\r
+       dw      ARM_instruction_mnfs-instruction_handler\r
+       db      'movs.n',0xe5\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'movs.w',0xe3\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'movs~~',0x01\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'movt~~',0x00\r
+       dw      ARM_instruction_movt-instruction_handler\r
+       db      'movw~~',0x00\r
+       dw      ARM_instruction_movw-instruction_handler\r
+       db      'mov~~s',0x01\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mrc2~~',0x00\r
+       dw      ARM_instruction_mrc2-instruction_handler\r
+       db      'mrrc~~',0x00\r
+       dw      ARM_instruction_mrrc-instruction_handler\r
+       db      'muf~~d',0x00\r
+       dw      ARM_instruction_mufd-instruction_handler\r
+       db      'muf~~e',0x00\r
+       dw      ARM_instruction_mufe-instruction_handler\r
+       db      'muf~~s',0x00\r
+       dw      ARM_instruction_mufs-instruction_handler\r
+       db      'muls.n',0xe5\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'muls.w',0xe3\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'muls~~',0x01\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul~~s',0x01\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvf~~d',0x00\r
+       dw      ARM_instruction_mvfd-instruction_handler\r
+       db      'mvf~~e',0x00\r
+       dw      ARM_instruction_mvfe-instruction_handler\r
+       db      'mvf~~s',0x00\r
+       dw      ARM_instruction_mvfs-instruction_handler\r
+       db      'mvns.n',0xe5\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvns.w',0xe3\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvns~~',0x01\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn~~s',0x01\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'negs.n',0xe5\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'negs.w',0xe3\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'negs~~',0x01\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg~~s',0x01\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'nrm~~d',0x00\r
+       dw      ARM_instruction_nrmd-instruction_handler\r
+       db      'nrm~~e',0x00\r
+       dw      ARM_instruction_nrme-instruction_handler\r
+       db      'nrm~~s',0x00\r
+       dw      ARM_instruction_nrms-instruction_handler\r
+       db      'orns~~',0x01\r
+       dw      ARM_instruction_orn-instruction_handler\r
+       db      'orn~~s',0x01\r
+       dw      ARM_instruction_orn-instruction_handler\r
+       db      'orrs.n',0xe5\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orrs.w',0xe3\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orrs~~',0x01\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr~~s',0x01\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'pldw~~',0x00\r
+       dw      ARM_instruction_pldw-instruction_handler\r
+       db      'pmull2',0xf0\r
+       dw      ARM_instruction_pmull2-instruction_handler\r
+       db      'pol~~d',0x00\r
+       dw      ARM_instruction_pold-instruction_handler\r
+       db      'pol~~e',0x00\r
+       dw      ARM_instruction_pole-instruction_handler\r
+       db      'pol~~s',0x00\r
+       dw      ARM_instruction_pols-instruction_handler\r
+       db      'pow~~d',0x00\r
+       dw      ARM_instruction_powd-instruction_handler\r
+       db      'pow~~e',0x00\r
+       dw      ARM_instruction_powe-instruction_handler\r
+       db      'pow~~s',0x00\r
+       dw      ARM_instruction_pows-instruction_handler\r
+       db      'public',0x00\r
+       dw      public_directive-instruction_handler\r
+       db      'push.n',0xe4\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'push.w',0xe2\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'push~~',0x00\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'qadd16',0xe0\r
+       dw      ARM_instruction_qadd16-instruction_handler\r
+       db      'qadd~~',0x00\r
+       dw      ARM_instruction_qadd-instruction_handler\r
+       db      'qasx~~',0x00\r
+       dw      ARM_instruction_qasx-instruction_handler\r
+       db      'qsax~~',0x00\r
+       dw      ARM_instruction_qsax-instruction_handler\r
+       db      'qsub16',0xe0\r
+       dw      ARM_instruction_qsub16-instruction_handler\r
+       db      'qsub~~',0x00\r
+       dw      ARM_instruction_qsub-instruction_handler\r
+       db      'raddhn',0xf0\r
+       dw      ARM_instruction_raddhn-instruction_handler\r
+       db      'rbit~~',0x00\r
+       dw      ARM_instruction_rbit-instruction_handler\r
+       db      'rdf~~d',0x00\r
+       dw      ARM_instruction_rdfd-instruction_handler\r
+       db      'rdf~~e',0x00\r
+       dw      ARM_instruction_rdfe-instruction_handler\r
+       db      'rdf~~s',0x00\r
+       dw      ARM_instruction_rdfs-instruction_handler\r
+       db      'repeat',0x00\r
+       dw      repeat_directive-instruction_handler\r
+       db      'rmf~~d',0x00\r
+       dw      ARM_instruction_rmfd-instruction_handler\r
+       db      'rmf~~e',0x00\r
+       dw      ARM_instruction_rmfe-instruction_handler\r
+       db      'rmf~~s',0x00\r
+       dw      ARM_instruction_rmfs-instruction_handler\r
+       db      'rnd~~d',0x00\r
+       dw      ARM_instruction_rndd-instruction_handler\r
+       db      'rnd~~e',0x00\r
+       dw      ARM_instruction_rnde-instruction_handler\r
+       db      'rnd~~s',0x00\r
+       dw      ARM_instruction_rnds-instruction_handler\r
+       db      'rors.n',0xe5\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rors.w',0xe3\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rors~~',0x01\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror~~s',0x01\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rpw~~d',0x00\r
+       dw      ARM_instruction_rpwd-instruction_handler\r
+       db      'rpw~~e',0x00\r
+       dw      ARM_instruction_rpwe-instruction_handler\r
+       db      'rpw~~s',0x00\r
+       dw      ARM_instruction_rpws-instruction_handler\r
+       db      'rrxs~~',0x01\r
+       dw      ARM_instruction_rrx-instruction_handler\r
+       db      'rrx~~s',0x01\r
+       dw      ARM_instruction_rrx-instruction_handler\r
+       db      'rsbs.n',0xe5\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsbs.w',0xe3\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsbs~~',0x01\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb~~s',0x01\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rscs~~',0x01\r
+       dw      ARM_instruction_rsc-instruction_handler\r
+       db      'rsc~~s',0x01\r
+       dw      ARM_instruction_rsc-instruction_handler\r
+       db      'rsf~~d',0x00\r
+       dw      ARM_instruction_rsfd-instruction_handler\r
+       db      'rsf~~e',0x00\r
+       dw      ARM_instruction_rsfe-instruction_handler\r
+       db      'rsf~~s',0x00\r
+       dw      ARM_instruction_rsfs-instruction_handler\r
+       db      'rshrn2',0xf0\r
+       dw      ARM_instruction_rshrn2-instruction_handler\r
+       db      'rsubhn',0xf0\r
+       dw      ARM_instruction_rsubhn-instruction_handler\r
+       db      'sabal2',0xf0\r
+       dw      ARM_instruction_sabal2-instruction_handler\r
+       db      'sabdl2',0xf0\r
+       dw      ARM_instruction_sabdl2-instruction_handler\r
+       db      'sadalp',0xf0\r
+       dw      ARM_instruction_sadalp-instruction_handler\r
+       db      'sadd16',0xe0\r
+       dw      ARM_instruction_sadd16-instruction_handler\r
+       db      'saddl2',0xf0\r
+       dw      ARM_instruction_saddl2-instruction_handler\r
+       db      'saddlp',0xf0\r
+       dw      ARM_instruction_saddlp-instruction_handler\r
+       db      'saddlv',0xf0\r
+       dw      ARM_instruction_saddlv-instruction_handler\r
+       db      'saddw2',0xf0\r
+       dw      ARM_instruction_saddw2-instruction_handler\r
+       db      'sasx~~',0x00\r
+       dw      ARM_instruction_sasx-instruction_handler\r
+       db      'sbcs.n',0xe5\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbcs.w',0xe3\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbcs~~',0x01\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc~~s',0x01\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbfx~~',0x00\r
+       dw      ARM_instruction_sbfx-instruction_handler\r
+       db      'sdiv~~',0x00\r
+       dw      ARM_instruction_sdiv-instruction_handler\r
+       db      'setend',0xf0\r
+       dw      ARM_instruction_setend-instruction_handler\r
+       db      'sevl.n',0xe4\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'sevl.w',0xe2\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'sevl~~',0x00\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'shadd8',0xe0\r
+       dw      ARM_instruction_shadd8-instruction_handler\r
+       db      'shsub8',0xe0\r
+       dw      ARM_instruction_shsub8-instruction_handler\r
+       db      'sin~~d',0x00\r
+       dw      ARM_instruction_sind-instruction_handler\r
+       db      'sin~~e',0x00\r
+       dw      ARM_instruction_sine-instruction_handler\r
+       db      'sin~~s',0x00\r
+       dw      ARM_instruction_sins-instruction_handler\r
+       db      'smaddl',0xf0\r
+       dw      ARM_instruction_smaddl-instruction_handler\r
+       db      'smlabb',0xe0\r
+       dw      ARM_instruction_smlabb-instruction_handler\r
+       db      'smlabt',0xe0\r
+       dw      ARM_instruction_smlabt-instruction_handler\r
+       db      'smladx',0xe0\r
+       dw      ARM_instruction_smladx-instruction_handler\r
+       db      'smlal2',0xf0\r
+       dw      ARM_instruction_smlal2-instruction_handler\r
+       db      'smlald',0xe0\r
+       dw      ARM_instruction_smlald-instruction_handler\r
+       db      'smlals',0xe1\r
+       dw      ARM_instruction_smlal-instruction_handler\r
+       db      'smlatb',0xe0\r
+       dw      ARM_instruction_smlatb-instruction_handler\r
+       db      'smlatt',0xe0\r
+       dw      ARM_instruction_smlatt-instruction_handler\r
+       db      'smlawb',0xe0\r
+       dw      ARM_instruction_smlawb-instruction_handler\r
+       db      'smlawt',0xe0\r
+       dw      ARM_instruction_smlawt-instruction_handler\r
+       db      'smlsdx',0xe0\r
+       dw      ARM_instruction_smlsdx-instruction_handler\r
+       db      'smlsl2',0xf0\r
+       dw      ARM_instruction_smlsl2-instruction_handler\r
+       db      'smlsld',0xe0\r
+       dw      ARM_instruction_smlsld-instruction_handler\r
+       db      'smmlar',0xe0\r
+       dw      ARM_instruction_smmlar-instruction_handler\r
+       db      'smmlsr',0xe0\r
+       dw      ARM_instruction_smmlsr-instruction_handler\r
+       db      'smmulr',0xe0\r
+       dw      ARM_instruction_smmulr-instruction_handler\r
+       db      'smnegl',0xf0\r
+       dw      ARM_instruction_smnegl-instruction_handler\r
+       db      'smsubl',0xf0\r
+       dw      ARM_instruction_smsubl-instruction_handler\r
+       db      'smuadx',0xe0\r
+       dw      ARM_instruction_smuadx-instruction_handler\r
+       db      'smulbb',0xe0\r
+       dw      ARM_instruction_smulbb-instruction_handler\r
+       db      'smulbt',0xe0\r
+       dw      ARM_instruction_smulbt-instruction_handler\r
+       db      'smull2',0xf0\r
+       dw      ARM_instruction_smull2-instruction_handler\r
+       db      'smulls',0xe1\r
+       dw      ARM_instruction_smull-instruction_handler\r
+       db      'smultb',0xe0\r
+       dw      ARM_instruction_smultb-instruction_handler\r
+       db      'smultt',0xe0\r
+       dw      ARM_instruction_smultt-instruction_handler\r
+       db      'smulwb',0xe0\r
+       dw      ARM_instruction_smulwb-instruction_handler\r
+       db      'smulwt',0xe0\r
+       dw      ARM_instruction_smulwt-instruction_handler\r
+       db      'smusdx',0xe0\r
+       dw      ARM_instruction_smusdx-instruction_handler\r
+       db      'sqrshl',0xf0\r
+       dw      ARM_instruction_sqrshl-instruction_handler\r
+       db      'sqshlu',0xf0\r
+       dw      ARM_instruction_sqshlu-instruction_handler\r
+       db      'sqshrn',0xf0\r
+       dw      ARM_instruction_sqshrn-instruction_handler\r
+       db      'sqt~~d',0x00\r
+       dw      ARM_instruction_sqtd-instruction_handler\r
+       db      'sqt~~e',0x00\r
+       dw      ARM_instruction_sqte-instruction_handler\r
+       db      'sqt~~s',0x00\r
+       dw      ARM_instruction_sqts-instruction_handler\r
+       db      'sqxtn2',0xf0\r
+       dw      ARM_instruction_sqxtn2-instruction_handler\r
+       db      'sqxtun',0xf0\r
+       dw      ARM_instruction_sqxtun-instruction_handler\r
+       db      'srhadd',0xf0\r
+       dw      ARM_instruction_srhadd-instruction_handler\r
+       db      'ssat16',0xe0\r
+       dw      ARM_instruction_ssat16-instruction_handler\r
+       db      'ssat~~',0x00\r
+       dw      ARM_instruction_ssat-instruction_handler\r
+       db      'ssax~~',0x00\r
+       dw      ARM_instruction_ssax-instruction_handler\r
+       db      'sshll2',0xf0\r
+       dw      ARM_instruction_sshll2-instruction_handler\r
+       db      'ssub16',0xe0\r
+       dw      ARM_instruction_ssub16-instruction_handler\r
+       db      'ssubl2',0xf0\r
+       dw      ARM_instruction_ssubl2-instruction_handler\r
+       db      'ssubw2',0xf0\r
+       dw      ARM_instruction_ssubw2-instruction_handler\r
+       db      'stc2~~',0x00\r
+       dw      ARM_instruction_stc2-instruction_handler\r
+       db      'stcl~~',0x00\r
+       dw      ARM_instruction_stcl-instruction_handler\r
+       db      'stc~~l',0x00\r
+       dw      ARM_instruction_stcl-instruction_handler\r
+       db      'stf~~d',0x00\r
+       dw      ARM_instruction_stfd-instruction_handler\r
+       db      'stf~~e',0x00\r
+       dw      ARM_instruction_stfe-instruction_handler\r
+       db      'stf~~p',0x00\r
+       dw      ARM_instruction_stfp-instruction_handler\r
+       db      'stf~~s',0x00\r
+       dw      ARM_instruction_stfs-instruction_handler\r
+       db      'stlb~~',0x00\r
+       dw      ARM_instruction_stlb-instruction_handler\r
+       db      'stlexb',0xe0\r
+       dw      ARM_instruction_stlexb-instruction_handler\r
+       db      'stlexd',0xe0\r
+       dw      ARM_instruction_stlexd-instruction_handler\r
+       db      'stlexh',0xe0\r
+       dw      ARM_instruction_stlexh-instruction_handler\r
+       db      'stlh~~',0x00\r
+       dw      ARM_instruction_stlh-instruction_handler\r
+       db      'stlxrb',0xf0\r
+       dw      ARM_instruction_stlxrb-instruction_handler\r
+       db      'stlxrh',0xf0\r
+       dw      ARM_instruction_stlxrh-instruction_handler\r
+       db      'stl~~b',0x00\r
+       dw      ARM_instruction_stlb-instruction_handler\r
+       db      'stl~~h',0x00\r
+       dw      ARM_instruction_stlh-instruction_handler\r
+       db      'strb.n',0xe4\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strb.w',0xe2\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strb~~',0x00\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strd~~',0x00\r
+       dw      ARM_instruction_strd-instruction_handler\r
+       db      'strexb',0xe0\r
+       dw      ARM_instruction_strexb-instruction_handler\r
+       db      'strexd',0xe0\r
+       dw      ARM_instruction_strexd-instruction_handler\r
+       db      'strexh',0xe0\r
+       dw      ARM_instruction_strexh-instruction_handler\r
+       db      'strh.n',0xe4\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'strh.w',0xe2\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'strh~~',0x00\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'strt~~',0x00\r
+       dw      ARM_instruction_strt-instruction_handler\r
+       db      'str~~b',0x00\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'str~~d',0x00\r
+       dw      ARM_instruction_strd-instruction_handler\r
+       db      'str~~h',0x00\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'str~~t',0x00\r
+       dw      ARM_instruction_strt-instruction_handler\r
+       db      'subhn2',0xf0\r
+       dw      ARM_instruction_subhn2-instruction_handler\r
+       db      'subs.n',0xe5\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subs.w',0xe3\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subs~~',0x01\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subw~~',0x00\r
+       dw      ARM_instruction_subw-instruction_handler\r
+       db      'sub~~s',0x01\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'suf~~d',0x00\r
+       dw      ARM_instruction_sufd-instruction_handler\r
+       db      'suf~~e',0x00\r
+       dw      ARM_instruction_sufe-instruction_handler\r
+       db      'suf~~s',0x00\r
+       dw      ARM_instruction_sufs-instruction_handler\r
+       db      'suqadd',0xf0\r
+       dw      ARM_instruction_suqadd-instruction_handler\r
+       db      'swpb~~',0x00\r
+       dw      ARM_instruction_swpb-instruction_handler\r
+       db      'swp~~b',0x00\r
+       dw      ARM_instruction_swpb-instruction_handler\r
+       db      'sxtb.n',0xe4\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxtb.w',0xe2\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxtb16',0xe0\r
+       dw      ARM_instruction_sxtb16-instruction_handler\r
+       db      'sxtb~~',0x00\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxth.n',0xe4\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'sxth.w',0xe2\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'sxth~~',0x00\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'tandcb',0xe0\r
+       dw      ARM_instruction_tandcb-instruction_handler\r
+       db      'tandch',0xe0\r
+       dw      ARM_instruction_tandch-instruction_handler\r
+       db      'tandcw',0xe0\r
+       dw      ARM_instruction_tandcw-instruction_handler\r
+       db      'tan~~d',0x00\r
+       dw      ARM_instruction_tand-instruction_handler\r
+       db      'tan~~e',0x00\r
+       dw      ARM_instruction_tane-instruction_handler\r
+       db      'tan~~s',0x00\r
+       dw      ARM_instruction_tans-instruction_handler\r
+       db      'tbcstb',0xe0\r
+       dw      ARM_instruction_tbcstb-instruction_handler\r
+       db      'tbcsth',0xe0\r
+       dw      ARM_instruction_tbcsth-instruction_handler\r
+       db      'tbcstw',0xe0\r
+       dw      ARM_instruction_tbcstw-instruction_handler\r
+       db      'teqp~~',0x00\r
+       dw      ARM_instruction_teqp-instruction_handler\r
+       db      'teq~~p',0x00\r
+       dw      ARM_instruction_teqp-instruction_handler\r
+       db      'tinsrb',0xe0\r
+       dw      ARM_instruction_tinsrb-instruction_handler\r
+       db      'tinsrh',0xe0\r
+       dw      ARM_instruction_tinsrh-instruction_handler\r
+       db      'tinsrw',0xe0\r
+       dw      ARM_instruction_tinsrw-instruction_handler\r
+       db      'tmcr~~',0x00\r
+       dw      ARM_instruction_tmcr-instruction_handler\r
+       db      'tmiabb',0xe0\r
+       dw      ARM_instruction_tmiabb-instruction_handler\r
+       db      'tmiabt',0xe0\r
+       dw      ARM_instruction_tmiabt-instruction_handler\r
+       db      'tmiaph',0xe0\r
+       dw      ARM_instruction_tmiaph-instruction_handler\r
+       db      'tmiatb',0xe0\r
+       dw      ARM_instruction_tmiatb-instruction_handler\r
+       db      'tmiatt',0xe0\r
+       dw      ARM_instruction_tmiatt-instruction_handler\r
+       db      'tmia~~',0x00\r
+       dw      ARM_instruction_tmia-instruction_handler\r
+       db      'tmrc~~',0x00\r
+       dw      ARM_instruction_tmrc-instruction_handler\r
+       db      'tstp~~',0x00\r
+       dw      ARM_instruction_tstp-instruction_handler\r
+       db      'tst~~p',0x00\r
+       dw      ARM_instruction_tstp-instruction_handler\r
+       db      'uabal2',0xf0\r
+       dw      ARM_instruction_uabal2-instruction_handler\r
+       db      'uabdl2',0xf0\r
+       dw      ARM_instruction_uabdl2-instruction_handler\r
+       db      'uadalp',0xf0\r
+       dw      ARM_instruction_uadalp-instruction_handler\r
+       db      'uadd16',0xe0\r
+       dw      ARM_instruction_uadd16-instruction_handler\r
+       db      'uaddl2',0xf0\r
+       dw      ARM_instruction_uaddl2-instruction_handler\r
+       db      'uaddlp',0xf0\r
+       dw      ARM_instruction_uaddlp-instruction_handler\r
+       db      'uaddlv',0xf0\r
+       dw      ARM_instruction_uaddlv-instruction_handler\r
+       db      'uaddw2',0xf0\r
+       dw      ARM_instruction_uaddw2-instruction_handler\r
+       db      'uasx~~',0x00\r
+       dw      ARM_instruction_uasx-instruction_handler\r
+       db      'ubfx~~',0x00\r
+       dw      ARM_instruction_ubfx-instruction_handler\r
+       db      'udiv~~',0x00\r
+       dw      ARM_instruction_udiv-instruction_handler\r
+       db      'uhadd8',0xe0\r
+       dw      ARM_instruction_uhadd8-instruction_handler\r
+       db      'uhsub8',0xe0\r
+       dw      ARM_instruction_uhsub8-instruction_handler\r
+       db      'umaddl',0xf0\r
+       dw      ARM_instruction_umaddl-instruction_handler\r
+       db      'umlal2',0xf0\r
+       dw      ARM_instruction_umlal2-instruction_handler\r
+       db      'umlals',0xe1\r
+       dw      ARM_instruction_umlal-instruction_handler\r
+       db      'umlsl2',0xf0\r
+       dw      ARM_instruction_umlsl2-instruction_handler\r
+       db      'umnegl',0xf0\r
+       dw      ARM_instruction_umnegl-instruction_handler\r
+       db      'umsubl',0xf0\r
+       dw      ARM_instruction_umsubl-instruction_handler\r
+       db      'umull2',0xf0\r
+       dw      ARM_instruction_umull2-instruction_handler\r
+       db      'umulls',0xe1\r
+       dw      ARM_instruction_umull-instruction_handler\r
+       db      'uqadd8',0xe0\r
+       dw      ARM_instruction_uqadd8-instruction_handler\r
+       db      'uqrshl',0xf0\r
+       dw      ARM_instruction_uqrshl-instruction_handler\r
+       db      'uqshrn',0xf0\r
+       dw      ARM_instruction_uqshrn-instruction_handler\r
+       db      'uqsub8',0xe0\r
+       dw      ARM_instruction_uqsub8-instruction_handler\r
+       db      'uqxtn2',0xf0\r
+       dw      ARM_instruction_uqxtn2-instruction_handler\r
+       db      'urd~~d',0x00\r
+       dw      ARM_instruction_urdd-instruction_handler\r
+       db      'urd~~e',0x00\r
+       dw      ARM_instruction_urde-instruction_handler\r
+       db      'urd~~s',0x00\r
+       dw      ARM_instruction_urds-instruction_handler\r
+       db      'urecpe',0xf0\r
+       dw      ARM_instruction_urecpe-instruction_handler\r
+       db      'urhadd',0xf0\r
+       dw      ARM_instruction_urhadd-instruction_handler\r
+       db      'usada8',0xe0\r
+       dw      ARM_instruction_usada8-instruction_handler\r
+       db      'usat16',0xe0\r
+       dw      ARM_instruction_usat16-instruction_handler\r
+       db      'usat~~',0x00\r
+       dw      ARM_instruction_usat-instruction_handler\r
+       db      'usax~~',0x00\r
+       dw      ARM_instruction_usax-instruction_handler\r
+       db      'ushll2',0xf0\r
+       dw      ARM_instruction_ushll2-instruction_handler\r
+       db      'usqadd',0xf0\r
+       dw      ARM_instruction_usqadd-instruction_handler\r
+       db      'usub16',0xe0\r
+       dw      ARM_instruction_usub16-instruction_handler\r
+       db      'usubl2',0xf0\r
+       dw      ARM_instruction_usubl2-instruction_handler\r
+       db      'usubw2',0xf0\r
+       dw      ARM_instruction_usubw2-instruction_handler\r
+       db      'uxtb.n',0xe4\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxtb.w',0xe2\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxtb16',0xe0\r
+       dw      ARM_instruction_uxtb16-instruction_handler\r
+       db      'uxtb~~',0x00\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxth.n',0xe4\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'uxth.w',0xe2\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'uxth~~',0x00\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'vand~~',0x00\r
+       dw      ARM_instruction_vand-instruction_handler\r
+       db      'vbic~~',0x00\r
+       dw      ARM_instruction_vbic-instruction_handler\r
+       db      'vbif~~',0x00\r
+       dw      ARM_instruction_vbif-instruction_handler\r
+       db      'vbit~~',0x00\r
+       dw      ARM_instruction_vbit-instruction_handler\r
+       db      'vbsl~~',0x00\r
+       dw      ARM_instruction_vbsl-instruction_handler\r
+       db      'vcnt.8',0xe0\r
+       dw      ARM_instruction_vcnt.8-instruction_handler\r
+       db      'vdup.8',0xe0\r
+       dw      ARM_instruction_vdup.8-instruction_handler\r
+       db      'veor~~',0x00\r
+       dw      ARM_instruction_veor-instruction_handler\r
+       db      'vext.8',0xe0\r
+       dw      ARM_instruction_vext.8-instruction_handler\r
+       db      'vld1.8',0xe0\r
+       dw      ARM_instruction_vld1.8-instruction_handler\r
+       db      'vld2.8',0xe0\r
+       dw      ARM_instruction_vld2.8-instruction_handler\r
+       db      'vld3.8',0xe0\r
+       dw      ARM_instruction_vld3.8-instruction_handler\r
+       db      'vld4.8',0xe0\r
+       dw      ARM_instruction_vld4.8-instruction_handler\r
+       db      'vldmdb',0xe0\r
+       dw      ARM_instruction_vldmdb-instruction_handler\r
+       db      'vldmea',0xe0\r
+       dw      ARM_instruction_vldmea-instruction_handler\r
+       db      'vldmfd',0xe0\r
+       dw      ARM_instruction_vldmfd-instruction_handler\r
+       db      'vldmia',0xe0\r
+       dw      ARM_instruction_vldmia-instruction_handler\r
+       db      'vldm~~',0x00\r
+       dw      ARM_instruction_vldm-instruction_handler\r
+       db      'vldr~~',0x00\r
+       dw      ARM_instruction_vldr-instruction_handler\r
+       db      'vmov.8',0xe0\r
+       dw      ARM_instruction_vmov.8-instruction_handler\r
+       db      'vmov~~',0x00\r
+       dw      ARM_instruction_vmov-instruction_handler\r
+       db      'vmrs~~',0x00\r
+       dw      ARM_instruction_vmrs-instruction_handler\r
+       db      'vmsr~~',0x00\r
+       dw      ARM_instruction_vmsr-instruction_handler\r
+       db      'vmvn~~',0x00\r
+       dw      ARM_instruction_vmvn-instruction_handler\r
+       db      'vorn~~',0x00\r
+       dw      ARM_instruction_vorn-instruction_handler\r
+       db      'vorr~~',0x00\r
+       dw      ARM_instruction_vorr-instruction_handler\r
+       db      'vpop~~',0x00\r
+       dw      ARM_instruction_vpop-instruction_handler\r
+       db      'vsli.8',0xe0\r
+       dw      ARM_instruction_vsli.8-instruction_handler\r
+       db      'vsri.8',0xe0\r
+       dw      ARM_instruction_vsri.8-instruction_handler\r
+       db      'vst1.8',0xe0\r
+       dw      ARM_instruction_vst1.8-instruction_handler\r
+       db      'vst2.8',0xe0\r
+       dw      ARM_instruction_vst2.8-instruction_handler\r
+       db      'vst3.8',0xe0\r
+       dw      ARM_instruction_vst3.8-instruction_handler\r
+       db      'vst4.8',0xe0\r
+       dw      ARM_instruction_vst4.8-instruction_handler\r
+       db      'vstmdb',0xe0\r
+       dw      ARM_instruction_vstmdb-instruction_handler\r
+       db      'vstmea',0xe0\r
+       dw      ARM_instruction_vstmea-instruction_handler\r
+       db      'vstmfd',0xe0\r
+       dw      ARM_instruction_vstmfd-instruction_handler\r
+       db      'vstmia',0xe0\r
+       dw      ARM_instruction_vstmia-instruction_handler\r
+       db      'vstm~~',0x00\r
+       dw      ARM_instruction_vstm-instruction_handler\r
+       db      'vstr~~',0x00\r
+       dw      ARM_instruction_vstr-instruction_handler\r
+       db      'vswp~~',0x00\r
+       dw      ARM_instruction_vswp-instruction_handler\r
+       db      'vtbl.8',0xe0\r
+       dw      ARM_instruction_vtbl.8-instruction_handler\r
+       db      'vtbx.8',0xe0\r
+       dw      ARM_instruction_vtbx.8-instruction_handler\r
+       db      'vtrn.8',0xe0\r
+       dw      ARM_instruction_vtrn.8-instruction_handler\r
+       db      'vtst.8',0xe0\r
+       dw      ARM_instruction_vtst.8-instruction_handler\r
+       db      'vuzp.8',0xe0\r
+       dw      ARM_instruction_vuzp.8-instruction_handler\r
+       db      'vzip.8',0xe0\r
+       dw      ARM_instruction_vzip.8-instruction_handler\r
+       db      'waddhc',0xe0\r
+       dw      ARM_instruction_waddhc-instruction_handler\r
+       db      'waddwc',0xe0\r
+       dw      ARM_instruction_waddwc-instruction_handler\r
+       db      'wand~~',0x00\r
+       dw      ARM_instruction_wand-instruction_handler\r
+       db      'wavg2b',0xe0\r
+       dw      ARM_instruction_wavg2b-instruction_handler\r
+       db      'wavg2h',0xe0\r
+       dw      ARM_instruction_wavg2h-instruction_handler\r
+       db      'wavg4r',0xe0\r
+       dw      ARM_instruction_wavg4r-instruction_handler\r
+       db      'wmacsz',0xe0\r
+       dw      ARM_instruction_wmacsz-instruction_handler\r
+       db      'wmacuz',0xe0\r
+       dw      ARM_instruction_wmacuz-instruction_handler\r
+       db      'wmadds',0xe0\r
+       dw      ARM_instruction_wmadds-instruction_handler\r
+       db      'wmaddu',0xe0\r
+       dw      ARM_instruction_wmaddu-instruction_handler\r
+       db      'wmaxsb',0xe0\r
+       dw      ARM_instruction_wmaxsb-instruction_handler\r
+       db      'wmaxsh',0xe0\r
+       dw      ARM_instruction_wmaxsh-instruction_handler\r
+       db      'wmaxsw',0xe0\r
+       dw      ARM_instruction_wmaxsw-instruction_handler\r
+       db      'wmaxub',0xe0\r
+       dw      ARM_instruction_wmaxub-instruction_handler\r
+       db      'wmaxuh',0xe0\r
+       dw      ARM_instruction_wmaxuh-instruction_handler\r
+       db      'wmaxuw',0xe0\r
+       dw      ARM_instruction_wmaxuw-instruction_handler\r
+       db      'wmerge',0xe0\r
+       dw      ARM_instruction_wmerge-instruction_handler\r
+       db      'wmiabb',0xe0\r
+       dw      ARM_instruction_wmiabb-instruction_handler\r
+       db      'wmiabt',0xe0\r
+       dw      ARM_instruction_wmiabt-instruction_handler\r
+       db      'wmiatb',0xe0\r
+       dw      ARM_instruction_wmiatb-instruction_handler\r
+       db      'wmiatt',0xe0\r
+       dw      ARM_instruction_wmiatt-instruction_handler\r
+       db      'wminsb',0xe0\r
+       dw      ARM_instruction_wminsb-instruction_handler\r
+       db      'wminsh',0xe0\r
+       dw      ARM_instruction_wminsh-instruction_handler\r
+       db      'wminsw',0xe0\r
+       dw      ARM_instruction_wminsw-instruction_handler\r
+       db      'wminub',0xe0\r
+       dw      ARM_instruction_wminub-instruction_handler\r
+       db      'wminuh',0xe0\r
+       dw      ARM_instruction_wminuh-instruction_handler\r
+       db      'wminuw',0xe0\r
+       dw      ARM_instruction_wminuw-instruction_handler\r
+       db      'wmov~~',0x00\r
+       dw      ARM_instruction_wmov-instruction_handler\r
+       db      'wmulsl',0xe0\r
+       dw      ARM_instruction_wmulsl-instruction_handler\r
+       db      'wmulsm',0xe0\r
+       dw      ARM_instruction_wmulsm-instruction_handler\r
+       db      'wmulul',0xe0\r
+       dw      ARM_instruction_wmulul-instruction_handler\r
+       db      'wmulum',0xe0\r
+       dw      ARM_instruction_wmulum-instruction_handler\r
+       db      'wmulwl',0xe0\r
+       dw      ARM_instruction_wmulwl-instruction_handler\r
+       db      'wqmulm',0xe0\r
+       dw      ARM_instruction_wqmulm-instruction_handler\r
+       db      'wrordg',0xe0\r
+       dw      ARM_instruction_wrordg-instruction_handler\r
+       db      'wrorhg',0xe0\r
+       dw      ARM_instruction_wrorhg-instruction_handler\r
+       db      'wrorwg',0xe0\r
+       dw      ARM_instruction_wrorwg-instruction_handler\r
+       db      'wsadbz',0xe0\r
+       dw      ARM_instruction_wsadbz-instruction_handler\r
+       db      'wsadhz',0xe0\r
+       dw      ARM_instruction_wsadhz-instruction_handler\r
+       db      'wshufh',0xe0\r
+       dw      ARM_instruction_wshufh-instruction_handler\r
+       db      'wslldg',0xe0\r
+       dw      ARM_instruction_wslldg-instruction_handler\r
+       db      'wsllhg',0xe0\r
+       dw      ARM_instruction_wsllhg-instruction_handler\r
+       db      'wsllwg',0xe0\r
+       dw      ARM_instruction_wsllwg-instruction_handler\r
+       db      'wsradg',0xe0\r
+       dw      ARM_instruction_wsradg-instruction_handler\r
+       db      'wsrahg',0xe0\r
+       dw      ARM_instruction_wsrahg-instruction_handler\r
+       db      'wsrawg',0xe0\r
+       dw      ARM_instruction_wsrawg-instruction_handler\r
+       db      'wsrldg',0xe0\r
+       dw      ARM_instruction_wsrldg-instruction_handler\r
+       db      'wsrlhg',0xe0\r
+       dw      ARM_instruction_wsrlhg-instruction_handler\r
+       db      'wsrlwg',0xe0\r
+       dw      ARM_instruction_wsrlwg-instruction_handler\r
+       db      'wxor~~',0x00\r
+       dw      ARM_instruction_wxor-instruction_handler\r
+       db      0\r
+instructions_7:\r
+       db      'abs~~dm',0x00\r
+       dw      ARM_instruction_absdm-instruction_handler\r
+       db      'abs~~dp',0x00\r
+       dw      ARM_instruction_absdp-instruction_handler\r
+       db      'abs~~dz',0x00\r
+       dw      ARM_instruction_absdz-instruction_handler\r
+       db      'abs~~em',0x00\r
+       dw      ARM_instruction_absem-instruction_handler\r
+       db      'abs~~ep',0x00\r
+       dw      ARM_instruction_absep-instruction_handler\r
+       db      'abs~~ez',0x00\r
+       dw      ARM_instruction_absez-instruction_handler\r
+       db      'abs~~sm',0x00\r
+       dw      ARM_instruction_abssm-instruction_handler\r
+       db      'abs~~sp',0x00\r
+       dw      ARM_instruction_abssp-instruction_handler\r
+       db      'abs~~sz',0x00\r
+       dw      ARM_instruction_abssz-instruction_handler\r
+       db      'acs~~dm',0x00\r
+       dw      ARM_instruction_acsdm-instruction_handler\r
+       db      'acs~~dp',0x00\r
+       dw      ARM_instruction_acsdp-instruction_handler\r
+       db      'acs~~dz',0x00\r
+       dw      ARM_instruction_acsdz-instruction_handler\r
+       db      'acs~~em',0x00\r
+       dw      ARM_instruction_acsem-instruction_handler\r
+       db      'acs~~ep',0x00\r
+       dw      ARM_instruction_acsep-instruction_handler\r
+       db      'acs~~ez',0x00\r
+       dw      ARM_instruction_acsez-instruction_handler\r
+       db      'acs~~sm',0x00\r
+       dw      ARM_instruction_acssm-instruction_handler\r
+       db      'acs~~sp',0x00\r
+       dw      ARM_instruction_acssp-instruction_handler\r
+       db      'acs~~sz',0x00\r
+       dw      ARM_instruction_acssz-instruction_handler\r
+       db      'adc~~.n',0x04\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc~~.w',0x02\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'add~~.n',0x04\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'add~~.w',0x02\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adf~~dm',0x00\r
+       dw      ARM_instruction_adfdm-instruction_handler\r
+       db      'adf~~dp',0x00\r
+       dw      ARM_instruction_adfdp-instruction_handler\r
+       db      'adf~~dz',0x00\r
+       dw      ARM_instruction_adfdz-instruction_handler\r
+       db      'adf~~em',0x00\r
+       dw      ARM_instruction_adfem-instruction_handler\r
+       db      'adf~~ep',0x00\r
+       dw      ARM_instruction_adfep-instruction_handler\r
+       db      'adf~~ez',0x00\r
+       dw      ARM_instruction_adfez-instruction_handler\r
+       db      'adf~~sm',0x00\r
+       dw      ARM_instruction_adfsm-instruction_handler\r
+       db      'adf~~sp',0x00\r
+       dw      ARM_instruction_adfsp-instruction_handler\r
+       db      'adf~~sz',0x00\r
+       dw      ARM_instruction_adfsz-instruction_handler\r
+       db      'adr~~.n',0x04\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'adr~~.w',0x02\r
+       dw      ARM_instruction_adr-instruction_handler\r
+       db      'aesmc.8',0xf0\r
+       dw      ARM_instruction_aesmc.8-instruction_handler\r
+       db      'and~~.n',0x04\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and~~.w',0x02\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asn~~dm',0x00\r
+       dw      ARM_instruction_asndm-instruction_handler\r
+       db      'asn~~dp',0x00\r
+       dw      ARM_instruction_asndp-instruction_handler\r
+       db      'asn~~dz',0x00\r
+       dw      ARM_instruction_asndz-instruction_handler\r
+       db      'asn~~em',0x00\r
+       dw      ARM_instruction_asnem-instruction_handler\r
+       db      'asn~~ep',0x00\r
+       dw      ARM_instruction_asnep-instruction_handler\r
+       db      'asn~~ez',0x00\r
+       dw      ARM_instruction_asnez-instruction_handler\r
+       db      'asn~~sm',0x00\r
+       dw      ARM_instruction_asnsm-instruction_handler\r
+       db      'asn~~sp',0x00\r
+       dw      ARM_instruction_asnsp-instruction_handler\r
+       db      'asn~~sz',0x00\r
+       dw      ARM_instruction_asnsz-instruction_handler\r
+       db      'asr~~.n',0x04\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr~~.w',0x02\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'atn~~dm',0x00\r
+       dw      ARM_instruction_atndm-instruction_handler\r
+       db      'atn~~dp',0x00\r
+       dw      ARM_instruction_atndp-instruction_handler\r
+       db      'atn~~dz',0x00\r
+       dw      ARM_instruction_atndz-instruction_handler\r
+       db      'atn~~em',0x00\r
+       dw      ARM_instruction_atnem-instruction_handler\r
+       db      'atn~~ep',0x00\r
+       dw      ARM_instruction_atnep-instruction_handler\r
+       db      'atn~~ez',0x00\r
+       dw      ARM_instruction_atnez-instruction_handler\r
+       db      'atn~~sm',0x00\r
+       dw      ARM_instruction_atnsm-instruction_handler\r
+       db      'atn~~sp',0x00\r
+       dw      ARM_instruction_atnsp-instruction_handler\r
+       db      'atn~~sz',0x00\r
+       dw      ARM_instruction_atnsz-instruction_handler\r
+       db      'bic~~.n',0x04\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic~~.w',0x02\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'blx~~.n',0x04\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'blx~~.w',0x02\r
+       dw      ARM_instruction_blx-instruction_handler\r
+       db      'cfabs32',0xe0\r
+       dw      ARM_instruction_cfabs32-instruction_handler\r
+       db      'cfabs64',0xe0\r
+       dw      ARM_instruction_cfabs64-instruction_handler\r
+       db      'cfadd32',0xe0\r
+       dw      ARM_instruction_cfadd32-instruction_handler\r
+       db      'cfadd64',0xe0\r
+       dw      ARM_instruction_cfadd64-instruction_handler\r
+       db      'cfcmp32',0xe0\r
+       dw      ARM_instruction_cfcmp32-instruction_handler\r
+       db      'cfcmp64',0xe0\r
+       dw      ARM_instruction_cfcmp64-instruction_handler\r
+       db      'cfcvtds',0xe0\r
+       dw      ARM_instruction_cfcvtds-instruction_handler\r
+       db      'cfcvtsd',0xe0\r
+       dw      ARM_instruction_cfcvtsd-instruction_handler\r
+       db      'cfldr32',0xe0\r
+       dw      ARM_instruction_cfldr32-instruction_handler\r
+       db      'cfldr64',0xe0\r
+       dw      ARM_instruction_cfldr64-instruction_handler\r
+       db      'cfmac32',0xe0\r
+       dw      ARM_instruction_cfmac32-instruction_handler\r
+       db      'cfmsc32',0xe0\r
+       dw      ARM_instruction_cfmsc32-instruction_handler\r
+       db      'cfmul32',0xe0\r
+       dw      ARM_instruction_cfmul32-instruction_handler\r
+       db      'cfmul64',0xe0\r
+       dw      ARM_instruction_cfmul64-instruction_handler\r
+       db      'cfmv32a',0xe0\r
+       dw      ARM_instruction_cfmv32a-instruction_handler\r
+       db      'cfmv64a',0xe0\r
+       dw      ARM_instruction_cfmv64a-instruction_handler\r
+       db      'cfmva32',0xe0\r
+       dw      ARM_instruction_cfmva32-instruction_handler\r
+       db      'cfmva64',0xe0\r
+       dw      ARM_instruction_cfmva64-instruction_handler\r
+       db      'cfmvdhr',0xe0\r
+       dw      ARM_instruction_cfmvdhr-instruction_handler\r
+       db      'cfmvdlr',0xe0\r
+       dw      ARM_instruction_cfmvdlr-instruction_handler\r
+       db      'cfmvrdh',0xe0\r
+       dw      ARM_instruction_cfmvrdh-instruction_handler\r
+       db      'cfmvrdl',0xe0\r
+       dw      ARM_instruction_cfmvrdl-instruction_handler\r
+       db      'cfneg32',0xe0\r
+       dw      ARM_instruction_cfneg32-instruction_handler\r
+       db      'cfneg64',0xe0\r
+       dw      ARM_instruction_cfneg64-instruction_handler\r
+       db      'cfstr32',0xe0\r
+       dw      ARM_instruction_cfstr32-instruction_handler\r
+       db      'cfstr64',0xe0\r
+       dw      ARM_instruction_cfstr64-instruction_handler\r
+       db      'cfsub32',0xe0\r
+       dw      ARM_instruction_cfsub32-instruction_handler\r
+       db      'cfsub64',0xe0\r
+       dw      ARM_instruction_cfsub64-instruction_handler\r
+       db      'clrex~~',0x00\r
+       dw      ARM_instruction_clrex-instruction_handler\r
+       db      'cmn~~.n',0x04\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmn~~.w',0x02\r
+       dw      ARM_instruction_cmn-instruction_handler\r
+       db      'cmp~~.n',0x04\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cmp~~.w',0x02\r
+       dw      ARM_instruction_cmp-instruction_handler\r
+       db      'cos~~dm',0x00\r
+       dw      ARM_instruction_cosdm-instruction_handler\r
+       db      'cos~~dp',0x00\r
+       dw      ARM_instruction_cosdp-instruction_handler\r
+       db      'cos~~dz',0x00\r
+       dw      ARM_instruction_cosdz-instruction_handler\r
+       db      'cos~~em',0x00\r
+       dw      ARM_instruction_cosem-instruction_handler\r
+       db      'cos~~ep',0x00\r
+       dw      ARM_instruction_cosep-instruction_handler\r
+       db      'cos~~ez',0x00\r
+       dw      ARM_instruction_cosez-instruction_handler\r
+       db      'cos~~sm',0x00\r
+       dw      ARM_instruction_cossm-instruction_handler\r
+       db      'cos~~sp',0x00\r
+       dw      ARM_instruction_cossp-instruction_handler\r
+       db      'cos~~sz',0x00\r
+       dw      ARM_instruction_cossz-instruction_handler\r
+       db      'cpsid.n',0xf4\r
+       dw      ARM_instruction_cpsid-instruction_handler\r
+       db      'cpsid.w',0xf2\r
+       dw      ARM_instruction_cpsid-instruction_handler\r
+       db      'cpsie.n',0xf4\r
+       dw      ARM_instruction_cpsie-instruction_handler\r
+       db      'cpsie.w',0xf2\r
+       dw      ARM_instruction_cpsie-instruction_handler\r
+       db      'cpy~~.n',0x04\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'cpy~~.w',0x02\r
+       dw      ARM_instruction_cpy-instruction_handler\r
+       db      'crc32cb',0xf0\r
+       dw      ARM_instruction_crc32cb-instruction_handler\r
+       db      'crc32ch',0xf0\r
+       dw      ARM_instruction_crc32ch-instruction_handler\r
+       db      'crc32cw',0xf0\r
+       dw      ARM_instruction_crc32cw-instruction_handler\r
+       db      'crc32cx',0xf0\r
+       dw      ARM_instruction_crc32cx-instruction_handler\r
+       db      'display',0x00\r
+       dw      display_directive-instruction_handler\r
+       db      'dvf~~dm',0x00\r
+       dw      ARM_instruction_dvfdm-instruction_handler\r
+       db      'dvf~~dp',0x00\r
+       dw      ARM_instruction_dvfdp-instruction_handler\r
+       db      'dvf~~dz',0x00\r
+       dw      ARM_instruction_dvfdz-instruction_handler\r
+       db      'dvf~~em',0x00\r
+       dw      ARM_instruction_dvfem-instruction_handler\r
+       db      'dvf~~ep',0x00\r
+       dw      ARM_instruction_dvfep-instruction_handler\r
+       db      'dvf~~ez',0x00\r
+       dw      ARM_instruction_dvfez-instruction_handler\r
+       db      'dvf~~sm',0x00\r
+       dw      ARM_instruction_dvfsm-instruction_handler\r
+       db      'dvf~~sp',0x00\r
+       dw      ARM_instruction_dvfsp-instruction_handler\r
+       db      'dvf~~sz',0x00\r
+       dw      ARM_instruction_dvfsz-instruction_handler\r
+       db      'eor~~.n',0x04\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor~~.w',0x02\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'exp~~dm',0x00\r
+       dw      ARM_instruction_expdm-instruction_handler\r
+       db      'exp~~dp',0x00\r
+       dw      ARM_instruction_expdp-instruction_handler\r
+       db      'exp~~dz',0x00\r
+       dw      ARM_instruction_expdz-instruction_handler\r
+       db      'exp~~em',0x00\r
+       dw      ARM_instruction_expem-instruction_handler\r
+       db      'exp~~ep',0x00\r
+       dw      ARM_instruction_expep-instruction_handler\r
+       db      'exp~~ez',0x00\r
+       dw      ARM_instruction_expez-instruction_handler\r
+       db      'exp~~sm',0x00\r
+       dw      ARM_instruction_expsm-instruction_handler\r
+       db      'exp~~sp',0x00\r
+       dw      ARM_instruction_expsp-instruction_handler\r
+       db      'exp~~sz',0x00\r
+       dw      ARM_instruction_expsz-instruction_handler\r
+       db      'fabsd~~',0x00\r
+       dw      ARM_instruction_fabsd-instruction_handler\r
+       db      'fabss~~',0x00\r
+       dw      ARM_instruction_fabss-instruction_handler\r
+       db      'faddd~~',0x00\r
+       dw      ARM_instruction_faddd-instruction_handler\r
+       db      'fadds~~',0x00\r
+       dw      ARM_instruction_fadds-instruction_handler\r
+       db      'fcmpd~~',0x00\r
+       dw      ARM_instruction_fcmpd-instruction_handler\r
+       db      'fcmpezd',0xe0\r
+       dw      ARM_instruction_fcmpezd-instruction_handler\r
+       db      'fcmpezs',0xe0\r
+       dw      ARM_instruction_fcmpezs-instruction_handler\r
+       db      'fcmps~~',0x00\r
+       dw      ARM_instruction_fcmps-instruction_handler\r
+       db      'fconstd',0xe0\r
+       dw      ARM_instruction_fconstd-instruction_handler\r
+       db      'fconsts',0xe0\r
+       dw      ARM_instruction_fconsts-instruction_handler\r
+       db      'fcpyd~~',0x00\r
+       dw      ARM_instruction_fcpyd-instruction_handler\r
+       db      'fcpys~~',0x00\r
+       dw      ARM_instruction_fcpys-instruction_handler\r
+       db      'fcvtxn2',0xf0\r
+       dw      ARM_instruction_fcvtxn2-instruction_handler\r
+       db      'fdivd~~',0x00\r
+       dw      ARM_instruction_fdivd-instruction_handler\r
+       db      'fdivs~~',0x00\r
+       dw      ARM_instruction_fdivs-instruction_handler\r
+       db      'fdv~~dm',0x00\r
+       dw      ARM_instruction_fdvdm-instruction_handler\r
+       db      'fdv~~dp',0x00\r
+       dw      ARM_instruction_fdvdp-instruction_handler\r
+       db      'fdv~~dz',0x00\r
+       dw      ARM_instruction_fdvdz-instruction_handler\r
+       db      'fdv~~em',0x00\r
+       dw      ARM_instruction_fdvem-instruction_handler\r
+       db      'fdv~~ep',0x00\r
+       dw      ARM_instruction_fdvep-instruction_handler\r
+       db      'fdv~~ez',0x00\r
+       dw      ARM_instruction_fdvez-instruction_handler\r
+       db      'fdv~~sm',0x00\r
+       dw      ARM_instruction_fdvsm-instruction_handler\r
+       db      'fdv~~sp',0x00\r
+       dw      ARM_instruction_fdvsp-instruction_handler\r
+       db      'fdv~~sz',0x00\r
+       dw      ARM_instruction_fdvsz-instruction_handler\r
+       db      'fldmdbd',0xe0\r
+       dw      ARM_instruction_fldmdbd-instruction_handler\r
+       db      'fldmdbs',0xe0\r
+       dw      ARM_instruction_fldmdbs-instruction_handler\r
+       db      'fldmdbx',0xe0\r
+       dw      ARM_instruction_fldmdbx-instruction_handler\r
+       db      'fldmd~~',0x00\r
+       dw      ARM_instruction_fldmd-instruction_handler\r
+       db      'fldmead',0xe0\r
+       dw      ARM_instruction_fldmead-instruction_handler\r
+       db      'fldmeas',0xe0\r
+       dw      ARM_instruction_fldmeas-instruction_handler\r
+       db      'fldmeax',0xe0\r
+       dw      ARM_instruction_fldmeax-instruction_handler\r
+       db      'fldmfdd',0xe0\r
+       dw      ARM_instruction_fldmfdd-instruction_handler\r
+       db      'fldmfds',0xe0\r
+       dw      ARM_instruction_fldmfds-instruction_handler\r
+       db      'fldmfdx',0xe0\r
+       dw      ARM_instruction_fldmfdx-instruction_handler\r
+       db      'fldmiad',0xe0\r
+       dw      ARM_instruction_fldmiad-instruction_handler\r
+       db      'fldmias',0xe0\r
+       dw      ARM_instruction_fldmias-instruction_handler\r
+       db      'fldmiax',0xe0\r
+       dw      ARM_instruction_fldmiax-instruction_handler\r
+       db      'fldms~~',0x00\r
+       dw      ARM_instruction_fldms-instruction_handler\r
+       db      'fldmx~~',0x00\r
+       dw      ARM_instruction_fldmx-instruction_handler\r
+       db      'flt~~dm',0x00\r
+       dw      ARM_instruction_fltdm-instruction_handler\r
+       db      'flt~~dp',0x00\r
+       dw      ARM_instruction_fltdp-instruction_handler\r
+       db      'flt~~dz',0x00\r
+       dw      ARM_instruction_fltdz-instruction_handler\r
+       db      'flt~~em',0x00\r
+       dw      ARM_instruction_fltem-instruction_handler\r
+       db      'flt~~ep',0x00\r
+       dw      ARM_instruction_fltep-instruction_handler\r
+       db      'flt~~ez',0x00\r
+       dw      ARM_instruction_fltez-instruction_handler\r
+       db      'flt~~sm',0x00\r
+       dw      ARM_instruction_fltsm-instruction_handler\r
+       db      'flt~~sp',0x00\r
+       dw      ARM_instruction_fltsp-instruction_handler\r
+       db      'flt~~sz',0x00\r
+       dw      ARM_instruction_fltsz-instruction_handler\r
+       db      'fmacd~~',0x00\r
+       dw      ARM_instruction_fmacd-instruction_handler\r
+       db      'fmacs~~',0x00\r
+       dw      ARM_instruction_fmacs-instruction_handler\r
+       db      'fmaxnmp',0xf0\r
+       dw      ARM_instruction_fmaxnmp-instruction_handler\r
+       db      'fmaxnmv',0xf0\r
+       dw      ARM_instruction_fmaxnmv-instruction_handler\r
+       db      'fmdhr~~',0x00\r
+       dw      ARM_instruction_fmdhr-instruction_handler\r
+       db      'fmdlr~~',0x00\r
+       dw      ARM_instruction_fmdlr-instruction_handler\r
+       db      'fmdrr~~',0x00\r
+       dw      ARM_instruction_fmdrr-instruction_handler\r
+       db      'fminnmp',0xf0\r
+       dw      ARM_instruction_fminnmp-instruction_handler\r
+       db      'fminnmv',0xf0\r
+       dw      ARM_instruction_fminnmv-instruction_handler\r
+       db      'fml~~dm',0x00\r
+       dw      ARM_instruction_fmldm-instruction_handler\r
+       db      'fml~~dp',0x00\r
+       dw      ARM_instruction_fmldp-instruction_handler\r
+       db      'fml~~dz',0x00\r
+       dw      ARM_instruction_fmldz-instruction_handler\r
+       db      'fml~~em',0x00\r
+       dw      ARM_instruction_fmlem-instruction_handler\r
+       db      'fml~~ep',0x00\r
+       dw      ARM_instruction_fmlep-instruction_handler\r
+       db      'fml~~ez',0x00\r
+       dw      ARM_instruction_fmlez-instruction_handler\r
+       db      'fml~~sm',0x00\r
+       dw      ARM_instruction_fmlsm-instruction_handler\r
+       db      'fml~~sp',0x00\r
+       dw      ARM_instruction_fmlsp-instruction_handler\r
+       db      'fml~~sz',0x00\r
+       dw      ARM_instruction_fmlsz-instruction_handler\r
+       db      'fmrdh~~',0x00\r
+       dw      ARM_instruction_fmrdh-instruction_handler\r
+       db      'fmrdl~~',0x00\r
+       dw      ARM_instruction_fmrdl-instruction_handler\r
+       db      'fmrrd~~',0x00\r
+       dw      ARM_instruction_fmrrd-instruction_handler\r
+       db      'fmrrs~~',0x00\r
+       dw      ARM_instruction_fmrrs-instruction_handler\r
+       db      'fmscd~~',0x00\r
+       dw      ARM_instruction_fmscd-instruction_handler\r
+       db      'fmscs~~',0x00\r
+       dw      ARM_instruction_fmscs-instruction_handler\r
+       db      'fmsrr~~',0x00\r
+       dw      ARM_instruction_fmsrr-instruction_handler\r
+       db      'fmuld~~',0x00\r
+       dw      ARM_instruction_fmuld-instruction_handler\r
+       db      'fmuls~~',0x00\r
+       dw      ARM_instruction_fmuls-instruction_handler\r
+       db      'fnegd~~',0x00\r
+       dw      ARM_instruction_fnegd-instruction_handler\r
+       db      'fnegs~~',0x00\r
+       dw      ARM_instruction_fnegs-instruction_handler\r
+       db      'frd~~dm',0x00\r
+       dw      ARM_instruction_frddm-instruction_handler\r
+       db      'frd~~dp',0x00\r
+       dw      ARM_instruction_frddp-instruction_handler\r
+       db      'frd~~dz',0x00\r
+       dw      ARM_instruction_frddz-instruction_handler\r
+       db      'frd~~em',0x00\r
+       dw      ARM_instruction_frdem-instruction_handler\r
+       db      'frd~~ep',0x00\r
+       dw      ARM_instruction_frdep-instruction_handler\r
+       db      'frd~~ez',0x00\r
+       dw      ARM_instruction_frdez-instruction_handler\r
+       db      'frd~~sm',0x00\r
+       dw      ARM_instruction_frdsm-instruction_handler\r
+       db      'frd~~sp',0x00\r
+       dw      ARM_instruction_frdsp-instruction_handler\r
+       db      'frd~~sz',0x00\r
+       dw      ARM_instruction_frdsz-instruction_handler\r
+       db      'frsqrte',0xf0\r
+       dw      ARM_instruction_frsqrte-instruction_handler\r
+       db      'frsqrts',0xf0\r
+       dw      ARM_instruction_frsqrts-instruction_handler\r
+       db      'fstmdbd',0xe0\r
+       dw      ARM_instruction_fstmdbd-instruction_handler\r
+       db      'fstmdbs',0xe0\r
+       dw      ARM_instruction_fstmdbs-instruction_handler\r
+       db      'fstmdbx',0xe0\r
+       dw      ARM_instruction_fstmdbx-instruction_handler\r
+       db      'fstmd~~',0x00\r
+       dw      ARM_instruction_fstmd-instruction_handler\r
+       db      'fstmead',0xe0\r
+       dw      ARM_instruction_fstmead-instruction_handler\r
+       db      'fstmeas',0xe0\r
+       dw      ARM_instruction_fstmeas-instruction_handler\r
+       db      'fstmeax',0xe0\r
+       dw      ARM_instruction_fstmeax-instruction_handler\r
+       db      'fstmfdd',0xe0\r
+       dw      ARM_instruction_fstmfdd-instruction_handler\r
+       db      'fstmfds',0xe0\r
+       dw      ARM_instruction_fstmfds-instruction_handler\r
+       db      'fstmfdx',0xe0\r
+       dw      ARM_instruction_fstmfdx-instruction_handler\r
+       db      'fstmiad',0xe0\r
+       dw      ARM_instruction_fstmiad-instruction_handler\r
+       db      'fstmias',0xe0\r
+       dw      ARM_instruction_fstmias-instruction_handler\r
+       db      'fstmiax',0xe0\r
+       dw      ARM_instruction_fstmiax-instruction_handler\r
+       db      'fstms~~',0x00\r
+       dw      ARM_instruction_fstms-instruction_handler\r
+       db      'fstmx~~',0x00\r
+       dw      ARM_instruction_fstmx-instruction_handler\r
+       db      'fsubd~~',0x00\r
+       dw      ARM_instruction_fsubd-instruction_handler\r
+       db      'fsubs~~',0x00\r
+       dw      ARM_instruction_fsubs-instruction_handler\r
+       db      'ftosizd',0xe0\r
+       dw      ARM_instruction_ftosizd-instruction_handler\r
+       db      'ftosizs',0xe0\r
+       dw      ARM_instruction_ftosizs-instruction_handler\r
+       db      'ftouizd',0xe0\r
+       dw      ARM_instruction_ftouizd-instruction_handler\r
+       db      'ftouizs',0xe0\r
+       dw      ARM_instruction_ftouizs-instruction_handler\r
+       db      'ldaex~~',0x00\r
+       dw      ARM_instruction_ldaex-instruction_handler\r
+       db      'ldc2l~~',0x00\r
+       dw      ARM_instruction_ldc2l-instruction_handler\r
+       db      'ldmda~~',0x00\r
+       dw      ARM_instruction_ldmda-instruction_handler\r
+       db      'ldmdb~~',0x00\r
+       dw      ARM_instruction_ldmdb-instruction_handler\r
+       db      'ldmea~~',0x00\r
+       dw      ARM_instruction_ldmea-instruction_handler\r
+       db      'ldmed~~',0x00\r
+       dw      ARM_instruction_ldmed-instruction_handler\r
+       db      'ldmfa~~',0x00\r
+       dw      ARM_instruction_ldmfa-instruction_handler\r
+       db      'ldmfd.n',0xe4\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmfd.w',0xe2\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmfd~~',0x00\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmia.n',0xe4\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldmia.w',0xe2\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldmia~~',0x00\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldmib~~',0x00\r
+       dw      ARM_instruction_ldmib-instruction_handler\r
+       db      'ldm~~.n',0x04\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldm~~.w',0x02\r
+       dw      ARM_instruction_ldm-instruction_handler\r
+       db      'ldm~~da',0x00\r
+       dw      ARM_instruction_ldmda-instruction_handler\r
+       db      'ldm~~db',0x00\r
+       dw      ARM_instruction_ldmdb-instruction_handler\r
+       db      'ldm~~ea',0x00\r
+       dw      ARM_instruction_ldmea-instruction_handler\r
+       db      'ldm~~ed',0x00\r
+       dw      ARM_instruction_ldmed-instruction_handler\r
+       db      'ldm~~fa',0x00\r
+       dw      ARM_instruction_ldmfa-instruction_handler\r
+       db      'ldm~~fd',0x00\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldm~~ia',0x00\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldm~~ib',0x00\r
+       dw      ARM_instruction_ldmib-instruction_handler\r
+       db      'ldrbt~~',0x00\r
+       dw      ARM_instruction_ldrbt-instruction_handler\r
+       db      'ldrex~~',0x00\r
+       dw      ARM_instruction_ldrex-instruction_handler\r
+       db      'ldrht~~',0x00\r
+       dw      ARM_instruction_ldrht-instruction_handler\r
+       db      'ldrsb.n',0xe4\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsb.w',0xe2\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsb~~',0x00\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsh.n',0xe4\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldrsh.w',0xe2\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldrsh~~',0x00\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldr~~.n',0x04\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'ldr~~.w',0x02\r
+       dw      ARM_instruction_ldr-instruction_handler\r
+       db      'ldr~~bt',0x00\r
+       dw      ARM_instruction_ldrbt-instruction_handler\r
+       db      'ldr~~ht',0x00\r
+       dw      ARM_instruction_ldrht-instruction_handler\r
+       db      'ldr~~sb',0x00\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldr~~sh',0x00\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'lfm~~ea',0x00\r
+       dw      ARM_instruction_lfmea-instruction_handler\r
+       db      'lfm~~fd',0x00\r
+       dw      ARM_instruction_lfmfd-instruction_handler\r
+       db      'lgn~~dm',0x00\r
+       dw      ARM_instruction_lgndm-instruction_handler\r
+       db      'lgn~~dp',0x00\r
+       dw      ARM_instruction_lgndp-instruction_handler\r
+       db      'lgn~~dz',0x00\r
+       dw      ARM_instruction_lgndz-instruction_handler\r
+       db      'lgn~~em',0x00\r
+       dw      ARM_instruction_lgnem-instruction_handler\r
+       db      'lgn~~ep',0x00\r
+       dw      ARM_instruction_lgnep-instruction_handler\r
+       db      'lgn~~ez',0x00\r
+       dw      ARM_instruction_lgnez-instruction_handler\r
+       db      'lgn~~sm',0x00\r
+       dw      ARM_instruction_lgnsm-instruction_handler\r
+       db      'lgn~~sp',0x00\r
+       dw      ARM_instruction_lgnsp-instruction_handler\r
+       db      'lgn~~sz',0x00\r
+       dw      ARM_instruction_lgnsz-instruction_handler\r
+       db      'log~~dm',0x00\r
+       dw      ARM_instruction_logdm-instruction_handler\r
+       db      'log~~dp',0x00\r
+       dw      ARM_instruction_logdp-instruction_handler\r
+       db      'log~~dz',0x00\r
+       dw      ARM_instruction_logdz-instruction_handler\r
+       db      'log~~em',0x00\r
+       dw      ARM_instruction_logem-instruction_handler\r
+       db      'log~~ep',0x00\r
+       dw      ARM_instruction_logep-instruction_handler\r
+       db      'log~~ez',0x00\r
+       dw      ARM_instruction_logez-instruction_handler\r
+       db      'log~~sm',0x00\r
+       dw      ARM_instruction_logsm-instruction_handler\r
+       db      'log~~sp',0x00\r
+       dw      ARM_instruction_logsp-instruction_handler\r
+       db      'log~~sz',0x00\r
+       dw      ARM_instruction_logsz-instruction_handler\r
+       db      'lsl~~.n',0x04\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl~~.w',0x02\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsr~~.n',0x04\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr~~.w',0x02\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'mcrr2~~',0x00\r
+       dw      ARM_instruction_mcrr2-instruction_handler\r
+       db      'miabb~~',0x00\r
+       dw      ARM_instruction_miabb-instruction_handler\r
+       db      'miabt~~',0x00\r
+       dw      ARM_instruction_miabt-instruction_handler\r
+       db      'miaph~~',0x00\r
+       dw      ARM_instruction_miaph-instruction_handler\r
+       db      'miatb~~',0x00\r
+       dw      ARM_instruction_miatb-instruction_handler\r
+       db      'miatt~~',0x00\r
+       dw      ARM_instruction_miatt-instruction_handler\r
+       db      'mnf~~dm',0x00\r
+       dw      ARM_instruction_mnfdm-instruction_handler\r
+       db      'mnf~~dp',0x00\r
+       dw      ARM_instruction_mnfdp-instruction_handler\r
+       db      'mnf~~dz',0x00\r
+       dw      ARM_instruction_mnfdz-instruction_handler\r
+       db      'mnf~~em',0x00\r
+       dw      ARM_instruction_mnfem-instruction_handler\r
+       db      'mnf~~ep',0x00\r
+       dw      ARM_instruction_mnfep-instruction_handler\r
+       db      'mnf~~ez',0x00\r
+       dw      ARM_instruction_mnfez-instruction_handler\r
+       db      'mnf~~sm',0x00\r
+       dw      ARM_instruction_mnfsm-instruction_handler\r
+       db      'mnf~~sp',0x00\r
+       dw      ARM_instruction_mnfsp-instruction_handler\r
+       db      'mnf~~sz',0x00\r
+       dw      ARM_instruction_mnfsz-instruction_handler\r
+       db      'mov~~.n',0x04\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mov~~.w',0x02\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mrrc2~~',0x00\r
+       dw      ARM_instruction_mrrc2-instruction_handler\r
+       db      'muf~~dm',0x00\r
+       dw      ARM_instruction_mufdm-instruction_handler\r
+       db      'muf~~dp',0x00\r
+       dw      ARM_instruction_mufdp-instruction_handler\r
+       db      'muf~~dz',0x00\r
+       dw      ARM_instruction_mufdz-instruction_handler\r
+       db      'muf~~em',0x00\r
+       dw      ARM_instruction_mufem-instruction_handler\r
+       db      'muf~~ep',0x00\r
+       dw      ARM_instruction_mufep-instruction_handler\r
+       db      'muf~~ez',0x00\r
+       dw      ARM_instruction_mufez-instruction_handler\r
+       db      'muf~~sm',0x00\r
+       dw      ARM_instruction_mufsm-instruction_handler\r
+       db      'muf~~sp',0x00\r
+       dw      ARM_instruction_mufsp-instruction_handler\r
+       db      'muf~~sz',0x00\r
+       dw      ARM_instruction_mufsz-instruction_handler\r
+       db      'mul~~.n',0x04\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul~~.w',0x02\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvf~~dm',0x00\r
+       dw      ARM_instruction_mvfdm-instruction_handler\r
+       db      'mvf~~dp',0x00\r
+       dw      ARM_instruction_mvfdp-instruction_handler\r
+       db      'mvf~~dz',0x00\r
+       dw      ARM_instruction_mvfdz-instruction_handler\r
+       db      'mvf~~em',0x00\r
+       dw      ARM_instruction_mvfem-instruction_handler\r
+       db      'mvf~~ep',0x00\r
+       dw      ARM_instruction_mvfep-instruction_handler\r
+       db      'mvf~~ez',0x00\r
+       dw      ARM_instruction_mvfez-instruction_handler\r
+       db      'mvf~~sm',0x00\r
+       dw      ARM_instruction_mvfsm-instruction_handler\r
+       db      'mvf~~sp',0x00\r
+       dw      ARM_instruction_mvfsp-instruction_handler\r
+       db      'mvf~~sz',0x00\r
+       dw      ARM_instruction_mvfsz-instruction_handler\r
+       db      'mvn~~.n',0x04\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn~~.w',0x02\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'neg~~.n',0x04\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg~~.w',0x02\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'nop~~.n',0x04\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'nop~~.w',0x02\r
+       dw      ARM_instruction_nop-instruction_handler\r
+       db      'nrm~~dm',0x00\r
+       dw      ARM_instruction_nrmdm-instruction_handler\r
+       db      'nrm~~dp',0x00\r
+       dw      ARM_instruction_nrmdp-instruction_handler\r
+       db      'nrm~~dz',0x00\r
+       dw      ARM_instruction_nrmdz-instruction_handler\r
+       db      'nrm~~em',0x00\r
+       dw      ARM_instruction_nrmem-instruction_handler\r
+       db      'nrm~~ep',0x00\r
+       dw      ARM_instruction_nrmep-instruction_handler\r
+       db      'nrm~~ez',0x00\r
+       dw      ARM_instruction_nrmez-instruction_handler\r
+       db      'nrm~~sm',0x00\r
+       dw      ARM_instruction_nrmsm-instruction_handler\r
+       db      'nrm~~sp',0x00\r
+       dw      ARM_instruction_nrmsp-instruction_handler\r
+       db      'nrm~~sz',0x00\r
+       dw      ARM_instruction_nrmsz-instruction_handler\r
+       db      'orr~~.n',0x04\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr~~.w',0x02\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'pkhbt~~',0x00\r
+       dw      ARM_instruction_pkhbt-instruction_handler\r
+       db      'pkhtb~~',0x00\r
+       dw      ARM_instruction_pkhtb-instruction_handler\r
+       db      'pol~~dm',0x00\r
+       dw      ARM_instruction_poldm-instruction_handler\r
+       db      'pol~~dp',0x00\r
+       dw      ARM_instruction_poldp-instruction_handler\r
+       db      'pol~~dz',0x00\r
+       dw      ARM_instruction_poldz-instruction_handler\r
+       db      'pol~~em',0x00\r
+       dw      ARM_instruction_polem-instruction_handler\r
+       db      'pol~~ep',0x00\r
+       dw      ARM_instruction_polep-instruction_handler\r
+       db      'pol~~ez',0x00\r
+       dw      ARM_instruction_polez-instruction_handler\r
+       db      'pol~~sm',0x00\r
+       dw      ARM_instruction_polsm-instruction_handler\r
+       db      'pol~~sp',0x00\r
+       dw      ARM_instruction_polsp-instruction_handler\r
+       db      'pol~~sz',0x00\r
+       dw      ARM_instruction_polsz-instruction_handler\r
+       db      'pop~~.n',0x04\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'pop~~.w',0x02\r
+       dw      ARM_instruction_pop-instruction_handler\r
+       db      'pow~~dm',0x00\r
+       dw      ARM_instruction_powdm-instruction_handler\r
+       db      'pow~~dp',0x00\r
+       dw      ARM_instruction_powdp-instruction_handler\r
+       db      'pow~~dz',0x00\r
+       dw      ARM_instruction_powdz-instruction_handler\r
+       db      'pow~~em',0x00\r
+       dw      ARM_instruction_powem-instruction_handler\r
+       db      'pow~~ep',0x00\r
+       dw      ARM_instruction_powep-instruction_handler\r
+       db      'pow~~ez',0x00\r
+       dw      ARM_instruction_powez-instruction_handler\r
+       db      'pow~~sm',0x00\r
+       dw      ARM_instruction_powsm-instruction_handler\r
+       db      'pow~~sp',0x00\r
+       dw      ARM_instruction_powsp-instruction_handler\r
+       db      'pow~~sz',0x00\r
+       dw      ARM_instruction_powsz-instruction_handler\r
+       db      'qadd8~~',0x00\r
+       dw      ARM_instruction_qadd8-instruction_handler\r
+       db      'qdadd~~',0x00\r
+       dw      ARM_instruction_qdadd-instruction_handler\r
+       db      'qdsub~~',0x00\r
+       dw      ARM_instruction_qdsub-instruction_handler\r
+       db      'qsub8~~',0x00\r
+       dw      ARM_instruction_qsub8-instruction_handler\r
+       db      'raddhn2',0xf0\r
+       dw      ARM_instruction_raddhn2-instruction_handler\r
+       db      'rdf~~dm',0x00\r
+       dw      ARM_instruction_rdfdm-instruction_handler\r
+       db      'rdf~~dp',0x00\r
+       dw      ARM_instruction_rdfdp-instruction_handler\r
+       db      'rdf~~dz',0x00\r
+       dw      ARM_instruction_rdfdz-instruction_handler\r
+       db      'rdf~~em',0x00\r
+       dw      ARM_instruction_rdfem-instruction_handler\r
+       db      'rdf~~ep',0x00\r
+       dw      ARM_instruction_rdfep-instruction_handler\r
+       db      'rdf~~ez',0x00\r
+       dw      ARM_instruction_rdfez-instruction_handler\r
+       db      'rdf~~sm',0x00\r
+       dw      ARM_instruction_rdfsm-instruction_handler\r
+       db      'rdf~~sp',0x00\r
+       dw      ARM_instruction_rdfsp-instruction_handler\r
+       db      'rdf~~sz',0x00\r
+       dw      ARM_instruction_rdfsz-instruction_handler\r
+       db      'rev16.n',0xe4\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'rev16.w',0xe2\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'rev16~~',0x00\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'revsh.n',0xe4\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'revsh.w',0xe2\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'revsh~~',0x00\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'rev~~.n',0x04\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rev~~.w',0x02\r
+       dw      ARM_instruction_rev-instruction_handler\r
+       db      'rmf~~dm',0x00\r
+       dw      ARM_instruction_rmfdm-instruction_handler\r
+       db      'rmf~~dp',0x00\r
+       dw      ARM_instruction_rmfdp-instruction_handler\r
+       db      'rmf~~dz',0x00\r
+       dw      ARM_instruction_rmfdz-instruction_handler\r
+       db      'rmf~~em',0x00\r
+       dw      ARM_instruction_rmfem-instruction_handler\r
+       db      'rmf~~ep',0x00\r
+       dw      ARM_instruction_rmfep-instruction_handler\r
+       db      'rmf~~ez',0x00\r
+       dw      ARM_instruction_rmfez-instruction_handler\r
+       db      'rmf~~sm',0x00\r
+       dw      ARM_instruction_rmfsm-instruction_handler\r
+       db      'rmf~~sp',0x00\r
+       dw      ARM_instruction_rmfsp-instruction_handler\r
+       db      'rmf~~sz',0x00\r
+       dw      ARM_instruction_rmfsz-instruction_handler\r
+       db      'rnd~~dm',0x00\r
+       dw      ARM_instruction_rnddm-instruction_handler\r
+       db      'rnd~~dp',0x00\r
+       dw      ARM_instruction_rnddp-instruction_handler\r
+       db      'rnd~~dz',0x00\r
+       dw      ARM_instruction_rnddz-instruction_handler\r
+       db      'rnd~~em',0x00\r
+       dw      ARM_instruction_rndem-instruction_handler\r
+       db      'rnd~~ep',0x00\r
+       dw      ARM_instruction_rndep-instruction_handler\r
+       db      'rnd~~ez',0x00\r
+       dw      ARM_instruction_rndez-instruction_handler\r
+       db      'rnd~~sm',0x00\r
+       dw      ARM_instruction_rndsm-instruction_handler\r
+       db      'rnd~~sp',0x00\r
+       dw      ARM_instruction_rndsp-instruction_handler\r
+       db      'rnd~~sz',0x00\r
+       dw      ARM_instruction_rndsz-instruction_handler\r
+       db      'ror~~.n',0x04\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror~~.w',0x02\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rpw~~dm',0x00\r
+       dw      ARM_instruction_rpwdm-instruction_handler\r
+       db      'rpw~~dp',0x00\r
+       dw      ARM_instruction_rpwdp-instruction_handler\r
+       db      'rpw~~dz',0x00\r
+       dw      ARM_instruction_rpwdz-instruction_handler\r
+       db      'rpw~~em',0x00\r
+       dw      ARM_instruction_rpwem-instruction_handler\r
+       db      'rpw~~ep',0x00\r
+       dw      ARM_instruction_rpwep-instruction_handler\r
+       db      'rpw~~ez',0x00\r
+       dw      ARM_instruction_rpwez-instruction_handler\r
+       db      'rpw~~sm',0x00\r
+       dw      ARM_instruction_rpwsm-instruction_handler\r
+       db      'rpw~~sp',0x00\r
+       dw      ARM_instruction_rpwsp-instruction_handler\r
+       db      'rpw~~sz',0x00\r
+       dw      ARM_instruction_rpwsz-instruction_handler\r
+       db      'rsb~~.n',0x04\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb~~.w',0x02\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsf~~dm',0x00\r
+       dw      ARM_instruction_rsfdm-instruction_handler\r
+       db      'rsf~~dp',0x00\r
+       dw      ARM_instruction_rsfdp-instruction_handler\r
+       db      'rsf~~dz',0x00\r
+       dw      ARM_instruction_rsfdz-instruction_handler\r
+       db      'rsf~~em',0x00\r
+       dw      ARM_instruction_rsfem-instruction_handler\r
+       db      'rsf~~ep',0x00\r
+       dw      ARM_instruction_rsfep-instruction_handler\r
+       db      'rsf~~ez',0x00\r
+       dw      ARM_instruction_rsfez-instruction_handler\r
+       db      'rsf~~sm',0x00\r
+       dw      ARM_instruction_rsfsm-instruction_handler\r
+       db      'rsf~~sp',0x00\r
+       dw      ARM_instruction_rsfsp-instruction_handler\r
+       db      'rsf~~sz',0x00\r
+       dw      ARM_instruction_rsfsz-instruction_handler\r
+       db      'rsubhn2',0xf0\r
+       dw      ARM_instruction_rsubhn2-instruction_handler\r
+       db      'sadd8~~',0x00\r
+       dw      ARM_instruction_sadd8-instruction_handler\r
+       db      'sbc~~.n',0x04\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc~~.w',0x02\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'section',0x00\r
+       dw      ARM_section_directive-instruction_handler\r
+       db      'segment',0x00\r
+       dw      segment_directive-instruction_handler\r
+       db      'sev~~.n',0x04\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sev~~.w',0x02\r
+       dw      ARM_instruction_sev-instruction_handler\r
+       db      'sfm~~ea',0x00\r
+       dw      ARM_instruction_sfmea-instruction_handler\r
+       db      'sfm~~fd',0x00\r
+       dw      ARM_instruction_sfmfd-instruction_handler\r
+       db      'sha1su0',0xf0\r
+       dw      ARM_instruction_sha1su0-instruction_handler\r
+       db      'sha1su1',0xf0\r
+       dw      ARM_instruction_sha1su1-instruction_handler\r
+       db      'sha256h',0xf0\r
+       dw      ARM_instruction_sha256h-instruction_handler\r
+       db      'shadd16',0xe0\r
+       dw      ARM_instruction_shadd16-instruction_handler\r
+       db      'shasx~~',0x00\r
+       dw      ARM_instruction_shasx-instruction_handler\r
+       db      'shsax~~',0x00\r
+       dw      ARM_instruction_shsax-instruction_handler\r
+       db      'shsub16',0xe0\r
+       dw      ARM_instruction_shsub16-instruction_handler\r
+       db      'sin~~dm',0x00\r
+       dw      ARM_instruction_sindm-instruction_handler\r
+       db      'sin~~dp',0x00\r
+       dw      ARM_instruction_sindp-instruction_handler\r
+       db      'sin~~dz',0x00\r
+       dw      ARM_instruction_sindz-instruction_handler\r
+       db      'sin~~em',0x00\r
+       dw      ARM_instruction_sinem-instruction_handler\r
+       db      'sin~~ep',0x00\r
+       dw      ARM_instruction_sinep-instruction_handler\r
+       db      'sin~~ez',0x00\r
+       dw      ARM_instruction_sinez-instruction_handler\r
+       db      'sin~~sm',0x00\r
+       dw      ARM_instruction_sinsm-instruction_handler\r
+       db      'sin~~sp',0x00\r
+       dw      ARM_instruction_sinsp-instruction_handler\r
+       db      'sin~~sz',0x00\r
+       dw      ARM_instruction_sinsz-instruction_handler\r
+       db      'smlad~~',0x00\r
+       dw      ARM_instruction_smlad-instruction_handler\r
+       db      'smlalbb',0xe0\r
+       dw      ARM_instruction_smlalbb-instruction_handler\r
+       db      'smlalbt',0xe0\r
+       dw      ARM_instruction_smlalbt-instruction_handler\r
+       db      'smlaldx',0xe0\r
+       dw      ARM_instruction_smlaldx-instruction_handler\r
+       db      'smlaltb',0xe0\r
+       dw      ARM_instruction_smlaltb-instruction_handler\r
+       db      'smlaltt',0xe0\r
+       dw      ARM_instruction_smlaltt-instruction_handler\r
+       db      'smlal~~',0x00\r
+       dw      ARM_instruction_smlal-instruction_handler\r
+       db      'smlsd~~',0x00\r
+       dw      ARM_instruction_smlsd-instruction_handler\r
+       db      'smlsldx',0xe0\r
+       dw      ARM_instruction_smlsldx-instruction_handler\r
+       db      'smmla~~',0x00\r
+       dw      ARM_instruction_smmla-instruction_handler\r
+       db      'smmls~~',0x00\r
+       dw      ARM_instruction_smmls-instruction_handler\r
+       db      'smmul~~',0x00\r
+       dw      ARM_instruction_smmul-instruction_handler\r
+       db      'smuad~~',0x00\r
+       dw      ARM_instruction_smuad-instruction_handler\r
+       db      'smull~~',0x00\r
+       dw      ARM_instruction_smull-instruction_handler\r
+       db      'smusd~~',0x00\r
+       dw      ARM_instruction_smusd-instruction_handler\r
+       db      'sqdmlal',0xf0\r
+       dw      ARM_instruction_sqdmlal-instruction_handler\r
+       db      'sqdmlsl',0xf0\r
+       dw      ARM_instruction_sqdmlsl-instruction_handler\r
+       db      'sqdmulh',0xf0\r
+       dw      ARM_instruction_sqdmulh-instruction_handler\r
+       db      'sqdmull',0xf0\r
+       dw      ARM_instruction_sqdmull-instruction_handler\r
+       db      'sqrshrn',0xf0\r
+       dw      ARM_instruction_sqrshrn-instruction_handler\r
+       db      'sqshrn2',0xf0\r
+       dw      ARM_instruction_sqshrn2-instruction_handler\r
+       db      'sqshrun',0xf0\r
+       dw      ARM_instruction_sqshrun-instruction_handler\r
+       db      'sqt~~dm',0x00\r
+       dw      ARM_instruction_sqtdm-instruction_handler\r
+       db      'sqt~~dp',0x00\r
+       dw      ARM_instruction_sqtdp-instruction_handler\r
+       db      'sqt~~dz',0x00\r
+       dw      ARM_instruction_sqtdz-instruction_handler\r
+       db      'sqt~~em',0x00\r
+       dw      ARM_instruction_sqtem-instruction_handler\r
+       db      'sqt~~ep',0x00\r
+       dw      ARM_instruction_sqtep-instruction_handler\r
+       db      'sqt~~ez',0x00\r
+       dw      ARM_instruction_sqtez-instruction_handler\r
+       db      'sqt~~sm',0x00\r
+       dw      ARM_instruction_sqtsm-instruction_handler\r
+       db      'sqt~~sp',0x00\r
+       dw      ARM_instruction_sqtsp-instruction_handler\r
+       db      'sqt~~sz',0x00\r
+       dw      ARM_instruction_sqtsz-instruction_handler\r
+       db      'sqxtun2',0xf0\r
+       dw      ARM_instruction_sqxtun2-instruction_handler\r
+       db      'ssub8~~',0x00\r
+       dw      ARM_instruction_ssub8-instruction_handler\r
+       db      'stc2l~~',0x00\r
+       dw      ARM_instruction_stc2l-instruction_handler\r
+       db      'stlex~~',0x00\r
+       dw      ARM_instruction_stlex-instruction_handler\r
+       db      'stmda~~',0x00\r
+       dw      ARM_instruction_stmda-instruction_handler\r
+       db      'stmdb.n',0xe4\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmdb.w',0xe2\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmdb~~',0x00\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmea~~',0x00\r
+       dw      ARM_instruction_stmea-instruction_handler\r
+       db      'stmed~~',0x00\r
+       dw      ARM_instruction_stmed-instruction_handler\r
+       db      'stmfa~~',0x00\r
+       dw      ARM_instruction_stmfa-instruction_handler\r
+       db      'stmfd.n',0xe4\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmfd.w',0xe2\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmfd~~',0x00\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmia.n',0xe4\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stmia.w',0xe2\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stmia~~',0x00\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stmib~~',0x00\r
+       dw      ARM_instruction_stmib-instruction_handler\r
+       db      'stm~~.n',0x04\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'stm~~.w',0x02\r
+       dw      ARM_instruction_stm-instruction_handler\r
+       db      'stm~~da',0x00\r
+       dw      ARM_instruction_stmda-instruction_handler\r
+       db      'stm~~db',0x00\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stm~~ea',0x00\r
+       dw      ARM_instruction_stmea-instruction_handler\r
+       db      'stm~~ed',0x00\r
+       dw      ARM_instruction_stmed-instruction_handler\r
+       db      'stm~~fa',0x00\r
+       dw      ARM_instruction_stmfa-instruction_handler\r
+       db      'stm~~fd',0x00\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stm~~ia',0x00\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stm~~ib',0x00\r
+       dw      ARM_instruction_stmib-instruction_handler\r
+       db      'strbt~~',0x00\r
+       dw      ARM_instruction_strbt-instruction_handler\r
+       db      'strex~~',0x00\r
+       dw      ARM_instruction_strex-instruction_handler\r
+       db      'strht~~',0x00\r
+       dw      ARM_instruction_strht-instruction_handler\r
+       db      'str~~.n',0x04\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'str~~.w',0x02\r
+       dw      ARM_instruction_str-instruction_handler\r
+       db      'str~~bt',0x00\r
+       dw      ARM_instruction_strbt-instruction_handler\r
+       db      'str~~ht',0x00\r
+       dw      ARM_instruction_strht-instruction_handler\r
+       db      'sub~~.n',0x04\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sub~~.w',0x02\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'suf~~dm',0x00\r
+       dw      ARM_instruction_sufdm-instruction_handler\r
+       db      'suf~~dp',0x00\r
+       dw      ARM_instruction_sufdp-instruction_handler\r
+       db      'suf~~dz',0x00\r
+       dw      ARM_instruction_sufdz-instruction_handler\r
+       db      'suf~~em',0x00\r
+       dw      ARM_instruction_sufem-instruction_handler\r
+       db      'suf~~ep',0x00\r
+       dw      ARM_instruction_sufep-instruction_handler\r
+       db      'suf~~ez',0x00\r
+       dw      ARM_instruction_sufez-instruction_handler\r
+       db      'suf~~sm',0x00\r
+       dw      ARM_instruction_sufsm-instruction_handler\r
+       db      'suf~~sp',0x00\r
+       dw      ARM_instruction_sufsp-instruction_handler\r
+       db      'suf~~sz',0x00\r
+       dw      ARM_instruction_sufsz-instruction_handler\r
+       db      'svc~~.n',0x04\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'svc~~.w',0x02\r
+       dw      ARM_instruction_svc-instruction_handler\r
+       db      'swi~~.n',0x04\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'swi~~.w',0x02\r
+       dw      ARM_instruction_swi-instruction_handler\r
+       db      'sxtab16',0xe0\r
+       dw      ARM_instruction_sxtab16-instruction_handler\r
+       db      'sxtab~~',0x00\r
+       dw      ARM_instruction_sxtab-instruction_handler\r
+       db      'sxtah~~',0x00\r
+       dw      ARM_instruction_sxtah-instruction_handler\r
+       db      'tan~~dm',0x00\r
+       dw      ARM_instruction_tandm-instruction_handler\r
+       db      'tan~~dp',0x00\r
+       dw      ARM_instruction_tandp-instruction_handler\r
+       db      'tan~~dz',0x00\r
+       dw      ARM_instruction_tandz-instruction_handler\r
+       db      'tan~~em',0x00\r
+       dw      ARM_instruction_tanem-instruction_handler\r
+       db      'tan~~ep',0x00\r
+       dw      ARM_instruction_tanep-instruction_handler\r
+       db      'tan~~ez',0x00\r
+       dw      ARM_instruction_tanez-instruction_handler\r
+       db      'tan~~sm',0x00\r
+       dw      ARM_instruction_tansm-instruction_handler\r
+       db      'tan~~sp',0x00\r
+       dw      ARM_instruction_tansp-instruction_handler\r
+       db      'tan~~sz',0x00\r
+       dw      ARM_instruction_tansz-instruction_handler\r
+       db      'textrcb',0xe0\r
+       dw      ARM_instruction_textrcb-instruction_handler\r
+       db      'textrch',0xe0\r
+       dw      ARM_instruction_textrch-instruction_handler\r
+       db      'textrcw',0xe0\r
+       dw      ARM_instruction_textrcw-instruction_handler\r
+       db      'thumbee',0x00\r
+       dw      ARM_thumbee_directive-instruction_handler\r
+       db      'tmcrr~~',0x00\r
+       dw      ARM_instruction_tmcrr-instruction_handler\r
+       db      'tmrrc~~',0x00\r
+       dw      ARM_instruction_tmrrc-instruction_handler\r
+       db      'torcb~~',0x00\r
+       dw      ARM_instruction_torcb-instruction_handler\r
+       db      'torch~~',0x00\r
+       dw      ARM_instruction_torch-instruction_handler\r
+       db      'torcw~~',0x00\r
+       dw      ARM_instruction_torcw-instruction_handler\r
+       db      'torvscb',0xe0\r
+       dw      ARM_instruction_torvscb-instruction_handler\r
+       db      'torvsch',0xe0\r
+       dw      ARM_instruction_torvsch-instruction_handler\r
+       db      'torvscw',0xe0\r
+       dw      ARM_instruction_torvscw-instruction_handler\r
+       db      'tst~~.n',0x04\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'tst~~.w',0x02\r
+       dw      ARM_instruction_tst-instruction_handler\r
+       db      'uadd8~~',0x00\r
+       dw      ARM_instruction_uadd8-instruction_handler\r
+       db      'uhadd16',0xe0\r
+       dw      ARM_instruction_uhadd16-instruction_handler\r
+       db      'uhasx~~',0x00\r
+       dw      ARM_instruction_uhasx-instruction_handler\r
+       db      'uhsax~~',0x00\r
+       dw      ARM_instruction_uhsax-instruction_handler\r
+       db      'uhsub16',0xe0\r
+       dw      ARM_instruction_uhsub16-instruction_handler\r
+       db      'umaal~~',0x00\r
+       dw      ARM_instruction_umaal-instruction_handler\r
+       db      'umlal~~',0x00\r
+       dw      ARM_instruction_umlal-instruction_handler\r
+       db      'umull~~',0x00\r
+       dw      ARM_instruction_umull-instruction_handler\r
+       db      'und~~.n',0x04\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'und~~.w',0x02\r
+       dw      ARM_instruction_und-instruction_handler\r
+       db      'uqadd16',0xe0\r
+       dw      ARM_instruction_uqadd16-instruction_handler\r
+       db      'uqasx~~',0x00\r
+       dw      ARM_instruction_uqasx-instruction_handler\r
+       db      'uqrshrn',0xf0\r
+       dw      ARM_instruction_uqrshrn-instruction_handler\r
+       db      'uqsax~~',0x00\r
+       dw      ARM_instruction_uqsax-instruction_handler\r
+       db      'uqshrn2',0xf0\r
+       dw      ARM_instruction_uqshrn2-instruction_handler\r
+       db      'uqsub16',0xe0\r
+       dw      ARM_instruction_uqsub16-instruction_handler\r
+       db      'urd~~dm',0x00\r
+       dw      ARM_instruction_urddm-instruction_handler\r
+       db      'urd~~dp',0x00\r
+       dw      ARM_instruction_urddp-instruction_handler\r
+       db      'urd~~dz',0x00\r
+       dw      ARM_instruction_urddz-instruction_handler\r
+       db      'urd~~em',0x00\r
+       dw      ARM_instruction_urdem-instruction_handler\r
+       db      'urd~~ep',0x00\r
+       dw      ARM_instruction_urdep-instruction_handler\r
+       db      'urd~~ez',0x00\r
+       dw      ARM_instruction_urdez-instruction_handler\r
+       db      'urd~~sm',0x00\r
+       dw      ARM_instruction_urdsm-instruction_handler\r
+       db      'urd~~sp',0x00\r
+       dw      ARM_instruction_urdsp-instruction_handler\r
+       db      'urd~~sz',0x00\r
+       dw      ARM_instruction_urdsz-instruction_handler\r
+       db      'ursqrte',0xf0\r
+       dw      ARM_instruction_ursqrte-instruction_handler\r
+       db      'usad8~~',0x00\r
+       dw      ARM_instruction_usad8-instruction_handler\r
+       db      'usub8~~',0x00\r
+       dw      ARM_instruction_usub8-instruction_handler\r
+       db      'uxtab16',0xe0\r
+       dw      ARM_instruction_uxtab16-instruction_handler\r
+       db      'uxtab~~',0x00\r
+       dw      ARM_instruction_uxtab-instruction_handler\r
+       db      'uxtah~~',0x00\r
+       dw      ARM_instruction_uxtah-instruction_handler\r
+       db      'vaba.s8',0xe0\r
+       dw      ARM_instruction_vaba.s8-instruction_handler\r
+       db      'vaba.u8',0xe0\r
+       dw      ARM_instruction_vaba.u8-instruction_handler\r
+       db      'vabd.s8',0xe0\r
+       dw      ARM_instruction_vabd.s8-instruction_handler\r
+       db      'vabd.u8',0xe0\r
+       dw      ARM_instruction_vabd.u8-instruction_handler\r
+       db      'vabs.s8',0xe0\r
+       dw      ARM_instruction_vabs.s8-instruction_handler\r
+       db      'vadd.i8',0xe0\r
+       dw      ARM_instruction_vadd.i8-instruction_handler\r
+       db      'vceq.i8',0xe0\r
+       dw      ARM_instruction_vceq.i8-instruction_handler\r
+       db      'vcge.s8',0xe0\r
+       dw      ARM_instruction_vcge.s8-instruction_handler\r
+       db      'vcge.u8',0xe0\r
+       dw      ARM_instruction_vcge.u8-instruction_handler\r
+       db      'vcgt.s8',0xe0\r
+       dw      ARM_instruction_vcgt.s8-instruction_handler\r
+       db      'vcgt.u8',0xe0\r
+       dw      ARM_instruction_vcgt.u8-instruction_handler\r
+       db      'vcle.s8',0xe0\r
+       dw      ARM_instruction_vcle.s8-instruction_handler\r
+       db      'vcle.u8',0xe0\r
+       dw      ARM_instruction_vcle.u8-instruction_handler\r
+       db      'vcls.s8',0xe0\r
+       dw      ARM_instruction_vcls.s8-instruction_handler\r
+       db      'vclt.s8',0xe0\r
+       dw      ARM_instruction_vclt.s8-instruction_handler\r
+       db      'vclt.u8',0xe0\r
+       dw      ARM_instruction_vclt.u8-instruction_handler\r
+       db      'vclz.i8',0xe0\r
+       dw      ARM_instruction_vclz.i8-instruction_handler\r
+       db      'vdup.16',0xe0\r
+       dw      ARM_instruction_vdup.16-instruction_handler\r
+       db      'vdup.32',0xe0\r
+       dw      ARM_instruction_vdup.32-instruction_handler\r
+       db      'vext.16',0xe0\r
+       dw      ARM_instruction_vext.16-instruction_handler\r
+       db      'vext.32',0xe0\r
+       dw      ARM_instruction_vext.32-instruction_handler\r
+       db      'vext.64',0xe0\r
+       dw      ARM_instruction_vext.64-instruction_handler\r
+       db      'virtual',0x00\r
+       dw      virtual_directive-instruction_handler\r
+       db      'vld1.16',0xe0\r
+       dw      ARM_instruction_vld1.16-instruction_handler\r
+       db      'vld1.32',0xe0\r
+       dw      ARM_instruction_vld1.32-instruction_handler\r
+       db      'vld1.64',0xe0\r
+       dw      ARM_instruction_vld1.64-instruction_handler\r
+       db      'vld2.16',0xe0\r
+       dw      ARM_instruction_vld2.16-instruction_handler\r
+       db      'vld2.32',0xe0\r
+       dw      ARM_instruction_vld2.32-instruction_handler\r
+       db      'vld3.16',0xe0\r
+       dw      ARM_instruction_vld3.16-instruction_handler\r
+       db      'vld3.32',0xe0\r
+       dw      ARM_instruction_vld3.32-instruction_handler\r
+       db      'vld4.16',0xe0\r
+       dw      ARM_instruction_vld4.16-instruction_handler\r
+       db      'vld4.32',0xe0\r
+       dw      ARM_instruction_vld4.32-instruction_handler\r
+       db      'vldm.32',0xe0\r
+       dw      ARM_instruction_vldm.32-instruction_handler\r
+       db      'vldm.64',0xe0\r
+       dw      ARM_instruction_vldm.64-instruction_handler\r
+       db      'vldr.32',0xe0\r
+       dw      ARM_instruction_vldr.32-instruction_handler\r
+       db      'vldr.64',0xe0\r
+       dw      ARM_instruction_vldr.64-instruction_handler\r
+       db      'vmax.s8',0xe0\r
+       dw      ARM_instruction_vmax.s8-instruction_handler\r
+       db      'vmax.u8',0xe0\r
+       dw      ARM_instruction_vmax.u8-instruction_handler\r
+       db      'vmin.s8',0xe0\r
+       dw      ARM_instruction_vmin.s8-instruction_handler\r
+       db      'vmin.u8',0xe0\r
+       dw      ARM_instruction_vmin.u8-instruction_handler\r
+       db      'vmla.i8',0xe0\r
+       dw      ARM_instruction_vmla.i8-instruction_handler\r
+       db      'vmla.s8',0xe0\r
+       dw      ARM_instruction_vmla.s8-instruction_handler\r
+       db      'vmla.u8',0xe0\r
+       dw      ARM_instruction_vmla.u8-instruction_handler\r
+       db      'vmls.i8',0xe0\r
+       dw      ARM_instruction_vmls.i8-instruction_handler\r
+       db      'vmls.s8',0xe0\r
+       dw      ARM_instruction_vmls.s8-instruction_handler\r
+       db      'vmls.u8',0xe0\r
+       dw      ARM_instruction_vmls.u8-instruction_handler\r
+       db      'vmov.16',0xe0\r
+       dw      ARM_instruction_vmov.16-instruction_handler\r
+       db      'vmov.32',0xe0\r
+       dw      ARM_instruction_vmov.32-instruction_handler\r
+       db      'vmov.i8',0xe0\r
+       dw      ARM_instruction_vmov.i8-instruction_handler\r
+       db      'vmov.s8',0xe0\r
+       dw      ARM_instruction_vmov.s8-instruction_handler\r
+       db      'vmov.u8',0xe0\r
+       dw      ARM_instruction_vmov.u8-instruction_handler\r
+       db      'vmul.i8',0xe0\r
+       dw      ARM_instruction_vmul.i8-instruction_handler\r
+       db      'vmul.p8',0xe0\r
+       dw      ARM_instruction_vmul.p8-instruction_handler\r
+       db      'vmul.s8',0xe0\r
+       dw      ARM_instruction_vmul.s8-instruction_handler\r
+       db      'vmul.u8',0xe0\r
+       dw      ARM_instruction_vmul.u8-instruction_handler\r
+       db      'vneg.s8',0xe0\r
+       dw      ARM_instruction_vneg.s8-instruction_handler\r
+       db      'vpop.32',0xe0\r
+       dw      ARM_instruction_vpop.32-instruction_handler\r
+       db      'vpop.64',0xe0\r
+       dw      ARM_instruction_vpop.64-instruction_handler\r
+       db      'vpush~~',0x00\r
+       dw      ARM_instruction_vpush-instruction_handler\r
+       db      'vshl.i8',0xe0\r
+       dw      ARM_instruction_vshl.i8-instruction_handler\r
+       db      'vshl.s8',0xe0\r
+       dw      ARM_instruction_vshl.s8-instruction_handler\r
+       db      'vshl.u8',0xe0\r
+       dw      ARM_instruction_vshl.u8-instruction_handler\r
+       db      'vshr.s8',0xe0\r
+       dw      ARM_instruction_vshr.s8-instruction_handler\r
+       db      'vshr.u8',0xe0\r
+       dw      ARM_instruction_vshr.u8-instruction_handler\r
+       db      'vsli.16',0xe0\r
+       dw      ARM_instruction_vsli.16-instruction_handler\r
+       db      'vsli.32',0xe0\r
+       dw      ARM_instruction_vsli.32-instruction_handler\r
+       db      'vsli.64',0xe0\r
+       dw      ARM_instruction_vsli.64-instruction_handler\r
+       db      'vsra.s8',0xe0\r
+       dw      ARM_instruction_vsra.s8-instruction_handler\r
+       db      'vsra.u8',0xe0\r
+       dw      ARM_instruction_vsra.u8-instruction_handler\r
+       db      'vsri.16',0xe0\r
+       dw      ARM_instruction_vsri.16-instruction_handler\r
+       db      'vsri.32',0xe0\r
+       dw      ARM_instruction_vsri.32-instruction_handler\r
+       db      'vsri.64',0xe0\r
+       dw      ARM_instruction_vsri.64-instruction_handler\r
+       db      'vst1.16',0xe0\r
+       dw      ARM_instruction_vst1.16-instruction_handler\r
+       db      'vst1.32',0xe0\r
+       dw      ARM_instruction_vst1.32-instruction_handler\r
+       db      'vst1.64',0xe0\r
+       dw      ARM_instruction_vst1.64-instruction_handler\r
+       db      'vst2.16',0xe0\r
+       dw      ARM_instruction_vst2.16-instruction_handler\r
+       db      'vst2.32',0xe0\r
+       dw      ARM_instruction_vst2.32-instruction_handler\r
+       db      'vst3.16',0xe0\r
+       dw      ARM_instruction_vst3.16-instruction_handler\r
+       db      'vst3.32',0xe0\r
+       dw      ARM_instruction_vst3.32-instruction_handler\r
+       db      'vst4.16',0xe0\r
+       dw      ARM_instruction_vst4.16-instruction_handler\r
+       db      'vst4.32',0xe0\r
+       dw      ARM_instruction_vst4.32-instruction_handler\r
+       db      'vstm.32',0xe0\r
+       dw      ARM_instruction_vstm.32-instruction_handler\r
+       db      'vstm.64',0xe0\r
+       dw      ARM_instruction_vstm.64-instruction_handler\r
+       db      'vstr.32',0xe0\r
+       dw      ARM_instruction_vstr.32-instruction_handler\r
+       db      'vstr.64',0xe0\r
+       dw      ARM_instruction_vstr.64-instruction_handler\r
+       db      'vsub.i8',0xe0\r
+       dw      ARM_instruction_vsub.i8-instruction_handler\r
+       db      'vtrn.16',0xe0\r
+       dw      ARM_instruction_vtrn.16-instruction_handler\r
+       db      'vtrn.32',0xe0\r
+       dw      ARM_instruction_vtrn.32-instruction_handler\r
+       db      'vtst.16',0xe0\r
+       dw      ARM_instruction_vtst.16-instruction_handler\r
+       db      'vtst.32',0xe0\r
+       dw      ARM_instruction_vtst.32-instruction_handler\r
+       db      'vuzp.16',0xe0\r
+       dw      ARM_instruction_vuzp.16-instruction_handler\r
+       db      'vuzp.32',0xe0\r
+       dw      ARM_instruction_vuzp.32-instruction_handler\r
+       db      'vzip.16',0xe0\r
+       dw      ARM_instruction_vzip.16-instruction_handler\r
+       db      'vzip.32',0xe0\r
+       dw      ARM_instruction_vzip.32-instruction_handler\r
+       db      'wabsb~~',0x00\r
+       dw      ARM_instruction_wabsb-instruction_handler\r
+       db      'wabsh~~',0x00\r
+       dw      ARM_instruction_wabsh-instruction_handler\r
+       db      'wabsw~~',0x00\r
+       dw      ARM_instruction_wabsw-instruction_handler\r
+       db      'waccb~~',0x00\r
+       dw      ARM_instruction_waccb-instruction_handler\r
+       db      'wacch~~',0x00\r
+       dw      ARM_instruction_wacch-instruction_handler\r
+       db      'waccw~~',0x00\r
+       dw      ARM_instruction_waccw-instruction_handler\r
+       db      'waddbss',0xe0\r
+       dw      ARM_instruction_waddbss-instruction_handler\r
+       db      'waddbus',0xe0\r
+       dw      ARM_instruction_waddbus-instruction_handler\r
+       db      'waddb~~',0x00\r
+       dw      ARM_instruction_waddb-instruction_handler\r
+       db      'waddhss',0xe0\r
+       dw      ARM_instruction_waddhss-instruction_handler\r
+       db      'waddhus',0xe0\r
+       dw      ARM_instruction_waddhus-instruction_handler\r
+       db      'waddh~~',0x00\r
+       dw      ARM_instruction_waddh-instruction_handler\r
+       db      'waddwss',0xe0\r
+       dw      ARM_instruction_waddwss-instruction_handler\r
+       db      'waddwus',0xe0\r
+       dw      ARM_instruction_waddwus-instruction_handler\r
+       db      'waddw~~',0x00\r
+       dw      ARM_instruction_waddw-instruction_handler\r
+       db      'waligni',0xe0\r
+       dw      ARM_instruction_waligni-instruction_handler\r
+       db      'wandn~~',0x00\r
+       dw      ARM_instruction_wandn-instruction_handler\r
+       db      'wavg2br',0xe0\r
+       dw      ARM_instruction_wavg2br-instruction_handler\r
+       db      'wavg2hr',0xe0\r
+       dw      ARM_instruction_wavg2hr-instruction_handler\r
+       db      'wavg4~~',0x00\r
+       dw      ARM_instruction_wavg4-instruction_handler\r
+       db      'wcmpeqb',0xe0\r
+       dw      ARM_instruction_wcmpeqb-instruction_handler\r
+       db      'wcmpeqh',0xe0\r
+       dw      ARM_instruction_wcmpeqh-instruction_handler\r
+       db      'wcmpeqw',0xe0\r
+       dw      ARM_instruction_wcmpeqw-instruction_handler\r
+       db      'wfe~~.n',0x04\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfe~~.w',0x02\r
+       dw      ARM_instruction_wfe-instruction_handler\r
+       db      'wfi~~.n',0x04\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wfi~~.w',0x02\r
+       dw      ARM_instruction_wfi-instruction_handler\r
+       db      'wldrb~~',0x00\r
+       dw      ARM_instruction_wldrb-instruction_handler\r
+       db      'wldrd~~',0x00\r
+       dw      ARM_instruction_wldrd-instruction_handler\r
+       db      'wldrh~~',0x00\r
+       dw      ARM_instruction_wldrh-instruction_handler\r
+       db      'wldrw~~',0x00\r
+       dw      ARM_instruction_wldrw-instruction_handler\r
+       db      'wmacs~~',0x00\r
+       dw      ARM_instruction_wmacs-instruction_handler\r
+       db      'wmacu~~',0x00\r
+       dw      ARM_instruction_wmacu-instruction_handler\r
+       db      'wmaddsn',0xe0\r
+       dw      ARM_instruction_wmaddsn-instruction_handler\r
+       db      'wmaddsx',0xe0\r
+       dw      ARM_instruction_wmaddsx-instruction_handler\r
+       db      'wmaddun',0xe0\r
+       dw      ARM_instruction_wmaddun-instruction_handler\r
+       db      'wmaddux',0xe0\r
+       dw      ARM_instruction_wmaddux-instruction_handler\r
+       db      'wmiabbn',0xe0\r
+       dw      ARM_instruction_wmiabbn-instruction_handler\r
+       db      'wmiabtn',0xe0\r
+       dw      ARM_instruction_wmiabtn-instruction_handler\r
+       db      'wmiatbn',0xe0\r
+       dw      ARM_instruction_wmiatbn-instruction_handler\r
+       db      'wmiattn',0xe0\r
+       dw      ARM_instruction_wmiattn-instruction_handler\r
+       db      'wmiawbb',0xe0\r
+       dw      ARM_instruction_wmiawbb-instruction_handler\r
+       db      'wmiawbt',0xe0\r
+       dw      ARM_instruction_wmiawbt-instruction_handler\r
+       db      'wmiawtb',0xe0\r
+       dw      ARM_instruction_wmiawtb-instruction_handler\r
+       db      'wmiawtt',0xe0\r
+       dw      ARM_instruction_wmiawtt-instruction_handler\r
+       db      'wmulsmr',0xe0\r
+       dw      ARM_instruction_wmulsmr-instruction_handler\r
+       db      'wmulumr',0xe0\r
+       dw      ARM_instruction_wmulumr-instruction_handler\r
+       db      'wmulwsm',0xe0\r
+       dw      ARM_instruction_wmulwsm-instruction_handler\r
+       db      'wmulwum',0xe0\r
+       dw      ARM_instruction_wmulwum-instruction_handler\r
+       db      'wqmiabb',0xe0\r
+       dw      ARM_instruction_wqmiabb-instruction_handler\r
+       db      'wqmiabt',0xe0\r
+       dw      ARM_instruction_wqmiabt-instruction_handler\r
+       db      'wqmiatb',0xe0\r
+       dw      ARM_instruction_wqmiatb-instruction_handler\r
+       db      'wqmiatt',0xe0\r
+       dw      ARM_instruction_wqmiatt-instruction_handler\r
+       db      'wqmulmr',0xe0\r
+       dw      ARM_instruction_wqmulmr-instruction_handler\r
+       db      'wqmulwm',0xe0\r
+       dw      ARM_instruction_wqmulwm-instruction_handler\r
+       db      'wrord~~',0x00\r
+       dw      ARM_instruction_wrord-instruction_handler\r
+       db      'wrorh~~',0x00\r
+       dw      ARM_instruction_wrorh-instruction_handler\r
+       db      'wrorw~~',0x00\r
+       dw      ARM_instruction_wrorw-instruction_handler\r
+       db      'wsadb~~',0x00\r
+       dw      ARM_instruction_wsadb-instruction_handler\r
+       db      'wsadh~~',0x00\r
+       dw      ARM_instruction_wsadh-instruction_handler\r
+       db      'wslld~~',0x00\r
+       dw      ARM_instruction_wslld-instruction_handler\r
+       db      'wsllh~~',0x00\r
+       dw      ARM_instruction_wsllh-instruction_handler\r
+       db      'wsllw~~',0x00\r
+       dw      ARM_instruction_wsllw-instruction_handler\r
+       db      'wsrad~~',0x00\r
+       dw      ARM_instruction_wsrad-instruction_handler\r
+       db      'wsrah~~',0x00\r
+       dw      ARM_instruction_wsrah-instruction_handler\r
+       db      'wsraw~~',0x00\r
+       dw      ARM_instruction_wsraw-instruction_handler\r
+       db      'wsrld~~',0x00\r
+       dw      ARM_instruction_wsrld-instruction_handler\r
+       db      'wsrlh~~',0x00\r
+       dw      ARM_instruction_wsrlh-instruction_handler\r
+       db      'wsrlw~~',0x00\r
+       dw      ARM_instruction_wsrlw-instruction_handler\r
+       db      'wstrb~~',0x00\r
+       dw      ARM_instruction_wstrb-instruction_handler\r
+       db      'wstrd~~',0x00\r
+       dw      ARM_instruction_wstrd-instruction_handler\r
+       db      'wstrh~~',0x00\r
+       dw      ARM_instruction_wstrh-instruction_handler\r
+       db      'wstrw~~',0x00\r
+       dw      ARM_instruction_wstrw-instruction_handler\r
+       db      'wsubbss',0xe0\r
+       dw      ARM_instruction_wsubbss-instruction_handler\r
+       db      'wsubbus',0xe0\r
+       dw      ARM_instruction_wsubbus-instruction_handler\r
+       db      'wsubb~~',0x00\r
+       dw      ARM_instruction_wsubb-instruction_handler\r
+       db      'wsubhss',0xe0\r
+       dw      ARM_instruction_wsubhss-instruction_handler\r
+       db      'wsubhus',0xe0\r
+       dw      ARM_instruction_wsubhus-instruction_handler\r
+       db      'wsubh~~',0x00\r
+       dw      ARM_instruction_wsubh-instruction_handler\r
+       db      'wsubwss',0xe0\r
+       dw      ARM_instruction_wsubwss-instruction_handler\r
+       db      'wsubwus',0xe0\r
+       dw      ARM_instruction_wsubwus-instruction_handler\r
+       db      'wsubw~~',0x00\r
+       dw      ARM_instruction_wsubw-instruction_handler\r
+       db      'wzero~~',0x00\r
+       dw      ARM_instruction_wzero-instruction_handler\r
+       db      'yield.n',0xe4\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      'yield.w',0xe2\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      'yield~~',0x00\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      0\r
+instructions_8:\r
+       db      'adcs~~.n',0x05\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adcs~~.w',0x03\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc~~s.n',0x05\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adc~~s.w',0x03\r
+       dw      ARM_instruction_adc-instruction_handler\r
+       db      'adds~~.n',0x05\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'adds~~.w',0x03\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'add~~s.n',0x05\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'add~~s.w',0x03\r
+       dw      ARM_instruction_add-instruction_handler\r
+       db      'aesimc.8',0xf0\r
+       dw      ARM_instruction_aesimc.8-instruction_handler\r
+       db      'ands~~.n',0x05\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'ands~~.w',0x03\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and~~s.n',0x05\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'and~~s.w',0x03\r
+       dw      ARM_instruction_and-instruction_handler\r
+       db      'asrs~~.n',0x05\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asrs~~.w',0x03\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr~~s.n',0x05\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'asr~~s.w',0x03\r
+       dw      ARM_instruction_asr-instruction_handler\r
+       db      'bics~~.n',0x05\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bics~~.w',0x03\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic~~s.n',0x05\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'bic~~s.w',0x03\r
+       dw      ARM_instruction_bic-instruction_handler\r
+       db      'cfabsd~~',0x00\r
+       dw      ARM_instruction_cfabsd-instruction_handler\r
+       db      'cfabss~~',0x00\r
+       dw      ARM_instruction_cfabss-instruction_handler\r
+       db      'cfaddd~~',0x00\r
+       dw      ARM_instruction_cfaddd-instruction_handler\r
+       db      'cfadds~~',0x00\r
+       dw      ARM_instruction_cfadds-instruction_handler\r
+       db      'cfcmpd~~',0x00\r
+       dw      ARM_instruction_cfcmpd-instruction_handler\r
+       db      'cfcmps~~',0x00\r
+       dw      ARM_instruction_cfcmps-instruction_handler\r
+       db      'cfcpyd~~',0x00\r
+       dw      ARM_instruction_cfcpyd-instruction_handler\r
+       db      'cfcpys~~',0x00\r
+       dw      ARM_instruction_cfcpys-instruction_handler\r
+       db      'cfcvt32d',0xe0\r
+       dw      ARM_instruction_cfcvt32d-instruction_handler\r
+       db      'cfcvt32s',0xe0\r
+       dw      ARM_instruction_cfcvt32s-instruction_handler\r
+       db      'cfcvt64d',0xe0\r
+       dw      ARM_instruction_cfcvt64d-instruction_handler\r
+       db      'cfcvt64s',0xe0\r
+       dw      ARM_instruction_cfcvt64s-instruction_handler\r
+       db      'cfcvtd32',0xe0\r
+       dw      ARM_instruction_cfcvtd32-instruction_handler\r
+       db      'cfcvts32',0xe0\r
+       dw      ARM_instruction_cfcvts32-instruction_handler\r
+       db      'cfldrd~~',0x00\r
+       dw      ARM_instruction_cfldrd-instruction_handler\r
+       db      'cfldrs~~',0x00\r
+       dw      ARM_instruction_cfldrs-instruction_handler\r
+       db      'cfmadd32',0xe0\r
+       dw      ARM_instruction_cfmadd32-instruction_handler\r
+       db      'cfmsub32',0xe0\r
+       dw      ARM_instruction_cfmsub32-instruction_handler\r
+       db      'cfmuld~~',0x00\r
+       dw      ARM_instruction_cfmuld-instruction_handler\r
+       db      'cfmuls~~',0x00\r
+       dw      ARM_instruction_cfmuls-instruction_handler\r
+       db      'cfmv32ah',0xe0\r
+       dw      ARM_instruction_cfmv32ah-instruction_handler\r
+       db      'cfmv32al',0xe0\r
+       dw      ARM_instruction_cfmv32al-instruction_handler\r
+       db      'cfmv32am',0xe0\r
+       dw      ARM_instruction_cfmv32am-instruction_handler\r
+       db      'cfmv32sc',0xe0\r
+       dw      ARM_instruction_cfmv32sc-instruction_handler\r
+       db      'cfmv64hr',0xe0\r
+       dw      ARM_instruction_cfmv64hr-instruction_handler\r
+       db      'cfmv64lr',0xe0\r
+       dw      ARM_instruction_cfmv64lr-instruction_handler\r
+       db      'cfmvah32',0xe0\r
+       dw      ARM_instruction_cfmvah32-instruction_handler\r
+       db      'cfmval32',0xe0\r
+       dw      ARM_instruction_cfmval32-instruction_handler\r
+       db      'cfmvam32',0xe0\r
+       dw      ARM_instruction_cfmvam32-instruction_handler\r
+       db      'cfmvr64h',0xe0\r
+       dw      ARM_instruction_cfmvr64h-instruction_handler\r
+       db      'cfmvr64l',0xe0\r
+       dw      ARM_instruction_cfmvr64l-instruction_handler\r
+       db      'cfmvrs~~',0x00\r
+       dw      ARM_instruction_cfmvrs-instruction_handler\r
+       db      'cfmvsc32',0xe0\r
+       dw      ARM_instruction_cfmvsc32-instruction_handler\r
+       db      'cfmvsr~~',0x00\r
+       dw      ARM_instruction_cfmvsr-instruction_handler\r
+       db      'cfnegd~~',0x00\r
+       dw      ARM_instruction_cfnegd-instruction_handler\r
+       db      'cfnegs~~',0x00\r
+       dw      ARM_instruction_cfnegs-instruction_handler\r
+       db      'cfrshl32',0xe0\r
+       dw      ARM_instruction_cfrshl32-instruction_handler\r
+       db      'cfrshl64',0xe0\r
+       dw      ARM_instruction_cfrshl64-instruction_handler\r
+       db      'cfsh32~~',0x00\r
+       dw      ARM_instruction_cfsh32-instruction_handler\r
+       db      'cfsh64~~',0x00\r
+       dw      ARM_instruction_cfsh64-instruction_handler\r
+       db      'cfstrd~~',0x00\r
+       dw      ARM_instruction_cfstrd-instruction_handler\r
+       db      'cfstrs~~',0x00\r
+       dw      ARM_instruction_cfstrs-instruction_handler\r
+       db      'cfsubd~~',0x00\r
+       dw      ARM_instruction_cfsubd-instruction_handler\r
+       db      'cfsubs~~',0x00\r
+       dw      ARM_instruction_cfsubs-instruction_handler\r
+       db      'eors~~.n',0x05\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eors~~.w',0x03\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor~~s.n',0x05\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'eor~~s.w',0x03\r
+       dw      ARM_instruction_eor-instruction_handler\r
+       db      'fcmped~~',0x00\r
+       dw      ARM_instruction_fcmped-instruction_handler\r
+       db      'fcmpes~~',0x00\r
+       dw      ARM_instruction_fcmpes-instruction_handler\r
+       db      'fcmpzd~~',0x00\r
+       dw      ARM_instruction_fcmpzd-instruction_handler\r
+       db      'fcmpzs~~',0x00\r
+       dw      ARM_instruction_fcmpzs-instruction_handler\r
+       db      'fcvtds~~',0x00\r
+       dw      ARM_instruction_fcvtds-instruction_handler\r
+       db      'fcvtsd~~',0x00\r
+       dw      ARM_instruction_fcvtsd-instruction_handler\r
+       db      'fmstat~~',0x00\r
+       dw      ARM_instruction_fmstat-instruction_handler\r
+       db      'fnmacd~~',0x00\r
+       dw      ARM_instruction_fnmacd-instruction_handler\r
+       db      'fnmacs~~',0x00\r
+       dw      ARM_instruction_fnmacs-instruction_handler\r
+       db      'fnmscd~~',0x00\r
+       dw      ARM_instruction_fnmscd-instruction_handler\r
+       db      'fnmscs~~',0x00\r
+       dw      ARM_instruction_fnmscs-instruction_handler\r
+       db      'fnmuld~~',0x00\r
+       dw      ARM_instruction_fnmuld-instruction_handler\r
+       db      'fnmuls~~',0x00\r
+       dw      ARM_instruction_fnmuls-instruction_handler\r
+       db      'fshtod~~',0x00\r
+       dw      ARM_instruction_fshtod-instruction_handler\r
+       db      'fshtos~~',0x00\r
+       dw      ARM_instruction_fshtos-instruction_handler\r
+       db      'fsitod~~',0x00\r
+       dw      ARM_instruction_fsitod-instruction_handler\r
+       db      'fsitos~~',0x00\r
+       dw      ARM_instruction_fsitos-instruction_handler\r
+       db      'fsltod~~',0x00\r
+       dw      ARM_instruction_fsltod-instruction_handler\r
+       db      'fsltos~~',0x00\r
+       dw      ARM_instruction_fsltos-instruction_handler\r
+       db      'fsqrtd~~',0x00\r
+       dw      ARM_instruction_fsqrtd-instruction_handler\r
+       db      'fsqrts~~',0x00\r
+       dw      ARM_instruction_fsqrts-instruction_handler\r
+       db      'ftoshd~~',0x00\r
+       dw      ARM_instruction_ftoshd-instruction_handler\r
+       db      'ftoshs~~',0x00\r
+       dw      ARM_instruction_ftoshs-instruction_handler\r
+       db      'ftosid~~',0x00\r
+       dw      ARM_instruction_ftosid-instruction_handler\r
+       db      'ftosis~~',0x00\r
+       dw      ARM_instruction_ftosis-instruction_handler\r
+       db      'ftosld~~',0x00\r
+       dw      ARM_instruction_ftosld-instruction_handler\r
+       db      'ftosls~~',0x00\r
+       dw      ARM_instruction_ftosls-instruction_handler\r
+       db      'ftouhd~~',0x00\r
+       dw      ARM_instruction_ftouhd-instruction_handler\r
+       db      'ftouhs~~',0x00\r
+       dw      ARM_instruction_ftouhs-instruction_handler\r
+       db      'ftouid~~',0x00\r
+       dw      ARM_instruction_ftouid-instruction_handler\r
+       db      'ftouis~~',0x00\r
+       dw      ARM_instruction_ftouis-instruction_handler\r
+       db      'ftould~~',0x00\r
+       dw      ARM_instruction_ftould-instruction_handler\r
+       db      'ftouls~~',0x00\r
+       dw      ARM_instruction_ftouls-instruction_handler\r
+       db      'fuhtod~~',0x00\r
+       dw      ARM_instruction_fuhtod-instruction_handler\r
+       db      'fuhtos~~',0x00\r
+       dw      ARM_instruction_fuhtos-instruction_handler\r
+       db      'fuitod~~',0x00\r
+       dw      ARM_instruction_fuitod-instruction_handler\r
+       db      'fuitos~~',0x00\r
+       dw      ARM_instruction_fuitos-instruction_handler\r
+       db      'fultod~~',0x00\r
+       dw      ARM_instruction_fultod-instruction_handler\r
+       db      'fultos~~',0x00\r
+       dw      ARM_instruction_fultos-instruction_handler\r
+       db      'itnoauto',0x00\r
+       dw      ARM_itnoauto_directive-instruction_handler\r
+       db      'ldaexb~~',0x00\r
+       dw      ARM_instruction_ldaexb-instruction_handler\r
+       db      'ldaexd~~',0x00\r
+       dw      ARM_instruction_ldaexd-instruction_handler\r
+       db      'ldaexh~~',0x00\r
+       dw      ARM_instruction_ldaexh-instruction_handler\r
+       db      'ldaex~~b',0x00\r
+       dw      ARM_instruction_ldaexb-instruction_handler\r
+       db      'ldaex~~d',0x00\r
+       dw      ARM_instruction_ldaexd-instruction_handler\r
+       db      'ldaex~~h',0x00\r
+       dw      ARM_instruction_ldaexh-instruction_handler\r
+       db      'ldrb~~.n',0x04\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrb~~.w',0x02\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldrexb~~',0x00\r
+       dw      ARM_instruction_ldrexb-instruction_handler\r
+       db      'ldrexd~~',0x00\r
+       dw      ARM_instruction_ldrexd-instruction_handler\r
+       db      'ldrexh~~',0x00\r
+       dw      ARM_instruction_ldrexh-instruction_handler\r
+       db      'ldrh~~.n',0x04\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrh~~.w',0x02\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldrsbt~~',0x00\r
+       dw      ARM_instruction_ldrsbt-instruction_handler\r
+       db      'ldrsht~~',0x00\r
+       dw      ARM_instruction_ldrsht-instruction_handler\r
+       db      'ldr~~b.n',0x04\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldr~~b.w',0x02\r
+       dw      ARM_instruction_ldrb-instruction_handler\r
+       db      'ldr~~h.n',0x04\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldr~~h.w',0x02\r
+       dw      ARM_instruction_ldrh-instruction_handler\r
+       db      'ldr~~sbt',0x00\r
+       dw      ARM_instruction_ldrsbt-instruction_handler\r
+       db      'ldr~~sht',0x00\r
+       dw      ARM_instruction_ldrsht-instruction_handler\r
+       db      'lsls~~.n',0x05\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsls~~.w',0x03\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl~~s.n',0x05\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsl~~s.w',0x03\r
+       dw      ARM_instruction_lsl-instruction_handler\r
+       db      'lsrs~~.n',0x05\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsrs~~.w',0x03\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr~~s.n',0x05\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'lsr~~s.w',0x03\r
+       dw      ARM_instruction_lsr-instruction_handler\r
+       db      'movs~~.n',0x05\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'movs~~.w',0x03\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mov~~s.n',0x05\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'mov~~s.w',0x03\r
+       dw      ARM_instruction_mov-instruction_handler\r
+       db      'muls~~.n',0x05\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'muls~~.w',0x03\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul~~s.n',0x05\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mul~~s.w',0x03\r
+       dw      ARM_instruction_mul-instruction_handler\r
+       db      'mvns~~.n',0x05\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvns~~.w',0x03\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn~~s.n',0x05\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'mvn~~s.w',0x03\r
+       dw      ARM_instruction_mvn-instruction_handler\r
+       db      'negs~~.n',0x05\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'negs~~.w',0x03\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg~~s.n',0x05\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'neg~~s.w',0x03\r
+       dw      ARM_instruction_neg-instruction_handler\r
+       db      'orrs~~.n',0x05\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orrs~~.w',0x03\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr~~s.n',0x05\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'orr~~s.w',0x03\r
+       dw      ARM_instruction_orr-instruction_handler\r
+       db      'push~~.n',0x04\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'push~~.w',0x02\r
+       dw      ARM_instruction_push-instruction_handler\r
+       db      'qadd16~~',0x00\r
+       dw      ARM_instruction_qadd16-instruction_handler\r
+       db      'qaddsubx',0xe0\r
+       dw      ARM_instruction_qaddsubx-instruction_handler\r
+       db      'qsub16~~',0x00\r
+       dw      ARM_instruction_qsub16-instruction_handler\r
+       db      'qsubaddx',0xe0\r
+       dw      ARM_instruction_qsubaddx-instruction_handler\r
+       db      'rors~~.n',0x05\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rors~~.w',0x03\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror~~s.n',0x05\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'ror~~s.w',0x03\r
+       dw      ARM_instruction_ror-instruction_handler\r
+       db      'rsbs~~.n',0x05\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsbs~~.w',0x03\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb~~s.n',0x05\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'rsb~~s.w',0x03\r
+       dw      ARM_instruction_rsb-instruction_handler\r
+       db      'sadd16~~',0x00\r
+       dw      ARM_instruction_sadd16-instruction_handler\r
+       db      'saddsubx',0xe0\r
+       dw      ARM_instruction_saddsubx-instruction_handler\r
+       db      'sbcs~~.n',0x05\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbcs~~.w',0x03\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc~~s.n',0x05\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sbc~~s.w',0x03\r
+       dw      ARM_instruction_sbc-instruction_handler\r
+       db      'sevl~~.n',0x04\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'sevl~~.w',0x02\r
+       dw      ARM_instruction_sevl-instruction_handler\r
+       db      'sha1c.32',0xf0\r
+       dw      ARM_instruction_sha1c.32-instruction_handler\r
+       db      'sha1h.32',0xf0\r
+       dw      ARM_instruction_sha1h.32-instruction_handler\r
+       db      'sha1m.32',0xf0\r
+       dw      ARM_instruction_sha1m.32-instruction_handler\r
+       db      'sha1p.32',0xf0\r
+       dw      ARM_instruction_sha1p.32-instruction_handler\r
+       db      'sha256h2',0xf0\r
+       dw      ARM_instruction_sha256h2-instruction_handler\r
+       db      'shadd8~~',0x00\r
+       dw      ARM_instruction_shadd8-instruction_handler\r
+       db      'shsub8~~',0x00\r
+       dw      ARM_instruction_shsub8-instruction_handler\r
+       db      'smlabb~~',0x00\r
+       dw      ARM_instruction_smlabb-instruction_handler\r
+       db      'smlabt~~',0x00\r
+       dw      ARM_instruction_smlabt-instruction_handler\r
+       db      'smladx~~',0x00\r
+       dw      ARM_instruction_smladx-instruction_handler\r
+       db      'smlald~~',0x00\r
+       dw      ARM_instruction_smlald-instruction_handler\r
+       db      'smlals~~',0x01\r
+       dw      ARM_instruction_smlal-instruction_handler\r
+       db      'smlal~~s',0x01\r
+       dw      ARM_instruction_smlal-instruction_handler\r
+       db      'smlatb~~',0x00\r
+       dw      ARM_instruction_smlatb-instruction_handler\r
+       db      'smlatt~~',0x00\r
+       dw      ARM_instruction_smlatt-instruction_handler\r
+       db      'smlawb~~',0x00\r
+       dw      ARM_instruction_smlawb-instruction_handler\r
+       db      'smlawt~~',0x00\r
+       dw      ARM_instruction_smlawt-instruction_handler\r
+       db      'smlsdx~~',0x00\r
+       dw      ARM_instruction_smlsdx-instruction_handler\r
+       db      'smlsld~~',0x00\r
+       dw      ARM_instruction_smlsld-instruction_handler\r
+       db      'smmlar~~',0x00\r
+       dw      ARM_instruction_smmlar-instruction_handler\r
+       db      'smmlsr~~',0x00\r
+       dw      ARM_instruction_smmlsr-instruction_handler\r
+       db      'smmulr~~',0x00\r
+       dw      ARM_instruction_smmulr-instruction_handler\r
+       db      'smuadx~~',0x00\r
+       dw      ARM_instruction_smuadx-instruction_handler\r
+       db      'smulbb~~',0x00\r
+       dw      ARM_instruction_smulbb-instruction_handler\r
+       db      'smulbt~~',0x00\r
+       dw      ARM_instruction_smulbt-instruction_handler\r
+       db      'smulls~~',0x01\r
+       dw      ARM_instruction_smull-instruction_handler\r
+       db      'smull~~s',0x01\r
+       dw      ARM_instruction_smull-instruction_handler\r
+       db      'smultb~~',0x00\r
+       dw      ARM_instruction_smultb-instruction_handler\r
+       db      'smultt~~',0x00\r
+       dw      ARM_instruction_smultt-instruction_handler\r
+       db      'smulwb~~',0x00\r
+       dw      ARM_instruction_smulwb-instruction_handler\r
+       db      'smulwt~~',0x00\r
+       dw      ARM_instruction_smulwt-instruction_handler\r
+       db      'smusdx~~',0x00\r
+       dw      ARM_instruction_smusdx-instruction_handler\r
+       db      'sqdmlal2',0xf0\r
+       dw      ARM_instruction_sqdmlal2-instruction_handler\r
+       db      'sqdmlsl2',0xf0\r
+       dw      ARM_instruction_sqdmlsl2-instruction_handler\r
+       db      'sqdmull2',0xf0\r
+       dw      ARM_instruction_sqdmull2-instruction_handler\r
+       db      'sqrdmulh',0xf0\r
+       dw      ARM_instruction_sqrdmulh-instruction_handler\r
+       db      'sqrshrn2',0xf0\r
+       dw      ARM_instruction_sqrshrn2-instruction_handler\r
+       db      'sqrshrun',0xf0\r
+       dw      ARM_instruction_sqrshrun-instruction_handler\r
+       db      'sqshrun2',0xf0\r
+       dw      ARM_instruction_sqshrun2-instruction_handler\r
+       db      'ssat16~~',0x00\r
+       dw      ARM_instruction_ssat16-instruction_handler\r
+       db      'ssub16~~',0x00\r
+       dw      ARM_instruction_ssub16-instruction_handler\r
+       db      'ssubaddx',0xe0\r
+       dw      ARM_instruction_ssubaddx-instruction_handler\r
+       db      'stlexb~~',0x00\r
+       dw      ARM_instruction_stlexb-instruction_handler\r
+       db      'stlexd~~',0x00\r
+       dw      ARM_instruction_stlexd-instruction_handler\r
+       db      'stlexh~~',0x00\r
+       dw      ARM_instruction_stlexh-instruction_handler\r
+       db      'stlex~~b',0x00\r
+       dw      ARM_instruction_stlexb-instruction_handler\r
+       db      'stlex~~d',0x00\r
+       dw      ARM_instruction_stlexd-instruction_handler\r
+       db      'stlex~~h',0x00\r
+       dw      ARM_instruction_stlexh-instruction_handler\r
+       db      'strb~~.n',0x04\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strb~~.w',0x02\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'strexb~~',0x00\r
+       dw      ARM_instruction_strexb-instruction_handler\r
+       db      'strexd~~',0x00\r
+       dw      ARM_instruction_strexd-instruction_handler\r
+       db      'strexh~~',0x00\r
+       dw      ARM_instruction_strexh-instruction_handler\r
+       db      'strh~~.n',0x04\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'strh~~.w',0x02\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'str~~b.n',0x04\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'str~~b.w',0x02\r
+       dw      ARM_instruction_strb-instruction_handler\r
+       db      'str~~h.n',0x04\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'str~~h.w',0x02\r
+       dw      ARM_instruction_strh-instruction_handler\r
+       db      'subs~~.n',0x05\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'subs~~.w',0x03\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sub~~s.n',0x05\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sub~~s.w',0x03\r
+       dw      ARM_instruction_sub-instruction_handler\r
+       db      'sxtb16~~',0x00\r
+       dw      ARM_instruction_sxtb16-instruction_handler\r
+       db      'sxtb~~.n',0x04\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxtb~~.w',0x02\r
+       dw      ARM_instruction_sxtb-instruction_handler\r
+       db      'sxth~~.n',0x04\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'sxth~~.w',0x02\r
+       dw      ARM_instruction_sxth-instruction_handler\r
+       db      'tandcb~~',0x00\r
+       dw      ARM_instruction_tandcb-instruction_handler\r
+       db      'tandch~~',0x00\r
+       dw      ARM_instruction_tandch-instruction_handler\r
+       db      'tandcw~~',0x00\r
+       dw      ARM_instruction_tandcw-instruction_handler\r
+       db      'tbcstb~~',0x00\r
+       dw      ARM_instruction_tbcstb-instruction_handler\r
+       db      'tbcsth~~',0x00\r
+       dw      ARM_instruction_tbcsth-instruction_handler\r
+       db      'tbcstw~~',0x00\r
+       dw      ARM_instruction_tbcstw-instruction_handler\r
+       db      'textrmsb',0xe0\r
+       dw      ARM_instruction_textrmsb-instruction_handler\r
+       db      'textrmsh',0xe0\r
+       dw      ARM_instruction_textrmsh-instruction_handler\r
+       db      'textrmsw',0xe0\r
+       dw      ARM_instruction_textrmsw-instruction_handler\r
+       db      'textrmub',0xe0\r
+       dw      ARM_instruction_textrmub-instruction_handler\r
+       db      'textrmuh',0xe0\r
+       dw      ARM_instruction_textrmuh-instruction_handler\r
+       db      'textrmuw',0xe0\r
+       dw      ARM_instruction_textrmuw-instruction_handler\r
+       db      'tinsrb~~',0x00\r
+       dw      ARM_instruction_tinsrb-instruction_handler\r
+       db      'tinsrh~~',0x00\r
+       dw      ARM_instruction_tinsrh-instruction_handler\r
+       db      'tinsrw~~',0x00\r
+       dw      ARM_instruction_tinsrw-instruction_handler\r
+       db      'tmiabb~~',0x00\r
+       dw      ARM_instruction_tmiabb-instruction_handler\r
+       db      'tmiabt~~',0x00\r
+       dw      ARM_instruction_tmiabt-instruction_handler\r
+       db      'tmiaph~~',0x00\r
+       dw      ARM_instruction_tmiaph-instruction_handler\r
+       db      'tmiatb~~',0x00\r
+       dw      ARM_instruction_tmiatb-instruction_handler\r
+       db      'tmiatt~~',0x00\r
+       dw      ARM_instruction_tmiatt-instruction_handler\r
+       db      'tmovmskb',0xe0\r
+       dw      ARM_instruction_tmovmskb-instruction_handler\r
+       db      'tmovmskh',0xe0\r
+       dw      ARM_instruction_tmovmskh-instruction_handler\r
+       db      'tmovmskw',0xe0\r
+       dw      ARM_instruction_tmovmskw-instruction_handler\r
+       db      'uadd16~~',0x00\r
+       dw      ARM_instruction_uadd16-instruction_handler\r
+       db      'uaddsubx',0xe0\r
+       dw      ARM_instruction_uaddsubx-instruction_handler\r
+       db      'uhadd8~~',0x00\r
+       dw      ARM_instruction_uhadd8-instruction_handler\r
+       db      'uhsub8~~',0x00\r
+       dw      ARM_instruction_uhsub8-instruction_handler\r
+       db      'umlals~~',0x01\r
+       dw      ARM_instruction_umlal-instruction_handler\r
+       db      'umlal~~s',0x01\r
+       dw      ARM_instruction_umlal-instruction_handler\r
+       db      'umulls~~',0x01\r
+       dw      ARM_instruction_umull-instruction_handler\r
+       db      'umull~~s',0x01\r
+       dw      ARM_instruction_umull-instruction_handler\r
+       db      'uqadd8~~',0x00\r
+       dw      ARM_instruction_uqadd8-instruction_handler\r
+       db      'uqrshrn2',0xf0\r
+       dw      ARM_instruction_uqrshrn2-instruction_handler\r
+       db      'uqsub8~~',0x00\r
+       dw      ARM_instruction_uqsub8-instruction_handler\r
+       db      'usada8~~',0x00\r
+       dw      ARM_instruction_usada8-instruction_handler\r
+       db      'usat16~~',0x00\r
+       dw      ARM_instruction_usat16-instruction_handler\r
+       db      'usub16~~',0x00\r
+       dw      ARM_instruction_usub16-instruction_handler\r
+       db      'usubaddx',0xe0\r
+       dw      ARM_instruction_usubaddx-instruction_handler\r
+       db      'uxtb16~~',0x00\r
+       dw      ARM_instruction_uxtb16-instruction_handler\r
+       db      'uxtb~~.n',0x04\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxtb~~.w',0x02\r
+       dw      ARM_instruction_uxtb-instruction_handler\r
+       db      'uxth~~.n',0x04\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'uxth~~.w',0x02\r
+       dw      ARM_instruction_uxth-instruction_handler\r
+       db      'vaba.s16',0xe0\r
+       dw      ARM_instruction_vaba.s16-instruction_handler\r
+       db      'vaba.s32',0xe0\r
+       dw      ARM_instruction_vaba.s32-instruction_handler\r
+       db      'vaba.u16',0xe0\r
+       dw      ARM_instruction_vaba.u16-instruction_handler\r
+       db      'vaba.u32',0xe0\r
+       dw      ARM_instruction_vaba.u32-instruction_handler\r
+       db      'vabal.s8',0xe0\r
+       dw      ARM_instruction_vabal.s8-instruction_handler\r
+       db      'vabal.u8',0xe0\r
+       dw      ARM_instruction_vabal.u8-instruction_handler\r
+       db      'vabd.f32',0xe0\r
+       dw      ARM_instruction_vabd.f32-instruction_handler\r
+       db      'vabd.s16',0xe0\r
+       dw      ARM_instruction_vabd.s16-instruction_handler\r
+       db      'vabd.s32',0xe0\r
+       dw      ARM_instruction_vabd.s32-instruction_handler\r
+       db      'vabd.u16',0xe0\r
+       dw      ARM_instruction_vabd.u16-instruction_handler\r
+       db      'vabd.u32',0xe0\r
+       dw      ARM_instruction_vabd.u32-instruction_handler\r
+       db      'vabdl.s8',0xe0\r
+       dw      ARM_instruction_vabdl.s8-instruction_handler\r
+       db      'vabdl.u8',0xe0\r
+       dw      ARM_instruction_vabdl.u8-instruction_handler\r
+       db      'vabs.f32',0xe0\r
+       dw      ARM_instruction_vabs.f32-instruction_handler\r
+       db      'vabs.f64',0xe0\r
+       dw      ARM_instruction_vabs.f64-instruction_handler\r
+       db      'vabs.s16',0xe0\r
+       dw      ARM_instruction_vabs.s16-instruction_handler\r
+       db      'vabs.s32',0xe0\r
+       dw      ARM_instruction_vabs.s32-instruction_handler\r
+       db      'vadd.f32',0xe0\r
+       dw      ARM_instruction_vadd.f32-instruction_handler\r
+       db      'vadd.f64',0xe0\r
+       dw      ARM_instruction_vadd.f64-instruction_handler\r
+       db      'vadd.i16',0xe0\r
+       dw      ARM_instruction_vadd.i16-instruction_handler\r
+       db      'vadd.i32',0xe0\r
+       dw      ARM_instruction_vadd.i32-instruction_handler\r
+       db      'vadd.i64',0xe0\r
+       dw      ARM_instruction_vadd.i64-instruction_handler\r
+       db      'vaddl.s8',0xe0\r
+       dw      ARM_instruction_vaddl.s8-instruction_handler\r
+       db      'vaddl.u8',0xe0\r
+       dw      ARM_instruction_vaddl.u8-instruction_handler\r
+       db      'vaddw.s8',0xe0\r
+       dw      ARM_instruction_vaddw.s8-instruction_handler\r
+       db      'vaddw.u8',0xe0\r
+       dw      ARM_instruction_vaddw.u8-instruction_handler\r
+       db      'vand.i16',0xe0\r
+       dw      ARM_instruction_vand.i16-instruction_handler\r
+       db      'vand.i32',0xe0\r
+       dw      ARM_instruction_vand.i32-instruction_handler\r
+       db      'vbic.i16',0xe0\r
+       dw      ARM_instruction_vbic.i16-instruction_handler\r
+       db      'vbic.i32',0xe0\r
+       dw      ARM_instruction_vbic.i32-instruction_handler\r
+       db      'vceq.f32',0xe0\r
+       dw      ARM_instruction_vceq.f32-instruction_handler\r
+       db      'vceq.i16',0xe0\r
+       dw      ARM_instruction_vceq.i16-instruction_handler\r
+       db      'vceq.i32',0xe0\r
+       dw      ARM_instruction_vceq.i32-instruction_handler\r
+       db      'vcge.f32',0xe0\r
+       dw      ARM_instruction_vcge.f32-instruction_handler\r
+       db      'vcge.s16',0xe0\r
+       dw      ARM_instruction_vcge.s16-instruction_handler\r
+       db      'vcge.s32',0xe0\r
+       dw      ARM_instruction_vcge.s32-instruction_handler\r
+       db      'vcge.u16',0xe0\r
+       dw      ARM_instruction_vcge.u16-instruction_handler\r
+       db      'vcge.u32',0xe0\r
+       dw      ARM_instruction_vcge.u32-instruction_handler\r
+       db      'vcgt.f32',0xe0\r
+       dw      ARM_instruction_vcgt.f32-instruction_handler\r
+       db      'vcgt.s16',0xe0\r
+       dw      ARM_instruction_vcgt.s16-instruction_handler\r
+       db      'vcgt.s32',0xe0\r
+       dw      ARM_instruction_vcgt.s32-instruction_handler\r
+       db      'vcgt.u16',0xe0\r
+       dw      ARM_instruction_vcgt.u16-instruction_handler\r
+       db      'vcgt.u32',0xe0\r
+       dw      ARM_instruction_vcgt.u32-instruction_handler\r
+       db      'vcle.f32',0xe0\r
+       dw      ARM_instruction_vcle.f32-instruction_handler\r
+       db      'vcle.s16',0xe0\r
+       dw      ARM_instruction_vcle.s16-instruction_handler\r
+       db      'vcle.s32',0xe0\r
+       dw      ARM_instruction_vcle.s32-instruction_handler\r
+       db      'vcle.u16',0xe0\r
+       dw      ARM_instruction_vcle.u16-instruction_handler\r
+       db      'vcle.u32',0xe0\r
+       dw      ARM_instruction_vcle.u32-instruction_handler\r
+       db      'vcls.s16',0xe0\r
+       dw      ARM_instruction_vcls.s16-instruction_handler\r
+       db      'vcls.s32',0xe0\r
+       dw      ARM_instruction_vcls.s32-instruction_handler\r
+       db      'vclt.f32',0xe0\r
+       dw      ARM_instruction_vclt.f32-instruction_handler\r
+       db      'vclt.s16',0xe0\r
+       dw      ARM_instruction_vclt.s16-instruction_handler\r
+       db      'vclt.s32',0xe0\r
+       dw      ARM_instruction_vclt.s32-instruction_handler\r
+       db      'vclt.u16',0xe0\r
+       dw      ARM_instruction_vclt.u16-instruction_handler\r
+       db      'vclt.u32',0xe0\r
+       dw      ARM_instruction_vclt.u32-instruction_handler\r
+       db      'vclz.i16',0xe0\r
+       dw      ARM_instruction_vclz.i16-instruction_handler\r
+       db      'vclz.i32',0xe0\r
+       dw      ARM_instruction_vclz.i32-instruction_handler\r
+       db      'vcmp.f32',0xe0\r
+       dw      ARM_instruction_vcmp.f32-instruction_handler\r
+       db      'vcmp.f64',0xe0\r
+       dw      ARM_instruction_vcmp.f64-instruction_handler\r
+       db      'vcnt~~.8',0x00\r
+       dw      ARM_instruction_vcnt.8-instruction_handler\r
+       db      'vdiv.f32',0xe0\r
+       dw      ARM_instruction_vdiv.f32-instruction_handler\r
+       db      'vdiv.f64',0xe0\r
+       dw      ARM_instruction_vdiv.f64-instruction_handler\r
+       db      'vdup~~.8',0x00\r
+       dw      ARM_instruction_vdup.8-instruction_handler\r
+       db      'vext~~.8',0x00\r
+       dw      ARM_instruction_vext.8-instruction_handler\r
+       db      'vfma.f32',0xe0\r
+       dw      ARM_instruction_vfma.f32-instruction_handler\r
+       db      'vfma.f64',0xe0\r
+       dw      ARM_instruction_vfma.f64-instruction_handler\r
+       db      'vfms.f32',0xe0\r
+       dw      ARM_instruction_vfms.f32-instruction_handler\r
+       db      'vfms.f64',0xe0\r
+       dw      ARM_instruction_vfms.f64-instruction_handler\r
+       db      'vhadd.s8',0xe0\r
+       dw      ARM_instruction_vhadd.s8-instruction_handler\r
+       db      'vhadd.u8',0xe0\r
+       dw      ARM_instruction_vhadd.u8-instruction_handler\r
+       db      'vhsub.s8',0xe0\r
+       dw      ARM_instruction_vhsub.s8-instruction_handler\r
+       db      'vhsub.u8',0xe0\r
+       dw      ARM_instruction_vhsub.u8-instruction_handler\r
+       db      'vld1~~.8',0x00\r
+       dw      ARM_instruction_vld1.8-instruction_handler\r
+       db      'vld2~~.8',0x00\r
+       dw      ARM_instruction_vld2.8-instruction_handler\r
+       db      'vld3~~.8',0x00\r
+       dw      ARM_instruction_vld3.8-instruction_handler\r
+       db      'vld4~~.8',0x00\r
+       dw      ARM_instruction_vld4.8-instruction_handler\r
+       db      'vldmdb~~',0x00\r
+       dw      ARM_instruction_vldmdb-instruction_handler\r
+       db      'vldmea~~',0x00\r
+       dw      ARM_instruction_vldmea-instruction_handler\r
+       db      'vldmfd~~',0x00\r
+       dw      ARM_instruction_vldmfd-instruction_handler\r
+       db      'vldmia~~',0x00\r
+       dw      ARM_instruction_vldmia-instruction_handler\r
+       db      'vmax.f32',0xe0\r
+       dw      ARM_instruction_vmax.f32-instruction_handler\r
+       db      'vmax.s16',0xe0\r
+       dw      ARM_instruction_vmax.s16-instruction_handler\r
+       db      'vmax.s32',0xe0\r
+       dw      ARM_instruction_vmax.s32-instruction_handler\r
+       db      'vmax.u16',0xe0\r
+       dw      ARM_instruction_vmax.u16-instruction_handler\r
+       db      'vmax.u32',0xe0\r
+       dw      ARM_instruction_vmax.u32-instruction_handler\r
+       db      'vmin.f32',0xe0\r
+       dw      ARM_instruction_vmin.f32-instruction_handler\r
+       db      'vmin.s16',0xe0\r
+       dw      ARM_instruction_vmin.s16-instruction_handler\r
+       db      'vmin.s32',0xe0\r
+       dw      ARM_instruction_vmin.s32-instruction_handler\r
+       db      'vmin.u16',0xe0\r
+       dw      ARM_instruction_vmin.u16-instruction_handler\r
+       db      'vmin.u32',0xe0\r
+       dw      ARM_instruction_vmin.u32-instruction_handler\r
+       db      'vmla.f32',0xe0\r
+       dw      ARM_instruction_vmla.f32-instruction_handler\r
+       db      'vmla.f64',0xe0\r
+       dw      ARM_instruction_vmla.f64-instruction_handler\r
+       db      'vmla.i16',0xe0\r
+       dw      ARM_instruction_vmla.i16-instruction_handler\r
+       db      'vmla.i32',0xe0\r
+       dw      ARM_instruction_vmla.i32-instruction_handler\r
+       db      'vmla.s16',0xe0\r
+       dw      ARM_instruction_vmla.s16-instruction_handler\r
+       db      'vmla.s32',0xe0\r
+       dw      ARM_instruction_vmla.s32-instruction_handler\r
+       db      'vmla.u16',0xe0\r
+       dw      ARM_instruction_vmla.u16-instruction_handler\r
+       db      'vmla.u32',0xe0\r
+       dw      ARM_instruction_vmla.u32-instruction_handler\r
+       db      'vmlal.s8',0xe0\r
+       dw      ARM_instruction_vmlal.s8-instruction_handler\r
+       db      'vmlal.u8',0xe0\r
+       dw      ARM_instruction_vmlal.u8-instruction_handler\r
+       db      'vmls.f32',0xe0\r
+       dw      ARM_instruction_vmls.f32-instruction_handler\r
+       db      'vmls.f64',0xe0\r
+       dw      ARM_instruction_vmls.f64-instruction_handler\r
+       db      'vmls.i16',0xe0\r
+       dw      ARM_instruction_vmls.i16-instruction_handler\r
+       db      'vmls.i32',0xe0\r
+       dw      ARM_instruction_vmls.i32-instruction_handler\r
+       db      'vmls.s16',0xe0\r
+       dw      ARM_instruction_vmls.s16-instruction_handler\r
+       db      'vmls.s32',0xe0\r
+       dw      ARM_instruction_vmls.s32-instruction_handler\r
+       db      'vmls.u16',0xe0\r
+       dw      ARM_instruction_vmls.u16-instruction_handler\r
+       db      'vmls.u32',0xe0\r
+       dw      ARM_instruction_vmls.u32-instruction_handler\r
+       db      'vmlsl.s8',0xe0\r
+       dw      ARM_instruction_vmlsl.s8-instruction_handler\r
+       db      'vmlsl.u8',0xe0\r
+       dw      ARM_instruction_vmlsl.u8-instruction_handler\r
+       db      'vmov.f32',0xe0\r
+       dw      ARM_instruction_vmov.f32-instruction_handler\r
+       db      'vmov.f64',0xe0\r
+       dw      ARM_instruction_vmov.f64-instruction_handler\r
+       db      'vmov.i16',0xe0\r
+       dw      ARM_instruction_vmov.i16-instruction_handler\r
+       db      'vmov.i32',0xe0\r
+       dw      ARM_instruction_vmov.i32-instruction_handler\r
+       db      'vmov.i64',0xe0\r
+       dw      ARM_instruction_vmov.i64-instruction_handler\r
+       db      'vmov.s16',0xe0\r
+       dw      ARM_instruction_vmov.s16-instruction_handler\r
+       db      'vmov.u16',0xe0\r
+       dw      ARM_instruction_vmov.u16-instruction_handler\r
+       db      'vmovl.s8',0xe0\r
+       dw      ARM_instruction_vmovl.s8-instruction_handler\r
+       db      'vmovl.u8',0xe0\r
+       dw      ARM_instruction_vmovl.u8-instruction_handler\r
+       db      'vmovn.i8',0xe0\r
+       dw      ARM_instruction_vmovn.i8-instruction_handler\r
+       db      'vmov~~.8',0x00\r
+       dw      ARM_instruction_vmov.8-instruction_handler\r
+       db      'vmul.f32',0xe0\r
+       dw      ARM_instruction_vmul.f32-instruction_handler\r
+       db      'vmul.f64',0xe0\r
+       dw      ARM_instruction_vmul.f64-instruction_handler\r
+       db      'vmul.i16',0xe0\r
+       dw      ARM_instruction_vmul.i16-instruction_handler\r
+       db      'vmul.i32',0xe0\r
+       dw      ARM_instruction_vmul.i32-instruction_handler\r
+       db      'vmul.s16',0xe0\r
+       dw      ARM_instruction_vmul.s16-instruction_handler\r
+       db      'vmul.s32',0xe0\r
+       dw      ARM_instruction_vmul.s32-instruction_handler\r
+       db      'vmul.u16',0xe0\r
+       dw      ARM_instruction_vmul.u16-instruction_handler\r
+       db      'vmul.u32',0xe0\r
+       dw      ARM_instruction_vmul.u32-instruction_handler\r
+       db      'vmull.p8',0xe0\r
+       dw      ARM_instruction_vmull.p8-instruction_handler\r
+       db      'vmull.s8',0xe0\r
+       dw      ARM_instruction_vmull.s8-instruction_handler\r
+       db      'vmull.u8',0xe0\r
+       dw      ARM_instruction_vmull.u8-instruction_handler\r
+       db      'vmvn.i16',0xe0\r
+       dw      ARM_instruction_vmvn.i16-instruction_handler\r
+       db      'vmvn.i32',0xe0\r
+       dw      ARM_instruction_vmvn.i32-instruction_handler\r
+       db      'vneg.f32',0xe0\r
+       dw      ARM_instruction_vneg.f32-instruction_handler\r
+       db      'vneg.f64',0xe0\r
+       dw      ARM_instruction_vneg.f64-instruction_handler\r
+       db      'vneg.s16',0xe0\r
+       dw      ARM_instruction_vneg.s16-instruction_handler\r
+       db      'vneg.s32',0xe0\r
+       dw      ARM_instruction_vneg.s32-instruction_handler\r
+       db      'vorn.i16',0xe0\r
+       dw      ARM_instruction_vorn.i16-instruction_handler\r
+       db      'vorn.i32',0xe0\r
+       dw      ARM_instruction_vorn.i32-instruction_handler\r
+       db      'vorr.i16',0xe0\r
+       dw      ARM_instruction_vorr.i16-instruction_handler\r
+       db      'vorr.i32',0xe0\r
+       dw      ARM_instruction_vorr.i32-instruction_handler\r
+       db      'vpadd.i8',0xe0\r
+       dw      ARM_instruction_vpadd.i8-instruction_handler\r
+       db      'vpmax.s8',0xe0\r
+       dw      ARM_instruction_vpmax.s8-instruction_handler\r
+       db      'vpmax.u8',0xe0\r
+       dw      ARM_instruction_vpmax.u8-instruction_handler\r
+       db      'vpmin.s8',0xe0\r
+       dw      ARM_instruction_vpmin.s8-instruction_handler\r
+       db      'vpmin.u8',0xe0\r
+       dw      ARM_instruction_vpmin.u8-instruction_handler\r
+       db      'vpush.32',0xe0\r
+       dw      ARM_instruction_vpush.32-instruction_handler\r
+       db      'vpush.64',0xe0\r
+       dw      ARM_instruction_vpush.64-instruction_handler\r
+       db      'vqabs.s8',0xe0\r
+       dw      ARM_instruction_vqabs.s8-instruction_handler\r
+       db      'vqadd.s8',0xe0\r
+       dw      ARM_instruction_vqadd.s8-instruction_handler\r
+       db      'vqadd.u8',0xe0\r
+       dw      ARM_instruction_vqadd.u8-instruction_handler\r
+       db      'vqneg.s8',0xe0\r
+       dw      ARM_instruction_vqneg.s8-instruction_handler\r
+       db      'vqshl.s8',0xe0\r
+       dw      ARM_instruction_vqshl.s8-instruction_handler\r
+       db      'vqshl.u8',0xe0\r
+       dw      ARM_instruction_vqshl.u8-instruction_handler\r
+       db      'vqsub.s8',0xe0\r
+       dw      ARM_instruction_vqsub.s8-instruction_handler\r
+       db      'vqsub.u8',0xe0\r
+       dw      ARM_instruction_vqsub.u8-instruction_handler\r
+       db      'vrev16.8',0xe0\r
+       dw      ARM_instruction_vrev16.8-instruction_handler\r
+       db      'vrev32.8',0xe0\r
+       dw      ARM_instruction_vrev32.8-instruction_handler\r
+       db      'vrev64.8',0xe0\r
+       dw      ARM_instruction_vrev64.8-instruction_handler\r
+       db      'vrshl.s8',0xe0\r
+       dw      ARM_instruction_vrshl.s8-instruction_handler\r
+       db      'vrshl.u8',0xe0\r
+       dw      ARM_instruction_vrshl.u8-instruction_handler\r
+       db      'vrshr.s8',0xe0\r
+       dw      ARM_instruction_vrshr.s8-instruction_handler\r
+       db      'vrshr.u8',0xe0\r
+       dw      ARM_instruction_vrshr.u8-instruction_handler\r
+       db      'vrsra.s8',0xe0\r
+       dw      ARM_instruction_vrsra.s8-instruction_handler\r
+       db      'vrsra.u8',0xe0\r
+       dw      ARM_instruction_vrsra.u8-instruction_handler\r
+       db      'vshl.i16',0xe0\r
+       dw      ARM_instruction_vshl.i16-instruction_handler\r
+       db      'vshl.i32',0xe0\r
+       dw      ARM_instruction_vshl.i32-instruction_handler\r
+       db      'vshl.i64',0xe0\r
+       dw      ARM_instruction_vshl.i64-instruction_handler\r
+       db      'vshl.s16',0xe0\r
+       dw      ARM_instruction_vshl.s16-instruction_handler\r
+       db      'vshl.s32',0xe0\r
+       dw      ARM_instruction_vshl.s32-instruction_handler\r
+       db      'vshl.s64',0xe0\r
+       dw      ARM_instruction_vshl.s64-instruction_handler\r
+       db      'vshl.u16',0xe0\r
+       dw      ARM_instruction_vshl.u16-instruction_handler\r
+       db      'vshl.u32',0xe0\r
+       dw      ARM_instruction_vshl.u32-instruction_handler\r
+       db      'vshl.u64',0xe0\r
+       dw      ARM_instruction_vshl.u64-instruction_handler\r
+       db      'vshll.i8',0xe0\r
+       dw      ARM_instruction_vshll.i8-instruction_handler\r
+       db      'vshll.s8',0xe0\r
+       dw      ARM_instruction_vshll.s8-instruction_handler\r
+       db      'vshll.u8',0xe0\r
+       dw      ARM_instruction_vshll.u8-instruction_handler\r
+       db      'vshr.s16',0xe0\r
+       dw      ARM_instruction_vshr.s16-instruction_handler\r
+       db      'vshr.s32',0xe0\r
+       dw      ARM_instruction_vshr.s32-instruction_handler\r
+       db      'vshr.s64',0xe0\r
+       dw      ARM_instruction_vshr.s64-instruction_handler\r
+       db      'vshr.u16',0xe0\r
+       dw      ARM_instruction_vshr.u16-instruction_handler\r
+       db      'vshr.u32',0xe0\r
+       dw      ARM_instruction_vshr.u32-instruction_handler\r
+       db      'vshr.u64',0xe0\r
+       dw      ARM_instruction_vshr.u64-instruction_handler\r
+       db      'vsli~~.8',0x00\r
+       dw      ARM_instruction_vsli.8-instruction_handler\r
+       db      'vsra.s16',0xe0\r
+       dw      ARM_instruction_vsra.s16-instruction_handler\r
+       db      'vsra.s32',0xe0\r
+       dw      ARM_instruction_vsra.s32-instruction_handler\r
+       db      'vsra.s64',0xe0\r
+       dw      ARM_instruction_vsra.s64-instruction_handler\r
+       db      'vsra.u16',0xe0\r
+       dw      ARM_instruction_vsra.u16-instruction_handler\r
+       db      'vsra.u32',0xe0\r
+       dw      ARM_instruction_vsra.u32-instruction_handler\r
+       db      'vsra.u64',0xe0\r
+       dw      ARM_instruction_vsra.u64-instruction_handler\r
+       db      'vsri~~.8',0x00\r
+       dw      ARM_instruction_vsri.8-instruction_handler\r
+       db      'vst1~~.8',0x00\r
+       dw      ARM_instruction_vst1.8-instruction_handler\r
+       db      'vst2~~.8',0x00\r
+       dw      ARM_instruction_vst2.8-instruction_handler\r
+       db      'vst3~~.8',0x00\r
+       dw      ARM_instruction_vst3.8-instruction_handler\r
+       db      'vst4~~.8',0x00\r
+       dw      ARM_instruction_vst4.8-instruction_handler\r
+       db      'vstmdb~~',0x00\r
+       dw      ARM_instruction_vstmdb-instruction_handler\r
+       db      'vstmea~~',0x00\r
+       dw      ARM_instruction_vstmea-instruction_handler\r
+       db      'vstmfd~~',0x00\r
+       dw      ARM_instruction_vstmfd-instruction_handler\r
+       db      'vstmia~~',0x00\r
+       dw      ARM_instruction_vstmia-instruction_handler\r
+       db      'vsub.f32',0xe0\r
+       dw      ARM_instruction_vsub.f32-instruction_handler\r
+       db      'vsub.f64',0xe0\r
+       dw      ARM_instruction_vsub.f64-instruction_handler\r
+       db      'vsub.i16',0xe0\r
+       dw      ARM_instruction_vsub.i16-instruction_handler\r
+       db      'vsub.i32',0xe0\r
+       dw      ARM_instruction_vsub.i32-instruction_handler\r
+       db      'vsub.i64',0xe0\r
+       dw      ARM_instruction_vsub.i64-instruction_handler\r
+       db      'vsubl.s8',0xe0\r
+       dw      ARM_instruction_vsubl.s8-instruction_handler\r
+       db      'vsubl.u8',0xe0\r
+       dw      ARM_instruction_vsubl.u8-instruction_handler\r
+       db      'vsubw.s8',0xe0\r
+       dw      ARM_instruction_vsubw.s8-instruction_handler\r
+       db      'vsubw.u8',0xe0\r
+       dw      ARM_instruction_vsubw.u8-instruction_handler\r
+       db      'vtbl~~.8',0x00\r
+       dw      ARM_instruction_vtbl.8-instruction_handler\r
+       db      'vtbx~~.8',0x00\r
+       dw      ARM_instruction_vtbx.8-instruction_handler\r
+       db      'vtrn~~.8',0x00\r
+       dw      ARM_instruction_vtrn.8-instruction_handler\r
+       db      'vtst~~.8',0x00\r
+       dw      ARM_instruction_vtst.8-instruction_handler\r
+       db      'vuzp~~.8',0x00\r
+       dw      ARM_instruction_vuzp.8-instruction_handler\r
+       db      'vzip~~.8',0x00\r
+       dw      ARM_instruction_vzip.8-instruction_handler\r
+       db      'waddhc~~',0x00\r
+       dw      ARM_instruction_waddhc-instruction_handler\r
+       db      'waddwc~~',0x00\r
+       dw      ARM_instruction_waddwc-instruction_handler\r
+       db      'walignr0',0xe0\r
+       dw      ARM_instruction_walignr0-instruction_handler\r
+       db      'walignr1',0xe0\r
+       dw      ARM_instruction_walignr1-instruction_handler\r
+       db      'walignr2',0xe0\r
+       dw      ARM_instruction_walignr2-instruction_handler\r
+       db      'walignr3',0xe0\r
+       dw      ARM_instruction_walignr3-instruction_handler\r
+       db      'wavg2b~~',0x00\r
+       dw      ARM_instruction_wavg2b-instruction_handler\r
+       db      'wavg2h~~',0x00\r
+       dw      ARM_instruction_wavg2h-instruction_handler\r
+       db      'wavg4r~~',0x00\r
+       dw      ARM_instruction_wavg4r-instruction_handler\r
+       db      'wcmpgtsb',0xe0\r
+       dw      ARM_instruction_wcmpgtsb-instruction_handler\r
+       db      'wcmpgtsh',0xe0\r
+       dw      ARM_instruction_wcmpgtsh-instruction_handler\r
+       db      'wcmpgtsw',0xe0\r
+       dw      ARM_instruction_wcmpgtsw-instruction_handler\r
+       db      'wcmpgtub',0xe0\r
+       dw      ARM_instruction_wcmpgtub-instruction_handler\r
+       db      'wcmpgtuh',0xe0\r
+       dw      ARM_instruction_wcmpgtuh-instruction_handler\r
+       db      'wcmpgtuw',0xe0\r
+       dw      ARM_instruction_wcmpgtuw-instruction_handler\r
+       db      'wmacsz~~',0x00\r
+       dw      ARM_instruction_wmacsz-instruction_handler\r
+       db      'wmacuz~~',0x00\r
+       dw      ARM_instruction_wmacuz-instruction_handler\r
+       db      'wmadds~~',0x00\r
+       dw      ARM_instruction_wmadds-instruction_handler\r
+       db      'wmaddu~~',0x00\r
+       dw      ARM_instruction_wmaddu-instruction_handler\r
+       db      'wmaxsb~~',0x00\r
+       dw      ARM_instruction_wmaxsb-instruction_handler\r
+       db      'wmaxsh~~',0x00\r
+       dw      ARM_instruction_wmaxsh-instruction_handler\r
+       db      'wmaxsw~~',0x00\r
+       dw      ARM_instruction_wmaxsw-instruction_handler\r
+       db      'wmaxub~~',0x00\r
+       dw      ARM_instruction_wmaxub-instruction_handler\r
+       db      'wmaxuh~~',0x00\r
+       dw      ARM_instruction_wmaxuh-instruction_handler\r
+       db      'wmaxuw~~',0x00\r
+       dw      ARM_instruction_wmaxuw-instruction_handler\r
+       db      'wmerge~~',0x00\r
+       dw      ARM_instruction_wmerge-instruction_handler\r
+       db      'wmiabb~~',0x00\r
+       dw      ARM_instruction_wmiabb-instruction_handler\r
+       db      'wmiabt~~',0x00\r
+       dw      ARM_instruction_wmiabt-instruction_handler\r
+       db      'wmiatb~~',0x00\r
+       dw      ARM_instruction_wmiatb-instruction_handler\r
+       db      'wmiatt~~',0x00\r
+       dw      ARM_instruction_wmiatt-instruction_handler\r
+       db      'wmiawbbn',0xe0\r
+       dw      ARM_instruction_wmiawbbn-instruction_handler\r
+       db      'wmiawbtn',0xe0\r
+       dw      ARM_instruction_wmiawbtn-instruction_handler\r
+       db      'wmiawtbn',0xe0\r
+       dw      ARM_instruction_wmiawtbn-instruction_handler\r
+       db      'wmiawttn',0xe0\r
+       dw      ARM_instruction_wmiawttn-instruction_handler\r
+       db      'wminsb~~',0x00\r
+       dw      ARM_instruction_wminsb-instruction_handler\r
+       db      'wminsh~~',0x00\r
+       dw      ARM_instruction_wminsh-instruction_handler\r
+       db      'wminsw~~',0x00\r
+       dw      ARM_instruction_wminsw-instruction_handler\r
+       db      'wminub~~',0x00\r
+       dw      ARM_instruction_wminub-instruction_handler\r
+       db      'wminuh~~',0x00\r
+       dw      ARM_instruction_wminuh-instruction_handler\r
+       db      'wminuw~~',0x00\r
+       dw      ARM_instruction_wminuw-instruction_handler\r
+       db      'wmulsl~~',0x00\r
+       dw      ARM_instruction_wmulsl-instruction_handler\r
+       db      'wmulsm~~',0x00\r
+       dw      ARM_instruction_wmulsm-instruction_handler\r
+       db      'wmulul~~',0x00\r
+       dw      ARM_instruction_wmulul-instruction_handler\r
+       db      'wmulum~~',0x00\r
+       dw      ARM_instruction_wmulum-instruction_handler\r
+       db      'wmulwl~~',0x00\r
+       dw      ARM_instruction_wmulwl-instruction_handler\r
+       db      'wmulwsmr',0xe0\r
+       dw      ARM_instruction_wmulwsmr-instruction_handler\r
+       db      'wmulwumr',0xe0\r
+       dw      ARM_instruction_wmulwumr-instruction_handler\r
+       db      'wpackdss',0xe0\r
+       dw      ARM_instruction_wpackdss-instruction_handler\r
+       db      'wpackdus',0xe0\r
+       dw      ARM_instruction_wpackdus-instruction_handler\r
+       db      'wpackhss',0xe0\r
+       dw      ARM_instruction_wpackhss-instruction_handler\r
+       db      'wpackhus',0xe0\r
+       dw      ARM_instruction_wpackhus-instruction_handler\r
+       db      'wpackwss',0xe0\r
+       dw      ARM_instruction_wpackwss-instruction_handler\r
+       db      'wpackwus',0xe0\r
+       dw      ARM_instruction_wpackwus-instruction_handler\r
+       db      'wqmiabbn',0xe0\r
+       dw      ARM_instruction_wqmiabbn-instruction_handler\r
+       db      'wqmiabtn',0xe0\r
+       dw      ARM_instruction_wqmiabtn-instruction_handler\r
+       db      'wqmiatbn',0xe0\r
+       dw      ARM_instruction_wqmiatbn-instruction_handler\r
+       db      'wqmiattn',0xe0\r
+       dw      ARM_instruction_wqmiattn-instruction_handler\r
+       db      'wqmulm~~',0x00\r
+       dw      ARM_instruction_wqmulm-instruction_handler\r
+       db      'wqmulwmr',0xe0\r
+       dw      ARM_instruction_wqmulwmr-instruction_handler\r
+       db      'wrordg~~',0x00\r
+       dw      ARM_instruction_wrordg-instruction_handler\r
+       db      'wrorhg~~',0x00\r
+       dw      ARM_instruction_wrorhg-instruction_handler\r
+       db      'wrorwg~~',0x00\r
+       dw      ARM_instruction_wrorwg-instruction_handler\r
+       db      'wsadbz~~',0x00\r
+       dw      ARM_instruction_wsadbz-instruction_handler\r
+       db      'wsadhz~~',0x00\r
+       dw      ARM_instruction_wsadhz-instruction_handler\r
+       db      'wshufh~~',0x00\r
+       dw      ARM_instruction_wshufh-instruction_handler\r
+       db      'wslldg~~',0x00\r
+       dw      ARM_instruction_wslldg-instruction_handler\r
+       db      'wsllhg~~',0x00\r
+       dw      ARM_instruction_wsllhg-instruction_handler\r
+       db      'wsllwg~~',0x00\r
+       dw      ARM_instruction_wsllwg-instruction_handler\r
+       db      'wsradg~~',0x00\r
+       dw      ARM_instruction_wsradg-instruction_handler\r
+       db      'wsrahg~~',0x00\r
+       dw      ARM_instruction_wsrahg-instruction_handler\r
+       db      'wsrawg~~',0x00\r
+       dw      ARM_instruction_wsrawg-instruction_handler\r
+       db      'wsrldg~~',0x00\r
+       dw      ARM_instruction_wsrldg-instruction_handler\r
+       db      'wsrlhg~~',0x00\r
+       dw      ARM_instruction_wsrlhg-instruction_handler\r
+       db      'wsrlwg~~',0x00\r
+       dw      ARM_instruction_wsrlwg-instruction_handler\r
+       db      0\r
+instructions_9:\r
+       db      'cfabs32~~',0x00\r
+       dw      ARM_instruction_cfabs32-instruction_handler\r
+       db      'cfabs64~~',0x00\r
+       dw      ARM_instruction_cfabs64-instruction_handler\r
+       db      'cfadd32~~',0x00\r
+       dw      ARM_instruction_cfadd32-instruction_handler\r
+       db      'cfadd64~~',0x00\r
+       dw      ARM_instruction_cfadd64-instruction_handler\r
+       db      'cfcmp32~~',0x00\r
+       dw      ARM_instruction_cfcmp32-instruction_handler\r
+       db      'cfcmp64~~',0x00\r
+       dw      ARM_instruction_cfcmp64-instruction_handler\r
+       db      'cfcvtds~~',0x00\r
+       dw      ARM_instruction_cfcvtds-instruction_handler\r
+       db      'cfcvtsd~~',0x00\r
+       dw      ARM_instruction_cfcvtsd-instruction_handler\r
+       db      'cfldr32~~',0x00\r
+       dw      ARM_instruction_cfldr32-instruction_handler\r
+       db      'cfldr64~~',0x00\r
+       dw      ARM_instruction_cfldr64-instruction_handler\r
+       db      'cfmac32~~',0x00\r
+       dw      ARM_instruction_cfmac32-instruction_handler\r
+       db      'cfmadda32',0xe0\r
+       dw      ARM_instruction_cfmadda32-instruction_handler\r
+       db      'cfmsc32~~',0x00\r
+       dw      ARM_instruction_cfmsc32-instruction_handler\r
+       db      'cfmsuba32',0xe0\r
+       dw      ARM_instruction_cfmsuba32-instruction_handler\r
+       db      'cfmul32~~',0x00\r
+       dw      ARM_instruction_cfmul32-instruction_handler\r
+       db      'cfmul64~~',0x00\r
+       dw      ARM_instruction_cfmul64-instruction_handler\r
+       db      'cfmv32a~~',0x00\r
+       dw      ARM_instruction_cfmv32a-instruction_handler\r
+       db      'cfmv64a~~',0x00\r
+       dw      ARM_instruction_cfmv64a-instruction_handler\r
+       db      'cfmva32~~',0x00\r
+       dw      ARM_instruction_cfmva32-instruction_handler\r
+       db      'cfmva64~~',0x00\r
+       dw      ARM_instruction_cfmva64-instruction_handler\r
+       db      'cfmvdhr~~',0x00\r
+       dw      ARM_instruction_cfmvdhr-instruction_handler\r
+       db      'cfmvdlr~~',0x00\r
+       dw      ARM_instruction_cfmvdlr-instruction_handler\r
+       db      'cfmvrdh~~',0x00\r
+       dw      ARM_instruction_cfmvrdh-instruction_handler\r
+       db      'cfmvrdl~~',0x00\r
+       dw      ARM_instruction_cfmvrdl-instruction_handler\r
+       db      'cfneg32~~',0x00\r
+       dw      ARM_instruction_cfneg32-instruction_handler\r
+       db      'cfneg64~~',0x00\r
+       dw      ARM_instruction_cfneg64-instruction_handler\r
+       db      'cfstr32~~',0x00\r
+       dw      ARM_instruction_cfstr32-instruction_handler\r
+       db      'cfstr64~~',0x00\r
+       dw      ARM_instruction_cfstr64-instruction_handler\r
+       db      'cfsub32~~',0x00\r
+       dw      ARM_instruction_cfsub32-instruction_handler\r
+       db      'cfsub64~~',0x00\r
+       dw      ARM_instruction_cfsub64-instruction_handler\r
+       db      'fcmpezd~~',0x00\r
+       dw      ARM_instruction_fcmpezd-instruction_handler\r
+       db      'fcmpezs~~',0x00\r
+       dw      ARM_instruction_fcmpezs-instruction_handler\r
+       db      'fconstd~~',0x00\r
+       dw      ARM_instruction_fconstd-instruction_handler\r
+       db      'fconsts~~',0x00\r
+       dw      ARM_instruction_fconsts-instruction_handler\r
+       db      'fldmdbd~~',0x00\r
+       dw      ARM_instruction_fldmdbd-instruction_handler\r
+       db      'fldmdbs~~',0x00\r
+       dw      ARM_instruction_fldmdbs-instruction_handler\r
+       db      'fldmdbx~~',0x00\r
+       dw      ARM_instruction_fldmdbx-instruction_handler\r
+       db      'fldmead~~',0x00\r
+       dw      ARM_instruction_fldmead-instruction_handler\r
+       db      'fldmeas~~',0x00\r
+       dw      ARM_instruction_fldmeas-instruction_handler\r
+       db      'fldmeax~~',0x00\r
+       dw      ARM_instruction_fldmeax-instruction_handler\r
+       db      'fldmfdd~~',0x00\r
+       dw      ARM_instruction_fldmfdd-instruction_handler\r
+       db      'fldmfds~~',0x00\r
+       dw      ARM_instruction_fldmfds-instruction_handler\r
+       db      'fldmfdx~~',0x00\r
+       dw      ARM_instruction_fldmfdx-instruction_handler\r
+       db      'fldmiad~~',0x00\r
+       dw      ARM_instruction_fldmiad-instruction_handler\r
+       db      'fldmias~~',0x00\r
+       dw      ARM_instruction_fldmias-instruction_handler\r
+       db      'fldmiax~~',0x00\r
+       dw      ARM_instruction_fldmiax-instruction_handler\r
+       db      'fstmdbd~~',0x00\r
+       dw      ARM_instruction_fstmdbd-instruction_handler\r
+       db      'fstmdbs~~',0x00\r
+       dw      ARM_instruction_fstmdbs-instruction_handler\r
+       db      'fstmdbx~~',0x00\r
+       dw      ARM_instruction_fstmdbx-instruction_handler\r
+       db      'fstmead~~',0x00\r
+       dw      ARM_instruction_fstmead-instruction_handler\r
+       db      'fstmeas~~',0x00\r
+       dw      ARM_instruction_fstmeas-instruction_handler\r
+       db      'fstmeax~~',0x00\r
+       dw      ARM_instruction_fstmeax-instruction_handler\r
+       db      'fstmfdd~~',0x00\r
+       dw      ARM_instruction_fstmfdd-instruction_handler\r
+       db      'fstmfds~~',0x00\r
+       dw      ARM_instruction_fstmfds-instruction_handler\r
+       db      'fstmfdx~~',0x00\r
+       dw      ARM_instruction_fstmfdx-instruction_handler\r
+       db      'fstmiad~~',0x00\r
+       dw      ARM_instruction_fstmiad-instruction_handler\r
+       db      'fstmias~~',0x00\r
+       dw      ARM_instruction_fstmias-instruction_handler\r
+       db      'fstmiax~~',0x00\r
+       dw      ARM_instruction_fstmiax-instruction_handler\r
+       db      'ftosizd~~',0x00\r
+       dw      ARM_instruction_ftosizd-instruction_handler\r
+       db      'ftosizs~~',0x00\r
+       dw      ARM_instruction_ftosizs-instruction_handler\r
+       db      'ftouizd~~',0x00\r
+       dw      ARM_instruction_ftouizd-instruction_handler\r
+       db      'ftouizs~~',0x00\r
+       dw      ARM_instruction_ftouizs-instruction_handler\r
+       db      'ldmfd~~.n',0x04\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmfd~~.w',0x02\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldmia~~.n',0x04\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldmia~~.w',0x02\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldm~~fd.n',0x04\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldm~~fd.w',0x02\r
+       dw      ARM_instruction_ldmfd-instruction_handler\r
+       db      'ldm~~ia.n',0x04\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldm~~ia.w',0x02\r
+       dw      ARM_instruction_ldmia-instruction_handler\r
+       db      'ldrsb~~.n',0x04\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsb~~.w',0x02\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldrsh~~.n',0x04\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldrsh~~.w',0x02\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldr~~sb.n',0x04\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldr~~sb.w',0x02\r
+       dw      ARM_instruction_ldrsb-instruction_handler\r
+       db      'ldr~~sh.n',0x04\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'ldr~~sh.w',0x02\r
+       dw      ARM_instruction_ldrsh-instruction_handler\r
+       db      'processor',0x00\r
+       dw      ARM_processor_directive-instruction_handler\r
+       db      'rev16~~.n',0x04\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'rev16~~.w',0x02\r
+       dw      ARM_instruction_rev16-instruction_handler\r
+       db      'revsh~~.n',0x04\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'revsh~~.w',0x02\r
+       dw      ARM_instruction_revsh-instruction_handler\r
+       db      'sha256su0',0xf0\r
+       dw      ARM_instruction_sha256su0-instruction_handler\r
+       db      'sha256su1',0xf0\r
+       dw      ARM_instruction_sha256su1-instruction_handler\r
+       db      'shadd16~~',0x00\r
+       dw      ARM_instruction_shadd16-instruction_handler\r
+       db      'shaddsubx',0xe0\r
+       dw      ARM_instruction_shaddsubx-instruction_handler\r
+       db      'shsub16~~',0x00\r
+       dw      ARM_instruction_shsub16-instruction_handler\r
+       db      'shsubaddx',0xe0\r
+       dw      ARM_instruction_shsubaddx-instruction_handler\r
+       db      'smlalbb~~',0x00\r
+       dw      ARM_instruction_smlalbb-instruction_handler\r
+       db      'smlalbt~~',0x00\r
+       dw      ARM_instruction_smlalbt-instruction_handler\r
+       db      'smlaldx~~',0x00\r
+       dw      ARM_instruction_smlaldx-instruction_handler\r
+       db      'smlaltb~~',0x00\r
+       dw      ARM_instruction_smlaltb-instruction_handler\r
+       db      'smlaltt~~',0x00\r
+       dw      ARM_instruction_smlaltt-instruction_handler\r
+       db      'smlsldx~~',0x00\r
+       dw      ARM_instruction_smlsldx-instruction_handler\r
+       db      'sqrshrun2',0xf0\r
+       dw      ARM_instruction_sqrshrun2-instruction_handler\r
+       db      'stmdb~~.n',0x04\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmdb~~.w',0x02\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stmfd~~.n',0x04\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmfd~~.w',0x02\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stmia~~.n',0x04\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stmia~~.w',0x02\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stm~~db.n',0x04\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stm~~db.w',0x02\r
+       dw      ARM_instruction_stmdb-instruction_handler\r
+       db      'stm~~fd.n',0x04\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stm~~fd.w',0x02\r
+       dw      ARM_instruction_stmfd-instruction_handler\r
+       db      'stm~~ia.n',0x04\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'stm~~ia.w',0x02\r
+       dw      ARM_instruction_stmia-instruction_handler\r
+       db      'sxtab16~~',0x00\r
+       dw      ARM_instruction_sxtab16-instruction_handler\r
+       db      'textrcb~~',0x00\r
+       dw      ARM_instruction_textrcb-instruction_handler\r
+       db      'textrch~~',0x00\r
+       dw      ARM_instruction_textrch-instruction_handler\r
+       db      'textrcw~~',0x00\r
+       dw      ARM_instruction_textrcw-instruction_handler\r
+       db      'torvscb~~',0x00\r
+       dw      ARM_instruction_torvscb-instruction_handler\r
+       db      'torvsch~~',0x00\r
+       dw      ARM_instruction_torvsch-instruction_handler\r
+       db      'torvscw~~',0x00\r
+       dw      ARM_instruction_torvscw-instruction_handler\r
+       db      'uhadd16~~',0x00\r
+       dw      ARM_instruction_uhadd16-instruction_handler\r
+       db      'uhaddsubx',0xe0\r
+       dw      ARM_instruction_uhaddsubx-instruction_handler\r
+       db      'uhsub16~~',0x00\r
+       dw      ARM_instruction_uhsub16-instruction_handler\r
+       db      'uhsubaddx',0xe0\r
+       dw      ARM_instruction_uhsubaddx-instruction_handler\r
+       db      'uqadd16~~',0x00\r
+       dw      ARM_instruction_uqadd16-instruction_handler\r
+       db      'uqaddsubx',0xe0\r
+       dw      ARM_instruction_uqaddsubx-instruction_handler\r
+       db      'uqsub16~~',0x00\r
+       dw      ARM_instruction_uqsub16-instruction_handler\r
+       db      'uqsubaddx',0xe0\r
+       dw      ARM_instruction_uqsubaddx-instruction_handler\r
+       db      'uxtab16~~',0x00\r
+       dw      ARM_instruction_uxtab16-instruction_handler\r
+       db      'vabal.s16',0xe0\r
+       dw      ARM_instruction_vabal.s16-instruction_handler\r
+       db      'vabal.s32',0xe0\r
+       dw      ARM_instruction_vabal.s32-instruction_handler\r
+       db      'vabal.u16',0xe0\r
+       dw      ARM_instruction_vabal.u16-instruction_handler\r
+       db      'vabal.u32',0xe0\r
+       dw      ARM_instruction_vabal.u32-instruction_handler\r
+       db      'vaba~~.s8',0x00\r
+       dw      ARM_instruction_vaba.s8-instruction_handler\r
+       db      'vaba~~.u8',0x00\r
+       dw      ARM_instruction_vaba.u8-instruction_handler\r
+       db      'vabdl.s16',0xe0\r
+       dw      ARM_instruction_vabdl.s16-instruction_handler\r
+       db      'vabdl.s32',0xe0\r
+       dw      ARM_instruction_vabdl.s32-instruction_handler\r
+       db      'vabdl.u16',0xe0\r
+       dw      ARM_instruction_vabdl.u16-instruction_handler\r
+       db      'vabdl.u32',0xe0\r
+       dw      ARM_instruction_vabdl.u32-instruction_handler\r
+       db      'vabd~~.s8',0x00\r
+       dw      ARM_instruction_vabd.s8-instruction_handler\r
+       db      'vabd~~.u8',0x00\r
+       dw      ARM_instruction_vabd.u8-instruction_handler\r
+       db      'vabs~~.s8',0x00\r
+       dw      ARM_instruction_vabs.s8-instruction_handler\r
+       db      'vacge.f32',0xe0\r
+       dw      ARM_instruction_vacge.f32-instruction_handler\r
+       db      'vacgt.f32',0xe0\r
+       dw      ARM_instruction_vacgt.f32-instruction_handler\r
+       db      'vacle.f32',0xe0\r
+       dw      ARM_instruction_vacle.f32-instruction_handler\r
+       db      'vaclt.f32',0xe0\r
+       dw      ARM_instruction_vaclt.f32-instruction_handler\r
+       db      'vaddl.s16',0xe0\r
+       dw      ARM_instruction_vaddl.s16-instruction_handler\r
+       db      'vaddl.s32',0xe0\r
+       dw      ARM_instruction_vaddl.s32-instruction_handler\r
+       db      'vaddl.u16',0xe0\r
+       dw      ARM_instruction_vaddl.u16-instruction_handler\r
+       db      'vaddl.u32',0xe0\r
+       dw      ARM_instruction_vaddl.u32-instruction_handler\r
+       db      'vaddw.s16',0xe0\r
+       dw      ARM_instruction_vaddw.s16-instruction_handler\r
+       db      'vaddw.s32',0xe0\r
+       dw      ARM_instruction_vaddw.s32-instruction_handler\r
+       db      'vaddw.u16',0xe0\r
+       dw      ARM_instruction_vaddw.u16-instruction_handler\r
+       db      'vaddw.u32',0xe0\r
+       dw      ARM_instruction_vaddw.u32-instruction_handler\r
+       db      'vadd~~.i8',0x00\r
+       dw      ARM_instruction_vadd.i8-instruction_handler\r
+       db      'vceq~~.i8',0x00\r
+       dw      ARM_instruction_vceq.i8-instruction_handler\r
+       db      'vcge~~.s8',0x00\r
+       dw      ARM_instruction_vcge.s8-instruction_handler\r
+       db      'vcge~~.u8',0x00\r
+       dw      ARM_instruction_vcge.u8-instruction_handler\r
+       db      'vcgt~~.s8',0x00\r
+       dw      ARM_instruction_vcgt.s8-instruction_handler\r
+       db      'vcgt~~.u8',0x00\r
+       dw      ARM_instruction_vcgt.u8-instruction_handler\r
+       db      'vcle~~.s8',0x00\r
+       dw      ARM_instruction_vcle.s8-instruction_handler\r
+       db      'vcle~~.u8',0x00\r
+       dw      ARM_instruction_vcle.u8-instruction_handler\r
+       db      'vcls~~.s8',0x00\r
+       dw      ARM_instruction_vcls.s8-instruction_handler\r
+       db      'vclt~~.s8',0x00\r
+       dw      ARM_instruction_vclt.s8-instruction_handler\r
+       db      'vclt~~.u8',0x00\r
+       dw      ARM_instruction_vclt.u8-instruction_handler\r
+       db      'vclz~~.i8',0x00\r
+       dw      ARM_instruction_vclz.i8-instruction_handler\r
+       db      'vcmpe.f32',0xe0\r
+       dw      ARM_instruction_vcmpe.f32-instruction_handler\r
+       db      'vcmpe.f64',0xe0\r
+       dw      ARM_instruction_vcmpe.f64-instruction_handler\r
+       db      'vdup~~.16',0x00\r
+       dw      ARM_instruction_vdup.16-instruction_handler\r
+       db      'vdup~~.32',0x00\r
+       dw      ARM_instruction_vdup.32-instruction_handler\r
+       db      'vext~~.16',0x00\r
+       dw      ARM_instruction_vext.16-instruction_handler\r
+       db      'vext~~.32',0x00\r
+       dw      ARM_instruction_vext.32-instruction_handler\r
+       db      'vext~~.64',0x00\r
+       dw      ARM_instruction_vext.64-instruction_handler\r
+       db      'vfnma.f32',0xe0\r
+       dw      ARM_instruction_vfnma.f32-instruction_handler\r
+       db      'vfnma.f64',0xe0\r
+       dw      ARM_instruction_vfnma.f64-instruction_handler\r
+       db      'vfnms.f32',0xe0\r
+       dw      ARM_instruction_vfnms.f32-instruction_handler\r
+       db      'vfnms.f64',0xe0\r
+       dw      ARM_instruction_vfnms.f64-instruction_handler\r
+       db      'vhadd.s16',0xe0\r
+       dw      ARM_instruction_vhadd.s16-instruction_handler\r
+       db      'vhadd.s32',0xe0\r
+       dw      ARM_instruction_vhadd.s32-instruction_handler\r
+       db      'vhadd.u16',0xe0\r
+       dw      ARM_instruction_vhadd.u16-instruction_handler\r
+       db      'vhadd.u32',0xe0\r
+       dw      ARM_instruction_vhadd.u32-instruction_handler\r
+       db      'vhsub.s16',0xe0\r
+       dw      ARM_instruction_vhsub.s16-instruction_handler\r
+       db      'vhsub.s32',0xe0\r
+       dw      ARM_instruction_vhsub.s32-instruction_handler\r
+       db      'vhsub.u16',0xe0\r
+       dw      ARM_instruction_vhsub.u16-instruction_handler\r
+       db      'vhsub.u32',0xe0\r
+       dw      ARM_instruction_vhsub.u32-instruction_handler\r
+       db      'vld1~~.16',0x00\r
+       dw      ARM_instruction_vld1.16-instruction_handler\r
+       db      'vld1~~.32',0x00\r
+       dw      ARM_instruction_vld1.32-instruction_handler\r
+       db      'vld1~~.64',0x00\r
+       dw      ARM_instruction_vld1.64-instruction_handler\r
+       db      'vld2~~.16',0x00\r
+       dw      ARM_instruction_vld2.16-instruction_handler\r
+       db      'vld2~~.32',0x00\r
+       dw      ARM_instruction_vld2.32-instruction_handler\r
+       db      'vld3~~.16',0x00\r
+       dw      ARM_instruction_vld3.16-instruction_handler\r
+       db      'vld3~~.32',0x00\r
+       dw      ARM_instruction_vld3.32-instruction_handler\r
+       db      'vld4~~.16',0x00\r
+       dw      ARM_instruction_vld4.16-instruction_handler\r
+       db      'vld4~~.32',0x00\r
+       dw      ARM_instruction_vld4.32-instruction_handler\r
+       db      'vldmdb.32',0xe0\r
+       dw      ARM_instruction_vldmdb.32-instruction_handler\r
+       db      'vldmdb.64',0xe0\r
+       dw      ARM_instruction_vldmdb.64-instruction_handler\r
+       db      'vldmea.32',0xe0\r
+       dw      ARM_instruction_vldmea.32-instruction_handler\r
+       db      'vldmea.64',0xe0\r
+       dw      ARM_instruction_vldmea.64-instruction_handler\r
+       db      'vldmfd.32',0xe0\r
+       dw      ARM_instruction_vldmfd.32-instruction_handler\r
+       db      'vldmfd.64',0xe0\r
+       dw      ARM_instruction_vldmfd.64-instruction_handler\r
+       db      'vldmia.32',0xe0\r
+       dw      ARM_instruction_vldmia.32-instruction_handler\r
+       db      'vldmia.64',0xe0\r
+       dw      ARM_instruction_vldmia.64-instruction_handler\r
+       db      'vldm~~.32',0x00\r
+       dw      ARM_instruction_vldm.32-instruction_handler\r
+       db      'vldm~~.64',0x00\r
+       dw      ARM_instruction_vldm.64-instruction_handler\r
+       db      'vldr~~.32',0x00\r
+       dw      ARM_instruction_vldr.32-instruction_handler\r
+       db      'vldr~~.64',0x00\r
+       dw      ARM_instruction_vldr.64-instruction_handler\r
+       db      'vmax~~.s8',0x00\r
+       dw      ARM_instruction_vmax.s8-instruction_handler\r
+       db      'vmax~~.u8',0x00\r
+       dw      ARM_instruction_vmax.u8-instruction_handler\r
+       db      'vmin~~.s8',0x00\r
+       dw      ARM_instruction_vmin.s8-instruction_handler\r
+       db      'vmin~~.u8',0x00\r
+       dw      ARM_instruction_vmin.u8-instruction_handler\r
+       db      'vmlal.s16',0xe0\r
+       dw      ARM_instruction_vmlal.s16-instruction_handler\r
+       db      'vmlal.s32',0xe0\r
+       dw      ARM_instruction_vmlal.s32-instruction_handler\r
+       db      'vmlal.u16',0xe0\r
+       dw      ARM_instruction_vmlal.u16-instruction_handler\r
+       db      'vmlal.u32',0xe0\r
+       dw      ARM_instruction_vmlal.u32-instruction_handler\r
+       db      'vmla~~.i8',0x00\r
+       dw      ARM_instruction_vmla.i8-instruction_handler\r
+       db      'vmla~~.s8',0x00\r
+       dw      ARM_instruction_vmla.s8-instruction_handler\r
+       db      'vmla~~.u8',0x00\r
+       dw      ARM_instruction_vmla.u8-instruction_handler\r
+       db      'vmlsl.s16',0xe0\r
+       dw      ARM_instruction_vmlsl.s16-instruction_handler\r
+       db      'vmlsl.s32',0xe0\r
+       dw      ARM_instruction_vmlsl.s32-instruction_handler\r
+       db      'vmlsl.u16',0xe0\r
+       dw      ARM_instruction_vmlsl.u16-instruction_handler\r
+       db      'vmlsl.u32',0xe0\r
+       dw      ARM_instruction_vmlsl.u32-instruction_handler\r
+       db      'vmls~~.i8',0x00\r
+       dw      ARM_instruction_vmls.i8-instruction_handler\r
+       db      'vmls~~.s8',0x00\r
+       dw      ARM_instruction_vmls.s8-instruction_handler\r
+       db      'vmls~~.u8',0x00\r
+       dw      ARM_instruction_vmls.u8-instruction_handler\r
+       db      'vmovl.s16',0xe0\r
+       dw      ARM_instruction_vmovl.s16-instruction_handler\r
+       db      'vmovl.s32',0xe0\r
+       dw      ARM_instruction_vmovl.s32-instruction_handler\r
+       db      'vmovl.u16',0xe0\r
+       dw      ARM_instruction_vmovl.u16-instruction_handler\r
+       db      'vmovl.u32',0xe0\r
+       dw      ARM_instruction_vmovl.u32-instruction_handler\r
+       db      'vmovn.i16',0xe0\r
+       dw      ARM_instruction_vmovn.i16-instruction_handler\r
+       db      'vmovn.i32',0xe0\r
+       dw      ARM_instruction_vmovn.i32-instruction_handler\r
+       db      'vmov~~.16',0x00\r
+       dw      ARM_instruction_vmov.16-instruction_handler\r
+       db      'vmov~~.32',0x00\r
+       dw      ARM_instruction_vmov.32-instruction_handler\r
+       db      'vmov~~.i8',0x00\r
+       dw      ARM_instruction_vmov.i8-instruction_handler\r
+       db      'vmov~~.s8',0x00\r
+       dw      ARM_instruction_vmov.s8-instruction_handler\r
+       db      'vmov~~.u8',0x00\r
+       dw      ARM_instruction_vmov.u8-instruction_handler\r
+       db      'vmull.p64',0xf0\r
+       dw      ARM_instruction_vmull.p64-instruction_handler\r
+       db      'vmull.s16',0xe0\r
+       dw      ARM_instruction_vmull.s16-instruction_handler\r
+       db      'vmull.s32',0xe0\r
+       dw      ARM_instruction_vmull.s32-instruction_handler\r
+       db      'vmull.u16',0xe0\r
+       dw      ARM_instruction_vmull.u16-instruction_handler\r
+       db      'vmull.u32',0xe0\r
+       dw      ARM_instruction_vmull.u32-instruction_handler\r
+       db      'vmul~~.i8',0x00\r
+       dw      ARM_instruction_vmul.i8-instruction_handler\r
+       db      'vmul~~.p8',0x00\r
+       dw      ARM_instruction_vmul.p8-instruction_handler\r
+       db      'vmul~~.s8',0x00\r
+       dw      ARM_instruction_vmul.s8-instruction_handler\r
+       db      'vmul~~.u8',0x00\r
+       dw      ARM_instruction_vmul.u8-instruction_handler\r
+       db      'vneg~~.s8',0x00\r
+       dw      ARM_instruction_vneg.s8-instruction_handler\r
+       db      'vnmla.f32',0xe0\r
+       dw      ARM_instruction_vnmla.f32-instruction_handler\r
+       db      'vnmla.f64',0xe0\r
+       dw      ARM_instruction_vnmla.f64-instruction_handler\r
+       db      'vnmls.f32',0xe0\r
+       dw      ARM_instruction_vnmls.f32-instruction_handler\r
+       db      'vnmls.f64',0xe0\r
+       dw      ARM_instruction_vnmls.f64-instruction_handler\r
+       db      'vnmul.f32',0xe0\r
+       dw      ARM_instruction_vnmul.f32-instruction_handler\r
+       db      'vnmul.f64',0xe0\r
+       dw      ARM_instruction_vnmul.f64-instruction_handler\r
+       db      'vpadal.s8',0xe0\r
+       dw      ARM_instruction_vpadal.s8-instruction_handler\r
+       db      'vpadal.u8',0xe0\r
+       dw      ARM_instruction_vpadal.u8-instruction_handler\r
+       db      'vpadd.f32',0xe0\r
+       dw      ARM_instruction_vpadd.f32-instruction_handler\r
+       db      'vpadd.i16',0xe0\r
+       dw      ARM_instruction_vpadd.i16-instruction_handler\r
+       db      'vpadd.i32',0xe0\r
+       dw      ARM_instruction_vpadd.i32-instruction_handler\r
+       db      'vpaddl.s8',0xe0\r
+       dw      ARM_instruction_vpaddl.s8-instruction_handler\r
+       db      'vpaddl.u8',0xe0\r
+       dw      ARM_instruction_vpaddl.u8-instruction_handler\r
+       db      'vpmax.f32',0xe0\r
+       dw      ARM_instruction_vpmax.f32-instruction_handler\r
+       db      'vpmax.s16',0xe0\r
+       dw      ARM_instruction_vpmax.s16-instruction_handler\r
+       db      'vpmax.s32',0xe0\r
+       dw      ARM_instruction_vpmax.s32-instruction_handler\r
+       db      'vpmax.u16',0xe0\r
+       dw      ARM_instruction_vpmax.u16-instruction_handler\r
+       db      'vpmax.u32',0xe0\r
+       dw      ARM_instruction_vpmax.u32-instruction_handler\r
+       db      'vpmin.f32',0xe0\r
+       dw      ARM_instruction_vpmin.f32-instruction_handler\r
+       db      'vpmin.s16',0xe0\r
+       dw      ARM_instruction_vpmin.s16-instruction_handler\r
+       db      'vpmin.s32',0xe0\r
+       dw      ARM_instruction_vpmin.s32-instruction_handler\r
+       db      'vpmin.u16',0xe0\r
+       dw      ARM_instruction_vpmin.u16-instruction_handler\r
+       db      'vpmin.u32',0xe0\r
+       dw      ARM_instruction_vpmin.u32-instruction_handler\r
+       db      'vpop~~.32',0x00\r
+       dw      ARM_instruction_vpop.32-instruction_handler\r
+       db      'vpop~~.64',0x00\r
+       dw      ARM_instruction_vpop.64-instruction_handler\r
+       db      'vqabs.s16',0xe0\r
+       dw      ARM_instruction_vqabs.s16-instruction_handler\r
+       db      'vqabs.s32',0xe0\r
+       dw      ARM_instruction_vqabs.s32-instruction_handler\r
+       db      'vqadd.s16',0xe0\r
+       dw      ARM_instruction_vqadd.s16-instruction_handler\r
+       db      'vqadd.s32',0xe0\r
+       dw      ARM_instruction_vqadd.s32-instruction_handler\r
+       db      'vqadd.s64',0xe0\r
+       dw      ARM_instruction_vqadd.s64-instruction_handler\r
+       db      'vqadd.u16',0xe0\r
+       dw      ARM_instruction_vqadd.u16-instruction_handler\r
+       db      'vqadd.u32',0xe0\r
+       dw      ARM_instruction_vqadd.u32-instruction_handler\r
+       db      'vqadd.u64',0xe0\r
+       dw      ARM_instruction_vqadd.u64-instruction_handler\r
+       db      'vqneg.s16',0xe0\r
+       dw      ARM_instruction_vqneg.s16-instruction_handler\r
+       db      'vqneg.s32',0xe0\r
+       dw      ARM_instruction_vqneg.s32-instruction_handler\r
+       db      'vqrshl.s8',0xe0\r
+       dw      ARM_instruction_vqrshl.s8-instruction_handler\r
+       db      'vqrshl.u8',0xe0\r
+       dw      ARM_instruction_vqrshl.u8-instruction_handler\r
+       db      'vqshl.s16',0xe0\r
+       dw      ARM_instruction_vqshl.s16-instruction_handler\r
+       db      'vqshl.s32',0xe0\r
+       dw      ARM_instruction_vqshl.s32-instruction_handler\r
+       db      'vqshl.s64',0xe0\r
+       dw      ARM_instruction_vqshl.s64-instruction_handler\r
+       db      'vqshl.u16',0xe0\r
+       dw      ARM_instruction_vqshl.u16-instruction_handler\r
+       db      'vqshl.u32',0xe0\r
+       dw      ARM_instruction_vqshl.u32-instruction_handler\r
+       db      'vqshl.u64',0xe0\r
+       dw      ARM_instruction_vqshl.u64-instruction_handler\r
+       db      'vqshlu.s8',0xe0\r
+       dw      ARM_instruction_vqshlu.s8-instruction_handler\r
+       db      'vqsub.s16',0xe0\r
+       dw      ARM_instruction_vqsub.s16-instruction_handler\r
+       db      'vqsub.s32',0xe0\r
+       dw      ARM_instruction_vqsub.s32-instruction_handler\r
+       db      'vqsub.s64',0xe0\r
+       dw      ARM_instruction_vqsub.s64-instruction_handler\r
+       db      'vqsub.u16',0xe0\r
+       dw      ARM_instruction_vqsub.u16-instruction_handler\r
+       db      'vqsub.u32',0xe0\r
+       dw      ARM_instruction_vqsub.u32-instruction_handler\r
+       db      'vqsub.u64',0xe0\r
+       dw      ARM_instruction_vqsub.u64-instruction_handler\r
+       db      'vrev32.16',0xe0\r
+       dw      ARM_instruction_vrev32.16-instruction_handler\r
+       db      'vrev64.16',0xe0\r
+       dw      ARM_instruction_vrev64.16-instruction_handler\r
+       db      'vrev64.32',0xe0\r
+       dw      ARM_instruction_vrev64.32-instruction_handler\r
+       db      'vrhadd.s8',0xe0\r
+       dw      ARM_instruction_vrhadd.s8-instruction_handler\r
+       db      'vrhadd.u8',0xe0\r
+       dw      ARM_instruction_vrhadd.u8-instruction_handler\r
+       db      'vrshl.s16',0xe0\r
+       dw      ARM_instruction_vrshl.s16-instruction_handler\r
+       db      'vrshl.s32',0xe0\r
+       dw      ARM_instruction_vrshl.s32-instruction_handler\r
+       db      'vrshl.s64',0xe0\r
+       dw      ARM_instruction_vrshl.s64-instruction_handler\r
+       db      'vrshl.u16',0xe0\r
+       dw      ARM_instruction_vrshl.u16-instruction_handler\r
+       db      'vrshl.u32',0xe0\r
+       dw      ARM_instruction_vrshl.u32-instruction_handler\r
+       db      'vrshl.u64',0xe0\r
+       dw      ARM_instruction_vrshl.u64-instruction_handler\r
+       db      'vrshr.s16',0xe0\r
+       dw      ARM_instruction_vrshr.s16-instruction_handler\r
+       db      'vrshr.s32',0xe0\r
+       dw      ARM_instruction_vrshr.s32-instruction_handler\r
+       db      'vrshr.s64',0xe0\r
+       dw      ARM_instruction_vrshr.s64-instruction_handler\r
+       db      'vrshr.u16',0xe0\r
+       dw      ARM_instruction_vrshr.u16-instruction_handler\r
+       db      'vrshr.u32',0xe0\r
+       dw      ARM_instruction_vrshr.u32-instruction_handler\r
+       db      'vrshr.u64',0xe0\r
+       dw      ARM_instruction_vrshr.u64-instruction_handler\r
+       db      'vrsra.s16',0xe0\r
+       dw      ARM_instruction_vrsra.s16-instruction_handler\r
+       db      'vrsra.s32',0xe0\r
+       dw      ARM_instruction_vrsra.s32-instruction_handler\r
+       db      'vrsra.s64',0xe0\r
+       dw      ARM_instruction_vrsra.s64-instruction_handler\r
+       db      'vrsra.u16',0xe0\r
+       dw      ARM_instruction_vrsra.u16-instruction_handler\r
+       db      'vrsra.u32',0xe0\r
+       dw      ARM_instruction_vrsra.u32-instruction_handler\r
+       db      'vrsra.u64',0xe0\r
+       dw      ARM_instruction_vrsra.u64-instruction_handler\r
+       db      'vshll.i16',0xe0\r
+       dw      ARM_instruction_vshll.i16-instruction_handler\r
+       db      'vshll.i32',0xe0\r
+       dw      ARM_instruction_vshll.i32-instruction_handler\r
+       db      'vshll.s16',0xe0\r
+       dw      ARM_instruction_vshll.s16-instruction_handler\r
+       db      'vshll.s32',0xe0\r
+       dw      ARM_instruction_vshll.s32-instruction_handler\r
+       db      'vshll.u16',0xe0\r
+       dw      ARM_instruction_vshll.u16-instruction_handler\r
+       db      'vshll.u32',0xe0\r
+       dw      ARM_instruction_vshll.u32-instruction_handler\r
+       db      'vshl~~.i8',0x00\r
+       dw      ARM_instruction_vshl.i8-instruction_handler\r
+       db      'vshl~~.s8',0x00\r
+       dw      ARM_instruction_vshl.s8-instruction_handler\r
+       db      'vshl~~.u8',0x00\r
+       dw      ARM_instruction_vshl.u8-instruction_handler\r
+       db      'vshrn.i16',0xe0\r
+       dw      ARM_instruction_vshrn.i16-instruction_handler\r
+       db      'vshrn.i32',0xe0\r
+       dw      ARM_instruction_vshrn.i32-instruction_handler\r
+       db      'vshrn.i64',0xe0\r
+       dw      ARM_instruction_vshrn.i64-instruction_handler\r
+       db      'vshr~~.s8',0x00\r
+       dw      ARM_instruction_vshr.s8-instruction_handler\r
+       db      'vshr~~.u8',0x00\r
+       dw      ARM_instruction_vshr.u8-instruction_handler\r
+       db      'vsli~~.16',0x00\r
+       dw      ARM_instruction_vsli.16-instruction_handler\r
+       db      'vsli~~.32',0x00\r
+       dw      ARM_instruction_vsli.32-instruction_handler\r
+       db      'vsli~~.64',0x00\r
+       dw      ARM_instruction_vsli.64-instruction_handler\r
+       db      'vsqrt.f32',0xe0\r
+       dw      ARM_instruction_vsqrt.f32-instruction_handler\r
+       db      'vsqrt.f64',0xe0\r
+       dw      ARM_instruction_vsqrt.f64-instruction_handler\r
+       db      'vsra~~.s8',0x00\r
+       dw      ARM_instruction_vsra.s8-instruction_handler\r
+       db      'vsra~~.u8',0x00\r
+       dw      ARM_instruction_vsra.u8-instruction_handler\r
+       db      'vsri~~.16',0x00\r
+       dw      ARM_instruction_vsri.16-instruction_handler\r
+       db      'vsri~~.32',0x00\r
+       dw      ARM_instruction_vsri.32-instruction_handler\r
+       db      'vsri~~.64',0x00\r
+       dw      ARM_instruction_vsri.64-instruction_handler\r
+       db      'vst1~~.16',0x00\r
+       dw      ARM_instruction_vst1.16-instruction_handler\r
+       db      'vst1~~.32',0x00\r
+       dw      ARM_instruction_vst1.32-instruction_handler\r
+       db      'vst1~~.64',0x00\r
+       dw      ARM_instruction_vst1.64-instruction_handler\r
+       db      'vst2~~.16',0x00\r
+       dw      ARM_instruction_vst2.16-instruction_handler\r
+       db      'vst2~~.32',0x00\r
+       dw      ARM_instruction_vst2.32-instruction_handler\r
+       db      'vst3~~.16',0x00\r
+       dw      ARM_instruction_vst3.16-instruction_handler\r
+       db      'vst3~~.32',0x00\r
+       dw      ARM_instruction_vst3.32-instruction_handler\r
+       db      'vst4~~.16',0x00\r
+       dw      ARM_instruction_vst4.16-instruction_handler\r
+       db      'vst4~~.32',0x00\r
+       dw      ARM_instruction_vst4.32-instruction_handler\r
+       db      'vstmdb.32',0xe0\r
+       dw      ARM_instruction_vstmdb.32-instruction_handler\r
+       db      'vstmdb.64',0xe0\r
+       dw      ARM_instruction_vstmdb.64-instruction_handler\r
+       db      'vstmea.32',0xe0\r
+       dw      ARM_instruction_vstmea.32-instruction_handler\r
+       db      'vstmea.64',0xe0\r
+       dw      ARM_instruction_vstmea.64-instruction_handler\r
+       db      'vstmfd.32',0xe0\r
+       dw      ARM_instruction_vstmfd.32-instruction_handler\r
+       db      'vstmfd.64',0xe0\r
+       dw      ARM_instruction_vstmfd.64-instruction_handler\r
+       db      'vstmia.32',0xe0\r
+       dw      ARM_instruction_vstmia.32-instruction_handler\r
+       db      'vstmia.64',0xe0\r
+       dw      ARM_instruction_vstmia.64-instruction_handler\r
+       db      'vstm~~.32',0x00\r
+       dw      ARM_instruction_vstm.32-instruction_handler\r
+       db      'vstm~~.64',0x00\r
+       dw      ARM_instruction_vstm.64-instruction_handler\r
+       db      'vstr~~.32',0x00\r
+       dw      ARM_instruction_vstr.32-instruction_handler\r
+       db      'vstr~~.64',0x00\r
+       dw      ARM_instruction_vstr.64-instruction_handler\r
+       db      'vsubl.s16',0xe0\r
+       dw      ARM_instruction_vsubl.s16-instruction_handler\r
+       db      'vsubl.s32',0xe0\r
+       dw      ARM_instruction_vsubl.s32-instruction_handler\r
+       db      'vsubl.u16',0xe0\r
+       dw      ARM_instruction_vsubl.u16-instruction_handler\r
+       db      'vsubl.u32',0xe0\r
+       dw      ARM_instruction_vsubl.u32-instruction_handler\r
+       db      'vsubw.s16',0xe0\r
+       dw      ARM_instruction_vsubw.s16-instruction_handler\r
+       db      'vsubw.s32',0xe0\r
+       dw      ARM_instruction_vsubw.s32-instruction_handler\r
+       db      'vsubw.u16',0xe0\r
+       dw      ARM_instruction_vsubw.u16-instruction_handler\r
+       db      'vsubw.u32',0xe0\r
+       dw      ARM_instruction_vsubw.u32-instruction_handler\r
+       db      'vsub~~.i8',0x00\r
+       dw      ARM_instruction_vsub.i8-instruction_handler\r
+       db      'vtrn~~.16',0x00\r
+       dw      ARM_instruction_vtrn.16-instruction_handler\r
+       db      'vtrn~~.32',0x00\r
+       dw      ARM_instruction_vtrn.32-instruction_handler\r
+       db      'vtst~~.16',0x00\r
+       dw      ARM_instruction_vtst.16-instruction_handler\r
+       db      'vtst~~.32',0x00\r
+       dw      ARM_instruction_vtst.32-instruction_handler\r
+       db      'vuzp~~.16',0x00\r
+       dw      ARM_instruction_vuzp.16-instruction_handler\r
+       db      'vuzp~~.32',0x00\r
+       dw      ARM_instruction_vuzp.32-instruction_handler\r
+       db      'vzip~~.16',0x00\r
+       dw      ARM_instruction_vzip.16-instruction_handler\r
+       db      'vzip~~.32',0x00\r
+       dw      ARM_instruction_vzip.32-instruction_handler\r
+       db      'wabsdiffb',0xe0\r
+       dw      ARM_instruction_wabsdiffb-instruction_handler\r
+       db      'wabsdiffh',0xe0\r
+       dw      ARM_instruction_wabsdiffh-instruction_handler\r
+       db      'wabsdiffw',0xe0\r
+       dw      ARM_instruction_wabsdiffw-instruction_handler\r
+       db      'waddbss~~',0x00\r
+       dw      ARM_instruction_waddbss-instruction_handler\r
+       db      'waddbus~~',0x00\r
+       dw      ARM_instruction_waddbus-instruction_handler\r
+       db      'waddhss~~',0x00\r
+       dw      ARM_instruction_waddhss-instruction_handler\r
+       db      'waddhus~~',0x00\r
+       dw      ARM_instruction_waddhus-instruction_handler\r
+       db      'waddsubhx',0xe0\r
+       dw      ARM_instruction_waddsubhx-instruction_handler\r
+       db      'waddwss~~',0x00\r
+       dw      ARM_instruction_waddwss-instruction_handler\r
+       db      'waddwus~~',0x00\r
+       dw      ARM_instruction_waddwus-instruction_handler\r
+       db      'waligni~~',0x00\r
+       dw      ARM_instruction_waligni-instruction_handler\r
+       db      'wavg2br~~',0x00\r
+       dw      ARM_instruction_wavg2br-instruction_handler\r
+       db      'wavg2hr~~',0x00\r
+       dw      ARM_instruction_wavg2hr-instruction_handler\r
+       db      'wcmpeqb~~',0x00\r
+       dw      ARM_instruction_wcmpeqb-instruction_handler\r
+       db      'wcmpeqh~~',0x00\r
+       dw      ARM_instruction_wcmpeqh-instruction_handler\r
+       db      'wcmpeqw~~',0x00\r
+       dw      ARM_instruction_wcmpeqw-instruction_handler\r
+       db      'wmaddsn~~',0x00\r
+       dw      ARM_instruction_wmaddsn-instruction_handler\r
+       db      'wmaddsx~~',0x00\r
+       dw      ARM_instruction_wmaddsx-instruction_handler\r
+       db      'wmaddun~~',0x00\r
+       dw      ARM_instruction_wmaddun-instruction_handler\r
+       db      'wmaddux~~',0x00\r
+       dw      ARM_instruction_wmaddux-instruction_handler\r
+       db      'wmiabbn~~',0x00\r
+       dw      ARM_instruction_wmiabbn-instruction_handler\r
+       db      'wmiabtn~~',0x00\r
+       dw      ARM_instruction_wmiabtn-instruction_handler\r
+       db      'wmiatbn~~',0x00\r
+       dw      ARM_instruction_wmiatbn-instruction_handler\r
+       db      'wmiattn~~',0x00\r
+       dw      ARM_instruction_wmiattn-instruction_handler\r
+       db      'wmiawbb~~',0x00\r
+       dw      ARM_instruction_wmiawbb-instruction_handler\r
+       db      'wmiawbt~~',0x00\r
+       dw      ARM_instruction_wmiawbt-instruction_handler\r
+       db      'wmiawtb~~',0x00\r
+       dw      ARM_instruction_wmiawtb-instruction_handler\r
+       db      'wmiawtt~~',0x00\r
+       dw      ARM_instruction_wmiawtt-instruction_handler\r
+       db      'wmulsmr~~',0x00\r
+       dw      ARM_instruction_wmulsmr-instruction_handler\r
+       db      'wmulumr~~',0x00\r
+       dw      ARM_instruction_wmulumr-instruction_handler\r
+       db      'wmulwsm~~',0x00\r
+       dw      ARM_instruction_wmulwsm-instruction_handler\r
+       db      'wmulwum~~',0x00\r
+       dw      ARM_instruction_wmulwum-instruction_handler\r
+       db      'wqmiabb~~',0x00\r
+       dw      ARM_instruction_wqmiabb-instruction_handler\r
+       db      'wqmiabt~~',0x00\r
+       dw      ARM_instruction_wqmiabt-instruction_handler\r
+       db      'wqmiatb~~',0x00\r
+       dw      ARM_instruction_wqmiatb-instruction_handler\r
+       db      'wqmiatt~~',0x00\r
+       dw      ARM_instruction_wqmiatt-instruction_handler\r
+       db      'wqmulmr~~',0x00\r
+       dw      ARM_instruction_wqmulmr-instruction_handler\r
+       db      'wqmulwm~~',0x00\r
+       dw      ARM_instruction_wqmulwm-instruction_handler\r
+       db      'wsubaddhx',0xe0\r
+       dw      ARM_instruction_wsubaddhx-instruction_handler\r
+       db      'wsubbss~~',0x00\r
+       dw      ARM_instruction_wsubbss-instruction_handler\r
+       db      'wsubbus~~',0x00\r
+       dw      ARM_instruction_wsubbus-instruction_handler\r
+       db      'wsubhss~~',0x00\r
+       dw      ARM_instruction_wsubhss-instruction_handler\r
+       db      'wsubhus~~',0x00\r
+       dw      ARM_instruction_wsubhus-instruction_handler\r
+       db      'wsubwss~~',0x00\r
+       dw      ARM_instruction_wsubwss-instruction_handler\r
+       db      'wsubwus~~',0x00\r
+       dw      ARM_instruction_wsubwus-instruction_handler\r
+       db      'wunpckihb',0xe0\r
+       dw      ARM_instruction_wunpckihb-instruction_handler\r
+       db      'wunpckihh',0xe0\r
+       dw      ARM_instruction_wunpckihh-instruction_handler\r
+       db      'wunpckihw',0xe0\r
+       dw      ARM_instruction_wunpckihw-instruction_handler\r
+       db      'wunpckilb',0xe0\r
+       dw      ARM_instruction_wunpckilb-instruction_handler\r
+       db      'wunpckilh',0xe0\r
+       dw      ARM_instruction_wunpckilh-instruction_handler\r
+       db      'wunpckilw',0xe0\r
+       dw      ARM_instruction_wunpckilw-instruction_handler\r
+       db      'yield~~.n',0x04\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      'yield~~.w',0x02\r
+       dw      ARM_instruction_yield-instruction_handler\r
+       db      0\r
+instructions_10:\r
+       db      'cfcvt32d~~',0x00\r
+       dw      ARM_instruction_cfcvt32d-instruction_handler\r
+       db      'cfcvt32s~~',0x00\r
+       dw      ARM_instruction_cfcvt32s-instruction_handler\r
+       db      'cfcvt64d~~',0x00\r
+       dw      ARM_instruction_cfcvt64d-instruction_handler\r
+       db      'cfcvt64s~~',0x00\r
+       dw      ARM_instruction_cfcvt64s-instruction_handler\r
+       db      'cfcvtd32~~',0x00\r
+       dw      ARM_instruction_cfcvtd32-instruction_handler\r
+       db      'cfcvts32~~',0x00\r
+       dw      ARM_instruction_cfcvts32-instruction_handler\r
+       db      'cfmadd32~~',0x00\r
+       dw      ARM_instruction_cfmadd32-instruction_handler\r
+       db      'cfmsub32~~',0x00\r
+       dw      ARM_instruction_cfmsub32-instruction_handler\r
+       db      'cfmv32ah~~',0x00\r
+       dw      ARM_instruction_cfmv32ah-instruction_handler\r
+       db      'cfmv32al~~',0x00\r
+       dw      ARM_instruction_cfmv32al-instruction_handler\r
+       db      'cfmv32am~~',0x00\r
+       dw      ARM_instruction_cfmv32am-instruction_handler\r
+       db      'cfmv32sc~~',0x00\r
+       dw      ARM_instruction_cfmv32sc-instruction_handler\r
+       db      'cfmv64hr~~',0x00\r
+       dw      ARM_instruction_cfmv64hr-instruction_handler\r
+       db      'cfmv64lr~~',0x00\r
+       dw      ARM_instruction_cfmv64lr-instruction_handler\r
+       db      'cfmvah32~~',0x00\r
+       dw      ARM_instruction_cfmvah32-instruction_handler\r
+       db      'cfmval32~~',0x00\r
+       dw      ARM_instruction_cfmval32-instruction_handler\r
+       db      'cfmvam32~~',0x00\r
+       dw      ARM_instruction_cfmvam32-instruction_handler\r
+       db      'cfmvr64h~~',0x00\r
+       dw      ARM_instruction_cfmvr64h-instruction_handler\r
+       db      'cfmvr64l~~',0x00\r
+       dw      ARM_instruction_cfmvr64l-instruction_handler\r
+       db      'cfmvsc32~~',0x00\r
+       dw      ARM_instruction_cfmvsc32-instruction_handler\r
+       db      'cfrshl32~~',0x00\r
+       dw      ARM_instruction_cfrshl32-instruction_handler\r
+       db      'cfrshl64~~',0x00\r
+       dw      ARM_instruction_cfrshl64-instruction_handler\r
+       db      'cftruncd32',0xe0\r
+       dw      ARM_instruction_cftruncd32-instruction_handler\r
+       db      'cftruncs32',0xe0\r
+       dw      ARM_instruction_cftruncs32-instruction_handler\r
+       db      'qaddsubx~~',0x00\r
+       dw      ARM_instruction_qaddsubx-instruction_handler\r
+       db      'qsubaddx~~',0x00\r
+       dw      ARM_instruction_qsubaddx-instruction_handler\r
+       db      'saddsubx~~',0x00\r
+       dw      ARM_instruction_saddsubx-instruction_handler\r
+       db      'sha1su0.32',0xf0\r
+       dw      ARM_instruction_sha1su0.32-instruction_handler\r
+       db      'sha1su1.32',0xf0\r
+       dw      ARM_instruction_sha1su1.32-instruction_handler\r
+       db      'sha256h.32',0xf0\r
+       dw      ARM_instruction_sha256h.32-instruction_handler\r
+       db      'ssubaddx~~',0x00\r
+       dw      ARM_instruction_ssubaddx-instruction_handler\r
+       db      'textrmsb~~',0x00\r
+       dw      ARM_instruction_textrmsb-instruction_handler\r
+       db      'textrmsh~~',0x00\r
+       dw      ARM_instruction_textrmsh-instruction_handler\r
+       db      'textrmsw~~',0x00\r
+       dw      ARM_instruction_textrmsw-instruction_handler\r
+       db      'textrmub~~',0x00\r
+       dw      ARM_instruction_textrmub-instruction_handler\r
+       db      'textrmuh~~',0x00\r
+       dw      ARM_instruction_textrmuh-instruction_handler\r
+       db      'textrmuw~~',0x00\r
+       dw      ARM_instruction_textrmuw-instruction_handler\r
+       db      'tmovmskb~~',0x00\r
+       dw      ARM_instruction_tmovmskb-instruction_handler\r
+       db      'tmovmskh~~',0x00\r
+       dw      ARM_instruction_tmovmskh-instruction_handler\r
+       db      'tmovmskw~~',0x00\r
+       dw      ARM_instruction_tmovmskw-instruction_handler\r
+       db      'uaddsubx~~',0x00\r
+       dw      ARM_instruction_uaddsubx-instruction_handler\r
+       db      'usubaddx~~',0x00\r
+       dw      ARM_instruction_usubaddx-instruction_handler\r
+       db      'vabal~~.s8',0x00\r
+       dw      ARM_instruction_vabal.s8-instruction_handler\r
+       db      'vabal~~.u8',0x00\r
+       dw      ARM_instruction_vabal.u8-instruction_handler\r
+       db      'vaba~~.s16',0x00\r
+       dw      ARM_instruction_vaba.s16-instruction_handler\r
+       db      'vaba~~.s32',0x00\r
+       dw      ARM_instruction_vaba.s32-instruction_handler\r
+       db      'vaba~~.u16',0x00\r
+       dw      ARM_instruction_vaba.u16-instruction_handler\r
+       db      'vaba~~.u32',0x00\r
+       dw      ARM_instruction_vaba.u32-instruction_handler\r
+       db      'vabdl~~.s8',0x00\r
+       dw      ARM_instruction_vabdl.s8-instruction_handler\r
+       db      'vabdl~~.u8',0x00\r
+       dw      ARM_instruction_vabdl.u8-instruction_handler\r
+       db      'vabd~~.f32',0x00\r
+       dw      ARM_instruction_vabd.f32-instruction_handler\r
+       db      'vabd~~.s16',0x00\r
+       dw      ARM_instruction_vabd.s16-instruction_handler\r
+       db      'vabd~~.s32',0x00\r
+       dw      ARM_instruction_vabd.s32-instruction_handler\r
+       db      'vabd~~.u16',0x00\r
+       dw      ARM_instruction_vabd.u16-instruction_handler\r
+       db      'vabd~~.u32',0x00\r
+       dw      ARM_instruction_vabd.u32-instruction_handler\r
+       db      'vabs~~.f32',0x00\r
+       dw      ARM_instruction_vabs.f32-instruction_handler\r
+       db      'vabs~~.f64',0x00\r
+       dw      ARM_instruction_vabs.f64-instruction_handler\r
+       db      'vabs~~.s16',0x00\r
+       dw      ARM_instruction_vabs.s16-instruction_handler\r
+       db      'vabs~~.s32',0x00\r
+       dw      ARM_instruction_vabs.s32-instruction_handler\r
+       db      'vaddhn.i16',0xe0\r
+       dw      ARM_instruction_vaddhn.i16-instruction_handler\r
+       db      'vaddhn.i32',0xe0\r
+       dw      ARM_instruction_vaddhn.i32-instruction_handler\r
+       db      'vaddhn.i64',0xe0\r
+       dw      ARM_instruction_vaddhn.i64-instruction_handler\r
+       db      'vaddl~~.s8',0x00\r
+       dw      ARM_instruction_vaddl.s8-instruction_handler\r
+       db      'vaddl~~.u8',0x00\r
+       dw      ARM_instruction_vaddl.u8-instruction_handler\r
+       db      'vaddw~~.s8',0x00\r
+       dw      ARM_instruction_vaddw.s8-instruction_handler\r
+       db      'vaddw~~.u8',0x00\r
+       dw      ARM_instruction_vaddw.u8-instruction_handler\r
+       db      'vadd~~.f32',0x00\r
+       dw      ARM_instruction_vadd.f32-instruction_handler\r
+       db      'vadd~~.f64',0x00\r
+       dw      ARM_instruction_vadd.f64-instruction_handler\r
+       db      'vadd~~.i16',0x00\r
+       dw      ARM_instruction_vadd.i16-instruction_handler\r
+       db      'vadd~~.i32',0x00\r
+       dw      ARM_instruction_vadd.i32-instruction_handler\r
+       db      'vadd~~.i64',0x00\r
+       dw      ARM_instruction_vadd.i64-instruction_handler\r
+       db      'vand~~.i16',0x00\r
+       dw      ARM_instruction_vand.i16-instruction_handler\r
+       db      'vand~~.i32',0x00\r
+       dw      ARM_instruction_vand.i32-instruction_handler\r
+       db      'vbic~~.i16',0x00\r
+       dw      ARM_instruction_vbic.i16-instruction_handler\r
+       db      'vbic~~.i32',0x00\r
+       dw      ARM_instruction_vbic.i32-instruction_handler\r
+       db      'vceq~~.f32',0x00\r
+       dw      ARM_instruction_vceq.f32-instruction_handler\r
+       db      'vceq~~.i16',0x00\r
+       dw      ARM_instruction_vceq.i16-instruction_handler\r
+       db      'vceq~~.i32',0x00\r
+       dw      ARM_instruction_vceq.i32-instruction_handler\r
+       db      'vcge~~.f32',0x00\r
+       dw      ARM_instruction_vcge.f32-instruction_handler\r
+       db      'vcge~~.s16',0x00\r
+       dw      ARM_instruction_vcge.s16-instruction_handler\r
+       db      'vcge~~.s32',0x00\r
+       dw      ARM_instruction_vcge.s32-instruction_handler\r
+       db      'vcge~~.u16',0x00\r
+       dw      ARM_instruction_vcge.u16-instruction_handler\r
+       db      'vcge~~.u32',0x00\r
+       dw      ARM_instruction_vcge.u32-instruction_handler\r
+       db      'vcgt~~.f32',0x00\r
+       dw      ARM_instruction_vcgt.f32-instruction_handler\r
+       db      'vcgt~~.s16',0x00\r
+       dw      ARM_instruction_vcgt.s16-instruction_handler\r
+       db      'vcgt~~.s32',0x00\r
+       dw      ARM_instruction_vcgt.s32-instruction_handler\r
+       db      'vcgt~~.u16',0x00\r
+       dw      ARM_instruction_vcgt.u16-instruction_handler\r
+       db      'vcgt~~.u32',0x00\r
+       dw      ARM_instruction_vcgt.u32-instruction_handler\r
+       db      'vcle~~.f32',0x00\r
+       dw      ARM_instruction_vcle.f32-instruction_handler\r
+       db      'vcle~~.s16',0x00\r
+       dw      ARM_instruction_vcle.s16-instruction_handler\r
+       db      'vcle~~.s32',0x00\r
+       dw      ARM_instruction_vcle.s32-instruction_handler\r
+       db      'vcle~~.u16',0x00\r
+       dw      ARM_instruction_vcle.u16-instruction_handler\r
+       db      'vcle~~.u32',0x00\r
+       dw      ARM_instruction_vcle.u32-instruction_handler\r
+       db      'vcls~~.s16',0x00\r
+       dw      ARM_instruction_vcls.s16-instruction_handler\r
+       db      'vcls~~.s32',0x00\r
+       dw      ARM_instruction_vcls.s32-instruction_handler\r
+       db      'vclt~~.f32',0x00\r
+       dw      ARM_instruction_vclt.f32-instruction_handler\r
+       db      'vclt~~.s16',0x00\r
+       dw      ARM_instruction_vclt.s16-instruction_handler\r
+       db      'vclt~~.s32',0x00\r
+       dw      ARM_instruction_vclt.s32-instruction_handler\r
+       db      'vclt~~.u16',0x00\r
+       dw      ARM_instruction_vclt.u16-instruction_handler\r
+       db      'vclt~~.u32',0x00\r
+       dw      ARM_instruction_vclt.u32-instruction_handler\r
+       db      'vclz~~.i16',0x00\r
+       dw      ARM_instruction_vclz.i16-instruction_handler\r
+       db      'vclz~~.i32',0x00\r
+       dw      ARM_instruction_vclz.i32-instruction_handler\r
+       db      'vcmp~~.f32',0x00\r
+       dw      ARM_instruction_vcmp.f32-instruction_handler\r
+       db      'vcmp~~.f64',0x00\r
+       dw      ARM_instruction_vcmp.f64-instruction_handler\r
+       db      'vdiv~~.f32',0x00\r
+       dw      ARM_instruction_vdiv.f32-instruction_handler\r
+       db      'vdiv~~.f64',0x00\r
+       dw      ARM_instruction_vdiv.f64-instruction_handler\r
+       db      'vfma~~.f32',0x00\r
+       dw      ARM_instruction_vfma.f32-instruction_handler\r
+       db      'vfma~~.f64',0x00\r
+       dw      ARM_instruction_vfma.f64-instruction_handler\r
+       db      'vfms~~.f32',0x00\r
+       dw      ARM_instruction_vfms.f32-instruction_handler\r
+       db      'vfms~~.f64',0x00\r
+       dw      ARM_instruction_vfms.f64-instruction_handler\r
+       db      'vhadd~~.s8',0x00\r
+       dw      ARM_instruction_vhadd.s8-instruction_handler\r
+       db      'vhadd~~.u8',0x00\r
+       dw      ARM_instruction_vhadd.u8-instruction_handler\r
+       db      'vhsub~~.s8',0x00\r
+       dw      ARM_instruction_vhsub.s8-instruction_handler\r
+       db      'vhsub~~.u8',0x00\r
+       dw      ARM_instruction_vhsub.u8-instruction_handler\r
+       db      'vmaxnm.f32',0xf0\r
+       dw      ARM_instruction_vmaxnm.f32-instruction_handler\r
+       db      'vmaxnm.f64',0xf0\r
+       dw      ARM_instruction_vmaxnm.f64-instruction_handler\r
+       db      'vmax~~.f32',0x00\r
+       dw      ARM_instruction_vmax.f32-instruction_handler\r
+       db      'vmax~~.s16',0x00\r
+       dw      ARM_instruction_vmax.s16-instruction_handler\r
+       db      'vmax~~.s32',0x00\r
+       dw      ARM_instruction_vmax.s32-instruction_handler\r
+       db      'vmax~~.u16',0x00\r
+       dw      ARM_instruction_vmax.u16-instruction_handler\r
+       db      'vmax~~.u32',0x00\r
+       dw      ARM_instruction_vmax.u32-instruction_handler\r
+       db      'vminnm.f32',0xf0\r
+       dw      ARM_instruction_vminnm.f32-instruction_handler\r
+       db      'vminnm.f64',0xf0\r
+       dw      ARM_instruction_vminnm.f64-instruction_handler\r
+       db      'vmin~~.f32',0x00\r
+       dw      ARM_instruction_vmin.f32-instruction_handler\r
+       db      'vmin~~.s16',0x00\r
+       dw      ARM_instruction_vmin.s16-instruction_handler\r
+       db      'vmin~~.s32',0x00\r
+       dw      ARM_instruction_vmin.s32-instruction_handler\r
+       db      'vmin~~.u16',0x00\r
+       dw      ARM_instruction_vmin.u16-instruction_handler\r
+       db      'vmin~~.u32',0x00\r
+       dw      ARM_instruction_vmin.u32-instruction_handler\r
+       db      'vmlal~~.s8',0x00\r
+       dw      ARM_instruction_vmlal.s8-instruction_handler\r
+       db      'vmlal~~.u8',0x00\r
+       dw      ARM_instruction_vmlal.u8-instruction_handler\r
+       db      'vmla~~.f32',0x00\r
+       dw      ARM_instruction_vmla.f32-instruction_handler\r
+       db      'vmla~~.f64',0x00\r
+       dw      ARM_instruction_vmla.f64-instruction_handler\r
+       db      'vmla~~.i16',0x00\r
+       dw      ARM_instruction_vmla.i16-instruction_handler\r
+       db      'vmla~~.i32',0x00\r
+       dw      ARM_instruction_vmla.i32-instruction_handler\r
+       db      'vmla~~.s16',0x00\r
+       dw      ARM_instruction_vmla.s16-instruction_handler\r
+       db      'vmla~~.s32',0x00\r
+       dw      ARM_instruction_vmla.s32-instruction_handler\r
+       db      'vmla~~.u16',0x00\r
+       dw      ARM_instruction_vmla.u16-instruction_handler\r
+       db      'vmla~~.u32',0x00\r
+       dw      ARM_instruction_vmla.u32-instruction_handler\r
+       db      'vmlsl~~.s8',0x00\r
+       dw      ARM_instruction_vmlsl.s8-instruction_handler\r
+       db      'vmlsl~~.u8',0x00\r
+       dw      ARM_instruction_vmlsl.u8-instruction_handler\r
+       db      'vmls~~.f32',0x00\r
+       dw      ARM_instruction_vmls.f32-instruction_handler\r
+       db      'vmls~~.f64',0x00\r
+       dw      ARM_instruction_vmls.f64-instruction_handler\r
+       db      'vmls~~.i16',0x00\r
+       dw      ARM_instruction_vmls.i16-instruction_handler\r
+       db      'vmls~~.i32',0x00\r
+       dw      ARM_instruction_vmls.i32-instruction_handler\r
+       db      'vmls~~.s16',0x00\r
+       dw      ARM_instruction_vmls.s16-instruction_handler\r
+       db      'vmls~~.s32',0x00\r
+       dw      ARM_instruction_vmls.s32-instruction_handler\r
+       db      'vmls~~.u16',0x00\r
+       dw      ARM_instruction_vmls.u16-instruction_handler\r
+       db      'vmls~~.u32',0x00\r
+       dw      ARM_instruction_vmls.u32-instruction_handler\r
+       db      'vmovl~~.s8',0x00\r
+       dw      ARM_instruction_vmovl.s8-instruction_handler\r
+       db      'vmovl~~.u8',0x00\r
+       dw      ARM_instruction_vmovl.u8-instruction_handler\r
+       db      'vmovn~~.i8',0x00\r
+       dw      ARM_instruction_vmovn.i8-instruction_handler\r
+       db      'vmov~~.f32',0x00\r
+       dw      ARM_instruction_vmov.f32-instruction_handler\r
+       db      'vmov~~.f64',0x00\r
+       dw      ARM_instruction_vmov.f64-instruction_handler\r
+       db      'vmov~~.i16',0x00\r
+       dw      ARM_instruction_vmov.i16-instruction_handler\r
+       db      'vmov~~.i32',0x00\r
+       dw      ARM_instruction_vmov.i32-instruction_handler\r
+       db      'vmov~~.i64',0x00\r
+       dw      ARM_instruction_vmov.i64-instruction_handler\r
+       db      'vmov~~.s16',0x00\r
+       dw      ARM_instruction_vmov.s16-instruction_handler\r
+       db      'vmov~~.u16',0x00\r
+       dw      ARM_instruction_vmov.u16-instruction_handler\r
+       db      'vmull~~.p8',0x00\r
+       dw      ARM_instruction_vmull.p8-instruction_handler\r
+       db      'vmull~~.s8',0x00\r
+       dw      ARM_instruction_vmull.s8-instruction_handler\r
+       db      'vmull~~.u8',0x00\r
+       dw      ARM_instruction_vmull.u8-instruction_handler\r
+       db      'vmul~~.f32',0x00\r
+       dw      ARM_instruction_vmul.f32-instruction_handler\r
+       db      'vmul~~.f64',0x00\r
+       dw      ARM_instruction_vmul.f64-instruction_handler\r
+       db      'vmul~~.i16',0x00\r
+       dw      ARM_instruction_vmul.i16-instruction_handler\r
+       db      'vmul~~.i32',0x00\r
+       dw      ARM_instruction_vmul.i32-instruction_handler\r
+       db      'vmul~~.s16',0x00\r
+       dw      ARM_instruction_vmul.s16-instruction_handler\r
+       db      'vmul~~.s32',0x00\r
+       dw      ARM_instruction_vmul.s32-instruction_handler\r
+       db      'vmul~~.u16',0x00\r
+       dw      ARM_instruction_vmul.u16-instruction_handler\r
+       db      'vmul~~.u32',0x00\r
+       dw      ARM_instruction_vmul.u32-instruction_handler\r
+       db      'vmvn~~.i16',0x00\r
+       dw      ARM_instruction_vmvn.i16-instruction_handler\r
+       db      'vmvn~~.i32',0x00\r
+       dw      ARM_instruction_vmvn.i32-instruction_handler\r
+       db      'vneg~~.f32',0x00\r
+       dw      ARM_instruction_vneg.f32-instruction_handler\r
+       db      'vneg~~.f64',0x00\r
+       dw      ARM_instruction_vneg.f64-instruction_handler\r
+       db      'vneg~~.s16',0x00\r
+       dw      ARM_instruction_vneg.s16-instruction_handler\r
+       db      'vneg~~.s32',0x00\r
+       dw      ARM_instruction_vneg.s32-instruction_handler\r
+       db      'vorn~~.i16',0x00\r
+       dw      ARM_instruction_vorn.i16-instruction_handler\r
+       db      'vorn~~.i32',0x00\r
+       dw      ARM_instruction_vorn.i32-instruction_handler\r
+       db      'vorr~~.i16',0x00\r
+       dw      ARM_instruction_vorr.i16-instruction_handler\r
+       db      'vorr~~.i32',0x00\r
+       dw      ARM_instruction_vorr.i32-instruction_handler\r
+       db      'vpadal.s16',0xe0\r
+       dw      ARM_instruction_vpadal.s16-instruction_handler\r
+       db      'vpadal.s32',0xe0\r
+       dw      ARM_instruction_vpadal.s32-instruction_handler\r
+       db      'vpadal.u16',0xe0\r
+       dw      ARM_instruction_vpadal.u16-instruction_handler\r
+       db      'vpadal.u32',0xe0\r
+       dw      ARM_instruction_vpadal.u32-instruction_handler\r
+       db      'vpaddl.s16',0xe0\r
+       dw      ARM_instruction_vpaddl.s16-instruction_handler\r
+       db      'vpaddl.s32',0xe0\r
+       dw      ARM_instruction_vpaddl.s32-instruction_handler\r
+       db      'vpaddl.u16',0xe0\r
+       dw      ARM_instruction_vpaddl.u16-instruction_handler\r
+       db      'vpaddl.u32',0xe0\r
+       dw      ARM_instruction_vpaddl.u32-instruction_handler\r
+       db      'vpadd~~.i8',0x00\r
+       dw      ARM_instruction_vpadd.i8-instruction_handler\r
+       db      'vpmax~~.s8',0x00\r
+       dw      ARM_instruction_vpmax.s8-instruction_handler\r
+       db      'vpmax~~.u8',0x00\r
+       dw      ARM_instruction_vpmax.u8-instruction_handler\r
+       db      'vpmin~~.s8',0x00\r
+       dw      ARM_instruction_vpmin.s8-instruction_handler\r
+       db      'vpmin~~.u8',0x00\r
+       dw      ARM_instruction_vpmin.u8-instruction_handler\r
+       db      'vpush~~.32',0x00\r
+       dw      ARM_instruction_vpush.32-instruction_handler\r
+       db      'vpush~~.64',0x00\r
+       dw      ARM_instruction_vpush.64-instruction_handler\r
+       db      'vqabs~~.s8',0x00\r
+       dw      ARM_instruction_vqabs.s8-instruction_handler\r
+       db      'vqadd~~.s8',0x00\r
+       dw      ARM_instruction_vqadd.s8-instruction_handler\r
+       db      'vqadd~~.u8',0x00\r
+       dw      ARM_instruction_vqadd.u8-instruction_handler\r
+       db      'vqmovn.s16',0xe0\r
+       dw      ARM_instruction_vqmovn.s16-instruction_handler\r
+       db      'vqmovn.s32',0xe0\r
+       dw      ARM_instruction_vqmovn.s32-instruction_handler\r
+       db      'vqmovn.s64',0xe0\r
+       dw      ARM_instruction_vqmovn.s64-instruction_handler\r
+       db      'vqmovn.u16',0xe0\r
+       dw      ARM_instruction_vqmovn.u16-instruction_handler\r
+       db      'vqmovn.u32',0xe0\r
+       dw      ARM_instruction_vqmovn.u32-instruction_handler\r
+       db      'vqmovn.u64',0xe0\r
+       dw      ARM_instruction_vqmovn.u64-instruction_handler\r
+       db      'vqneg~~.s8',0x00\r
+       dw      ARM_instruction_vqneg.s8-instruction_handler\r
+       db      'vqrshl.s16',0xe0\r
+       dw      ARM_instruction_vqrshl.s16-instruction_handler\r
+       db      'vqrshl.s32',0xe0\r
+       dw      ARM_instruction_vqrshl.s32-instruction_handler\r
+       db      'vqrshl.s64',0xe0\r
+       dw      ARM_instruction_vqrshl.s64-instruction_handler\r
+       db      'vqrshl.u16',0xe0\r
+       dw      ARM_instruction_vqrshl.u16-instruction_handler\r
+       db      'vqrshl.u32',0xe0\r
+       dw      ARM_instruction_vqrshl.u32-instruction_handler\r
+       db      'vqrshl.u64',0xe0\r
+       dw      ARM_instruction_vqrshl.u64-instruction_handler\r
+       db      'vqshlu.s16',0xe0\r
+       dw      ARM_instruction_vqshlu.s16-instruction_handler\r
+       db      'vqshlu.s32',0xe0\r
+       dw      ARM_instruction_vqshlu.s32-instruction_handler\r
+       db      'vqshlu.s64',0xe0\r
+       dw      ARM_instruction_vqshlu.s64-instruction_handler\r
+       db      'vqshl~~.s8',0x00\r
+       dw      ARM_instruction_vqshl.s8-instruction_handler\r
+       db      'vqshl~~.u8',0x00\r
+       dw      ARM_instruction_vqshl.u8-instruction_handler\r
+       db      'vqshrn.s16',0xe0\r
+       dw      ARM_instruction_vqshrn.s16-instruction_handler\r
+       db      'vqshrn.s32',0xe0\r
+       dw      ARM_instruction_vqshrn.s32-instruction_handler\r
+       db      'vqshrn.s64',0xe0\r
+       dw      ARM_instruction_vqshrn.s64-instruction_handler\r
+       db      'vqshrn.u16',0xe0\r
+       dw      ARM_instruction_vqshrn.u16-instruction_handler\r
+       db      'vqshrn.u32',0xe0\r
+       dw      ARM_instruction_vqshrn.u32-instruction_handler\r
+       db      'vqshrn.u64',0xe0\r
+       dw      ARM_instruction_vqshrn.u64-instruction_handler\r
+       db      'vqsub~~.s8',0x00\r
+       dw      ARM_instruction_vqsub.s8-instruction_handler\r
+       db      'vqsub~~.u8',0x00\r
+       dw      ARM_instruction_vqsub.u8-instruction_handler\r
+       db      'vrecpe.f32',0xe0\r
+       dw      ARM_instruction_vrecpe.f32-instruction_handler\r
+       db      'vrecpe.u32',0xe0\r
+       dw      ARM_instruction_vrecpe.u32-instruction_handler\r
+       db      'vrecps.f32',0xe0\r
+       dw      ARM_instruction_vrecps.f32-instruction_handler\r
+       db      'vrev16~~.8',0x00\r
+       dw      ARM_instruction_vrev16.8-instruction_handler\r
+       db      'vrev32~~.8',0x00\r
+       dw      ARM_instruction_vrev32.8-instruction_handler\r
+       db      'vrev64~~.8',0x00\r
+       dw      ARM_instruction_vrev64.8-instruction_handler\r
+       db      'vrhadd.s16',0xe0\r
+       dw      ARM_instruction_vrhadd.s16-instruction_handler\r
+       db      'vrhadd.s32',0xe0\r
+       dw      ARM_instruction_vrhadd.s32-instruction_handler\r
+       db      'vrhadd.u16',0xe0\r
+       dw      ARM_instruction_vrhadd.u16-instruction_handler\r
+       db      'vrhadd.u32',0xe0\r
+       dw      ARM_instruction_vrhadd.u32-instruction_handler\r
+       db      'vrshl~~.s8',0x00\r
+       dw      ARM_instruction_vrshl.s8-instruction_handler\r
+       db      'vrshl~~.u8',0x00\r
+       dw      ARM_instruction_vrshl.u8-instruction_handler\r
+       db      'vrshrn.i16',0xe0\r
+       dw      ARM_instruction_vrshrn.i16-instruction_handler\r
+       db      'vrshrn.i32',0xe0\r
+       dw      ARM_instruction_vrshrn.i32-instruction_handler\r
+       db      'vrshrn.i64',0xe0\r
+       dw      ARM_instruction_vrshrn.i64-instruction_handler\r
+       db      'vrshr~~.s8',0x00\r
+       dw      ARM_instruction_vrshr.s8-instruction_handler\r
+       db      'vrshr~~.u8',0x00\r
+       dw      ARM_instruction_vrshr.u8-instruction_handler\r
+       db      'vrsra~~.s8',0x00\r
+       dw      ARM_instruction_vrsra.s8-instruction_handler\r
+       db      'vrsra~~.u8',0x00\r
+       dw      ARM_instruction_vrsra.u8-instruction_handler\r
+       db      'vseleq.f32',0xf0\r
+       dw      ARM_instruction_vseleq.f32-instruction_handler\r
+       db      'vseleq.f64',0xf0\r
+       dw      ARM_instruction_vseleq.f64-instruction_handler\r
+       db      'vselge.f32',0xf0\r
+       dw      ARM_instruction_vselge.f32-instruction_handler\r
+       db      'vselge.f64',0xf0\r
+       dw      ARM_instruction_vselge.f64-instruction_handler\r
+       db      'vselgt.f32',0xf0\r
+       dw      ARM_instruction_vselgt.f32-instruction_handler\r
+       db      'vselgt.f64',0xf0\r
+       dw      ARM_instruction_vselgt.f64-instruction_handler\r
+       db      'vselvs.f32',0xf0\r
+       dw      ARM_instruction_vselvs.f32-instruction_handler\r
+       db      'vselvs.f64',0xf0\r
+       dw      ARM_instruction_vselvs.f64-instruction_handler\r
+       db      'vshll~~.i8',0x00\r
+       dw      ARM_instruction_vshll.i8-instruction_handler\r
+       db      'vshll~~.s8',0x00\r
+       dw      ARM_instruction_vshll.s8-instruction_handler\r
+       db      'vshll~~.u8',0x00\r
+       dw      ARM_instruction_vshll.u8-instruction_handler\r
+       db      'vshl~~.i16',0x00\r
+       dw      ARM_instruction_vshl.i16-instruction_handler\r
+       db      'vshl~~.i32',0x00\r
+       dw      ARM_instruction_vshl.i32-instruction_handler\r
+       db      'vshl~~.i64',0x00\r
+       dw      ARM_instruction_vshl.i64-instruction_handler\r
+       db      'vshl~~.s16',0x00\r
+       dw      ARM_instruction_vshl.s16-instruction_handler\r
+       db      'vshl~~.s32',0x00\r
+       dw      ARM_instruction_vshl.s32-instruction_handler\r
+       db      'vshl~~.s64',0x00\r
+       dw      ARM_instruction_vshl.s64-instruction_handler\r
+       db      'vshl~~.u16',0x00\r
+       dw      ARM_instruction_vshl.u16-instruction_handler\r
+       db      'vshl~~.u32',0x00\r
+       dw      ARM_instruction_vshl.u32-instruction_handler\r
+       db      'vshl~~.u64',0x00\r
+       dw      ARM_instruction_vshl.u64-instruction_handler\r
+       db      'vshr~~.s16',0x00\r
+       dw      ARM_instruction_vshr.s16-instruction_handler\r
+       db      'vshr~~.s32',0x00\r
+       dw      ARM_instruction_vshr.s32-instruction_handler\r
+       db      'vshr~~.s64',0x00\r
+       dw      ARM_instruction_vshr.s64-instruction_handler\r
+       db      'vshr~~.u16',0x00\r
+       dw      ARM_instruction_vshr.u16-instruction_handler\r
+       db      'vshr~~.u32',0x00\r
+       dw      ARM_instruction_vshr.u32-instruction_handler\r
+       db      'vshr~~.u64',0x00\r
+       dw      ARM_instruction_vshr.u64-instruction_handler\r
+       db      'vsra~~.s16',0x00\r
+       dw      ARM_instruction_vsra.s16-instruction_handler\r
+       db      'vsra~~.s32',0x00\r
+       dw      ARM_instruction_vsra.s32-instruction_handler\r
+       db      'vsra~~.s64',0x00\r
+       dw      ARM_instruction_vsra.s64-instruction_handler\r
+       db      'vsra~~.u16',0x00\r
+       dw      ARM_instruction_vsra.u16-instruction_handler\r
+       db      'vsra~~.u32',0x00\r
+       dw      ARM_instruction_vsra.u32-instruction_handler\r
+       db      'vsra~~.u64',0x00\r
+       dw      ARM_instruction_vsra.u64-instruction_handler\r
+       db      'vsubhn.i16',0xe0\r
+       dw      ARM_instruction_vsubhn.i16-instruction_handler\r
+       db      'vsubhn.i32',0xe0\r
+       dw      ARM_instruction_vsubhn.i32-instruction_handler\r
+       db      'vsubhn.i64',0xe0\r
+       dw      ARM_instruction_vsubhn.i64-instruction_handler\r
+       db      'vsubl~~.s8',0x00\r
+       dw      ARM_instruction_vsubl.s8-instruction_handler\r
+       db      'vsubl~~.u8',0x00\r
+       dw      ARM_instruction_vsubl.u8-instruction_handler\r
+       db      'vsubw~~.s8',0x00\r
+       dw      ARM_instruction_vsubw.s8-instruction_handler\r
+       db      'vsubw~~.u8',0x00\r
+       dw      ARM_instruction_vsubw.u8-instruction_handler\r
+       db      'vsub~~.f32',0x00\r
+       dw      ARM_instruction_vsub.f32-instruction_handler\r
+       db      'vsub~~.f64',0x00\r
+       dw      ARM_instruction_vsub.f64-instruction_handler\r
+       db      'vsub~~.i16',0x00\r
+       dw      ARM_instruction_vsub.i16-instruction_handler\r
+       db      'vsub~~.i32',0x00\r
+       dw      ARM_instruction_vsub.i32-instruction_handler\r
+       db      'vsub~~.i64',0x00\r
+       dw      ARM_instruction_vsub.i64-instruction_handler\r
+       db      'walignr0~~',0x00\r
+       dw      ARM_instruction_walignr0-instruction_handler\r
+       db      'walignr1~~',0x00\r
+       dw      ARM_instruction_walignr1-instruction_handler\r
+       db      'walignr2~~',0x00\r
+       dw      ARM_instruction_walignr2-instruction_handler\r
+       db      'walignr3~~',0x00\r
+       dw      ARM_instruction_walignr3-instruction_handler\r
+       db      'wcmpgtsb~~',0x00\r
+       dw      ARM_instruction_wcmpgtsb-instruction_handler\r
+       db      'wcmpgtsh~~',0x00\r
+       dw      ARM_instruction_wcmpgtsh-instruction_handler\r
+       db      'wcmpgtsw~~',0x00\r
+       dw      ARM_instruction_wcmpgtsw-instruction_handler\r
+       db      'wcmpgtub~~',0x00\r
+       dw      ARM_instruction_wcmpgtub-instruction_handler\r
+       db      'wcmpgtuh~~',0x00\r
+       dw      ARM_instruction_wcmpgtuh-instruction_handler\r
+       db      'wcmpgtuw~~',0x00\r
+       dw      ARM_instruction_wcmpgtuw-instruction_handler\r
+       db      'wmiawbbn~~',0x00\r
+       dw      ARM_instruction_wmiawbbn-instruction_handler\r
+       db      'wmiawbtn~~',0x00\r
+       dw      ARM_instruction_wmiawbtn-instruction_handler\r
+       db      'wmiawtbn~~',0x00\r
+       dw      ARM_instruction_wmiawtbn-instruction_handler\r
+       db      'wmiawttn~~',0x00\r
+       dw      ARM_instruction_wmiawttn-instruction_handler\r
+       db      'wmulwsmr~~',0x00\r
+       dw      ARM_instruction_wmulwsmr-instruction_handler\r
+       db      'wmulwumr~~',0x00\r
+       dw      ARM_instruction_wmulwumr-instruction_handler\r
+       db      'wpackdss~~',0x00\r
+       dw      ARM_instruction_wpackdss-instruction_handler\r
+       db      'wpackdus~~',0x00\r
+       dw      ARM_instruction_wpackdus-instruction_handler\r
+       db      'wpackhss~~',0x00\r
+       dw      ARM_instruction_wpackhss-instruction_handler\r
+       db      'wpackhus~~',0x00\r
+       dw      ARM_instruction_wpackhus-instruction_handler\r
+       db      'wpackwss~~',0x00\r
+       dw      ARM_instruction_wpackwss-instruction_handler\r
+       db      'wpackwus~~',0x00\r
+       dw      ARM_instruction_wpackwus-instruction_handler\r
+       db      'wqmiabbn~~',0x00\r
+       dw      ARM_instruction_wqmiabbn-instruction_handler\r
+       db      'wqmiabtn~~',0x00\r
+       dw      ARM_instruction_wqmiabtn-instruction_handler\r
+       db      'wqmiatbn~~',0x00\r
+       dw      ARM_instruction_wqmiatbn-instruction_handler\r
+       db      'wqmiattn~~',0x00\r
+       dw      ARM_instruction_wqmiattn-instruction_handler\r
+       db      'wqmulwmr~~',0x00\r
+       dw      ARM_instruction_wqmulwmr-instruction_handler\r
+       db      'wunpckehsb',0xe0\r
+       dw      ARM_instruction_wunpckehsb-instruction_handler\r
+       db      'wunpckehsh',0xe0\r
+       dw      ARM_instruction_wunpckehsh-instruction_handler\r
+       db      'wunpckehsw',0xe0\r
+       dw      ARM_instruction_wunpckehsw-instruction_handler\r
+       db      'wunpckehub',0xe0\r
+       dw      ARM_instruction_wunpckehub-instruction_handler\r
+       db      'wunpckehuh',0xe0\r
+       dw      ARM_instruction_wunpckehuh-instruction_handler\r
+       db      'wunpckehuw',0xe0\r
+       dw      ARM_instruction_wunpckehuw-instruction_handler\r
+       db      'wunpckelsb',0xe0\r
+       dw      ARM_instruction_wunpckelsb-instruction_handler\r
+       db      'wunpckelsh',0xe0\r
+       dw      ARM_instruction_wunpckelsh-instruction_handler\r
+       db      'wunpckelsw',0xe0\r
+       dw      ARM_instruction_wunpckelsw-instruction_handler\r
+       db      'wunpckelub',0xe0\r
+       dw      ARM_instruction_wunpckelub-instruction_handler\r
+       db      'wunpckeluh',0xe0\r
+       dw      ARM_instruction_wunpckeluh-instruction_handler\r
+       db      'wunpckeluw',0xe0\r
+       dw      ARM_instruction_wunpckeluw-instruction_handler\r
+       db      0\r
+instructions_11:\r
+       db      'cfmadda32~~',0x00\r
+       dw      ARM_instruction_cfmadda32-instruction_handler\r
+       db      'cfmsuba32~~',0x00\r
+       dw      ARM_instruction_cfmsuba32-instruction_handler\r
+       db      'coprocessor',0x00\r
+       dw      ARM_coprocessor_directive-instruction_handler\r
+       db      'sha256h2.32',0xf0\r
+       dw      ARM_instruction_sha256h2.32-instruction_handler\r
+       db      'shaddsubx~~',0x00\r
+       dw      ARM_instruction_shaddsubx-instruction_handler\r
+       db      'shsubaddx~~',0x00\r
+       dw      ARM_instruction_shsubaddx-instruction_handler\r
+       db      'uhaddsubx~~',0x00\r
+       dw      ARM_instruction_uhaddsubx-instruction_handler\r
+       db      'uhsubaddx~~',0x00\r
+       dw      ARM_instruction_uhsubaddx-instruction_handler\r
+       db      'uqaddsubx~~',0x00\r
+       dw      ARM_instruction_uqaddsubx-instruction_handler\r
+       db      'uqsubaddx~~',0x00\r
+       dw      ARM_instruction_uqsubaddx-instruction_handler\r
+       db      'vabal~~.s16',0x00\r
+       dw      ARM_instruction_vabal.s16-instruction_handler\r
+       db      'vabal~~.s32',0x00\r
+       dw      ARM_instruction_vabal.s32-instruction_handler\r
+       db      'vabal~~.u16',0x00\r
+       dw      ARM_instruction_vabal.u16-instruction_handler\r
+       db      'vabal~~.u32',0x00\r
+       dw      ARM_instruction_vabal.u32-instruction_handler\r
+       db      'vabdl~~.s16',0x00\r
+       dw      ARM_instruction_vabdl.s16-instruction_handler\r
+       db      'vabdl~~.s32',0x00\r
+       dw      ARM_instruction_vabdl.s32-instruction_handler\r
+       db      'vabdl~~.u16',0x00\r
+       dw      ARM_instruction_vabdl.u16-instruction_handler\r
+       db      'vabdl~~.u32',0x00\r
+       dw      ARM_instruction_vabdl.u32-instruction_handler\r
+       db      'vacge~~.f32',0x00\r
+       dw      ARM_instruction_vacge.f32-instruction_handler\r
+       db      'vacgt~~.f32',0x00\r
+       dw      ARM_instruction_vacgt.f32-instruction_handler\r
+       db      'vacle~~.f32',0x00\r
+       dw      ARM_instruction_vacle.f32-instruction_handler\r
+       db      'vaclt~~.f32',0x00\r
+       dw      ARM_instruction_vaclt.f32-instruction_handler\r
+       db      'vaddl~~.s16',0x00\r
+       dw      ARM_instruction_vaddl.s16-instruction_handler\r
+       db      'vaddl~~.s32',0x00\r
+       dw      ARM_instruction_vaddl.s32-instruction_handler\r
+       db      'vaddl~~.u16',0x00\r
+       dw      ARM_instruction_vaddl.u16-instruction_handler\r
+       db      'vaddl~~.u32',0x00\r
+       dw      ARM_instruction_vaddl.u32-instruction_handler\r
+       db      'vaddw~~.s16',0x00\r
+       dw      ARM_instruction_vaddw.s16-instruction_handler\r
+       db      'vaddw~~.s32',0x00\r
+       dw      ARM_instruction_vaddw.s32-instruction_handler\r
+       db      'vaddw~~.u16',0x00\r
+       dw      ARM_instruction_vaddw.u16-instruction_handler\r
+       db      'vaddw~~.u32',0x00\r
+       dw      ARM_instruction_vaddw.u32-instruction_handler\r
+       db      'vcmpe~~.f32',0x00\r
+       dw      ARM_instruction_vcmpe.f32-instruction_handler\r
+       db      'vcmpe~~.f64',0x00\r
+       dw      ARM_instruction_vcmpe.f64-instruction_handler\r
+       db      'vfnma~~.f32',0x00\r
+       dw      ARM_instruction_vfnma.f32-instruction_handler\r
+       db      'vfnma~~.f64',0x00\r
+       dw      ARM_instruction_vfnma.f64-instruction_handler\r
+       db      'vfnms~~.f32',0x00\r
+       dw      ARM_instruction_vfnms.f32-instruction_handler\r
+       db      'vfnms~~.f64',0x00\r
+       dw      ARM_instruction_vfnms.f64-instruction_handler\r
+       db      'vhadd~~.s16',0x00\r
+       dw      ARM_instruction_vhadd.s16-instruction_handler\r
+       db      'vhadd~~.s32',0x00\r
+       dw      ARM_instruction_vhadd.s32-instruction_handler\r
+       db      'vhadd~~.u16',0x00\r
+       dw      ARM_instruction_vhadd.u16-instruction_handler\r
+       db      'vhadd~~.u32',0x00\r
+       dw      ARM_instruction_vhadd.u32-instruction_handler\r
+       db      'vhsub~~.s16',0x00\r
+       dw      ARM_instruction_vhsub.s16-instruction_handler\r
+       db      'vhsub~~.s32',0x00\r
+       dw      ARM_instruction_vhsub.s32-instruction_handler\r
+       db      'vhsub~~.u16',0x00\r
+       dw      ARM_instruction_vhsub.u16-instruction_handler\r
+       db      'vhsub~~.u32',0x00\r
+       dw      ARM_instruction_vhsub.u32-instruction_handler\r
+       db      'vldmdb~~.32',0x00\r
+       dw      ARM_instruction_vldmdb.32-instruction_handler\r
+       db      'vldmdb~~.64',0x00\r
+       dw      ARM_instruction_vldmdb.64-instruction_handler\r
+       db      'vldmea~~.32',0x00\r
+       dw      ARM_instruction_vldmea.32-instruction_handler\r
+       db      'vldmea~~.64',0x00\r
+       dw      ARM_instruction_vldmea.64-instruction_handler\r
+       db      'vldmfd~~.32',0x00\r
+       dw      ARM_instruction_vldmfd.32-instruction_handler\r
+       db      'vldmfd~~.64',0x00\r
+       dw      ARM_instruction_vldmfd.64-instruction_handler\r
+       db      'vldmia~~.32',0x00\r
+       dw      ARM_instruction_vldmia.32-instruction_handler\r
+       db      'vldmia~~.64',0x00\r
+       dw      ARM_instruction_vldmia.64-instruction_handler\r
+       db      'vmlal~~.s16',0x00\r
+       dw      ARM_instruction_vmlal.s16-instruction_handler\r
+       db      'vmlal~~.s32',0x00\r
+       dw      ARM_instruction_vmlal.s32-instruction_handler\r
+       db      'vmlal~~.u16',0x00\r
+       dw      ARM_instruction_vmlal.u16-instruction_handler\r
+       db      'vmlal~~.u32',0x00\r
+       dw      ARM_instruction_vmlal.u32-instruction_handler\r
+       db      'vmlsl~~.s16',0x00\r
+       dw      ARM_instruction_vmlsl.s16-instruction_handler\r
+       db      'vmlsl~~.s32',0x00\r
+       dw      ARM_instruction_vmlsl.s32-instruction_handler\r
+       db      'vmlsl~~.u16',0x00\r
+       dw      ARM_instruction_vmlsl.u16-instruction_handler\r
+       db      'vmlsl~~.u32',0x00\r
+       dw      ARM_instruction_vmlsl.u32-instruction_handler\r
+       db      'vmovl~~.s16',0x00\r
+       dw      ARM_instruction_vmovl.s16-instruction_handler\r
+       db      'vmovl~~.s32',0x00\r
+       dw      ARM_instruction_vmovl.s32-instruction_handler\r
+       db      'vmovl~~.u16',0x00\r
+       dw      ARM_instruction_vmovl.u16-instruction_handler\r
+       db      'vmovl~~.u32',0x00\r
+       dw      ARM_instruction_vmovl.u32-instruction_handler\r
+       db      'vmovn~~.i16',0x00\r
+       dw      ARM_instruction_vmovn.i16-instruction_handler\r
+       db      'vmovn~~.i32',0x00\r
+       dw      ARM_instruction_vmovn.i32-instruction_handler\r
+       db      'vmull~~.s16',0x00\r
+       dw      ARM_instruction_vmull.s16-instruction_handler\r
+       db      'vmull~~.s32',0x00\r
+       dw      ARM_instruction_vmull.s32-instruction_handler\r
+       db      'vmull~~.u16',0x00\r
+       dw      ARM_instruction_vmull.u16-instruction_handler\r
+       db      'vmull~~.u32',0x00\r
+       dw      ARM_instruction_vmull.u32-instruction_handler\r
+       db      'vnmla~~.f32',0x00\r
+       dw      ARM_instruction_vnmla.f32-instruction_handler\r
+       db      'vnmla~~.f64',0x00\r
+       dw      ARM_instruction_vnmla.f64-instruction_handler\r
+       db      'vnmls~~.f32',0x00\r
+       dw      ARM_instruction_vnmls.f32-instruction_handler\r
+       db      'vnmls~~.f64',0x00\r
+       dw      ARM_instruction_vnmls.f64-instruction_handler\r
+       db      'vnmul~~.f32',0x00\r
+       dw      ARM_instruction_vnmul.f32-instruction_handler\r
+       db      'vnmul~~.f64',0x00\r
+       dw      ARM_instruction_vnmul.f64-instruction_handler\r
+       db      'vpadal~~.s8',0x00\r
+       dw      ARM_instruction_vpadal.s8-instruction_handler\r
+       db      'vpadal~~.u8',0x00\r
+       dw      ARM_instruction_vpadal.u8-instruction_handler\r
+       db      'vpaddl~~.s8',0x00\r
+       dw      ARM_instruction_vpaddl.s8-instruction_handler\r
+       db      'vpaddl~~.u8',0x00\r
+       dw      ARM_instruction_vpaddl.u8-instruction_handler\r
+       db      'vpadd~~.f32',0x00\r
+       dw      ARM_instruction_vpadd.f32-instruction_handler\r
+       db      'vpadd~~.i16',0x00\r
+       dw      ARM_instruction_vpadd.i16-instruction_handler\r
+       db      'vpadd~~.i32',0x00\r
+       dw      ARM_instruction_vpadd.i32-instruction_handler\r
+       db      'vpmax~~.f32',0x00\r
+       dw      ARM_instruction_vpmax.f32-instruction_handler\r
+       db      'vpmax~~.s16',0x00\r
+       dw      ARM_instruction_vpmax.s16-instruction_handler\r
+       db      'vpmax~~.s32',0x00\r
+       dw      ARM_instruction_vpmax.s32-instruction_handler\r
+       db      'vpmax~~.u16',0x00\r
+       dw      ARM_instruction_vpmax.u16-instruction_handler\r
+       db      'vpmax~~.u32',0x00\r
+       dw      ARM_instruction_vpmax.u32-instruction_handler\r
+       db      'vpmin~~.f32',0x00\r
+       dw      ARM_instruction_vpmin.f32-instruction_handler\r
+       db      'vpmin~~.s16',0x00\r
+       dw      ARM_instruction_vpmin.s16-instruction_handler\r
+       db      'vpmin~~.s32',0x00\r
+       dw      ARM_instruction_vpmin.s32-instruction_handler\r
+       db      'vpmin~~.u16',0x00\r
+       dw      ARM_instruction_vpmin.u16-instruction_handler\r
+       db      'vpmin~~.u32',0x00\r
+       dw      ARM_instruction_vpmin.u32-instruction_handler\r
+       db      'vqabs~~.s16',0x00\r
+       dw      ARM_instruction_vqabs.s16-instruction_handler\r
+       db      'vqabs~~.s32',0x00\r
+       dw      ARM_instruction_vqabs.s32-instruction_handler\r
+       db      'vqadd~~.s16',0x00\r
+       dw      ARM_instruction_vqadd.s16-instruction_handler\r
+       db      'vqadd~~.s32',0x00\r
+       dw      ARM_instruction_vqadd.s32-instruction_handler\r
+       db      'vqadd~~.s64',0x00\r
+       dw      ARM_instruction_vqadd.s64-instruction_handler\r
+       db      'vqadd~~.u16',0x00\r
+       dw      ARM_instruction_vqadd.u16-instruction_handler\r
+       db      'vqadd~~.u32',0x00\r
+       dw      ARM_instruction_vqadd.u32-instruction_handler\r
+       db      'vqadd~~.u64',0x00\r
+       dw      ARM_instruction_vqadd.u64-instruction_handler\r
+       db      'vqdmlal.s16',0xe0\r
+       dw      ARM_instruction_vqdmlal.s16-instruction_handler\r
+       db      'vqdmlal.s32',0xe0\r
+       dw      ARM_instruction_vqdmlal.s32-instruction_handler\r
+       db      'vqdmlsl.s16',0xe0\r
+       dw      ARM_instruction_vqdmlsl.s16-instruction_handler\r
+       db      'vqdmlsl.s32',0xe0\r
+       dw      ARM_instruction_vqdmlsl.s32-instruction_handler\r
+       db      'vqdmulh.s16',0xe0\r
+       dw      ARM_instruction_vqdmulh.s16-instruction_handler\r
+       db      'vqdmulh.s32',0xe0\r
+       dw      ARM_instruction_vqdmulh.s32-instruction_handler\r
+       db      'vqdmull.s16',0xe0\r
+       dw      ARM_instruction_vqdmull.s16-instruction_handler\r
+       db      'vqdmull.s32',0xe0\r
+       dw      ARM_instruction_vqdmull.s32-instruction_handler\r
+       db      'vqmovun.s16',0xe0\r
+       dw      ARM_instruction_vqmovun.s16-instruction_handler\r
+       db      'vqmovun.s32',0xe0\r
+       dw      ARM_instruction_vqmovun.s32-instruction_handler\r
+       db      'vqmovun.s64',0xe0\r
+       dw      ARM_instruction_vqmovun.s64-instruction_handler\r
+       db      'vqneg~~.s16',0x00\r
+       dw      ARM_instruction_vqneg.s16-instruction_handler\r
+       db      'vqneg~~.s32',0x00\r
+       dw      ARM_instruction_vqneg.s32-instruction_handler\r
+       db      'vqrshl~~.s8',0x00\r
+       dw      ARM_instruction_vqrshl.s8-instruction_handler\r
+       db      'vqrshl~~.u8',0x00\r
+       dw      ARM_instruction_vqrshl.u8-instruction_handler\r
+       db      'vqrshrn.s16',0xe0\r
+       dw      ARM_instruction_vqrshrn.s16-instruction_handler\r
+       db      'vqrshrn.s32',0xe0\r
+       dw      ARM_instruction_vqrshrn.s32-instruction_handler\r
+       db      'vqrshrn.s64',0xe0\r
+       dw      ARM_instruction_vqrshrn.s64-instruction_handler\r
+       db      'vqrshrn.u16',0xe0\r
+       dw      ARM_instruction_vqrshrn.u16-instruction_handler\r
+       db      'vqrshrn.u32',0xe0\r
+       dw      ARM_instruction_vqrshrn.u32-instruction_handler\r
+       db      'vqrshrn.u64',0xe0\r
+       dw      ARM_instruction_vqrshrn.u64-instruction_handler\r
+       db      'vqshlu~~.s8',0x00\r
+       dw      ARM_instruction_vqshlu.s8-instruction_handler\r
+       db      'vqshl~~.s16',0x00\r
+       dw      ARM_instruction_vqshl.s16-instruction_handler\r
+       db      'vqshl~~.s32',0x00\r
+       dw      ARM_instruction_vqshl.s32-instruction_handler\r
+       db      'vqshl~~.s64',0x00\r
+       dw      ARM_instruction_vqshl.s64-instruction_handler\r
+       db      'vqshl~~.u16',0x00\r
+       dw      ARM_instruction_vqshl.u16-instruction_handler\r
+       db      'vqshl~~.u32',0x00\r
+       dw      ARM_instruction_vqshl.u32-instruction_handler\r
+       db      'vqshl~~.u64',0x00\r
+       dw      ARM_instruction_vqshl.u64-instruction_handler\r
+       db      'vqshrun.s16',0xe0\r
+       dw      ARM_instruction_vqshrun.s16-instruction_handler\r
+       db      'vqshrun.s32',0xe0\r
+       dw      ARM_instruction_vqshrun.s32-instruction_handler\r
+       db      'vqshrun.s64',0xe0\r
+       dw      ARM_instruction_vqshrun.s64-instruction_handler\r
+       db      'vqsub~~.s16',0x00\r
+       dw      ARM_instruction_vqsub.s16-instruction_handler\r
+       db      'vqsub~~.s32',0x00\r
+       dw      ARM_instruction_vqsub.s32-instruction_handler\r
+       db      'vqsub~~.s64',0x00\r
+       dw      ARM_instruction_vqsub.s64-instruction_handler\r
+       db      'vqsub~~.u16',0x00\r
+       dw      ARM_instruction_vqsub.u16-instruction_handler\r
+       db      'vqsub~~.u32',0x00\r
+       dw      ARM_instruction_vqsub.u32-instruction_handler\r
+       db      'vqsub~~.u64',0x00\r
+       dw      ARM_instruction_vqsub.u64-instruction_handler\r
+       db      'vraddhn.i16',0xe0\r
+       dw      ARM_instruction_vraddhn.i16-instruction_handler\r
+       db      'vraddhn.i32',0xe0\r
+       dw      ARM_instruction_vraddhn.i32-instruction_handler\r
+       db      'vraddhn.i64',0xe0\r
+       dw      ARM_instruction_vraddhn.i64-instruction_handler\r
+       db      'vrev32~~.16',0x00\r
+       dw      ARM_instruction_vrev32.16-instruction_handler\r
+       db      'vrev64~~.16',0x00\r
+       dw      ARM_instruction_vrev64.16-instruction_handler\r
+       db      'vrev64~~.32',0x00\r
+       dw      ARM_instruction_vrev64.32-instruction_handler\r
+       db      'vrhadd~~.s8',0x00\r
+       dw      ARM_instruction_vrhadd.s8-instruction_handler\r
+       db      'vrhadd~~.u8',0x00\r
+       dw      ARM_instruction_vrhadd.u8-instruction_handler\r
+       db      'vrshl~~.s16',0x00\r
+       dw      ARM_instruction_vrshl.s16-instruction_handler\r
+       db      'vrshl~~.s32',0x00\r
+       dw      ARM_instruction_vrshl.s32-instruction_handler\r
+       db      'vrshl~~.s64',0x00\r
+       dw      ARM_instruction_vrshl.s64-instruction_handler\r
+       db      'vrshl~~.u16',0x00\r
+       dw      ARM_instruction_vrshl.u16-instruction_handler\r
+       db      'vrshl~~.u32',0x00\r
+       dw      ARM_instruction_vrshl.u32-instruction_handler\r
+       db      'vrshl~~.u64',0x00\r
+       dw      ARM_instruction_vrshl.u64-instruction_handler\r
+       db      'vrshr~~.s16',0x00\r
+       dw      ARM_instruction_vrshr.s16-instruction_handler\r
+       db      'vrshr~~.s32',0x00\r
+       dw      ARM_instruction_vrshr.s32-instruction_handler\r
+       db      'vrshr~~.s64',0x00\r
+       dw      ARM_instruction_vrshr.s64-instruction_handler\r
+       db      'vrshr~~.u16',0x00\r
+       dw      ARM_instruction_vrshr.u16-instruction_handler\r
+       db      'vrshr~~.u32',0x00\r
+       dw      ARM_instruction_vrshr.u32-instruction_handler\r
+       db      'vrshr~~.u64',0x00\r
+       dw      ARM_instruction_vrshr.u64-instruction_handler\r
+       db      'vrsqrte.f32',0xe0\r
+       dw      ARM_instruction_vrsqrte.f32-instruction_handler\r
+       db      'vrsqrte.u32',0xe0\r
+       dw      ARM_instruction_vrsqrte.u32-instruction_handler\r
+       db      'vrsqrts.f32',0xe0\r
+       dw      ARM_instruction_vrsqrts.f32-instruction_handler\r
+       db      'vrsra~~.s16',0x00\r
+       dw      ARM_instruction_vrsra.s16-instruction_handler\r
+       db      'vrsra~~.s32',0x00\r
+       dw      ARM_instruction_vrsra.s32-instruction_handler\r
+       db      'vrsra~~.s64',0x00\r
+       dw      ARM_instruction_vrsra.s64-instruction_handler\r
+       db      'vrsra~~.u16',0x00\r
+       dw      ARM_instruction_vrsra.u16-instruction_handler\r
+       db      'vrsra~~.u32',0x00\r
+       dw      ARM_instruction_vrsra.u32-instruction_handler\r
+       db      'vrsra~~.u64',0x00\r
+       dw      ARM_instruction_vrsra.u64-instruction_handler\r
+       db      'vrsubhn.i16',0xe0\r
+       dw      ARM_instruction_vrsubhn.i16-instruction_handler\r
+       db      'vrsubhn.i32',0xe0\r
+       dw      ARM_instruction_vrsubhn.i32-instruction_handler\r
+       db      'vrsubhn.i64',0xe0\r
+       dw      ARM_instruction_vrsubhn.i64-instruction_handler\r
+       db      'vshll~~.i16',0x00\r
+       dw      ARM_instruction_vshll.i16-instruction_handler\r
+       db      'vshll~~.i32',0x00\r
+       dw      ARM_instruction_vshll.i32-instruction_handler\r
+       db      'vshll~~.s16',0x00\r
+       dw      ARM_instruction_vshll.s16-instruction_handler\r
+       db      'vshll~~.s32',0x00\r
+       dw      ARM_instruction_vshll.s32-instruction_handler\r
+       db      'vshll~~.u16',0x00\r
+       dw      ARM_instruction_vshll.u16-instruction_handler\r
+       db      'vshll~~.u32',0x00\r
+       dw      ARM_instruction_vshll.u32-instruction_handler\r
+       db      'vshrn~~.i16',0x00\r
+       dw      ARM_instruction_vshrn.i16-instruction_handler\r
+       db      'vshrn~~.i32',0x00\r
+       dw      ARM_instruction_vshrn.i32-instruction_handler\r
+       db      'vshrn~~.i64',0x00\r
+       dw      ARM_instruction_vshrn.i64-instruction_handler\r
+       db      'vsqrt~~.f32',0x00\r
+       dw      ARM_instruction_vsqrt.f32-instruction_handler\r
+       db      'vsqrt~~.f64',0x00\r
+       dw      ARM_instruction_vsqrt.f64-instruction_handler\r
+       db      'vstmdb~~.32',0x00\r
+       dw      ARM_instruction_vstmdb.32-instruction_handler\r
+       db      'vstmdb~~.64',0x00\r
+       dw      ARM_instruction_vstmdb.64-instruction_handler\r
+       db      'vstmea~~.32',0x00\r
+       dw      ARM_instruction_vstmea.32-instruction_handler\r
+       db      'vstmea~~.64',0x00\r
+       dw      ARM_instruction_vstmea.64-instruction_handler\r
+       db      'vstmfd~~.32',0x00\r
+       dw      ARM_instruction_vstmfd.32-instruction_handler\r
+       db      'vstmfd~~.64',0x00\r
+       dw      ARM_instruction_vstmfd.64-instruction_handler\r
+       db      'vstmia~~.32',0x00\r
+       dw      ARM_instruction_vstmia.32-instruction_handler\r
+       db      'vstmia~~.64',0x00\r
+       dw      ARM_instruction_vstmia.64-instruction_handler\r
+       db      'vsubl~~.s16',0x00\r
+       dw      ARM_instruction_vsubl.s16-instruction_handler\r
+       db      'vsubl~~.s32',0x00\r
+       dw      ARM_instruction_vsubl.s32-instruction_handler\r
+       db      'vsubl~~.u16',0x00\r
+       dw      ARM_instruction_vsubl.u16-instruction_handler\r
+       db      'vsubl~~.u32',0x00\r
+       dw      ARM_instruction_vsubl.u32-instruction_handler\r
+       db      'vsubw~~.s16',0x00\r
+       dw      ARM_instruction_vsubw.s16-instruction_handler\r
+       db      'vsubw~~.s32',0x00\r
+       dw      ARM_instruction_vsubw.s32-instruction_handler\r
+       db      'vsubw~~.u16',0x00\r
+       dw      ARM_instruction_vsubw.u16-instruction_handler\r
+       db      'vsubw~~.u32',0x00\r
+       dw      ARM_instruction_vsubw.u32-instruction_handler\r
+       db      'wabsdiffb~~',0x00\r
+       dw      ARM_instruction_wabsdiffb-instruction_handler\r
+       db      'wabsdiffh~~',0x00\r
+       dw      ARM_instruction_wabsdiffh-instruction_handler\r
+       db      'wabsdiffw~~',0x00\r
+       dw      ARM_instruction_wabsdiffw-instruction_handler\r
+       db      'waddsubhx~~',0x00\r
+       dw      ARM_instruction_waddsubhx-instruction_handler\r
+       db      'wsubaddhx~~',0x00\r
+       dw      ARM_instruction_wsubaddhx-instruction_handler\r
+       db      'wunpckihb~~',0x00\r
+       dw      ARM_instruction_wunpckihb-instruction_handler\r
+       db      'wunpckihh~~',0x00\r
+       dw      ARM_instruction_wunpckihh-instruction_handler\r
+       db      'wunpckihw~~',0x00\r
+       dw      ARM_instruction_wunpckihw-instruction_handler\r
+       db      'wunpckilb~~',0x00\r
+       dw      ARM_instruction_wunpckilb-instruction_handler\r
+       db      'wunpckilh~~',0x00\r
+       dw      ARM_instruction_wunpckilh-instruction_handler\r
+       db      'wunpckilw~~',0x00\r
+       dw      ARM_instruction_wunpckilw-instruction_handler\r
+       db      0\r
+instructions_12:\r
+       db      'cftruncd32~~',0x00\r
+       dw      ARM_instruction_cftruncd32-instruction_handler\r
+       db      'cftruncs32~~',0x00\r
+       dw      ARM_instruction_cftruncs32-instruction_handler\r
+       db      'sha256su0.32',0xf0\r
+       dw      ARM_instruction_sha256su0.32-instruction_handler\r
+       db      'sha256su1.32',0xf0\r
+       dw      ARM_instruction_sha256su1.32-instruction_handler\r
+       db      'vaddhn~~.i16',0x00\r
+       dw      ARM_instruction_vaddhn.i16-instruction_handler\r
+       db      'vaddhn~~.i32',0x00\r
+       dw      ARM_instruction_vaddhn.i32-instruction_handler\r
+       db      'vaddhn~~.i64',0x00\r
+       dw      ARM_instruction_vaddhn.i64-instruction_handler\r
+       db      'vcvt.f16.f32',0xe0\r
+       dw      ARM_instruction_vcvt.f16.f32-instruction_handler\r
+       db      'vcvt.f32.f16',0xe0\r
+       dw      ARM_instruction_vcvt.f32.f16-instruction_handler\r
+       db      'vcvt.f32.f64',0xe0\r
+       dw      ARM_instruction_vcvt.f32.f64-instruction_handler\r
+       db      'vcvt.f32.s16',0xe0\r
+       dw      ARM_instruction_vcvt.f32.s16-instruction_handler\r
+       db      'vcvt.f32.s32',0xe0\r
+       dw      ARM_instruction_vcvt.f32.s32-instruction_handler\r
+       db      'vcvt.f32.u16',0xe0\r
+       dw      ARM_instruction_vcvt.f32.u16-instruction_handler\r
+       db      'vcvt.f32.u32',0xe0\r
+       dw      ARM_instruction_vcvt.f32.u32-instruction_handler\r
+       db      'vcvt.f64.f32',0xe0\r
+       dw      ARM_instruction_vcvt.f64.f32-instruction_handler\r
+       db      'vcvt.f64.s16',0xe0\r
+       dw      ARM_instruction_vcvt.f64.s16-instruction_handler\r
+       db      'vcvt.f64.s32',0xe0\r
+       dw      ARM_instruction_vcvt.f64.s32-instruction_handler\r
+       db      'vcvt.f64.u16',0xe0\r
+       dw      ARM_instruction_vcvt.f64.u16-instruction_handler\r
+       db      'vcvt.f64.u32',0xe0\r
+       dw      ARM_instruction_vcvt.f64.u32-instruction_handler\r
+       db      'vcvt.s16.f32',0xe0\r
+       dw      ARM_instruction_vcvt.s16.f32-instruction_handler\r
+       db      'vcvt.s16.f64',0xe0\r
+       dw      ARM_instruction_vcvt.s16.f64-instruction_handler\r
+       db      'vcvt.s32.f32',0xe0\r
+       dw      ARM_instruction_vcvt.s32.f32-instruction_handler\r
+       db      'vcvt.s32.f64',0xe0\r
+       dw      ARM_instruction_vcvt.s32.f64-instruction_handler\r
+       db      'vcvt.u16.f32',0xe0\r
+       dw      ARM_instruction_vcvt.u16.f32-instruction_handler\r
+       db      'vcvt.u16.f64',0xe0\r
+       dw      ARM_instruction_vcvt.u16.f64-instruction_handler\r
+       db      'vcvt.u32.f32',0xe0\r
+       dw      ARM_instruction_vcvt.u32.f32-instruction_handler\r
+       db      'vcvt.u32.f64',0xe0\r
+       dw      ARM_instruction_vcvt.u32.f64-instruction_handler\r
+       db      'vpadal~~.s16',0x00\r
+       dw      ARM_instruction_vpadal.s16-instruction_handler\r
+       db      'vpadal~~.s32',0x00\r
+       dw      ARM_instruction_vpadal.s32-instruction_handler\r
+       db      'vpadal~~.u16',0x00\r
+       dw      ARM_instruction_vpadal.u16-instruction_handler\r
+       db      'vpadal~~.u32',0x00\r
+       dw      ARM_instruction_vpadal.u32-instruction_handler\r
+       db      'vpaddl~~.s16',0x00\r
+       dw      ARM_instruction_vpaddl.s16-instruction_handler\r
+       db      'vpaddl~~.s32',0x00\r
+       dw      ARM_instruction_vpaddl.s32-instruction_handler\r
+       db      'vpaddl~~.u16',0x00\r
+       dw      ARM_instruction_vpaddl.u16-instruction_handler\r
+       db      'vpaddl~~.u32',0x00\r
+       dw      ARM_instruction_vpaddl.u32-instruction_handler\r
+       db      'vqmovn~~.s16',0x00\r
+       dw      ARM_instruction_vqmovn.s16-instruction_handler\r
+       db      'vqmovn~~.s32',0x00\r
+       dw      ARM_instruction_vqmovn.s32-instruction_handler\r
+       db      'vqmovn~~.s64',0x00\r
+       dw      ARM_instruction_vqmovn.s64-instruction_handler\r
+       db      'vqmovn~~.u16',0x00\r
+       dw      ARM_instruction_vqmovn.u16-instruction_handler\r
+       db      'vqmovn~~.u32',0x00\r
+       dw      ARM_instruction_vqmovn.u32-instruction_handler\r
+       db      'vqmovn~~.u64',0x00\r
+       dw      ARM_instruction_vqmovn.u64-instruction_handler\r
+       db      'vqrdmulh.s16',0xe0\r
+       dw      ARM_instruction_vqrdmulh.s16-instruction_handler\r
+       db      'vqrdmulh.s32',0xe0\r
+       dw      ARM_instruction_vqrdmulh.s32-instruction_handler\r
+       db      'vqrshl~~.s16',0x00\r
+       dw      ARM_instruction_vqrshl.s16-instruction_handler\r
+       db      'vqrshl~~.s32',0x00\r
+       dw      ARM_instruction_vqrshl.s32-instruction_handler\r
+       db      'vqrshl~~.s64',0x00\r
+       dw      ARM_instruction_vqrshl.s64-instruction_handler\r
+       db      'vqrshl~~.u16',0x00\r
+       dw      ARM_instruction_vqrshl.u16-instruction_handler\r
+       db      'vqrshl~~.u32',0x00\r
+       dw      ARM_instruction_vqrshl.u32-instruction_handler\r
+       db      'vqrshl~~.u64',0x00\r
+       dw      ARM_instruction_vqrshl.u64-instruction_handler\r
+       db      'vqrshrun.s16',0xe0\r
+       dw      ARM_instruction_vqrshrun.s16-instruction_handler\r
+       db      'vqrshrun.s32',0xe0\r
+       dw      ARM_instruction_vqrshrun.s32-instruction_handler\r
+       db      'vqrshrun.s64',0xe0\r
+       dw      ARM_instruction_vqrshrun.s64-instruction_handler\r
+       db      'vqshlu~~.s16',0x00\r
+       dw      ARM_instruction_vqshlu.s16-instruction_handler\r
+       db      'vqshlu~~.s32',0x00\r
+       dw      ARM_instruction_vqshlu.s32-instruction_handler\r
+       db      'vqshlu~~.s64',0x00\r
+       dw      ARM_instruction_vqshlu.s64-instruction_handler\r
+       db      'vqshrn~~.s16',0x00\r
+       dw      ARM_instruction_vqshrn.s16-instruction_handler\r
+       db      'vqshrn~~.s32',0x00\r
+       dw      ARM_instruction_vqshrn.s32-instruction_handler\r
+       db      'vqshrn~~.s64',0x00\r
+       dw      ARM_instruction_vqshrn.s64-instruction_handler\r
+       db      'vqshrn~~.u16',0x00\r
+       dw      ARM_instruction_vqshrn.u16-instruction_handler\r
+       db      'vqshrn~~.u32',0x00\r
+       dw      ARM_instruction_vqshrn.u32-instruction_handler\r
+       db      'vqshrn~~.u64',0x00\r
+       dw      ARM_instruction_vqshrn.u64-instruction_handler\r
+       db      'vrecpe~~.f32',0x00\r
+       dw      ARM_instruction_vrecpe.f32-instruction_handler\r
+       db      'vrecpe~~.u32',0x00\r
+       dw      ARM_instruction_vrecpe.u32-instruction_handler\r
+       db      'vrecps~~.f32',0x00\r
+       dw      ARM_instruction_vrecps.f32-instruction_handler\r
+       db      'vrhadd~~.s16',0x00\r
+       dw      ARM_instruction_vrhadd.s16-instruction_handler\r
+       db      'vrhadd~~.s32',0x00\r
+       dw      ARM_instruction_vrhadd.s32-instruction_handler\r
+       db      'vrhadd~~.u16',0x00\r
+       dw      ARM_instruction_vrhadd.u16-instruction_handler\r
+       db      'vrhadd~~.u32',0x00\r
+       dw      ARM_instruction_vrhadd.u32-instruction_handler\r
+       db      'vrshrn~~.i16',0x00\r
+       dw      ARM_instruction_vrshrn.i16-instruction_handler\r
+       db      'vrshrn~~.i32',0x00\r
+       dw      ARM_instruction_vrshrn.i32-instruction_handler\r
+       db      'vrshrn~~.i64',0x00\r
+       dw      ARM_instruction_vrshrn.i64-instruction_handler\r
+       db      'vsubhn~~.i16',0x00\r
+       dw      ARM_instruction_vsubhn.i16-instruction_handler\r
+       db      'vsubhn~~.i32',0x00\r
+       dw      ARM_instruction_vsubhn.i32-instruction_handler\r
+       db      'vsubhn~~.i64',0x00\r
+       dw      ARM_instruction_vsubhn.i64-instruction_handler\r
+       db      'wunpckehsb~~',0x00\r
+       dw      ARM_instruction_wunpckehsb-instruction_handler\r
+       db      'wunpckehsh~~',0x00\r
+       dw      ARM_instruction_wunpckehsh-instruction_handler\r
+       db      'wunpckehsw~~',0x00\r
+       dw      ARM_instruction_wunpckehsw-instruction_handler\r
+       db      'wunpckehub~~',0x00\r
+       dw      ARM_instruction_wunpckehub-instruction_handler\r
+       db      'wunpckehuh~~',0x00\r
+       dw      ARM_instruction_wunpckehuh-instruction_handler\r
+       db      'wunpckehuw~~',0x00\r
+       dw      ARM_instruction_wunpckehuw-instruction_handler\r
+       db      'wunpckelsb~~',0x00\r
+       dw      ARM_instruction_wunpckelsb-instruction_handler\r
+       db      'wunpckelsh~~',0x00\r
+       dw      ARM_instruction_wunpckelsh-instruction_handler\r
+       db      'wunpckelsw~~',0x00\r
+       dw      ARM_instruction_wunpckelsw-instruction_handler\r
+       db      'wunpckelub~~',0x00\r
+       dw      ARM_instruction_wunpckelub-instruction_handler\r
+       db      'wunpckeluh~~',0x00\r
+       dw      ARM_instruction_wunpckeluh-instruction_handler\r
+       db      'wunpckeluw~~',0x00\r
+       dw      ARM_instruction_wunpckeluw-instruction_handler\r
+       db      0\r
+instructions_13:\r
+       db      'vcvta.s32.f32',0xf0\r
+       dw      ARM_instruction_vcvta.s32.f32-instruction_handler\r
+       db      'vcvta.s32.f64',0xf0\r
+       dw      ARM_instruction_vcvta.s32.f64-instruction_handler\r
+       db      'vcvta.u32.f32',0xf0\r
+       dw      ARM_instruction_vcvta.u32.f32-instruction_handler\r
+       db      'vcvta.u32.f64',0xf0\r
+       dw      ARM_instruction_vcvta.u32.f64-instruction_handler\r
+       db      'vcvtb.f16.f32',0xe0\r
+       dw      ARM_instruction_vcvtb.f16.f32-instruction_handler\r
+       db      'vcvtb.f16.f64',0xe0\r
+       dw      ARM_instruction_vcvtb.f16.f64-instruction_handler\r
+       db      'vcvtb.f32.f16',0xe0\r
+       dw      ARM_instruction_vcvtb.f32.f16-instruction_handler\r
+       db      'vcvtb.f64.f16',0xe0\r
+       dw      ARM_instruction_vcvtb.f64.f16-instruction_handler\r
+       db      'vcvtm.s32.f32',0xf0\r
+       dw      ARM_instruction_vcvtm.s32.f32-instruction_handler\r
+       db      'vcvtm.s32.f64',0xf0\r
+       dw      ARM_instruction_vcvtm.s32.f64-instruction_handler\r
+       db      'vcvtm.u32.f32',0xf0\r
+       dw      ARM_instruction_vcvtm.u32.f32-instruction_handler\r
+       db      'vcvtm.u32.f64',0xf0\r
+       dw      ARM_instruction_vcvtm.u32.f64-instruction_handler\r
+       db      'vcvtn.s32.f32',0xf0\r
+       dw      ARM_instruction_vcvtn.s32.f32-instruction_handler\r
+       db      'vcvtn.s32.f64',0xf0\r
+       dw      ARM_instruction_vcvtn.s32.f64-instruction_handler\r
+       db      'vcvtn.u32.f32',0xf0\r
+       dw      ARM_instruction_vcvtn.u32.f32-instruction_handler\r
+       db      'vcvtn.u32.f64',0xf0\r
+       dw      ARM_instruction_vcvtn.u32.f64-instruction_handler\r
+       db      'vcvtp.s32.f32',0xf0\r
+       dw      ARM_instruction_vcvtp.s32.f32-instruction_handler\r
+       db      'vcvtp.s32.f64',0xf0\r
+       dw      ARM_instruction_vcvtp.s32.f64-instruction_handler\r
+       db      'vcvtp.u32.f32',0xf0\r
+       dw      ARM_instruction_vcvtp.u32.f32-instruction_handler\r
+       db      'vcvtp.u32.f64',0xf0\r
+       dw      ARM_instruction_vcvtp.u32.f64-instruction_handler\r
+       db      'vcvtr.s32.f32',0xe0\r
+       dw      ARM_instruction_vcvtr.s32.f32-instruction_handler\r
+       db      'vcvtr.s32.f64',0xe0\r
+       dw      ARM_instruction_vcvtr.s32.f64-instruction_handler\r
+       db      'vcvtr.u32.f32',0xe0\r
+       dw      ARM_instruction_vcvtr.u32.f32-instruction_handler\r
+       db      'vcvtr.u32.f64',0xe0\r
+       dw      ARM_instruction_vcvtr.u32.f64-instruction_handler\r
+       db      'vcvtt.f16.f32',0xe0\r
+       dw      ARM_instruction_vcvtt.f16.f32-instruction_handler\r
+       db      'vcvtt.f16.f64',0xe0\r
+       dw      ARM_instruction_vcvtt.f16.f64-instruction_handler\r
+       db      'vcvtt.f32.f16',0xe0\r
+       dw      ARM_instruction_vcvtt.f32.f16-instruction_handler\r
+       db      'vcvtt.f64.f16',0xe0\r
+       dw      ARM_instruction_vcvtt.f64.f16-instruction_handler\r
+       db      'vqdmlal~~.s16',0x00\r
+       dw      ARM_instruction_vqdmlal.s16-instruction_handler\r
+       db      'vqdmlal~~.s32',0x00\r
+       dw      ARM_instruction_vqdmlal.s32-instruction_handler\r
+       db      'vqdmlsl~~.s16',0x00\r
+       dw      ARM_instruction_vqdmlsl.s16-instruction_handler\r
+       db      'vqdmlsl~~.s32',0x00\r
+       dw      ARM_instruction_vqdmlsl.s32-instruction_handler\r
+       db      'vqdmulh~~.s16',0x00\r
+       dw      ARM_instruction_vqdmulh.s16-instruction_handler\r
+       db      'vqdmulh~~.s32',0x00\r
+       dw      ARM_instruction_vqdmulh.s32-instruction_handler\r
+       db      'vqdmull~~.s16',0x00\r
+       dw      ARM_instruction_vqdmull.s16-instruction_handler\r
+       db      'vqdmull~~.s32',0x00\r
+       dw      ARM_instruction_vqdmull.s32-instruction_handler\r
+       db      'vqmovun~~.s16',0x00\r
+       dw      ARM_instruction_vqmovun.s16-instruction_handler\r
+       db      'vqmovun~~.s32',0x00\r
+       dw      ARM_instruction_vqmovun.s32-instruction_handler\r
+       db      'vqmovun~~.s64',0x00\r
+       dw      ARM_instruction_vqmovun.s64-instruction_handler\r
+       db      'vqrshrn~~.s16',0x00\r
+       dw      ARM_instruction_vqrshrn.s16-instruction_handler\r
+       db      'vqrshrn~~.s32',0x00\r
+       dw      ARM_instruction_vqrshrn.s32-instruction_handler\r
+       db      'vqrshrn~~.s64',0x00\r
+       dw      ARM_instruction_vqrshrn.s64-instruction_handler\r
+       db      'vqrshrn~~.u16',0x00\r
+       dw      ARM_instruction_vqrshrn.u16-instruction_handler\r
+       db      'vqrshrn~~.u32',0x00\r
+       dw      ARM_instruction_vqrshrn.u32-instruction_handler\r
+       db      'vqrshrn~~.u64',0x00\r
+       dw      ARM_instruction_vqrshrn.u64-instruction_handler\r
+       db      'vqshrun~~.s16',0x00\r
+       dw      ARM_instruction_vqshrun.s16-instruction_handler\r
+       db      'vqshrun~~.s32',0x00\r
+       dw      ARM_instruction_vqshrun.s32-instruction_handler\r
+       db      'vqshrun~~.s64',0x00\r
+       dw      ARM_instruction_vqshrun.s64-instruction_handler\r
+       db      'vraddhn~~.i16',0x00\r
+       dw      ARM_instruction_vraddhn.i16-instruction_handler\r
+       db      'vraddhn~~.i32',0x00\r
+       dw      ARM_instruction_vraddhn.i32-instruction_handler\r
+       db      'vraddhn~~.i64',0x00\r
+       dw      ARM_instruction_vraddhn.i64-instruction_handler\r
+       db      'vrsqrte~~.f32',0x00\r
+       dw      ARM_instruction_vrsqrte.f32-instruction_handler\r
+       db      'vrsqrte~~.u32',0x00\r
+       dw      ARM_instruction_vrsqrte.u32-instruction_handler\r
+       db      'vrsqrts~~.f32',0x00\r
+       dw      ARM_instruction_vrsqrts.f32-instruction_handler\r
+       db      'vrsubhn~~.i16',0x00\r
+       dw      ARM_instruction_vrsubhn.i16-instruction_handler\r
+       db      'vrsubhn~~.i32',0x00\r
+       dw      ARM_instruction_vrsubhn.i32-instruction_handler\r
+       db      'vrsubhn~~.i64',0x00\r
+       dw      ARM_instruction_vrsubhn.i64-instruction_handler\r
+       db      0\r
+instructions_14:\r
+       db      'vcvt~~.f16.f32',0x00\r
+       dw      ARM_instruction_vcvt.f16.f32-instruction_handler\r
+       db      'vcvt~~.f32.f16',0x00\r
+       dw      ARM_instruction_vcvt.f32.f16-instruction_handler\r
+       db      'vcvt~~.f32.f64',0x00\r
+       dw      ARM_instruction_vcvt.f32.f64-instruction_handler\r
+       db      'vcvt~~.f32.s16',0x00\r
+       dw      ARM_instruction_vcvt.f32.s16-instruction_handler\r
+       db      'vcvt~~.f32.s32',0x00\r
+       dw      ARM_instruction_vcvt.f32.s32-instruction_handler\r
+       db      'vcvt~~.f32.u16',0x00\r
+       dw      ARM_instruction_vcvt.f32.u16-instruction_handler\r
+       db      'vcvt~~.f32.u32',0x00\r
+       dw      ARM_instruction_vcvt.f32.u32-instruction_handler\r
+       db      'vcvt~~.f64.f32',0x00\r
+       dw      ARM_instruction_vcvt.f64.f32-instruction_handler\r
+       db      'vcvt~~.f64.s16',0x00\r
+       dw      ARM_instruction_vcvt.f64.s16-instruction_handler\r
+       db      'vcvt~~.f64.s32',0x00\r
+       dw      ARM_instruction_vcvt.f64.s32-instruction_handler\r
+       db      'vcvt~~.f64.u16',0x00\r
+       dw      ARM_instruction_vcvt.f64.u16-instruction_handler\r
+       db      'vcvt~~.f64.u32',0x00\r
+       dw      ARM_instruction_vcvt.f64.u32-instruction_handler\r
+       db      'vcvt~~.s16.f32',0x00\r
+       dw      ARM_instruction_vcvt.s16.f32-instruction_handler\r
+       db      'vcvt~~.s16.f64',0x00\r
+       dw      ARM_instruction_vcvt.s16.f64-instruction_handler\r
+       db      'vcvt~~.s32.f32',0x00\r
+       dw      ARM_instruction_vcvt.s32.f32-instruction_handler\r
+       db      'vcvt~~.s32.f64',0x00\r
+       dw      ARM_instruction_vcvt.s32.f64-instruction_handler\r
+       db      'vcvt~~.u16.f32',0x00\r
+       dw      ARM_instruction_vcvt.u16.f32-instruction_handler\r
+       db      'vcvt~~.u16.f64',0x00\r
+       dw      ARM_instruction_vcvt.u16.f64-instruction_handler\r
+       db      'vcvt~~.u32.f32',0x00\r
+       dw      ARM_instruction_vcvt.u32.f32-instruction_handler\r
+       db      'vcvt~~.u32.f64',0x00\r
+       dw      ARM_instruction_vcvt.u32.f64-instruction_handler\r
+       db      'vqrdmulh~~.s16',0x00\r
+       dw      ARM_instruction_vqrdmulh.s16-instruction_handler\r
+       db      'vqrdmulh~~.s32',0x00\r
+       dw      ARM_instruction_vqrdmulh.s32-instruction_handler\r
+       db      'vqrshrun~~.s16',0x00\r
+       dw      ARM_instruction_vqrshrun.s16-instruction_handler\r
+       db      'vqrshrun~~.s32',0x00\r
+       dw      ARM_instruction_vqrshrun.s32-instruction_handler\r
+       db      'vqrshrun~~.s64',0x00\r
+       dw      ARM_instruction_vqrshrun.s64-instruction_handler\r
+       db      'vrinta.f32.f32',0xf0\r
+       dw      ARM_instruction_vrinta.f32.f32-instruction_handler\r
+       db      'vrinta.f64.f64',0xf0\r
+       dw      ARM_instruction_vrinta.f64.f64-instruction_handler\r
+       db      'vrintm.f32.f32',0xf0\r
+       dw      ARM_instruction_vrintm.f32.f32-instruction_handler\r
+       db      'vrintm.f64.f64',0xf0\r
+       dw      ARM_instruction_vrintm.f64.f64-instruction_handler\r
+       db      'vrintn.f32.f32',0xf0\r
+       dw      ARM_instruction_vrintn.f32.f32-instruction_handler\r
+       db      'vrintn.f64.f64',0xf0\r
+       dw      ARM_instruction_vrintn.f64.f64-instruction_handler\r
+       db      'vrintp.f32.f32',0xf0\r
+       dw      ARM_instruction_vrintp.f32.f32-instruction_handler\r
+       db      'vrintp.f64.f64',0xf0\r
+       dw      ARM_instruction_vrintp.f64.f64-instruction_handler\r
+       db      'vrintr.f32.f32',0xe0\r
+       dw      ARM_instruction_vrintr.f32.f32-instruction_handler\r
+       db      'vrintr.f64.f64',0xe0\r
+       dw      ARM_instruction_vrintr.f64.f64-instruction_handler\r
+       db      'vrintx.f32.f32',0xe0\r
+       dw      ARM_instruction_vrintx.f32.f32-instruction_handler\r
+       db      'vrintx.f64.f64',0xe0\r
+       dw      ARM_instruction_vrintx.f64.f64-instruction_handler\r
+       db      'vrintz.f32.f32',0xe0\r
+       dw      ARM_instruction_vrintz.f32.f32-instruction_handler\r
+       db      'vrintz.f64.f64',0xe0\r
+       dw      ARM_instruction_vrintz.f64.f64-instruction_handler\r
+       db      0\r
+instructions_15:\r
+       db      'vcvtb~~.f16.f32',0x00\r
+       dw      ARM_instruction_vcvtb.f16.f32-instruction_handler\r
+       db      'vcvtb~~.f16.f64',0x00\r
+       dw      ARM_instruction_vcvtb.f16.f64-instruction_handler\r
+       db      'vcvtb~~.f32.f16',0x00\r
+       dw      ARM_instruction_vcvtb.f32.f16-instruction_handler\r
+       db      'vcvtb~~.f64.f16',0x00\r
+       dw      ARM_instruction_vcvtb.f64.f16-instruction_handler\r
+       db      'vcvtr~~.s32.f32',0x00\r
+       dw      ARM_instruction_vcvtr.s32.f32-instruction_handler\r
+       db      'vcvtr~~.s32.f64',0x00\r
+       dw      ARM_instruction_vcvtr.s32.f64-instruction_handler\r
+       db      'vcvtr~~.u32.f32',0x00\r
+       dw      ARM_instruction_vcvtr.u32.f32-instruction_handler\r
+       db      'vcvtr~~.u32.f64',0x00\r
+       dw      ARM_instruction_vcvtr.u32.f64-instruction_handler\r
+       db      'vcvtt~~.f16.f32',0x00\r
+       dw      ARM_instruction_vcvtt.f16.f32-instruction_handler\r
+       db      'vcvtt~~.f16.f64',0x00\r
+       dw      ARM_instruction_vcvtt.f16.f64-instruction_handler\r
+       db      'vcvtt~~.f32.f16',0x00\r
+       dw      ARM_instruction_vcvtt.f32.f16-instruction_handler\r
+       db      'vcvtt~~.f64.f16',0x00\r
+       dw      ARM_instruction_vcvtt.f64.f16-instruction_handler\r
+       db      0\r
+instructions_16:\r
+       db      'vrintr~~.f32.f32',0x00\r
+       dw      ARM_instruction_vrintr.f32.f32-instruction_handler\r
+       db      'vrintr~~.f64.f64',0x00\r
+       dw      ARM_instruction_vrintr.f64.f64-instruction_handler\r
+       db      'vrintx~~.f32.f32',0x00\r
+       dw      ARM_instruction_vrintx.f32.f32-instruction_handler\r
+       db      'vrintx~~.f64.f64',0x00\r
+       dw      ARM_instruction_vrintx.f64.f64-instruction_handler\r
+       db      'vrintz~~.f32.f32',0x00\r
+       dw      ARM_instruction_vrintz.f32.f32-instruction_handler\r
+       db      'vrintz~~.f64.f64',0x00\r
+       dw      ARM_instruction_vrintz.f64.f64-instruction_handler\r
+       db      0\r
+instructions_end:\r
+purge dw\r

diff --git a/source/armv8.inc b/source/armv8.inc
new file mode 100644 (file)
index 0000000..5dda0b6
--- /dev/null
+++ b/source/armv8.inc
@@ -0,0 +1,30304 @@
+; NOTE: This software is under the same copyright as FASM with only the\r
+; copyright holder name changed.\r
+\r
+; ARMv8 assembler core module v1.44 for flat assembler,\r
+; Copyright (c) 2005-2023, revolution.\r
+; All rights reserved.\r
+\r
+; This program is free for commercial and non-commercial use as long as\r
+; the following conditions are adhered to.\r
+\r
+; Copyright remains revolution, and as such any Copyright notices\r
+; in the code are not to be removed.\r
+\r
+; Redistribution and use in source and binary forms, with or without\r
+; modification, are permitted provided that the following conditions are\r
+; met:\r
+\r
+; 1. Redistributions of source code must retain the above copyright notice,\r
+;    this list of conditions and the following disclaimer.\r
+; 2. Redistributions in binary form must reproduce the above copyright\r
+;    notice, this list of conditions and the following disclaimer in the\r
+;    documentation and/or other materials provided with the distribution.\r
+\r
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
+; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR\r
+; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
+; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
+; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+; The licence and distribution terms for any publically available\r
+; version or derivative of this code cannot be changed. i.e. this code\r
+; cannot simply be copied and put under another distribution licence\r
+; (including the GNU Public Licence).\r
+\r
+; For best viewing pleasure use a tab stop of 8 characters and fixed\r
+; spacing font\r
+\r
+; Not everything matches the ARM ADS assembly style, where possible the\r
+; original style is used but there are some differences\r
+; 1) label names cannot begin with a digit\r
+; 2) CPSIE and CPSID formats are changed, use "iflags_aif" form instead of\r
+;    "aif" (eg. "CPSIE iflags_i" instead of "CPSID i")\r
+; 3) SRS with writeback must have a separating space after the mode number\r
+;    and before "!" (eg. "SRSDB 16 !" instead of "SRSDB 16!")\r
+; 4) macro, rept, irp, format, if, virtual etc. are all significant changes\r
+;    from the ARM ADS, so you will need to re-write those sections of\r
+;    existing code\r
+\r
+ARM_VERSION_STRING equ "1.44"\r
+ARM_VERSION_MAJOR = 1\r
+ARM_VERSION_MINOR = 44\r
+\r
+;outline of [code_type] bits\r
+\r
+CPU_ACTIVITY_THUMB_NON_UAL     = 1 shl 1       ;1 for THUMB_NON_UAL mode, 0 for ARM or THUMB_UAL mode\r
+CPU_ACTIVITY_THUMB_UAL         = 1 shl 2       ;1 for THUMB_UAL mode, 0 for ARM or THUMB_NON_UAL mode\r
+CPU_ACTIVITY_ARM               = 1 shl 3       ;1 for ARM mode, 0 for THUMB_NON_UAL or THUMB_UAL mode\r
+CPU_ACTIVITY_UNKNOWN           = 1 shl 4       ;this the default at startup\r
+CPU_ACTIVITY_THUMBEE           = 1 shl 5       ;1 for THUMBEE mode when CPU_ACTIVITY_THUMB_UAL is active\r
+CPU_ACTIVITY_ARM64             = 1 shl 6       ;1 for ARM64 code\r
+\r
+CPU32_CAPABILITY_26BIT         = 0\r
+CPU32_CAPABILITY_V1            = 1\r
+CPU32_CAPABILITY_V2            = 2\r
+CPU32_CAPABILITY_A             = 3\r
+CPU32_CAPABILITY_V3            = 4\r
+CPU32_CAPABILITY_M             = 5\r
+CPU32_CAPABILITY_V4            = 6\r
+CPU32_CAPABILITY_V4T           = 7\r
+CPU32_CAPABILITY_V5            = 8\r
+CPU32_CAPABILITY_V5T           = 9\r
+CPU32_CAPABILITY_E             = 10\r
+CPU32_CAPABILITY_P             = 11\r
+CPU32_CAPABILITY_J             = 12\r
+CPU32_CAPABILITY_X             = 13\r
+CPU32_CAPABILITY_V6            = 14\r
+CPU32_CAPABILITY_V6T           = 15\r
+CPU32_CAPABILITY_ALIGN         = 16\r
+CPU32_CAPABILITY_K             = 17\r
+CPU32_CAPABILITY_Z             = 18\r
+CPU32_CAPABILITY_6M            = 19\r
+CPU32_CAPABILITY_7M            = 20\r
+CPU32_CAPABILITY_T2            = 21\r
+CPU32_CAPABILITY_V7            = 22\r
+CPU32_CAPABILITY_SYNC          = 23\r
+CPU32_CAPABILITY_DIV           = 24\r
+CPU32_CAPABILITY_T2EE          = 25\r
+CPU32_CAPABILITY_MP            = 26\r
+CPU32_CAPABILITY_VE            = 27\r
+CPU32_CAPABILITY_V8            = 28    ;v8 instructions in ARM32 and THUMB modes\r
+CPU32_CAPABILITY_CRC           = 29    ;CRC instructions in ARM32 and THUMB modes\r
+\r
+COPRO_CAPABILITY_FPA_V1                = 0\r
+COPRO_CAPABILITY_FPA_V2                = 1\r
+COPRO_CAPABILITY_MAVERICK      = 2\r
+COPRO_CAPABILITY_VFP_V1xD      = 3\r
+COPRO_CAPABILITY_VFP_V1                = 4\r
+COPRO_CAPABILITY_VFP_V2                = 5\r
+COPRO_CAPABILITY_VFP_V3                = 6\r
+COPRO_CAPABILITY_VFP_D32       = 7\r
+COPRO_CAPABILITY_VFP_HP                = 8\r
+COPRO_CAPABILITY_XSCALE                = 9\r
+COPRO_CAPABILITY_IWMMXT_V1     = 10\r
+COPRO_CAPABILITY_IWMMXT_V2     = 11\r
+COPRO_CAPABILITY_SIMD_INT      = 12\r
+COPRO_CAPABILITY_SIMD_FLOAT    = 13\r
+COPRO_CAPABILITY_SIMD_HP       = 14\r
+COPRO_CAPABILITY_VFP_V4                = 15\r
+COPRO_CAPABILITY_SIMD_V2       = 16\r
+COPRO_CAPABILITY_SIMD_V8       = 17\r
+COPRO_CAPABILITY_SIMD_CRYPTO   = 18\r
+\r
+CPU_CAPABILITY_DEFAULT         =\\r
+                               1 shl CPU32_CAPABILITY_26BIT +\\r
+                               1 shl CPU32_CAPABILITY_V1 +\\r
+                               1 shl CPU32_CAPABILITY_V2 +\\r
+                               1 shl CPU32_CAPABILITY_A +\\r
+                               1 shl CPU32_CAPABILITY_V3 +\\r
+                               1 shl CPU32_CAPABILITY_M +\\r
+                               1 shl CPU32_CAPABILITY_V4 +\\r
+                               1 shl CPU32_CAPABILITY_V4T +\\r
+                               1 shl CPU32_CAPABILITY_V5 +\\r
+                               1 shl CPU32_CAPABILITY_V5T +\\r
+                               1 shl CPU32_CAPABILITY_E +\\r
+                               1 shl CPU32_CAPABILITY_P +\\r
+                               1 shl CPU32_CAPABILITY_J +\\r
+                               1 shl CPU32_CAPABILITY_X +\\r
+                               1 shl CPU32_CAPABILITY_V6 +\\r
+                               1 shl CPU32_CAPABILITY_V6T +\\r
+                               1 shl CPU32_CAPABILITY_ALIGN +\\r
+                               1 shl CPU32_CAPABILITY_K +\\r
+                               1 shl CPU32_CAPABILITY_Z +\\r
+                               1 shl CPU32_CAPABILITY_6M +\\r
+                               1 shl CPU32_CAPABILITY_7M +\\r
+                               1 shl CPU32_CAPABILITY_T2 +\\r
+                               1 shl CPU32_CAPABILITY_V7 +\\r
+                               1 shl CPU32_CAPABILITY_SYNC +\\r
+                               1 shl CPU32_CAPABILITY_DIV +\\r
+                               1 shl CPU32_CAPABILITY_T2EE +\\r
+                               1 shl CPU32_CAPABILITY_MP +\\r
+                               1 shl CPU32_CAPABILITY_VE +\\r
+                               1 shl CPU32_CAPABILITY_V8 +\\r
+                               1 shl CPU32_CAPABILITY_CRC\r
+\r
+COPRO_CAPABILITY_DEFAULT       =\\r
+                               1 shl COPRO_CAPABILITY_FPA_V1 +\\r
+                               1 shl COPRO_CAPABILITY_FPA_V2 +\\r
+                               1 shl COPRO_CAPABILITY_MAVERICK +\\r
+                               1 shl COPRO_CAPABILITY_VFP_V1xD +\\r
+                               1 shl COPRO_CAPABILITY_VFP_V1 +\\r
+                               1 shl COPRO_CAPABILITY_VFP_V2 +\\r
+                               1 shl COPRO_CAPABILITY_VFP_V3 +\\r
+                               1 shl COPRO_CAPABILITY_VFP_D32 +\\r
+                               1 shl COPRO_CAPABILITY_VFP_HP +\\r
+                               1 shl COPRO_CAPABILITY_XSCALE +\\r
+                               1 shl COPRO_CAPABILITY_IWMMXT_V1 +\\r
+                               1 shl COPRO_CAPABILITY_IWMMXT_V2 +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_INT +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_FLOAT +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_HP +\\r
+                               1 shl COPRO_CAPABILITY_VFP_V4 +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_V2 +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_V8 +\\r
+                               1 shl COPRO_CAPABILITY_SIMD_CRYPTO\r
+\r
+CPU64_CAPABILITY_V8            = 32                            ;v8 instructions in ARM64 mode\r
+CPU64_CAPABILITY_FP            = CPU64_CAPABILITY_V8 + 1       ;floating point instructions in ARM64 mode\r
+CPU64_CAPABILITY_SIMD          = CPU64_CAPABILITY_FP + 1       ;SIMD instructions in ARM64 mode\r
+CPU64_CAPABILITY_CRC           = CPU64_CAPABILITY_SIMD + 1     ;CRC instructions in ARM64 mode\r
+CPU64_CAPABILITY_CRYPTO                = CPU64_CAPABILITY_CRC + 1      ;cryptography instructions in ARM64 mode\r
+\r
+CPU32_CAPABILITY_ALL           = CPU_CAPABILITY_DEFAULT\r
+COPRO_CAPABILITY_ALL           = COPRO_CAPABILITY_DEFAULT\r
+CPU64_CAPABILITY_ALL           =\\r
+                               1 shl CPU64_CAPABILITY_V8 +\\r
+                               1 shl CPU64_CAPABILITY_FP +\\r
+                               1 shl CPU64_CAPABILITY_SIMD +\\r
+                               1 shl CPU64_CAPABILITY_CRC +\\r
+                               1 shl CPU64_CAPABILITY_CRYPTO\r
+\r
+ARM_code                       = CPU_ACTIVITY_ARM\r
+\r
+FLAG_BIT_CONDITION_SET         = 0\r
+FLAG_BIT_FORCE_WIDE            = 1\r
+FLAG_BIT_FORCE_NARROW          = 2\r
+FLAG_BIT_FORCE_AUTO_WIDE       = 3\r
+\r
+FLAG_CONDITION_SET             = 1 shl FLAG_BIT_CONDITION_SET\r
+FLAG_FORCE_WIDE                        = 1 shl FLAG_BIT_FORCE_WIDE\r
+FLAG_FORCE_NARROW              = 1 shl FLAG_BIT_FORCE_NARROW\r
+FLAG_FORCE_AUTO_WIDE           = 1 shl FLAG_BIT_FORCE_AUTO_WIDE\r
+\r
+CONDITION_SEARCH_CHARACTER     = '~'\r
+\r
+;undefined instruction space, we use this for triggering unencodable instructions\r
+;xxxx_0111_1111_xxxx_xxxx_xxxx_1111_xxxx  x7fxxxfx arm\r
+\r
+UNENCODEABLE_INSTRUCTION_ARM   = 0xf7ffffff\r
+\r
+THUMB_FLAG_NOT_INSIDE_IT       = 1 shl 0       ;not allowable inside an IT block\r
+THUMB_FLAG_ONLY_INSIDE_IT      = 1 shl 1       ;only allowable inside an IT block\r
+THUMB_FLAG_ONLY_LAST_IT                = 1 shl 2       ;only allowable as last instruction of an IT block\r
+THUMB_FLAG_IS_BCC              = 1 shl 3       ;special Bcc opcodes are conditional but exist outside an IT block\r
+\r
+ARM_INSTRUCTION_OPCODE_AND     = 0000b\r
+ARM_INSTRUCTION_OPCODE_EOR     = 0001b\r
+ARM_INSTRUCTION_OPCODE_SUB     = 0010b\r
+ARM_INSTRUCTION_OPCODE_RSB     = 0011b\r
+ARM_INSTRUCTION_OPCODE_ADD     = 0100b\r
+ARM_INSTRUCTION_OPCODE_ADC     = 0101b\r
+ARM_INSTRUCTION_OPCODE_SBC     = 0110b\r
+ARM_INSTRUCTION_OPCODE_RSC     = 0111b\r
+ARM_INSTRUCTION_OPCODE_TST     = 1000b\r
+ARM_INSTRUCTION_OPCODE_TEQ     = 1001b\r
+ARM_INSTRUCTION_OPCODE_CMP     = 1010b\r
+ARM_INSTRUCTION_OPCODE_CMN     = 1011b\r
+ARM_INSTRUCTION_OPCODE_ORR     = 1100b\r
+ARM_INSTRUCTION_OPCODE_MOV     = 1101b\r
+ARM_INSTRUCTION_OPCODE_BIC     = 1110b\r
+ARM_INSTRUCTION_OPCODE_MVN     = 1111b\r
+\r
+ARM_SHIFT_OPCODE_LSL   = 0\r
+ARM_SHIFT_OPCODE_LSR   = 1\r
+ARM_SHIFT_OPCODE_ASR   = 2\r
+ARM_SHIFT_OPCODE_ROR   = 3\r
+\r
+THUMB_INSTRUCTION_OPCODE_AND   = 0000b\r
+THUMB_INSTRUCTION_OPCODE_EOR   = 0001b\r
+THUMB_INSTRUCTION_OPCODE_LSL   = 0010b\r
+THUMB_INSTRUCTION_OPCODE_LSR   = 0011b\r
+THUMB_INSTRUCTION_OPCODE_ASR   = 0100b\r
+THUMB_INSTRUCTION_OPCODE_ADC   = 0101b\r
+THUMB_INSTRUCTION_OPCODE_SBC   = 0110b\r
+THUMB_INSTRUCTION_OPCODE_ROR   = 0111b\r
+THUMB_INSTRUCTION_OPCODE_TST   = 1000b\r
+THUMB_INSTRUCTION_OPCODE_NEG   = 1001b\r
+THUMB_INSTRUCTION_OPCODE_CMP   = 1010b\r
+THUMB_INSTRUCTION_OPCODE_CMN   = 1011b\r
+THUMB_INSTRUCTION_OPCODE_ORR   = 1100b\r
+THUMB_INSTRUCTION_OPCODE_MUL   = 1101b\r
+THUMB_INSTRUCTION_OPCODE_BIC   = 1110b\r
+THUMB_INSTRUCTION_OPCODE_MVN   = 1111b\r
+\r
+SIMD_REG_LIST_TYPE_REGISTER    = 0                     ;dy\r
+SIMD_REG_LIST_TYPE_ELEMENT     = 1                     ;dy[x]\r
+SIMD_REG_LIST_TYPE_VECTOR      = 2                     ;dy[]\r
+\r
+IT_MODE_AUTO                   = 1\r
+\r
+;conditions for choosing 16 bit thumb when two options are available:\r
+;      OPs     reg,...         - always encoded as short unless forced by a condition or explicit IT block\r
+;      OP      reg,...         - default encoded as long. If the preceeding instruction was the same type,\r
+;                                then if the preceeding instruction was encoded as long we recode it as\r
+;                                short+short (IT + movs reg1,reg2 i.e. to begin the IT block), or if there\r
+;                                are still remaining slots available in a previous IT block, then we encode\r
+;                                this instruction as short (movs reg1,reg2) and extend the previous IT block.\r
+\r
+       ;renamed variables in X86_64\r
+label force_wide_flag          dword at address_high\r
+label IT_anchor_distance        byte at segment_register\r
+       ;renamed variables in preprocessor for our use\r
+label potential_IT_anchor      dword at macro_line\r
+label explicit_IT_state                dword at macro_block\r
+label current_IT_block         dword at macro_block_line\r
+label thumb32_error            dword at macro_block_line_number\r
+label thumb16_error            dword at macro_symbols\r
+label thumb32_instruction      dword at struc_name\r
+      arm64_instruction                     equ thumb32_instruction\r
+label thumb16_instruction       word at struc_label\r
+label anchor_instruction        word at struc_label+2\r
+label arm_instruction          dword at instant_macro_start\r
+      arm64_instruction2            equ arm_instruction\r
+label reg_list_bitmap          dword at parameters_end\r
+  label simd_reg_list_first     byte at parameters_end+0\r
+  label simd_reg_list_count     byte at parameters_end+1\r
+  label simd_reg_list_x                 byte at parameters_end+2\r
+  label simd_reg_list_type      byte at parameters_end+3\r
+label operand_registers                dword at locals_counter\r
+  label operand_register0       byte at locals_counter+0\r
+  label operand_register1       byte at locals_counter+1\r
+  label operand_register2       byte at locals_counter+2\r
+  label operand_register3       byte at locals_counter+3\r
+  label instruction_condition   byte at locals_counter+4\r
+  label instruction_shift_op    byte at locals_counter+5\r
+  label        copro_opcode1            byte at locals_counter+6\r
+  label        copro_opcode2            byte at locals_counter+7\r
+label cpu_capability_flags2    dword at default_argument_value\r
+label immediate_value_high     dword at initial_definitions\r
+label it_control                byte at macro_status\r
+       ;renamed variables in parser for our use\r
+label immediate_value          dword at current_locals_prefix\r
+label immediate_value2         dword at anonymous_reverse\r
+  label current_reg_number      byte at anonymous_forward+0\r
+  label current_parameter       byte at anonymous_forward+1\r
+  label        thumb_flags_16           byte at anonymous_forward+2\r
+  label        thumb_flags_32           byte at anonymous_forward+3\r
+label cpu_capability_flags     dword at label_hash\r
+label copro_capability_flags   dword at label_leaf\r
+label ARM_error_line           dword at parsed_lines\r
+       ;renamed variables in AVX for our use\r
+label first_global_symbol      dword at uncompressed_displacement\r
+       ;renamed variables in x64 for our use\r
+label can_swap_rm_rn            byte at rex_prefix\r
+\r
+irpv any, esp {\r
+       irp reg,ax,bx,cx,dx,si,di,sp,bp \{ v\#reg equ r\#reg \}\r
+       __is_64 = 1\r
+rept 0 {} rept 1 {\r
+       irp reg,ax,bx,cx,dx,si,di,sp,bp \{ v\#reg equ e\#reg \}\r
+       __is_64 = 0\r
+       ;remove this macro if you want to drop support for processors that don't have CMOVcc\r
+       irp cc,a,ae,b,be,c,e,g,ge,l,le,na,nae,nb,nbe,nc,ne,ng,nge,nl,nle,no,np,ns,nz,o,p,pe,po,s,z \{\r
+               local i\r
+               macro cmov#cc [args] \\{\r
+                   \\common\r
+                   \\local .x\r
+                       j#cc    .x\r
+                       load    i from $-2\r
+                       store   (i xor 1) at $-2\r
+                       mov     args\r
+                   .x:\r
+               \\}\r
+       \}\r
+}\r
+\r
+patch_error_displayed = 0\r
+macro patch labl,instr_search,instr_replace,offset {\r
+       local expecting, length, new, a, b\r
+       macro display_nibble value \{\r
+               local nibble\r
+               nibble=(value) and 0fh + '0'\r
+               if nibble > '9'\r
+                       nibble=nibble - '9' - 1 + 'a'\r
+               end if\r
+               display nibble\r
+       \}\r
+       macro display_hex prefix, address, length \{\r
+               display prefix\r
+               while % <= length\r
+                       load a byte from address + % - 1\r
+                       display_nibble a shr 4\r
+                       display_nibble a\r
+                       display ' '\r
+               end while\r
+               display 13, 10\r
+       \}\r
+       virtual at labl + offset\r
+               expecting::\r
+               irp i,instr_search\{i\}\r
+               length = $ - $$\r
+       end virtual\r
+       virtual at labl + offset\r
+               new::\r
+               irp i,instr_replace\{i\}\r
+               if $ - $$ <= length\r
+                       times (length + $$ - $) nop\r
+               else\r
+                       if ~ patch_error_displayed\r
+                               display $ - $$ - length + '0', " too many bytes", 13, 10\r
+                               patch_error_displayed = 1\r
+                               rb -1 ; "Instruction patch is too long"\r
+                       end if\r
+               end if\r
+       end virtual\r
+       while % <= length\r
+               load a byte from labl + offset + % - 1\r
+               load b byte from expecting:labl + offset + % - 1\r
+               if a <> b\r
+                       if ~ patch_error_displayed\r
+                               display_hex '-16: ', labl + offset - 16, 16\r
+                               display_hex '+00: ', labl + offset + 00, 16\r
+                               display_hex '+16: ', labl + offset + 16, 16\r
+                               display_hex 'this ', expecting:labl + offset, length\r
+                               patch_error_displayed = 1\r
+                               rb -1 ; "Mismatched instructions for patch"\r
+                       end if\r
+               end if\r
+       end while\r
+       while % <= length\r
+               load a byte from new:labl + offset + % - 1\r
+               store byte a at labl + offset + % - 1\r
+       end while\r
+       purge display_nibble, display_hex\r
+}\r
+\r
+macro override labl, instr {\r
+       local new, length, a\r
+       virtual at labl\r
+               new::\r
+               irp i,instr{i\}\r
+               length = $ - $$\r
+       end virtual\r
+       while % <= length\r
+               load a byte from new:labl + % - 1\r
+               store byte a at labl + % - 1\r
+       end while\r
+}\r
+\r
+;All patches are done here\r
+\r
+;patch to add FIT operator\r
+\r
+       patch calculation_loop, <je calculate_not>, <call ARM_fit_operator>, 123 + __is_64 * 2\r
+\r
+;patches to add PROCESSOR operator\r
+\r
+       patch parse_instruction_arguments,\\r
+                               <<cmp bx,prefix_instruction-instruction_handler>,je allow_embedded_instruction>,\\r
+                                                            <call ARM_processor_directives>,           0\r
+       patch parse_argument,   <<cmp al,'-'>,je separator>, <jmp ARM_parse_processor_separators>,      160 + __is_64 * 2\r
+       patch operator_argument,<jmp argument_parsed>,       <jmp ARM_check_operator>,                  58 + __is_64 * 8\r
+       patch negation_ok,      <je check_for_used>,         <call ARM_check_processor>,                37 + __is_64 * 8\r
+\r
+;patches to save IT data inside virtual blocks\r
+\r
+       patch addressing_space_extension_ok,    <jmp instruction_assembled>, <jmp ARM_set_virtual>,  60 + __is_64 * 24\r
+       patch continue_virtual_area,            <jmp instruction_assembled>, <jmp ARM_set_virtual>,  182 + __is_64 * 46\r
+       patch end_virtual,                      <call find_structure_data>,  <call ARM_end_virtual>, 0\r
+\r
+;patch to inhibit IT block generation across labels\r
+\r
+       patch assemble_line, <jb define_label>, <jb ARM_define_label>, 35 + __is_64 * 2\r
+\r
+;two patches to catch the format arguments\r
+\r
+       patch parse_instruction_arguments,<<cmp bx,section_directive-instruction_handler>>,<<cmp bx,ARM_section_directive-instruction_handler>>,88\r
+       patch parse_instruction_arguments,<<cmp bx,format_directive-instruction_handler>>,<<cmp bx,ARM_format_directive-instruction_handler>>,95\r
+\r
+;three patches for ELF format\r
+\r
+       patch format_elf, \\r
+               <<mov al,1>, \\r
+                       <mov [edx+4],al>, \\r
+                       <mov [edx+5],al>, \\r
+                       <mov [edx+6],al>, \\r
+                       <mov [edx+14h],al>, \\r
+                       <mov byte[edx+12h],3>, \\r
+                       <mov byte[edx+28h],34h>>, \\r
+               <<mov dword[edx+4],0x00010101>, \\r
+                       <mov byte[edx+14h],1>, \\r
+                       <mov byte[edx+12h],40>, \\r
+                       <mov word[edx+27h],3405h>>, \\r
+               48 + __is_64 * 3\r
+       patch format_elf, <<mov [code_type],32>>, <<mov [code_type],ARM_code>>, 74 + __is_64 * 10       ;CODE32\r
+       patch format_elf64, \\r
+               <<mov al,1>, \\r
+                       <mov [edx+5],al>, \\r
+                       <mov [edx+6],al>, \\r
+                       <mov [edx+14h],al>, \\r
+                       <mov byte[edx+4],2>, \\r
+                       <mov byte[edx+12h],62>, \\r
+                       <mov byte[edx+34h],40h>>, \\r
+               <<mov dword[edx+4],0x00010102>, \\r
+                       <mov byte[edx+14h],1>, \\r
+                       <mov byte[edx+12h],0xb7>, \\r
+                       <mov word[edx+33h],4005h>>, \\r
+               32 + __is_64 * 3\r
+       patch elf_exe_brand_ok, <<mov [image_base],8048000h>>, <<mov [image_base],8000h>>, 0\r
+\r
+;nine patches for PE format\r
+\r
+       patch format_pe,        <<mov [machine],14Ch>>,                  <<mov [machine],1C0h>>,          2   ;ARM\r
+       patch format_pe,        <<mov [subsystem],3>>,                   <<mov [subsystem],9>>,           11  ;WinCE\r
+       patch format_pe,        <<mov [subsystem_version],3+10 shl 16>>, <<mov [subsystem_version],3>>,   20  ;3.0\r
+       patch format_pe,        <<mov [image_base],400000h>>,            <<mov [image_base],10000h>>,     30\r
+       patch pe_settings,      <<mov [machine],8664h>>,                 <<mov [machine],0xaa64>>,       -19\r
+       patch init_peplus_specific,<<mov dword[edx+16h],20B002Fh>>,      <<mov dword[edx+16h],20B0022h>>, 4 + __is_64\r
+       patch pe_org_ok,        <<mov [code_type],32>>,                  <<mov [code_type],ARM_code>>,    14  ;CODE32\r
+       patch new_section,      <<mov [code_type],32>>,                  <<mov [code_type],ARM_code>>,    83 + __is_64 * 31  ;CODE32\r
+       patch pe_alignment_ok,  <<mov word [edx+1Ah],VERSION_MAJOR + VERSION_MINOR shl 8>>,\\r
+                               <<mov word [edx+1Ah],ARM_VERSION_MAJOR + ARM_VERSION_MINOR shl 8>>, 0\r
+\r
+;three patches to allow {} around register lists and custom address formats\r
+\r
+       patch parse_argument, <<cmp al,'['>,je address_argument>,    <<cmp al,'['>,je ARM_square_parser>, 99 + __is_64 * 2\r
+       patch parse_argument, <<cmp al,'{'>,je open_decorator>,      <<cmp al,'{'>,je ARM_curly_parser>,  115 + __is_64 * 2\r
+       patch parse_argument, <<cmp al,'#'>,je unallowed_character>, <<cmp al,'#'>,je separator>,         131 + __is_64 * 2\r
+\r
+;a patch for setting the alignment bytes to 0xff\r
+\r
+       patch nops, <<mov eax,90909090h>>, <<mov eax,-1>>, 0\r
+\r
+;patch to give us control when the code stream has finished being assembled\r
+\r
+       macro finish_elf_exe_patch_code { mov ebx,[number_of_sections] }\r
+       patch finish_elf_segment, finish_elf_exe_patch_code, jmp ARM_finish_elf_segment, 0\r
+\r
+;patch the reset state at beginning of assembly passes\r
+\r
+       patch pass_loop, <call assemble_line>, <call ARM_assemble_line>, 0\r
+\r
+;patch to allow alternative half-precision number range\r
+\r
+       patch fp_word_ok, <jge value_out_of_range>, <jg value_out_of_range>, 8\r
+\r
+;patch to use a custom instruction searcher to convert '~~' to conditionals\r
+\r
+       override get_instruction, jmp ARM_get_instruction\r
+\r
+;patch to allow skipping of commas inside address expressions\r
+\r
+       override skip_address, jmp skip_done\r
+\r
+;patch to allow %p and %c predefined variables\r
+\r
+       override get_predefined_id, jmp ARM_get_predefined_id   ;in PARSER.INC\r
+       override predefined_label, jmp ARM_predefined_label     ;in EXPRCALC.INC\r
+\r
+;patch to use a custom instruction handler to store address of line start\r
+\r
+       override instruction_handler, jmp ARM_instruction_handler\r
+\r
+;patch to disable use of 0x13 as code type setting (this is now a directive)\r
+\r
+       patch assemble_line, <je code_type_setting>, <nop>, 61 + __is_64 * 2\r
+\r
+;patches to recognise base address registers in virtual\r
+\r
+       patch symbol_value,     <<shr ah,4>>,                   <jmp register_value>,           46 + __is_64 * 12\r
+       patch address_size_ok,  <<mov ax,bx>,<shr ah,4>>,       <jmp check_qword_value>,        52 + __is_64 * 5\r
+\r
+;patch to allow for 17 character symbols\r
+\r
+       patch get_symbol, <<cmp cl,11>>,<<cmp cl,17>>,10 + __is_64 * 7\r
+\r
+;seven patches for the IDE caption\r
+\r
+       if defined _caption\r
+\r
+               patch convert_table,            <push _caption>,<call ARM_push_caption>,256\r
+               patch loading_error,            <push _caption>,<call ARM_push_caption>,26\r
+               patch not_enough_mem,           <push _caption>,<call ARM_push_caption>,23\r
+               patch move_file_name,           <push _caption>,<call ARM_push_caption>,76\r
+               patch open_single_file,         <push _caption>,<call ARM_push_caption>,52\r
+               patch run_object,               <push _caption>,<call ARM_push_caption>,2\r
+               patch drop_files,               <push _caption>,<call ARM_push_caption>,102\r
+\r
+               ARM_push_caption:\r
+                       mov     eax,_logo\r
+                       xchg    eax,[esp]\r
+                       jmp     vax\r
+\r
+       end if\r
+\r
+;patch the error_summary_dialog to show the full error message by wrapping the text\r
+\r
+macro dialogitem class,title,id,x,y,cx,cy,style,exstyle {\r
+       if (style) and SS_LEFTNOWORDWRAP = SS_LEFTNOWORDWRAP            ;check for error_summary_dialog message item\r
+                       dialogitem class,<title>,id,x,y-5,cx,cy+16,(style) and (not SS_LEFTNOWORDWRAP),exstyle\r
+       else\r
+                       dialogitem class,<title>,id,x,y,cx,cy,style,exstyle\r
+       end if\r
+}\r
+\r
+;ARM, ARM64, THUMB and THUMB_T2 encodings are sufficiently different that we use separate decoding code for each.\r
+;The basic premise is that we decode all three together as much a possible using the templates.\r
+;We decode the parameters and then split into each separate encoder once basic syntax checks are passed.\r
+;Once split off, specific invalid encodings are checked by each encoder.\r
+;\r
+;In T2 mode, the IT instruction is checked by a common handler function and it is possible that previous\r
+;instructions will be recoded if IT prediction was sub-optimal or invalid.\r
+\r
+;decoder template definitions:\r
+\r
+align 4\r
+\r
+struc make_template_entry [name] {\r
+    common\r
+       local counter\r
+       counter = 0\r
+    forward\r
+       dd decode_template.#name\r
+       name = counter\r
+       counter = counter + 1\r
+}\r
+\r
+template_decode_table make_template_entry \\r
+       TMPL_modifier_exclaim   ,\;'!'\r
+       TMPL_modifier_translate ,\;'^'\r
+       TMPL_cpu_sel            ,\;cpu32_*, cpu64_*\r
+       TMPL_copro_sel          ,\;copro32_\r
+       TMPL_copro_opcode1      ,\;imm\r
+       TMPL_copro_opcode2      ,\;imm\r
+       TMPL_EOL                ,\;0xf\r
+       TMPL_base_reg           ,\;r0-r15\r
+       TMPL_base_reg!          ,\;r0!-r15!\r
+       TMPL_cpro_sel           ,\;p0-p15\r
+       TMPL_cpro_reg           ,\;c0-c15\r
+       TMPL_endian             ,\;le,be\r
+       TMPL_shift_op           ,\;lsl,lsr,asr,ror\r
+       TMPL_shift_op3          ,\;lsl,lsr,asr\r
+       TMPL_rrx_op             ,\;rrx\r
+       TMPL_lsl                ,\;lsl\r
+       TMPL_msl                ,\;msl\r
+       TMPL_vfps_reg           ,\;s0-s31\r
+       TMPL_vfpd_reg           ,\;d0-d31\r
+       TMPL_acc_40bt           ,\;acc0-acc7\r
+       TMPL_vfp_syst           ,\;vfp_syst\r
+       TMPL_iflags             ,\;iflags_*\r
+       TMPL_psr                ,\;cpsr_*,spsr_*\r
+       TMPL_imm                ,\;'('\r
+       TMPL_imm2               ,\;'('\r
+       TMPL_imm64              ,\;64-bit immediates\r
+       TMPL_bracket_left       ,\;'['\r
+       TMPL_bracket_right      ,\;']'\r
+       TMPL_reg_list           ,\;'{..}'\r
+       TMPL_vfp_reg_list_s     ,\;'{..}'\r
+       TMPL_vfp_reg_list_d     ,\;'{..}'\r
+       TMPL_add_sub_reg        ,\;-rm, +rm\r
+       TMPL_expression         ,\;implicit or explicit reg + offset\r
+       TMPL_address            ,\;code address immediate\r
+       TMPL_address64          ,\;64-bit code address immediate\r
+       TMPL_option             ,\;{imm}\r
+       TMPL_comma              ,\;,\r
+       TMPL_iwmmx_wreg         ,\;wr0-wr15\r
+       TMPL_iwmmx_creg         ,\;iwmmx_creg\r
+       TMPL_mvrk_areg          ,\;a0-a3\r
+       TMPL_mvrk_psc           ,\;dspsc\r
+       TMPL_fpa_freg           ,\;f0-f7\r
+       TMPL_imm_float          ,\;float\r
+       TMPL_barrier            ,\;barrier\r
+       TMPL_condition          ,\;conditions\r
+       TMPL_condition_nv       ,\;conditions with nv\r
+       TMPL_simd_qreg          ,\;q0-q15\r
+       TMPL_vfpdx_reg          ,\;d0[x]-d31[x] x=0-7\r
+       TMPL_simd_reg_list      ,\;{d0,d1,...}, {d0,d2,...}, {d0[x],d1[x],...}, {d0[x],d2[x],...}, {d0[],d1[],...}, {d0[],d2[],...}\r
+       TMPL_address_reg@       ,\;r0@x-r15@x\r
+       TMPL_sysm_reg           ,\;apsr, iapsr, eapsr, xpsr, ipsr, epsr, iepsr, msp, psp, primask, basepri, basepri_max, faultmask, control\r
+       TMPL_banked_reg         ,\;banked registers for MSR/MRS access\r
+       TMPL_word_z_reg         ,\;32-bit w0-w30,wzr\r
+       TMPL_word_s_reg         ,\;32-bit w0-w30,wsp\r
+       TMPL_dword_z_reg        ,\;64-bit x0-x30,xzr\r
+       TMPL_dword_s_reg        ,\;64-bit x0-x30,sp\r
+       TMPL_word_gen_reg       ,\;32-bit w0-w30\r
+       TMPL_word_zr_reg        ,\;32-bit wzr\r
+       TMPL_word_sp_reg        ,\;32-bit wsp\r
+       TMPL_dword_gen_reg      ,\;64-bit x0-x30\r
+       TMPL_dword_zr_reg       ,\;64-bit xzr\r
+       TMPL_dword_sp_reg       ,\;64-bit sp\r
+       TMPL_vect_breg          ,\;b0-b31\r
+       TMPL_vect_hreg          ,\;h0-h31\r
+       TMPL_vect_sreg          ,\;s0-s31\r
+       TMPL_vect_dreg          ,\;d0-d31\r
+       TMPL_vect_qreg          ,\;q0-q31\r
+       TMPL_vect_v8b           ,\;v0.8b-v31.8b\r
+       TMPL_vect_v16b          ,\;v0.16b-v31.16b\r
+       TMPL_vect_v4h           ,\;v0.4h-v31.4h\r
+       TMPL_vect_v8h           ,\;v0.8h-v31.8h\r
+       TMPL_vect_v2s           ,\;v0.2s-v31.2s\r
+       TMPL_vect_v4s           ,\;v0.4s-v31.4s\r
+       TMPL_vect_v1d           ,\;v0.1d-v31.1d\r
+       TMPL_vect_v2d           ,\;v0.2d-v31.2d\r
+       TMPL_vect_v1q           ,\;v0.1q-v31.1q\r
+       TMPL_extend             ,\;[su]xt[]bhwx]\r
+       TMPL_always             ,\;always match everything\r
+       TMPL_never              ,\;never match anything\r
+       TMPL_at_op              ,\;at ops\r
+       TMPL_dc_op              ,\;dc ops\r
+       TMPL_ic_op              ,\;ic ops\r
+       TMPL_tlbi_op            ,\;tlbi ops\r
+       TMPL_prf_op             ,\;pldl1keep-pstl3strm\r
+       TMPL_msr_reg            ,\;msr registers\r
+       TMPL_pstate_reg         ,\;pstate registers\r
+       TMPL_sysreg_dynamic     ,\;s<op0>_<op1>_<Cn>_<Cm>_<op2> registers\r
+       TMPL_vect_element_b     ,\;v0.b[imm]-v31.b[imm]\r
+       TMPL_vect_element_h     ,\;v0.h[imm]-v31.h[imm]\r
+       TMPL_vect_element_s     ,\;v0.s[imm]-v31.s[imm]\r
+       TMPL_vect_element_d     ,\;v0.d[imm]-v31.d[imm]\r
+       TMPL_vect_list_8b       ,\;{v.8b,...}\r
+       TMPL_vect_list_16b      ,\;{v.16b,...}\r
+       TMPL_vect_list_4h       ,\;{v.4h,...}\r
+       TMPL_vect_list_8h       ,\;{v.8h,...}\r
+       TMPL_vect_list_2s       ,\;{v.2s,...}\r
+       TMPL_vect_list_4s       ,\;{v.4s,...}\r
+       TMPL_vect_list_1d       ,\;{v.1d,...}\r
+       TMPL_vect_list_2d       ,\;{v.2d,...}\r
+       TMPL_vect_list_vb       ,\;{v0.b}[imm]-{v31.b}[imm]\r
+       TMPL_vect_list_vh       ,\;{v0.b}[imm]-{v31.b}[imm]\r
+       TMPL_vect_list_vs       ,\;{v0.b}[imm]-{v31.b}[imm]\r
+       TMPL_vect_list_vd       ,\;{v0.b}[imm]-{v31.b}[imm]\r
+       TMPL_size_1             ,\;set operand_size to byte\r
+       TMPL_size_2             ,\;set operand_size to hword\r
+       TMPL_size_4             ,\;set operand_size to word\r
+       TMPL_size_8             ,\;set operand_size to dword\r
+       TMPL_size_16            ,\;set operand_size to qword\r
+       TMPL_size_32              ;set operand_size to dqword\r
+\r
+restruc make_template_entry\r
+\r
+TEMPLATE_maximum_operand= 9\r
+TEMPLATE_length                = TEMPLATE_maximum_operand\r
+\r
+macro TEMPLATE [arg] {\r
+    common\r
+       local .x,.y\r
+       db 0            ;index number of the last template\r
+       .x:\r
+    forward\r
+       .y = $\r
+       irp val,arg \{\r
+               db val\r
+       \}\r
+       db TMPL_EOL\r
+       assert ($-.y) <= TEMPLATE_maximum_operand\r
+       while ($-.y) < TEMPLATE_length\r
+               db -1\r
+       end while\r
+    common\r
+       store byte (($-.x)/TEMPLATE_length)-1 at .x-1\r
+}\r
+\r
+decode_template:\r
+       mov     [instruction_condition],al\r
+       mov     [arm_instruction],edx\r
+       mov     [thumb32_instruction],ecx\r
+       call    ARM_generic_mode_checks\r
+       xor     eax,eax\r
+       mov     [immediate_value_high],eax\r
+       mov     [instruction_shift_op],al\r
+       mov     [current_reg_number],al\r
+       mov     [operand_registers],eax\r
+       mov     [current_parameter],al\r
+       mov     [immediate_value2],eax\r
+       mov     [immediate_value],eax\r
+       mov     [thumb_flags_16],al\r
+       mov     [thumb_flags_32],al\r
+       mov     [copro_opcode1],al\r
+       mov     [copro_opcode2],al\r
+       mov     eax,[esp]                               ;get template definitions\r
+       mov     ebx,0                                   ;ebx=current template definition\r
+       mov     ah,[eax]                                ;ah=highest constraint\r
+       mov     al,0                                    ;al=lowest constriant\r
+    .refine_constraint:\r
+    .refine_lower_constraint:\r
+       movzx   ecx,al\r
+       imul    ecx,ecx,TEMPLATE_length\r
+       add     ecx,[esp]\r
+       lea     ecx,[ecx+ebx+1]\r
+       movzx   ecx,byte[ecx]                           ;ecx=template value\r
+       movzx   eax,ax                                  ;clear the multi-match mask\r
+       push    ebx ecx esi eax\r
+       call    near dword[template_decode_table+ecx*4]\r
+       pop     eax edx ecx ebx\r
+       jnc     .lower_constraint_found\r
+       mov     esi,edx\r
+    .try_next_constraint:\r
+       inc     al\r
+       cmp     al,ah\r
+       ja      .failed\r
+       movzx   edx,al\r
+       imul    edx,edx,TEMPLATE_length\r
+       add     edx,[esp]\r
+       lea     edx,[edx+ebx+1]\r
+       cmp     cl,[edx]\r
+       jz      .try_next_constraint\r
+       jmp     .refine_lower_constraint\r
+    .lower_constraint_found:\r
+       test    eax,0xffff0000\r
+       setnz   ch\r
+       or      cl,ch                                   ;mask off similar matches\r
+    .refine_higher_constraint:\r
+       movzx   edx,ah\r
+       imul    edx,edx,TEMPLATE_length\r
+       add     edx,[esp]\r
+       lea     edx,[edx+ebx+1]\r
+       mov     ch,[edx]\r
+       test    eax,0xffff0000\r
+       setnz   dl\r
+       or      ch,dl                                   ;mask off similar matches\r
+       cmp     cl,ch\r
+       jz      .higher_constraint_found\r
+       dec     ah\r
+       cmp     ah,al\r
+       jb      .failed\r
+       jmp     .refine_higher_constraint\r
+    .higher_constraint_found:\r
+    .next_parameter:\r
+       cmp     cl,TMPL_EOL\r
+       jz      .end_of_line\r
+       inc     bl\r
+       cmp     bl,TEMPLATE_maximum_operand\r
+       jb      .refine_constraint\r
+       cmp     byte[esi],0xf                           ;end of line?\r
+       jne     .extra_characters_on_line\r
+    .end_of_line:\r
+       cmp     ah,al\r
+       jnz     .amibguous_definition\r
+    .finish:\r
+    ;return al=matched template ordinal\r
+       mov     ecx,[esp]                               ;get template definitions\r
+       movzx   ebx,byte[ecx]\r
+       imul    ebx,ebx,TEMPLATE_length\r
+       lea     ebx,[ebx+ecx+1+TEMPLATE_length]\r
+       mov     [esp],ebx\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     .ret\r
+    ;create a default instruction for ARM\r
+       mov     ebp,[arm_instruction]\r
+       mov     cl,[instruction_condition]\r
+       and     cl,0xf0\r
+       shl     ecx,24\r
+       or      ebp,ecx\r
+       mov     ecx,ebp\r
+       or      ecx,1 shl 20                            ;set the S bit\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       cmovnz  ebp,ecx\r
+       mov     [arm_instruction],ebp\r
+    .ret:\r
+       ret\r
+    .unexpected_end_of_line:\r
+       jmp     ERROR_unexpected_end_of_line\r
+    .extra_characters_on_line:\r
+       jmp     extra_characters_on_line\r
+    .amibguous_definition:\r
+    .failed:\r
+       cmp     [current_parameter],0\r
+       jz      ERROR_parameter_n_not_valid.first\r
+       cmp     [current_parameter],1\r
+       jz      ERROR_parameter_n_not_valid.second\r
+       cmp     [current_parameter],2\r
+       jz      ERROR_parameter_n_not_valid.third\r
+       cmp     [current_parameter],3\r
+       jz      ERROR_parameter_n_not_valid.fourth\r
+       cmp     [current_parameter],4\r
+       jz      ERROR_parameter_n_not_valid.fifth\r
+       cmp     [current_parameter],5\r
+       jz      ERROR_parameter_n_not_valid.sixth\r
+       jmp     ERROR_parameter_n_not_valid.all\r
+    .skip_comma:\r
+       mov     al,[esi]\r
+       cmp     al,0xf                                  ;end of line?\r
+       jz      .TMPL_okay\r
+       cmp     al,0x0                                  ;end of source?\r
+       jz      .TMPL_okay\r
+       cmp     al,']'\r
+       jz      .TMPL_okay\r
+       inc     esi\r
+       cmp     al,','\r
+       jnz     .expecting_comma\r
+       cmp     byte[esi],0xf                           ;end of line?\r
+       jz      .unexpected_end_of_line\r
+       cmp     byte[esi],0x0                           ;end of source?\r
+       jz      .unexpected_end_of_line\r
+    .TMPL_always:\r
+    .TMPL_okay:\r
+       clc\r
+       retn\r
+    .expecting_comma:\r
+    .TMPL_never:\r
+    .TMPL_not_matched:\r
+       stc\r
+       retn\r
+    .TMPL_modifier_exclaim:\r
+       cmp     word[esi],(modifier + 0) shr 8 + ((modifier + 0) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       jmp     .TMPL_okay\r
+    .TMPL_modifier_translate:\r
+       cmp     word[esi],(modifier + 1) shr 8 + ((modifier + 1) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       jmp     .TMPL_okay\r
+    .TMPL_copro_opcode1:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [copro_opcode1],al\r
+       inc     [current_parameter]\r
+       cmp     eax,0xf\r
+       ja      .TMPL_out_of_range\r
+       test    edx,edx\r
+       jnz     .TMPL_out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jz      .skip_comma\r
+    .TMPL_out_of_range:\r
+       mov     ecx,ERROR_value_out_of_range\r
+       call    ARM_defer_error\r
+       jmp     .skip_comma\r
+    .TMPL_copro_opcode2:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [copro_opcode2],al\r
+       inc     [current_parameter]\r
+       cmp     eax,0x7\r
+       ja      .TMPL_out_of_range\r
+       test    edx,edx\r
+       jnz     .TMPL_out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jz      .skip_comma\r
+       jmp     .TMPL_out_of_range\r
+    .TMPL_EOL:\r
+       cmp     byte[esi],0xf                           ;end of line?\r
+       jz      .TMPL_okay\r
+       cmp     byte[esi],0x0                           ;end of source?\r
+       jz      .TMPL_okay\r
+       jmp     .TMPL_not_matched\r
+    .TMPL_reg_decoder:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       shr     edx,16\r
+       cmp     ax,dx\r
+       jae     .TMPL_not_matched\r
+       cmp     byte[esi],'('\r
+       jz      .TMPL_not_matched\r
+    .TMPL_put_reg:\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],al\r
+       inc     [current_reg_number]\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_base_reg:\r
+       mov     edx,base_reg + base_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_base_reg!:\r
+       mov     edx,base_reg! + base_reg!.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_cpro_sel:\r
+       mov     edx,cpro_sel + cpro_sel.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_cpro_reg:\r
+       mov     edx,cpro_reg + cpro_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_fpa_freg:\r
+       mov     edx,fpa_freg + fpa_freg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_barrier:\r
+       mov     edx,barrier + barrier.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_condition_nv:\r
+       mov     edx,condition + condition.size shl 16\r
+       jmp     .TMPL_condition.do\r
+    .TMPL_condition:\r
+       mov     edx,condition + (condition.size-1) shl 16                       ;exclude NV\r
+    .TMPL_condition.do:\r
+       cmp     word[esi],(endian + 0) shr 8 + ((endian + 0) and 0xff) shl 8    ;special value for overlap with LE\r
+       mov     al,0xd\r
+       jz      .TMPL_condition.found2\r
+       cmp     byte[esi],0xf0                                                  ;special value for overlap with EQ\r
+       mov     al,0x0\r
+       jz      .TMPL_condition.found1\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_condition.found2:\r
+       inc     esi\r
+    .TMPL_condition.found1:\r
+       inc     esi\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_shift_op:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,shift_op\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,shift_op.size\r
+       jae     .TMPL_not_matched\r
+       mov     [instruction_shift_op],al\r
+       jmp     .TMPL_okay\r
+    .TMPL_shift_op3:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,shift_op\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,shift_op.size-1                      ;ror not allowed\r
+       jae     .TMPL_not_matched\r
+       mov     [instruction_shift_op],al\r
+       jmp     .TMPL_okay\r
+    .TMPL_vfpdx_reg:\r
+       cmp     word[esi+2],'[('\r
+       jnz     .TMPL_not_matched\r
+       lodsd\r
+       xchg    ah,al\r
+       sub     ax,vfpd_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,vfpd_reg.size\r
+       jae     .TMPL_not_matched\r
+       push    eax\r
+       call    ARM_calculate_expression\r
+       pop     eax\r
+       cmp     byte[esi],']'\r
+       jnz     .TMPL_not_matched\r
+       cmp     word[edi+10],0                          ;mult2, mult1\r
+       jnz     .TMPL_not_matched\r
+    ;double and shift high bit to LSb\r
+       add     al,al\r
+       mov     ah,al\r
+       shr     al,5\r
+       and     ax,0x1e01\r
+       or      ah,al\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],ah\r
+       inc     [current_reg_number]\r
+       inc     esi\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       cmp     eax,0x7\r
+       ja      .TMPL_out_of_range\r
+       test    edx,edx\r
+       jnz     .TMPL_out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jnz     .TMPL_out_of_range\r
+       jmp     .skip_comma\r
+    .TMPL_vfps_reg:\r
+       mov     edx,vfps_reg + vfps_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vfpd_reg:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,vfpd_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,vfpd_reg.size\r
+       jae     .TMPL_not_matched\r
+    .TMPL_vfpd_reg.do:\r
+    ;double and shift high bit to LSb\r
+       add     al,al\r
+       mov     ah,al\r
+       shr     al,5\r
+       and     ax,0x1e01\r
+       or      ah,al\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],ah\r
+       inc     [current_reg_number]\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_simd_qreg:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,simd_qreg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,simd_qreg.size\r
+       jae     .TMPL_not_matched\r
+       add     al,al\r
+       jmp     .TMPL_vfpd_reg.do\r
+    .TMPL_vect_breg:\r
+       mov     edx,vect_breg + vect_breg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_hreg:\r
+       mov     edx,vect_hreg + vect_hreg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_sreg:\r
+       mov     edx,vect_sreg + vect_sreg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_dreg:\r
+       mov     edx,vect_dreg + vect_dreg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_qreg:\r
+       mov     edx,vect_qreg + vect_qreg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v8b:\r
+       mov     edx,vect_v8b + vect_v8b.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v16b:\r
+       mov     edx,vect_v16b + vect_v16b.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v4h:\r
+       mov     edx,vect_v4h + vect_v4h.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v8h:\r
+       mov     edx,vect_v8h + vect_v8h.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v2s:\r
+       mov     edx,vect_v2s + vect_v2s.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v4s:\r
+       mov     edx,vect_v4s + vect_v4s.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v1d:\r
+       mov     edx,vect_v1d + vect_v1d.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v2d:\r
+       mov     edx,vect_v2d + vect_v2d.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vect_v1q:\r
+       mov     edx,vect_v1q + vect_v1q.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_vfp_syst:\r
+       mov     edx,vfp_syst + vfp_syst.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_acc_40bt:\r
+       mov     edx,acc_40bt + acc_40bt.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_endian:\r
+       mov     edx,endian + endian.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_iflags:\r
+       mov     edx,iflags + iflags.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_psr:\r
+       mov     edx,psr_reg + psr_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_iwmmx_wreg:\r
+       mov     edx,iwmmx_wreg + iwmmx_wreg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_iwmmx_creg:\r
+       mov     edx,iwmmx_creg + iwmmx_creg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_address:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       cmp     byte[edx+1],'.'                         ;float?\r
+       jz      .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       movzx   ecx,byte[edi+13]                        ;sign bit\r
+       and     ecx,1\r
+       or      ecx,edx\r
+       jz      .TMPL_okay\r
+       cdq\r
+       cmp     edx,[edi+4]\r
+       jnz     .TMPL_address.out_of_range\r
+       xor     dl,[edi+13]                             ;check sign\r
+       test    dl,1\r
+       jz      .TMPL_okay\r
+       jmp     .TMPL_address.out_of_range\r
+    .TMPL_address64:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       cmp     byte[edx+1],'.'                         ;float?\r
+       jz      .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       mov     [immediate_value_high],edx\r
+       inc     [current_parameter]\r
+       movzx   ecx,byte[edi+13]                        ;sign bit\r
+       and     ecx,1\r
+       jz      .TMPL_okay\r
+       test    edx,edx\r
+       js      .TMPL_okay\r
+    .TMPL_address.out_of_range:\r
+       mov     ecx,ERROR_value_out_of_range\r
+       call    ARM_defer_error\r
+       jmp     .TMPL_okay\r
+    .TMPL_imm_float:\r
+       mov     eax,[esi]\r
+       cmp     ax,'(.'\r
+       jz      .TMPL_imm\r
+       and     eax,0x00ffffff\r
+       cmp     eax,'#(.'\r
+       jz      .TMPL_imm\r
+       jmp     .TMPL_not_matched\r
+    .TMPL_imm2:\r
+       mov     ecx,immediate_value2\r
+       jmp     .TMPL_imm.do\r
+    .TMPL_imm:\r
+       mov     ecx,immediate_value\r
+    .TMPL_imm.do:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       push    esi ecx\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     ecx esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [ecx],eax\r
+       inc     [current_parameter]\r
+       movzx   ecx,byte[edi+13]                        ;sign bit\r
+       and     ecx,1\r
+       or      ecx,edx\r
+       jz      .TMPL_okay\r
+       cdq\r
+       cmp     edx,[edi+4]\r
+       jnz     .TMPL_imm.out_of_range\r
+       xor     dl,[edi+13]                             ;check sign\r
+       test    dl,1\r
+       jz      .TMPL_okay\r
+       jmp     .TMPL_imm.out_of_range\r
+    .TMPL_imm64:\r
+       cmp     byte[esi],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       add     edx,esi\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       mov     [immediate_value_high],edx\r
+       inc     [current_parameter]\r
+       movzx   ecx,byte[edi+13]                        ;sign bit\r
+       and     ecx,1\r
+       jz      .TMPL_okay\r
+       test    edx,edx\r
+       js      .TMPL_okay\r
+    .TMPL_imm.out_of_range:\r
+       mov     ecx,ERROR_value_out_of_range\r
+       call    ARM_defer_error\r
+       jmp     .TMPL_okay\r
+    .TMPL_bracket_left:\r
+       mov     [operand_flags],0\r
+       mov     edx,esi\r
+       mov     cx,[edx]\r
+       xchg    ch,cl\r
+       sub     cx,size_opr\r
+       jb      .no_size_operator\r
+       cmp     cx,size_opr.size\r
+       jae     .no_size_operator\r
+       cmp     cl,[operand_size]\r
+       jnz     ERROR_operand_sizes_do_not_match\r
+       add     edx,2\r
+       mov     [operand_flags],1\r
+    .no_size_operator:\r
+       cmp     byte[edx],'['\r
+       jnz     .TMPL_not_matched\r
+       inc     edx\r
+       mov     esi,edx\r
+       jmp     .TMPL_okay\r
+    .TMPL_bracket_right:\r
+       cmp     byte[esi],']'\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       cmp     word[esi],(modifier + 0) shr 8 + ((modifier + 0) and 0xff) shl 8\r
+       jnz     .skip_comma\r
+       jmp     .TMPL_okay\r
+    .TMPL_simd_reg_list:\r
+       cmp     byte[esi],0x91\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,vfpd_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,vfpd_reg.size\r
+       jae     .TMPL_not_matched\r
+       mov     [simd_reg_list_first],al\r
+       mov     [simd_reg_list_count],1\r
+       mov     [simd_reg_list_x],0\r
+       mov     [simd_reg_list_type],SIMD_REG_LIST_TYPE_REGISTER\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_simd_reg_list.done\r
+       cmp     word[esi],'[]'\r
+       jz      .TMPL_simd_reg_list.vector\r
+       cmp     word[esi],'[('\r
+       jz      .TMPL_simd_reg_list.element\r
+    .TMPL_simd_reg_list.check_next:\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_simd_reg_list.done\r
+       cmp     byte[esi],','\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,vfpd_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,vfpd_reg.size\r
+       jae     .TMPL_not_matched\r
+       inc     [simd_reg_list_count]\r
+       cmp     [simd_reg_list_count],2                 ;second reg sets the separation\r
+       jnz     .TMPL_simd_reg_list.check_separation\r
+       sub     al,[simd_reg_list_first]\r
+       dec     al\r
+       test    al,not 1\r
+       jnz     .TMPL_not_matched\r
+       and     al,1\r
+       ror     al,1\r
+       or      [simd_reg_list_count],al\r
+       jmp     .TMPL_simd_reg_list.separation_okay\r
+    .TMPL_simd_reg_list.check_separation:\r
+       mov     ah,[simd_reg_list_first]\r
+       mov     cl,[simd_reg_list_count]\r
+       mov     ch,cl\r
+       and     ch,0x7f\r
+       sub     al,ah\r
+       rol     cl,1\r
+       and     cl,1\r
+       shr     al,cl\r
+       jc      .TMPL_not_matched\r
+       inc     al\r
+       cmp     al,ch\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_simd_reg_list.separation_okay:\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       jz      .TMPL_simd_reg_list.check_vector\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       jz      .TMPL_simd_reg_list.check_element\r
+       jmp     .TMPL_simd_reg_list.check_next\r
+    .TMPL_simd_reg_list.check_vector:\r
+       cmp     word[esi],'[]'\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       jmp     .TMPL_simd_reg_list.check_next\r
+    .TMPL_simd_reg_list.check_element:\r
+       cmp     word[esi],'[('\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       call    ARM_calculate_expression\r
+       cmp     word[edi+10],0                          ;mult2, mult1\r
+       jnz     .TMPL_not_matched\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       test    edx,edx\r
+       jnz     .TMPL_not_matched\r
+       test    byte[edi+13],1                          ;check sign\r
+       jnz     .TMPL_not_matched\r
+       cmp     eax,7\r
+       ja      .TMPL_not_matched\r
+       cmp     [simd_reg_list_x],al\r
+       jnz     .TMPL_not_matched\r
+       lodsb\r
+       cmp     al,']'\r
+       jnz     .TMPL_not_matched\r
+       jmp     .TMPL_simd_reg_list.check_next\r
+    .TMPL_simd_reg_list.vector:\r
+       mov     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       add     esi,2\r
+       jmp     .TMPL_simd_reg_list.check_next\r
+    .TMPL_simd_reg_list.element:\r
+       mov     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       add     esi,2\r
+       call    ARM_calculate_expression\r
+       cmp     word[edi+8],0                           ;reg2, reg1\r
+       jnz     .TMPL_not_matched\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       test    edx,edx\r
+       jnz     .TMPL_not_matched\r
+       test    byte[edi+13],1                          ;check sign\r
+       jnz     .TMPL_not_matched\r
+       cmp     eax,7\r
+       ja      .TMPL_not_matched\r
+       mov     [simd_reg_list_x],al\r
+       lodsb\r
+       cmp     al,']'\r
+       jnz     .TMPL_not_matched\r
+       jmp     .TMPL_simd_reg_list.check_next\r
+    .TMPL_simd_reg_list.done:\r
+       inc     esi\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_vfp_reg_list_s:\r
+       mov     edx,vfps_reg + vfps_reg.size shl 16\r
+       jmp     .TMPL_reg_list.decode\r
+    .TMPL_vfp_reg_list_d:\r
+       mov     edx,vfpd_reg + vfpd_reg.size shl 16\r
+       jmp     .TMPL_reg_list.decode\r
+    .TMPL_reg_list:\r
+       mov     edx,base_reg + base_reg.size shl 16\r
+    .TMPL_reg_list.decode:\r
+       cmp     byte[esi],0x91\r
+       jnz     .TMPL_not_matched\r
+       mov     [reg_list_bitmap],0\r
+    .TMPL_reg_list.next:\r
+       inc     esi\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_reg_list.done\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       cmp     ax,dx\r
+       jae     .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   ecx,al\r
+       bts     [reg_list_bitmap],ecx\r
+       jc      ERROR_repeated_register_in_list\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_reg_list.done\r
+       cmp     byte[esi],','\r
+       jz      .TMPL_reg_list.next\r
+       cmp     byte[esi],'-'\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       cmp     ax,dx\r
+       jae     .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   ebx,al\r
+       btr     [reg_list_bitmap],ecx\r
+       cmp     ecx,ebx\r
+       je      ERROR_repeated_register_in_list\r
+       jg      .TMPL_reg_list.range_next\r
+       xchg    ecx,ebx\r
+    .TMPL_reg_list.range_next:\r
+       bts     [reg_list_bitmap],ecx\r
+       jc      ERROR_repeated_register_in_list\r
+       dec     ecx\r
+       cmp     ecx,ebx\r
+       jge     .TMPL_reg_list.range_next\r
+       cmp     byte[esi],','\r
+       jz      .TMPL_reg_list.next\r
+       cmp     byte[esi],0x92\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_reg_list.done:\r
+       inc     esi\r
+       cmp     [reg_list_bitmap],0\r
+       jz      ERROR_empty_set\r
+       inc     [current_parameter]\r
+       jmp     .TMPL_okay\r
+    .TMPL_rrx_op:\r
+       cmp     word[esi],rrx_op shr 8 + (rrx_op and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       inc     [current_parameter]\r
+       jmp     .TMPL_okay\r
+    .TMPL_sysm_reg:\r
+       mov     ax,word[esi]\r
+       xchg    ah,al\r
+       cmp     ax,psr_reg+34\r
+       jz      .TMPL_sysm_reg.apsr\r
+       mov     edx,sysm_reg + sysm_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_sysm_reg.apsr:\r
+       mov     al,0\r
+       add     esi,2\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_banked_reg:\r
+       mov     edx,banked_reg + banked_reg.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_mvrk_areg:\r
+       mov     ax,word[esi]\r
+       xchg    ah,al\r
+       cmp     ax,mvrk_areg\r
+       jnz     .TMPL_mvrk_areg_a1_a3\r
+       sub     ax,mvrk_areg\r
+       jz      .TMPL_mvrk_areg_a0\r
+    .TMPL_mvrk_areg_a1_a3:\r
+       sub     ax,base_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,2\r
+       ja      .TMPL_not_matched\r
+       inc     al\r
+    .TMPL_mvrk_areg_a0:\r
+       add     esi,2\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_mvrk_psc:\r
+       cmp     word[esi],mvrk_psc shr 8 + (mvrk_psc and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_add_sub_reg:\r
+       mov     cl,0\r
+       cmp     byte[esi],'-'\r
+       jnz     .TMPL_add_reg\r
+       mov     cl,0x80\r
+       inc     esi\r
+    .TMPL_add_reg:\r
+       mov     ax,[esi]\r
+       xchg    ah,al\r
+       sub     ax,base_reg\r
+       jb      .TMPL_reg_in_expression\r
+       cmp     ax,base_reg.size\r
+       jae     .TMPL_reg_in_expression\r
+       add     esi,2\r
+       or      al,cl\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_reg_in_expression:\r
+       lodsb\r
+       cmp     al,'('\r
+       jnz     .TMPL_not_matched\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,base_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,base_reg.size\r
+       jae     .TMPL_not_matched\r
+       cmp     byte[esi],')'\r
+       jz      .TMPL_reg_in_expression.add_reg\r
+       cmp     word[esi],')' shl 8 + 0x83              ;unary minus?\r
+       jnz     .TMPL_not_matched\r
+       or      al,0x80\r
+       inc     esi\r
+    .TMPL_reg_in_expression.add_reg:\r
+       inc     esi\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_address_reg@:\r
+       lodsw\r
+       xchg    ah,al\r
+       mov     edx,base_reg + (0*16) shl 16\r
+       cmp     ax,base_reg\r
+       jb      @f\r
+       cmp     ax,base_reg + base_reg.size\r
+       jb      .TMPL_address_reg@.make\r
+    @@:        mov     edx,base_@16 + (1*16) shl 16\r
+       cmp     ax,base_@16\r
+       jb      @f\r
+       cmp     ax,base_@16 + base_@16.size\r
+       jb      .TMPL_address_reg@.make\r
+    @@:        mov     edx,base_@32 + (2*16) shl 16\r
+       cmp     ax,base_@32\r
+       jb      @f\r
+       cmp     ax,base_@32 + base_@32.size\r
+       jb      .TMPL_address_reg@.make\r
+    @@:        mov     edx,base_@64 + (3*16) shl 16\r
+       cmp     ax,base_@64\r
+       jb      @f\r
+       cmp     ax,base_@64 + base_@64.size\r
+       jb      .TMPL_address_reg@.make\r
+    @@:        mov     edx,base_@128 + (4*16) shl 16\r
+       cmp     ax,base_@128\r
+       jb      @f\r
+       cmp     ax,base_@128 + base_@128.size\r
+       jb      .TMPL_address_reg@.make\r
+    @@:        mov     edx,base_@256 + (5*16) shl 16\r
+       cmp     ax,base_@256\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,base_@256 + base_@256.size\r
+       jae     .TMPL_not_matched\r
+    .TMPL_address_reg@.make:\r
+       sub     ax,dx\r
+       shr     edx,16\r
+       add     al,dl\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_expression:\r
+       xor     edx,edx\r
+       cmp     byte[esi],'('\r
+       jz      .TMPL_expression.start_okay\r
+       cmp     byte[esi],0x10\r
+       jnz     .TMPL_not_matched\r
+       cmp     byte[esi+2],'('\r
+       jnz     .TMPL_not_matched\r
+       lodsw\r
+       mov     dl,ah\r
+       add     edx,0x10000\r
+    .TMPL_expression.start_okay:\r
+       push    esi edx\r
+       inc     esi\r
+       call    ARM_calculate_expression\r
+       pop     eax edx\r
+       xchg    esi,edx\r
+       mov     ecx,[edi+8]                             ;mult2, mult1, reg2, reg1\r
+       add     ecx,eax\r
+       cmp     ecx,0xffff\r
+       jbe     .TMPL_not_matched\r
+       xor     ecx,0x00010000\r
+       cmp     ecx,0xff\r
+       ja      .TMPL_invalid_expression.too_complex\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     .TMPL_expression.64\r
+       sub     cl,base_reg - 0x1000\r
+       jb      .TMPL_invalid_expression.not_base\r
+       cmp     cl,base_reg.size\r
+       jae     .TMPL_invalid_expression.not_base\r
+       jmp     .TMPL_expression.set_reg\r
+    .TMPL_expression.64:\r
+       cmp     cl,dword_reg + 31 - 0x1000              ;xzr not allowed\r
+       je      .TMPL_invalid_expression.not_base64\r
+       mov     al,dword_reg + 31 - 0x1000\r
+       cmp     cl,base_reg + 13 - 0x1000               ;sp?\r
+       cmovz   ecx,eax\r
+       sub     cl,dword_reg - 0x1000\r
+       jb      .TMPL_invalid_expression.not_base64\r
+       cmp     cl,dword_reg.size\r
+       jae     .TMPL_invalid_expression.not_base64\r
+    .TMPL_expression.set_reg:\r
+       xchg    esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       movzx   ebx,[current_reg_number]\r
+       mov     [operand_register0+ebx],cl\r
+       inc     [current_reg_number]\r
+       inc     [current_parameter]\r
+       movzx   ecx,byte[edi+13]                        ;sign bit\r
+       and     ecx,1\r
+       or      ecx,edx\r
+       jz      .TMPL_okay\r
+       cdq\r
+       cmp     edx,[edi+4]\r
+       jnz     .TMPL_expression.out_of_range\r
+       xor     dl,[edi+13]                             ;check sign\r
+       test    dl,1\r
+       jz      .TMPL_okay\r
+    .TMPL_expression.out_of_range:\r
+       mov     ecx,ERROR_value_out_of_range\r
+       call    ARM_defer_error\r
+       jmp     .TMPL_okay\r
+    .TMPL_invalid_expression.too_complex:\r
+       jmp     ERROR_register_out_of_range.too_complex\r
+    .TMPL_invalid_expression.not_base:\r
+       jmp     ERROR_register_out_of_range.only_base\r
+    .TMPL_invalid_expression.not_base64:\r
+       jmp     ERROR_register_out_of_range.only_base64\r
+    .TMPL_option:\r
+       cmp     byte[esi],0x91\r
+       jnz     .TMPL_not_matched\r
+       cmp     byte[esi+1],'#'\r
+       setz    dl\r
+       movzx   edx,dl\r
+       lea     edx,[esi+edx+1]\r
+       cmp     byte[edx],'('\r
+       jnz     .TMPL_not_matched\r
+       push    esi\r
+       lea     esi,[edx+1]\r
+       call    ARM_calculate_expression\r
+       mov     edx,esi\r
+       pop     esi\r
+       cmp     word[edi+10],0                          ;mult2, mult1\r
+       jnz     .TMPL_not_matched\r
+       inc     edx\r
+       cmp     byte[edx-1],0x92\r
+       jnz     .TMPL_not_matched\r
+       mov     esi,edx\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       test    edx,edx\r
+       jnz     .TMPL_option.out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jz      .TMPL_okay\r
+    .TMPL_option.out_of_range:\r
+       mov     ecx,ERROR_value_out_of_range\r
+       call    ARM_defer_error\r
+       jmp     .TMPL_okay\r
+    .TMPL_comma:\r
+       cmp     byte[esi],','\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       jmp     .TMPL_okay\r
+    .TMPL_word_z_reg:\r
+       assert  TMPL_word_z_reg and not 1 = TMPL_word_s_reg and not 1\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,word_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,word_reg.size - 2\r
+       ja      .TMPL_not_matched                       ;wsp not allowed\r
+       setnz   cl                                      ;wzr?\r
+       or      [esp+6 + __is_64 * 4],cl\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_word_s_reg:\r
+       assert  TMPL_word_z_reg and not 1 = TMPL_word_s_reg and not 1\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,word_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,word_reg.size\r
+       jae     .TMPL_not_matched\r
+       cmp     al,word_reg.size - 2\r
+       jz      .TMPL_not_matched                       ;wzr not allowed\r
+       seta    cl                                      ;wsp?\r
+       sub     al,cl\r
+       or      [esp+6 + __is_64 * 4],cl\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_dword_z_reg:\r
+       assert  TMPL_dword_z_reg and not 1 = TMPL_dword_s_reg and not 1\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dword_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,dword_reg.size - 1\r
+       ja      .TMPL_not_matched\r
+       setnz   cl                                      ;wzr?\r
+       or      [esp+6 + __is_64 * 4],cl\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_dword_s_reg:\r
+       assert  TMPL_dword_z_reg and not 1 = TMPL_dword_s_reg and not 1\r
+       lodsw\r
+       xchg    ah,al\r
+       cmp     ax,base_reg + 13                        ;sp?\r
+       jz      .TMPL_dword_s_reg.sp\r
+       sub     ax,dword_reg\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,dword_reg.size - 1\r
+       jae     .TMPL_not_matched                       ;xzr not allowed\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_dword_s_reg.sp:\r
+       or      byte[esp+6 + __is_64 * 4],1\r
+       mov     al,0x1f\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_word_gen_reg:\r
+       mov     edx,word_reg + (word_reg.size - 2) shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_word_zr_reg:\r
+       lodsw\r
+       cmp     ax,(word_reg + word_reg.size - 2) shr 8 + ((word_reg + word_reg.size - 2) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       mov     al,0x1f\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_word_sp_reg:\r
+       lodsw\r
+       cmp     ax,(word_reg + word_reg.size - 1) shr 8 + ((word_reg + word_reg.size - 1) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       mov     al,0x1f\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_dword_gen_reg:\r
+       mov     edx,dword_reg + (dword_reg.size - 1) shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_prf_op:\r
+       mov     edx,prf_op + prf_op.size shl 16\r
+       jmp     .TMPL_reg_decoder\r
+    .TMPL_dword_zr_reg:\r
+       lodsw\r
+       cmp     ax,(dword_reg + dword_reg.size - 1) shr 8 + ((dword_reg + dword_reg.size - 1) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       mov     al,0x1f\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_dword_sp_reg:\r
+       lodsw\r
+       cmp     ax,(base_reg+13) shr 8 + ((base_reg+13) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       mov     al,0x1f\r
+       jmp     .TMPL_put_reg\r
+    .TMPL_extend:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,xtnd_op\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,xtnd_op.size\r
+       jae     .TMPL_not_matched\r
+       mov     [instruction_shift_op],al\r
+       jmp     .TMPL_okay\r
+    .TMPL_lsl:\r
+       lodsw\r
+       cmp     ax,(shift_op+0) shr 8 + ((shift_op+0) and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       mov     [instruction_shift_op],0\r
+       jmp     .TMPL_okay\r
+    .TMPL_at_op:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,sys_at\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_at.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_dc_op:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,sys_dc\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_dc.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_ic_op:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,sys_ic\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_ic.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_tlbi_op:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,sys_tlbi\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_tlbi.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_msr_reg:\r
+       lodsw\r
+       xchg    ah,al\r
+       cmp     ax,banked_reg+32+20                     ;spsr_abt?\r
+       mov     cx,sys_msr+(sys_encode_spsr_abt-sys_encode_table_msr) shr 1\r
+       cmovz   eax,ecx\r
+       cmp     ax,banked_reg+32+14                     ;spsr_fiq?\r
+       mov     cx,sys_msr+(sys_encode_spsr_fiq-sys_encode_table_msr) shr 1\r
+       cmovz   eax,ecx\r
+       cmp     ax,banked_reg+32+16                     ;spsr_irq?\r
+       mov     cx,sys_msr+(sys_encode_spsr_irq-sys_encode_table_msr) shr 1\r
+       cmovz   eax,ecx\r
+       cmp     ax,banked_reg+32+22                     ;spsr_und?\r
+       mov     cx,sys_msr+(sys_encode_spsr_und-sys_encode_table_msr) shr 1\r
+       cmovz   eax,ecx\r
+       sub     ax,sys_msr\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_msr.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_pstate_reg:\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,sys_pstate\r
+       jb      .TMPL_not_matched\r
+       cmp     ax,sys_pstate.size\r
+       jae     .TMPL_not_matched\r
+       movzx   eax,ax\r
+       mov     [immediate_value],eax\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_sysreg_dynamic:\r
+       lodsw\r
+       cmp     ax,'(' + 0x11 shl 8\r
+       jnz     .TMPL_not_matched\r
+       lodsd\r
+       cmp     byte[esi],')'\r
+       jnz     .TMPL_not_matched\r
+       inc     esi\r
+       xor     edx,edx\r
+       mov     ebx,[eax+0x18]\r
+       ;S<op0>_<op1>_<Cn>_<Cm>_<op2>\r
+       mov     cl,[ebx]\r
+       inc     ebx\r
+       cmp     cl,'s'\r
+       jz      .TMPL_sysreg_dynamic.start_okay\r
+       cmp     cl,'S'\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_sysreg_dynamic.start_okay:\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,3\r
+       ja      .TMPL_not_matched\r
+       cmp     cl,2\r
+       jb      .TMPL_not_matched\r
+       or      edx,ecx\r
+       cmp     byte[ebx],'_'\r
+       jnz     .TMPL_not_matched\r
+       inc     ebx\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,7\r
+       ja      .TMPL_not_matched\r
+       shl     edx,3\r
+       or      edx,ecx\r
+       cmp     word[ebx],'_c'\r
+       jz      .TMPL_sysreg_dynamic.first_reg_okay\r
+       cmp     word[ebx],'_C'\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_sysreg_dynamic.first_reg_okay:\r
+       inc     ebx\r
+       inc     ebx\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,9\r
+       ja      .TMPL_not_matched\r
+       cmp     byte[ebx],'_'\r
+       jz      .TMPL_sysreg_dynamic.place_first_reg\r
+       cmp     cl,1\r
+       jnz     .TMPL_not_matched\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,5\r
+       ja      .TMPL_not_matched\r
+       add     cl,10\r
+    .TMPL_sysreg_dynamic.place_first_reg:\r
+       shl     edx,4\r
+       or      edx,ecx\r
+       cmp     word[ebx],'_c'\r
+       jz      .TMPL_sysreg_dynamic.second_reg_okay\r
+       cmp     word[ebx],'_C'\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_sysreg_dynamic.second_reg_okay:\r
+       inc     ebx\r
+       inc     ebx\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,9\r
+       ja      .TMPL_not_matched\r
+       cmp     byte[ebx],'_'\r
+       jz      .TMPL_sysreg_dynamic.place_second_reg\r
+       cmp     cl,1\r
+       jnz     .TMPL_not_matched\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,5\r
+       ja      .TMPL_not_matched\r
+       add     cl,10\r
+    .TMPL_sysreg_dynamic.place_second_reg:\r
+       shl     edx,4\r
+       or      edx,ecx\r
+       cmp     byte[ebx],'_'\r
+       jnz     .TMPL_not_matched\r
+       inc     ebx\r
+       movzx   ecx,byte[ebx]\r
+       inc     ebx\r
+       sub     cl,'0'\r
+       jb      .TMPL_not_matched\r
+       cmp     cl,7\r
+       ja      .TMPL_not_matched\r
+       shl     edx,3\r
+       or      edx,ecx\r
+       cmp     byte[ebx],','\r
+       jz      .TMPL_sysreg_dynamic.create\r
+       cmp     byte[ebx],0\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_sysreg_dynamic.create:\r
+       mov     [immediate_value],edx\r
+       mov     cx,[current_pass]\r
+       xchg    [eax+16],cx\r
+       mov     edx,[current_line]\r
+       mov     [eax+28],edx\r
+       or      byte[eax+8],1+2\r
+       jmp     .skip_comma\r
+    .TMPL_vect_element_b:\r
+       mov     edx,vect_vb + vect_vb.size shl 16 + 15 shl 24\r
+       jmp     .TMPL_vect_element\r
+    .TMPL_vect_element_h:\r
+       mov     edx,vect_vh + vect_vh.size shl 16 + 7 shl 24\r
+       jmp     .TMPL_vect_element\r
+    .TMPL_vect_element_s:\r
+       mov     edx,vect_vs + vect_vs.size shl 16 + 3 shl 24\r
+       jmp     .TMPL_vect_element\r
+    .TMPL_vect_element_d:\r
+       mov     edx,vect_vd + vect_vd.size shl 16 + 1 shl 24\r
+    .TMPL_vect_element:\r
+       cmp     word[esi+2],'[('\r
+       jnz     .TMPL_not_matched\r
+       lodsd\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   cx,dl\r
+       cmp     ax,cx\r
+       jae     .TMPL_not_matched\r
+       push    eax edx\r
+       call    ARM_calculate_expression\r
+       pop     ebx eax\r
+       cmp     byte[esi],']'\r
+       jnz     .TMPL_not_matched\r
+       cmp     word[edi+10],0                          ;mult2, mult1\r
+       jnz     .TMPL_not_matched\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],al\r
+       inc     [current_reg_number]\r
+       inc     esi\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,immediate_value\r
+       mov     edx,immediate_value2\r
+       test    ecx,ecx\r
+       cmovnz  eax,edx\r
+       mov     ecx,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [eax],ecx\r
+       inc     [current_parameter]\r
+       movzx   ebx,bh\r
+       cmp     ecx,ebx\r
+       ja      .TMPL_out_of_range\r
+       test    edx,edx\r
+       jnz     .TMPL_out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jnz     .TMPL_out_of_range\r
+       jmp     .skip_comma\r
+    .TMPL_vect_list_8b:\r
+       mov     edx,vect_v8b + vect_v8b.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_16b:\r
+       mov     edx,vect_v16b + vect_v16b.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_4h:\r
+       mov     edx,vect_v4h + vect_v4h.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_8h:\r
+       mov     edx,vect_v8h + vect_v8h.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_2s:\r
+       mov     edx,vect_v2s + vect_v2s.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_4s:\r
+       mov     edx,vect_v4s + vect_v4s.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_1d:\r
+       mov     edx,vect_v1d + vect_v1d.size shl 16\r
+       jmp     .TMPL_vect_list\r
+    .TMPL_vect_list_2d:\r
+       mov     edx,vect_v2d + vect_v2d.size shl 16\r
+    .TMPL_vect_list:\r
+       lodsb\r
+       cmp     al,0x91\r
+       jnz     .TMPL_not_matched\r
+       mov     [simd_reg_list_count],0\r
+    .TMPL_vect_list.next:\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_vect_list.done\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       cmp     ax,dx\r
+       jae     .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   eax,al\r
+       movzx   ecx,[simd_reg_list_count]\r
+       test    ecx,ecx\r
+       jnz     .TMPL_vect_list.check_increment\r
+       mov     [simd_reg_list_first],al\r
+       jmp     .TMPL_vect_list.advance\r
+    .TMPL_vect_list.check_increment:\r
+       mov     ebx,ecx\r
+       add     bl,[simd_reg_list_first]\r
+       and     bl,0x1f\r
+       cmp     bl,al\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_vect_list.advance:\r
+       inc     cl\r
+       mov     [simd_reg_list_count],cl\r
+       lodsb\r
+       cmp     al,','\r
+       jz      .TMPL_vect_list.next\r
+       cmp     al,0x92\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_vect_list.done:\r
+       cmp     [simd_reg_list_count],0\r
+       jz      ERROR_empty_set\r
+       cmp     [simd_reg_list_count],4\r
+       ja      .TMPL_not_matched\r
+       mov     bl,[simd_reg_list_first]\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],bl\r
+       inc     [current_reg_number]\r
+       inc     [current_parameter]\r
+       jmp     .skip_comma\r
+    .TMPL_vect_list_vb:\r
+       mov     edx,vect_vb + vect_vb.size shl 16 + 15 shl 24\r
+       jmp     .TMPL_vect_list_v\r
+    .TMPL_vect_list_vh:\r
+       mov     edx,vect_vh + vect_vh.size shl 16 + 7 shl 24\r
+       jmp     .TMPL_vect_list_v\r
+    .TMPL_vect_list_vs:\r
+       mov     edx,vect_vs + vect_vs.size shl 16 + 3 shl 24\r
+       jmp     .TMPL_vect_list_v\r
+    .TMPL_vect_list_vd:\r
+       mov     edx,vect_vd + vect_vd.size shl 16 + 1 shl 24\r
+    .TMPL_vect_list_v:\r
+       lodsb\r
+       cmp     al,0x91\r
+       jnz     .TMPL_not_matched\r
+       mov     [simd_reg_list_count],0\r
+    .TMPL_vect_list_v.next:\r
+       cmp     byte[esi],0x92\r
+       jz      .TMPL_vect_list_v.done\r
+       lodsw\r
+       xchg    ah,al\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   cx,dl\r
+       cmp     ax,cx\r
+       jae     .TMPL_not_matched\r
+       ror     edx,16\r
+       movzx   eax,al\r
+       movzx   ecx,[simd_reg_list_count]\r
+       test    ecx,ecx\r
+       jnz     .TMPL_vect_list_v.check_increment\r
+       mov     [simd_reg_list_first],al\r
+       jmp     .TMPL_vect_list_v.advance\r
+    .TMPL_vect_list_v.check_increment:\r
+       mov     ebx,ecx\r
+       add     bl,[simd_reg_list_first]\r
+       and     bl,0x1f\r
+       cmp     bl,al\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_vect_list_v.advance:\r
+       inc     cl\r
+       mov     [simd_reg_list_count],cl\r
+       lodsb\r
+       cmp     al,','\r
+       jz      .TMPL_vect_list_v.next\r
+       cmp     al,0x92\r
+       jnz     .TMPL_not_matched\r
+    .TMPL_vect_list_v.done:\r
+       cmp     [simd_reg_list_count],0\r
+       jz      ERROR_empty_set\r
+       cmp     [simd_reg_list_count],4\r
+       ja      .TMPL_not_matched\r
+       lodsw\r
+       cmp     ax,'[('\r
+       jnz     .TMPL_not_matched\r
+       push    edx\r
+       call    ARM_calculate_expression\r
+       pop     ebx\r
+       lodsb\r
+       cmp     al,']'\r
+       jnz     .TMPL_not_matched\r
+       cmp     word[edi+10],0                          ;mult2, mult1\r
+       jnz     .TMPL_not_matched\r
+       mov     bl,[simd_reg_list_first]\r
+       movzx   ecx,[current_reg_number]\r
+       mov     [operand_register0+ecx],bl\r
+       inc     [current_reg_number]\r
+       mov     eax,[edi+16]\r
+       mov     [symbol_identifier],eax\r
+       mov     al,[edi+12]\r
+       mov     [value_type],al\r
+       mov     eax,immediate_value\r
+       mov     edx,immediate_value2\r
+       test    ecx,ecx\r
+       cmovnz  eax,edx\r
+       mov     ecx,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [eax],ecx\r
+       inc     [current_parameter]\r
+       shr     ebx,24\r
+       cmp     ecx,ebx\r
+       ja      .TMPL_out_of_range\r
+       test    edx,edx\r
+       jnz     .TMPL_out_of_range\r
+       test    byte[edi+13],1                          ;check sign\r
+       jnz     .TMPL_out_of_range\r
+       jmp     .skip_comma\r
+    .TMPL_msl:\r
+       cmp     word[esi],msl_op shr 8 + (msl_op and 0xff) shl 8\r
+       jnz     .TMPL_not_matched\r
+       add     esi,2\r
+       inc     [current_parameter]\r
+       jmp     .TMPL_okay\r
+    .TMPL_cpu_sel:\r
+       mov     ecx,[cpu_capability_flags]\r
+       mov     ebx,[cpu_capability_flags2]\r
+       mov     edx,cpu_sel + cpu_sel.size shl 16\r
+       jmp     .TMPL_processor_selection\r
+    .TMPL_copro_sel:\r
+       mov     ecx,[copro_capability_flags]\r
+       xor     ebx,ebx\r
+       mov     edx,copro_sel + copro_sel.size shl 16\r
+    .TMPL_processor_selection:\r
+       cmp     byte[esi],'-'\r
+       jz      .TMPL_processor_selection.accumulate\r
+       cmp     byte[esi],'+'\r
+       jz      .TMPL_processor_selection.accumulate\r
+       ;start from scratch\r
+       xor     ecx,ecx\r
+       xor     ebx,ebx\r
+    .TMPL_processor_selection.accumulate:\r
+       xor     eax,eax\r
+       cmp     byte[esi],'+'\r
+       jz      .TMPL_processor_selection.increment\r
+       cmp     byte[esi],'-'\r
+       jnz     .TMPL_processor_selection.next\r
+       or      eax,-1\r
+    .TMPL_processor_selection.increment:\r
+       inc     esi\r
+    .TMPL_processor_selection.next:\r
+       lodsw\r
+       xchg    ah,al\r
+       cmp     ax,cpu_sel.all32\r
+       jz      .TMPL_processor_selection.cpu_sel.all32\r
+       cmp     ax,cpu_sel.all64\r
+       jz      .TMPL_processor_selection.cpu_sel.all64\r
+       cmp     ax,copro_sel.all\r
+       jz      .TMPL_processor_selection.copro_sel.all\r
+       sub     ax,dx\r
+       jb      .TMPL_not_matched\r
+       ror     edx,16\r
+       cmp     ax,dx\r
+       jae     .TMPL_not_matched\r
+       ror     edx,16\r
+       cmp     al,32\r
+       jb      @f\r
+       xchg    ecx,ebx\r
+    @@:        bts     ecx,eax\r
+       test    eax,eax\r
+       jns     @f\r
+       btr     ecx,eax\r
+    @@:        cmp     al,32\r
+       jb      .TMPL_processor_selection.advance\r
+       xchg    ecx,ebx\r
+    .TMPL_processor_selection.advance:\r
+       mov     al,[esi]\r
+       cmp     al,'+'\r
+       jz      .TMPL_processor_selection.accumulate\r
+       cmp     al,'-'\r
+       jz      .TMPL_processor_selection.accumulate\r
+       mov     [immediate_value],ecx\r
+       mov     [immediate_value_high],ebx\r
+       inc     [current_parameter]\r
+       jmp     .TMPL_okay\r
+    .TMPL_processor_selection.cpu_sel.all32:\r
+       cmp     dx,cpu_sel\r
+       jnz     .TMPL_not_matched\r
+       or      ecx,CPU32_CAPABILITY_ALL and (1 shl 32 - 1)\r
+       or      ebx,CPU32_CAPABILITY_ALL shr 32\r
+       test    eax,eax\r
+       jns     .TMPL_processor_selection.advance\r
+       and     ecx,not (CPU32_CAPABILITY_ALL and (1 shl 32 - 1))\r
+       and     ebx,not (CPU32_CAPABILITY_ALL shr 32)\r
+       jmp     .TMPL_processor_selection.advance\r
+    .TMPL_processor_selection.cpu_sel.all64:\r
+       cmp     dx,cpu_sel\r
+       jnz     .TMPL_not_matched\r
+       or      ecx,CPU64_CAPABILITY_ALL and (1 shl 32 - 1)\r
+       or      ebx,CPU64_CAPABILITY_ALL shr 32\r
+       test    eax,eax\r
+       jns     .TMPL_processor_selection.advance\r
+       and     ecx,not (CPU64_CAPABILITY_ALL and (1 shl 32 - 1))\r
+       and     ebx,not (CPU64_CAPABILITY_ALL shr 32)\r
+       jmp     .TMPL_processor_selection.advance\r
+    .TMPL_processor_selection.copro_sel.all:\r
+       cmp     dx,copro_sel\r
+       jnz     .TMPL_not_matched\r
+       or      ecx,COPRO_CAPABILITY_ALL\r
+       test    eax,eax\r
+       jns     .TMPL_processor_selection.advance\r
+       and     ecx,not COPRO_CAPABILITY_ALL\r
+       jmp     .TMPL_processor_selection.advance\r
+    .TMPL_size_1:\r
+       mov     [operand_size],1\r
+       jmp     .TMPL_okay\r
+    .TMPL_size_2:\r
+       mov     [operand_size],2\r
+       jmp     .TMPL_okay\r
+    .TMPL_size_4:\r
+       mov     [operand_size],4\r
+       jmp     .TMPL_okay\r
+    .TMPL_size_8:\r
+       mov     [operand_size],8\r
+       jmp     .TMPL_okay\r
+    .TMPL_size_16:\r
+       mov     [operand_size],16\r
+       jmp     .TMPL_okay\r
+    .TMPL_size_32:\r
+       mov     [operand_size],32\r
+       jmp     .TMPL_okay\r
+\r
+ARM_code16_directive:\r
+       call    ARM_generic_mode_checks\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_mode_change_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       mov     [code_type],CPU_ACTIVITY_THUMB_NON_UAL\r
+       jmp     instruction_assembled\r
+\r
+ARM_thumb_directive:\r
+       call    ARM_generic_mode_checks\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_mode_change_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       mov     [code_type],CPU_ACTIVITY_THUMB_UAL\r
+       jmp     instruction_assembled\r
+\r
+ARM_itauto_directive:\r
+       or      [it_control],IT_MODE_AUTO\r
+       xor     eax,eax\r
+       mov     [current_IT_block],eax\r
+       mov     [potential_IT_anchor],eax\r
+       jmp     instruction_assembled\r
+ARM_itnoauto_directive:\r
+       and     [it_control],not IT_MODE_AUTO\r
+       xor     eax,eax\r
+       mov     [current_IT_block],eax\r
+       jmp     instruction_assembled\r
+\r
+ARM_thumbee_directive:\r
+       call    ARM_generic_mode_checks\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_mode_change_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       mov     [code_type],CPU_ACTIVITY_THUMB_UAL + CPU_ACTIVITY_THUMBEE\r
+       jmp     instruction_assembled\r
+\r
+ARM_code32_directive:\r
+       call    ARM_generic_mode_checks\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_mode_change_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       mov     [code_type],CPU_ACTIVITY_ARM\r
+       jmp     instruction_assembled\r
+\r
+ARM_code64_directive:\r
+       call    ARM_generic_mode_checks\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_mode_change_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       mov     [code_type],CPU_ACTIVITY_ARM64\r
+       jmp     instruction_assembled\r
+\r
+ARM_coprocessor_directive:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>,\                                    ;0=imm\r
+       <TMPL_copro_sel>                                ;1=imm\r
+       mov     ecx,[immediate_value]\r
+       cmp     al,1\r
+       je      .selected\r
+       and     ecx,COPRO_CAPABILITY_DEFAULT\r
+    .selected:\r
+       mov     [copro_capability_flags],ecx\r
+       jmp     instruction_assembled\r
+\r
+ARM_processor_directive:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>,\                                    ;0=imm\r
+       <TMPL_cpu_sel>                                  ;1=imm\r
+       mov     ecx,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       cmp     al,1\r
+       je      .selected\r
+       and     ecx,CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1)\r
+       and     edx,CPU_CAPABILITY_DEFAULT shr 32\r
+    .selected:\r
+       mov     [cpu_capability_flags],ecx\r
+       mov     [cpu_capability_flags2],edx\r
+       jmp     instruction_assembled\r
+\r
+ARM_format_directive:\r
+       cmp     dword[esi],05018h + 0c019h shl 16       ;"elf dwarf"\r
+       jnz     format_directive\r
+       cmp     word[esi+4],01d19h                      ;"executable"\r
+       jnz     format_directive\r
+       cmp     edi,[code_start]\r
+       jne     unexpected_instruction\r
+       mov     edx,[addressing_space]\r
+       test    byte [edx+0Ah],1\r
+       jne     unexpected_instruction\r
+       cmp     [output_format],0\r
+       jne     unexpected_instruction\r
+       mov     [format_flags],5        ;set to DWARF(4) + executable(1)\r
+       mov     [output_format],5       ;set to ELF\r
+       mov     edx,edi\r
+       mov     ecx,34h shr 2\r
+       lea     eax,[edi+ecx*4]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       xor     eax,eax\r
+       rep     stosd\r
+       mov     dword[edx],7fh + 'ELF' shl 8\r
+       mov     al,1\r
+       mov     [edx+4],al\r
+       mov     [edx+5],al\r
+       mov     [edx+6],al\r
+       mov     byte[edx+10h],2         ;e_type\r
+       mov     byte[edx+12h],40        ;machine type ARM\r
+       mov     [edx+14h],al            ;e_version\r
+       mov     dword[edx+024h],02000016h ;e_flags\r
+       mov     byte[edx+28h],34h       ;e_ehsize\r
+       mov     byte[edx+2ah],20h       ;e_phentsize\r
+       mov     byte[edx+2eh],28h       ;e_shentsize\r
+       mov     [code_type],ARM_code\r
+       add     esi,6\r
+       mov     [image_base],0\r
+       cmp     byte[esi],80h\r
+       jne     .base_ok\r
+       lodsw\r
+       cmp     ah,'('\r
+       jne     invalid_argument\r
+       cmp     byte[esi],'.'\r
+       je      invalid_value\r
+       push    edx\r
+       call    get_dword_value\r
+       cmp     [value_type],0\r
+       jne     invalid_use_of_symbol\r
+       mov     [image_base],eax\r
+       pop     edx\r
+    .base_ok:\r
+       mov     ebx,edi\r
+       mov     ecx,20h shr 2\r
+       cmp     [current_pass],0\r
+       je      .init_sections\r
+       imul    ecx,[number_of_sections]\r
+    .init_sections:\r
+       xor     eax,eax\r
+       rep     stosd\r
+       mov     [number_of_sections],0\r
+       mov     ecx,edi\r
+       sub     ecx,[code_start]\r
+       mov     eax,[image_base]\r
+       mov     byte[ebx],1             ;p_type\r
+       mov     [ebx+4],ecx             ;file offset\r
+       mov     [ebx+8],eax             ;p_vaddr\r
+       mov     [ebx+0ch],eax           ;p_paddr\r
+       mov     byte[ebx+18h],7         ;p_flags\r
+       mov     word[ebx+1ch],20h       ;p_align\r
+       mov     [edx+18h],eax           ;e_entry\r
+       or      edx,-1\r
+       mov     cl,-1\r
+       not     eax\r
+       add     eax,1\r
+       adc     edx,0\r
+       adc     cl,0\r
+       add     eax,edi\r
+       adc     edx,0\r
+       mov     ebx,[addressing_space]\r
+       movzx   ecx,cl\r
+       mov     [ebx+0x00],eax\r
+       mov     [ebx+0x04],edx\r
+       mov     [ebx+0x08],ecx\r
+       mov     dword[ebx+0x10],0\r
+       mov     dword[ebx+0x14],0\r
+       mov     [ebx+0x18],edi\r
+       mov     dword[ebx+0x1c],0\r
+       mov     [symbols_stream],edi\r
+       jmp     instruction_assembled\r
+\r
+ARM_section_directive:\r
+       cmp     [output_format],5\r
+       jnz     section_directive\r
+       test    [format_flags],4\r
+       jz      section_directive\r
+       mov     eax,[addressing_space]\r
+       test    byte[eax+0x0a],1\r
+       jne     illegal_instruction\r
+    ;first we close the current section\r
+       cmp     [number_of_sections],0\r
+       jz      .first_section\r
+       call    ARM_finish_elf_segment\r
+       jmp     .next_section\r
+    .first_section:\r
+       cmp     edi,[symbols_stream]    ;has some code already been emitted?\r
+       jnz     ERROR_code_is_not_in_a_section\r
+       mov     eax,[image_base]\r
+    .next_section:\r
+       push    eax\r
+       mov     ebx,[number_of_sections]\r
+       shl     ebx,5\r
+       add     ebx,[code_start]\r
+       add     ebx,34h\r
+       cmp     ebx,[symbols_stream]\r
+       jb      .new_section_okay\r
+       mov     ebx,[symbols_stream]\r
+       sub     ebx,20h\r
+       mov     [next_pass_needed],-1\r
+    .new_section_okay:\r
+       push    edi\r
+       mov     edi,ebx\r
+       mov     ecx,20h shr 2\r
+       xor     eax,eax\r
+       rep     stosd\r
+       pop     edi\r
+       pop     ecx\r
+       mov     eax,edi\r
+       sub     eax,[code_start]\r
+       mov     [ebx+04h],eax           ;p_offset\r
+       mov     [ebx+08h],ecx           ;p_vaddr\r
+       mov     dword[ebx+0ch],0        ;p_paddr\r
+       lodsw\r
+       cmp     ax,'('\r
+       jne     ERROR_expecting_section_name\r
+       mov     [ebx],esi               ;we use p_type to temporarily store the string offset\r
+       mov     ecx,[esi]\r
+       lea     esi,[esi+4+ecx+1]\r
+    .next_attribute:\r
+       cmp     byte[esi],8Ch\r
+       jz      .section_alignment\r
+       cmp     byte[esi],80h\r
+       jz      .section_at\r
+       cmp     byte[esi],19h\r
+       jnz     .section_attributes_done\r
+       lodsw\r
+       sub     ah,28\r
+       jbe     invalid_argument\r
+       cmp     ah,1\r
+       je      .set_flag\r
+       cmp     ah,3\r
+       ja      invalid_argument\r
+       xor     ah,1\r
+       cmp     ah,2\r
+       je      .set_flag\r
+       inc     ah\r
+    .set_flag:                         ;at least one flag required\r
+       test    [ebx+18h],ah\r
+       jnz     ERROR_duplicate_flag_setting\r
+       or      [ebx+18h],ah\r
+       jmp     .next_attribute\r
+    .section_alignment:                        ;required\r
+       inc     esi\r
+       lodsb\r
+       cmp     al,'('\r
+       jne     invalid_argument\r
+       cmp     byte[esi],'.'\r
+       je      invalid_value\r
+       push    ebx\r
+       call    get_dword_value\r
+       pop     ebx\r
+       cmp     [value_type],0\r
+       jne     ERROR_invalid_use_of_symbol_in_align\r
+       mov     edx,eax\r
+       dec     edx\r
+       test    eax,edx\r
+       jnz     invalid_value\r
+       test    eax,eax\r
+       jz      invalid_value\r
+       xchg    [ebx+1ch],eax           ;p_align\r
+       test    eax,eax\r
+       jnz     ERROR_duplicate_align_setting\r
+       jmp     .next_attribute\r
+    .section_at:                       ;optional\r
+       lodsw\r
+       cmp     ah,'('\r
+       jne     invalid_argument\r
+       cmp     byte[esi],'.'\r
+       je      invalid_value\r
+       push    ebx\r
+       call    get_dword_value\r
+       pop     ebx\r
+       cmp     [value_type],0\r
+       jne     ERROR_invalid_use_of_symbol_in_at\r
+       mov     [ebx+0ch],eax           ;p_paddr\r
+       or      dword[ebx+018h],1 shl 31\r
+       jmp     .next_attribute\r
+    .section_attributes_done:\r
+       test    byte[ebx+018h],-1       ;p_flags\r
+       jz      ERROR_section_flags_zero\r
+       mov     ecx,[ebx+01ch]          ;p_align\r
+       sub     ecx,1\r
+       js      ERROR_section_align_zero\r
+       test    dword[ebx+018h],1 shl 31\r
+       jz      .no_at_specified\r
+       and     dword[ebx+018h],not (1 shl 31)\r
+       mov     eax,[ebx+0ch]           ;p_paddr\r
+       test    eax,ecx\r
+       jnz     ERROR_section_at_not_aligned\r
+       jmp     .finish\r
+    .no_at_specified:\r
+       mov     eax,[ebx+08h]           ;p_vaddr\r
+       add     eax,ecx\r
+       not     ecx\r
+       and     eax,ecx\r
+       mov     [ebx+0ch],eax           ;p_paddr\r
+    .finish:\r
+       mov     [ebx+08h],eax           ;p_vaddr\r
+       or      edx,-1\r
+       mov     cl,-1\r
+       neg     eax\r
+       cmc\r
+       adc     edx,0\r
+       adc     cl,0\r
+       add     eax,edi\r
+       adc     edx,0\r
+       adc     cl,0\r
+       push    eax ecx edx\r
+       call    create_addressing_space\r
+       pop     edx ecx eax\r
+       mov     ebx,[addressing_space]\r
+       mov     [ebx+0x00],eax\r
+       mov     [ebx+0x04],edx\r
+       mov     [ebx+0x08],cl\r
+       inc     [number_of_sections]\r
+       jmp     instruction_assembled\r
+\r
+ARM_finish_elf_segment:\r
+    ;called by close_elf after the last line is assembled\r
+    ;we must patch it to properly close the last section\r
+       cmp     [output_format],5\r
+       jnz     .not_my_format\r
+       test    [format_flags],4\r
+       jz      .not_my_format\r
+       mov     eax,[code_start]\r
+       mov     ecx,[eax]\r
+       cmp     ecx,7fh + 'ELF' shl 8\r
+       jnz     .done\r
+       mov     ebx,[number_of_sections]\r
+       dec     ebx\r
+       shl     ebx,5\r
+       lea     ebx,[ebx+eax+0x34]\r
+       cmp     ebx,[symbols_stream]\r
+       jb      .exe_section_ok\r
+       mov     ebx,[symbols_stream]\r
+       sub     ebx,20h\r
+    .exe_section_ok:\r
+       mov     edx,edi                 ;edx=the original data end\r
+       mov     eax,edi\r
+       mov     ecx,[addressing_space]\r
+       sub     eax,[ecx+0x18]          ;length of code in this section\r
+       mov     ecx,[ebx+01ch]          ;align\r
+       sub     ecx,1\r
+       jc      .align_done\r
+       and     eax,ecx\r
+       jz      .align_done\r
+       not     eax\r
+       lea     eax,[eax+ecx+2]\r
+       add     eax,edi\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       xor     ecx,ecx\r
+    .align:\r
+       mov     dword[edi],ecx\r
+       add     edi,4\r
+       cmp     edi,eax\r
+       jb      .align\r
+       mov     edi,eax                 ;edi=the aligned data end\r
+    .align_done:\r
+       mov     eax,edi\r
+       sub     eax,[code_start]        ;offset into file position of emitted code on disk\r
+       sub     eax,[ebx+4]             ;length code in this section\r
+       cmp     edx,[undefined_data_end]\r
+       jne     .size_ok\r
+       mov     edi,[undefined_data_start]\r
+       mov     dword[edi],0\r
+       mov     ecx,[addressing_space]\r
+       sub     edi,[ecx+0x00]          ;length of initialised code in this section\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[ecx+0x00]\r
+    .size_ok:\r
+       mov     [ebx+14h],eax           ;p_memsz\r
+       mov     eax,edi\r
+       sub     eax,[code_start]        ;offset into file position of emitted code on disk\r
+       sub     eax,[ebx+4]             ;length code in this section\r
+       mov     [ebx+10h],eax           ;p_filesz\r
+       mov     eax,[ebx+8]             ;p_vaddr\r
+       add     eax,[ebx+14h]           ;p_memsz\r
+    ;return eax = desired p_vaddr for next section\r
+    .done:\r
+       ret\r
+    .not_my_format:\r
+       mov     ebx,[code_start]\r
+       mov     dword[ebx+024h],0202h   ;e_flags\r
+    .patch_start:\r
+       finish_elf_exe_patch_code\r
+       jmp     finish_elf_segment+($-.patch_start)\r
+\r
+ARM_sections_added=7\r
+\r
+ARM_close_dwarf:\r
+;this is called after the assembler has finished\r
+       cmp     [output_format],3       ;pe\r
+       jz      ARM_close_pe\r
+       cmp     [output_format],5       ;elf\r
+       jnz     .ret\r
+       test    [format_flags],4\r
+       jz      .ret\r
+       mov     ebx,[code_start]\r
+       mov     eax,edi\r
+       sub     eax,ebx\r
+       mov     [ebx+020h],eax          ;e_shoff\r
+       movzx   eax,word[ebx+02ch]      ;e_phmnum\r
+       add     eax,ARM_sections_added  ;we add some sections\r
+       mov     [ebx+30h],ax            ;e_shnum\r
+       lea     ecx,[eax*8]\r
+       sub     vsp,vcx\r
+       mov     vbp,vsp\r
+    ;build the .shstrtab table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vax*8+4-ARM_sections_added*8],edx\r
+       xor     al,al\r
+       stosb\r
+       xor     ecx,ecx\r
+    .next_code_section:\r
+       cmp     cx,[ebx+02ch]           ;e_phmnum\r
+       jae     .code_section_names_done\r
+       mov     edx,ecx\r
+       shl     edx,5\r
+       add     edx,[ebx+01ch]          ;e_phoff\r
+       add     edx,[code_start]\r
+       mov     eax,1\r
+       xchg    eax,[edx]               ;p_type\r
+       cmp     eax,1\r
+       jnz     .code_section_name_found\r
+       mov     eax,ARM_string_noname_section\r
+    .code_section_name_found:\r
+       mov     edx,[edx+04h]           ;p_offset\r
+       mov     [vbp+vcx*8+4],edx\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       jmp     .next_code_section\r
+    .code_section_names_done:\r
+       lea     eax,[ecx+1]\r
+       mov     word[ebx+032h],ax       ;e_shstrndx\r
+       mov     eax,ARM_string_shstrtab\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       mov     eax,ARM_string_debug_abbrev\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       mov     eax,ARM_string_debug_info\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       mov     eax,ARM_string_debug_line\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       mov     eax,ARM_string_symtab\r
+       call    .add_string_to_shstrtab\r
+       add     ecx,1\r
+       mov     eax,ARM_string_strtab\r
+       call    .add_string_to_shstrtab\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[code_start]\r
+       sub     ecx,ARM_sections_added-3\r
+    ;build the .debug_abbrev table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vcx*8+4],edx\r
+       mov     esi,ARM_data_debug_abbrev\r
+       mov     edx,ecx\r
+       mov     ecx,ARM_data_debug_abbrev_len\r
+       lea     eax,[edi+ecx+010h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[code_start]\r
+       lea     ecx,[edx+1]\r
+    ;build the .debug_info table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vcx*8+4],edx\r
+       mov     esi,ARM_data_debug_info\r
+       mov     edx,ecx\r
+       mov     ecx,ARM_data_debug_info_len\r
+       lea     eax,[edi+ecx+010h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       call    .get_top_level_file_name\r
+       mov     ecx,esi\r
+       test    byte[esi],-1\r
+       jz      .top_level_file_done\r
+    .top_level_file_loop:\r
+       add     esi,1\r
+       test    byte[esi],-1\r
+       jnz     .top_level_file_loop\r
+    .top_level_file_done:\r
+       sub     esi,ecx\r
+       xchg    esi,ecx\r
+       lea     eax,[edi+ecx+010h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       xor     al,al\r
+       stosb\r
+       mov     esi,ARM_data_debug_producer\r
+       mov     ecx,ARM_data_debug_producer_len\r
+       lea     eax,[edi+ecx+020h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       mov     eax,[image_base]\r
+       stosd           ;low_pc\r
+       mov     eax,-1\r
+       stosd           ;high_pc\r
+       xor     eax,eax\r
+       stosd           ;stmt_list\r
+       stosb\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       mov     eax,edi\r
+       lea     ecx,[edx+1]\r
+       sub     eax,[vbp+vcx*8+4-8]\r
+       add     edi,[code_start]\r
+       lea     edx,[eax-4]\r
+       neg     eax\r
+       mov     [edi+eax],edx\r
+    ;build the .debug_line table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vcx*8+4],edx\r
+       push    ecx\r
+       mov     esi,ARM_data_debug_line_prologue\r
+       mov     ecx,ARM_data_debug_line_prologue_len\r
+       lea     eax,[edi+ecx+010h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       PUSH    vbp\r
+       call    ARM_debug_add_file_names\r
+       POP     vbp\r
+       mov     eax,[esp]\r
+       mov     eax,[vbp+vax*8+4]\r
+       add     eax,[code_start]\r
+       mov     ebx,edi\r
+       sub     ebx,eax\r
+       sub     ebx,10\r
+       mov     [eax+6],ebx\r
+       PUSH    vbp\r
+       call    ARM_debug_add_line_info\r
+       POP     vbp\r
+       pop     ecx\r
+       sub     edi,[code_start]\r
+       mov     eax,edi\r
+       add     ecx,1\r
+       sub     eax,[vbp+vcx*8+4-8]\r
+       add     edi,[code_start]\r
+       lea     edx,[eax-4]\r
+       neg     eax\r
+       mov     [edi+eax],edx\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[code_start]\r
+    ;build the .symtab table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vcx*8+4],edx\r
+       push    ecx\r
+       PUSH    vbp\r
+       lea     eax,[edi+20h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       xor     eax,eax\r
+       stosd\r
+       stosd\r
+       stosd\r
+       stosd\r
+       call    ARM_make_code_identifier_table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [first_global_symbol],edx\r
+       call    ARM_make_symbol_symtab\r
+       POP     vbp\r
+       pop     ecx\r
+       mov     edx,[first_global_symbol]\r
+       sub     edx,[vbp+vcx*8+4]\r
+       mov     [first_global_symbol],edx\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[code_start]\r
+       add     ecx,1\r
+    ;build the .strtab table\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       mov     [vbp+vcx*8+4],edx\r
+       push    ecx\r
+       call    ARM_make_symbol_strtab\r
+       pop     ecx\r
+       mov     dword[edi],0\r
+       sub     edi,[code_start]\r
+       add     edi,3\r
+       and     edi,not 3\r
+       add     edi,[code_start]\r
+       add     ecx,1\r
+       mov     ebx,[code_start]\r
+       mov     edx,edi\r
+       sub     edx,ebx\r
+       mov     [vbp+vcx*8+4],edx\r
+       mov     [ebx+020h],edx          ;e_shoff\r
+    ;zero the new section headers\r
+       movzx   ecx,word[ebx+30h]       ;e_shnum\r
+       imul    ecx,28h shr 2\r
+       lea     edx,[ecx*4-28h]         ;skip the null section header\r
+       lea     eax,[edi+ecx+10h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       xor     eax,eax\r
+       rep     stosd\r
+       sub     edi,edx\r
+    ;place_the code section headers\r
+       xor     ecx,ecx\r
+    .next_code_placement:\r
+       cmp     cx,[ebx+02ch]           ;e_phmnum\r
+       jae     .code_section_placement_done\r
+       mov     edx,ecx\r
+       shl     edx,5\r
+       add     edx,[ebx+01ch]          ;e_phoff\r
+       add     edx,[code_start]\r
+       mov     eax,[vbp+vcx*8]\r
+       mov     [edi+00h],eax           ;sh_name\r
+       mov     byte[edi+04h],1         ;sh_type\r
+       mov     eax,[edx+018h]          ;p_flags\r
+       test    al,2                    ;test write flag\r
+       setnz   ah\r
+       and     al,1\r
+       shl     al,2\r
+       or      al,ah\r
+       or      al,2\r
+       movzx   eax,al\r
+       mov     [edi+08h],eax           ;sh_flags\r
+       mov     eax,[edx+08h]           ;p_vaddr\r
+       mov     [edi+0ch],eax           ;sh_addr\r
+       mov     eax,[edx+04h]           ;p_offset\r
+       mov     [edi+010h],eax          ;sh_offset\r
+       mov     eax,[edx+010h]          ;p_filesz\r
+       mov     [edi+014h],eax          ;sh_size\r
+       mov     eax,[edx+01ch]          ;p_align\r
+       mov     [edi+020h],eax          ;sh_addralign\r
+       add     edi,028h\r
+       add     ecx,1\r
+       jmp     .next_code_placement\r
+    .code_section_placement_done:\r
+    ;place the .shstrtab section header\r
+       mov     dl,3\r
+       call    .make_section_header\r
+    ;place the .debug_abbrev section header\r
+       mov     dl,1\r
+       call    .make_section_header\r
+    ;place the .debug_info section header\r
+       mov     dl,1\r
+       call    .make_section_header\r
+    ;place the .debug_line section header\r
+       mov     dl,1\r
+       call    .make_section_header\r
+    ;place the .symtab section header\r
+       mov     dl,2\r
+       call    .make_section_header\r
+       mov     edx,[first_global_symbol]\r
+       lea     eax,[ecx+1]                     ;index to the next section (.strtab)\r
+       mov     [edi-28h+018h],eax              ;sh_link\r
+       shr     edx,4\r
+       mov     [edi-28h+01ch],edx              ;sh_info\r
+       mov     byte[edi-28h+020h],04h          ;sh_addralign\r
+       mov     byte[edi-28h+024h],10h          ;sh_size\r
+    ;place the .strtab section header\r
+       mov     dl,3\r
+       call    .make_section_header\r
+    .done:\r
+       movzx   eax,word[ebx+02ch]      ;e_phmnum\r
+       add     eax,ARM_sections_added\r
+       lea     vsp,[vbp+vax*8]\r
+    .ret:\r
+       ret\r
+    .add_string_to_shstrtab:\r
+    ;ecx=section number\r
+    ;eax=pointer to string\r
+       push    ecx\r
+       mov     edx,edi\r
+       sub     edx,[code_start]\r
+       sub     edx,[ebx+020h]          ;s_shoff\r
+       mov     [vbp+vcx*8],edx         ;store the string offset\r
+       mov     ecx,[eax]\r
+       lea     esi,[edi+ecx+010h]\r
+       cmp     esi,[tagged_blocks]\r
+       jae     out_of_memory\r
+       lea     esi,[eax+4]\r
+       rep     movsb\r
+       xor     al,al\r
+       stosb\r
+       pop     ecx\r
+       ret\r
+    .make_section_header:\r
+       mov     eax,[vbp+vcx*8]\r
+       mov     [edi+00h],eax           ;sh_name\r
+       mov     [edi+04h],dl            ;sh_type\r
+       mov     eax,[vbp+vcx*8+4]\r
+       mov     dword[edi+010h],eax     ;sh_offset\r
+       sub     eax,[vbp+vcx*8+4+8]\r
+       neg     eax\r
+       mov     [edi+014h],eax          ;sh_size\r
+       add     edi,028h\r
+       add     ecx,1\r
+       ret\r
+    .get_top_level_file_name:\r
+       mov     esi,[source_start]\r
+       mov     esi,[esi+1]\r
+       mov     esi,[esi]\r
+       ret\r
+\r
+ARM_close_pe:\r
+       mov     ebx,[code_start]        ;ebx points to PE header\r
+  ;calculate size of code\r
+       movzx   eax,word[ebx+0x14]\r
+       lea     edx,[ebx+eax+0x18]      ;edx points to section headers\r
+       xor     eax,eax\r
+       xor     ecx,ecx\r
+       cmp     cx,[ebx+6]\r
+       jae     .code_size_known\r
+    .code_size_loop:\r
+       test    dword[edx+0x24],0x20\r
+       jz      .next_code_section\r
+       add     eax,[edx+0x10]\r
+       cmp     dword[ebx+0x18+20],0\r
+       jnz     .next_code_section\r
+       mov     esi,[edx+0xc]           ;get virtual address\r
+       mov     [ebx+0x18+20],esi       ;update base of code\r
+    .next_code_section:\r
+       add     edx,0x28\r
+       inc     ecx\r
+       cmp     cx,[ebx+6]\r
+       jb      .code_size_loop\r
+    .code_size_known:\r
+       mov     [ebx+0x18+4],eax        ;update the size of code\r
+  ;calculate size of initialised data\r
+       movzx   eax,word[ebx+0x14]\r
+       lea     edx,[ebx+eax+0x18]      ;edx points to section headers\r
+       xor     eax,eax\r
+       xor     ecx,ecx\r
+       cmp     cx,[ebx+6]\r
+       jae     .initialised_size_known\r
+    .initialised_size_loop:\r
+       test    dword[edx+0x24],0x40\r
+       jz      .next_initialised_section\r
+       add     eax,[edx+0x10]\r
+       cmp     dword[ebx+0x18+24],0\r
+       jnz     .next_initialised_section\r
+       mov     esi,[edx+0xc]           ;get virtual address\r
+       mov     [ebx+0x18+24],esi       ;update base of data\r
+    .next_initialised_section:\r
+       add     edx,0x28\r
+       inc     ecx\r
+       cmp     cx,[ebx+6]\r
+       jb      .initialised_size_loop\r
+    .initialised_size_known:\r
+       mov     [ebx+0x18+8],eax        ;update the size of initialised data\r
+  ;calculate size of uninitialised data\r
+       movzx   eax,word[ebx+0x14]\r
+       lea     edx,[ebx+eax+0x18]      ;edx points to section headers\r
+       xor     eax,eax\r
+       xor     ecx,ecx\r
+       cmp     cx,[ebx+6]\r
+       jae     .uninitialised_size_known\r
+    .uninitialised_size_loop:\r
+       test    dword[edx+0x24],0x80\r
+       jz      .next_uninitialised_section\r
+       add     eax,[edx+0x8]\r
+       sub     eax,[edx+0x10]\r
+    .next_uninitialised_section:\r
+       add     edx,0x28\r
+       inc     ecx\r
+       cmp     cx,[ebx+6]\r
+       jb      .uninitialised_size_loop\r
+    .uninitialised_size_known:\r
+       mov     [ebx+0x18+12],eax       ;update the size of uninitialised data\r
+  ;update relocs stripped flag\r
+       cmp     dword[ebx+0x78+5*8+4],0\r
+       jz      .checksum\r
+       and     word[ebx+0x16],not 1\r
+    .checksum:\r
+       mov     ecx,0x10\r
+       mov     dword[ebx+0x58],0\r
+       jmp     directory_ok            ;recompute checksum and return\r
+\r
+ARM_start_line_processing:\r
+       add     edi,0fh\r
+       and     edi,not 0fh\r
+       cmp     edi,[tagged_blocks]\r
+       jae     out_of_memory\r
+       mov     eax,[labels_list]\r
+       mov     [tagged_blocks],eax\r
+       mov     eax,[additional_memory]\r
+       mov     [free_additional_memory],eax\r
+       mov     eax,[additional_memory_end]\r
+       mov     [structures_buffer],eax\r
+       mov     esi,[source_start]\r
+       mov     [code_start],edi\r
+       xor     eax,eax\r
+       mov     dword [adjustment],eax\r
+       mov     dword [adjustment+4],eax\r
+       mov     [addressing_space],eax\r
+       mov     [error_line],eax\r
+       mov     [counter],eax\r
+       mov     [format_flags],eax\r
+       mov     [number_of_relocations],eax\r
+       mov     [undefined_data_end],eax\r
+       mov     [file_extension],eax\r
+       mov     [next_pass_needed],al\r
+       mov     [output_format],al\r
+       mov     [adjustment_sign],al\r
+       mov     [code_type],ARM_code\r
+       call    init_addressing_space\r
+       inc     [current_pass]\r
+       mov     ax,[current_pass]\r
+       cmp     ax,[passes_limit]\r
+       je      code_cannot_be_generated\r
+       ret\r
+\r
+ARM_debug_add_file_names:\r
+    ;file names are compared by string and not address,\r
+    ;this is because it is possible to include a file more than once,\r
+    ;then we would have duplicated entries in the table\r
+       push    [code_start]\r
+       push    edi\r
+       call    ARM_start_line_processing\r
+       mov     vbp,vsp\r
+       .neg1 = -1\r
+       push    .neg1   ;-4 total files\r
+       push    [input_file]\r
+    .line_loop:\r
+       cmp     byte[esi],0Fh\r
+       jne     .next_line\r
+       call    .find_source_line\r
+       mov     eax,[eax]\r
+       mov     ebx,[vbp-4]\r
+       test    ebx,ebx\r
+       jz      .add_file\r
+    .file_loop:\r
+       if __is_64\r
+               movsxd  rbx,ebx\r
+       end if\r
+       mov     ecx,[vbp-4+vbx*4]\r
+       cmp     eax,ecx\r
+       jz      .next_line\r
+    .char_loop:\r
+       mov     dl,[eax]\r
+       mov     dh,[ecx]\r
+       add     eax,1\r
+       add     ecx,1\r
+       cmp     dh,dl\r
+       jnz     .next_file\r
+       test    dl,dl\r
+       jnz     .char_loop\r
+       jmp     .next_line\r
+    .next_file:\r
+       call    .find_source_line\r
+       mov     eax,[eax]\r
+       add     ebx,1\r
+       jnz     .file_loop\r
+    .add_file:\r
+       mov     ebx,[vbp-4]\r
+       sub     ebx,1\r
+       mov     [vbp-4],ebx\r
+       call    .find_source_line\r
+       mov     eax,[eax]\r
+       push    eax\r
+    .next_line:\r
+       PUSH    vbp\r
+       call    assemble_line\r
+       POP     vbp\r
+       jnc     .line_loop\r
+       mov     edi,[vbp]\r
+       xor     edx,edx\r
+       cmp     edx,[vbp-4]\r
+       jle     .done\r
+    .copy_loop:\r
+       mov     esi,[vbp-8+vdx*4]\r
+       mov     ecx,[input_file]\r
+       cmp     ecx,esi\r
+       jnz     .not_top_level_source\r
+       test    byte[esi],-1\r
+       jz      .top_level_file_done\r
+    .top_level_file_loop:\r
+       add     esi,1\r
+       test    byte[esi],-1\r
+       jnz     .top_level_file_loop\r
+    .top_level_file_done:\r
+       sub     esi,ecx\r
+       xchg    esi,ecx\r
+       jmp     .copy\r
+    .not_top_level_source:\r
+       movzx   ecx,byte[esi-1]\r
+       sub     ecx,1\r
+       jns     .copy\r
+       mov     ecx,dword[esi-4]\r
+    .copy:\r
+       lea     eax,[edi+ecx+010h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       xor     eax,eax\r
+       stosd\r
+       sub     edx,1\r
+       cmp     edx,[vbp-4]\r
+       jg      .copy_loop\r
+    .done:\r
+       xor     al,al\r
+       stosb\r
+       mov     [vbp],edi\r
+       mov     vsp,vbp\r
+       cmp     [number_of_sections],0\r
+       jnz     .section_count_okay\r
+       inc     [number_of_sections]\r
+    .section_count_okay:\r
+       pop     edi\r
+       pop     [code_start]\r
+    .ret:\r
+       ret\r
+    .find_source_line:\r
+       mov     eax,[esi+1]\r
+    .next_source_link:\r
+       test    byte[eax+7],0x80\r
+       jz      .ret\r
+       mov     eax,[eax+12]\r
+       jmp     .next_source_link\r
+\r
+ARM_debug_add_line_info:\r
+       mov     ecx,[code_start]\r
+       mov     ecx,[ecx+0x38]\r
+       .16k = 16 shl 10\r
+       push    .16k            ;+20 initial buffer size\r
+       push    edi             ;+16 start of line data\r
+       push    ecx             ;+12 offset to first program byte\r
+       push    [code_start]    ;+8 real generated code\r
+       push    edi             ;+4 current output position for line data\r
+       add     eax,ARM_data_debug_line_prologue_len\r
+       push    eax             ;+0 file name buffer\r
+       mov     vbp,vsp\r
+    .restart:\r
+       add     edi,[vbp+20]\r
+       lea     eax,[edi+0x20]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       call    ARM_start_line_processing\r
+       push    1               ;-4 state machine file number\r
+       push    1               ;-8 state machine line number\r
+       push    0               ;-12 state machine address offset\r
+       push    0               ;-16 address before assembly\r
+       push    0               ;-20 address after assembly\r
+       push    0               ;-24 source line before assembly\r
+    .line_loop:\r
+       cmp     byte[esi],0x0f\r
+       jne     .skip_line\r
+       mov     ecx,[addressing_space]\r
+       test    byte[ecx+0x0a],1\r
+       jnz     .skip_line\r
+       mov     ecx,[ecx+0x00]\r
+       sub     ecx,edi\r
+       neg     ecx\r
+       mov     [vbp-16],ecx\r
+       mov     [vbp-24],esi\r
+       PUSH    vbp\r
+       call    assemble_line\r
+       POP     vbp\r
+       jc      .close\r
+       mov     ecx,[addressing_space]\r
+       test    byte[ecx+0x0a],1\r
+       jnz     .line_loop\r
+       mov     ecx,[ecx+0x00]\r
+       sub     ecx,edi\r
+       neg     ecx\r
+       mov     [vbp-20],ecx\r
+       call    .emit_line_data\r
+       jmp     .line_loop\r
+    .skip_line:\r
+       PUSH    vbp\r
+       call    assemble_line\r
+       POP     vbp\r
+       jnc     .line_loop\r
+    .close:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       sub     eax,[vbp-12]            ;current\r
+       call    .pc_far\r
+       mov     al,0                    ;extended opcode\r
+       call    .write_line_code\r
+       mov     al,1                    ;one byte\r
+       call    .write_line_code\r
+       mov     al,1                    ;end sequence\r
+       call    .write_line_code\r
+       mov     eax,[vbp+4]\r
+       cmp     eax,[code_start]\r
+       jbe     .close_okay\r
+       mov     edi,[vbp+16]\r
+       sub     eax,edi\r
+       mov     [vbp+4],edi\r
+       add     eax,0x100\r
+       mov     [vbp+20],eax            ;adjust the buffer size\r
+       mov     vsp,vbp\r
+       jmp     .restart\r
+    .close_okay:\r
+       lea     vsp,[vbp+4]\r
+       cmp     [number_of_sections],0\r
+       jnz     .section_count_okay\r
+       inc     [number_of_sections]\r
+    .section_count_okay:\r
+       pop     edi\r
+       pop     [code_start]\r
+       add     esp,12\r
+       ret\r
+    .emit_line_data:\r
+       mov     eax,[vbp+4]\r
+       lea     eax,[eax+20h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       mov     eax,edi\r
+       sub     eax,[code_start]\r
+       cmp     eax,[vbp+12]            ;any output yet?\r
+       jb      .ret\r
+       mov     eax,[vbp-20]\r
+       cmp     eax,[vbp-16]\r
+       je      .ret\r
+       call    .update_file\r
+       call    .update_address\r
+       jmp     .update_line\r
+    .update_file:\r
+       mov     edx,1 shl 16            ;start at file number 1\r
+       mov     ecx,[vbp]\r
+    .file_loop:\r
+       call    .find_source_line\r
+       mov     eax,[eax+0]             ;file name\r
+    .char_loop:\r
+       mov     dl,[eax]\r
+       mov     dh,[ecx]\r
+       add     eax,1\r
+       add     ecx,1\r
+       cmp     dh,dl\r
+       jnz     .next_file\r
+       test    dl,dl\r
+       jnz     .char_loop\r
+       jmp     .found_file\r
+    .next_file:\r
+       add     edx,1 shl 16            ;bump to next file\r
+       test    dh,dh\r
+       jz      .skip_null\r
+    .skip_loop:\r
+       add     ecx,1\r
+       mov     dh,[ecx]\r
+       test    dh,dh\r
+       jnz     .skip_loop\r
+    .skip_null:\r
+       add     ecx,4\r
+       cmp     byte[ecx],0\r
+       jnz     .file_loop\r
+       jmp     ERROR_line_processing_error\r
+    .found_file:\r
+       shr     edx,16\r
+       cmp     edx,[vbp-4]\r
+       jz      .ret\r
+    ;set a new file\r
+       mov     [vbp-4],edx\r
+       mov     al,4                    ;opcode 4: set file\r
+       call    .write_line_code\r
+       jmp     .emit_leb128\r
+    .update_address:\r
+       mov     eax,[vbp-16]            ;before\r
+       sub     eax,[vbp-12]            ;current\r
+       cmp     eax,40\r
+       jbe     .ret\r
+       cmp     eax,80\r
+       ja      .pc_far\r
+       add     dword[vbp-12],40\r
+       push    eax\r
+       mov     al,8                    ;opcode 8: const add pc\r
+       call    .write_line_code\r
+       pop     eax\r
+       sub     eax,40\r
+       ret\r
+    .pc_far:\r
+       add     [vbp-12],eax\r
+       test    eax,eax\r
+       js      .pc_negative\r
+       mov     edx,eax\r
+       mov     al,2                    ;opcode 2: advance pc\r
+       call    .write_line_code\r
+       call    .emit_leb128\r
+       xor     eax,eax\r
+       ret\r
+    .pc_negative:\r
+       mov     al,0                    ;extended opcode\r
+       call    .write_line_code\r
+       mov     al,5                    ;5 bytes\r
+       call    .write_line_code\r
+       mov     al,2                    ;set address\r
+       call    .write_line_code\r
+       mov     eax,[vbp-12]            ;LSB\r
+       call    .write_line_code\r
+       shr     eax,8\r
+       call    .write_line_code\r
+       shr     eax,8\r
+       call    .write_line_code\r
+       shr     eax,8                   ;MSB\r
+       call    .write_line_code\r
+       xor     eax,eax\r
+       ret\r
+    .update_line:\r
+       ;eax=address advance value\r
+       push    eax\r
+       call    .find_source_line\r
+       mov     edx,[eax+4]\r
+       sub     edx,[vbp-8]\r
+       add     [vbp-8],edx\r
+       pop     eax\r
+       cmp     edx,6\r
+       jb      .send_special_code\r
+    .send_line_advance:\r
+       push    eax\r
+       mov     al,3                    ;opcode 3: advance line\r
+       call    .write_line_code\r
+       call    .emit_signed_leb\r
+       xor     edx,edx\r
+       pop     eax\r
+       test    eax,eax\r
+       jnz     .send_special_code\r
+    .copy:\r
+       mov     al,1                    ;opcode 1: copy\r
+       jmp     .write_line_code\r
+    .send_special_code:\r
+       add     [vbp-12],eax\r
+       imul    eax,6\r
+       add     eax,edx\r
+       jz      .copy\r
+       add     eax,10                  ;special opcode\r
+       jmp     .write_line_code\r
+    .find_source_line:\r
+       mov     eax,[vbp-24]\r
+       mov     eax,[eax+1]\r
+    .next_source_link:\r
+       test    byte[eax+7],0x80\r
+       jz      .ret\r
+       mov     eax,[eax+12]\r
+       jmp     .next_source_link\r
+    .emit_leb128:\r
+       bsr     ecx,edx\r
+       jnz     .leb_calcu\r
+       or      ecx,-1\r
+    .leb_calcu:\r
+       add     ecx,1\r
+       jmp     .next_leb128\r
+    .emit_signed_leb:\r
+    ;edx is the value to emit\r
+       test    edx,edx\r
+       jns     .leb_pos\r
+       not     edx\r
+       bsr     ecx,edx\r
+       not     edx\r
+       jmp     .leb_bits\r
+    .leb_pos:\r
+       bsr     ecx,edx\r
+    .leb_bits:\r
+       jnz     .leb_calc\r
+       or      ecx,-1\r
+    .leb_calc:\r
+       add     ecx,2\r
+    .next_leb128:\r
+       mov     eax,edx\r
+       and     eax,0x7f\r
+       shr     edx,7\r
+       sub     ecx,7\r
+       jle     .write_line_code\r
+       or      al,0x80                 ;set continuation bit\r
+       call    .write_line_code\r
+       jmp     .next_leb128\r
+    .write_line_code:\r
+       mov     ebx,[vbp+4]\r
+       cmp     ebx,[code_start]\r
+       jae     .skip_overwrite\r
+       mov     [ebx],al\r
+    .skip_overwrite:\r
+       inc     ebx\r
+       mov     [vbp+4],ebx\r
+    .ret:\r
+       ret\r
+\r
+ARM_string_arm_code_offset     = 1\r
+ARM_string_thumb_code_offset   = 1+ARM_string_arm_code_offset+ARM_string_arm_code_identifier_len\r
+ARM_string_data_offset         = 1+ARM_string_thumb_code_offset+ARM_string_thumb_code_identifier_len\r
+ARM_string_thumbee_code_offset = 1+ARM_string_data_offset+ARM_string_data_identifier_len\r
+\r
+ARM_make_symbol_strtab:\r
+       mov     ebx,[code_start]\r
+       xor     al,al\r
+       stosb\r
+       mov     esi,ARM_string_arm_code_identifier\r
+       mov     ecx,ARM_string_arm_code_identifier_len\r
+       rep     movsb\r
+       stosb\r
+       mov     esi,ARM_string_thumb_code_identifier\r
+       mov     ecx,ARM_string_thumb_code_identifier_len\r
+       rep     movsb\r
+       stosb\r
+       mov     esi,ARM_string_data_identifier\r
+       mov     ecx,ARM_string_data_identifier_len\r
+       rep     movsb\r
+       stosb\r
+       mov     esi,ARM_string_thumbee_code_identifier\r
+       mov     ecx,ARM_string_thumbee_code_identifier_len\r
+       rep     movsb\r
+       stosb\r
+       mov     esi,[ebx-4]             ;esi=source of label data\r
+       mov     ebx,[ebx-8]             ;ebx=last address+1\r
+       cmp     esi,ebx\r
+       jae     .ret\r
+    .loop:\r
+       movzx   ecx,byte[esi]\r
+       lea     eax,[esi+1]\r
+       mov     edx,[esi+ecx+1]\r
+       lea     esi,[esi+ecx+5]\r
+       test    dword[edx+8],0100h\r
+       jz      .skip\r
+       xchg    esi,eax\r
+       lea     edx,[edi+ecx+10h]\r
+       cmp     edx,[tagged_blocks]\r
+       jae     out_of_memory\r
+       rep     movsb\r
+       xchg    esi,eax\r
+       xor     al,al\r
+       stosb\r
+    .skip:\r
+       cmp     esi,ebx\r
+       jb      .loop\r
+    .ret:\r
+       ret\r
+\r
+ARM_make_symbol_symtab:\r
+       mov     ebx,[code_start]\r
+       mov     esi,[ebx-4]             ;esi=source of label data\r
+       mov     ebx,[ebx-8]             ;ebx=last address+1\r
+       cmp     esi,ebx\r
+       jae     .ret\r
+       push    ebp\r
+       mov     ebp,1+ARM_string_arm_code_identifier_len+\\r
+                   1+ARM_string_thumb_code_identifier_len+\\r
+                   1+ARM_string_data_identifier_len+\\r
+                   1+ARM_string_thumbee_code_identifier_len+\\r
+                   1\r
+    .loop:\r
+       movzx   ecx,byte[esi]\r
+       mov     edx,[esi+ecx+1]\r
+       lea     esi,[esi+ecx+5]\r
+       test    dword[edx+8],0100h\r
+       jz      .skip\r
+       lea     eax,[edi+20h]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       mov     [edi],ebp               ;name\r
+       lea     ebp,[ebp+ecx+1]\r
+       mov     eax,[edx]\r
+       mov     [edi+4],eax             ;value\r
+       movzx   eax,byte[edx+10]\r
+       mov     [edi+8],eax             ;size\r
+       test    eax,eax\r
+       setz    al\r
+       movzx   eax,al\r
+       add     eax,1 + 1 shl 4         ;object = 1, function = 2 + binding global\r
+       mov     [edi+12],ax             ;binding type\r
+       mov     eax,[edx]\r
+    ;find the section associated with this label\r
+       mov     ecx,[code_start]\r
+       movzx   edx,word[ecx+02ch]      ;e_phnum\r
+       add     edx,1\r
+    .next_section:\r
+       sub     edx,1\r
+       je      .no_section\r
+       lea     ecx,[edx-1]\r
+       shl     ecx,5\r
+       add     ecx,[code_start]\r
+       cmp     eax,[ecx+034h+8]        ;p_vaddr\r
+       jb      .next_section\r
+       sub     eax,[ecx+034h+8]        ;p_vaddr\r
+       cmp     eax,[ecx+034h+14h]      ;p_memsz\r
+       jb      .section_found\r
+       add     eax,[ecx+034h+8]        ;p_vaddr\r
+       jmp     .next_section\r
+    .no_section:\r
+       xor     edx,edx\r
+    .section_found:\r
+       mov     word[edi+14],dx         ;section\r
+       add     edi,16\r
+    .skip:\r
+       cmp     esi,ebx\r
+       jb      .loop\r
+       pop     ebp\r
+    .ret:\r
+       ret\r
+\r
+ARM_make_code_identifier_table:\r
+       mov     ecx,[code_start]\r
+       mov     ecx,[ecx+38h]\r
+       .16k = 16 shl 10\r
+       push    .16k            ;+16 initial buffer size\r
+       push    edi             ;+12 start of data\r
+       push    ecx             ;+8 offset to first program byte\r
+       push    [code_start]\r
+       push    edi             ;+0 current output position\r
+       mov     vbp,vsp\r
+    .restart:\r
+       add     edi,[vbp+16]\r
+       lea     ebx,[edi+0x20]\r
+       cmp     ebx,[tagged_blocks]\r
+       jae     out_of_memory\r
+       call    ARM_start_line_processing\r
+       .neg1 = -1\r
+       push    .neg1   ;-4 last code type\r
+       push    .neg1   ;-8 this code type\r
+       push    .neg1   ;-12 this code address\r
+    .line_loop:\r
+       mov     edx,esi\r
+       cmp     byte[edx],0Fh\r
+       jnz     .check_data\r
+       add     edx,5\r
+    .check_data:\r
+    ;any data yet?\r
+       mov     eax,edi\r
+       sub     eax,[code_start]\r
+       cmp     eax,[vbp+8]\r
+       jb      .skip_line\r
+    .find_line:\r
+       mov     al,[edx]\r
+       cmp     al,1\r
+       jz      .do_line\r
+       cmp     al,2\r
+       jz      .do_value\r
+       cmp     al,3\r
+       jnz     .skip_line\r
+    .do_value:\r
+       add     edx,6\r
+       jmp     .find_line\r
+    .do_line:\r
+       mov     ecx,[addressing_space]\r
+       test    byte[ecx+0x0a],1\r
+       jnz     .skip_line\r
+       movzx   eax,word[edx+1]\r
+       mov     ecx,080h        ;data code type\r
+       cmp     eax,ARM_code_generator_start-instruction_handler\r
+       jb      .found_generator\r
+       movzx   ecx,[code_type]\r
+    .found_generator:\r
+       mov     [vbp-8],ecx\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       mov     [vbp-12],eax\r
+       PUSH    vbp\r
+       call    assemble_line\r
+       POP     vbp\r
+       lahf\r
+       mov     ecx,[vbp-8]\r
+       cmp     ecx,[vbp-4]\r
+       jz      .next_line\r
+       mov     edx,[addressing_space]\r
+       test    byte[edx+0x0a],1\r
+       jnz     .next_line\r
+       push    eax\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       cmp     eax,[vbp-12]\r
+       jz      .non_code_line\r
+       xchg    edi,[vbp]\r
+       lea     ebx,[edi+16]\r
+       cmp     ebx,[code_start]\r
+       jae     .skip_overwrite1\r
+       mov     [vbp-4],ecx\r
+       lea     edx,[edi+20h]\r
+       cmp     edx,[tagged_blocks]\r
+       jae     out_of_memory\r
+       mov     edx,ARM_string_data_offset\r
+       test    cl,cl\r
+       js      .found_generator2\r
+       mov     edx,ARM_string_arm_code_offset\r
+       test    ecx,CPU_ACTIVITY_ARM\r
+       jnz     .found_generator2\r
+       mov     edx,ARM_string_thumb_code_offset\r
+       test    ecx,CPU_ACTIVITY_THUMBEE\r
+       jz      .found_generator2\r
+       mov     edx,ARM_string_thumbee_code_offset\r
+    .found_generator2:\r
+       mov     eax,[vbp-12]\r
+       mov     [edi],edx               ;name\r
+       mov     [edi+4],eax             ;address\r
+       mov     dword[edi+8],0          ;length\r
+       mov     ecx,2\r
+       cmp     edx,ARM_string_data_offset\r
+       jnz     @f\r
+       mov     ecx,1\r
+    @@:        mov     [edi+12],cx             ;binding type\r
+    ;find the section associated with this address\r
+       mov     ecx,[vbp+4]\r
+       movzx   edx,word[ecx+02ch]      ;e_phnum\r
+       add     edx,1\r
+    .next_section:\r
+       sub     edx,1\r
+       je      .no_section\r
+       lea     ecx,[edx-1]\r
+       shl     ecx,5\r
+       add     ecx,[vbp+4]\r
+       cmp     eax,[ecx+034h+8]        ;p_vaddr\r
+       jb      .next_section\r
+       sub     eax,[ecx+034h+8]        ;p_vaddr\r
+       cmp     eax,[ecx+034h+14h]      ;p_memsz\r
+       jb      .section_found\r
+       add     eax,[ecx+034h+8]        ;p_vaddr\r
+       jmp     .next_section\r
+    .no_section:\r
+       xor     edx,edx\r
+    .section_found:\r
+       mov     word[edi+14],dx         ;section\r
+    .skip_overwrite1:\r
+       add     edi,16\r
+       xchg    edi,[vbp]\r
+    .non_code_line:\r
+       pop     eax\r
+    .next_line:\r
+       sahf\r
+       jmp     .finish_line\r
+    .skip_line:\r
+       PUSH    vbp\r
+       call    assemble_line\r
+       POP     vbp\r
+    .finish_line:\r
+       jnc     .line_loop\r
+       mov     ecx,[vbp-8]\r
+       test    cl,cl\r
+       js      .done\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       xchg    edi,[vbp]\r
+       lea     ebx,[edi+16]\r
+       cmp     ebx,[code_start]\r
+       jae     .skip_overwrite2\r
+       mov     edx,ARM_string_data_offset\r
+       mov     [edi],edx               ;name\r
+       mov     [edi+4],eax             ;address\r
+       mov     dword[edi+8],0          ;length\r
+       mov     word[edi+12],1          ;binding type\r
+       mov     word[edi+14],0          ;section\r
+    .skip_overwrite2:\r
+       add     edi,16\r
+       xchg    edi,[vbp]\r
+    .done:\r
+       mov     eax,[vbp]\r
+       cmp     eax,[code_start]\r
+       jb      .done_okay\r
+       mov     edi,[vbp+12]\r
+       mov     eax,[vbp]\r
+       sub     eax,edi\r
+       mov     [vbp],edi\r
+       add     eax,0x100\r
+       mov     [vbp+16],eax            ;adjust the buffer size\r
+       mov     vsp,vbp\r
+       jmp     .restart\r
+    .done_okay:\r
+       mov     vsp,vbp\r
+       cmp     [number_of_sections],0\r
+       jnz     .section_count_okay\r
+       inc     [number_of_sections]\r
+    .section_count_okay:\r
+       pop     edi\r
+       pop     [code_start]\r
+       add     esp,12\r
+       ret\r
+\r
+ARM_label_walker:\r
+       mov     edi,[code_start]\r
+       add     edi,4\r
+       push    edi\r
+       call    .walk\r
+       pop     esi\r
+       mov     ebx,edi\r
+       add     edi,0fh+8\r
+       and     edi,not 0fh\r
+       mov     [code_start],edi\r
+       mov     [edi-4],esi\r
+       mov     [edi-8],ebx\r
+       mov     [esi-4],eax\r
+       ret\r
+    .walk:\r
+       mov     edx,32+1\r
+       mov     ebx,hash_tree\r
+       xor     eax,eax\r
+       test    dword[ebx],-1\r
+       jz      .done\r
+    .recur:\r
+       mov     ebx,[ebx]\r
+       sub     edx,1\r
+       jz      .store\r
+       test    dword[ebx],-1\r
+       jz      .right\r
+       push    ebx\r
+       call    .recur\r
+       pop     ebx\r
+    .right:\r
+       add     ebx,4\r
+       test    dword[ebx],-1\r
+       jz      .done\r
+       call    .recur\r
+    .done:\r
+       add     edx,1\r
+       ret\r
+    .store:\r
+       add     eax,1           ;bump the label count\r
+       mov     esi,[ebx+4]\r
+       mov     esi,[esi+18h]   ;string text name\r
+       movzx   ecx,byte[esi-1] ;name length\r
+       mov     [edi],cl\r
+       add     edi,1\r
+       lea     esi,[edi+ecx+20h]\r
+       cmp     esi,[labels_list]\r
+       jae     out_of_memory\r
+       mov     esi,[ebx+4]\r
+       mov     esi,[esi+18h]   ;string text name\r
+       rep     movsb\r
+       lea     esi,[ebx+4]     ;offset to 24 byte data field\r
+       movsd\r
+       mov     ebx,[ebx]       ;next link?\r
+       test    ebx,ebx\r
+       jnz     .store\r
+       jmp     .done\r
+\r
+ARM_org_directive:\r
+       cmp     [output_format],5\r
+       jnz     org_directive\r
+       test    [format_flags],4\r
+       jz      org_directive\r
+       jmp     ERROR_org_not_allowed\r
+\r
+;we must supply this label for parser.inc to assemble\r
+\r
+prefix_instruction:    ;not used in ARM\r
+\r
+ARM_data_debug_abbrev:\r
+    ;this is the debug_abbrev table, it is the minimum requirement to make a complete table for AXD\r
+       db      1       ;abbrev code\r
+       db      11h     ;tag_compile_unit\r
+       db      1       ;has children\r
+       db      3,8     ;name,string\r
+       db      25h,8   ;producer,string\r
+       db      11h,1   ;low_pc,address\r
+       db      12h,1   ;high_pc,address\r
+       db      10h,6   ;stmt_list,data4\r
+       db      0       ;terminate child\r
+       db      0       ;no siblings\r
+ARM_data_debug_abbrev_len=$-ARM_data_debug_abbrev\r
+\r
+ARM_data_debug_producer:\r
+       db      'ARMv8 assembler core v',ARM_VERSION_STRING,' for flat assembler v',VERSION_STRING,' by revolution',0\r
+ARM_data_debug_producer_len=$-ARM_data_debug_producer\r
+\r
+ARM_data_debug_info:\r
+       dd      0       ;length\r
+       dw      2       ;version\r
+       dd      0       ;offset to abbrev table\r
+       db      4       ;address size\r
+       db      1       ;abbrev code\r
+ARM_data_debug_info_len=$-ARM_data_debug_info\r
+\r
+ARM_data_debug_line_prologue:\r
+    ;this defines the layout of the line numbers table\r
+       dd      0       ;total length\r
+       dw      2       ;version\r
+       dd      0       ;prologue length\r
+       db      1       ;minimum instruction length\r
+       db      1       ;default is statment\r
+       db      0       ;line base\r
+       db      6       ;line range\r
+       db      10      ;opcode base\r
+       db      0,1,1,1,1,0,0,0,0       ;standard opcode lengths\r
+       db      0       ;no include directories\r
+ARM_data_debug_line_prologue_len=$-ARM_data_debug_line_prologue\r
+\r
+ARM_string_arm_code_identifier:\r
+       db      '$a'\r
+       ARM_string_arm_code_identifier_len=$-ARM_string_arm_code_identifier\r
+ARM_string_thumb_code_identifier:\r
+       db      '$t'\r
+       ARM_string_thumb_code_identifier_len=$-ARM_string_thumb_code_identifier\r
+ARM_string_data_identifier:\r
+       db      '$d'\r
+       ARM_string_data_identifier_len=$-ARM_string_data_identifier\r
+ARM_string_thumbee_code_identifier:\r
+       db      '$t.x'\r
+       ARM_string_thumbee_code_identifier_len=$-ARM_string_thumbee_code_identifier\r
+ARM_string_shstrtab:\r
+       dd      ARM_string_shstrtab_len\r
+       db      '.shstrtab'\r
+       ARM_string_shstrtab_len=$-ARM_string_shstrtab-4\r
+ARM_string_debug_abbrev:\r
+       dd      ARM_string_debug_abbrev_len\r
+       db      '.debug_abbrev'\r
+       ARM_string_debug_abbrev_len=$-ARM_string_debug_abbrev-4\r
+ARM_string_debug_info:\r
+       dd      ARM_string_debug_info_len\r
+       db      '.debug_info'\r
+       ARM_string_debug_info_len=$-ARM_string_debug_info-4\r
+ARM_string_debug_line:\r
+       dd      ARM_string_debug_line_len\r
+       db      '.debug_line'\r
+       ARM_string_debug_line_len=$-ARM_string_debug_line-4\r
+ARM_string_symtab:\r
+       dd      ARM_string_symtab_len\r
+       db      '.symtab'\r
+       ARM_string_symtab_len=$-ARM_string_symtab-4\r
+ARM_string_strtab:\r
+       dd      ARM_string_strtab_len\r
+       db      '.strtab'\r
+       ARM_string_strtab_len=$-ARM_string_strtab-4\r
+ARM_string_noname_section:\r
+       dd      ARM_string_noname_section_len\r
+       db      '.flat'\r
+       ARM_string_noname_section_len=$-ARM_string_noname_section-4\r
+\r
+ARM_code_generator_start:\r
+\r
+;ARM/THUMB jump table\r
+\r
+INST_ARM64     equ es\r
+INST_ARM64S    equ fs\r
+INST_ARM64V    equ gs\r
+\r
+ARM_instruction_adc:\r
+       INST_ARM64S\r
+       dd      0x1a000000\r
+       dd      ARM64_dz_nz_mz\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_ADC shl 21\r
+       mov     ecx,0xe shl 28 + 0xa shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_add:\r
+       INST_ARM64S\r
+       dd      0x00000000\r
+       dd      ARM64_arithmetic1\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_ADD shl 21\r
+       mov     ecx,0xe shl 28 + 0x8 shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_addw:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_ADD shl 21\r
+       mov     ecx,0xf2000000\r
+       jmp     THUMB_rd_rn_imm12\r
+ARM_instruction_adr:\r
+       INST_ARM64\r
+       dd      0x10000000\r
+       dd      ARM64_adr\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_ADD shl 21\r
+       jmp     ARM_rd_target\r
+ARM_instruction_and:\r
+       INST_ARM64S\r
+       dd      0x00000000\r
+       dd      ARM64_arithmetic2\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_AND shl 21\r
+       mov     ecx,0xe shl 28 + 0x0 shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_asr:\r
+       INST_ARM64\r
+       dd      0x1ac02800\r
+       dd      ARM64_arithmetic3\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ASR shl 5\r
+       jmp     ARM_rd_rn_shift\r
+ARM_instruction_b:\r
+       INST_ARM64\r
+       dd      0x14000000\r
+       dd      ARM64_b\r
+       mov     edx,0x0a000000\r
+       jmp     ARM_target\r
+ARM_instruction_bfc:\r
+       mov     edx,0x07c0001f\r
+       mov     ecx,0xf36f0000\r
+       jmp     ARM_rd_imm_imm\r
+ARM_instruction_bfi:\r
+       INST_ARM64\r
+       dd      0x33000000\r
+       dd      ARM64_bfi\r
+       mov     edx,0x07c00010\r
+       mov     ecx,0xf3600000\r
+       jmp     ARM_rd_rn_imm_imm\r
+ARM_instruction_bic:\r
+       INST_ARM64S\r
+       dd      0x00200000\r
+       dd      ARM64_arithmetic2\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_BIC shl 21\r
+       mov     ecx,0xe shl 28 + 0x1 shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_bkpt:\r
+       mov     edx,0x01200070\r
+       jmp     ARM_immediate16\r
+ARM_instruction_bl:\r
+       INST_ARM64\r
+       dd      0x94000000\r
+       dd      ARM64_b\r
+       mov     edx,0x0b000000\r
+       jmp     ARM_target\r
+ARM_instruction_blx:\r
+       mov     edx,0                                   ;instruction varies depending upon parameters\r
+       jmp     ARM_Xtarget\r
+ARM_instruction_bx:\r
+       mov     edx,0x012fff10\r
+       jmp     ARM_rm\r
+ARM_instruction_bxj:\r
+       mov     edx,0x012fff20\r
+       mov     ecx,0xf3c08f00\r
+       jmp     ARM_rm_J\r
+ARM_instruction_cbnz:\r
+       INST_ARM64\r
+       dd      0x35000000\r
+       dd      ARM64_b_reg\r
+       mov     ecx,0xb900\r
+       jmp     THUMB_reg_address\r
+ARM_instruction_cbz:\r
+       INST_ARM64\r
+       dd      0x34000000\r
+       dd      ARM64_b_reg\r
+       mov     ecx,0xb100\r
+       jmp     THUMB_reg_address\r
+ARM_instruction_cdp:\r
+       mov     edx,0x0e000000\r
+       jmp     ARM_copro_op1_crd_crn_crm_op2\r
+ARM_instruction_cdp2:\r
+       mov     edx,0xfe000000\r
+       jmp     ARM_copro_op1_crd_crn_crm_op2\r
+ARM_instruction_chka:\r
+       jmp     THUMBEE_rn_rm\r
+ARM_instruction_clrex:\r
+       INST_ARM64\r
+       dd      0xd503305f\r
+       dd      ARM64_clrex\r
+       mov     edx,0xf57ff01f\r
+       mov     ecx,0xf3bf8f2f\r
+       jmp     ARM_clrex\r
+ARM_instruction_clz:\r
+       INST_ARM64\r
+       dd      0x5ac01000\r
+       dd      ARM64_arithmetic4\r
+       mov     edx,0x016f0f10\r
+       mov     ecx,0xfab0f080\r
+       jmp     ARM_rd_rm_CLZ\r
+ARM_instruction_cmn:\r
+       INST_ARM64\r
+       dd      0x20000000\r
+       dd      ARM64_arithmetic1_zr\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_CMN shl 21 + 1 shl 20\r
+       mov     ecx,0xe shl 28 + 0x8 shl 21 + 1 shl 20 + 0xf shl 8\r
+       jmp     ARM_rn_shifter\r
+ARM_instruction_cmnp:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_CMN shl 21 + 1 shl 20 + 0xf shl 12\r
+       jmp     ARM_rn_shifter_26bit\r
+ARM_instruction_cmp:\r
+       INST_ARM64\r
+       dd      0x60000000\r
+       dd      ARM64_arithmetic1_zr\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_CMP shl 21 + 1 shl 20\r
+       mov     ecx,0xe shl 28 + 0xd shl 21 + 1 shl 20 + 0xf shl 8\r
+       jmp     ARM_rn_shifter\r
+ARM_instruction_cmpp:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_CMP shl 21 + 1 shl 20 + 0xf shl 12\r
+       jmp     ARM_rn_shifter_26bit\r
+ARM_instruction_cps:\r
+       mov     edx,0xf1020000\r
+       mov     ecx,0xf3af8100\r
+       jmp     ARM_mode\r
+ARM_instruction_cpsid:\r
+       mov     edx,0xf10c0000\r
+       mov     ecx,0xf3af8600\r
+       jmp     ARM_iflags_mode\r
+ARM_instruction_cpsie:\r
+       mov     edx,0xf1080000\r
+       mov     ecx,0xf3af8400\r
+       jmp     ARM_iflags_mode\r
+ARM_instruction_cpy:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21\r
+       mov     ecx,0xe shl 28 + 0x2 shl 21 + 0xf shl 16\r
+       jmp     ARM_rd_rm_CPY\r
+ARM_instruction_dbg:\r
+       mov     edx,0x0320f0f0\r
+       mov     ecx,0xf3af80f0\r
+       jmp     ARM_imm4\r
+ARM_instruction_dmb:\r
+       INST_ARM64\r
+       dd      0xd50330bf\r
+       dd      ARM64_data_barrier\r
+       mov     edx,0xf57ff050\r
+       mov     ecx,0xf3bf8f50\r
+       jmp     ARM_barrier\r
+ARM_instruction_dsb:\r
+       INST_ARM64\r
+       dd      0xd503309f\r
+       dd      ARM64_data_barrier\r
+       mov     edx,0xf57ff040\r
+       mov     ecx,0xf3bf8f40\r
+       jmp     ARM_barrier\r
+ARM_instruction_enterx:\r
+       mov     ecx,0xf3bf8f1f\r
+       jmp     THUMBEE_enterx\r
+ARM_instruction_eor:\r
+       INST_ARM64\r
+       dd      0x40000000\r
+       dd      ARM64_arithmetic2\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_EOR shl 21\r
+       mov     ecx,0xe shl 28 + 0x4 shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_hb:\r
+       mov     edx,0x0000c200\r
+       jmp     THUMBEE_imm\r
+ARM_instruction_hbl:\r
+       mov     edx,0x0000c300\r
+       jmp     THUMBEE_imm\r
+ARM_instruction_hblp:\r
+       mov     edx,0x0000c400\r
+       jmp     THUMBEE_imm5_imm5\r
+ARM_instruction_hbp:\r
+       mov     edx,0x0000c000\r
+       jmp     THUMBEE_imm3_imm5\r
+ARM_instruction_isb:\r
+       INST_ARM64\r
+       dd      0xd50330df\r
+       dd      ARM64_instruction_barrier\r
+       mov     edx,0xf57ff060\r
+       mov     ecx,0xf3bf8f60\r
+       jmp     ARM_barrier\r
+ARM_instruction_it:\r
+       mov     ecx,0xbf08\r
+       jmp     THUMB_condition\r
+ARM_instruction_ite:\r
+       mov     ecx,0xbf0c\r
+       jmp     THUMB_condition\r
+ARM_instruction_itee:\r
+       mov     ecx,0xbf0e\r
+       jmp     THUMB_condition\r
+ARM_instruction_iteee:\r
+       mov     ecx,0xbf0f\r
+       jmp     THUMB_condition\r
+ARM_instruction_iteet:\r
+       mov     ecx,0xbf0d\r
+       jmp     THUMB_condition\r
+ARM_instruction_itet:\r
+       mov     ecx,0xbf0a\r
+       jmp     THUMB_condition\r
+ARM_instruction_itete:\r
+       mov     ecx,0xbf0b\r
+       jmp     THUMB_condition\r
+ARM_instruction_itett:\r
+       mov     ecx,0xbf09\r
+       jmp     THUMB_condition\r
+ARM_instruction_itt:\r
+       mov     ecx,0xbf04\r
+       jmp     THUMB_condition\r
+ARM_instruction_itte:\r
+       mov     ecx,0xbf06\r
+       jmp     THUMB_condition\r
+ARM_instruction_ittee:\r
+       mov     ecx,0xbf07\r
+       jmp     THUMB_condition\r
+ARM_instruction_ittet:\r
+       mov     ecx,0xbf05\r
+       jmp     THUMB_condition\r
+ARM_instruction_ittt:\r
+       mov     ecx,0xbf02\r
+       jmp     THUMB_condition\r
+ARM_instruction_ittte:\r
+       mov     ecx,0xbf03\r
+       jmp     THUMB_condition\r
+ARM_instruction_itttt:\r
+       mov     ecx,0xbf01\r
+       jmp     THUMB_condition\r
+ARM_instruction_ldc:\r
+       mov     edx,0x0c100000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_ldc2:\r
+       mov     edx,0xfc100000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_ldc2l:\r
+       mov     edx,0xfc500000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_ldcl:\r
+       mov     edx,0x0c500000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_ldm:\r
+ARM_instruction_ldmia:\r
+ARM_instruction_ldmfd:\r
+       mov     edx,0x08900000\r
+       mov     ecx,0xe8900000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_ldmda:\r
+ARM_instruction_ldmfa:\r
+       mov     edx,0x08100000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_ldmdb:\r
+ARM_instruction_ldmea:\r
+       mov     edx,0x09100000\r
+       mov     ecx,0xe9100000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_ldmed:\r
+ARM_instruction_ldmib:\r
+       mov     edx,0x09900000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_ldr:\r
+       INST_ARM64\r
+       dd      0x38400000\r
+       dd      ARM64_memory\r
+       mov     [operand_size],4\r
+       mov     edx,0x04100000\r
+       mov     ecx,0xf8500000\r
+       jmp     ARM_rd_address2\r
+ARM_instruction_ldrb:\r
+       INST_ARM64\r
+       dd      0x38400000\r
+       dd      ARM64_memory_byte_hword\r
+       mov     [operand_size],1\r
+       mov     edx,0x04500000\r
+       mov     ecx,0xf8100000\r
+       jmp     ARM_rd_address2\r
+ARM_instruction_ldrbt:\r
+       mov     [operand_size],1\r
+       mov     edx,0x04700000\r
+       mov     ecx,0xf8100e00\r
+       jmp     ARM_rd_address2_post\r
+ARM_instruction_ldrd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x000000d0\r
+       mov     ecx,0xe8500000\r
+       jmp     ARM_rd_address3D\r
+ARM_instruction_ldrex:\r
+       mov     [operand_size],4\r
+       mov     edx,0x01900f9f\r
+       mov     ecx,0xe8500f00\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldrexb:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01d00f9f\r
+       mov     ecx,0xe8d00f4f\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldrexd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x01b00f9f\r
+       mov     ecx,0xe8d0007f\r
+       jmp     ARM_rt_rt2_q_rn_p\r
+ARM_instruction_ldrexh:\r
+       mov     [operand_size],2\r
+       mov     edx,0x01f00f9f\r
+       mov     ecx,0xe8d00f5f\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldrh:\r
+       INST_ARM64\r
+       dd      0x38400001\r
+       dd      ARM64_memory_byte_hword\r
+       mov     [operand_size],2\r
+       mov     edx,0x001000b0\r
+       mov     ecx,0xf8300000\r
+       jmp     ARM_rd_address3\r
+ARM_instruction_ldrht:\r
+       mov     [operand_size],2\r
+       mov     edx,0x003000b0\r
+       mov     ecx,0xf8300e00\r
+       jmp     ARM_rd_address3T\r
+ARM_instruction_ldrsb:\r
+       INST_ARM64\r
+       dd      0x38800000\r
+       dd      ARM64_memory_signed_byte_hword\r
+       mov     [operand_size],1\r
+       mov     edx,0x001000d0\r
+       mov     ecx,0xf9100000\r
+       jmp     ARM_rd_address3\r
+ARM_instruction_ldrsbt:\r
+       mov     [operand_size],1\r
+       mov     edx,0x003000d0\r
+       mov     ecx,0xf9100e00\r
+       jmp     ARM_rd_address3T\r
+ARM_instruction_ldrsh:\r
+       INST_ARM64\r
+       dd      0x38800001\r
+       dd      ARM64_memory_signed_byte_hword\r
+       mov     [operand_size],2\r
+       mov     edx,0x001000f0\r
+       mov     ecx,0xf9300000\r
+       jmp     ARM_rd_address3\r
+ARM_instruction_ldrsht:\r
+       mov     [operand_size],2\r
+       mov     edx,0x003000f0\r
+       mov     ecx,0xf9300e00\r
+       jmp     ARM_rd_address3T\r
+ARM_instruction_ldrt:\r
+       mov     [operand_size],4\r
+       mov     edx,0x04300000\r
+       mov     ecx,0xf8500e00\r
+       jmp     ARM_rd_address2_post\r
+ARM_instruction_leavex:\r
+       mov     ecx,0xf3bf8f0f\r
+       jmp     THUMBEE_enterx\r
+ARM_instruction_lsl:\r
+       INST_ARM64\r
+       dd      0x1ac02000\r
+       dd      ARM64_arithmetic3\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_LSL shl 5\r
+       jmp     ARM_rd_rn_shift\r
+ARM_instruction_lsr:\r
+       INST_ARM64\r
+       dd      0x1ac02400\r
+       dd      ARM64_arithmetic3\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_LSR shl 5\r
+       jmp     ARM_rd_rn_shift\r
+ARM_instruction_mcr:\r
+       mov     edx,0x0e000010\r
+       jmp     ARM_copro_op1_rd_crn_crm_op2\r
+ARM_instruction_mcr2:\r
+       mov     edx,0xfe000010\r
+       jmp     ARM_copro_op1_rd_crn_crm_op2\r
+ARM_instruction_mcrr:\r
+       mov     edx,0x0c400000\r
+       jmp     ARM_copro_op1_rd_rn_crm\r
+ARM_instruction_mcrr2:\r
+       mov     edx,0xfc400000\r
+       jmp     ARM_copro_op1_rd_rn_crm\r
+ARM_instruction_mla:\r
+       INST_ARM64V\r
+       dd      0x0e209400      ;vector\r
+       dd      0x2f000000      ;element\r
+       dd      ARM64_arithmetic17\r
+       mov     edx,0x00200090\r
+       mov     ecx,0xfb000000\r
+       jmp     ARM_rd_rm_rs_rn\r
+ARM_instruction_mls:\r
+       INST_ARM64V\r
+       dd      0x2e209400      ;vector\r
+       dd      0x2f004000      ;element\r
+       dd      ARM64_arithmetic17\r
+       mov     edx,0x00600090\r
+       mov     ecx,0xfb000010\r
+       jmp     ARM_rd_rm_rs_rn\r
+ARM_instruction_mov:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_mov_aliases\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21\r
+       mov     ecx,0xe shl 28 + 0x2 shl 21 + 0xf shl 16\r
+       jmp     ARM_rd_shifter_exp\r
+ARM_instruction_movt:\r
+       mov     edx,0x03400000\r
+       mov     ecx,0xf2c00000\r
+       jmp     ARM_rd_imm16\r
+ARM_instruction_movw:\r
+       mov     edx,0x03000000\r
+       mov     ecx,0xf2400000\r
+       jmp     ARM_rd_imm16\r
+ARM_instruction_mrc:\r
+       mov     edx,0x0e100010\r
+       jmp     ARM_copro_op1_rd_crn_crm_op2\r
+ARM_instruction_mrc2:\r
+       mov     edx,0xfe100010\r
+       jmp     ARM_copro_op1_rd_crn_crm_op2\r
+ARM_instruction_mrrc:\r
+       mov     edx,0x0c500000\r
+       jmp     ARM_copro_op1_rd_rn_crm\r
+ARM_instruction_mrrc2:\r
+       mov     edx,0xfc500000\r
+       jmp     ARM_copro_op1_rd_rn_crm\r
+ARM_instruction_mrs:\r
+       INST_ARM64\r
+       dd      0xd5200000\r
+       dd      ARM64_sys_predefined_mrs\r
+       mov     edx,0x010f0000\r
+       mov     ecx,0xf3ef8000\r
+       jmp     ARM_rd_psr\r
+ARM_instruction_msr:\r
+       INST_ARM64\r
+       dd      0xd5000000\r
+       dd      ARM64_sys_predefined_msr\r
+       mov     edx,0x0120f000\r
+       mov     ecx,0xf3808000\r
+       jmp     ARM_psr_value\r
+ARM_instruction_mul:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_arithmetic6\r
+       mov     edx,0x00000090\r
+       mov     ecx,0xfb00f000\r
+       jmp     ARM_rd_rm_rs\r
+ARM_instruction_mvn:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_arithmetic7\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MVN shl 21\r
+       mov     ecx,0xe shl 28 + 0x3 shl 21 + 0xf shl 16\r
+       jmp     ARM_rd_shifter\r
+ARM_instruction_neg:\r
+       INST_ARM64S\r
+       dd      0x4b0003e0\r
+       dd      ARM64_arithmetic8\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_RSB shl 21\r
+       mov     ecx,0xe shl 28 + 0xe shl 21\r
+       jmp     ARM_rd_rm\r
+ARM_instruction_nop:\r
+       INST_ARM64\r
+       dd      0xd503201f\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f000\r
+       jmp     ARM_nop\r
+ARM_instruction_orn:\r
+       INST_ARM64\r
+       dd      0x20200000\r
+       dd      ARM64_arithmetic2\r
+       mov     ecx,0xe shl 28 + 0x3 shl 21\r
+       jmp     THUMB_rd_rn_shifter_ORN\r
+ARM_instruction_orr:\r
+       INST_ARM64\r
+       dd      0x20000000\r
+       dd      ARM64_arithmetic2\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_ORR shl 21\r
+       mov     ecx,0xe shl 28 + 0x2 shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_pkhbt:\r
+       mov     edx,0x06800010\r
+       mov     ecx,0xeac00000\r
+       jmp     ARM_rd_rn_rm_shift_imm\r
+ARM_instruction_pkhtb:\r
+       mov     edx,0x06800050\r
+       mov     ecx,0xeac00020\r
+       jmp     ARM_rd_rn_rm_shift_imm\r
+ARM_instruction_pld:\r
+       mov     [operand_size],1\r
+       mov     edx,0x04500000\r
+       mov     ecx,0xf810f000\r
+       jmp     ARM_address2\r
+ARM_instruction_pldw:\r
+       mov     [operand_size],1\r
+       mov     edx,0x04100000\r
+       mov     ecx,0xf830f000\r
+       jmp     ARM_address2\r
+ARM_instruction_pli:\r
+       mov     [operand_size],1\r
+       mov     edx,0x05500000\r
+       mov     ecx,0xf910f000\r
+       jmp     ARM_address2\r
+ARM_instruction_pop:\r
+       mov     edx,0x08900000\r
+       mov     ecx,0xe8900000\r
+       jmp     ARM_address4\r
+ARM_instruction_push:\r
+       mov     edx,0x09000000\r
+       mov     ecx,0xe9000000\r
+       jmp     ARM_address4\r
+ARM_instruction_qadd:\r
+       mov     edx,0x01000050\r
+       mov     ecx,0xfa80f080\r
+       jmp     ARM_rd_rm_rn\r
+ARM_instruction_qadd16:\r
+       mov     edx,0x06200f10\r
+       mov     ecx,0xfa90f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_qadd8:\r
+       mov     edx,0x06200f90\r
+       mov     ecx,0xfa80f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_qaddsubx:\r
+ARM_instruction_qasx:\r
+       mov     edx,0x06200f30\r
+       mov     ecx,0xfaa0f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_qdadd:\r
+       mov     edx,0x01400050\r
+       mov     ecx,0xfa80f090\r
+       jmp     ARM_rd_rm_rn\r
+ARM_instruction_qdsub:\r
+       mov     edx,0x01600050\r
+       mov     ecx,0xfa80f0b0\r
+       jmp     ARM_rd_rm_rn\r
+ARM_instruction_qsub:\r
+       mov     edx,0x01200050\r
+       mov     ecx,0xfa80f0a0\r
+       jmp     ARM_rd_rm_rn\r
+ARM_instruction_qsub16:\r
+       mov     edx,0x06200f70\r
+       mov     ecx,0xfad0f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_qsub8:\r
+       mov     edx,0x06200ff0\r
+       mov     ecx,0xfac0f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_qsubaddx:\r
+ARM_instruction_qsax:\r
+       mov     edx,0x06200f50\r
+       mov     ecx,0xfae0f010\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_rbit:\r
+       INST_ARM64\r
+       dd      0x5ac00000\r
+       dd      ARM64_arithmetic10\r
+       mov     edx,0x06ff0f30\r
+       mov     ecx,0xfa90f0a0\r
+       jmp     ARM_rd_rm_REV\r
+ARM_instruction_rev:\r
+       INST_ARM64\r
+       dd      0x5ac00800\r
+       dd      ARM64_arithmetic11\r
+       mov     edx,0x06bf0f30\r
+       mov     ecx,0xfa90f080\r
+       jmp     ARM_rd_rm_REV\r
+ARM_instruction_rev16:\r
+       INST_ARM64\r
+       dd      0x5ac00400\r
+       dd      ARM64_arithmetic12\r
+       mov     edx,0x06bf0fb0\r
+       mov     ecx,0xfa90f090\r
+       jmp     ARM_rd_rm_REV\r
+ARM_instruction_revsh:\r
+       mov     edx,0x06ff0fb0\r
+       mov     ecx,0xfa90f0b0\r
+       jmp     ARM_rd_rm_REV\r
+ARM_instruction_rfe:\r
+ARM_instruction_rfeia:\r
+ARM_instruction_rfefd:\r
+       mov     edx,0xf8900a00\r
+       mov     ecx,0xe990c000\r
+       jmp     ARM_rn\r
+ARM_instruction_rfeda:\r
+ARM_instruction_rfefa:\r
+       mov     edx,0xf8100a00\r
+       jmp     ARM_rn\r
+ARM_instruction_rfedb:\r
+ARM_instruction_rfeea:\r
+       mov     edx,0xf9100a00\r
+       mov     ecx,0xe810c000\r
+       jmp     ARM_rn\r
+ARM_instruction_rfeib:\r
+ARM_instruction_rfeed:\r
+       mov     edx,0xf9900a00\r
+       jmp     ARM_rn\r
+ARM_instruction_ror:\r
+       INST_ARM64\r
+       dd      0x1ac02c00\r
+       dd      ARM64_arithmetic3\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ROR shl 5\r
+       jmp     ARM_rd_rn_shift\r
+ARM_instruction_rrx:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_MOV shl 21 + ARM_SHIFT_OPCODE_ROR shl 5\r
+       mov     ecx,0xea4f0000\r
+       jmp     ARM_rd_shift\r
+ARM_instruction_rsb:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_RSB shl 21\r
+       mov     ecx,0xe shl 28 + 0xe shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_rsc:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_RSC shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_sadd16:\r
+       mov     edx,0x06100f10\r
+       mov     ecx,0xfa90f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_sadd8:\r
+       mov     edx,0x06100f90\r
+       mov     ecx,0xfa80f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_saddsubx:\r
+ARM_instruction_sasx:\r
+       mov     edx,0x06100f30\r
+       mov     ecx,0xfaa0f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_sbc:\r
+       INST_ARM64S\r
+       dd      0x5a000000\r
+       dd      ARM64_dz_nz_mz\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_SBC shl 21\r
+       mov     ecx,0xe shl 28 + 0xb shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_sbfx:\r
+       INST_ARM64\r
+       dd      0x13000000\r
+       dd      ARM64_bfxil\r
+       mov     edx,0x07a00050\r
+       mov     ecx,0xf3400000\r
+       jmp     ARM_rd_rn_imm_imm_X\r
+ARM_instruction_sdiv:\r
+       INST_ARM64\r
+       dd      0x1ac00c00\r
+       dd      ARM64_dz_nz_mz\r
+       mov     edx,0x0710f010\r
+       mov     ecx,0xfb90f0f0\r
+       jmp     ARM_rd_rn_rm_DIV\r
+ARM_instruction_sel:\r
+       mov     edx,0x06800fb0\r
+       mov     ecx,0xfaa0f080\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_setend:\r
+       mov     edx,0xf1010000\r
+       jmp     ARM_endian\r
+ARM_instruction_sev:\r
+       INST_ARM64\r
+       dd      0xd503209f\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f004\r
+       mov     ecx,0xf3af8004\r
+       jmp     ARM_nops\r
+ARM_instruction_shadd16:\r
+       mov     edx,0x06300f10\r
+       mov     ecx,0xfa90f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_shadd8:\r
+       mov     edx,0x06300f90\r
+       mov     ecx,0xfa80f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_shaddsubx:\r
+ARM_instruction_shasx:\r
+       mov     edx,0x06300f30\r
+       mov     ecx,0xfaa0f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_shsub16:\r
+       mov     edx,0x06300f70\r
+       mov     ecx,0xfad0f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_shsub8:\r
+       mov     edx,0x06300ff0\r
+       mov     ecx,0xfac0f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_shsubaddx:\r
+ARM_instruction_shsax:\r
+       mov     edx,0x06300f50\r
+       mov     ecx,0xfae0f020\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_smc:\r
+       INST_ARM64\r
+       dd      0xd4000003\r
+       dd      ARM64_debug\r
+ARM_instruction_smi:\r
+       mov     edx,0x01600070\r
+       mov     ecx,0xf7f08000\r
+       jmp     ARM_immediate4\r
+ARM_instruction_smlabb:\r
+       mov     edx,0x01000080\r
+       mov     ecx,0xfb100000\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlabt:\r
+       mov     edx,0x010000c0\r
+       mov     ecx,0xfb100010\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlad:\r
+       mov     edx,0x07000010\r
+       mov     ecx,0xfb200000\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smladx:\r
+       mov     edx,0x07000030\r
+       mov     ecx,0xfb200010\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smlal:\r
+       INST_ARM64V\r
+       dd      0x0e208000      ;vector\r
+       dd      0x0f002000      ;element\r
+       dd      ARM64_arithmetic18_long\r
+       mov     edx,0x00e00090\r
+       mov     ecx,0xfbc00000\r
+       jmp     ARM_rdlo_rdhi_rm_rs\r
+ARM_instruction_smlalbb:\r
+       mov     edx,0x01400080\r
+       mov     ecx,0xfbc00080\r
+       jmp     ARM_rdlo_rdhi_rm_rs_E\r
+ARM_instruction_smlalbt:\r
+       mov     edx,0x014000c0\r
+       mov     ecx,0xfbc00090\r
+       jmp     ARM_rdlo_rdhi_rm_rs_E\r
+ARM_instruction_smlald:\r
+       mov     edx,0x07400010\r
+       mov     ecx,0xfbc000c0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_D\r
+ARM_instruction_smlaldx:\r
+       mov     edx,0x07400030\r
+       mov     ecx,0xfbc000d0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_D\r
+ARM_instruction_smlaltb:\r
+       mov     edx,0x014000a0\r
+       mov     ecx,0xfbc000a0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_E\r
+ARM_instruction_smlaltt:\r
+       mov     edx,0x014000e0\r
+       mov     ecx,0xfbc000b0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_E\r
+ARM_instruction_smlatb:\r
+       mov     edx,0x010000a0\r
+       mov     ecx,0xfb100020\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlatt:\r
+       mov     edx,0x010000e0\r
+       mov     ecx,0xfb100030\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlawb:\r
+       mov     edx,0x01200080\r
+       mov     ecx,0xfb300000\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlawt:\r
+       mov     edx,0x012000c0\r
+       mov     ecx,0xfb300010\r
+       jmp     ARM_rd_rm_rs_rn_E\r
+ARM_instruction_smlsd:\r
+       mov     edx,0x07000050\r
+       mov     ecx,0xfb400000\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smlsdx:\r
+       mov     edx,0x07000070\r
+       mov     ecx,0xfb400010\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smlsld:\r
+       mov     edx,0x07400050\r
+       mov     ecx,0xfbd000c0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_D\r
+ARM_instruction_smlsldx:\r
+       mov     edx,0x07400070\r
+       mov     ecx,0xfbd000d0\r
+       jmp     ARM_rdlo_rdhi_rm_rs_D\r
+ARM_instruction_smmla:\r
+       mov     edx,0x07500010\r
+       mov     ecx,0xfb500000\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smmlar:\r
+       mov     edx,0x07500030\r
+       mov     ecx,0xfb500010\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smmls:\r
+       mov     edx,0x075000d0\r
+       mov     ecx,0xfb600000\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smmlsr:\r
+       mov     edx,0x075000f0\r
+       mov     ecx,0xfb600010\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_smmul:\r
+       mov     edx,0x0750f010\r
+       mov     ecx,0xfb50f000\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_smmulr:\r
+       mov     edx,0x0750f030\r
+       mov     ecx,0xfb50f010\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_smuad:\r
+       mov     edx,0x0700f010\r
+       mov     ecx,0xfb20f000\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_smuadx:\r
+       mov     edx,0x0700f030\r
+       mov     ecx,0xfb20f010\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_smulbb:\r
+       mov     edx,0x01600080\r
+       mov     ecx,0xfb10f000\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smulbt:\r
+       mov     edx,0x016000c0\r
+       mov     ecx,0xfb10f010\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smull:\r
+       INST_ARM64\r
+       dd      0x9b207c00\r
+       dd      ARM64_arithmetic15\r
+       mov     edx,0x00c00090\r
+       mov     ecx,0xfb800000\r
+       jmp     ARM_rdlo_rdhi_rm_rs\r
+ARM_instruction_smultb:\r
+       mov     edx,0x016000a0\r
+       mov     ecx,0xfb10f020\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smultt:\r
+       mov     edx,0x016000e0\r
+       mov     ecx,0xfb10f030\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smulwb:\r
+       mov     edx,0x012000a0\r
+       mov     ecx,0xfb30f000\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smulwt:\r
+       mov     edx,0x012000e0\r
+       mov     ecx,0xfb30f010\r
+       jmp     ARM_rd_rm_rs_E\r
+ARM_instruction_smusd:\r
+       mov     edx,0x0700f050\r
+       mov     ecx,0xfb40f000\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_smusdx:\r
+       mov     edx,0x0700f070\r
+       mov     ecx,0xfb40f010\r
+       jmp     ARM_rd_rm_rs_M\r
+ARM_instruction_srs:\r
+ARM_instruction_srsia:\r
+ARM_instruction_srsea:\r
+       mov     edx,0xf8cd0500\r
+       mov     ecx,0xe98dc000\r
+       jmp     ARM_reg_mode\r
+ARM_instruction_srsda:\r
+ARM_instruction_srsfa:\r
+       mov     edx,0xf84d0500\r
+       jmp     ARM_reg_mode\r
+ARM_instruction_srsdb:\r
+ARM_instruction_srsfd:\r
+       mov     edx,0xf94d0500\r
+       mov     ecx,0xe80dc000\r
+       jmp     ARM_reg_mode\r
+ARM_instruction_srsib:\r
+ARM_instruction_srsed:\r
+       mov     edx,0xf9cd0500\r
+       jmp     ARM_reg_mode\r
+ARM_instruction_ssat:\r
+       mov     edx,0x06a00010\r
+       mov     ecx,0xf3000000\r
+       jmp     ARM_rd_imm_rm_shift\r
+ARM_instruction_ssat16:\r
+       mov     edx,0x06a00f30\r
+       mov     ecx,0xf3200000\r
+       jmp     ARM_rd_imm_rm\r
+ARM_instruction_ssub16:\r
+       mov     edx,0x06100f70\r
+       mov     ecx,0xfad0f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_ssub8:\r
+       mov     edx,0x06100ff0\r
+       mov     ecx,0xfac0f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_ssubaddx:\r
+ARM_instruction_ssax:\r
+       mov     edx,0x06100f50\r
+       mov     ecx,0xfae0f000\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_stc:\r
+       mov     edx,0x0c000000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_stc2:\r
+       mov     edx,0xfc000000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_stc2l:\r
+       mov     edx,0xfc400000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_stcl:\r
+       mov     edx,0x0c400000\r
+       jmp     ARM_copro_crd_address5\r
+ARM_instruction_stm:\r
+ARM_instruction_stmia:\r
+ARM_instruction_stmea:\r
+       mov     edx,0x08800000\r
+       mov     ecx,0xe8800000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_stmda:\r
+ARM_instruction_stmed:\r
+       mov     edx,0x08000000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_stmdb:\r
+ARM_instruction_stmfd:\r
+       mov     edx,0x09000000\r
+       mov     ecx,0xe9000000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_stmib:\r
+ARM_instruction_stmfa:\r
+       mov     edx,0x09800000\r
+       jmp     ARM_rn_address4\r
+ARM_instruction_str:\r
+       INST_ARM64\r
+       dd      0x38000000\r
+       dd      ARM64_memory\r
+       mov     [operand_size],4\r
+       mov     edx,0x04000000\r
+       mov     ecx,0xf8400000\r
+       jmp     ARM_rd_address2\r
+ARM_instruction_strb:\r
+       INST_ARM64\r
+       dd      0x38000000\r
+       dd      ARM64_memory_byte_hword\r
+       mov     [operand_size],1\r
+       mov     edx,0x04400000\r
+       mov     ecx,0xf8000000\r
+       jmp     ARM_rd_address2\r
+ARM_instruction_strbt:\r
+       mov     [operand_size],1\r
+       mov     edx,0x04600000\r
+       mov     ecx,0xf8000e00\r
+       jmp     ARM_rd_address2_post\r
+ARM_instruction_strd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x000000f0\r
+       mov     ecx,0xe8400000\r
+       jmp     ARM_rd_address3D\r
+ARM_instruction_strex:\r
+       mov     [operand_size],4\r
+       mov     edx,0x01800f90\r
+       mov     ecx,0xe8400000\r
+       jmp     ARM_rd_rm_q_rn_p_STREX\r
+ARM_instruction_strexb:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01c00f90\r
+       mov     ecx,0xe8c00f40\r
+       jmp     ARM_rd_rm_q_rn_p_STREX\r
+ARM_instruction_strexd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x01a00f90\r
+       mov     ecx,0xe8c00070\r
+       jmp     ARM_rd_rt_rt2_q_rn_p\r
+ARM_instruction_strexh:\r
+       mov     [operand_size],2\r
+       mov     edx,0x01e00f90\r
+       mov     ecx,0xe8c00f50\r
+       jmp     ARM_rd_rm_q_rn_p_STREX\r
+ARM_instruction_strh:\r
+       INST_ARM64\r
+       dd      0x38000001\r
+       dd      ARM64_memory_byte_hword\r
+       mov     [operand_size],2\r
+       mov     edx,0x000000b0\r
+       mov     ecx,0xf8200000\r
+       jmp     ARM_rd_address3\r
+ARM_instruction_strht:\r
+       mov     [operand_size],2\r
+       mov     edx,0x002000b0\r
+       mov     ecx,0xf8200e00\r
+       jmp     ARM_rd_address3T\r
+ARM_instruction_strt:\r
+       mov     [operand_size],4\r
+       mov     edx,0x04200000\r
+       mov     ecx,0xf8400e00\r
+       jmp     ARM_rd_address2_post\r
+ARM_instruction_sub:\r
+       INST_ARM64S\r
+       dd      0x40000000\r
+       dd      ARM64_arithmetic1\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_SUB shl 21\r
+       mov     ecx,0xe shl 28 + 0xd shl 21\r
+       jmp     ARM_rd_rn_shifter\r
+ARM_instruction_subw:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_SUB shl 21\r
+       mov     ecx,0xf2000000 + 5 shl 21\r
+       jmp     THUMB_rd_rn_imm12\r
+ARM_instruction_svc:\r
+       INST_ARM64\r
+       dd      0xd4000001\r
+       dd      ARM64_debug\r
+ARM_instruction_swi:\r
+       mov     edx,0x0f000000\r
+       jmp     ARM_immediate24\r
+ARM_instruction_swp:\r
+       mov     edx,0x01000090\r
+       jmp     ARM_rd_rm_q_rn_p\r
+ARM_instruction_swpb:\r
+       mov     edx,0x01400090\r
+       jmp     ARM_rd_rm_q_rn_p\r
+ARM_instruction_sxtab:\r
+       mov     edx,0x06a00070\r
+       mov     ecx,0xfa40f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_sxtab16:\r
+       mov     edx,0x06800070\r
+       mov     ecx,0xfa20f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_sxtah:\r
+       mov     edx,0x06b00070\r
+       mov     ecx,0xfa00f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_sxtb:\r
+       INST_ARM64\r
+       dd      0x13001c00\r
+       dd      ARM64_dz_nw\r
+       mov     edx,0x06af0070\r
+       mov     ecx,0xfa4ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_sxtb16:\r
+       mov     edx,0x068f0070\r
+       mov     ecx,0xfa2ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_sxth:\r
+       INST_ARM64\r
+       dd      0x13003c00\r
+       dd      ARM64_dz_nw\r
+       mov     edx,0x06bf0070\r
+       mov     ecx,0xfa0ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_tbb:\r
+       mov     ecx,0xe8d0f000\r
+       jmp     THUMB_q_rn_rm_p\r
+ARM_instruction_tbh:\r
+       mov     ecx,0xe8d0f010\r
+       jmp     THUMB_q_rn_rm_lsl_1_p\r
+ARM_instruction_teq:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_TEQ shl 21 + 1 shl 20\r
+       mov     ecx,0xe shl 28 + 0x4 shl 21 + 1 shl 20 + 0xf shl 8\r
+       jmp     ARM_rn_shifter\r
+ARM_instruction_teqp:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_TEQ shl 21 + 1 shl 20 + 0xf shl 12\r
+       jmp     ARM_rn_shifter_26bit\r
+ARM_instruction_tst:\r
+       INST_ARM64\r
+       dd      0x60000000\r
+       dd      ARM64_arithmetic16\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_TST shl 21 + 1 shl 20\r
+       mov     ecx,0xe shl 28 + 0x0 shl 21 + 1 shl 20 + 0xf shl 8\r
+       jmp     ARM_rn_shifter\r
+ARM_instruction_tstp:\r
+       mov     edx,ARM_INSTRUCTION_OPCODE_TST shl 21 + 1 shl 20 + 0xf shl 12\r
+       jmp     ARM_rn_shifter_26bit\r
+ARM_instruction_uadd16:\r
+       mov     edx,0x06500f10\r
+       mov     ecx,0xfa90f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uadd8:\r
+       mov     edx,0x06500f90\r
+       mov     ecx,0xfa80f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uaddsubx:\r
+ARM_instruction_uasx:\r
+       mov     edx,0x06500f30\r
+       mov     ecx,0xfaa0f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_ubfx:\r
+       INST_ARM64\r
+       dd      0x53000000\r
+       dd      ARM64_bfxil\r
+       mov     edx,0x07e00050\r
+       mov     ecx,0xf3c00000\r
+       jmp     ARM_rd_rn_imm_imm_X\r
+ARM_instruction_udiv:\r
+       INST_ARM64\r
+       dd      0x1ac00800\r
+       dd      ARM64_dz_nz_mz\r
+       mov     edx,0x0730f010\r
+       mov     ecx,0xfbb0f0f0\r
+       jmp     ARM_rd_rn_rm_DIV\r
+ARM_instruction_uhadd16:\r
+       mov     edx,0x06700f10\r
+       mov     ecx,0xfa90f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uhadd8:\r
+       mov     edx,0x06700f90\r
+       mov     ecx,0xfa80f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uhaddsubx:\r
+ARM_instruction_uhasx:\r
+       mov     edx,0x06700f30\r
+       mov     ecx,0xfaa0f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uhsub16:\r
+       mov     edx,0x06700f70\r
+       mov     ecx,0xfad0f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uhsub8:\r
+       mov     edx,0x06700ff0\r
+       mov     ecx,0xfac0f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uhsubaddx:\r
+ARM_instruction_uhsax:\r
+       mov     edx,0x06700f50\r
+       mov     ecx,0xfae0f060\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_umaal:\r
+       mov     edx,0x00400090\r
+       mov     ecx,0xfbe00060\r
+       jmp     ARM_rdlo_rdhi_rm_rs\r
+ARM_instruction_umlal:\r
+       INST_ARM64V\r
+       dd      0x2e208000      ;vector\r
+       dd      0x2f002000      ;element\r
+       dd      ARM64_arithmetic18_long\r
+       mov     edx,0x00a00090\r
+       mov     ecx,0xfbe00000\r
+       jmp     ARM_rdlo_rdhi_rm_rs\r
+ARM_instruction_umull:\r
+       INST_ARM64\r
+       dd      0x9ba07c00\r
+       dd      ARM64_arithmetic15\r
+       mov     edx,0x00800090\r
+       mov     ecx,0xfba00000\r
+       jmp     ARM_rdlo_rdhi_rm_rs\r
+ARM_instruction_und:\r
+       mov     edx,0x07f000f0\r
+       mov     ecx,0xf7f0a0f0\r
+       jmp     ARM_und\r
+ARM_instruction_uqadd16:\r
+       mov     edx,0x06600f10\r
+       mov     ecx,0xfa90f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uqadd8:\r
+       mov     edx,0x06600f90\r
+       mov     ecx,0xfa80f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uqaddsubx:\r
+ARM_instruction_uqasx:\r
+       mov     edx,0x06600f30\r
+       mov     ecx,0xfaa0f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uqsub16:\r
+       mov     edx,0x06600f70\r
+       mov     ecx,0xfad0f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uqsub8:\r
+       mov     edx,0x06600ff0\r
+       mov     ecx,0xfac0f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uqsubaddx:\r
+ARM_instruction_uqsax:\r
+       mov     edx,0x06600f50\r
+       mov     ecx,0xfae0f050\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_usad8:\r
+       mov     edx,0x0780f010\r
+       mov     ecx,0xfb70f000\r
+       jmp     ARM_rd_rm_rs_SAD\r
+ARM_instruction_usada8:\r
+       mov     edx,0x07800010\r
+       mov     ecx,0xfb700000\r
+       jmp     ARM_rd_rm_rs_rn_D\r
+ARM_instruction_usat:\r
+       mov     edx,0x06e00010\r
+       mov     ecx,0xf3800000\r
+       jmp     ARM_rd_imm_rm_shift\r
+ARM_instruction_usat16:\r
+       mov     edx,0x06e00f30\r
+       mov     ecx,0xf3a00000\r
+       jmp     ARM_rd_imm_rm\r
+ARM_instruction_usub16:\r
+       mov     edx,0x06500f70\r
+       mov     ecx,0xfad0f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_usub8:\r
+       mov     edx,0x06500ff0\r
+       mov     ecx,0xfac0f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_usubaddx:\r
+ARM_instruction_usax:\r
+       mov     edx,0x06500f50\r
+       mov     ecx,0xfae0f040\r
+       jmp     ARM_rd_rn_rm\r
+ARM_instruction_uxtab:\r
+       mov     edx,0x06e00070\r
+       mov     ecx,0xfa50f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_uxtab16:\r
+       mov     edx,0x06c00070\r
+       mov     ecx,0xfa30f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_uxtah:\r
+       mov     edx,0x06f00070\r
+       mov     ecx,0xfa10f080\r
+       jmp     ARM_rd_rn_rm_rotation\r
+ARM_instruction_uxtb:\r
+       INST_ARM64\r
+       dd      0x53001c00\r
+       dd      ARM64_dw_nw\r
+       mov     edx,0x06ef0070\r
+       mov     ecx,0xfa5ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_uxtb16:\r
+       mov     edx,0x06cf0070\r
+       mov     ecx,0xfa3ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_uxth:\r
+       INST_ARM64\r
+       dd      0x53003c00\r
+       dd      ARM64_dw_nw\r
+       mov     edx,0x06ff0070\r
+       mov     ecx,0xfa1ff080\r
+       jmp     ARM_rd_rm_rotation\r
+ARM_instruction_wfe:\r
+       INST_ARM64\r
+       dd      0xd503205f\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f002\r
+       mov     ecx,0xf3af8002\r
+       jmp     ARM_nops\r
+ARM_instruction_wfi:\r
+       INST_ARM64\r
+       dd      0xd503207f\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f003\r
+       mov     ecx,0xf3af8003\r
+       jmp     ARM_nops\r
+ARM_instruction_yield:\r
+       INST_ARM64\r
+       dd      0xd503203f\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f001\r
+       mov     ecx,0xf3af8001\r
+       jmp     ARM_nops\r
+\r
+;FPA jump table\r
+\r
+ARM_instruction_absd:\r
+       mov     edx,0x0e208180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absdm:\r
+       mov     edx,0x0e2081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absdp:\r
+       mov     edx,0x0e2081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absdz:\r
+       mov     edx,0x0e2081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_abse:\r
+       mov     edx,0x0e288100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absem:\r
+       mov     edx,0x0e288140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absep:\r
+       mov     edx,0x0e288120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_absez:\r
+       mov     edx,0x0e288160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_abss:\r
+       mov     edx,0x0e208100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_abssm:\r
+       mov     edx,0x0e208140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_abssp:\r
+       mov     edx,0x0e208120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_abssz:\r
+       mov     edx,0x0e208160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsd:\r
+       mov     edx,0x0ec08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsdm:\r
+       mov     edx,0x0ec081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsdp:\r
+       mov     edx,0x0ec081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsdz:\r
+       mov     edx,0x0ec081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acse:\r
+       mov     edx,0x0ec88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsem:\r
+       mov     edx,0x0ec88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsep:\r
+       mov     edx,0x0ec88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acsez:\r
+       mov     edx,0x0ec88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acss:\r
+       mov     edx,0x0ec08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acssm:\r
+       mov     edx,0x0ec08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acssp:\r
+       mov     edx,0x0ec08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_acssz:\r
+       mov     edx,0x0ec08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_adfd:\r
+       mov     edx,0x0e000180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfdm:\r
+       mov     edx,0x0e0001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfdp:\r
+       mov     edx,0x0e0001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfdz:\r
+       mov     edx,0x0e0001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfe:\r
+       mov     edx,0x0e080100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfem:\r
+       mov     edx,0x0e080140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfep:\r
+       mov     edx,0x0e080120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfez:\r
+       mov     edx,0x0e080160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfs:\r
+       mov     edx,0x0e000100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfsm:\r
+       mov     edx,0x0e000140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfsp:\r
+       mov     edx,0x0e000120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_adfsz:\r
+       mov     edx,0x0e000160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_asnd:\r
+       mov     edx,0x0eb08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asndm:\r
+       mov     edx,0x0eb081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asndp:\r
+       mov     edx,0x0eb081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asndz:\r
+       mov     edx,0x0eb081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asne:\r
+       mov     edx,0x0eb88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnem:\r
+       mov     edx,0x0eb88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnep:\r
+       mov     edx,0x0eb88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnez:\r
+       mov     edx,0x0eb88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asns:\r
+       mov     edx,0x0eb08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnsm:\r
+       mov     edx,0x0eb08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnsp:\r
+       mov     edx,0x0eb08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_asnsz:\r
+       mov     edx,0x0eb08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnd:\r
+       mov     edx,0x0ed08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atndm:\r
+       mov     edx,0x0ed081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atndp:\r
+       mov     edx,0x0ed081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atndz:\r
+       mov     edx,0x0ed081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atne:\r
+       mov     edx,0x0ed88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnem:\r
+       mov     edx,0x0ed88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnep:\r
+       mov     edx,0x0ed88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnez:\r
+       mov     edx,0x0ed88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atns:\r
+       mov     edx,0x0ed08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnsm:\r
+       mov     edx,0x0ed08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnsp:\r
+       mov     edx,0x0ed08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_atnsz:\r
+       mov     edx,0x0ed08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cmf:\r
+       mov     edx,0x0e90f110\r
+       jmp     FPA_fn_fm\r
+ARM_instruction_cmfe:\r
+       mov     edx,0x0ed0f110\r
+       jmp     FPA_fn_fm\r
+ARM_instruction_cnf:\r
+       mov     edx,0x0eb0f110\r
+       jmp     FPA_fn_fm\r
+ARM_instruction_cnfe:\r
+       mov     edx,0x0ef0f110\r
+       jmp     FPA_fn_fm\r
+ARM_instruction_cosd:\r
+       mov     edx,0x0e908180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosdm:\r
+       mov     edx,0x0e9081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosdp:\r
+       mov     edx,0x0e9081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosdz:\r
+       mov     edx,0x0e9081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cose:\r
+       mov     edx,0x0e988100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosem:\r
+       mov     edx,0x0e988140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosep:\r
+       mov     edx,0x0e988120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cosez:\r
+       mov     edx,0x0e988160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_coss:\r
+       mov     edx,0x0e908100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cossm:\r
+       mov     edx,0x0e908140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cossp:\r
+       mov     edx,0x0e908120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_cossz:\r
+       mov     edx,0x0e908160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_dvfd:\r
+       mov     edx,0x0e400180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfdm:\r
+       mov     edx,0x0e4001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfdp:\r
+       mov     edx,0x0e4001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfdz:\r
+       mov     edx,0x0e4001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfe:\r
+       mov     edx,0x0e480100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfem:\r
+       mov     edx,0x0e480140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfep:\r
+       mov     edx,0x0e480120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfez:\r
+       mov     edx,0x0e480160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfs:\r
+       mov     edx,0x0e400100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfsm:\r
+       mov     edx,0x0e400140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfsp:\r
+       mov     edx,0x0e400120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_dvfsz:\r
+       mov     edx,0x0e400160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_expd:\r
+       mov     edx,0x0e708180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expdm:\r
+       mov     edx,0x0e7081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expdp:\r
+       mov     edx,0x0e7081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expdz:\r
+       mov     edx,0x0e7081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expe:\r
+       mov     edx,0x0e788100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expem:\r
+       mov     edx,0x0e788140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expep:\r
+       mov     edx,0x0e788120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expez:\r
+       mov     edx,0x0e788160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_exps:\r
+       mov     edx,0x0e708100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expsm:\r
+       mov     edx,0x0e708140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expsp:\r
+       mov     edx,0x0e708120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_expsz:\r
+       mov     edx,0x0e708160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_fdvd:\r
+       mov     edx,0x0ea00180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvdm:\r
+       mov     edx,0x0ea001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvdp:\r
+       mov     edx,0x0ea001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvdz:\r
+       mov     edx,0x0ea001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdve:\r
+       mov     edx,0x0ea80100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvem:\r
+       mov     edx,0x0ea80140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvep:\r
+       mov     edx,0x0ea80120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvez:\r
+       mov     edx,0x0ea80160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvs:\r
+       mov     edx,0x0ea00100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvsm:\r
+       mov     edx,0x0ea00140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvsp:\r
+       mov     edx,0x0ea00120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fdvsz:\r
+       mov     edx,0x0ea00160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fix:\r
+       mov     edx,0x0e100110\r
+       jmp     FPA_rd_fm\r
+ARM_instruction_fixm:\r
+       mov     edx,0x0e100150\r
+       jmp     FPA_rd_fm\r
+ARM_instruction_fixp:\r
+       mov     edx,0x0e100130\r
+       jmp     FPA_rd_fm\r
+ARM_instruction_fixz:\r
+       mov     edx,0x0e100170\r
+       jmp     FPA_rd_fm\r
+ARM_instruction_fltd:\r
+       mov     edx,0x0e000190\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltdm:\r
+       mov     edx,0x0e0001d0\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltdp:\r
+       mov     edx,0x0e0001b0\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltdz:\r
+       mov     edx,0x0e0001f0\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_flte:\r
+       mov     edx,0x0e080110\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltem:\r
+       mov     edx,0x0e080150\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltep:\r
+       mov     edx,0x0e080130\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltez:\r
+       mov     edx,0x0e080170\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_flts:\r
+       mov     edx,0x0e000110\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltsm:\r
+       mov     edx,0x0e000150\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltsp:\r
+       mov     edx,0x0e000130\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fltsz:\r
+       mov     edx,0x0e000170\r
+       jmp     FPA_fn_rd\r
+ARM_instruction_fmld:\r
+       mov     edx,0x0e900180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmldm:\r
+       mov     edx,0x0e9001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmldp:\r
+       mov     edx,0x0e9001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmldz:\r
+       mov     edx,0x0e9001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmle:\r
+       mov     edx,0x0e980100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlem:\r
+       mov     edx,0x0e980140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlep:\r
+       mov     edx,0x0e980120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlez:\r
+       mov     edx,0x0e980160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmls:\r
+       INST_ARM64V\r
+       dd      0x5f805000      ;scalar\r
+       dd      0x0f805000      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg_element_sub\r
+       mov     edx,0x0e900100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlsm:\r
+       mov     edx,0x0e900140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlsp:\r
+       mov     edx,0x0e900120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_fmlsz:\r
+       mov     edx,0x0e900160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdd:\r
+       mov     edx,0x0eb00180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frddm:\r
+       mov     edx,0x0eb001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frddp:\r
+       mov     edx,0x0eb001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frddz:\r
+       mov     edx,0x0eb001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frde:\r
+       mov     edx,0x0eb80100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdem:\r
+       mov     edx,0x0eb80140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdep:\r
+       mov     edx,0x0eb80120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdez:\r
+       mov     edx,0x0eb80160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frds:\r
+       mov     edx,0x0eb00100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdsm:\r
+       mov     edx,0x0eb00140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdsp:\r
+       mov     edx,0x0eb00120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_frdsz:\r
+       mov     edx,0x0eb00160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_ldfd:\r
+       mov     edx,0x0c108100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_ldfe:\r
+       mov     edx,0x0c500100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_ldfp:\r
+       mov     edx,0x0c508100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_ldfs:\r
+       mov     edx,0x0c100100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_lfm:\r
+       mov     edx,0x0c100200\r
+       jmp     FPA_fd_imm_address5\r
+ARM_instruction_lfmea:\r
+       mov     edx,0x0d100200\r
+       jmp     FPA_fd_imm_rn\r
+ARM_instruction_lfmfd:\r
+       mov     edx,0x0c900200\r
+       jmp     FPA_fd_imm_rn\r
+ARM_instruction_lgnd:\r
+       mov     edx,0x0e608180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgndm:\r
+       mov     edx,0x0e6081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgndp:\r
+       mov     edx,0x0e6081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgndz:\r
+       mov     edx,0x0e6081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgne:\r
+       mov     edx,0x0e688100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnem:\r
+       mov     edx,0x0e688140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnep:\r
+       mov     edx,0x0e688120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnez:\r
+       mov     edx,0x0e688160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgns:\r
+       mov     edx,0x0e608100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnsm:\r
+       mov     edx,0x0e608140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnsp:\r
+       mov     edx,0x0e608120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_lgnsz:\r
+       mov     edx,0x0e608160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logd:\r
+       mov     edx,0x0e508180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logdm:\r
+       mov     edx,0x0e5081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logdp:\r
+       mov     edx,0x0e5081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logdz:\r
+       mov     edx,0x0e5081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_loge:\r
+       mov     edx,0x0e588100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logem:\r
+       mov     edx,0x0e588140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logep:\r
+       mov     edx,0x0e588120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logez:\r
+       mov     edx,0x0e588160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logs:\r
+       mov     edx,0x0e508100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logsm:\r
+       mov     edx,0x0e508140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logsp:\r
+       mov     edx,0x0e508120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_logsz:\r
+       mov     edx,0x0e508160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfd:\r
+       mov     edx,0x0e108180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfdm:\r
+       mov     edx,0x0e1081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfdp:\r
+       mov     edx,0x0e1081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfdz:\r
+       mov     edx,0x0e1081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfe:\r
+       mov     edx,0x0e188100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfem:\r
+       mov     edx,0x0e188140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfep:\r
+       mov     edx,0x0e188120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfez:\r
+       mov     edx,0x0e188160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfs:\r
+       mov     edx,0x0e108100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfsm:\r
+       mov     edx,0x0e108140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfsp:\r
+       mov     edx,0x0e108120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mnfsz:\r
+       mov     edx,0x0e108160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mufd:\r
+       mov     edx,0x0e100180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufdm:\r
+       mov     edx,0x0e1001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufdp:\r
+       mov     edx,0x0e1001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufdz:\r
+       mov     edx,0x0e1001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufe:\r
+       mov     edx,0x0e180100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufem:\r
+       mov     edx,0x0e180140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufep:\r
+       mov     edx,0x0e180120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufez:\r
+       mov     edx,0x0e180160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufs:\r
+       mov     edx,0x0e100100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufsm:\r
+       mov     edx,0x0e100140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufsp:\r
+       mov     edx,0x0e100120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mufsz:\r
+       mov     edx,0x0e100160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_mvfd:\r
+       mov     edx,0x0e008180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfdm:\r
+       mov     edx,0x0e0081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfdp:\r
+       mov     edx,0x0e0081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfdz:\r
+       mov     edx,0x0e0081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfe:\r
+       mov     edx,0x0e088100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfem:\r
+       mov     edx,0x0e088140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfep:\r
+       mov     edx,0x0e088120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfez:\r
+       mov     edx,0x0e088160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfs:\r
+       mov     edx,0x0e008100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfsm:\r
+       mov     edx,0x0e008140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfsp:\r
+       mov     edx,0x0e008120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_mvfsz:\r
+       mov     edx,0x0e008160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmd:\r
+       mov     edx,0x0ef08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmdm:\r
+       mov     edx,0x0ef081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmdp:\r
+       mov     edx,0x0ef081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmdz:\r
+       mov     edx,0x0ef081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrme:\r
+       mov     edx,0x0ef88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmem:\r
+       mov     edx,0x0ef88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmep:\r
+       mov     edx,0x0ef88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmez:\r
+       mov     edx,0x0ef88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrms:\r
+       mov     edx,0x0ef08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmsm:\r
+       mov     edx,0x0ef08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmsp:\r
+       mov     edx,0x0ef08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_nrmsz:\r
+       mov     edx,0x0ef08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_pold:\r
+       mov     edx,0x0ec00180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_poldm:\r
+       mov     edx,0x0ec001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_poldp:\r
+       mov     edx,0x0ec001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_poldz:\r
+       mov     edx,0x0ec001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_pole:\r
+       mov     edx,0x0ec80100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polem:\r
+       mov     edx,0x0ec80140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polep:\r
+       mov     edx,0x0ec80120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polez:\r
+       mov     edx,0x0ec80160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_pols:\r
+       mov     edx,0x0ec00100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polsm:\r
+       mov     edx,0x0ec00140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polsp:\r
+       mov     edx,0x0ec00120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_polsz:\r
+       mov     edx,0x0ec00160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powd:\r
+       mov     edx,0x0e600180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powdm:\r
+       mov     edx,0x0e6001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powdp:\r
+       mov     edx,0x0e6001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powdz:\r
+       mov     edx,0x0e6001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powe:\r
+       mov     edx,0x0e680100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powem:\r
+       mov     edx,0x0e680140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powep:\r
+       mov     edx,0x0e680120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powez:\r
+       mov     edx,0x0e680160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_pows:\r
+       mov     edx,0x0e600100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powsm:\r
+       mov     edx,0x0e600140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powsp:\r
+       mov     edx,0x0e600120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_powsz:\r
+       mov     edx,0x0e600160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfd:\r
+       mov     edx,0x0e500180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfdm:\r
+       mov     edx,0x0e5001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfdp:\r
+       mov     edx,0x0e5001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfdz:\r
+       mov     edx,0x0e5001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfe:\r
+       mov     edx,0x0e580100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfem:\r
+       mov     edx,0x0e580140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfep:\r
+       mov     edx,0x0e580120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfez:\r
+       mov     edx,0x0e580160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfs:\r
+       mov     edx,0x0e500100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfsm:\r
+       mov     edx,0x0e500140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfsp:\r
+       mov     edx,0x0e500120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rdfsz:\r
+       mov     edx,0x0e500160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rfc:\r
+       mov     edx,0x0e500110\r
+       jmp     FPA_rd\r
+ARM_instruction_rfs:\r
+       mov     edx,0x0e300110\r
+       jmp     FPA_rd\r
+ARM_instruction_rmfd:\r
+       mov     edx,0x0e800180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfdm:\r
+       mov     edx,0x0e8001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfdp:\r
+       mov     edx,0x0e8001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfdz:\r
+       mov     edx,0x0e8001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfe:\r
+       mov     edx,0x0e880100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfem:\r
+       mov     edx,0x0e880140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfep:\r
+       mov     edx,0x0e880120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfez:\r
+       mov     edx,0x0e880160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfs:\r
+       mov     edx,0x0e800100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfsm:\r
+       mov     edx,0x0e800140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfsp:\r
+       mov     edx,0x0e800120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rmfsz:\r
+       mov     edx,0x0e800160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rndd:\r
+       mov     edx,0x0e308180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rnddm:\r
+       mov     edx,0x0e3081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rnddp:\r
+       mov     edx,0x0e3081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rnddz:\r
+       mov     edx,0x0e3081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rnde:\r
+       mov     edx,0x0e388100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndem:\r
+       mov     edx,0x0e388140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndep:\r
+       mov     edx,0x0e388120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndez:\r
+       mov     edx,0x0e388160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rnds:\r
+       mov     edx,0x0e308100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndsm:\r
+       mov     edx,0x0e308140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndsp:\r
+       mov     edx,0x0e308120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rndsz:\r
+       mov     edx,0x0e308160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_rpwd:\r
+       mov     edx,0x0e700180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwdm:\r
+       mov     edx,0x0e7001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwdp:\r
+       mov     edx,0x0e7001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwdz:\r
+       mov     edx,0x0e7001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwe:\r
+       mov     edx,0x0e780100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwem:\r
+       mov     edx,0x0e780140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwep:\r
+       mov     edx,0x0e780120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwez:\r
+       mov     edx,0x0e780160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpws:\r
+       mov     edx,0x0e700100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwsm:\r
+       mov     edx,0x0e700140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwsp:\r
+       mov     edx,0x0e700120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rpwsz:\r
+       mov     edx,0x0e700160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfd:\r
+       mov     edx,0x0e300180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfdm:\r
+       mov     edx,0x0e3001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfdp:\r
+       mov     edx,0x0e3001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfdz:\r
+       mov     edx,0x0e3001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfe:\r
+       mov     edx,0x0e380100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfem:\r
+       mov     edx,0x0e380140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfep:\r
+       mov     edx,0x0e380120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfez:\r
+       mov     edx,0x0e380160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfs:\r
+       mov     edx,0x0e300100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfsm:\r
+       mov     edx,0x0e300140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfsp:\r
+       mov     edx,0x0e300120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_rsfsz:\r
+       mov     edx,0x0e300160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sfm:\r
+       mov     edx,0x0c000200\r
+       jmp     FPA_fd_imm_address5\r
+ARM_instruction_sfmea:\r
+       mov     edx,0x0c800200\r
+       jmp     FPA_fd_imm_rn\r
+ARM_instruction_sfmfd:\r
+       mov     edx,0x0d000200\r
+       jmp     FPA_fd_imm_rn\r
+ARM_instruction_sind:\r
+       mov     edx,0x0e808180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sindm:\r
+       mov     edx,0x0e8081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sindp:\r
+       mov     edx,0x0e8081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sindz:\r
+       mov     edx,0x0e8081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sine:\r
+       mov     edx,0x0e888100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinem:\r
+       mov     edx,0x0e888140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinep:\r
+       mov     edx,0x0e888120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinez:\r
+       mov     edx,0x0e888160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sins:\r
+       mov     edx,0x0e808100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinsm:\r
+       mov     edx,0x0e808140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinsp:\r
+       mov     edx,0x0e808120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sinsz:\r
+       mov     edx,0x0e808160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtd:\r
+       mov     edx,0x0e408180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtdm:\r
+       mov     edx,0x0e4081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtdp:\r
+       mov     edx,0x0e4081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtdz:\r
+       mov     edx,0x0e4081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqte:\r
+       mov     edx,0x0e488100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtem:\r
+       mov     edx,0x0e488140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtep:\r
+       mov     edx,0x0e488120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtez:\r
+       mov     edx,0x0e488160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqts:\r
+       mov     edx,0x0e408100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtsm:\r
+       mov     edx,0x0e408140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtsp:\r
+       mov     edx,0x0e408120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_sqtsz:\r
+       mov     edx,0x0e408160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_stfd:\r
+       mov     edx,0x0c008100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_stfe:\r
+       mov     edx,0x0c400100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_stfp:\r
+       mov     edx,0x0c408100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_stfs:\r
+       mov     edx,0x0c000100\r
+       jmp     FPA_fd_address5\r
+ARM_instruction_sufd:\r
+       mov     edx,0x0e200180\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufdm:\r
+       mov     edx,0x0e2001c0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufdp:\r
+       mov     edx,0x0e2001a0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufdz:\r
+       mov     edx,0x0e2001e0\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufe:\r
+       mov     edx,0x0e280100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufem:\r
+       mov     edx,0x0e280140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufep:\r
+       mov     edx,0x0e280120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufez:\r
+       mov     edx,0x0e280160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufs:\r
+       mov     edx,0x0e200100\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufsm:\r
+       mov     edx,0x0e200140\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufsp:\r
+       mov     edx,0x0e200120\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_sufsz:\r
+       mov     edx,0x0e200160\r
+       jmp     FPA_fd_fn_fm\r
+ARM_instruction_tand:\r
+       mov     edx,0x0ea08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tandm:\r
+       mov     edx,0x0ea081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tandp:\r
+       mov     edx,0x0ea081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tandz:\r
+       mov     edx,0x0ea081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tane:\r
+       mov     edx,0x0ea88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tanem:\r
+       mov     edx,0x0ea88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tanep:\r
+       mov     edx,0x0ea88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tanez:\r
+       mov     edx,0x0ea88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tans:\r
+       mov     edx,0x0ea08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tansm:\r
+       mov     edx,0x0ea08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tansp:\r
+       mov     edx,0x0ea08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_tansz:\r
+       mov     edx,0x0ea08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdd:\r
+       mov     edx,0x0ee08180\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urddm:\r
+       mov     edx,0x0ee081c0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urddp:\r
+       mov     edx,0x0ee081a0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urddz:\r
+       mov     edx,0x0ee081e0\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urde:\r
+       mov     edx,0x0ee88100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdem:\r
+       mov     edx,0x0ee88140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdep:\r
+       mov     edx,0x0ee88120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdez:\r
+       mov     edx,0x0ee88160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urds:\r
+       mov     edx,0x0ee08100\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdsm:\r
+       mov     edx,0x0ee08140\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdsp:\r
+       mov     edx,0x0ee08120\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_urdsz:\r
+       mov     edx,0x0ee08160\r
+       jmp     FPA_fd_fm\r
+ARM_instruction_wfc:\r
+       mov     edx,0x0e400110\r
+       jmp     FPA_rd\r
+ARM_instruction_wfs:\r
+       mov     edx,0x0e200110\r
+       jmp     FPA_rd\r
+\r
+;Maverick jump table\r
+\r
+ARM_instruction_cfabs32:\r
+       mov     edx,0x0e300500\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfabs64:\r
+       mov     edx,0x0e300520\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfabsd:\r
+       mov     edx,0x0e300420\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfabss:\r
+       mov     edx,0x0e300400\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfadd32:\r
+       mov     edx,0x0e300580\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfadd64:\r
+       mov     edx,0x0e3005a0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfaddd:\r
+       mov     edx,0x0e3004a0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfadds:\r
+       mov     edx,0x0e300480\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfcmp32:\r
+       mov     edx,0x0e100590\r
+       jmp     MAVERICK_rd_crn_crm\r
+ARM_instruction_cfcmp64:\r
+       mov     edx,0x0e1005b0\r
+       jmp     MAVERICK_rd_crn_crm\r
+ARM_instruction_cfcmpd:\r
+       mov     edx,0x0e1004b0\r
+       jmp     MAVERICK_rd_crn_crm\r
+ARM_instruction_cfcmps:\r
+       mov     edx,0x0e100490\r
+       jmp     MAVERICK_rd_crn_crm\r
+ARM_instruction_cfcpyd:\r
+       mov     edx,0x0e000420\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcpys:\r
+       mov     edx,0x0e000400\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvt32d:\r
+       mov     edx,0x0e0004a0\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvt32s:\r
+       mov     edx,0x0e000480\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvt64d:\r
+       mov     edx,0x0e0004e0\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvt64s:\r
+       mov     edx,0x0e0004c0\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvtd32:\r
+       mov     edx,0x0e1005a0\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvtds:\r
+       mov     edx,0x0e000440\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvts32:\r
+       mov     edx,0x0e100580\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfcvtsd:\r
+       mov     edx,0x0e000460\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfldr32:\r
+       mov     edx,0x0c100500\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfldr64:\r
+       mov     edx,0x0c500500\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfldrd:\r
+       mov     edx,0x0c500400\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfldrs:\r
+       mov     edx,0x0c100400\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfmac32:\r
+       mov     edx,0x0e100540\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmadd32:\r
+       mov     edx,0x0e000600\r
+       jmp     MAVERICK_aa_crd_crn_crm\r
+ARM_instruction_cfmadda32:\r
+       mov     edx,0x0e200600\r
+       jmp     MAVERICK_aa_ad_crn_crm\r
+ARM_instruction_cfmsc32:\r
+       mov     edx,0x0e100560\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmsub32:\r
+       mov     edx,0x0e100600\r
+       jmp     MAVERICK_aa_crd_crn_crm\r
+ARM_instruction_cfmsuba32:\r
+       mov     edx,0x0e300600\r
+       jmp     MAVERICK_aa_ad_crn_crm\r
+ARM_instruction_cfmul32:\r
+       mov     edx,0x0e100500\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmul64:\r
+       mov     edx,0x0e100520\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmuld:\r
+       mov     edx,0x0e100420\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmuls:\r
+       mov     edx,0x0e100400\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfmv32a:\r
+       mov     edx,0x0e1004a0\r
+       jmp     MAVERICK_crd_an\r
+ARM_instruction_cfmv32ah:\r
+       mov     edx,0x0e100480\r
+       jmp     MAVERICK_crd_an\r
+ARM_instruction_cfmv32al:\r
+       mov     edx,0x0e100440\r
+       jmp     MAVERICK_crd_an\r
+ARM_instruction_cfmv32am:\r
+       mov     edx,0x0e100460\r
+       jmp     MAVERICK_crd_an\r
+ARM_instruction_cfmv32sc:\r
+       mov     edx,0x0e1004e0\r
+       jmp     MAVERICK_crd_psc\r
+ARM_instruction_cfmv64a:\r
+       mov     edx,0x0e1004c0\r
+       jmp     MAVERICK_crd_an\r
+ARM_instruction_cfmv64hr:\r
+       mov     edx,0x0e000530\r
+       jmp     MAVERICK_crn_rd\r
+ARM_instruction_cfmv64lr:\r
+       mov     edx,0x0e000510\r
+       jmp     MAVERICK_crn_rd\r
+ARM_instruction_cfmva32:\r
+       mov     edx,0x0e2004a0\r
+       jmp     MAVERICK_ad_crn\r
+ARM_instruction_cfmva64:\r
+       mov     edx,0x0e2004c0\r
+       jmp     MAVERICK_ad_crn\r
+ARM_instruction_cfmvah32:\r
+       mov     edx,0x0e200480\r
+       jmp     MAVERICK_ad_crn\r
+ARM_instruction_cfmval32:\r
+       mov     edx,0x0e200440\r
+       jmp     MAVERICK_ad_crn\r
+ARM_instruction_cfmvam32:\r
+       mov     edx,0x0e200460\r
+       jmp     MAVERICK_ad_crn\r
+ARM_instruction_cfmvdhr:\r
+       mov     edx,0x0e000430\r
+       jmp     MAVERICK_crn_rd\r
+ARM_instruction_cfmvdlr:\r
+       mov     edx,0x0e000410\r
+       jmp     MAVERICK_crn_rd\r
+ARM_instruction_cfmvr64h:\r
+       mov     edx,0x0e100530\r
+       jmp     MAVERICK_rd_crn\r
+ARM_instruction_cfmvr64l:\r
+       mov     edx,0x0e100510\r
+       jmp     MAVERICK_rd_crn\r
+ARM_instruction_cfmvrdh:\r
+       mov     edx,0x0e100430\r
+       jmp     MAVERICK_rd_crn\r
+ARM_instruction_cfmvrdl:\r
+       mov     edx,0x0e100410\r
+       jmp     MAVERICK_rd_crn\r
+ARM_instruction_cfmvrs:\r
+       mov     edx,0x0e100450\r
+       jmp     MAVERICK_rd_crn\r
+ARM_instruction_cfmvsc32:\r
+       mov     edx,0x0e2004e0\r
+       jmp     MAVERICK_psc_crd\r
+ARM_instruction_cfmvsr:\r
+       mov     edx,0x0e000450\r
+       jmp     MAVERICK_crn_rd\r
+ARM_instruction_cfneg32:\r
+       mov     edx,0x0e300540\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfneg64:\r
+       mov     edx,0x0e300560\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfnegd:\r
+       mov     edx,0x0e300460\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfnegs:\r
+       mov     edx,0x0e300440\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cfrshl32:\r
+       mov     edx,0x0e000550\r
+       jmp     MAVERICK_crm_crn_rd\r
+ARM_instruction_cfrshl64:\r
+       mov     edx,0x0e000570\r
+       jmp     MAVERICK_crm_crn_rd\r
+ARM_instruction_cfsh32:\r
+       mov     edx,0x0e000500\r
+       jmp     MAVERICK_crd_crn_imm\r
+ARM_instruction_cfsh64:\r
+       mov     edx,0x0e200500\r
+       jmp     MAVERICK_crd_crn_imm\r
+ARM_instruction_cfstr32:\r
+       mov     edx,0x0c000500\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfstr64:\r
+       mov     edx,0x0c400500\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfstrd:\r
+       mov     edx,0x0c400400\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfstrs:\r
+       mov     edx,0x0c000400\r
+       jmp     MAVERICK_crd_address5\r
+ARM_instruction_cfsub32:\r
+       mov     edx,0x0e3005c0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfsub64:\r
+       mov     edx,0x0e3005e0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfsubd:\r
+       mov     edx,0x0e3004e0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cfsubs:\r
+       mov     edx,0x0e3004c0\r
+       jmp     MAVERICK_crd_crn_crm\r
+ARM_instruction_cftruncd32:\r
+       mov     edx,0x0e1005e0\r
+       jmp     MAVERICK_crd_crn\r
+ARM_instruction_cftruncs32:\r
+       mov     edx,0x0e1005c0\r
+       jmp     MAVERICK_crd_crn\r
+\r
+;VFP jump table\r
+\r
+ARM_instruction_fabsd:\r
+       mov     edx,0x0eb00bc0\r
+       jmp     VFP_dd_dm\r
+ARM_instruction_fabss:\r
+       mov     edx,0x0eb00ac0\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_faddd:\r
+       mov     edx,0x0e300b00\r
+       jmp     VFP_dd_dn_dm\r
+ARM_instruction_fadds:\r
+       mov     edx,0x0e300a00\r
+       jmp     VFP_sd_sn_sm\r
+ARM_instruction_fcmpd:\r
+       mov     edx,0x0eb40b40\r
+       jmp     VFP_dd_dm_zero\r
+ARM_instruction_fcmped:\r
+       mov     edx,0x0eb40bc0\r
+       jmp     VFP_dd_dm_zero\r
+ARM_instruction_fcmpes:\r
+       mov     edx,0x0eb40ac0\r
+       jmp     VFP_sd_sm_zero\r
+ARM_instruction_fcmpezd:\r
+       mov     edx,0x0eb50bc0\r
+       jmp     VFP_dd\r
+ARM_instruction_fcmpezs:\r
+       mov     edx,0x0eb50ac0\r
+       jmp     VFP_sd\r
+ARM_instruction_fcmps:\r
+       mov     edx,0x0eb40a40\r
+       jmp     VFP_sd_sm_zero\r
+ARM_instruction_fcmpzd:\r
+       mov     edx,0x0eb50b40\r
+       jmp     VFP_dd\r
+ARM_instruction_fcmpzs:\r
+       mov     edx,0x0eb50a40\r
+       jmp     VFP_sd\r
+ARM_instruction_fconstd:\r
+       mov     edx,0x0eb00b00\r
+       jmp     VFP_dm_imm\r
+ARM_instruction_fconsts:\r
+       mov     edx,0x0eb00a00\r
+       jmp     VFP_sm_imm\r
+ARM_instruction_fcpyd:\r
+       mov     edx,0x0eb00b40\r
+       jmp     VFP_dd_dm\r
+ARM_instruction_fcpys:\r
+       mov     edx,0x0eb00a40\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_fcvtds:\r
+       mov     edx,0x0eb70ac0\r
+       jmp     VFP_dd_sm\r
+ARM_instruction_fcvtsd:\r
+       mov     edx,0x0eb70bc0\r
+       jmp     VFP_sd_dm\r
+ARM_instruction_fdivd:\r
+       mov     edx,0x0e800b00\r
+       jmp     VFP_dd_dn_dm\r
+ARM_instruction_fdivs:\r
+       mov     edx,0x0e800a00\r
+       jmp     VFP_sd_sn_sm\r
+ARM_instruction_fldd:\r
+       mov     edx,0x0d100b00\r
+       jmp     VFP_dd_rn_offset\r
+ARM_instruction_fldmdbd:\r
+ARM_instruction_fldmead:\r
+       mov     edx,0xd100b00\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fldmdbx:\r
+ARM_instruction_fldmeax:\r
+       mov     edx,0xd100b01\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fldmdbs:\r
+ARM_instruction_fldmeas:\r
+       mov     edx,0xd100a00\r
+       jmp     VFP_rn_list_s\r
+ARM_instruction_fldmd:\r
+ARM_instruction_fldmiad:\r
+ARM_instruction_fldmfdd:\r
+       mov     edx,0xc900b00\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fldmx:\r
+ARM_instruction_fldmiax:\r
+ARM_instruction_fldmfdx:\r
+       mov     edx,0xc900b01\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fldms:\r
+ARM_instruction_fldmias:\r
+ARM_instruction_fldmfds:\r
+       mov     edx,0xc900a00\r
+       jmp     VFP_rn_list_s\r
+ARM_instruction_flds:\r
+       mov     edx,0x0d100a00\r
+       jmp     VFP_sd_rn_offset\r
+ARM_instruction_fmacd:\r
+       mov     edx,0x0e000b00\r
+       jmp     VFP_FLOAT_dd_dn_dm\r
+ARM_instruction_fmacs:\r
+       mov     edx,0x0e000a00\r
+       jmp     VFP_FLOAT_sd_sn_sm\r
+ARM_instruction_fmdhr:\r
+       mov     edx,0xe200b10\r
+       jmp     VFP_dn_rd\r
+ARM_instruction_fmdlr:\r
+       mov     edx,0xe000b10\r
+       jmp     VFP_dn_rd\r
+ARM_instruction_fmdrr:\r
+       mov     edx,0x0c400b10\r
+       jmp     VFP_dm_rd_rn\r
+ARM_instruction_fmrdh:\r
+       mov     edx,0x0e300b10\r
+       jmp     VFP_rd_dn\r
+ARM_instruction_fmrdl:\r
+       mov     edx,0x0e100b10\r
+       jmp     VFP_rd_dn\r
+ARM_instruction_fmrrd:\r
+       mov     edx,0x0c500b10\r
+       jmp     VFP_rd_rn_dm\r
+ARM_instruction_fmrrs:\r
+       mov     edx,0x0c500a10\r
+       jmp     VFP_rd_rn_sm\r
+ARM_instruction_fmrs:\r
+       mov     edx,0x0e100a10\r
+       jmp     VFP_rd_sn\r
+ARM_instruction_fmrx:\r
+       mov     edx,0x0ef00a10\r
+       jmp     VFP_rd_sysreg\r
+ARM_instruction_fmscd:\r
+       mov     edx,0x0e100b00\r
+       jmp     VFP_FLOAT_dd_dn_dm\r
+ARM_instruction_fmscs:\r
+       mov     edx,0x0e100a00\r
+       jmp     VFP_FLOAT_sd_sn_sm\r
+ARM_instruction_fmsr:\r
+       mov     edx,0x0e000a10\r
+       jmp     VFP_sn_rd\r
+ARM_instruction_fmsrr:\r
+       mov     edx,0x0c400a10\r
+       jmp     VFP_sm_rd_rn\r
+ARM_instruction_fmstat:\r
+       mov     edx,0x0ef1fa10\r
+       jmp     VFP_fmstat\r
+ARM_instruction_fmuld:\r
+       mov     edx,0x0e200b00\r
+       jmp     VFP_dd_dn_dm\r
+ARM_instruction_fmuls:\r
+       mov     edx,0x0e200a00\r
+       jmp     VFP_sd_sn_sm\r
+ARM_instruction_fmxr:\r
+       mov     edx,0x0ee00a10\r
+       jmp     VFP_sysreg_rd\r
+ARM_instruction_fnegd:\r
+       mov     edx,0x0eb10b40\r
+       jmp     VFP_dd_dm\r
+ARM_instruction_fnegs:\r
+       mov     edx,0x0eb10a40\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_fnmacd:\r
+       mov     edx,0x0e000b40\r
+       jmp     VFP_FLOAT_dd_dn_dm\r
+ARM_instruction_fnmacs:\r
+       mov     edx,0x0e000a40\r
+       jmp     VFP_FLOAT_sd_sn_sm\r
+ARM_instruction_fnmscd:\r
+       mov     edx,0x0e100b40\r
+       jmp     VFP_FLOAT_dd_dn_dm\r
+ARM_instruction_fnmscs:\r
+       mov     edx,0x0e100a40\r
+       jmp     VFP_FLOAT_sd_sn_sm\r
+ARM_instruction_fnmuld:\r
+       mov     edx,0x0e200b40\r
+       jmp     VFP_dd_dn_dm\r
+ARM_instruction_fnmuls:\r
+       mov     edx,0x0e200a40\r
+       jmp     VFP_sd_sn_sm\r
+ARM_instruction_fshtod:\r
+       mov     edx,0x0eba0b40\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_fshtos:\r
+       mov     edx,0x0eba0a40\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_fsitod:\r
+       mov     edx,0x0eb80bc0\r
+       jmp     VFP_dd_sm\r
+ARM_instruction_fsitos:\r
+       mov     edx,0x0eb80ac0\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_fsltod:\r
+       mov     edx,0x0eba0bc0\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_fsltos:\r
+       mov     edx,0x0eba0ac0\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_fsqrtd:\r
+       mov     edx,0x0eb10bc0\r
+       jmp     VFP_dd_dm\r
+ARM_instruction_fsqrts:\r
+       mov     edx,0x0eb10ac0\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_fstd:\r
+       mov     edx,0x0d000b00\r
+       jmp     VFP_dd_rn_offset\r
+ARM_instruction_fstmdbd:\r
+ARM_instruction_fstmfdd:\r
+       mov     edx,0xd000b00\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fstmdbx:\r
+ARM_instruction_fstmfdx:\r
+       mov     edx,0xd000b01\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fstmdbs:\r
+ARM_instruction_fstmfds:\r
+       mov     edx,0xd000a00\r
+       jmp     VFP_rn_list_s\r
+ARM_instruction_fstmd:\r
+ARM_instruction_fstmiad:\r
+ARM_instruction_fstmead:\r
+       mov     edx,0xc800b00\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fstmx:\r
+ARM_instruction_fstmiax:\r
+ARM_instruction_fstmeax:\r
+       mov     edx,0xc800b01\r
+       jmp     VFP_rn_list_d\r
+ARM_instruction_fstms:\r
+ARM_instruction_fstmias:\r
+ARM_instruction_fstmeas:\r
+       mov     edx,0xc800a00\r
+       jmp     VFP_rn_list_s\r
+ARM_instruction_fsts:\r
+       mov     edx,0x0d000a00\r
+       jmp     VFP_sd_rn_offset\r
+ARM_instruction_fsubd:\r
+       mov     edx,0x0e300b40\r
+       jmp     VFP_dd_dn_dm\r
+ARM_instruction_fsubs:\r
+       mov     edx,0x0e300a40\r
+       jmp     VFP_sd_sn_sm\r
+ARM_instruction_ftoshd:\r
+       mov     edx,0x0ebe0b40\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_ftoshs:\r
+       mov     edx,0x0ebe0a40\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_ftosid:\r
+       mov     edx,0x0ebd0b40\r
+       jmp     VFP_sd_dm\r
+ARM_instruction_ftosis:\r
+       mov     edx,0x0ebd0a40\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_ftosizd:\r
+       mov     edx,0x0ebd0bc0\r
+       jmp     VFP_sd_dm\r
+ARM_instruction_ftosizs:\r
+       mov     edx,0x0ebd0ac0\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_ftosld:\r
+       mov     edx,0x0ebe0bc0\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_ftosls:\r
+       mov     edx,0x0ebe0ac0\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_ftouhd:\r
+       mov     edx,0x0ebf0b40\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_ftouhs:\r
+       mov     edx,0x0ebf0a40\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_ftouid:\r
+       mov     edx,0x0ebc0b40\r
+       jmp     VFP_sd_dm\r
+ARM_instruction_ftouis:\r
+       mov     edx,0x0ebc0a40\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_ftouizd:\r
+       mov     edx,0x0ebc0bc0\r
+       jmp     VFP_sd_dm\r
+ARM_instruction_ftouizs:\r
+       mov     edx,0x0ebc0ac0\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_ftould:\r
+       mov     edx,0x0ebf0bc0\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_ftouls:\r
+       mov     edx,0x0ebf0ac0\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_fuhtod:\r
+       mov     edx,0x0ebb0b40\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_fuhtos:\r
+       mov     edx,0x0ebb0a40\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_fuitod:\r
+       mov     edx,0x0eb80b40\r
+       jmp     VFP_dd_sm\r
+ARM_instruction_fuitos:\r
+       mov     edx,0x0eb80a40\r
+       jmp     VFP_sd_sm\r
+ARM_instruction_fultod:\r
+       mov     edx,0x0ebb0bc0\r
+       jmp     VFP_dd_dd_imm\r
+ARM_instruction_fultos:\r
+       mov     edx,0x0ebb0ac0\r
+       jmp     VFP_sd_sd_imm\r
+ARM_instruction_vcvtb.f16.f32:\r
+       mov     edx,0x0eb30a40\r
+       jmp     VFP_sd_sm_HP\r
+ARM_instruction_vcvtb.f32.f16:\r
+       mov     edx,0x0eb20a40\r
+       jmp     VFP_sd_sm_HP\r
+ARM_instruction_vcvtt.f16.f32:\r
+       mov     edx,0x0eb30ac0\r
+       jmp     VFP_sd_sm_HP\r
+ARM_instruction_vcvtt.f32.f16:\r
+       mov     edx,0x0eb20ac0\r
+       jmp     VFP_sd_sm_HP\r
+\r
+;xScale jump table\r
+\r
+ARM_instruction_mar:\r
+       mov     edx,0x0c400000\r
+       jmp     XSCALE_acc_rdlo_rdhi\r
+ARM_instruction_mia:\r
+       mov     edx,0x0e200010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_miabb:\r
+       mov     edx,0x0e2c0010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_miabt:\r
+       mov     edx,0x0e2d0010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_miaph:\r
+       mov     edx,0x0e280010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_miatb:\r
+       mov     edx,0x0e2e0010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_miatt:\r
+       mov     edx,0x0e2f0010\r
+       jmp     XSCALE_acc_rm_rs\r
+ARM_instruction_mra:\r
+       mov     edx,0x0c500000\r
+       jmp     XSCALE_rdlo_rdhi_acc\r
+\r
+;IWMMXT v1 jump table\r
+\r
+ARM_instruction_tandcb:\r
+       mov     edx,0x0e13f130\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_tandch:\r
+       mov     edx,0x0e53f130\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_tandcw:\r
+       mov     edx,0x0e93f130\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_tbcstb:\r
+       mov     edx,0x0e400010\r
+       jmp     IWMMXT_wrd_rn\r
+ARM_instruction_tbcsth:\r
+       mov     edx,0x0e400050\r
+       jmp     IWMMXT_wrd_rn\r
+ARM_instruction_tbcstw:\r
+       mov     edx,0x0e400090\r
+       jmp     IWMMXT_wrd_rn\r
+ARM_instruction_textrcb:\r
+       mov     edx,0x0e13f170\r
+       jmp     IWMMXT_r15_imm\r
+ARM_instruction_textrch:\r
+       mov     edx,0x0e53f170\r
+       jmp     IWMMXT_r15_imm\r
+ARM_instruction_textrcw:\r
+       mov     edx,0x0e93f170\r
+       jmp     IWMMXT_r15_imm\r
+ARM_instruction_textrmsb:\r
+       mov     edx,0x0e100078\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_textrmsh:\r
+       mov     edx,0x0e500078\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_textrmsw:\r
+       mov     edx,0x0e900078\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_textrmub:\r
+       mov     edx,0x0e100070\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_textrmuh:\r
+       mov     edx,0x0e500070\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_textrmuw:\r
+       mov     edx,0x0e900070\r
+       jmp     IWMMXT_rd_wrn_imm\r
+ARM_instruction_tinsrb:\r
+       mov     edx,0x0e600010\r
+       jmp     IWMMXT_wrd_rn_imm\r
+ARM_instruction_tinsrh:\r
+       mov     edx,0x0e600050\r
+       jmp     IWMMXT_wrd_rn_imm\r
+ARM_instruction_tinsrw:\r
+       mov     edx,0x0e600090\r
+       jmp     IWMMXT_wrd_rn_imm\r
+ARM_instruction_tmcr:\r
+       mov     edx,0x0e000110\r
+       jmp     IWMMXT_wcd_rn\r
+ARM_instruction_tmcrr:\r
+       mov     edx,0x0c400000\r
+       jmp     IWMMXT_wrd_rdlo_rdhi\r
+ARM_instruction_tmia:\r
+       mov     edx,0x0e200010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmiabb:\r
+       mov     edx,0x0e2c0010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmiabt:\r
+       mov     edx,0x0e2d0010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmiaph:\r
+       mov     edx,0x0e280010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmiatb:\r
+       mov     edx,0x0e2e0010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmiatt:\r
+       mov     edx,0x0e2f0010\r
+       jmp     IWMMXT_wrd_rm_rs\r
+ARM_instruction_tmovmskb:\r
+       mov     edx,0x0e100030\r
+       jmp     IWMMXT_rd_wrn\r
+ARM_instruction_tmovmskh:\r
+       mov     edx,0x0e500030\r
+       jmp     IWMMXT_rd_wrn\r
+ARM_instruction_tmovmskw:\r
+       mov     edx,0x0e900030\r
+       jmp     IWMMXT_rd_wrn\r
+ARM_instruction_tmrc:\r
+       mov     edx,0x0e100110\r
+       jmp     IWMMXT_rd_wcn\r
+ARM_instruction_tmrrc:\r
+       mov     edx,0x0c500000\r
+       jmp     IWMMXT_rdlo_rdhi_wrn\r
+ARM_instruction_torcb:\r
+       mov     edx,0x0e13f150\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_torch:\r
+       mov     edx,0x0e53f150\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_torcw:\r
+       mov     edx,0x0e93f150\r
+       jmp     IWMMXT_r15\r
+ARM_instruction_waccb:\r
+       mov     edx,0x0e0001c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wacch:\r
+       mov     edx,0x0e4001c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_waccw:\r
+       mov     edx,0x0e8001c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_waddb:\r
+       mov     edx,0x0e000180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddbss:\r
+       mov     edx,0x0e300180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddbus:\r
+       mov     edx,0x0e100180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddh:\r
+       mov     edx,0x0e400180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddhss:\r
+       mov     edx,0x0e700180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddhus:\r
+       mov     edx,0x0e500180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddw:\r
+       mov     edx,0x0e800180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddwss:\r
+       mov     edx,0x0eb00180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waddwus:\r
+       mov     edx,0x0e900180\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_waligni:\r
+       mov     edx,0x0e000020\r
+       jmp     IWMMXT_wrd_wrn_wrm_imm\r
+ARM_instruction_walignr0:\r
+       mov     edx,0x0e800020\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_walignr1:\r
+       mov     edx,0x0e900020\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_walignr2:\r
+       mov     edx,0x0ea00020\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_walignr3:\r
+       mov     edx,0x0eb00020\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wand:\r
+       mov     edx,0x0e200000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wandn:\r
+       mov     edx,0x0e300000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wavg2b:\r
+       mov     edx,0x0e800000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wavg2br:\r
+       mov     edx,0x0e900000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wavg2h:\r
+       mov     edx,0x0ec00000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wavg2hr:\r
+       mov     edx,0x0ed00000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpeqb:\r
+       mov     edx,0x0e000060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpeqh:\r
+       mov     edx,0x0e400060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpeqw:\r
+       mov     edx,0x0e800060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtsb:\r
+       mov     edx,0x0e300060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtsh:\r
+       mov     edx,0x0e700060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtsw:\r
+       mov     edx,0x0eb00060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtub:\r
+       mov     edx,0x0e100060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtuh:\r
+       mov     edx,0x0e500060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wcmpgtuw:\r
+       mov     edx,0x0e900060\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wldrb:\r
+       mov     edx,0x0c100000\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wldrd:\r
+       mov     edx,0x0c500100\r
+       jmp     IWMMXT_wrd_address5_reg_offset\r
+ARM_instruction_wldrh:\r
+       mov     edx,0x0c500000\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wldrw:\r
+       mov     edx,0x0c100100\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wmacs:\r
+       mov     edx,0x0e600100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmacsz:\r
+       mov     edx,0x0e700100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmacu:\r
+       mov     edx,0x0e400100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmacuz:\r
+       mov     edx,0x0e500100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmadds:\r
+       mov     edx,0x0ea00100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaddu:\r
+       mov     edx,0x0e800100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxsb:\r
+       mov     edx,0x0e200160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxsh:\r
+       mov     edx,0x0e600160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxsw:\r
+       mov     edx,0x0ea00160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxub:\r
+       mov     edx,0x0e000160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxuh:\r
+       mov     edx,0x0e400160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmaxuw:\r
+       mov     edx,0x0e800160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminsb:\r
+       mov     edx,0x0e300160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminsh:\r
+       mov     edx,0x0e700160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminsw:\r
+       mov     edx,0x0eb00160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminub:\r
+       mov     edx,0x0e100160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminuh:\r
+       mov     edx,0x0e500160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wminuw:\r
+       mov     edx,0x0e900160\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmov:\r
+       mov     edx,0x0e000000\r
+       jmp     IWMMXT_wrd_wrn_WMOV\r
+ARM_instruction_wmulsl:\r
+       mov     edx,0x0e200100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmulsm:\r
+       mov     edx,0x0e300100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmulul:\r
+       mov     edx,0x0e000100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wmulum:\r
+       mov     edx,0x0e100100\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wor:\r
+       mov     edx,0x0e000000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackdss:\r
+       mov     edx,0x0ef00080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackdus:\r
+       mov     edx,0x0ed00080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackhss:\r
+       mov     edx,0x0e700080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackhus:\r
+       mov     edx,0x0e500080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackwss:\r
+       mov     edx,0x0eb00080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wpackwus:\r
+       mov     edx,0x0e900080\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wrord:\r
+       mov     edx,0x0ef00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wrordg:\r
+       mov     edx,0x0ef00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wrorh:\r
+       mov     edx,0x0e700040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wrorhg:\r
+       mov     edx,0x0e700140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wrorw:\r
+       mov     edx,0x0eb00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wrorwg:\r
+       mov     edx,0x0eb00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsadb:\r
+       mov     edx,0x0e000120\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsadbz:\r
+       mov     edx,0x0e100120\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsadh:\r
+       mov     edx,0x0e400120\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsadhz:\r
+       mov     edx,0x0e500120\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wshufh:\r
+       mov     edx,0x0e0001e0\r
+       jmp     IWMMXT_wrd_wrn_imm\r
+ARM_instruction_wslld:\r
+       mov     edx,0x0ed00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wslldg:\r
+       mov     edx,0x0ed00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsllh:\r
+       mov     edx,0x0e500040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsllhg:\r
+       mov     edx,0x0e500140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsllw:\r
+       mov     edx,0x0e900040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsllwg:\r
+       mov     edx,0x0e900140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsrad:\r
+       mov     edx,0x0ec00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsradg:\r
+       mov     edx,0x0ec00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsrah:\r
+       mov     edx,0x0e400040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsrahg:\r
+       mov     edx,0x0e400140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsraw:\r
+       mov     edx,0x0e800040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsrawg:\r
+       mov     edx,0x0e800140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsrld:\r
+       mov     edx,0x0ee00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsrldg:\r
+       mov     edx,0x0ee00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsrlh:\r
+       mov     edx,0x0e600040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsrlhg:\r
+       mov     edx,0x0e600140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wsrlw:\r
+       mov     edx,0x0ea00040\r
+       jmp     IWMMXT_wrd_wrn_param\r
+ARM_instruction_wsrlwg:\r
+       mov     edx,0x0ea00140\r
+       jmp     IWMMXT_wrd_wrn_wcm\r
+ARM_instruction_wstrb:\r
+       mov     edx,0x0c000000\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wstrd:\r
+       mov     edx,0x0c400100\r
+       jmp     IWMMXT_wrd_address5_reg_offset\r
+ARM_instruction_wstrh:\r
+       mov     edx,0x0c400000\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wstrw:\r
+       mov     edx,0x0c000100\r
+       jmp     IWMMXT_wrd_address5\r
+ARM_instruction_wsubb:\r
+       mov     edx,0x0e0001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubbss:\r
+       mov     edx,0x0e3001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubbus:\r
+       mov     edx,0x0e1001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubh:\r
+       mov     edx,0x0e4001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubhss:\r
+       mov     edx,0x0e7001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubhus:\r
+       mov     edx,0x0e5001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubw:\r
+       mov     edx,0x0e8001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubwss:\r
+       mov     edx,0x0eb001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wsubwus:\r
+       mov     edx,0x0e9001a0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckehsb:\r
+       mov     edx,0x0e2000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckehsh:\r
+       mov     edx,0x0e6000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckehsw:\r
+       mov     edx,0x0ea000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckehub:\r
+       mov     edx,0x0e0000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckehuh:\r
+       mov     edx,0x0e4000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckehuw:\r
+       mov     edx,0x0e8000c0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckelsb:\r
+       mov     edx,0x0e2000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckelsh:\r
+       mov     edx,0x0e6000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckelsw:\r
+       mov     edx,0x0ea000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckelub:\r
+       mov     edx,0x0e0000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckeluh:\r
+       mov     edx,0x0e4000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckeluw:\r
+       mov     edx,0x0e8000e0\r
+       jmp     IWMMXT_wrd_wrn\r
+ARM_instruction_wunpckihb:\r
+       mov     edx,0x0e1000c0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckihh:\r
+       mov     edx,0x0e5000c0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckihw:\r
+       mov     edx,0x0e9000c0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckilb:\r
+       mov     edx,0x0e1000e0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckilh:\r
+       mov     edx,0x0e5000e0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wunpckilw:\r
+       mov     edx,0x0e9000e0\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wxor:\r
+       mov     edx,0x0e100000\r
+       jmp     IWMMXT_wrd_wrn_wrm\r
+ARM_instruction_wzero:\r
+       mov     edx,0x0e300000\r
+       jmp     IWMMXT_wrd\r
+;IWMMXT V2 jump table\r
+ARM_instruction_torvscb:\r
+       mov     edx,0x0e12f190\r
+       jmp     IWMMXT_r15_v2\r
+ARM_instruction_torvsch:\r
+       mov     edx,0x0e52f190\r
+       jmp     IWMMXT_r15_v2\r
+ARM_instruction_torvscw:\r
+       mov     edx,0x0e92f190\r
+       jmp     IWMMXT_r15_v2\r
+ARM_instruction_wabsb:\r
+       mov     edx,0x0e2001c0\r
+       jmp     IWMMXT_rd_rn_v2\r
+ARM_instruction_wabsh:\r
+       mov     edx,0x0e6001c0\r
+       jmp     IWMMXT_rd_rn_v2\r
+ARM_instruction_wabsw:\r
+       mov     edx,0x0ea001c0\r
+       jmp     IWMMXT_rd_rn_v2\r
+ARM_instruction_wabsdiffb:\r
+       mov     edx,0x0e1001c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wabsdiffh:\r
+       mov     edx,0x0e5001c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wabsdiffw:\r
+       mov     edx,0x0e9001c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+;;ARM_instruction_waddbhusl:\r
+;;     mov     edx,0x0e2001a0\r
+;;     jmp     IWMMXT_rd_rn_rm_v2\r
+;;ARM_instruction_waddbhusm:\r
+;;     mov     edx,0x0e6001a0\r
+;;     jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_waddhc:\r
+       mov     edx,0x0e600180\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_waddwc:\r
+       mov     edx,0x0ea00180\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_waddsubhx:\r
+       mov     edx,0x0ea001a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wavg4:\r
+       mov     edx,0x0e400000\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wavg4r:\r
+       mov     edx,0x0e500000\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmaddsn:\r
+       mov     edx,0x0ee00100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmaddsx:\r
+       mov     edx,0x0eb00100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmaddun:\r
+       mov     edx,0x0ec00100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmaddux:\r
+       mov     edx,0x0e900100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmerge:\r
+       mov     edx,0x0e000080\r
+       jmp     IWMMXT_rd_rn_rm_imm\r
+ARM_instruction_wmiabb:\r
+       mov     edx,0x0e0000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiabt:\r
+       mov     edx,0x0e1000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiatb:\r
+       mov     edx,0x0e2000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiatt:\r
+       mov     edx,0x0e3000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiabbn:\r
+       mov     edx,0x0e4000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiabtn:\r
+       mov     edx,0x0e5000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiatbn:\r
+       mov     edx,0x0e6000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiattn:\r
+       mov     edx,0x0e7000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawbb:\r
+       mov     edx,0x0e800120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawbt:\r
+       mov     edx,0x0e900120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawtb:\r
+       mov     edx,0x0ea00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawtt:\r
+       mov     edx,0x0eb00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawbbn:\r
+       mov     edx,0x0ec00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawbtn:\r
+       mov     edx,0x0ed00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawtbn:\r
+       mov     edx,0x0ee00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmiawttn:\r
+       mov     edx,0x0ef00120\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulsmr:\r
+       mov     edx,0x0ef00100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulumr:\r
+       mov     edx,0x0ed00100\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulwumr:\r
+       mov     edx,0x0ec000c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulwsmr:\r
+       mov     edx,0x0ee000c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulwum:\r
+       mov     edx,0x0ed000c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulwsm:\r
+       mov     edx,0x0ef000c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wmulwl:\r
+       mov     edx,0x0eb000c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiabb:\r
+       mov     edx,0x0e8000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiabt:\r
+       mov     edx,0x0e9000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiatb:\r
+       mov     edx,0x0ea000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiatt:\r
+       mov     edx,0x0eb000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiabbn:\r
+       mov     edx,0x0ec000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiabtn:\r
+       mov     edx,0x0ed000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiatbn:\r
+       mov     edx,0x0ee000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmiattn:\r
+       mov     edx,0x0ef000a0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmulm:\r
+       mov     edx,0x0e100080\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmulmr:\r
+       mov     edx,0x0e300080\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmulwm:\r
+       mov     edx,0x0ec000e0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wqmulwmr:\r
+       mov     edx,0x0ee000e0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+ARM_instruction_wsubaddhx:\r
+       mov     edx,0x0ed001c0\r
+       jmp     IWMMXT_rd_rn_rm_v2\r
+\r
+;SIMD int & float jump table, with some aliases to VFP opcodes\r
+\r
+ARM_instruction_vaba.s16:\r
+       mov     edx,0xf2100710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vaba.s32:\r
+       mov     edx,0xf2200710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vaba.s8:\r
+       mov     edx,0xf2000710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vaba.u16:\r
+       mov     edx,0xf3100710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vaba.u32:\r
+       mov     edx,0xf3200710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vaba.u8:\r
+       mov     edx,0xf3000710\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vabal.s16:\r
+       mov     edx,0xf2900500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabal.s32:\r
+       mov     edx,0xf2a00500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabal.s8:\r
+       mov     edx,0xf2800500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabal.u16:\r
+       mov     edx,0xf3900500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabal.u32:\r
+       mov     edx,0xf3a00500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabal.u8:\r
+       mov     edx,0xf3800500\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabd.f32:\r
+       mov     edx,0xf3200d00\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vabd.s16:\r
+       mov     edx,0xf2100700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabd.s32:\r
+       mov     edx,0xf2200700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabd.s8:\r
+       mov     edx,0xf2000700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabd.u16:\r
+       mov     edx,0xf3100700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabd.u32:\r
+       mov     edx,0xf3200700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabd.u8:\r
+       mov     edx,0xf3000700\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vabdl.s16:\r
+       mov     edx,0xf2900700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabdl.s32:\r
+       mov     edx,0xf2a00700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabdl.s8:\r
+       mov     edx,0xf2800700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabdl.u16:\r
+       mov     edx,0xf3900700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabdl.u32:\r
+       mov     edx,0xf3a00700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabdl.u8:\r
+       mov     edx,0xf3800700\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vabs.f32:\r
+       mov     edx,0xf3b90700\r
+       mov     ecx,0x0eb00ac0\r
+       jmp     SIMD_FLOAT_vd_vm_f32\r
+ARM_instruction_vabs.f64 = ARM_instruction_fabsd\r
+ARM_instruction_vabs.s16:\r
+       mov     edx,0xf3b50300\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vabs.s32:\r
+       mov     edx,0xf3b90300\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vabs.s8:\r
+       mov     edx,0xf3b10300\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vacge.f32:\r
+       mov     edx,0xf3000e10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vacgt.f32:\r
+       mov     edx,0xf3200e10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vacle.f32:\r
+       mov     edx,0xf3000e10\r
+       jmp     SIMD_FLOAT_vd_vm_vn_alt\r
+ARM_instruction_vaclt.f32:\r
+       mov     edx,0xf3200e10\r
+       jmp     SIMD_FLOAT_vd_vm_vn_alt\r
+ARM_instruction_vadd.f32:\r
+       mov     edx,0xf2000d00\r
+       mov     ecx,0x0e300a00\r
+       jmp     SIMD_FLOAT_vd_vn_vm_f32\r
+ARM_instruction_vadd.f64 = ARM_instruction_faddd\r
+ARM_instruction_vadd.i16:\r
+       mov     edx,0xf2100800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vadd.i32:\r
+       mov     edx,0xf2200800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vadd.i64:\r
+       mov     edx,0xf2300800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vadd.i8:\r
+       mov     edx,0xf2000800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vaddhn.i16:\r
+       mov     edx,0xf2800400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vaddhn.i32:\r
+       mov     edx,0xf2900400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vaddhn.i64:\r
+       mov     edx,0xf2a00400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vaddl.s16:\r
+       mov     edx,0xf2900000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddl.s32:\r
+       mov     edx,0xf2a00000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddl.s8:\r
+       mov     edx,0xf2800000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddl.u16:\r
+       mov     edx,0xf3900000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddl.u32:\r
+       mov     edx,0xf3a00000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddl.u8:\r
+       mov     edx,0xf3800000\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vaddw.s16:\r
+       mov     edx,0xf2900100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vaddw.s32:\r
+       mov     edx,0xf2a00100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vaddw.s8:\r
+       mov     edx,0xf2800100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vaddw.u16:\r
+       mov     edx,0xf3900100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vaddw.u32:\r
+       mov     edx,0xf3a00100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vaddw.u8:\r
+       mov     edx,0xf3800100\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vand.i16:\r
+       mov     edx,0xf2800931\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vand.i32:\r
+       mov     edx,0xf2800131\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vand:\r
+       mov     edx,0xf2000110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vbic.i16:\r
+       mov     edx,0xf2800930\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vbic.i32:\r
+       mov     edx,0xf2800130\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vbic:\r
+       mov     edx,0xf2100110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vbif:\r
+       mov     edx,0xf3300110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vbit:\r
+       mov     edx,0xf3200110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vbsl:\r
+       mov     edx,0xf3100110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vceq.f32:\r
+       mov     edx,0xf2000e00\r
+       mov     ecx,0xf3b90500\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt_zero\r
+ARM_instruction_vceq.i16:\r
+       mov     edx,0xf3100810\r
+       mov     ecx,0xf3b50100\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vceq.i32:\r
+       mov     edx,0xf3200810\r
+       mov     ecx,0xf3b90100\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vceq.i8:\r
+       mov     edx,0xf3000810\r
+       mov     ecx,0xf3b10100\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcge.f32:\r
+       mov     edx,0xf3000e00\r
+       mov     ecx,0xf3b90480\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcge.s16:\r
+       mov     edx,0xf2100310\r
+       mov     ecx,0xf3b50080\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcge.s32:\r
+       mov     edx,0xf2200310\r
+       mov     ecx,0xf3b90080\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcge.s8:\r
+       mov     edx,0xf2000310\r
+       mov     ecx,0xf3b10080\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcge.u16:\r
+       mov     edx,0xf3100310\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcge.u32:\r
+       mov     edx,0xf3200310\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcge.u8:\r
+       mov     edx,0xf3000310\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcgt.f32:\r
+       mov     edx,0xf3200e00\r
+       mov     ecx,0xf3b90400\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcgt.s16:\r
+       mov     edx,0xf2100300\r
+       mov     ecx,0xf3b50000\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcgt.s32:\r
+       mov     edx,0xf2200300\r
+       mov     ecx,0xf3b90000\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcgt.s8:\r
+       mov     edx,0xf2000300\r
+       mov     ecx,0xf3b10000\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero\r
+ARM_instruction_vcgt.u16:\r
+       mov     edx,0xf3100300\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcgt.u32:\r
+       mov     edx,0xf3200300\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcgt.u8:\r
+       mov     edx,0xf3000300\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vcle.f32:\r
+       mov     edx,0xf3000e00\r
+       mov     ecx,0xf3b90580\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vcle.s16:\r
+       mov     edx,0xf2100310\r
+       mov     ecx,0xf3b50180\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vcle.s32:\r
+       mov     edx,0xf2200310\r
+       mov     ecx,0xf3b90180\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vcle.s8:\r
+       mov     edx,0xf2000310\r
+       mov     ecx,0xf3b10180\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vcle.u16:\r
+       mov     edx,0xf3100310\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vcle.u32:\r
+       mov     edx,0xf3200310\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vcle.u8:\r
+       mov     edx,0xf3000310\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vcls.s16:\r
+       mov     edx,0xf3b40400\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vcls.s32:\r
+       mov     edx,0xf3b80400\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vcls.s8:\r
+       mov     edx,0xf3b00400\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vclt.f32:\r
+       mov     edx,0xf3200e00\r
+       mov     ecx,0xf3b90600\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vclt.s16:\r
+       mov     edx,0xf2100300\r
+       mov     ecx,0xf3b50200\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vclt.s32:\r
+       mov     edx,0xf2200300\r
+       mov     ecx,0xf3b90200\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vclt.s8:\r
+       mov     edx,0xf2000300\r
+       mov     ecx,0xf3b10200\r
+       jmp     SIMD_INT_vd_vn_vm_alt_zero_swap\r
+ARM_instruction_vclt.u16:\r
+       mov     edx,0xf3100300\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vclt.u32:\r
+       mov     edx,0xf3200300\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vclt.u8:\r
+       mov     edx,0xf3000300\r
+       jmp     SIMD_INT_vd_vn_vm_alt_swap\r
+ARM_instruction_vclz.i16:\r
+       mov     edx,0xf3b40480\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vclz.i32:\r
+       mov     edx,0xf3b80480\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vclz.i8:\r
+       mov     edx,0xf3b00480\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vcmp.f32 = ARM_instruction_fcmps\r
+ARM_instruction_vcmp.f64 = ARM_instruction_fcmpd\r
+ARM_instruction_vcmpe.f32 = ARM_instruction_fcmpes\r
+ARM_instruction_vcmpe.f64 = ARM_instruction_fcmped\r
+ARM_instruction_vcnt.8:\r
+       mov     edx,0xf3b00500\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vcvt.f16.f32:\r
+       mov     edx,0xf3b60600\r
+       jmp     SIMD_FLOAT_dd_qm\r
+ARM_instruction_vcvt.f32.f16:\r
+       mov     edx,0xf3b60700\r
+       jmp     SIMD_FLOAT_qd_dm\r
+ARM_instruction_vcvt.f32.f64 = ARM_instruction_fcvtsd\r
+ARM_instruction_vcvt.f32.s16 = ARM_instruction_fshtos\r
+ARM_instruction_vcvt.f32.s32:\r
+       mov     edx,0xf3bb0600\r
+       mov     ecx,0x0eb80ac0                          ;FSITOS\r
+       jmp     SIMD_FLOAT_vd_vm_imm\r
+ARM_instruction_vcvt.f32.u16 = ARM_instruction_fuhtos\r
+ARM_instruction_vcvt.f32.u32:\r
+       mov     edx,0xf3bb0680\r
+       mov     ecx,0x0eb80a40                          ;FUITOS\r
+       jmp     SIMD_FLOAT_vd_vm_imm\r
+ARM_instruction_vcvt.f64.f32 = ARM_instruction_fcvtds\r
+ARM_instruction_vcvt.f64.s16 = ARM_instruction_fshtod\r
+ARM_instruction_vcvt.f64.s32:\r
+       mov     edx,0x0eb80bc0                          ;FSITOD\r
+       mov     ecx,0x0eba0bc0                          ;FSLTOD\r
+       jmp     SIMD_FLOAT_dd_sm_CVT\r
+ARM_instruction_vcvt.f64.u16 = ARM_instruction_fuhtod\r
+ARM_instruction_vcvt.f64.u32:\r
+       mov     edx,0x0eb80b40                          ;FUITOD\r
+       mov     ecx,0x0ebb0bc0                          ;FULTOD\r
+       jmp     SIMD_FLOAT_dd_sm_CVT\r
+ARM_instruction_vcvt.s16.f32 = ARM_instruction_ftoshs\r
+ARM_instruction_vcvt.s16.f64 = ARM_instruction_ftoshd\r
+ARM_instruction_vcvt.s32.f32:\r
+       mov     edx,0xf3bb0700\r
+       mov     ecx,0x0ebd0ac0                          ;FTOSIZS\r
+       jmp     SIMD_FLOAT_vd_vm_imm\r
+ARM_instruction_vcvt.s32.f64:\r
+       mov     edx,0x0ebd0bc0                          ;FTOSIZD\r
+       mov     ecx,0x0ebe0bc0                          ;FTOSLD\r
+       jmp     SIMD_FLOAT_sd_dm_CVT\r
+ARM_instruction_vcvt.u16.f32 = ARM_instruction_ftouhs\r
+ARM_instruction_vcvt.u16.f64 = ARM_instruction_ftouhd\r
+ARM_instruction_vcvt.u32.f32:\r
+       mov     edx,0xf3bb0780\r
+       mov     ecx,0x0ebc0ac0                          ;FTOUIZS\r
+       jmp     SIMD_FLOAT_vd_vm_imm\r
+ARM_instruction_vcvt.u32.f64:\r
+       mov     edx,0x0ebc0bc0                          ;FTOUIZD\r
+       mov     ecx,0x0ebf0bc0                          ;FTOULD\r
+       jmp     SIMD_FLOAT_sd_dm_CVT\r
+ARM_instruction_vcvtr.s32.f32 = ARM_instruction_ftosis\r
+ARM_instruction_vcvtr.s32.f64 = ARM_instruction_ftosid\r
+ARM_instruction_vcvtr.u32.f32 = ARM_instruction_ftouis\r
+ARM_instruction_vcvtr.u32.f64 = ARM_instruction_ftouid\r
+ARM_instruction_vdiv.f32 = ARM_instruction_fdivs\r
+ARM_instruction_vdiv.f64 = ARM_instruction_fdivd\r
+ARM_instruction_vdup.16:\r
+       mov     edx,0xf3b20c00\r
+       mov     ecx,0x0e800b30\r
+       jmp     SIMD_INT_qd_dmx\r
+ARM_instruction_vdup.32:\r
+       mov     edx,0xf3b30c00\r
+       mov     ecx,0x0e800b10\r
+       jmp     SIMD_INT_qd_dmx\r
+ARM_instruction_vdup.8:\r
+       mov     edx,0xf3b10c00\r
+       mov     ecx,0x0ec00b10\r
+       jmp     SIMD_INT_qd_dmx\r
+ARM_instruction_veor:\r
+       mov     edx,0xf3000110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vext.16:\r
+       mov     edx,0xf2b00200\r
+       jmp     SIMD_INT_vd_vn_vm_imm\r
+ARM_instruction_vext.32:\r
+       mov     edx,0xf2b00400\r
+       jmp     SIMD_INT_vd_vn_vm_imm\r
+ARM_instruction_vext.64:\r
+       mov     edx,0xf2b00800\r
+       jmp     SIMD_INT_vd_vn_vm_imm\r
+ARM_instruction_vext.8:\r
+       mov     edx,0xf2b00100\r
+       jmp     SIMD_INT_vd_vn_vm_imm\r
+ARM_instruction_vhadd.s16:\r
+       mov     edx,0xf2100000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhadd.s32:\r
+       mov     edx,0xf2200000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhadd.s8:\r
+       mov     edx,0xf2000000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhadd.u16:\r
+       mov     edx,0xf3100000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhadd.u32:\r
+       mov     edx,0xf3200000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhadd.u8:\r
+       mov     edx,0xf3000000\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.s16:\r
+       mov     edx,0xf2100200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.s32:\r
+       mov     edx,0xf2200200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.s8:\r
+       mov     edx,0xf2000200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.u16:\r
+       mov     edx,0xf3100200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.u32:\r
+       mov     edx,0xf3200200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vhsub.u8:\r
+       mov     edx,0xf3000200\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vld1.16:\r
+       mov     edx,0xf4200040\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vld1.32:\r
+       mov     edx,0xf4200080\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vld1.64:\r
+       mov     edx,0xf42000c0\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vld1.8:\r
+       mov     edx,0xf4200000\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vld2.16:\r
+       mov     edx,0xf4200040\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vld2.32:\r
+       mov     edx,0xf4200080\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vld2.8:\r
+       mov     edx,0xf4200000\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vld3.16:\r
+       mov     edx,0xf4200040\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vld3.32:\r
+       mov     edx,0xf4200080\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vld3.8:\r
+       mov     edx,0xf4200000\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vld4.16:\r
+       mov     edx,0xf4200040\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vld4.32:\r
+       mov     edx,0xf4200080\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vld4.8:\r
+       mov     edx,0xf4200000\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vldm.32 = ARM_instruction_fldmias\r
+ARM_instruction_vldm.64 = ARM_instruction_fldmiad\r
+ARM_instruction_vldmdb.32 = ARM_instruction_fldmdbs\r
+ARM_instruction_vldmdb.64 = ARM_instruction_fldmdbd\r
+ARM_instruction_vldmfd.32 = ARM_instruction_fldmfds\r
+ARM_instruction_vldmfd.64 = ARM_instruction_fldmfdd\r
+ARM_instruction_vldmea.32 = ARM_instruction_fldmeas\r
+ARM_instruction_vldmea.64 = ARM_instruction_fldmead\r
+ARM_instruction_vldmia.32 = ARM_instruction_fldmias\r
+ARM_instruction_vldmia.64 = ARM_instruction_fldmiad\r
+ARM_instruction_vldmea:\r
+ARM_instruction_vldmdb:\r
+       mov     edx,0xd100a00\r
+       jmp     SIMD_INT_rn_list\r
+ARM_instruction_vldm:\r
+ARM_instruction_vldmfd:\r
+ARM_instruction_vldmia:\r
+       mov     edx,0xc900a00\r
+       jmp     SIMD_INT_rn_list\r
+ARM_instruction_vldr.32 = ARM_instruction_flds\r
+ARM_instruction_vldr.64 = ARM_instruction_fldd\r
+ARM_instruction_vldr:\r
+       mov     edx,0x0d100a00\r
+       jmp     SIMD_INT_vd_rn_offset\r
+ARM_instruction_vmax.f32:\r
+       mov     edx,0xf2000f00\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vmax.s16:\r
+       mov     edx,0xf2100600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmax.s32:\r
+       mov     edx,0xf2200600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmax.s8:\r
+       mov     edx,0xf2000600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmax.u16:\r
+       mov     edx,0xf3100600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmax.u32:\r
+       mov     edx,0xf3200600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmax.u8:\r
+       mov     edx,0xf3000600\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.f32:\r
+       mov     edx,0xf2200f00\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vmin.s16:\r
+       mov     edx,0xf2100610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.s32:\r
+       mov     edx,0xf2200610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.s8:\r
+       mov     edx,0xf2000610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.u16:\r
+       mov     edx,0xf3100610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.u32:\r
+       mov     edx,0xf3200610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmin.u8:\r
+       mov     edx,0xf3000610\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmla.f32:\r
+       mov     edx,0xf2000d10\r
+       mov     ecx,0x0e000a00\r
+       jmp     SIMD_FLOAT_vd_vn_vmx_f32\r
+ARM_instruction_vmla.f64 = ARM_instruction_fmacd\r
+ARM_instruction_vmla.i16:\r
+       mov     edx,0xf2100900\r
+       jmp     SIMD_INT_vd_vn_vmx\r
+ARM_instruction_vmla.i32:\r
+       mov     edx,0xf2200900\r
+       jmp     SIMD_INT_vd_vn_vmx\r
+ARM_instruction_vmla.i8:\r
+       mov     edx,0xf2000900\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vmla.s16 = ARM_instruction_vmla.i16\r
+ARM_instruction_vmla.s32 = ARM_instruction_vmla.i32\r
+ARM_instruction_vmla.s8 = ARM_instruction_vmla.i8\r
+ARM_instruction_vmla.u16 = ARM_instruction_vmla.i16\r
+ARM_instruction_vmla.u32 = ARM_instruction_vmla.i32\r
+ARM_instruction_vmla.u8 = ARM_instruction_vmla.i8\r
+ARM_instruction_vmlal.s16:\r
+       mov     edx,0xf2900800\r
+       mov     ecx,0xf2900240\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlal.s32:\r
+       mov     edx,0xf2a00800\r
+       mov     ecx,0xf2a00240\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlal.s8:\r
+       mov     edx,0xf2800800\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmlal.u16:\r
+       mov     edx,0xf3900800\r
+       mov     ecx,0xf3900240\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlal.u32:\r
+       mov     edx,0xf3a00800\r
+       mov     ecx,0xf3a00240\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlal.u8:\r
+       mov     edx,0xf3800800\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmls.f32:\r
+       mov     edx,0xf2200d10\r
+       mov     ecx,0x0e000a40\r
+       jmp     SIMD_FLOAT_vd_vn_vmx_f32\r
+ARM_instruction_vmls.f64 = ARM_instruction_fnmacd\r
+ARM_instruction_vmls.i16:\r
+       mov     edx,0xf3100900\r
+       jmp     SIMD_INT_vd_vn_vmx\r
+ARM_instruction_vmls.i32:\r
+       mov     edx,0xf3200900\r
+       jmp     SIMD_INT_vd_vn_vmx\r
+ARM_instruction_vmls.i8:\r
+       mov     edx,0xf3000900\r
+       jmp     SIMD_INT_vd_vn_vm\r
+ARM_instruction_vmls.s16 = ARM_instruction_vmls.i16\r
+ARM_instruction_vmls.s32 = ARM_instruction_vmls.i32\r
+ARM_instruction_vmls.s8 = ARM_instruction_vmls.i8\r
+ARM_instruction_vmls.u16 = ARM_instruction_vmls.i16\r
+ARM_instruction_vmls.u32 = ARM_instruction_vmls.i32\r
+ARM_instruction_vmls.u8 = ARM_instruction_vmls.i8\r
+ARM_instruction_vmlsl.s16:\r
+       mov     edx,0xf2900a00\r
+       mov     ecx,0xf2900640\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlsl.s32:\r
+       mov     edx,0xf2a00a00\r
+       mov     ecx,0xf2a00640\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlsl.s8:\r
+       mov     edx,0xf2800a00\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmlsl.u16:\r
+       mov     edx,0xf3900a00\r
+       mov     ecx,0xf3900640\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlsl.u32:\r
+       mov     edx,0xf3a00a00\r
+       mov     ecx,0xf3a00640\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmlsl.u8:\r
+       mov     edx,0xf3800a00\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmov.16:\r
+       mov     edx,0x0e000b30\r
+       jmp     SIMD_INT_ddx_rn\r
+ARM_instruction_vmov.32:\r
+       mov     edx,0x0e000b10\r
+       jmp     SIMD_INT_rdd_rdn\r
+ARM_instruction_vmov.8:\r
+       mov     edx,0x0e400b10\r
+       jmp     SIMD_INT_ddx_rn\r
+ARM_instruction_vmov.f32:\r
+       mov     edx,0x0eb00a00                          ;FCONSTS\r
+       mov     ecx,0xf2800f10\r
+       jmp     SIMD_FLOAT_sm_imm\r
+ARM_instruction_vmov.f64:\r
+       mov     edx,0x0eb00b00                          ;FCONSTD\r
+       jmp     SIMD_FLOAT_dm_imm\r
+ARM_instruction_vmov.i16:\r
+       mov     edx,0xf2800810\r
+       jmp     SIMD_INT_vd_imm_i16\r
+ARM_instruction_vmov.i32:\r
+       mov     edx,0xf2800010\r
+       jmp     SIMD_INT_vd_imm_i32\r
+ARM_instruction_vmov.i64:\r
+       mov     edx,0xf2800e30\r
+       jmp     SIMD_INT_vd_imm_i8\r
+ARM_instruction_vmov.i8:\r
+       mov     edx,0xf2800e10\r
+       jmp     SIMD_INT_vd_imm_i8\r
+ARM_instruction_vmov.s16:\r
+       mov     edx,0x0e100b30\r
+       jmp     SIMD_INT_rd_dnx\r
+ARM_instruction_vmov.s8:\r
+       mov     edx,0x0e500b10\r
+       jmp     SIMD_INT_rd_dnx\r
+ARM_instruction_vmov.u16:\r
+       mov     edx,0x0e900b30\r
+       jmp     SIMD_INT_rd_dnx\r
+ARM_instruction_vmov.u8:\r
+       mov     edx,0x0ed00b10\r
+       jmp     SIMD_INT_rd_dnx\r
+ARM_instruction_vmov:\r
+       jmp     SIMD_INT_MOV\r
+ARM_instruction_vmovl.s16:\r
+       mov     edx,0xf2900a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovl.s32:\r
+       mov     edx,0xf2a00a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovl.s8:\r
+       mov     edx,0xf2880a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovl.u16:\r
+       mov     edx,0xf3900a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovl.u32:\r
+       mov     edx,0xf3a00a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovl.u8:\r
+       mov     edx,0xf3880a10\r
+       jmp     SIMD_INT_qd_dm\r
+ARM_instruction_vmovn.i16:\r
+       mov     edx,0xf3b60200\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vmovn.i32:\r
+       mov     edx,0xf3ba0200\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vmovn.i8:\r
+       mov     edx,0xf3b20200\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vmrs = ARM_instruction_fmrx\r
+ARM_instruction_vmsr = ARM_instruction_fmxr\r
+ARM_instruction_vmul.f32:\r
+       mov     edx,0xf3000d10\r
+       mov     ecx,0x0e200a00\r
+       jmp     SIMD_FLOAT_vd_vn_vmx_alt_f32\r
+ARM_instruction_vmul.f64 = ARM_instruction_fmuld\r
+ARM_instruction_vmul.i16:\r
+       mov     edx,0xf2100910\r
+       mov     ecx,0xf2900840\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vmul.i32:\r
+       mov     edx,0xf2200910\r
+       mov     ecx,0xf2a00840\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vmul.i8:\r
+       mov     edx,0xf2000910\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmul.p8:\r
+       mov     edx,0xf3000910\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmul.s16:\r
+       mov     edx,0xf2100910\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmul.s32:\r
+       mov     edx,0xf2200910\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vmul.s8 = ARM_instruction_vmul.i8\r
+ARM_instruction_vmul.u16 = ARM_instruction_vmul.s16\r
+ARM_instruction_vmul.u32 = ARM_instruction_vmul.s32\r
+ARM_instruction_vmul.u8 = ARM_instruction_vmul.i8\r
+ARM_instruction_vmull.p8:\r
+       mov     edx,0xf2800e00\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmull.s16:\r
+       mov     edx,0xf2900c00\r
+       mov     ecx,0xf2900a40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmull.s32:\r
+       mov     edx,0xf2a00c00\r
+       mov     ecx,0xf2a00a40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmull.s8:\r
+       mov     edx,0xf2800c00\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmull.u16:\r
+       mov     edx,0xf3900c00\r
+       mov     ecx,0xf3900a40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmull.u32:\r
+       mov     edx,0xf3a00c00\r
+       mov     ecx,0xf3a00a40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vmull.u8:\r
+       mov     edx,0xf3800c00\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vmvn.i16:\r
+       mov     edx,0xf2800830\r
+       jmp     SIMD_INT_vd_imm_i16\r
+ARM_instruction_vmvn.i32:\r
+       mov     edx,0xf2800030\r
+       jmp     SIMD_INT_vd_imm_i32\r
+ARM_instruction_vmvn:\r
+       mov     edx,0xf3b00580\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vneg.f32:\r
+       mov     edx,0xf3b90780\r
+       mov     ecx,0x0eb10a40\r
+       jmp     SIMD_FLOAT_vd_vm_f32\r
+ARM_instruction_vneg.f64 = ARM_instruction_fnegd\r
+ARM_instruction_vneg.s16:\r
+       mov     edx,0xf3b50380\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vneg.s32:\r
+       mov     edx,0xf3b90380\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vneg.s8:\r
+       mov     edx,0xf3b10380\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vnmla.f32 = ARM_instruction_fnmscs\r
+ARM_instruction_vnmla.f64 = ARM_instruction_fnmscd\r
+ARM_instruction_vnmls.f32 = ARM_instruction_fmscs\r
+ARM_instruction_vnmls.f64 = ARM_instruction_fmscd\r
+ARM_instruction_vnmul.f32 = ARM_instruction_fnmuls\r
+ARM_instruction_vnmul.f64 = ARM_instruction_fnmuld\r
+ARM_instruction_vorn.i16:\r
+       mov     edx,0xf2800911\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vorn.i32:\r
+       mov     edx,0xf2800111\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vorn:\r
+       mov     edx,0xf2300110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vorr.i16:\r
+       mov     edx,0xf2800910\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vorr.i32:\r
+       mov     edx,0xf2800110\r
+       jmp     SIMD_INT_vd_imm\r
+ARM_instruction_vorr:\r
+       mov     edx,0xf2200110\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vpadal.s16:\r
+       mov     edx,0xf3b40600\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadal.s32:\r
+       mov     edx,0xf3b80600\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadal.s8:\r
+       mov     edx,0xf3b00600\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadal.u16:\r
+       mov     edx,0xf3b40680\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadal.u32:\r
+       mov     edx,0xf3b80680\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadal.u8:\r
+       mov     edx,0xf3b00680\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpadd.f32:\r
+       mov     edx,0xf3000d00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_alt\r
+ARM_instruction_vpadd.i16:\r
+       mov     edx,0xf2100b10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpadd.i32:\r
+       mov     edx,0xf2200b10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpadd.i8:\r
+       mov     edx,0xf2000b10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpaddl.s16:\r
+       mov     edx,0xf3b40200\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpaddl.s32:\r
+       mov     edx,0xf3b80200\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpaddl.s8:\r
+       mov     edx,0xf3b00200\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpaddl.u16:\r
+       mov     edx,0xf3b40280\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpaddl.u32:\r
+       mov     edx,0xf3b80280\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpaddl.u8:\r
+       mov     edx,0xf3b00280\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vpmax.f32:\r
+       mov     edx,0xf3000f00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.s16:\r
+       mov     edx,0xf2100a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.s32:\r
+       mov     edx,0xf2200a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.s8:\r
+       mov     edx,0xf2000a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.u16:\r
+       mov     edx,0xf3100a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.u32:\r
+       mov     edx,0xf3200a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmax.u8:\r
+       mov     edx,0xf3000a00\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.f32:\r
+       mov     edx,0xf3200f00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.s16:\r
+       mov     edx,0xf2100a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.s32:\r
+       mov     edx,0xf2200a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.s8:\r
+       mov     edx,0xf2000a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.u16:\r
+       mov     edx,0xf3100a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.u32:\r
+       mov     edx,0xf3200a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpmin.u8:\r
+       mov     edx,0xf3000a10\r
+       jmp     SIMD_INT_dd_dn_dm_alt\r
+ARM_instruction_vpop:\r
+       mov     edx,0x0c900a00\r
+       jmp     SIMD_INT_list\r
+ARM_instruction_vpush:\r
+       mov     edx,0x0d000a00\r
+       jmp     SIMD_INT_list\r
+ARM_instruction_vpop.32:\r
+       mov     edx,0x0c900a00\r
+       jmp     SIMD_INT_list.32\r
+ARM_instruction_vpush.32:\r
+       mov     edx,0x0d000a00\r
+       jmp     SIMD_INT_list.32\r
+ARM_instruction_vpop.64:\r
+       mov     edx,0x0c900b00\r
+       jmp     SIMD_INT_list.64\r
+ARM_instruction_vpush.64:\r
+       mov     edx,0x0d000b00\r
+       jmp     SIMD_INT_list.64\r
+ARM_instruction_vqabs.s16:\r
+       mov     edx,0xf3b40700\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqabs.s32:\r
+       mov     edx,0xf3b80700\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqabs.s8:\r
+       mov     edx,0xf3b00700\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqadd.s16:\r
+       mov     edx,0xf2100010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.s32:\r
+       mov     edx,0xf2200010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.s64:\r
+       mov     edx,0xf2300010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.s8:\r
+       mov     edx,0xf2000010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.u16:\r
+       mov     edx,0xf3100010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.u32:\r
+       mov     edx,0xf3200010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.u64:\r
+       mov     edx,0xf3300010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqadd.u8:\r
+       mov     edx,0xf3000010\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqdmlal.s16:\r
+       mov     edx,0xf2900900\r
+       mov     ecx,0xf2900340\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqdmlal.s32:\r
+       mov     edx,0xf2a00900\r
+       mov     ecx,0xf2a00340\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqdmlsl.s16:\r
+       mov     edx,0xf2900b00\r
+       mov     ecx,0xf2900740\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqdmlsl.s32:\r
+       mov     edx,0xf2a00b00\r
+       mov     ecx,0xf2a00740\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqdmulh.s16:\r
+       mov     edx,0xf2100b00\r
+       mov     ecx,0xf2900c40\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vqdmulh.s32:\r
+       mov     edx,0xf2200b00\r
+       mov     ecx,0xf2a00c40\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vqdmull.s16:\r
+       mov     edx,0xf2900d00\r
+       mov     ecx,0xf2900b40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqdmull.s32:\r
+       mov     edx,0xf2a00d00\r
+       mov     ecx,0xf2a00b40\r
+       jmp     SIMD_INT_vd_vn_vmx_long\r
+ARM_instruction_vqmovn.s16:\r
+       mov     edx,0xf3b20280\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovn.s32:\r
+       mov     edx,0xf3b60280\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovn.s64:\r
+       mov     edx,0xf3ba0280\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovn.u16:\r
+       mov     edx,0xf3b202c0\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovn.u32:\r
+       mov     edx,0xf3b602c0\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovn.u64:\r
+       mov     edx,0xf3ba02c0\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovun.s16:\r
+       mov     edx,0xf3b20240\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovun.s32:\r
+       mov     edx,0xf3b60240\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqmovun.s64:\r
+       mov     edx,0xf3ba0240\r
+       jmp     SIMD_INT_dd_qm\r
+ARM_instruction_vqneg.s16:\r
+       mov     edx,0xf3b40780\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqneg.s32:\r
+       mov     edx,0xf3b80780\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqneg.s8:\r
+       mov     edx,0xf3b00780\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vqrdmulh.s16:\r
+       mov     edx,0xf3100b00\r
+       mov     ecx,0xf2900d40\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vqrdmulh.s32:\r
+       mov     edx,0xf3200b00\r
+       mov     ecx,0xf2a00d40\r
+       jmp     SIMD_INT_vd_vn_vmx_alt\r
+ARM_instruction_vqrshl.s16:\r
+       mov     edx,0xf2100510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.s32:\r
+       mov     edx,0xf2200510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.s64:\r
+       mov     edx,0xf2300510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.s8:\r
+       mov     edx,0xf2000510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.u16:\r
+       mov     edx,0xf3100510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.u32:\r
+       mov     edx,0xf3200510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.u64:\r
+       mov     edx,0xf3300510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshl.u8:\r
+       mov     edx,0xf3000510\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqrshrn.s16:\r
+       mov     edx,0xf2880950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrn.s32:\r
+       mov     edx,0xf2900950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrn.s64:\r
+       mov     edx,0xf2a00950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrn.u16:\r
+       mov     edx,0xf3880950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrn.u32:\r
+       mov     edx,0xf3900950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrn.u64:\r
+       mov     edx,0xf3a00950\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrun.s16:\r
+       mov     edx,0xf3880850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrun.s32:\r
+       mov     edx,0xf3900850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqrshrun.s64:\r
+       mov     edx,0xf3a00850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshl.s16:\r
+       mov     edx,0xf2100410\r
+       mov     ecx,0xf2900710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.s32:\r
+       mov     edx,0xf2200410\r
+       mov     ecx,0xf2a00710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.s64:\r
+       mov     edx,0xf2300410\r
+       mov     ecx,0xf2800790\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.s8:\r
+       mov     edx,0xf2000410\r
+       mov     ecx,0xf2880710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.u16:\r
+       mov     edx,0xf3100410\r
+       mov     ecx,0xf3900710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.u32:\r
+       mov     edx,0xf3200410\r
+       mov     ecx,0xf3a00710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.u64:\r
+       mov     edx,0xf3300410\r
+       mov     ecx,0xf3800790\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshl.u8:\r
+       mov     edx,0xf3000410\r
+       mov     ecx,0xf3880710\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt\r
+ARM_instruction_vqshlu.s16:\r
+       mov     edx,0xf3900610\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vqshlu.s32:\r
+       mov     edx,0xf3a00610\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vqshlu.s64:\r
+       mov     edx,0xf3800690\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vqshlu.s8:\r
+       mov     edx,0xf3880610\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vqshrn.s16:\r
+       mov     edx,0xf2880910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrn.s32:\r
+       mov     edx,0xf2900910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrn.s64:\r
+       mov     edx,0xf2a00910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrn.u16:\r
+       mov     edx,0xf3880910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrn.u32:\r
+       mov     edx,0xf3900910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrn.u64:\r
+       mov     edx,0xf3a00910\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrun.s16:\r
+       mov     edx,0xf3880810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrun.s32:\r
+       mov     edx,0xf3900810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqshrun.s64:\r
+       mov     edx,0xf3a00810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vqsub.s16:\r
+       mov     edx,0xf2100210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.s32:\r
+       mov     edx,0xf2200210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.s64:\r
+       mov     edx,0xf2300210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.s8:\r
+       mov     edx,0xf2000210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.u16:\r
+       mov     edx,0xf3100210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.u32:\r
+       mov     edx,0xf3200210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.u64:\r
+       mov     edx,0xf3300210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vqsub.u8:\r
+       mov     edx,0xf3000210\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vraddhn.i16:\r
+       mov     edx,0xf3800400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vraddhn.i32:\r
+       mov     edx,0xf3900400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vraddhn.i64:\r
+       mov     edx,0xf3a00400\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vrecpe.f32:\r
+       mov     edx,0xf3bb0500\r
+       jmp     SIMD_FLOAT_vd_vm\r
+ARM_instruction_vrecpe.u32:\r
+       mov     edx,0xf3bb0400\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrecps.f32:\r
+       mov     edx,0xf2000f10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vrev16.8:\r
+       mov     edx,0xf3b00100\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrev32.16:\r
+       mov     edx,0xf3b40080\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrev32.8:\r
+       mov     edx,0xf3b00080\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrev64.16:\r
+       mov     edx,0xf3b40000\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrev64.32:\r
+       mov     edx,0xf3b80000\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrev64.8:\r
+       mov     edx,0xf3b00000\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrhadd.s16:\r
+       mov     edx,0xf2100100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrhadd.s32:\r
+       mov     edx,0xf2200100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrhadd.s8:\r
+       mov     edx,0xf2000100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrhadd.u16:\r
+       mov     edx,0xf3100100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrhadd.u32:\r
+       mov     edx,0xf3200100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrhadd.u8:\r
+       mov     edx,0xf3000100\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.s16:\r
+       mov     edx,0xf2100500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.s32:\r
+       mov     edx,0xf2200500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.s64:\r
+       mov     edx,0xf2300500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.s8:\r
+       mov     edx,0xf2000500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.u16:\r
+       mov     edx,0xf3100500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.u32:\r
+       mov     edx,0xf3200500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.u64:\r
+       mov     edx,0xf3300500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshl.u8:\r
+       mov     edx,0xf3000500\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vrshr.s16:\r
+       mov     edx,0xf2900210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.s32:\r
+       mov     edx,0xf2a00210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.s64:\r
+       mov     edx,0xf2800290\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.s8:\r
+       mov     edx,0xf2880210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.u16:\r
+       mov     edx,0xf3900210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.u32:\r
+       mov     edx,0xf3a00210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.u64:\r
+       mov     edx,0xf3800290\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshr.u8:\r
+       mov     edx,0xf3880210\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrshrn.i16:\r
+       mov     edx,0xf2880850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vrshrn.i32:\r
+       mov     edx,0xf2900850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vrshrn.i64:\r
+       mov     edx,0xf2a00850\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vrsqrte.f32:\r
+       mov     edx,0xf3bb0580\r
+       jmp     SIMD_FLOAT_vd_vm\r
+ARM_instruction_vrsqrte.u32:\r
+       mov     edx,0xf3bb0480\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vrsqrts.f32:\r
+       mov     edx,0xf2200f10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt\r
+ARM_instruction_vrsra.s16:\r
+       mov     edx,0xf2900310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.s32:\r
+       mov     edx,0xf2a00310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.s64:\r
+       mov     edx,0xf2800390\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.s8:\r
+       mov     edx,0xf2880310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.u16:\r
+       mov     edx,0xf3900310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.u32:\r
+       mov     edx,0xf3a00310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.u64:\r
+       mov     edx,0xf3800390\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsra.u8:\r
+       mov     edx,0xf3880310\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vrsubhn.i16:\r
+       mov     edx,0xf3800600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vrsubhn.i32:\r
+       mov     edx,0xf3900600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vrsubhn.i64:\r
+       mov     edx,0xf3a00600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vshl.i16:\r
+       mov     edx,0xf2900510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vshl.i32:\r
+       mov     edx,0xf2a00510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vshl.i64:\r
+       mov     edx,0xf2800590\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vshl.i8:\r
+       mov     edx,0xf2880510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vshl.s16:\r
+       mov     edx,0xf2100400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.s32:\r
+       mov     edx,0xf2200400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.s64:\r
+       mov     edx,0xf2300400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.s8:\r
+       mov     edx,0xf2000400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.u16:\r
+       mov     edx,0xf3100400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.u32:\r
+       mov     edx,0xf3200400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.u64:\r
+       mov     edx,0xf3300400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshl.u8:\r
+       mov     edx,0xf3000400\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vshll.i16:\r
+       mov     edx,0xf3b60300\r
+       jmp     SIMD_INT_qd_dm_imm_I\r
+ARM_instruction_vshll.i32:\r
+       mov     edx,0xf3ba0300\r
+       jmp     SIMD_INT_qd_dm_imm_I\r
+ARM_instruction_vshll.i8:\r
+       mov     edx,0xf3b20300\r
+       jmp     SIMD_INT_qd_dm_imm_I\r
+ARM_instruction_vshll.s16:\r
+       mov     edx,0xf2900a10\r
+       mov     ecx,0xf3b60300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshll.s32:\r
+       mov     edx,0xf2a00a10\r
+       mov     ecx,0xf3ba0300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshll.s8:\r
+       mov     edx,0xf2880a10\r
+       mov     ecx,0xf3b20300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshll.u16:\r
+       mov     edx,0xf3900a10\r
+       mov     ecx,0xf3b60300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshll.u32:\r
+       mov     edx,0xf3a00a10\r
+       mov     ecx,0xf3ba0300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshll.u8:\r
+       mov     edx,0xf3880a10\r
+       mov     ecx,0xf3b20300\r
+       jmp     SIMD_INT_qd_dm_imm\r
+ARM_instruction_vshr.s16:\r
+       mov     edx,0xf2900010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.s32:\r
+       mov     edx,0xf2a00010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.s64:\r
+       mov     edx,0xf2800090\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.s8:\r
+       mov     edx,0xf2880010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.u16:\r
+       mov     edx,0xf3900010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.u32:\r
+       mov     edx,0xf3a00010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.u64:\r
+       mov     edx,0xf3800090\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshr.u8:\r
+       mov     edx,0xf3880010\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vshrn.i16:\r
+       mov     edx,0xf2880810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vshrn.i32:\r
+       mov     edx,0xf2900810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vshrn.i64:\r
+       mov     edx,0xf2a00810\r
+       jmp     SIMD_INT_dd_qm_imm\r
+ARM_instruction_vsli.16:\r
+       mov     edx,0xf3900510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vsli.32:\r
+       mov     edx,0xf3a00510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vsli.64:\r
+       mov     edx,0xf3800590\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vsli.8:\r
+       mov     edx,0xf3880510\r
+       jmp     SIMD_INT_vd_vm_imm_alt\r
+ARM_instruction_vsqrt.f32 = ARM_instruction_fsqrts\r
+ARM_instruction_vsqrt.f64 = ARM_instruction_fsqrtd\r
+ARM_instruction_vsra.s16:\r
+       mov     edx,0xf2900110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.s32:\r
+       mov     edx,0xf2a00110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.s64:\r
+       mov     edx,0xf2800190\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.s8:\r
+       mov     edx,0xf2880110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.u16:\r
+       mov     edx,0xf3900110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.u32:\r
+       mov     edx,0xf3a00110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.u64:\r
+       mov     edx,0xf3800190\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsra.u8:\r
+       mov     edx,0xf3880110\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsri.16:\r
+       mov     edx,0xf3900410\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsri.32:\r
+       mov     edx,0xf3a00410\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsri.64:\r
+       mov     edx,0xf3800490\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vsri.8:\r
+       mov     edx,0xf3880410\r
+       jmp     SIMD_INT_vd_vm_imm_alt_neg\r
+ARM_instruction_vst1.16:\r
+       mov     edx,0xf4000040\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vst1.32:\r
+       mov     edx,0xf4000080\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vst1.64:\r
+       mov     edx,0xf40000c0\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vst1.8:\r
+       mov     edx,0xf4000000\r
+       jmp     SIMD_INT_list_rn_rm_1\r
+ARM_instruction_vst2.16:\r
+       mov     edx,0xf4000040\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vst2.32:\r
+       mov     edx,0xf4000080\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vst2.8:\r
+       mov     edx,0xf4000000\r
+       jmp     SIMD_INT_list_rn_rm_2\r
+ARM_instruction_vst3.16:\r
+       mov     edx,0xf4000040\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vst3.32:\r
+       mov     edx,0xf4000080\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vst3.8:\r
+       mov     edx,0xf4000000\r
+       jmp     SIMD_INT_list_rn_rm_3\r
+ARM_instruction_vst4.16:\r
+       mov     edx,0xf4000040\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vst4.32:\r
+       mov     edx,0xf4000080\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vst4.8:\r
+       mov     edx,0xf4000000\r
+       jmp     SIMD_INT_list_rn_rm_4\r
+ARM_instruction_vstm.32 = ARM_instruction_fstmias\r
+ARM_instruction_vstm.64 = ARM_instruction_fstmiad\r
+ARM_instruction_vstmdb.32 = ARM_instruction_fstmdbs\r
+ARM_instruction_vstmdb.64 = ARM_instruction_fstmdbd\r
+ARM_instruction_vstmfd.32 = ARM_instruction_fstmfds\r
+ARM_instruction_vstmfd.64 = ARM_instruction_fstmfdd\r
+ARM_instruction_vstmea.32 = ARM_instruction_fstmeas\r
+ARM_instruction_vstmea.64 = ARM_instruction_fstmead\r
+ARM_instruction_vstmia.32 = ARM_instruction_fstmias\r
+ARM_instruction_vstmia.64 = ARM_instruction_fstmiad\r
+ARM_instruction_vstmfd:\r
+ARM_instruction_vstmdb:\r
+       mov     edx,0xd000a00\r
+       jmp     SIMD_INT_rn_list\r
+ARM_instruction_vstm:\r
+ARM_instruction_vstmea:\r
+ARM_instruction_vstmia:\r
+       mov     edx,0xc800a00\r
+       jmp     SIMD_INT_rn_list\r
+ARM_instruction_vstr.32 = ARM_instruction_fsts\r
+ARM_instruction_vstr.64 = ARM_instruction_fstd\r
+ARM_instruction_vstr:\r
+       mov     edx,0x0d000a00\r
+       jmp     SIMD_INT_vd_rn_offset\r
+ARM_instruction_vsub.f32:\r
+       mov     edx,0xf2200d00\r
+       mov     ecx,0x0e300a40\r
+       jmp     SIMD_FLOAT_vd_vn_vm_f32\r
+ARM_instruction_vsub.f64 = ARM_instruction_fsubd\r
+ARM_instruction_vsub.i16:\r
+       mov     edx,0xf3100800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vsub.i32:\r
+       mov     edx,0xf3200800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vsub.i64:\r
+       mov     edx,0xf3300800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vsub.i8:\r
+       mov     edx,0xf3000800\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vsubhn.i16:\r
+       mov     edx,0xf2800600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vsubhn.i32:\r
+       mov     edx,0xf2900600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vsubhn.i64:\r
+       mov     edx,0xf2a00600\r
+       jmp     SIMD_INT_vd_vn_vm_narrow\r
+ARM_instruction_vsubl.s16:\r
+       mov     edx,0xf2900200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubl.s32:\r
+       mov     edx,0xf2a00200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubl.s8:\r
+       mov     edx,0xf2800200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubl.u16:\r
+       mov     edx,0xf3900200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubl.u32:\r
+       mov     edx,0xf3a00200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubl.u8:\r
+       mov     edx,0xf3800200\r
+       jmp     SIMD_INT_vd_vn_vm_long\r
+ARM_instruction_vsubw.s16:\r
+       mov     edx,0xf2900300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vsubw.s32:\r
+       mov     edx,0xf2a00300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vsubw.s8:\r
+       mov     edx,0xf2800300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vsubw.u16:\r
+       mov     edx,0xf3900300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vsubw.u32:\r
+       mov     edx,0xf3a00300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vsubw.u8:\r
+       mov     edx,0xf3800300\r
+       jmp     SIMD_INT_vd_vn_vm_wide\r
+ARM_instruction_vswp:\r
+       mov     edx,0xf3b20000\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vtbl.8:\r
+       mov     edx,0xf3b00800\r
+       jmp     SIMD_dn_list_dm\r
+ARM_instruction_vtbx.8:\r
+       mov     edx,0xf3b00840\r
+       jmp     SIMD_dn_list_dm\r
+ARM_instruction_vtrn.16:\r
+       mov     edx,0xf3b60080\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vtrn.32:\r
+       mov     edx,0xf3ba0080\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vtrn.8:\r
+       mov     edx,0xf3b20080\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vtst.16:\r
+       mov     edx,0xf2100810\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vtst.32:\r
+       mov     edx,0xf2200810\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vtst.8:\r
+       mov     edx,0xf2000810\r
+       jmp     SIMD_INT_vd_vn_vm_alt\r
+ARM_instruction_vuzp.16:\r
+       mov     edx,0xf3b60100\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vuzp.32:\r
+       mov     edx,0xf3ba0100\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vuzp.8:\r
+       mov     edx,0xf3b20100\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vzip.16:\r
+       mov     edx,0xf3b60180\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vzip.32:\r
+       mov     edx,0xf3ba0180\r
+       jmp     SIMD_INT_vd_vm\r
+ARM_instruction_vzip.8:\r
+       mov     edx,0xf3b20180\r
+       jmp     SIMD_INT_vd_vm\r
+\r
+;VFPv4 and SIMDv2\r
+\r
+ARM_instruction_vfma.f32:\r
+       mov     edx,0xf2000c10\r
+       mov     ecx,0x0ea00a00\r
+       jmp     SIMD_FLOAT_vd_vn_vm\r
+ARM_instruction_vfms.f32:\r
+       mov     edx,0xf2200c10\r
+       mov     ecx,0x0ea00a40\r
+       jmp     SIMD_FLOAT_vd_vn_vm\r
+ARM_instruction_vfma.f64:\r
+       mov     ecx,0x0ea00b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm\r
+ARM_instruction_vfms.f64:\r
+       mov     ecx,0x0ea00b40\r
+       jmp     SIMD_FLOAT_dd_dn_dm\r
+ARM_instruction_vfnma.f32:\r
+       mov     ecx,0x0e900a40\r
+       jmp     SIMD_FLOAT_sd_sn_sm\r
+ARM_instruction_vfnms.f32:\r
+       mov     ecx,0x0e900a00\r
+       jmp     SIMD_FLOAT_sd_sn_sm\r
+ARM_instruction_vfnma.f64:\r
+       mov     ecx,0x0e900b40\r
+       jmp     SIMD_FLOAT_dd_dn_dm\r
+ARM_instruction_vfnms.f64:\r
+       mov     ecx,0x0e900b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm\r
+\r
+;v7VE\r
+\r
+ARM_instruction_eret:\r
+       INST_ARM64\r
+       dd      0xd69f03e0\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0160006e\r
+       mov     ecx,0xf3de8f00\r
+       jmp     ARM_eret\r
+ARM_instruction_hvc:\r
+       INST_ARM64\r
+       dd      0xd4000002\r
+       dd      ARM64_debug\r
+       mov     edx,0x01400070\r
+       mov     ecx,0xf7e08000\r
+       jmp     ARM_immediate16_ve\r
+\r
+;v8\r
+\r
+ARM_instruction_hlt:\r
+       INST_ARM64\r
+       dd      0xd4400000\r
+       dd      ARM64_debug\r
+       mov     edx,0x01000070\r
+       jmp     ARM_immediate16_v8\r
+ARM_instruction_lda:\r
+       mov     [operand_size],4\r
+       mov     edx,0x01900c9f\r
+       mov     ecx,0xe8d00faf\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldab:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01d00c9f\r
+       mov     ecx,0xe8d00f8f\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldah:\r
+       mov     [operand_size],2\r
+       mov     edx,0x01f00c9f\r
+       mov     ecx,0xe8d00f9f\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldaex:\r
+       mov     [operand_size],4\r
+       mov     edx,0x01900e9f\r
+       mov     ecx,0xe8d00fef\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldaexb:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01d00e9f\r
+       mov     ecx,0xe8d00fcf\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldaexh:\r
+       mov     [operand_size],2\r
+       mov     edx,0x01f00e9f\r
+       mov     ecx,0xe8d00fdf\r
+       jmp     ARM_rd_q_rn_p\r
+ARM_instruction_ldaexd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x01b00e9f\r
+       mov     ecx,0xe8d000ff\r
+       jmp     ARM_rt_rt2_q_rn_p\r
+ARM_instruction_sevl:\r
+       INST_ARM64\r
+       dd      0xd50320bf\r
+       dd      ARM64_debug3\r
+       mov     edx,0x0320f005\r
+       mov     ecx,0xf3af8005\r
+       jmp     ARM_nops\r
+ARM_instruction_stl:\r
+       mov     [operand_size],4\r
+       mov     edx,0x0180fc90\r
+       mov     ecx,0xe8c00faf\r
+       jmp     ARM_rt_q_rn_p\r
+ARM_instruction_stlb:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01c0fc90\r
+       mov     ecx,0xe8c00f8f\r
+       jmp     ARM_rt_q_rn_p\r
+ARM_instruction_stlh:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01e0fc90\r
+       mov     ecx,0xe8c00f9f\r
+       jmp     ARM_rt_q_rn_p\r
+ARM_instruction_stlex:\r
+       mov     [operand_size],4\r
+       mov     edx,0x01800e90\r
+       mov     ecx,0xe8c00fe0\r
+       jmp     ARM_rd_rt_q_rn_p_STLEX\r
+ARM_instruction_stlexb:\r
+       mov     [operand_size],1\r
+       mov     edx,0x01c00e90\r
+       mov     ecx,0xe8c00fc0\r
+       jmp     ARM_rd_rt_q_rn_p_STLEX\r
+ARM_instruction_stlexh:\r
+       mov     [operand_size],2\r
+       mov     edx,0x01e00e90\r
+       mov     ecx,0xe8c00fd0\r
+       jmp     ARM_rd_rt_q_rn_p_STLEX\r
+ARM_instruction_stlexd:\r
+       mov     [operand_size],8\r
+       mov     edx,0x01a00e90\r
+       mov     ecx,0xe8c000f0\r
+       jmp     ARM_rd_rt_rt2_q_rn_p_STLEXD\r
+ARM_instruction_dcps1:\r
+       INST_ARM64\r
+       dd      0xd4a00001\r
+       dd      ARM64_debug2\r
+       mov     ecx,0xf78f8001\r
+       jmp     THUMB_v8\r
+ARM_instruction_dcps2:\r
+       INST_ARM64\r
+       dd      0xd4a00002\r
+       dd      ARM64_debug2\r
+       mov     ecx,0xf78f8002\r
+       jmp     THUMB_v8\r
+ARM_instruction_dcps3:\r
+       INST_ARM64\r
+       dd      0xd4a00003\r
+       dd      ARM64_debug2\r
+       mov     ecx,0xf78f8003\r
+       jmp     THUMB_v8\r
+\r
+;v8 VFP/SIMD\r
+ARM_instruction_vcvtm.s32.f32:\r
+       mov     edx,0xfebf0ac0\r
+       mov     ecx,0xf3bb0300\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtm.u32.f32:\r
+       mov     edx,0xfebf0a40\r
+       mov     ecx,0xf3bb0380\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtm.s32.f64:\r
+       mov     edx,0xfebf0bc0\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtm.u32.f64:\r
+       mov     edx,0xfebf0b40\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtp.s32.f32:\r
+       mov     edx,0xfebe0ac0\r
+       mov     ecx,0xf3bb0200\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtp.u32.f32:\r
+       mov     edx,0xfebe0a40\r
+       mov     ecx,0xf3bb0280\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtp.s32.f64:\r
+       mov     edx,0xfebe0bc0\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtp.u32.f64:\r
+       mov     edx,0xfebe0b40\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtn.s32.f32:\r
+       mov     edx,0xfebd0ac0\r
+       mov     ecx,0xf3bb0100\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtn.u32.f32:\r
+       mov     edx,0xfebd0a40\r
+       mov     ecx,0xf3bb0180\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvtn.s32.f64:\r
+       mov     edx,0xfebd0bc0\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtn.u32.f64:\r
+       mov     edx,0xfebd0b40\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvta.s32.f32:\r
+       mov     edx,0xfebc0ac0\r
+       mov     ecx,0xf3bb0000\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvta.u32.f32:\r
+       mov     edx,0xfebc0a40\r
+       mov     ecx,0xf3bb0080\r
+       jmp     SIMD_sd_sm\r
+ARM_instruction_vcvta.s32.f64:\r
+       mov     edx,0xfebc0bc0\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvta.u32.f64:\r
+       mov     edx,0xfebc0b40\r
+       jmp     SIMD_sd_dm\r
+ARM_instruction_vcvtb.f16.f64:\r
+       mov     edx,0x0eb30b40\r
+       jmp     VFP_sd_dm_HP\r
+ARM_instruction_vcvtb.f64.f16:\r
+       mov     edx,0x0eb20b40\r
+       jmp     VFP_dd_sm_HP\r
+ARM_instruction_vcvtt.f16.f64:\r
+       mov     edx,0x0eb30bc0\r
+       jmp     VFP_sd_dm_HP\r
+ARM_instruction_vcvtt.f64.f16:\r
+       mov     edx,0x0eb20bc0\r
+       jmp     VFP_dd_sm_HP\r
+ARM_instruction_vmaxnm.f32:\r
+       mov     edx,0xfe800a00\r
+       mov     ecx,0xf3000f10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_v8\r
+ARM_instruction_vmaxnm.f64:\r
+       mov     ecx,0xfe800b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+ARM_instruction_vminnm.f32:\r
+       mov     edx,0xfe800a40\r
+       mov     ecx,0xf3200f10\r
+       jmp     SIMD_FLOAT_vd_vn_vm_v8\r
+ARM_instruction_vminnm.f64:\r
+       mov     ecx,0xfe800b40\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+ARM_instruction_vrintm.f32.f32:\r
+       mov     edx,0xfebb0a40\r
+       mov     ecx,0xf3ba0680\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrintm.f64.f64:\r
+       mov     edx,0xfebb0b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrintp.f32.f32:\r
+       mov     edx,0xfeba0a40\r
+       mov     ecx,0xf3ba0780\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrintp.f64.f64:\r
+       mov     edx,0xfeba0b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrintn.f32.f32:\r
+       mov     edx,0xfeb90a40\r
+       mov     ecx,0xf3ba0400\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrintn.f64.f64:\r
+       mov     edx,0xfeb90b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrinta.f32.f32:\r
+       mov     edx,0xfeb80a40\r
+       mov     ecx,0xf3ba0500\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrinta.f64.f64:\r
+       mov     edx,0xfeb80b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrintx.f32.f32:\r
+       mov     edx,0x0eb70a40\r
+       mov     ecx,0xf3ba0480\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrintx.f64.f64:\r
+       mov     edx,0x0eb70b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrintr.f32.f32:\r
+       mov     edx,0x0eb60a40\r
+       jmp     SIMD_FLOAT_sd_sn_v8\r
+ARM_instruction_vrintr.f64.f64:\r
+       mov     edx,0x0eb60b40\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vrintz.f32.f32:\r
+       mov     edx,0x0eb60ac0\r
+       mov     ecx,0xf3ba0580\r
+       jmp     SIMD_FLOAT_vd_vn_v8\r
+ARM_instruction_vrintz.f64.f64:\r
+       mov     edx,0x0eb60bc0\r
+       jmp     SIMD_FLOAT_dd_dn_v8\r
+ARM_instruction_vseleq.f32:\r
+       mov     ecx,0xfe000a00\r
+       jmp     SIMD_FLOAT_sd_sn_sm_v8\r
+ARM_instruction_vseleq.f64:\r
+       mov     ecx,0xfe000b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+ARM_instruction_vselvs.f32:\r
+       mov     ecx,0xfe100a00\r
+       jmp     SIMD_FLOAT_sd_sn_sm_v8\r
+ARM_instruction_vselvs.f64:\r
+       mov     ecx,0xfe100b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+ARM_instruction_vselge.f32:\r
+       mov     ecx,0xfe200a00\r
+       jmp     SIMD_FLOAT_sd_sn_sm_v8\r
+ARM_instruction_vselge.f64:\r
+       mov     ecx,0xfe200b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+ARM_instruction_vselgt.f32:\r
+       mov     ecx,0xfe300a00\r
+       jmp     SIMD_FLOAT_sd_sn_sm_v8\r
+ARM_instruction_vselgt.f64:\r
+       mov     ecx,0xfe300b00\r
+       jmp     SIMD_FLOAT_dd_dn_dm_v8\r
+\r
+;v8 CRC\r
+ARM_instruction_crc32b:\r
+       INST_ARM64\r
+       dd      0x1ac04000\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1000040\r
+       mov     ecx,0xfac0f080\r
+       jmp     ARM_rd_rn_rm_crc\r
+ARM_instruction_crc32h:\r
+       INST_ARM64\r
+       dd      0x1ac04400\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1200040\r
+       mov     ecx,0xfac0f090\r
+       jmp     ARM_rd_rn_rm_crc\r
+ARM_instruction_crc32w:\r
+       INST_ARM64\r
+       dd      0x1ac04800\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1400040\r
+       mov     ecx,0xfac0f0a0\r
+       jmp     ARM_rd_rn_rm_crc\r
+ARM_instruction_crc32cb:\r
+       INST_ARM64\r
+       dd      0x1ac05000\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1000240\r
+       mov     ecx,0xfad0f080\r
+       jmp     ARM_rd_rn_rm_crc\r
+ARM_instruction_crc32ch:\r
+       INST_ARM64\r
+       dd      0x1ac05400\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1200240\r
+       mov     ecx,0xfad0f090\r
+       jmp     ARM_rd_rn_rm_crc\r
+ARM_instruction_crc32cw:\r
+       INST_ARM64\r
+       dd      0x1ac05800\r
+       dd      ARM64_wz_wz_wz\r
+       mov     edx,0xe1400240\r
+       mov     ecx,0xfad0f0a0\r
+       jmp     ARM_rd_rn_rm_crc\r
+\r
+;v8 crypto\r
+ARM_instruction_aesd.8:\r
+       mov     edx,0xf3b00340\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_aese.8:\r
+       mov     edx,0xf3b00300\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_aesimc.8:\r
+       mov     edx,0xf3b003c0\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_aesmc.8:\r
+       mov     edx,0xf3b00380\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_sha1h.32:\r
+       mov     edx,0xf3b902c0\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_sha1su1.32:\r
+       mov     edx,0xf3ba0380\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_sha256su0.32:\r
+       mov     edx,0xf3ba03c0\r
+       jmp     SIMD_CRYPTO_qd_qm\r
+ARM_instruction_sha1c.32:\r
+       mov     edx,0xf2000c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha1p.32:\r
+       mov     edx,0xf2100c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha1m.32:\r
+       mov     edx,0xf2200c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha1su0.32:\r
+       mov     edx,0xf2300c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha256h.32:\r
+       mov     edx,0xf3000c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha256h2.32:\r
+       mov     edx,0xf3100c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_sha256su1.32:\r
+       mov     edx,0xf3200c40\r
+       jmp     SIMD_CRYPTO_qd_qn_qm\r
+ARM_instruction_vmull.p64:\r
+       mov     edx,0xf2a00e00\r
+       jmp     SIMD_INT_qd_dn_dm\r
+\r
+;v8 64-bit\r
+\r
+ARM_instruction_adrp:\r
+       INST_ARM64\r
+       dd      0x90000000\r
+       dd      ARM64_adr\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_asrv:\r
+       INST_ARM64\r
+       dd      0x1ac02800\r
+       dd      ARM64_register_rotate\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_at:\r
+       INST_ARM64\r
+       dd      0xd5000000\r
+       dd      ARM64_sys_predefined_at\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.eq:\r
+       INST_ARM64\r
+       dd      0x54000000\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.ne:\r
+       INST_ARM64\r
+       dd      0x54000001\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.cs:\r
+       INST_ARM64\r
+       dd      0x54000002\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.cc:\r
+       INST_ARM64\r
+       dd      0x54000003\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.mi:\r
+       INST_ARM64\r
+       dd      0x54000004\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.pl:\r
+       INST_ARM64\r
+       dd      0x54000005\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.vs:\r
+       INST_ARM64\r
+       dd      0x54000006\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.vc:\r
+       INST_ARM64\r
+       dd      0x54000007\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.hi:\r
+       INST_ARM64\r
+       dd      0x54000008\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.ls:\r
+       INST_ARM64\r
+       dd      0x54000009\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.ge:\r
+       INST_ARM64\r
+       dd      0x5400000a\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.lt:\r
+       INST_ARM64\r
+       dd      0x5400000b\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.gt:\r
+       INST_ARM64\r
+       dd      0x5400000c\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.le:\r
+       INST_ARM64\r
+       dd      0x5400000d\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.al:\r
+       INST_ARM64\r
+       dd      0x5400000e\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.hs:\r
+       INST_ARM64\r
+       dd      0x54000002\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.lo:\r
+       INST_ARM64\r
+       dd      0x54000003\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_b.nv:\r
+       INST_ARM64\r
+       dd      0x5400000f\r
+       dd      ARM64_b_cond\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_bfm:\r
+       INST_ARM64\r
+       dd      0x33000000\r
+       dd      ARM64_bfm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_bfxil:\r
+       INST_ARM64\r
+       dd      0x33000000\r
+       dd      ARM64_bfxil\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_blr:\r
+       INST_ARM64\r
+       dd      0xd63f0000\r
+       dd      ARM64_br\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_br:\r
+       INST_ARM64\r
+       dd      0xd61f0000\r
+       dd      ARM64_br\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_brk:\r
+       INST_ARM64\r
+       dd      0xd4200000\r
+       dd      ARM64_debug\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ccmn:\r
+       INST_ARM64\r
+       dd      0x3a400000\r
+       dd      ARM64_conditional_compare\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ccmp:\r
+       INST_ARM64\r
+       dd      0x7a400000\r
+       dd      ARM64_conditional_compare\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cinc:\r
+       INST_ARM64\r
+       dd      0x1a800400\r
+       dd      ARM64_conditional_modify\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cinv:\r
+       INST_ARM64\r
+       dd      0x5a800000\r
+       dd      ARM64_conditional_modify\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cls:\r
+       INST_ARM64\r
+       dd      0x5ac01400\r
+       dd      ARM64_arithmetic4\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cneg:\r
+       INST_ARM64\r
+       dd      0x5a800400\r
+       dd      ARM64_conditional_modify_zr\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_crc32x:\r
+       INST_ARM64\r
+       dd      0x9ac04c00\r
+       dd      ARM64_wz_wz_xz\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_crc32cx:\r
+       INST_ARM64\r
+       dd      0x9ac05c00\r
+       dd      ARM64_wz_wz_xz\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_csel:\r
+       INST_ARM64\r
+       dd      0x1a800000\r
+       dd      ARM64_conditional_select\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cset:\r
+       INST_ARM64\r
+       dd      0x1a9f07e0\r
+       dd      ARM64_conditional_set\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_csetm:\r
+       INST_ARM64\r
+       dd      0x5a9f03e0\r
+       dd      ARM64_conditional_set\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_csinc:\r
+       INST_ARM64\r
+       dd      0x1a800400\r
+       dd      ARM64_conditional_select\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_csinv:\r
+       INST_ARM64\r
+       dd      0x5a800000\r
+       dd      ARM64_conditional_select\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_csneg:\r
+       INST_ARM64\r
+       dd      0x5a800400\r
+       dd      ARM64_conditional_select\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_dc:\r
+       INST_ARM64\r
+       dd      0xd5000000\r
+       dd      ARM64_sys_predefined_dc\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_drps:\r
+       INST_ARM64\r
+       dd      0xd6bf03e0\r
+       dd      ARM64_debug3\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_eon:\r
+       INST_ARM64\r
+       dd      0x40200000\r
+       dd      ARM64_arithmetic2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_extr:\r
+       INST_ARM64\r
+       dd      0x13800000\r
+       dd      ARM64_arithmetic5\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_hint:\r
+       INST_ARM64\r
+       dd      0xd503201f\r
+       dd      ARM64_hint\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ic:\r
+       INST_ARM64\r
+       dd      0xd5000000\r
+       dd      ARM64_sys_predefined_ic\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldar:\r
+       INST_ARM64\r
+       dd      0x88dffc00\r
+       dd      ARM64_memory_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldarb:\r
+       INST_ARM64\r
+       dd      0x08dffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldarh:\r
+       INST_ARM64\r
+       dd      0x48dffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldaxp:\r
+       INST_ARM64\r
+       dd      0x887f8000\r
+       dd      ARM64_memory_double_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldaxr:\r
+       INST_ARM64\r
+       dd      0x885ffc00\r
+       dd      ARM64_memory_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldaxrb:\r
+       INST_ARM64\r
+       dd      0x085ffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldaxrh:\r
+       INST_ARM64\r
+       dd      0x485ffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldnp:\r
+       INST_ARM64\r
+       dd      0x28400000\r
+       dd      ARM64_memory_double_imm7\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldp:\r
+       INST_ARM64\r
+       dd      0x28400000\r
+       dd      ARM64_memory_double_imm7_post_pre_offset\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldpsw:\r
+       INST_ARM64\r
+       dd      0x68400000\r
+       dd      ARM64_memory_double_imm7_signed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldrsw:\r
+       INST_ARM64\r
+       dd      0x38800000\r
+       dd      ARM64_memory_signed_word\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtr:\r
+       INST_ARM64\r
+       dd      0x38400c00\r
+       dd      ARM64_memory_unprivileged\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtrb:\r
+       INST_ARM64\r
+       dd      0x38400c00\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtrh:\r
+       INST_ARM64\r
+       dd      0x38400c01\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtrsb:\r
+       INST_ARM64\r
+       dd      0x38c00c00\r
+       dd      ARM64_memory_unprivileged_signed_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtrsh:\r
+       INST_ARM64\r
+       dd      0x38c00c01\r
+       dd      ARM64_memory_unprivileged_signed_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldtrsw:\r
+       INST_ARM64\r
+       dd      0x38800c00\r
+       dd      ARM64_memory_unprivileged_signed_word\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldur:\r
+       INST_ARM64\r
+       dd      0x38400400\r
+       dd      ARM64_memory_unscaled\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldurb:\r
+       INST_ARM64\r
+       dd      0x38400400\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldurh:\r
+       INST_ARM64\r
+       dd      0x38400401\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldursb:\r
+       INST_ARM64\r
+       dd      0x38800400\r
+       dd      ARM64_memory_unprivileged_signed_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldursh:\r
+       INST_ARM64\r
+       dd      0x38800401\r
+       dd      ARM64_memory_unprivileged_signed_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldursw:\r
+       INST_ARM64\r
+       dd      0x38800400\r
+       dd      ARM64_memory_unprivileged_signed_word\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldxp:\r
+       INST_ARM64\r
+       dd      0x887f0000\r
+       dd      ARM64_memory_double_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldxr:\r
+       INST_ARM64\r
+       dd      0x885f7c00\r
+       dd      ARM64_memory_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldxrb:\r
+       INST_ARM64\r
+       dd      0x085f7c00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ldxrh:\r
+       INST_ARM64\r
+       dd      0x485f7c00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_lslv:\r
+       INST_ARM64\r
+       dd      0x1ac02000\r
+       dd      ARM64_register_rotate\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_lsrv:\r
+       INST_ARM64\r
+       dd      0x1ac02400\r
+       dd      ARM64_register_rotate\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_madd:\r
+       INST_ARM64\r
+       dd      0x1b000000\r
+       dd      ARM64_dz_nz_mz_az\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_mneg:\r
+       INST_ARM64\r
+       dd      0x1b00fc00\r
+       dd      ARM64_dz_nz_mz\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_movk:\r
+       INST_ARM64\r
+       dd      0x72800000\r
+       dd      ARM64_mov_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_movn:\r
+       INST_ARM64\r
+       dd      0x12800000\r
+       dd      ARM64_mov_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_movz:\r
+       INST_ARM64\r
+       dd      0x52800000\r
+       dd      ARM64_mov_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_msub:\r
+       INST_ARM64\r
+       dd      0x1b008000\r
+       dd      ARM64_dz_nz_mz_az\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ngc:\r
+       INST_ARM64S\r
+       dd      0x5a0003e0\r
+       dd      ARM64_arithmetic9\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_prfm:\r
+       INST_ARM64\r
+       dd      0xf8800000\r
+       dd      ARM64_prefetch\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ret:\r
+       INST_ARM64\r
+       dd      0xd65f0000\r
+       dd      ARM64_ret\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rev32:\r
+       INST_ARM64\r
+       dd      0xdac00800\r
+       dd      ARM64_arithmetic13\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rev64:\r
+       INST_ARM64\r
+       dd      0xdac00c00\r
+       dd      ARM64_arithmetic14\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rorv:\r
+       INST_ARM64\r
+       dd      0x1ac02c00\r
+       dd      ARM64_register_rotate\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sbfiz:\r
+       INST_ARM64\r
+       dd      0x13000000\r
+       dd      ARM64_bfi\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sbfm:\r
+       INST_ARM64\r
+       dd      0x13000000\r
+       dd      ARM64_bfm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smaddl:\r
+       INST_ARM64\r
+       dd      0x9b200000\r
+       dd      ARM64_dx_nw_mw_ax\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smnegl:\r
+       INST_ARM64\r
+       dd      0x9b20fc00\r
+       dd      ARM64_dx_nw_mw\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smsubl:\r
+       INST_ARM64\r
+       dd      0x9b208000\r
+       dd      ARM64_dx_nw_mw_ax\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smulh:\r
+       INST_ARM64\r
+       dd      0x9b407c00\r
+       dd      ARM64_xz_xz_xz\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlr:\r
+       INST_ARM64\r
+       dd      0x889ffc00\r
+       dd      ARM64_memory_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlrb:\r
+       INST_ARM64\r
+       dd      0x089ffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlrh:\r
+       INST_ARM64\r
+       dd      0x489ffc00\r
+       dd      ARM64_memory_word_single_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlxp:\r
+       INST_ARM64\r
+       dd      0x88208000\r
+       dd      ARM64_memory_triple_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlxr:\r
+       INST_ARM64\r
+       dd      0x8800fc00\r
+       dd      ARM64_memory_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlxrb:\r
+       INST_ARM64\r
+       dd      0x0800fc00\r
+       dd      ARM64_memory_word_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stlxrh:\r
+       INST_ARM64\r
+       dd      0x4800fc00\r
+       dd      ARM64_memory_word_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stnp:\r
+       INST_ARM64\r
+       dd      0x28000000\r
+       dd      ARM64_memory_double_imm7\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stp:\r
+       INST_ARM64\r
+       dd      0x28000000\r
+       dd      ARM64_memory_double_imm7_post_pre_offset\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sttr:\r
+       INST_ARM64\r
+       dd      0x38000c00\r
+       dd      ARM64_memory_unprivileged\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sttrb:\r
+       INST_ARM64\r
+       dd      0x38000c00\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sttrh:\r
+       INST_ARM64\r
+       dd      0x38000c01\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stur:\r
+       INST_ARM64\r
+       dd      0x38000400\r
+       dd      ARM64_memory_unscaled\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sturb:\r
+       INST_ARM64\r
+       dd      0x38000400\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sturh:\r
+       INST_ARM64\r
+       dd      0x38000401\r
+       dd      ARM64_memory_unprivileged_byte_hword\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stxp:\r
+       INST_ARM64\r
+       dd      0x88200000\r
+       dd      ARM64_memory_triple_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stxr:\r
+       INST_ARM64\r
+       dd      0x88007c00\r
+       dd      ARM64_memory_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stxrb:\r
+       INST_ARM64\r
+       dd      0x08007c00\r
+       dd      ARM64_memory_word_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_stxrh:\r
+       INST_ARM64\r
+       dd      0x48007c00\r
+       dd      ARM64_memory_word_double_release_fixed\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sxtw:\r
+       INST_ARM64\r
+       dd      0x93407c00\r
+       dd      ARM64_dx_nw\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sys:\r
+       INST_ARM64\r
+       dd      0xd5080000\r
+       dd      ARM64_sys\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sysl:\r
+       INST_ARM64\r
+       dd      0xd5280000\r
+       dd      ARM64_sysl\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_tbnz:\r
+       INST_ARM64\r
+       dd      0x37000000\r
+       dd      ARM64_tb\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_tbz:\r
+       INST_ARM64\r
+       dd      0x36000000\r
+       dd      ARM64_tb\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_tlbi:\r
+       INST_ARM64\r
+       dd      0xd5000000\r
+       dd      ARM64_sys_predefined_tlbi\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ubfiz:\r
+       INST_ARM64\r
+       dd      0x53000000\r
+       dd      ARM64_bfi\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ubfm:\r
+       INST_ARM64\r
+       dd      0x53000000\r
+       dd      ARM64_bfm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umaddl:\r
+       INST_ARM64\r
+       dd      0x9ba00000\r
+       dd      ARM64_dx_nw_mw_ax\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umnegl:\r
+       INST_ARM64\r
+       dd      0x9ba0fc00\r
+       dd      ARM64_dx_nw_mw\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umsubl:\r
+       INST_ARM64\r
+       dd      0x9ba08000\r
+       dd      ARM64_dx_nw_mw_ax\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umulh:\r
+       INST_ARM64\r
+       dd      0x9bc07c00\r
+       dd      ARM64_xz_xz_xz\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_abs:\r
+       INST_ARM64\r
+       dd      0x0e20b800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_addhn:\r
+       INST_ARM64\r
+       dd      0x0e204000\r
+       dd      ARM64_vector_narrow_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_addhn2:\r
+       INST_ARM64\r
+       dd      0x4e204000\r
+       dd      ARM64_vector_narrow_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_addp:\r
+       INST_ARM64\r
+       dd      0x0e20bc00\r
+       dd      ARM64_vector_narrow_3reg_scalar_2reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_addv:\r
+       INST_ARM64\r
+       dd      0x0e31b800\r
+       dd      ARM64_vector_reduce_bhs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_aesd:\r
+       INST_ARM64\r
+       dd      0x4e285800\r
+       dd      ARM64_crypto_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_aese:\r
+       INST_ARM64\r
+       dd      0x4e284800\r
+       dd      ARM64_crypto_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_aesimc:\r
+       INST_ARM64\r
+       dd      0x4e287800\r
+       dd      ARM64_crypto_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_aesmc:\r
+       INST_ARM64\r
+       dd      0x4e286800\r
+       dd      ARM64_crypto_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_bif:\r
+       INST_ARM64\r
+       dd      0x2ee01c00\r
+       dd      ARM64_vector_scalar_b_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_bit:\r
+       INST_ARM64\r
+       dd      0x2ea01c00\r
+       dd      ARM64_vector_scalar_b_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_bsl:\r
+       INST_ARM64\r
+       dd      0x2e601c00\r
+       dd      ARM64_vector_scalar_b_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmeq:\r
+       INST_ARM64\r
+       dd      0x2e208c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_zero\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmge:\r
+       INST_ARM64\r
+       dd      0x0e203c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_zero\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmgt:\r
+       INST_ARM64\r
+       dd      0x0e203400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_zero\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmhi:\r
+       INST_ARM64\r
+       dd      0x2e203400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmhs:\r
+       INST_ARM64\r
+       dd      0x2e203c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmle:\r
+       INST_ARM64\r
+       dd      0x2e209800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_zero\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmlt:\r
+       INST_ARM64\r
+       dd      0x0e20a800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_zero\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cmtst:\r
+       INST_ARM64\r
+       dd      0x0e208c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_cnt:\r
+       INST_ARM64\r
+       dd      0x0e205800\r
+       dd      ARM64_vector_b_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_dup:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_dup\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ext:\r
+       INST_ARM64\r
+       dd      0x2e000000\r
+       dd      ARM64_vector_b_three_reg_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fabd:\r
+       INST_ARM64V\r
+       dd      0x7ea0d400      ;scalar\r
+       dd      0x2ea0d400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fabs:\r
+       INST_ARM64V\r
+       dd      0x1e20c000      ;scalar\r
+       dd      0x0ea0f800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_facge:\r
+       INST_ARM64V\r
+       dd      0x7e20ec00      ;scalar\r
+       dd      0x2e20ec00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_facgt:\r
+       INST_ARM64V\r
+       dd      0x7ea0ec00      ;scalar\r
+       dd      0x2ea0ec00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fadd:\r
+       INST_ARM64V\r
+       dd      0x1e202800      ;scalar\r
+       dd      0x0e20d400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_faddp:\r
+       INST_ARM64V\r
+       dd      0x7e30d800      ;scalar\r
+       dd      0x2e20d400      ;vector\r
+       dd      ARM64_vector_scalar_sd_pairs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fccmp:\r
+       INST_ARM64\r
+       dd      0x1e200400\r
+       dd      ARM64_conditional_compare_float\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fccmpe:\r
+       INST_ARM64\r
+       dd      0x1e200410\r
+       dd      ARM64_conditional_compare_float\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmeq:\r
+       INST_ARM64V\r
+       dd      0x5e20e400      ;scalar\r
+       dd      0x0e20e400      ;vector\r
+       dd      ARM64_vector_scalar_sd_compare_mask_eq\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmge:\r
+       INST_ARM64V\r
+       dd      0x7e20e400      ;scalar\r
+       dd      0x2e20e400      ;vector\r
+       dd      ARM64_vector_scalar_sd_compare_mask_ge\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmgt:\r
+       INST_ARM64V\r
+       dd      0x7ea0e400      ;scalar\r
+       dd      0x2ea0e400      ;vector\r
+       dd      ARM64_vector_scalar_sd_compare_mask_gt\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmle:\r
+       INST_ARM64V\r
+       dd      0x7ea0d800      ;scalar\r
+       dd      0x2ea0d800      ;vector\r
+       dd      ARM64_vector_scalar_sd_compare_mask_le\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmlt:\r
+       INST_ARM64V\r
+       dd      0x5ea0e800      ;scalar\r
+       dd      0x0ea0e800      ;vector\r
+       dd      ARM64_vector_scalar_sd_compare_mask_le\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmp:\r
+       INST_ARM64\r
+       dd      0x1e202000\r
+       dd      ARM64_scalar_sd_compare\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcmpe:\r
+       INST_ARM64\r
+       dd      0x1e202010\r
+       dd      ARM64_scalar_sd_compare\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcsel:\r
+       INST_ARM64\r
+       dd      0x1e200c00\r
+       dd      ARM64_scalar_conditional_select\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvt:\r
+       INST_ARM64\r
+       dd      0x1e224000\r
+       dd      ARM64_scalar_hsd_convert\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtas:\r
+       INST_ARM64V\r
+       dd      0x5e21c800      ;scalar\r
+       dd      0x0e21c800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_as\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtau:\r
+       INST_ARM64V\r
+       dd      0x7e21c800      ;scalar\r
+       dd      0x2e21c800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_au\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtl:\r
+       INST_ARM64\r
+       dd      0x0e217800\r
+       dd      ARM64_vector_convert_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtl2:\r
+       INST_ARM64\r
+       dd      0x4e217800\r
+       dd      ARM64_vector_convert_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtms:\r
+       INST_ARM64V\r
+       dd      0x5e21b800      ;scalar\r
+       dd      0x0e21b800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_ms\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtmu:\r
+       INST_ARM64V\r
+       dd      0x7e21b800      ;scalar\r
+       dd      0x2e21b800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_mu\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtn:\r
+       INST_ARM64\r
+       dd      0x0e216800\r
+       dd      ARM64_vector_convert_narrow\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtn2:\r
+       INST_ARM64\r
+       dd      0x4e216800\r
+       dd      ARM64_vector_convert_narrow2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtns:\r
+       INST_ARM64V\r
+       dd      0x5e21a800      ;scalar\r
+       dd      0x0e21a800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_ns\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtnu:\r
+       INST_ARM64V\r
+       dd      0x7e21a800      ;scalar\r
+       dd      0x2e21a800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_nu\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtps:\r
+       INST_ARM64V\r
+       dd      0x5ea1a800      ;scalar\r
+       dd      0x0ea1a800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_ps\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtpu:\r
+       INST_ARM64V\r
+       dd      0x7ea1a800      ;scalar\r
+       dd      0x2ea1a800      ;vector\r
+       dd      ARM64_vector_scalar_sdwx_two_reg_pu\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtxn:\r
+       INST_ARM64V\r
+       dd      0x7e616800      ;scalar\r
+       dd      0x2e616800      ;vector\r
+       dd      ARM64_vector_convert_odd_narrow\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtxn2:\r
+       INST_ARM64\r
+       dd      0x6e616800\r
+       dd      ARM64_vector_convert_odd_narrow2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtzs:\r
+       INST_ARM64V\r
+       dd      0x5ea1b800      ;scalar\r
+       dd      0x0ea1b800      ;vector\r
+       dd      ARM64_vector_scalar_sd_convert_zero_s\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fcvtzu:\r
+       INST_ARM64V\r
+       dd      0x7ea1b800      ;scalar\r
+       dd      0x2ea1b800      ;vector\r
+       dd      ARM64_vector_scalar_sd_convert_zero_u\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fdiv:\r
+       INST_ARM64V\r
+       dd      0x1e201800      ;scalar\r
+       dd      0x2e20fc00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmadd:\r
+       INST_ARM64\r
+       dd      0x1f000000\r
+       dd      ARM64_scalar_sd_four_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmax:\r
+       INST_ARM64V\r
+       dd      0x1e204800      ;scalar\r
+       dd      0x0e20f400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmaxnm:\r
+       INST_ARM64V\r
+       dd      0x1e206800      ;scalar\r
+       dd      0x0e20c400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmaxnmp:\r
+       INST_ARM64V\r
+       dd      0x7e30c800      ;scalar\r
+       dd      0x2e20c400      ;vector\r
+       dd      ARM64_vector_scalar_sd_pairs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmaxnmv:\r
+       INST_ARM64\r
+       dd      0x6e30c800\r
+       dd      ARM64_vector_4_to_1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmaxp:\r
+       INST_ARM64V\r
+       dd      0x7e30f800      ;scalar\r
+       dd      0x2e20f400      ;vector\r
+       dd      ARM64_vector_scalar_sd_pairs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmaxv:\r
+       INST_ARM64\r
+       dd      0x6e30f800\r
+       dd      ARM64_vector_4_to_1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmin:\r
+       INST_ARM64V\r
+       dd      0x1e205800      ;scalar\r
+       dd      0x0ea0f400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fminnm:\r
+       INST_ARM64V\r
+       dd      0x1e207800      ;scalar\r
+       dd      0x0ea0c400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fminnmp:\r
+       INST_ARM64V\r
+       dd      0x7eb0c800      ;scalar\r
+       dd      0x2ea0c400      ;vector\r
+       dd      ARM64_vector_scalar_sd_pairs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fminnmv:\r
+       INST_ARM64\r
+       dd      0x6eb0c800\r
+       dd      ARM64_vector_4_to_1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fminp:\r
+       INST_ARM64V\r
+       dd      0x7eb0f800      ;scalar\r
+       dd      0x2ea0f400      ;vector\r
+       dd      ARM64_vector_scalar_sd_pairs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fminv:\r
+       INST_ARM64\r
+       dd      0x6eb0f800\r
+       dd      ARM64_vector_4_to_1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmla:\r
+       INST_ARM64V\r
+       dd      0x5f801000      ;scalar\r
+       dd      0x0f801000      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg_element_add\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmov:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_fmov\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmsub:\r
+       INST_ARM64\r
+       dd      0x1f008000\r
+       dd      ARM64_scalar_sd_four_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmul:\r
+       INST_ARM64V\r
+       dd      0x1e200800      ;scalar\r
+       dd      0x2e20dc00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg_element\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fmulx:\r
+       INST_ARM64V\r
+       dd      0x5e20dc00      ;scalar\r
+       dd      0x0e20dc00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg_element_x\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fneg:\r
+       INST_ARM64V\r
+       dd      0x1e214000      ;scalar\r
+       dd      0x2ea0f800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fnmadd:\r
+       INST_ARM64\r
+       dd      0x1f200000\r
+       dd      ARM64_scalar_sd_four_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fnmsub:\r
+       INST_ARM64\r
+       dd      0x1f208000\r
+       dd      ARM64_scalar_sd_four_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fnmul:\r
+       INST_ARM64\r
+       dd      0x1e208800\r
+       dd      ARM64_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frecpe:\r
+       INST_ARM64V\r
+       dd      0x5ea1d800      ;scalar\r
+       dd      0x0ea1d800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frecps:\r
+       INST_ARM64V\r
+       dd      0x5e20fc00      ;scalar\r
+       dd      0x0e20fc00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frecpx:\r
+       INST_ARM64\r
+       dd      0x5ea1f800\r
+       dd      ARM64_scalar_sd_rwo_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frinta:\r
+       INST_ARM64V\r
+       dd      0x1e264000      ;scalar\r
+       dd      0x2e218800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frinti:\r
+       INST_ARM64V\r
+       dd      0x1e27c000      ;scalar\r
+       dd      0x2ea19800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frintm:\r
+       INST_ARM64V\r
+       dd      0x1e254000      ;scalar\r
+       dd      0x0e219800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frintn:\r
+       INST_ARM64V\r
+       dd      0x1e244000      ;scalar\r
+       dd      0x0e218800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frintp:\r
+       INST_ARM64V\r
+       dd      0x1e24c000      ;scalar\r
+       dd      0x0ea18800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frintx:\r
+       INST_ARM64V\r
+       dd      0x1e274000      ;scalar\r
+       dd      0x2e219800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frintz:\r
+       INST_ARM64V\r
+       dd      0x1e25c000      ;scalar\r
+       dd      0x0ea19800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frsqrte:\r
+       INST_ARM64V\r
+       dd      0x7ea1d800      ;scalar\r
+       dd      0x2ea1d800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_frsqrts:\r
+       INST_ARM64V\r
+       dd      0x5ea0fc00      ;scalar\r
+       dd      0x0ea0fc00      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fsqrt:\r
+       INST_ARM64V\r
+       dd      0x1e21c000      ;scalar\r
+       dd      0x2ea1f800      ;vector\r
+       dd      ARM64_vector_scalar_sd_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_fsub:\r
+       INST_ARM64V\r
+       dd      0x1e203800      ;scalar\r
+       dd      0x0ea0d400      ;vector\r
+       dd      ARM64_vector_scalar_sd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ins:\r
+       INST_ARM64\r
+       dd      0x00000000\r
+       dd      ARM64_ins\r
+ARM_instruction_ld1:\r
+       INST_ARM64V\r
+       dd      0x0dc00000      ;single\r
+       dd      0x0cc02000      ;multiple\r
+       dd      ARM64_ld1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ld1r:\r
+       INST_ARM64\r
+       dd      0x0dc0c000\r
+       dd      ARM64_ld1r\r
+ARM_instruction_ld2:\r
+       INST_ARM64V\r
+       dd      0x0de00000      ;single\r
+       dd      0x0cc00000      ;multiple\r
+       dd      ARM64_ld2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ld2r:\r
+       INST_ARM64\r
+       dd      0x0de0c000\r
+       dd      ARM64_ld2r\r
+ARM_instruction_ld3:\r
+       INST_ARM64V\r
+       dd      0x0dc02000      ;single\r
+       dd      0x0cc00000      ;multiple\r
+       dd      ARM64_ld3\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ld3r:\r
+       INST_ARM64\r
+       dd      0x0dc0e000\r
+       dd      ARM64_ld3r\r
+ARM_instruction_ld4:\r
+       INST_ARM64V\r
+       dd      0x0de02000      ;single\r
+       dd      0x0cc00000      ;multiple\r
+       dd      ARM64_ld4\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ld4r:\r
+       INST_ARM64\r
+       dd      0x0de0e000\r
+       dd      ARM64_ld4r\r
+ARM_instruction_movi:\r
+       INST_ARM64\r
+       dd      0x0f000400\r
+       dd      ARM64_movi\r
+ARM_instruction_mvni:\r
+       INST_ARM64\r
+       dd      0x2f000400\r
+       dd      ARM64_mvni\r
+ARM_instruction_not:\r
+       INST_ARM64\r
+       dd      0x2e205800\r
+       dd      ARM64_vector_b_two_reg\r
+ARM_instruction_pmul:\r
+       INST_ARM64\r
+       dd      0x2e209c00\r
+       dd      ARM64_vector_scalar_b_three_reg\r
+ARM_instruction_pmull:\r
+       INST_ARM64\r
+       dd      0x0e20e000\r
+       dd      ARM64_polynomial\r
+ARM_instruction_pmull2:\r
+       INST_ARM64\r
+       dd      0x4e20e000\r
+       dd      ARM64_polynomial2\r
+ARM_instruction_raddhn:\r
+       INST_ARM64\r
+       dd      0x2e204000\r
+       dd      ARM64_vector_narrow_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_raddhn2:\r
+       INST_ARM64\r
+       dd      0x6e204000\r
+       dd      ARM64_vector_narrow_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rshrn:\r
+       INST_ARM64\r
+       dd      0x0f008c00\r
+       dd      ARM64_vector_narrow_shift_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rshrn2:\r
+       INST_ARM64\r
+       dd      0x4f008c00\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rsubhn:\r
+       INST_ARM64\r
+       dd      0x2e206000\r
+       dd      ARM64_vector_narrow_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_rsubhn2:\r
+       INST_ARM64\r
+       dd      0x6e206000\r
+       dd      ARM64_vector_narrow_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saba:\r
+       INST_ARM64\r
+       dd      0x0e207c00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sabal:\r
+       INST_ARM64\r
+       dd      0x0e205000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sabal2:\r
+       INST_ARM64\r
+       dd      0x4e205000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sabd:\r
+       INST_ARM64\r
+       dd      0x0e207400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sabdl:\r
+       INST_ARM64\r
+       dd      0x0e207000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sabdl2:\r
+       INST_ARM64\r
+       dd      0x4e207000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sadalp:\r
+       INST_ARM64\r
+       dd      0x0e206800\r
+       dd      ARM64_vector_bhs_two_reg_pair\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddl:\r
+       INST_ARM64\r
+       dd      0x0e200000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddl2:\r
+       INST_ARM64\r
+       dd      0x4e200000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddlp:\r
+       INST_ARM64\r
+       dd      0x0e202800\r
+       dd      ARM64_vector_bhs_two_reg_pair\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddlv:\r
+       INST_ARM64\r
+       dd      0x0e303800\r
+       dd      ARM64_scalar_vector_bhs_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddw:\r
+       INST_ARM64\r
+       dd      0x0e201000\r
+       dd      ARM64_vector_bhs_three_reg_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_saddw2:\r
+       INST_ARM64\r
+       dd      0x4e201000\r
+       dd      ARM64_vector_bhs_three_reg_wide2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_scvtf:\r
+       INST_ARM64V\r
+       dd      0x5e21d800      ;scalar\r
+       dd      0x0e21d800      ;vector\r
+       dd      ARM64_scalar_vector_sd_convert_zero_s\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1c:\r
+       INST_ARM64\r
+       dd      0x5e000000\r
+       dd      ARM64_sha_qsv\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1h:\r
+       INST_ARM64\r
+       dd      0x5e280800\r
+       dd      ARM64_sha_s_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1m:\r
+       INST_ARM64\r
+       dd      0x5e002000\r
+       dd      ARM64_sha_qsv\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1p:\r
+       INST_ARM64\r
+       dd      0x5e001000\r
+       dd      ARM64_sha_qsv\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1su0:\r
+       INST_ARM64\r
+       dd      0x5e003000\r
+       dd      ARM64_sha_vs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha1su1:\r
+       INST_ARM64\r
+       dd      0x5e281800\r
+       dd      ARM64_sha_vs_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha256h:\r
+       INST_ARM64\r
+       dd      0x5e004000\r
+       dd      ARM64_sha_qqv\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha256h2:\r
+       INST_ARM64\r
+       dd      0x5e005000\r
+       dd      ARM64_sha_qqv\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha256su0:\r
+       INST_ARM64\r
+       dd      0x5e282800\r
+       dd      ARM64_sha_vs_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sha256su1:\r
+       INST_ARM64\r
+       dd      0x5e006000\r
+       dd      ARM64_sha_vs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shadd:\r
+       INST_ARM64\r
+       dd      0x0e200400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shl:\r
+       INST_ARM64\r
+       dd      0x0f005400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_left_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shll:\r
+       INST_ARM64\r
+       dd      0x2e213800\r
+       dd      ARM64_vector_scalar_bhs_long_size\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shll2:\r
+       INST_ARM64\r
+       dd      0x6e213800\r
+       dd      ARM64_vector_scalar_bhs_long2_size\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shrn:\r
+       INST_ARM64\r
+       dd      0x0f008400\r
+       dd      ARM64_vector_narrow_shift_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shrn2:\r
+       INST_ARM64\r
+       dd      0x4f008400\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_shsub:\r
+       INST_ARM64\r
+       dd      0x0e202400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sli:\r
+       INST_ARM64\r
+       dd      0x2f005400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_left_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smax:\r
+       INST_ARM64\r
+       dd      0x0e206400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smaxp:\r
+       INST_ARM64\r
+       dd      0x0e20a400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smaxv:\r
+       INST_ARM64\r
+       dd      0x0e30a800\r
+       dd      ARM64_vector_reduce_bhs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smin:\r
+       INST_ARM64\r
+       dd      0x0e206c00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sminp:\r
+       INST_ARM64\r
+       dd      0x0e20ac00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sminv:\r
+       INST_ARM64\r
+       dd      0x0e31a800\r
+       dd      ARM64_vector_reduce_bhs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smlal2:\r
+       INST_ARM64V\r
+       dd      0x4e208000      ;vector\r
+       dd      0x4f002000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smlsl:\r
+       INST_ARM64V\r
+       dd      0x0e20a000      ;vector\r
+       dd      0x0f006000      ;element\r
+       dd      ARM64_arithmetic18_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smlsl2:\r
+       INST_ARM64V\r
+       dd      0x4e20a000      ;vector\r
+       dd      0x4f006000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smov:\r
+       INST_ARM64\r
+       dd      0x0e002c00\r
+       dd      ARM64_smov\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_smull2:\r
+       INST_ARM64V\r
+       dd      0x4e20c000      ;vector\r
+       dd      0x4f00a000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqabs:\r
+       INST_ARM64\r
+       dd      0x0e207800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqadd:\r
+       INST_ARM64\r
+       dd      0x0e200c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmlal:\r
+       INST_ARM64V\r
+       dd      0x0e209000      ;vector\r
+       dd      0x0f003000      ;element\r
+       dd      ARM64_arithmetic19_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmlal2:\r
+       INST_ARM64V\r
+       dd      0x4e209000      ;vector\r
+       dd      0x4f003000      ;element\r
+       dd      ARM64_arithmetic19_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmlsl:\r
+       INST_ARM64V\r
+       dd      0x0e20b000      ;vector\r
+       dd      0x0f007000      ;element\r
+       dd      ARM64_arithmetic19_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmlsl2:\r
+       INST_ARM64V\r
+       dd      0x4e20b000      ;vector\r
+       dd      0x4f007000      ;element\r
+       dd      ARM64_arithmetic19_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmulh:\r
+       INST_ARM64V\r
+       dd      0x0e20b400      ;vector\r
+       dd      0x0f00c000      ;element\r
+       dd      ARM64_arithmetic20\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmull:\r
+       INST_ARM64V\r
+       dd      0x0e20d000      ;vector\r
+       dd      0x0f00b000      ;element\r
+       dd      ARM64_arithmetic19_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqdmull2:\r
+       INST_ARM64V\r
+       dd      0x4e20d000      ;vector\r
+       dd      0x4f00b000      ;element\r
+       dd      ARM64_arithmetic19_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqneg:\r
+       INST_ARM64\r
+       dd      0x2e207800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrdmulh:\r
+       INST_ARM64V\r
+       dd      0x2e20b400      ;vector\r
+       dd      0x0f00d000      ;element\r
+       dd      ARM64_arithmetic20\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrshl:\r
+       INST_ARM64\r
+       dd      0x0e205c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrshrn:\r
+       INST_ARM64\r
+       dd      0x0f009c00\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrshrn2:\r
+       INST_ARM64\r
+       dd      0x4f009c00\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrshrun:\r
+       INST_ARM64\r
+       dd      0x2f008c00\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqrshrun2:\r
+       INST_ARM64\r
+       dd      0x6f008c00\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshl:\r
+       INST_ARM64V\r
+       dd      0x0e204c00      ;register\r
+       dd      0x0f007400      ;immediate\r
+       dd      ARM64_vector_scalar_bhsd_shift_reg_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshlu:\r
+       INST_ARM64\r
+       dd      0x2f006400\r
+       dd      ARM64_vector_scalar_bhsd_shift_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshrn:\r
+       INST_ARM64\r
+       dd      0x0f009400\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshrn2:\r
+       INST_ARM64\r
+       dd      0x4f009400\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshrun:\r
+       INST_ARM64\r
+       dd      0x2f008400\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqshrun2:\r
+       INST_ARM64\r
+       dd      0x6f008400\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqsub:\r
+       INST_ARM64\r
+       dd      0x0e202c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqxtn:\r
+       INST_ARM64\r
+       dd      0x0e214800\r
+       dd      ARM64_vector_scalar_narrow_extract_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqxtn2:\r
+       INST_ARM64\r
+       dd      0x4e214800\r
+       dd      ARM64_vector_narrow_extract_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqxtun:\r
+       INST_ARM64\r
+       dd      0x2e212800\r
+       dd      ARM64_vector_scalar_narrow_extract_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sqxtun2:\r
+       INST_ARM64\r
+       dd      0x6e212800\r
+       dd      ARM64_vector_narrow_extract_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_srhadd:\r
+       INST_ARM64\r
+       dd      0x0e201400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sri:\r
+       INST_ARM64\r
+       dd      0x2f004400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_srshl:\r
+       INST_ARM64\r
+       dd      0x0e205400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_srshr:\r
+       INST_ARM64\r
+       dd      0x0f002400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_srsra:\r
+       INST_ARM64\r
+       dd      0x0f003400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sshl:\r
+       INST_ARM64\r
+       dd      0x0e204400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sshll:\r
+       INST_ARM64\r
+       dd      0x0f00a400\r
+       dd      ARM64_vector_scalar_bhs_long_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sshll2:\r
+       INST_ARM64\r
+       dd      0x4f00a400\r
+       dd      ARM64_vector_scalar_bhs_long2_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sshr:\r
+       INST_ARM64\r
+       dd      0x0f000400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ssra:\r
+       INST_ARM64\r
+       dd      0x0f001400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ssubl:\r
+       INST_ARM64\r
+       dd      0x0e202000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ssubl2:\r
+       INST_ARM64\r
+       dd      0x4e202000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ssubw:\r
+       INST_ARM64\r
+       dd      0x0e203000\r
+       dd      ARM64_vector_bhs_three_reg_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ssubw2:\r
+       INST_ARM64\r
+       dd      0x4e203000\r
+       dd      ARM64_vector_bhs_three_reg_wide2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_st1:\r
+       INST_ARM64V\r
+       dd      0x0d800000      ;single\r
+       dd      0x0c802000      ;multiple\r
+       dd      ARM64_ld1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_st2:\r
+       INST_ARM64V\r
+       dd      0x0da00000      ;single\r
+       dd      0x0c800000      ;multiple\r
+       dd      ARM64_ld2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_st3:\r
+       INST_ARM64V\r
+       dd      0x0d802000      ;single\r
+       dd      0x0c800000      ;multiple\r
+       dd      ARM64_ld3\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_st4:\r
+       INST_ARM64V\r
+       dd      0x0da02000      ;single\r
+       dd      0x0c800000      ;multiple\r
+       dd      ARM64_ld4\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_subhn:\r
+       INST_ARM64\r
+       dd      0x0e206000\r
+       dd      ARM64_vector_narrow_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_subhn2:\r
+       INST_ARM64\r
+       dd      0x4e206000\r
+       dd      ARM64_vector_narrow_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_suqadd:\r
+       INST_ARM64\r
+       dd      0x0e203800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sxtl:\r
+       INST_ARM64\r
+       dd      0x0f00a400\r
+       dd      ARM64_vector_scalar_bhs_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_sxtl2:\r
+       INST_ARM64\r
+       dd      0x4f00a400\r
+       dd      ARM64_vector_scalar_bhs_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_tbl:\r
+       INST_ARM64\r
+       dd      0x0e000000\r
+       dd      ARM64_tb1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_tbx:\r
+       INST_ARM64\r
+       dd      0x0e001000\r
+       dd      ARM64_tb1\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_trn1:\r
+       INST_ARM64\r
+       dd      0x0e002800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_trn2:\r
+       INST_ARM64\r
+       dd      0x0e006800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaba:\r
+       INST_ARM64\r
+       dd      0x2e207c00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uabal:\r
+       INST_ARM64\r
+       dd      0x2e205000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uabal2:\r
+       INST_ARM64\r
+       dd      0x6e205000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uabd:\r
+       INST_ARM64\r
+       dd      0x2e207400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uabdl:\r
+       INST_ARM64\r
+       dd      0x2e207000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uabdl2:\r
+       INST_ARM64\r
+       dd      0x6e207000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uadalp:\r
+       INST_ARM64\r
+       dd      0x2e206800\r
+       dd      ARM64_vector_bhs_two_reg_pair\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddl:\r
+       INST_ARM64\r
+       dd      0x2e200000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddl2:\r
+       INST_ARM64\r
+       dd      0x6e200000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddlp:\r
+       INST_ARM64\r
+       dd      0x2e202800\r
+       dd      ARM64_vector_bhs_two_reg_pair\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddlv:\r
+       INST_ARM64\r
+       dd      0x2e303800\r
+       dd      ARM64_scalar_vector_bhs_two_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddw:\r
+       INST_ARM64\r
+       dd      0x2e201000\r
+       dd      ARM64_vector_bhs_three_reg_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uaddw2:\r
+       INST_ARM64\r
+       dd      0x6e201000\r
+       dd      ARM64_vector_bhs_three_reg_wide2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ucvtf:\r
+       INST_ARM64V\r
+       dd      0x7e21d800      ;scalar\r
+       dd      0x2e21d800      ;vector\r
+       dd      ARM64_scalar_vector_sd_convert_zero_u\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uhadd:\r
+       INST_ARM64\r
+       dd      0x2e200400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uhsub:\r
+       INST_ARM64\r
+       dd      0x2e202400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umax:\r
+       INST_ARM64\r
+       dd      0x2e206400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umaxp:\r
+       INST_ARM64\r
+       dd      0x2e20a400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umaxv:\r
+       INST_ARM64\r
+       dd      0x2e30a800\r
+       dd      ARM64_vector_reduce_bhs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umin:\r
+       INST_ARM64\r
+       dd      0x2e206c00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uminp:\r
+       INST_ARM64\r
+       dd      0x2e20ac00\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uminv:\r
+       INST_ARM64\r
+       dd      0x2e31a800\r
+       dd      ARM64_vector_reduce_bhs\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umlal2:\r
+       INST_ARM64V\r
+       dd      0x6e208000      ;vector\r
+       dd      0x6f002000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umlsl:\r
+       INST_ARM64V\r
+       dd      0x2e20a000      ;vector\r
+       dd      0x2f006000      ;element\r
+       dd      ARM64_arithmetic18_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umlsl2:\r
+       INST_ARM64V\r
+       dd      0x6e20a000      ;vector\r
+       dd      0x6f006000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umov:\r
+       INST_ARM64\r
+       dd      0x0e003c00\r
+       dd      ARM64_umov\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_umull2:\r
+       INST_ARM64V\r
+       dd      0x6e20c000      ;vector\r
+       dd      0x6f00a000      ;element\r
+       dd      ARM64_arithmetic18_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqadd:\r
+       INST_ARM64\r
+       dd      0x2e200c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqrshl:\r
+       INST_ARM64\r
+       dd      0x2e205c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqrshrn:\r
+       INST_ARM64\r
+       dd      0x2f009c00\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqrshrn2:\r
+       INST_ARM64\r
+       dd      0x6f009c00\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqshl:\r
+       INST_ARM64V\r
+       dd      0x2e204c00      ;register\r
+       dd      0x2f007400      ;immediate\r
+       dd      ARM64_vector_scalar_bhsd_shift_reg_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqshrn:\r
+       INST_ARM64\r
+       dd      0x2f009400\r
+       dd      ARM64_vector_scalar_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqshrn2:\r
+       INST_ARM64\r
+       dd      0x6f009400\r
+       dd      ARM64_vector_narrow_shift_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqsub:\r
+       INST_ARM64\r
+       dd      0x2e202c00\r
+       dd      ARM64_vector_scalar_bhsd_three_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqxtn:\r
+       INST_ARM64\r
+       dd      0x2e214800\r
+       dd      ARM64_vector_scalar_narrow_extract_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uqxtn2:\r
+       INST_ARM64\r
+       dd      0x6e214800\r
+       dd      ARM64_vector_narrow_extract_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_urecpe:\r
+       INST_ARM64\r
+       dd      0x0ea1c800\r
+       dd      ARM64_arithmetic21\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_urhadd:\r
+       INST_ARM64\r
+       dd      0x2e201400\r
+       dd      ARM64_vector_bhs_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_urshl:\r
+       INST_ARM64\r
+       dd      0x2e205400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_urshr:\r
+       INST_ARM64\r
+       dd      0x2f002400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ursqrte:\r
+       INST_ARM64\r
+       dd      0x2ea1c800\r
+       dd      ARM64_arithmetic21\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ursra:\r
+       INST_ARM64\r
+       dd      0x2f003400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ushl:\r
+       INST_ARM64\r
+       dd      0x2e204400\r
+       dd      ARM64_vector_scalar_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ushll:\r
+       INST_ARM64\r
+       dd      0x2f00a400\r
+       dd      ARM64_vector_scalar_bhs_long_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ushll2:\r
+       INST_ARM64\r
+       dd      0x6f00a400\r
+       dd      ARM64_vector_scalar_bhs_long2_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_ushr:\r
+       INST_ARM64\r
+       dd      0x2f000400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usqadd:\r
+       INST_ARM64\r
+       dd      0x2e203800\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_q\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usra:\r
+       INST_ARM64\r
+       dd      0x2f001400\r
+       dd      ARM64_vector_scalar_bhsd_two_reg_right_imm\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usubl:\r
+       INST_ARM64\r
+       dd      0x2e202000\r
+       dd      ARM64_vector_bhs_three_reg_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usubl2:\r
+       INST_ARM64\r
+       dd      0x6e202000\r
+       dd      ARM64_vector_bhs_three_reg_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usubw:\r
+       INST_ARM64\r
+       dd      0x2e203000\r
+       dd      ARM64_vector_bhs_three_reg_wide\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_usubw2:\r
+       INST_ARM64\r
+       dd      0x6e203000\r
+       dd      ARM64_vector_bhs_three_reg_wide2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uxtl:\r
+       INST_ARM64\r
+       dd      0x2f00a400\r
+       dd      ARM64_vector_scalar_bhs_long\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uxtl2:\r
+       INST_ARM64\r
+       dd      0x6f00a400\r
+       dd      ARM64_vector_scalar_bhs_long2\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uzp1:\r
+       INST_ARM64\r
+       dd      0x0e001800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_uzp2:\r
+       INST_ARM64\r
+       dd      0x0e005800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_xtn:\r
+       INST_ARM64\r
+       dd      0x0e212800\r
+       dd      ARM64_vector_narrow_extract_low\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_xtn2:\r
+       INST_ARM64\r
+       dd      0x4e212800\r
+       dd      ARM64_vector_narrow_extract_high\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_zip1:\r
+       INST_ARM64\r
+       dd      0x0e003800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+ARM_instruction_zip2:\r
+       INST_ARM64\r
+       dd      0x0e007800\r
+       dd      ARM64_vector_bhsd_three_reg\r
+       jmp     ERROR_instruction_not_32bit\r
+\r
+;special\r
+\r
+ARM_instruction_crc32:\r
+       jmp     CRC_32\r
+\r
+ARM_set_virtual:\r
+       call    allocate_structure_data\r
+       mov     al,[IT_anchor_distance]\r
+       mov     ecx,[potential_IT_anchor]\r
+       mov     edx,[explicit_IT_state]\r
+       mov     ebp,[current_IT_block]\r
+       mov     word[ebx],ARM_set_virtual-instruction_handler\r
+       mov     [ebx+2],al\r
+       mov     [ebx+4],ecx\r
+       mov     [ebx+8],edx\r
+       mov     [ebx+12],ebp\r
+       mov     ax,[anchor_instruction]\r
+       mov     [ebx+16],ax\r
+       xor     eax,eax\r
+       mov     [IT_anchor_distance],al\r
+       mov     [potential_IT_anchor],eax\r
+       mov     [explicit_IT_state],eax\r
+       mov     [current_IT_block],eax\r
+       mov     [anchor_instruction],ax\r
+       jmp     instruction_assembled\r
+\r
+ARM_square_parser:\r
+       mov     al,'['\r
+       stosb\r
+    .next:\r
+       lodsb\r
+       test    al,al\r
+       jz      .close\r
+       cmp     al,']'\r
+       jz      .done\r
+       cmp     al,','\r
+       jz      .store\r
+       cmp     al,'#'\r
+       jz      .store\r
+       cmp     al,01ah\r
+       jnz     .expression\r
+       lodsb\r
+       movzx   ecx,al\r
+       push    edi\r
+       mov     edi,symbols\r
+       call    get_symbol\r
+       pop     edi\r
+       jnc     .symbol\r
+       sub     esi,1\r
+    .expression:\r
+       sub     esi,1\r
+       mov     al,'('\r
+       stosb\r
+       push    edi\r
+       call    convert_expression\r
+       pop     eax\r
+       cmp     byte[eax],'!'\r
+       jnz     .converted_okay\r
+       inc     esi\r
+    .converted_okay:\r
+       mov     al,')'\r
+    .store:\r
+       stosb\r
+       jmp     .next\r
+    .symbol:\r
+       stosw\r
+       jmp     .next\r
+    .close:\r
+       dec     esi\r
+    .done:\r
+       stosb\r
+       jmp     argument_parsed\r
+\r
+ARM_curly_parser:\r
+       mov     al,0x91\r
+       stosb\r
+    .next:\r
+       lodsb\r
+       test    al,al\r
+       jz      .close\r
+       cmp     al,'}'\r
+       jz      .done\r
+       cmp     al,','\r
+       jz      .store\r
+       cmp     al,'['\r
+       jz      .store\r
+       cmp     al,']'\r
+       jz      .store\r
+       cmp     al,'-'\r
+       jz      .store\r
+       cmp     al,'#'\r
+       jz      .store\r
+       cmp     al,01ah\r
+       jnz     .expression\r
+       lodsb\r
+       movzx   ecx,al\r
+       push    edi\r
+       mov     edi,symbols\r
+       call    get_symbol\r
+       pop     edi\r
+       jnc     .symbol\r
+       sub     esi,1\r
+    .expression:\r
+       sub     esi,1\r
+       mov     al,'('\r
+       stosb\r
+       push    edi\r
+       call    convert_expression\r
+       pop     eax\r
+       cmp     byte[eax],'!'\r
+       jnz     .converted_okay\r
+       inc     esi\r
+    .converted_okay:\r
+       mov     al,')'\r
+    .store:\r
+       stosb\r
+       jmp     .next\r
+    .symbol:\r
+       stosw\r
+       jmp     .next\r
+    .close:\r
+       dec     esi\r
+       stosb\r
+       jmp     argument_parsed\r
+    .done:\r
+       mov     al,0x92\r
+       stosb\r
+       jmp     argument_parsed\r
+\r
+ARM_calculate_expression:\r
+       xor     eax,eax\r
+       mov     [edi+8],eax\r
+       mov     [edi+12],eax\r
+       push    [error] [error_info] [error_line]\r
+       mov     [error_line],0\r
+       mov     [value_size],0\r
+       cmp     byte[esi],'.'                                   ;float?\r
+       jnz     .size_known\r
+       mov     [value_size],4\r
+    .size_known:\r
+       call    calculate_expression\r
+       mov     ecx,[error_line]\r
+       test    ecx,ecx\r
+       jz      .no_error\r
+       mov     [ARM_error_line],ecx\r
+       pop     ecx\r
+       test    ecx,ecx\r
+       jz      .new_error\r
+       mov     [error_line],ecx\r
+       pop     [error_info] [error]\r
+       stc\r
+       ret\r
+    .new_error:\r
+       pop     ecx ecx\r
+       stc\r
+       ret\r
+    .no_error:\r
+       pop     [error_line] [error_info] [error]\r
+       clc\r
+       ret\r
+\r
+ARM_defer_error:\r
+       mov     ebp,UNENCODEABLE_INSTRUCTION_ARM\r
+       cmp     [error_line],0\r
+       jne     @f\r
+       mov     [error],ecx\r
+       mov     ecx,[current_line]\r
+       mov     [error_line],ecx\r
+    @@:        mov     ecx,[current_line]\r
+       mov     [ARM_error_line],ecx\r
+       ret\r
+\r
+ARM_store_instruction_with_error:\r
+       call    ARM_defer_error\r
+       jmp     ARM_store_instruction.store\r
+ARM_store_instruction:\r
+       cmp     ebp,0xf shl 28\r
+       jb      .unconditional_okay\r
+       mov     ah,[instruction_condition]\r
+       and     ah,0xf0\r
+       cmp     ah,0xe0\r
+       jb      ERROR_instruction_not_conditional\r
+    .unconditional_okay:\r
+       cmp     [explicit_IT_state],0\r
+       jz      .explicit_okay\r
+       mov     cl,byte[explicit_IT_state]              ;get currently specified condition\r
+       mov     ch,[instruction_condition]\r
+       and     cx,0xf0f0\r
+       cmp     ch,cl\r
+       mov     ecx,ERROR_condition_does_not_match_IT_specifier\r
+       jnz     ARM_store_instruction_with_error\r
+    .explicit_okay:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       test    eax,3\r
+       mov     ecx,ERROR_instruction_not_aligned\r
+       jnz     ARM_store_instruction_with_error\r
+    .store:\r
+       shr     [explicit_IT_state],8\r
+       cmp     [error_line],0\r
+       jz      .store_instruction\r
+       mov     ecx,[current_line]\r
+       cmp     [ARM_error_line],ecx\r
+       jnz     .store_instruction\r
+       cmp     [current_pass],1\r
+       jbe     .store_instruction\r
+       cmp     [error],ERROR_immediate_cannot_be_encoded\r
+       jz      .soft_error\r
+       cmp     [error],ERROR_immediate_offset_out_of_range\r
+       jz      .soft_error\r
+       cmp     [error],ERROR_value_out_of_range\r
+       jne     .store_instruction\r
+    .soft_error:\r
+       or      ebp,-1  ;set to this value so that we can use if/else/end if to detect unencodable instructions\r
+    .store_instruction:\r
+       mov     [edi],ebp\r
+       add     edi,4\r
+       jmp     instruction_assembled\r
+\r
+ARM64_store_instruction:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       test    eax,3\r
+       mov     ecx,ERROR_instruction_not_aligned\r
+       jnz     ARM_store_instruction_with_error\r
+    .store:\r
+       cmp     [error_line],0\r
+       jz      .store_instruction\r
+       mov     ecx,[current_line]\r
+       cmp     [ARM_error_line],ecx\r
+       jnz     .store_instruction\r
+       cmp     [current_pass],1\r
+       jbe     .store_instruction\r
+       cmp     [error],ERROR_immediate_cannot_be_encoded\r
+       jz      .soft_error\r
+       cmp     [error],ERROR_immediate_offset_out_of_range\r
+       jz      .soft_error\r
+       cmp     [error],ERROR_value_out_of_range\r
+       jne     .store_instruction\r
+    .soft_error:\r
+       or      ebp,-1  ;set to this value so that we can use if/else/end if to detect unencodable instructions\r
+    .store_instruction:\r
+       mov     [edi],ebp\r
+       add     edi,4\r
+       jmp     instruction_assembled\r
+\r
+;we must supply this function for expressi.inc to assemble\r
+;called by exprcalc.inc during store\r
+get_size_operator:\r
+       xor     ah,ah\r
+       cmp     al,11h\r
+       jne     .no_size_operator\r
+       mov     [size_declared],1\r
+       lods    word[esi]\r
+       xchg    al,ah\r
+       mov     [operand_flags],1\r
+       cmp     ah,[operand_size]\r
+       je      .size_operator_ok\r
+       cmp     [operand_size],0\r
+       jne     operand_sizes_do_not_match\r
+       mov     [operand_size],ah\r
+    .size_operator_ok:\r
+       ret\r
+    .no_size_operator:\r
+       mov     [size_declared],0\r
+       cmp     al,'['\r
+       jne     .size_operator_ok\r
+       mov     [operand_flags],0\r
+       ret\r
+\r
+;we must provide this function for assemble.inc\r
+\r
+segment_prefix = ERROR_illegal_instruction\r
+\r
+;use a custom instruction searcher to convert '~~' to conditionals\r
+\r
+conditional_strings:\r
+       db      'eq',0,0x00\r
+       db      'ne',0,0x10\r
+       db      'cs',0,0x20\r
+       db      'cc',0,0x30\r
+       db      'mi',0,0x40\r
+       db      'pl',0,0x50\r
+       db      'vs',0,0x60\r
+       db      'vc',0,0x70\r
+       db      'hi',0,0x80\r
+       db      'ls',0,0x90\r
+       db      'ge',0,0xa0\r
+       db      'lt',0,0xb0\r
+       db      'gt',0,0xc0\r
+       db      'le',0,0xd0\r
+       db      'al',0,0xe0\r
+       db      'hs',0,0x20\r
+       db      'lo',0,0x30\r
+       db      0\r
+\r
+ARM_get_instruction:\r
+       ;esi=pointer to string\r
+       ;ecx=length of string\r
+       push    esi ecx\r
+       call    ARM_find_instruction\r
+       jnc     .found\r
+       lea     edi,[converted+ecx-2]\r
+    .try_condition:\r
+       cmp     edi,converted\r
+       jbe     .not_found\r
+       mov     ax,[edi]\r
+       mov     esi,conditional_strings\r
+    .next_condition:\r
+       cmp     ax,[esi]\r
+       jz      .condition_matched\r
+       add     esi,4\r
+       cmp     byte[esi],0\r
+       jnz     .next_condition\r
+    .next_position:\r
+       dec     edi\r
+       jmp     .try_condition\r
+    .condition_matched:\r
+       push    dword[edi]\r
+       mov     word[edi],CONDITION_SEARCH_CHARACTER*0x101\r
+       movzx   eax,byte[esi+3]\r
+       push    eax edi\r
+       mov     esi,converted\r
+       call    ARM_find_instruction\r
+       pop     edi edx\r
+       pop     dword[edi]\r
+       jc      .next_position\r
+       or      al,dl\r
+    .found:\r
+       pop     ecx esi\r
+       add     esi,ecx\r
+       clc\r
+       ret\r
+    .not_found:\r
+       pop     ecx esi\r
+       stc\r
+       ret\r
+\r
+ARM_find_instruction:\r
+       push    esi\r
+       mov     ebp,ecx\r
+       mov     byte[characters+CONDITION_SEARCH_CHARACTER],CONDITION_SEARCH_CHARACTER\r
+       call    lower_case\r
+       mov     byte[characters+CONDITION_SEARCH_CHARACTER],0\r
+       mov     ecx,ebp\r
+       cmp     cl,16\r
+       ja      .no_instruction\r
+       sub     cl,1\r
+       jc      .no_instruction\r
+       mov     ebx,[instructions+ecx*8]\r
+       add     ebx,instructions\r
+       mov     edx,[instructions+ecx*8+4]\r
+    .scan_instructions:\r
+       or      edx,edx\r
+       jz      .no_instruction\r
+       mov     eax,edx\r
+       shr     eax,1\r
+       lea     edi,[ebp+3]\r
+       imul    eax,edi\r
+       lea     edi,[ebx+eax]\r
+       mov     esi,converted\r
+       mov     ecx,ebp\r
+       repe    cmps byte [esi],[edi]\r
+       ja      .instructions_up\r
+       jb      .instructions_down\r
+       pop     esi\r
+       add     esi,ebp\r
+       mov     al,[edi]\r
+       mov     bx,[edi+1]\r
+       clc\r
+       ret\r
+    .no_instruction:\r
+       pop     esi\r
+       mov     ecx,ebp\r
+       stc\r
+       ret\r
+    .instructions_down:\r
+       shr     edx,1\r
+       jmp     .scan_instructions\r
+    .instructions_up:\r
+       lea     ebx,[edi+ecx+3]\r
+       shr     edx,1\r
+       adc     edx,-1\r
+       jmp     .scan_instructions\r
+\r
+;custom handler to store address of line start\r
+\r
+virtual\r
+       INST_ARM64\r
+       assert  $-1=$$\r
+       load ARM64_ENCODING byte from $-1\r
+end virtual\r
+virtual\r
+       INST_ARM64S\r
+       assert  $-1=$$\r
+       load ARM64S_ENCODING byte from $-1              ;for instruction that allow setting the flags\r
+end virtual\r
+virtual\r
+       INST_ARM64V\r
+       assert  $-1=$$\r
+       load ARM64V_ENCODING byte from $-1              ;for instruction that allow setting the flags\r
+end virtual\r
+\r
+ARM_instruction_handler:\r
+       movzx   ebx,word[esi]\r
+       mov     al,[esi+2]\r
+       add     esi,3\r
+       mov     [force_wide_flag],esi\r
+       POP     vdx\r
+       add     ebx,edx\r
+       cmp     ebx,ARM_code_generator_start            ;directives and other non-instructions\r
+       jb      .execute\r
+       cmp     byte[ebx],ARM64_ENCODING\r
+       jz      .check_64bit\r
+       cmp     byte[ebx],ARM64S_ENCODING\r
+       jz      .check_64bit\r
+       cmp     byte[ebx],ARM64V_ENCODING\r
+       jz      .check_64bit\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     ERROR_instruction_not_64bit\r
+    .execute:\r
+       jmp     vbx\r
+    .check_64bit:\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     .64bit\r
+       add     ebx,9\r
+       cmp     byte[ebx-9],ARM64V_ENCODING\r
+       jnz     .execute_ARM\r
+       add     ebx,4\r
+    .execute_ARM:\r
+       jmp     vbx\r
+    .64bit:\r
+       cmp     byte[ebx],ARM64S_ENCODING\r
+       jz      .64bit_s\r
+       test    al,FLAG_CONDITION_SET\r
+       jnz     ERROR_cannot_set_flags\r
+       cmp     byte[ebx],ARM64V_ENCODING\r
+       jz      .64bit_v\r
+    .64bit_s:\r
+       mov     ecx,[ebx+1]     ;get instruction template\r
+       mov     edx,ecx\r
+       or      edx,1 shl 29    ;set S\r
+       test    al,FLAG_CONDITION_SET\r
+       cmovnz  ecx,edx\r
+       cmp     al,0xe0\r
+       jb      ERROR_instruction_not_conditional\r
+       mov     ebx,[ebx+5]\r
+       jmp     vbx\r
+    .64bit_v:\r
+       mov     ecx,[ebx+1]     ;get scalar instruction template\r
+       mov     edx,[ebx+5]     ;get vector instruction template\r
+       cmp     al,0xe0\r
+       jb      ERROR_instruction_not_conditional\r
+       mov     ebx,[ebx+9]\r
+       jmp     vbx\r
+\r
+ARM_opcode_swap_table:\r
+       db      (0eh xor 00h)                           ;0 - and --> bic, invert\r
+       db      0                                       ;1 - eor\r
+       db      (04h xor 02h)+0x80                      ;2 - sub --> add, negate\r
+       db      0                                       ;3 - rsb\r
+       db      (02h xor 04h)+0x80                      ;4 - add --> sub, negate\r
+       db      (06h xor 05h)+0x80                      ;5 - adc --> sbc, negate\r
+       db      (05h xor 06h)+0x80                      ;6 - sbc --> adc, negate\r
+       db      0                                       ;7 - rsc\r
+       db      0                                       ;8 - tst\r
+       db      0                                       ;9 - teq\r
+       db      (0bh xor 0ah)+0x80                      ;a - cmp --> cmn, negate\r
+       db      (0ah xor 0bh)+0x80                      ;b - cmn --> cmp, negate\r
+       db      0                                       ;c - orr\r
+       db      (0fh xor 0dh)                           ;d - mov --> mvn, invert\r
+       db      (00h xor 0eh)                           ;e - bic --> and, invert\r
+       db      (0dh xor 0fh)                           ;f - mvn --> mov, invert\r
+\r
+ARM_encode_immediate_with_opcode_swap:\r
+       call    ARM_encode_immediate\r
+       jnc     .done\r
+       mov     eax,[arm_instruction]\r
+       shr     eax,21\r
+       and     eax,0xf\r
+       mov     al,[eax+ARM_opcode_swap_table]\r
+       test    al,al\r
+       jz      .fail\r
+       mov     ecx,[immediate_value]\r
+       not     ecx\r
+       test    al,0x80\r
+       jz      .try\r
+       inc     ecx\r
+       and     eax,0xf\r
+    .try:\r
+       mov     [immediate_value],ecx\r
+       shl     eax,21\r
+       xor     [arm_instruction],eax\r
+       xor     ebp,eax\r
+       call    ARM_encode_immediate\r
+       jnc     .done\r
+    .fail:\r
+       stc\r
+    .done:\r
+       ret\r
+\r
+ARM_encode_immediate:\r
+       mov     eax,[immediate_value]\r
+       xor     ecx,ecx\r
+    .try:\r
+       cmp     eax,0ffh\r
+       jbe     .immediate_ok\r
+       add     ch,1\r
+       rol     eax,2\r
+       cmp     ch,010h\r
+       jb      .try\r
+       stc\r
+       ret\r
+    .immediate_ok:\r
+       or      eax,ecx\r
+       mov     [immediate_value],eax\r
+       clc\r
+       ret\r
+\r
+THUMB_opcode_swap_table:\r
+       db      (01h xor 00h)                           ;0 - and --> bic, invert\r
+       db      (00h xor 01h)                           ;1 - bic --> and, invert\r
+       db      (03h xor 02h)                           ;2 - mov --> mvn, invert, also orr --> orn, invert\r
+       db      (02h xor 03h)                           ;3 - mvn --> mov, invert, also orn --> orr, invert\r
+       db      0                                       ;4 - eor, teq\r
+       db      0                                       ;5 -\r
+       db      0                                       ;6 -\r
+       db      0                                       ;7 -\r
+       db      (0dh xor 08h)+0x80                      ;8 - add --> sub, negate, also cmn --> cmp, negate\r
+       db      0                                       ;9 -\r
+       db      (0bh xor 0ah)+0x80                      ;a - adc --> sbc, negate\r
+       db      (0ah xor 0bh)+0x80                      ;b - sbc --> adc, negate\r
+       db      0                                       ;c -\r
+       db      (08h xor 0dh)+0x80                      ;d - sub --> add, negate, also cmp --> cmn, negate\r
+       db      0                                       ;e - rsb\r
+       db      0                                       ;f -\r
+\r
+THUMB_encode_immediate_with_opcode_swap:\r
+       call    THUMB_encode_immediate\r
+       jnc     .done\r
+       mov     eax,[thumb32_instruction]\r
+       shr     eax,21\r
+       and     eax,0xf\r
+       mov     al,[eax+THUMB_opcode_swap_table]\r
+       test    al,al\r
+       jz      .fail\r
+       mov     ecx,[immediate_value]\r
+       not     ecx\r
+       test    al,0x80\r
+       jz      .try\r
+       inc     ecx\r
+       and     eax,0xf\r
+    .try:\r
+       mov     [immediate_value],ecx\r
+       shl     eax,21\r
+       xor     [thumb32_instruction],eax\r
+       xor     ebp,eax\r
+       call    THUMB_encode_immediate\r
+       jnc     .done\r
+    .fail:\r
+       stc\r
+    .done:\r
+       ret\r
+\r
+THUMB_encode_immediate:\r
+       mov     eax,[immediate_value]\r
+       xor     edx,edx\r
+       bsr     ecx,eax\r
+       jz      .immediate_ok\r
+       sub     ecx,8\r
+       jb      .immediate_ok\r
+       mov     edx,2\r
+       shl     edx,cl\r
+       dec     edx\r
+       test    eax,edx\r
+       jnz     .check_special_combos\r
+       sub     ecx,31\r
+       neg     ecx\r
+       mov     edx,ecx\r
+       shl     edx,7\r
+       rol     eax,cl\r
+       and     eax,0x7f\r
+       jmp     .immediate_ok\r
+    .check_special_combos:\r
+       mov     ecx,eax\r
+       shr     ecx,16\r
+       cmp     ax,cx\r
+       jnz     .fail\r
+       mov     edx,1 shl 8\r
+       cmp     ah,0                                    ;0X0X\r
+       jz      .immediate_ok\r
+       mov     edx,2 shl 8\r
+       xchg    ah,al\r
+       cmp     ah,0                                    ;X0X0\r
+       jz      .immediate_ok\r
+       mov     edx,3 shl 8\r
+       movzx   eax,al\r
+       cmp     ch,cl                                   ;XXXX\r
+       jz      .immediate_ok\r
+    .fail:\r
+       stc\r
+       ret\r
+    .immediate_ok:\r
+       or      eax,edx\r
+       mov     [immediate_value],eax\r
+       clc\r
+       ret\r
+\r
+THUMB_check_12bit_immediate:\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,eax\r
+       neg     ecx\r
+       cmovns  eax,ecx\r
+       test    eax,not 0xfff\r
+       jnz     .fail\r
+    ;check for fit into a modified immediate value\r
+       bsr     ecx,eax\r
+       jz      .fail\r
+       bsf     edx,eax\r
+       sub     ecx,edx\r
+       cmp     ecx,8\r
+       jb      .fail\r
+       clc\r
+       ret\r
+    .fail:\r
+       stc\r
+       ret\r
+\r
+PREDEFINED_LABEL_PROCESSOR     = 4     ;%p\r
+PREDEFINED_LABEL_COPROCESSOR   = 5     ;%c\r
+\r
+ARM_predefined_label:\r
+       or      eax,eax\r
+       jz      current_offset_label\r
+       cmp     eax,1\r
+       je      counter_label\r
+       cmp     eax,2\r
+       je      timestamp_label\r
+       cmp     eax,3\r
+       je      org_origin_label\r
+       cmp     eax,PREDEFINED_LABEL_PROCESSOR\r
+       je      .processor_id\r
+       cmp     eax,PREDEFINED_LABEL_COPROCESSOR\r
+       je      .coprocessor_id\r
+       mov     edx,invalid_value\r
+       jmp     error_undefined\r
+    .processor_id:\r
+       mov     eax,[cpu_capability_flags]\r
+       mov     edx,[cpu_capability_flags2]\r
+       and     eax,CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1)\r
+       and     edx,CPU_CAPABILITY_DEFAULT shr 32\r
+       jmp     make_qword_label_value\r
+    .coprocessor_id:\r
+       mov     eax,[copro_capability_flags]\r
+       and     eax,COPRO_CAPABILITY_DEFAULT\r
+       jmp     make_dword_label_value\r
+\r
+ARM_get_predefined_id:\r
+       cmp     ecx,2\r
+       ja      find_label\r
+       inc     esi\r
+       cmp     cl,1\r
+       je      get_counter_id\r
+       lods    byte [esi]\r
+       mov     ebx,characters\r
+       xlat    [ebx]\r
+       cmp     al,'t'\r
+       je      get_timestamp_id\r
+       cmp     al,'p'\r
+       je      .processor_id\r
+       cmp     al,'c'\r
+       je      .coprocessor_id\r
+       sub     esi,2\r
+       jmp     find_label\r
+    .processor_id:\r
+       mov     eax,PREDEFINED_LABEL_PROCESSOR\r
+       ret\r
+    .coprocessor_id:\r
+       mov     eax,PREDEFINED_LABEL_COPROCESSOR\r
+       ret\r
+\r
+ARM_assemble_line:\r
+       test    [code_type],CPU_ACTIVITY_UNKNOWN\r
+       jz      assemble_line\r
+       jmp     ARM_generic_mode_checks.default\r
+\r
+ARM_generic_mode_checks:\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     .arm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .other\r
+    .arm:\r
+       test    al,FLAG_FORCE_NARROW\r
+       jnz     ERROR_narrow_instructions_are_not_encodable_in_arm_mode\r
+       ret\r
+    .other:\r
+       test    [code_type],CPU_ACTIVITY_UNKNOWN\r
+       jnz     .default\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       ret\r
+    .default:\r
+       mov     [code_type],CPU_ACTIVITY_ARM\r
+       mov     [cpu_capability_flags],CPU_CAPABILITY_DEFAULT and (1 shl 32 - 1)\r
+       mov     [cpu_capability_flags2],CPU_CAPABILITY_DEFAULT shr 32\r
+       mov     [copro_capability_flags],COPRO_CAPABILITY_DEFAULT\r
+       mov     [it_control],IT_MODE_AUTO\r
+       mov     [potential_IT_anchor],0\r
+       mov     [explicit_IT_state],0\r
+       mov     [current_IT_block],0\r
+       jmp     .arm\r
+\r
+ARM_check_shift_range:\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0\r
+       jnz     .shift_not_zero\r
+    ;force to LSL 0\r
+       mov     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       and     ebp,not (3 shl 5)\r
+    .shift_not_zero:\r
+       movzx   ecx,[instruction_shift_op]\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       mov     edx,0x1f00                              ;lsl is 0 to 31\r
+       cmp     ecx,ARM_SHIFT_OPCODE_LSL shl 5\r
+       je      .check_range\r
+       mov     edx,0x2001                              ;lsr & asr are 1 to 32\r
+       cmp     ecx,ARM_SHIFT_OPCODE_LSR shl 5\r
+       je      .check_range\r
+       cmp     ecx,ARM_SHIFT_OPCODE_ASR shl 5\r
+       je      .check_range\r
+       mov     edx,0x1f01                              ;ror is 1 to 31\r
+    .check_range:\r
+       cmp     eax,32\r
+       ja      .shift_out_of_range\r
+       cmp     al,dl\r
+       jb      .shift_out_of_range\r
+       cmp     al,dh\r
+       ja      .shift_out_of_range\r
+       and     eax,0x1f\r
+       shl     eax,7\r
+       or      ebp,eax\r
+       ret\r
+    .shift_out_of_range:\r
+       cmp     edx,0x1f00\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_31\r
+       jz      .defer_error\r
+       cmp     edx,0x2001\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_32\r
+       jz      .defer_error\r
+       cmp     edx,0x1f01\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_31\r
+       jz      .defer_error\r
+       ud2\r
+    .defer_error:\r
+       call    ARM_defer_error\r
+       ret\r
+\r
+       align 4\r
+THUMB_UAL_s_table:\r
+       ;bit=1 instruction needs 's' modifier outside of IT block\r
+       ;bit=0 instruction never uses 's' modifier\r
+       ;everything after 0x4400 never uses 's' modifier\r
+       dd      0xffffffff      ;0000-07ff lsl r,r,i5\r
+       dd      0xffffffff      ;0800-0fff lsr r,r,i5\r
+       dd      0xffffffff      ;1000-17ff asr r,r,i5\r
+       dd      0xffffffff      ;1800-1fff add r,r,r/sub r,r,r/add r,r,i3/sub r,r,i3\r
+       dd      0xffffffff      ;2000-27ff mov r,i8\r
+       dd      0x00000000      ;2800-2fff cmp r,i8\r
+       dd      0xffffffff      ;3000-37ff add r,i8\r
+       dd      0xffffffff      ;3800-3fff sub r,i8\r
+       dw      0xf2ff          ;4000-43ff {and/eor/lsl/lsr/asr/adc/sbc/ror/tst/neg/cmp/cmn/orr/mul/bic/mvn} r,r\r
+\r
+THUMB_do_non_UAL_S_override:\r
+       ;in pre-UAL code a 'OP reg,...' and 'OPs reg,...' are the same and use the 'OPs' form\r
+       ;we can fake this by forcing the S version if the encoding is in range\r
+       cmp     [thumb16_error],0\r
+       jnz     .16bit_okay\r
+       movzx   eax,[thumb16_instruction]\r
+       shr     eax,6\r
+       test    [code_type],CPU_ACTIVITY_THUMB_NON_UAL\r
+       jz      .flag_set_override_done\r
+       cmp     eax,0x4400 shr 6\r
+       jae     .flag_set_override_done\r
+       bt      [THUMB_UAL_s_table],eax\r
+       jnc     .flag_set_override_done\r
+       or      [instruction_condition],FLAG_CONDITION_SET\r
+       ;every thumb32 equivalent instruction except MUL has the 's' in bit 20\r
+       cmp     eax,0x4340 shr 6                        ;MUL?\r
+       jnz     .do_thumb32_s_override\r
+       ;cannot be encoded in thumb32\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       jmp     .flag_set_override_done\r
+    .do_thumb32_s_override:\r
+       or      [thumb32_instruction],1 shl 20\r
+    .flag_set_override_done:\r
+       ;now check the S flag\r
+       cmp     eax,0x4400 shr 6\r
+       jae     .flag_must_be_unset\r
+       bt      [THUMB_UAL_s_table],eax\r
+       jnc     .flag_must_be_unset\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .only_outside\r
+    ;only inside IT\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_INSIDE_IT\r
+       jmp     .16bit_okay\r
+    .only_outside:\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       jmp     .16bit_okay\r
+    .flag_must_be_unset:\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jz      .16bit_okay\r
+    .16bit_unavailable:\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+    .16bit_okay:\r
+       ret\r
+\r
+THUMB_try_place_narrow_with_IT:\r
+       cmp     [thumb16_error],ERROR_instruction_not_16bit\r
+       jz      .unencodable\r
+       call    THUMB_try_place_narrow_without_IT\r
+       jnc     .done\r
+       test    [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       jnz     .fail\r
+       call    THUMB_start_IT_block\r
+    .done:\r
+       ret\r
+    .unencodable:\r
+       mov     ecx,ERROR_instruction_not_16bit\r
+    .fail:\r
+       stc\r
+       ret\r
+\r
+THUMB_try_place_wide_with_IT:\r
+       cmp     [thumb32_error],ERROR_instruction_not_16bit\r
+       jz      .unencodable\r
+       call    THUMB_try_place_wide_without_IT\r
+       jnc     .done\r
+       test    [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       jnz     .fail\r
+       call    THUMB_start_IT_block\r
+    .done:\r
+       ret\r
+    .unencodable:\r
+       mov     ecx,ERROR_instruction_not_16bit\r
+    .fail:\r
+       stc\r
+       ret\r
+\r
+THUMB_try_place_wide_without_IT:\r
+       cmp     [thumb32_error],ERROR_instruction_not_16bit\r
+       jz      .unencodable\r
+       mov     ecx,thumb_flags_32\r
+       jmp     THUMB_try_place_without_IT\r
+    .unencodable:\r
+       mov     ecx,ERROR_instruction_not_16bit\r
+       stc\r
+       ret\r
+\r
+THUMB_try_place_narrow_without_IT:\r
+       cmp     [thumb16_error],ERROR_instruction_not_16bit\r
+       jz      .unencodable\r
+       mov     ecx,thumb_flags_16\r
+       jmp     THUMB_try_place_without_IT\r
+    .unencodable:\r
+       mov     ecx,ERROR_instruction_not_16bit\r
+       stc\r
+       ret\r
+\r
+THUMB_try_place_without_IT:\r
+       ;ecx=flag check address\r
+       mov     al,[instruction_condition]\r
+       and     al,0xf0\r
+       test    byte[ecx],THUMB_FLAG_ONLY_INSIDE_IT\r
+       jnz     .force_inside\r
+       test    byte[ecx],THUMB_FLAG_NOT_INSIDE_IT\r
+       jnz     .force_outside\r
+    ;decide based upon the condition\r
+       cmp     al,0xf0                                 ;unconditional?\r
+       jae     .success\r
+       cmp     al,0xe0\r
+       jb      .force_inside\r
+    ;try inside with AL condition. We try to extend open IT blocks if possible\r
+       test    byte[ecx],THUMB_FLAG_NOT_INSIDE_IT\r
+       jnz     .success                                ;this can happen when an explicit IT block is used\r
+       call    THUMB_extend_IT_block\r
+       clc                                             ;always give success even if the extension failed\r
+       ret\r
+    .force_inside:\r
+       test    byte[ecx],THUMB_FLAG_NOT_INSIDE_IT\r
+       jnz     .fail                                   ;this can happen when an explicit IT block is used\r
+       cmp     [explicit_IT_state],0\r
+       jnz     .success\r
+       call    THUMB_extend_IT_block\r
+       ret\r
+    .force_outside:\r
+       test    [explicit_IT_state],2\r
+       jnz     .success\r
+       cmp     [explicit_IT_state],0\r
+       jnz     .fail\r
+       cmp     al,0xe0                                 ;AL condition?\r
+       jae     .success\r
+       test    byte[ecx],THUMB_FLAG_IS_BCC\r
+       jz      .fail\r
+    .success:\r
+       mov     [current_IT_block],0                    ;since we are not extending the IT block we have to kill it\r
+       clc\r
+       ret\r
+    .fail:\r
+       mov     ecx,ERROR_instruction_not_16bit\r
+       stc\r
+       ret\r
+\r
+THUMB_query_condition_pc:\r
+       mov     ecx,edi\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .done\r
+       mov     ah,[instruction_condition]\r
+       and     ah,0xf0\r
+       cmp     ah,0xe0\r
+       jae     .done\r
+       push    eax ecx\r
+       call    THUMB_query_condition_match\r
+       pop     ecx eax\r
+       setc    dl\r
+       movzx   edx,dl\r
+       lea     ecx,[ecx+edx*2]                         ;adjust for IT block\r
+    .done:\r
+       ret\r
+\r
+THUMB_query_condition_match:\r
+       ;check to see if the current instruction would match or extend an existing IT block\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      .not_match\r
+       cmp     [explicit_IT_state],0\r
+       jnz     .explicit\r
+       mov     eax,[current_IT_block]\r
+       test    eax,eax\r
+       jz      .not_match\r
+       mov     ch,[instruction_condition]\r
+       cmp     ch,0xf0\r
+       jae     .not_match\r
+       mov     cl,[eax]\r
+       mov     edx,ecx\r
+       and     ecx,0xe0e0\r
+       cmp     ch,cl\r
+       jnz     .not_match\r
+    .okay:\r
+       clc\r
+       ret\r
+    .explicit:\r
+       mov     cl,byte[explicit_IT_state]              ;get currently specified condition\r
+       mov     ch,[instruction_condition]\r
+       and     cx,0xf0f0\r
+       cmp     ch,cl\r
+       jz      .okay\r
+    .not_match:\r
+       stc\r
+       ret\r
+\r
+BKPT_force_condition_match:\r
+       ;used by BKPT\r
+       mov     cl,[instruction_condition]\r
+       mov     eax,[explicit_IT_state]\r
+       test    eax,eax\r
+       jnz     .explicit\r
+       mov     eax,[current_IT_block]\r
+       test    eax,eax\r
+       jz      .done\r
+       mov     al,[eax]\r
+    .explicit:\r
+       and     al,0xf0\r
+       and     cl,0x0f\r
+       or      al,cl\r
+       mov     [instruction_condition],al\r
+    .done:\r
+       ret\r
+\r
+THUMB_check_condition:\r
+       mov     al,[instruction_condition]\r
+       and     al,0xf0\r
+       cmp     [explicit_IT_state],0\r
+       jnz     .explicit\r
+    .not_explicit:\r
+       cmp     al,0xe0                                 ;AL condition?\r
+       jz      .okay\r
+       test    [thumb_flags_32],THUMB_FLAG_IS_BCC\r
+       jnz     .okay\r
+       cmp     al,0xf0\r
+       jz      .not_conditional\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       mov     ecx,ERROR_requires_cpu_capability_arm_7m\r
+       jz      .fail\r
+    .inside:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_INSIDE_IT\r
+    .okay:\r
+       clc\r
+       ret\r
+    .not_conditional:\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       jmp     .okay\r
+    .explicit:\r
+       mov     edx,[explicit_IT_state]\r
+       test    edx,2\r
+       jnz     .not_explicit\r
+       cmp     al,0xf0                                 ;AL condition?\r
+       jz      ERROR_instruction_not_conditional\r
+       test    [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       jz      .check_explicit_match\r
+       mov     ecx,ERROR_instruction_must_be_last_in_IT_block\r
+       test    edx,0xffffff00                          ;must be no more conditions\r
+       jnz     .fail\r
+    .check_explicit_match:\r
+       and     dl,0xf0\r
+       cmp     al,dl\r
+       jz      .inside\r
+       mov     ecx,ERROR_condition_does_not_match_IT_specifier\r
+    .fail:\r
+       stc\r
+       ret\r
+\r
+THUMB_start_IT_block:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      .capability\r
+       mov     al,[instruction_condition]\r
+       and     eax,0xf0\r
+       cmp     al,0xf0\r
+       jae     .cannot_start\r
+       cmp     al,0xe0\r
+       jnz     .make_new_IT_here\r
+       call    THUMB_convert_anchor\r
+       jnc     .okay\r
+    .make_new_IT_here:\r
+       mov     [potential_IT_anchor],0\r
+       or      eax,0xbf08\r
+       mov     [current_IT_block],edi\r
+       mov     [edi],ax\r
+       add     edi,2\r
+    .okay:\r
+       clc\r
+       ret\r
+    .cannot_start:\r
+       mov     ecx,ERROR_instruction_not_conditional\r
+       stc\r
+       ret\r
+    .capability:\r
+       mov     ecx,ERROR_requires_cpu_capability_arm_7m\r
+       stc\r
+       ret\r
+\r
+THUMB_convert_anchor:\r
+       test    [it_control],IT_MODE_AUTO\r
+       jz      .cannot_convert\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      .cannot_convert\r
+       mov     al,[instruction_condition]\r
+       and     eax,0xf0\r
+       cmp     al,0xf0\r
+       jae     .cannot_convert\r
+       cmp     al,0xe0\r
+       jnz     .cannot_convert\r
+       mov     cl,[IT_anchor_distance]\r
+       cmp     cl,3\r
+       ja      .cannot_convert\r
+       mov     eax,[potential_IT_anchor]\r
+       test    eax,eax\r
+       jz      .cannot_convert\r
+       mov     dx,[anchor_instruction]\r
+       shl     edx,16\r
+       or      edx,0xbfe0\r
+       mov     ch,0x10\r
+       shr     ch,cl\r
+       movzx   ecx,ch\r
+       or      edx,ecx\r
+       mov     [current_IT_block],eax\r
+       mov     [eax],edx\r
+       mov     [potential_IT_anchor],0\r
+       clc\r
+       ret\r
+    .cannot_convert:\r
+       stc\r
+       ret\r
+\r
+THUMB_extend_IT_block:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      .cannot_extend\r
+       mov     eax,[current_IT_block]\r
+       test    eax,eax\r
+       jz      .cannot_extend\r
+       cmp     [explicit_IT_state],0\r
+       jnz     .okay\r
+       mov     ch,[instruction_condition]\r
+       cmp     ch,0xf0\r
+       jae     .cannot_extend\r
+       mov     cl,[eax]\r
+       mov     edx,ecx\r
+       and     ecx,0xe0e0\r
+       cmp     ch,cl\r
+       jnz     .cannot_extend\r
+       bsf     ecx,edx\r
+       test    ecx,ecx\r
+       jz      .cannot_extend\r
+       shr     dh,4\r
+       and     dh,0x1\r
+       shl     dh,cl\r
+       btr     edx,ecx\r
+       or      dl,dh\r
+       dec     ecx\r
+       bts     edx,ecx\r
+       mov     [eax],dl\r
+    .okay:\r
+       clc\r
+       ret\r
+    .cannot_extend:\r
+       mov     [current_IT_block],0\r
+       stc\r
+       ret\r
+\r
+ARM_post_process_simd_with_error:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     [thumb32_error],ecx\r
+       jmp     THUMB_post_process\r
+\r
+ARM_post_process_simd_convert_table:\r
+       db      0x00    ;f0 ---> invalid\r
+       db      0x00    ;f1 ---> invalid\r
+       db      0xef    ;f2 ---> ef\r
+       db      0xff    ;f3 ---> ff\r
+       db      0xf9    ;f4 ---> f9\r
+       db      0x00    ;f5 ---> invalid\r
+       db      0x00    ;f6 ---> invalid\r
+       db      0x00    ;f7 ---> invalid\r
+       db      0x00    ;f8 ---> invalid\r
+       db      0x00    ;f9 ---> invalid\r
+       db      0x00    ;fa ---> invalid\r
+       db      0x00    ;fb ---> invalid\r
+       db      0x00    ;fc ---> invalid\r
+       db      0x00    ;fd ---> invalid\r
+       db      0xfe    ;fe ---> fe\r
+       db      0x00    ;ff ---> invalid\r
+\r
+ARM_post_process_simd:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction\r
+       mov     [thumb32_error],0\r
+       mov     eax,ebp\r
+       shr     eax,24\r
+       sub     eax,0xf0\r
+       jb      .fatal_error\r
+       movzx   eax,byte[eax+ARM_post_process_simd_convert_table]\r
+       test    eax,eax\r
+       jz      .fatal_error\r
+       shl     eax,24\r
+       and     ebp,not 0xff000000\r
+       or      eax,ebp\r
+       mov     [thumb32_instruction],eax\r
+       jmp     THUMB_post_process\r
+    .fatal_error:\r
+       jmp     ERROR_thumb_recode_error\r
+\r
+ARM_post_process_copro_with_error:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction_with_error\r
+       jmp     ARM_post_process_copro.thumb\r
+\r
+ARM_post_process_copro:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       xor     ecx,ecx\r
+    .thumb:\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],ecx\r
+       cmp     ebp,0xf shl 28                          ;is it a '2' version?\r
+       jae     THUMB_post_process\r
+       and     ebp,not (0xf shl 28)\r
+       or      ebp,0xe shl 28\r
+       mov     [thumb32_instruction],ebp\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_post_process:\r
+       cmp     [thumb16_error],0\r
+       jz      .forced_wide_done\r
+       cmp     [thumb32_error],0\r
+       jnz     .forced_wide_done\r
+       mov     ax,[passes_limit]\r
+       sub     ax,[current_pass]\r
+       cmp     ax,6\r
+       ja      .forced_wide_done\r
+       mov     eax,[force_wide_flag]\r
+       mov     cl,[eax-1]\r
+       and     cl,FLAG_FORCE_AUTO_WIDE\r
+       shr     cl,FLAG_BIT_FORCE_AUTO_WIDE - FLAG_BIT_FORCE_WIDE\r
+       or      cl,FLAG_FORCE_AUTO_WIDE\r
+       or      [eax-1],cl\r
+    .forced_wide_done:\r
+       call    THUMB_do_non_UAL_S_override\r
+       call    THUMB_check_condition\r
+       jc      .fail\r
+       test    [instruction_condition],FLAG_FORCE_NARROW\r
+       jz      .narrow_not_forced\r
+       call    THUMB_try_place_narrow_with_IT\r
+       jnc     .store_narrow\r
+       jmp     .fail\r
+    .narrow_not_forced:\r
+       test    [instruction_condition],FLAG_FORCE_WIDE\r
+       jz      .wide_not_forced\r
+       call    THUMB_try_place_wide_with_IT\r
+       jnc     .store_wide\r
+       jmp     .fail\r
+    .wide_not_forced:\r
+       cmp     [thumb16_error],0\r
+       setz    al\r
+       cmp     [thumb32_error],0\r
+       setz    ah\r
+       xor     al,ah\r
+       jnz     .no_free_choice\r
+       test    ah,ah\r
+       jnz     .free_choice_without_error_copy\r
+       mov     ecx,[thumb32_error]\r
+       cmp     ecx,ERROR_instruction_not_16bit\r
+       jz      .free_choice_without_error_copy\r
+       mov     [thumb16_error],ecx\r
+    .free_choice_without_error_copy:\r
+       call    THUMB_try_place_narrow_without_IT\r
+       jnc     .store_narrow\r
+       call    THUMB_convert_anchor\r
+       jc      .not_converted\r
+       call    THUMB_try_place_narrow_without_IT\r
+       jnc     .store_narrow\r
+    .not_converted:\r
+       call    THUMB_try_place_wide_without_IT\r
+       jnc     .store_wide\r
+       call    THUMB_try_place_narrow_with_IT\r
+       jnc     .store_narrow\r
+       call    THUMB_try_place_wide_with_IT\r
+       jnc     .store_wide\r
+       cmp     ecx,ERROR_instruction_not_16bit\r
+       jnz     .fail\r
+       mov     eax,[thumb32_error]\r
+       test    eax,eax\r
+       cmovnz  ecx,eax\r
+       jmp     .fail\r
+    .no_free_choice:\r
+       test    ah,ah\r
+       jz      .not_prefer_wide\r
+       call    THUMB_try_place_wide_with_IT\r
+       jnc     .store_wide\r
+       jmp     .fail\r
+    .not_prefer_wide:\r
+       call    THUMB_try_place_narrow_with_IT\r
+       jnc     .store_narrow\r
+       jmp     .fail\r
+    .store_narrow:\r
+       mov     ecx,[thumb16_error]\r
+       movzx   ebp,[thumb16_instruction]\r
+       test    ecx,ecx\r
+       jnz     THUMB_store_instruction_16_with_error\r
+       jmp     THUMB_store_instruction_16\r
+    .store_wide:\r
+       mov     ecx,[thumb32_error]\r
+       mov     ebp,[thumb32_instruction]\r
+       test    ecx,ecx\r
+       jnz     THUMB_store_instruction_32_with_error\r
+       jmp     THUMB_store_instruction_32\r
+    .fail:\r
+;      jmp     THUMB_store_instruction_16_with_error\r
+\r
+THUMB_store_instruction_16_with_error:\r
+       call    ARM_defer_error\r
+       jmp     THUMB_store_instruction_16.store\r
+THUMB_store_instruction_16:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       test    eax,1\r
+       mov     ecx,ERROR_instruction_not_aligned\r
+       jnz     THUMB_store_instruction_16_with_error\r
+    .store:\r
+       mov     [edi],bp\r
+       mov     ebp,2\r
+       jmp     THUMB_finalise_instruction\r
+\r
+THUMB_store_instruction_32_with_error:\r
+       call    ARM_defer_error\r
+       jmp     THUMB_store_instruction_32.store\r
+THUMB_store_instruction_32:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       sub     eax,edi\r
+       neg     eax\r
+       test    eax,1\r
+       mov     ecx,ERROR_instruction_not_aligned\r
+       jnz     THUMB_store_instruction_32_with_error\r
+    .store:\r
+       ror     ebp,16                                  ;swap the hword endian\r
+       mov     [edi],ebp\r
+       mov     ebp,4\r
+       jmp     THUMB_finalise_instruction\r
+\r
+THUMB_finalise_instruction:\r
+       mov     al,[IT_anchor_distance]\r
+       add     al,1\r
+       sbb     al,0\r
+       mov     [IT_anchor_distance],al\r
+       add     edi,ebp\r
+       mov     ecx,[explicit_IT_state]\r
+       btr     [explicit_IT_state],1\r
+       jc      .explicit_beginning\r
+       shr     [explicit_IT_state],8\r
+    .explicit_beginning:\r
+       test    ecx,ecx\r
+       jnz     instruction_assembled\r
+       mov     eax,[current_IT_block]\r
+       test    eax,eax\r
+       jz      .check_potential_IT_anchor\r
+       test    [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       jnz     .kill_implicit_IT_block\r
+       test    byte[eax],1                             ;end of condition?\r
+       jz      instruction_assembled\r
+    .kill_implicit_IT_block:\r
+       mov     [current_IT_block],0\r
+       jmp     instruction_assembled\r
+    .check_potential_IT_anchor:\r
+       cmp     [instruction_condition],0xe0\r
+       jb      .kill_potential_anchor\r
+       cmp     [instruction_condition],0xf0\r
+       jae     .kill_potential_anchor\r
+       cmp     ebp,4\r
+       jnz     .check_potential_anchor_extension\r
+       cmp     [thumb16_error],0\r
+       jnz     .check_potential_anchor_extension\r
+       test    [instruction_condition],FLAG_CONDITION_SET + FLAG_FORCE_WIDE\r
+       jnz     .check_potential_anchor_extension\r
+       lea     eax,[edi-4]                             ;make a new anchor\r
+       mov     cx,[thumb16_instruction]\r
+       mov     [IT_anchor_distance],1\r
+       mov     [potential_IT_anchor],eax\r
+       mov     [anchor_instruction],cx\r
+       jmp     instruction_assembled\r
+    .check_potential_anchor_extension:\r
+       cmp     [potential_IT_anchor],0\r
+       jz      instruction_assembled\r
+       cmp     ebp,2\r
+       jnz     .check_potential_anchor_extension_32\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .kill_potential_anchor\r
+    .check_potential_anchor_extension_32:\r
+       test    [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_ONLY_LAST_IT + THUMB_FLAG_IS_BCC\r
+       jnz     .kill_potential_anchor\r
+       cmp     [IT_anchor_distance],4\r
+       jbe     instruction_assembled                   ;anchor extention is okay\r
+    .kill_potential_anchor:\r
+       mov     [potential_IT_anchor],0\r
+       jmp     instruction_assembled\r
+\r
+ARM_define_label:\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_label_inside_IT_block\r
+       mov     [current_IT_block],0\r
+       mov     [potential_IT_anchor],0\r
+       jmp     define_label\r
+\r
+ARM_end_virtual:\r
+       call    find_structure_data\r
+       jc      .ret\r
+       sub     ebx,0x18\r
+       mov     al,[ebx+2]\r
+       mov     ecx,[ebx+4]\r
+       mov     edx,[ebx+8]\r
+       mov     ebp,[ebx+12]\r
+       mov     [IT_anchor_distance],al\r
+       mov     [potential_IT_anchor],ecx\r
+       mov     [explicit_IT_state],edx\r
+       mov     [current_IT_block],ebp\r
+       mov     ax,[ebx+16]\r
+       mov     [anchor_instruction],ax\r
+       call    remove_structure_data\r
+       add     ebx,0x18\r
+    .ret:\r
+       ret\r
+\r
+ARM_fit_operator:\r
+       POP     vdx\r
+       je      calculate_not\r
+       cmp     al,0D1h                                 ;FIT?\r
+       je      .calculate_fit\r
+       jmp     vdx\r
+    .calculate_fit:\r
+       cmp     word [edi+8],0\r
+       jne     invalid_expression\r
+       cmp     byte [edi+12],0\r
+       je      .fit_ok\r
+       cmp     [error_line],0\r
+       jne     .fit_ok\r
+       mov     eax,[current_line]\r
+       mov     [error_line],eax\r
+       mov     [error],invalid_use_of_symbol\r
+    .fit_ok:\r
+       xor     ebx,ebx\r
+       test    [code_type],CPU_ACTIVITY_ARM64\r
+       jnz     .fit_mask_test64\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       test    edx,edx\r
+       jz      .fit_test\r
+       cdq\r
+       cmp     edx,[edi+4]\r
+       jnz     .fit_done\r
+    .fit_test:\r
+       push    [immediate_value]\r
+       mov     ebp,ARM_encode_immediate\r
+       mov     edx,THUMB_encode_immediate\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       cmovz   ebp,edx\r
+       mov     [immediate_value],eax\r
+       call    vbp\r
+       setnc   bl                                      ;bit-0 = can fit normal\r
+       mov     eax,1 shl CPU32_CAPABILITY_T2\r
+       mov     ecx,1 shl CPU32_CAPABILITY_7M\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       cmovz   eax,ecx\r
+       test    [cpu_capability_flags],eax\r
+       jz      .movw_done\r
+       cmp     [immediate_value],1 shl 16\r
+       setb    cl\r
+       shl     cl,3\r
+       or      bl,cl                                   ;bit-3 = can fit movw\r
+    .movw_done:\r
+       mov     eax,[edi]\r
+       not     eax\r
+       mov     [immediate_value],eax\r
+       call    vbp\r
+       setnc   cl\r
+       shl     cl,1\r
+       or      bl,cl                                   ;bit-1 = can fit inverted\r
+       mov     eax,[edi]\r
+       neg     eax\r
+       mov     [immediate_value],eax\r
+       call    vbp\r
+       setnc   cl\r
+       shl     cl,2\r
+       or      bl,cl                                   ;bit-2 = can fit negated\r
+       pop     [immediate_value]\r
+    .fit_done:\r
+       mov     [edi],ebx                               ;set low dword\r
+       mov     dword[edi+4],0                          ;set high dword\r
+       mov     byte[edi+13],0                          ;set sign\r
+       add     edi,14h\r
+       jmp     calculation_loop\r
+    .fit_mask_test64:\r
+       push    [immediate_value]\r
+       push    [immediate_value_high]\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       mov     [immediate_value],eax\r
+       mov     [immediate_value_high],edx\r
+       push    ebx\r
+       call    ARM64_encode_bitmask\r
+       pop     ebx\r
+       setnc   bl                                      ;bit-0 = can fit in 64 bit mask\r
+       mov     eax,[edi]\r
+       mov     edx,[edi+4]\r
+       test    edx,edx\r
+       jz      .fit_mask_test32\r
+       cdq\r
+       cmp     edx,[edi+4]\r
+       jnz     .fit_mask_done\r
+    .fit_mask_test32:\r
+       mov     [immediate_value],eax\r
+       mov     [immediate_value_high],eax\r
+       push    ebx\r
+       call    ARM64_encode_bitmask\r
+       pop     ebx\r
+       setnc   cl\r
+       shl     cl,1\r
+       or      bl,cl                                   ;bit-1 = can fit in 32 bit mask\r
+    .fit_mask_done:\r
+       pop     [immediate_value_high]\r
+       pop     [immediate_value]\r
+       jmp     .fit_done\r
+\r
+ARM_processor_directives:\r
+       ;called during parsing\r
+       cmp     bx,ARM_processor_directive-instruction_handler\r
+       jz      .enable_cpu_selection_symbols\r
+       cmp     bx,ARM_coprocessor_directive-instruction_handler\r
+       jnz     .done\r
+    .enable_cpu_selection_symbols:\r
+       mov     [decorator_symbols_allowed],1\r
+    .done:\r
+       ret\r
+\r
+ARM_parse_processor_separators:\r
+       ;called during parsing\r
+       cmp     al,'-'\r
+       je      separator\r
+       cmp     al,'+'\r
+       je      separator\r
+       jmp     not_a_separator\r
+\r
+ARM_check_operator:\r
+       ;called during parsing\r
+       cmp     al,8Fh                          ;processor?\r
+       je      .get_symbol\r
+       cmp     al,8Eh                          ;coprocessor?\r
+       jne     argument_parsed\r
+    .get_symbol:\r
+       mov     [decorator_symbols_allowed],1\r
+       inc     esi\r
+       movzx   ecx,byte [esi]\r
+       inc     esi\r
+       push    edi\r
+       call    get_symbol\r
+       pop     edi\r
+       mov     [decorator_symbols_allowed],0\r
+       lea     esi,[esi-2]\r
+       jc      argument_parsed\r
+       add     esi,2\r
+       stosw\r
+       jmp     argument_parsed\r
+\r
+ARM_check_processor:\r
+       ;called during assembly\r
+       je      .used\r
+       cmp     al,8Fh\r
+       je      .processor\r
+       cmp     al,8Eh\r
+       je      .coprocessor\r
+       ret\r
+    .used:\r
+       add     esp,4 + __is_64 * 4\r
+       jmp     check_for_used\r
+    .processor:\r
+       add     esp,4 + __is_64 * 4\r
+       inc     esi\r
+       lodsw\r
+       xchg    ah,al\r
+       cmp     ax,cpu_sel\r
+       jb      ERROR_expecting_CPU_selection_symbol\r
+       cmp     ax,cpu_sel + cpu_sel.size\r
+       jae     ERROR_expecting_CPU_selection_symbol\r
+       sub     ax,cpu_sel\r
+       mov     ecx,[cpu_capability_flags]\r
+       mov     ebx,[cpu_capability_flags2]\r
+       jmp     .symbol_okay\r
+    .coprocessor:\r
+       add     esp,4 + __is_64 * 4\r
+       inc     esi\r
+       lodsw\r
+       xchg    ah,al\r
+       cmp     ax,copro_sel\r
+       jb      ERROR_expecting_COPRO_selection_symbol\r
+       cmp     ax,copro_sel + copro_sel.size\r
+       jae     ERROR_expecting_COPRO_selection_symbol\r
+       sub     ax,copro_sel\r
+       mov     ecx,[copro_capability_flags]\r
+       xor     ebx,ebx\r
+    .symbol_okay:\r
+       cmp     ax,32\r
+       cmovae  ecx,ebx\r
+       bt      ecx,eax\r
+       jc      return_true\r
+       jmp     return_false\r
+\r
+;V1\r
+\r
+ARM_rd_rn_shifter:\r
+       ;used by ADC, ADD, AND, BIC, EOR, ORR, RSB, RSC, SBC, SUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                              ; 0=reg,imm             alternate for reg,reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                         ; 1=reg,byte,rot        alternate for reg,reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                         ; 2=reg,reg             alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                             ; 3=reg,reg,rrx         alternate for reg,reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\                  ; 4=reg,reg,shift imm   alternate for reg,reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\             ; 5=reg,reg,shift reg   alternate for reg,reg,reg,shift reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\                                ; 6=reg,reg,imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\           ; 7=reg,reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\                           ; 8=reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\               ; 9=reg,reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\    ;10=reg,reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;11=reg,reg,reg,shift reg\r
+       movzx   eax,al\r
+       mov     ecx,eax\r
+       shl     ecx,24\r
+       or      eax,ecx\r
+       cmp     al,6\r
+       jae     .encode_instruction\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+    .encode_shifter:\r
+       ;used by ADC, ADD, AND, BIC, EOR, ORR, RSB (NEG), RSC, SBC, SUB\r
+       ;used by MOV (LSL, LSR, ASR, ROR, RRX), MVN, CMN, CMP, TEQ, TST\r
+       add     al,6\r
+    .encode_instruction:\r
+       ;used by ADR, MOV reg,exp\r
+       cmp     [operand_register0],0xf\r
+       jnz     .pc_check_done\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+    .pc_check_done:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_rd_rn_shifter\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+    .encode:\r
+       ;used by CMNP, CMPP, TEQP, TSTP\r
+       cmp     al,6\r
+       jz      .reg_reg_imm\r
+       cmp     al,7\r
+       jz      .reg_reg_byte_rot\r
+       cmp     al,8\r
+       jz      .reg_reg_reg\r
+       cmp     al,9\r
+       jz      .reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      .reg_reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      .reg_reg_reg_shift_reg\r
+       ud2\r
+    .reg_reg_byte_rot:\r
+       cmp     [immediate_value],0xff\r
+       ja      .byte_out_of_range\r
+       test    [immediate_value2],not (0xf shl 1)\r
+       jnz     .rotation_out_of_range\r
+       mov     eax,[immediate_value2]\r
+       shl     eax,8-1\r
+       or      [immediate_value],eax\r
+       jmp     .reg_reg_imm_make\r
+    .reg_reg_imm:\r
+       call    ARM_encode_immediate_with_opcode_swap\r
+       jc      .immediate_out_of_range\r
+    .reg_reg_imm_make:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       or      ebp,eax\r
+       bts     ebp,25\r
+       jmp     ARM_store_instruction\r
+    .reg_reg_reg_shift_imm:\r
+       call    ARM_check_shift_range\r
+    .reg_reg_reg:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .reg_reg_reg_shift_reg:\r
+       movzx   eax,[operand_register0]\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       or      ebp,eax\r
+       movzx   eax,[instruction_shift_op]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       bts     ebp,4\r
+       jmp     ARM_store_instruction\r
+    .reg_reg_reg_rrx:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       or      ebp,eax\r
+       or      ebp,ARM_SHIFT_OPCODE_ROR shl 5\r
+       jmp     ARM_store_instruction\r
+    .immediate_out_of_range:\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jmp     ARM_store_instruction_with_error\r
+    .byte_out_of_range:\r
+       mov     ecx,ERROR_byte_value_out_of_range\r
+       jmp     ARM_store_instruction_with_error\r
+    .rotation_out_of_range:\r
+       mov     ecx,ERROR_rotation_value_out_of_range\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM_rd_shifter:\r
+       ;used by MVN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                      ;0=reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                 ;1=reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                 ;2=reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                     ;3=reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\          ;4=reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>       ;5=reg,reg,shift reg\r
+    .encode:\r
+       cmp     al,0\r
+       jnz     .do\r
+       mov     ecx,[immediate_value]\r
+       cmp     ecx,0xffff\r
+       ja      .do\r
+       test    ebp,1 shl 22                            ;1=mvn\r
+       jnz     .do\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .do\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB\r
+       push    eax ecx\r
+       call    ARM_encode_immediate\r
+       pop     [immediate_value] eax\r
+       jnc     .do\r
+       and     ebp,0xf shl 28\r
+       or      ebp,0x03000000                          ;switch to movw\r
+       jmp     ARM_rd_imm16.do                         ;do movw\r
+    .THUMB:\r
+       push    eax [immediate_value]\r
+       call    THUMB_encode_immediate\r
+       pop     [immediate_value] eax\r
+       jnc     .do\r
+       mov     [thumb32_instruction],0xf2400000        ;switch to movw\r
+       jmp     ARM_rd_imm16.do                         ;do movw\r
+    .do:\r
+       ;used by CPY\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       mov     dh,0\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+       jmp     ARM_rd_rn_shifter.encode_shifter\r
+\r
+ARM_rd_shifter_exp:\r
+       ;used by MOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                      ;0=reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                 ;1=reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                 ;2=reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                     ;3=reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\          ;4=reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\     ;5=reg,reg,shift reg\r
+       <TMPL_base_reg,TMPL_expression>                                 ;6=reg,exp      converted to add reg,reg,imm\r
+       cmp     al,6\r
+       jb      ARM_rd_shifter.encode\r
+       xor     ebp,(ARM_INSTRUCTION_OPCODE_MOV xor ARM_INSTRUCTION_OPCODE_ADD) shl 21\r
+       xor     [arm_instruction],(ARM_INSTRUCTION_OPCODE_MOV xor ARM_INSTRUCTION_OPCODE_ADD) shl 21\r
+       xor     [thumb32_instruction],(0x2 shl 21 + 0xf shl 16) xor (0x8 shl 21)\r
+       jmp     ARM_rd_rn_shifter.encode_instruction\r
+\r
+ARM_rd_rn_shift:\r
+       ;used by LSL, LSR, ASR, ROR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                      ;0=reg,imm      alternate for reg,reg,imm\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;1=reg,reg      alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\        ;2=reg,reg,imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;3=reg,reg,reg\r
+       mov     ecx,ebp\r
+       shr     ecx,5\r
+       and     ecx,3\r
+       mov     [instruction_shift_op],cl\r
+       ;make the thumb32 opcode\r
+       test    al,1\r
+       jz      .reg_reg_imm\r
+       ;for reg,reg,reg\r
+       shl     ecx,21\r
+       or      ecx,0xfa00f000\r
+       mov     [thumb32_instruction],ecx\r
+       jmp     .thumb32_done\r
+    .reg_reg_imm:\r
+       shl     ecx,4\r
+       or      ecx,0xea4f0000\r
+       mov     [thumb32_instruction],ecx\r
+    .thumb32_done:\r
+       cmp     al,2\r
+       jae     .registers_shifted\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+       add     al,2\r
+    .registers_shifted:\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       mov     dh,0\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+       add     al,2\r
+       jmp     ARM_rd_rn_shifter.encode_shifter\r
+\r
+ARM_rd_shift:\r
+       ;used by RRX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>,\                               ;0=reg          alternate for reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;1=reg,reg\r
+       mov     [instruction_shift_op],ARM_SHIFT_OPCODE_ROR\r
+       cmp     al,1\r
+       jae     .registers_shifted\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+    .registers_shifted:\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       mov     dh,0\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+       mov     al,3\r
+       jmp     ARM_rd_rn_shifter.encode_shifter\r
+\r
+ARM_rn_shifter:\r
+       ;used by CMN, CMP, TEQ, TST\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                      ;0=reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                 ;1=reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                 ;2=reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                     ;3=reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\          ;4=reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>       ;5=reg,reg,shift reg\r
+       mov     edx,[operand_registers]\r
+       shl     edx,8\r
+       mov     [operand_registers],edx\r
+       jmp     ARM_rd_rn_shifter.encode_shifter\r
+\r
+ARM_rn_shifter_26bit:\r
+       ;used by CMNP, CMPP, TEQP, TSTP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                      ;0=reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                 ;1=reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                 ;2=reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                     ;3=reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\          ;4=reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>       ;5=reg,reg,shift reg\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ERROR_instruction_not_16bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_26BIT\r
+       jz      ERROR_requires_cpu_capability_arm_26bit\r
+       mov     edx,[operand_registers]\r
+       shl     edx,8\r
+       mov     [operand_registers],edx\r
+       add     al,6\r
+       jmp     ARM_rd_rn_shifter.encode\r
+\r
+ARM_rd_address2:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_rd_address\r
+       ;used by LDR, LDRB, STR, STRB, selectively: PLD, LDRT, LDRBT, STRT, STRBT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                                                    ; 0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                                                   ; 1=rd,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\                            ; 2=rd,[rn],+-rm,shift imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_rrx_op>,\                                       ; 3=rd,[rn],+-rm,rrx\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                                           ; 4=rd,[rn],imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                                           ; 5=rd,[rn,imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\                                     ; 6=rd,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                                                   ; 7=rd,[rn,+-rm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\                             ; 8=rd,[rn,+-rm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\                            ; 9=rd,[rn,+-rm,shift imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\      ;10=rd,[rn,+-rm,shift imm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right>,\                                       ;11=rd,[rn,+-rm,rrx]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right,TMPL_modifier_exclaim>,\                 ;12=rd,[rn,+-rm,rrx]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                                                     ;13=rd,[imm]    PC relative\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                                                  ;14=rd,[exp]    implicit reg from structure\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                                              ;15=rd,[exp]!   implicit reg from structure\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+    ;check that rd!=15 unless LDR, STR\r
+       cmp     [operand_size],4\r
+       jnz     .check_rd\r
+    ;check for LDRT\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21\r
+       cmp     edx,1 shl 21\r
+       jnz     .process\r
+    .check_rd:\r
+       mov     cl,[operand_register0]\r
+       cmp     cl,15\r
+       jz      ERROR_r15_not_valid.first\r
+    .process:\r
+       cmp     al,0\r
+       jz      .rd_q_rn_p\r
+       cmp     al,1\r
+       jz      .rd_q_rn_p_PMrm\r
+       cmp     al,2\r
+       jz      .rd_q_rn_p_PMrm_shift_imm\r
+       cmp     al,3\r
+       jz      .rd_q_rn_p_PMrm_rrx\r
+       cmp     al,4\r
+       jz      .rd_q_rn_p_imm\r
+       cmp     al,5\r
+       jz      .rd_q_rn_imm_p\r
+       cmp     al,6\r
+       jz      .rd_q_rn_imm_p!\r
+       cmp     al,7\r
+       jz      .rd_q_rn_PMrm_p\r
+       cmp     al,8\r
+       jz      .rd_q_rn_PMrm_p!\r
+       cmp     al,9\r
+       jz      .rd_q_rn_PMrm_shift_imm_p\r
+       cmp     al,10\r
+       jz      .rd_q_rn_PMrm_shift_imm_p!\r
+       cmp     al,11\r
+       jz      .rd_q_rn_PMrm_rrx_p\r
+       cmp     al,12\r
+       jz      .rd_q_rn_PMrm_rrx_p!\r
+       cmp     al,13\r
+       jz      .rd_q_imm_p\r
+       cmp     al,14\r
+       jz      .rd_q_exp_p\r
+       cmp     al,15\r
+       jz      .rd_q_exp_p!\r
+       ud2\r
+    .rd_q_rn_p_imm:\r
+       cmp     [immediate_value],0\r
+       jz      .rd_q_rn_p\r
+    .rd_q_rn_p_imm.do:\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       jmp     .rd_rn_imm\r
+    .rd_q_rn_imm_p!:\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax\r
+       jz      .rd_q_rn_imm_p\r
+       xor     ebp,1 shl 21 + 1 shl 24\r
+       jmp     .rd_rn_imm\r
+    .rd_q_rn_p:\r
+    .rd_q_rn_imm_p:\r
+       xor     ebp,1 shl 24\r
+    .rd_rn_imm:\r
+       or      ebp,1 shl 23\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xfff\r
+       jg      .immediate_offset_out_of_range\r
+       cmp     eax,-0xfff\r
+       jl      .immediate_offset_out_of_range\r
+       test    eax,eax\r
+       jns     .store_offset\r
+       neg     eax\r
+       btr     ebp,23\r
+    .store_offset:\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .rd_q_rn_PMrm_p!:\r
+       mov     [instruction_shift_op],0\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       jmp     .rd_q_rn_PMrm_shift_imm_p!\r
+    .rd_q_rn_p_PMrm:\r
+       mov     [instruction_shift_op],0\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       jmp     .rd_q_rn_p_PMrm_shift_imm\r
+    .rd_q_rn_PMrm_p:\r
+       mov     [instruction_shift_op],0\r
+       jmp     .rd_q_rn_PMrm_shift_imm_p\r
+    .rd_q_rn_PMrm_shift_imm_p!:\r
+       call    ARM_check_shift_range\r
+       xor     ebp,1 shl 21 + 1 shl 24\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       jmp     .check_rn_rm\r
+    .rd_q_rn_p_PMrm_shift_imm:\r
+       call    ARM_check_shift_range\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+    .check_rn_rm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jnz     .rd_rn_PMrm_shift_imm\r
+       mov     ax,word[operand_register1]\r
+       and     ax,0x7f7f\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_offset_must_differ_with_writeback\r
+       jmp     .rd_rn_PMrm_shift_imm\r
+    .rd_q_rn_PMrm_shift_imm_p:\r
+       call    ARM_check_shift_range\r
+       xor     ebp,1 shl 24\r
+    .rd_rn_PMrm_shift_imm:\r
+       or      ebp,1 shl 23 + 1 shl 25\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       test    al,al\r
+       jns     .store_reg\r
+       and     eax,0xf\r
+       btr     ebp,23\r
+    .store_reg:\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .rd_q_rn_PMrm_rrx_p!:\r
+       xor     ebp,1 shl 21 + 1 shl 24 + 3 shl 5\r
+       jmp     .rd_q_rn_p_PMrm_rrx.do\r
+    .rd_q_rn_p_PMrm_rrx:\r
+       or      ebp,3 shl 5\r
+    .rd_q_rn_p_PMrm_rrx.do:\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       mov     ax,word[operand_register0]\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jnz     .rd_rn_PMrm_shift_imm\r
+       mov     ax,word[operand_register1]\r
+       and     ax,0x7f7f\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_offset_must_differ_with_writeback\r
+       jmp     .rd_rn_PMrm_shift_imm\r
+    .rd_q_rn_PMrm_rrx_p:\r
+       xor     ebp,1 shl 24 + 3 shl 5\r
+       jmp     .rd_rn_PMrm_shift_imm\r
+    .rd_q_imm_p:\r
+       mov     [operand_register1],0xf\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       add     eax,[immediate_value]\r
+       sub     eax,edi\r
+       sub     eax,8\r
+       mov     [immediate_value],eax\r
+       jmp     .rd_q_rn_imm_p\r
+    .rd_q_exp_p:\r
+       jmp     .rd_q_rn_imm_p\r
+    .rd_q_exp_p!:\r
+       jmp     .rd_q_rn_imm_p!\r
+    .immediate_offset_out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0xfff\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM_rd_address2_post:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_rd_address\r
+       ;used by LDRT, LDRBT, STRT, STRBT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                            ;0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                           ;1=rd,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\    ;2=rd,[rn],+-rm,shift imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_rrx_op>,\               ;3=rd,[rn],+-rm,rrx\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>                                     ;4=rd,[rn],imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       cmp     [operand_register0],15\r
+       jz      ERROR_r15_not_valid.first\r
+       cmp     al,0\r
+       jz      ARM_rd_address2.rd_q_rn_p_imm.do\r
+       cmp     al,1\r
+       jz      ARM_rd_address2.rd_q_rn_p_PMrm\r
+       cmp     al,2\r
+       jz      ARM_rd_address2.rd_q_rn_p_PMrm_shift_imm\r
+       cmp     al,3\r
+       jz      ARM_rd_address2.rd_q_rn_p_PMrm_rrx\r
+       cmp     al,4\r
+       jz      ARM_rd_address2.rd_q_rn_p_imm.do\r
+       ud2\r
+\r
+ARM_rn_address4:\r
+       ;used by LDM, STM\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_reg_list>,\                         ;0=rn,{..}\r
+       <TMPL_base_reg,TMPL_reg_list,TMPL_modifier_translate>,\ ;1=rn,{..}^\r
+       <TMPL_base_reg!,TMPL_reg_list>,\                        ;2=rn!,{..}\r
+       <TMPL_base_reg!,TMPL_reg_list,TMPL_modifier_translate>  ;3=rn!,{..}^\r
+       mov     [operand_size],4\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_rn_address4\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       test    al,1\r
+       jnz     .do_multiple                            ;cannot change to ldr when using translate\r
+    .do:\r
+       mov     ecx,[reg_list_bitmap]\r
+       dec     ecx\r
+       and     ecx,[reg_list_bitmap]\r
+       jz      .do_single                              ;single registers use a different encoding\r
+    .do_multiple:\r
+       cmp     al,0\r
+       jz      .rn_list\r
+       cmp     al,1\r
+       jz      .rn_list_t\r
+       cmp     al,2\r
+       jz      .rn!_list\r
+       cmp     al,3\r
+       jz      .rn!_list_t\r
+       ud2\r
+    .rn_list:\r
+       mov     ecx,0\r
+       jmp     .make\r
+    .rn_list_t:\r
+       mov     ecx,1 shl 22\r
+       jmp     .make\r
+    .rn!_list:\r
+       mov     ecx,1 shl 21\r
+       jmp     .make\r
+    .rn!_list_t:\r
+       test    [reg_list_bitmap],1 shl 15              ;if PC is not present then we can't use writeback\r
+       jz      ERROR_register_writeback_not_allowed\r
+       mov     ecx,1 shl 22 + 1 shl 21\r
+    .make:\r
+       or      ebp,ecx\r
+       or      ebp,[reg_list_bitmap]\r
+       movzx   ecx,[operand_register0]\r
+       bt      ebp,21\r
+       jnc     .dest_okay\r
+       bt      ebp,20\r
+       jc      .ldm_check\r
+    ;stm check\r
+       bt      ebp,22                                  ;translate?\r
+       jnc     .writeback_okay\r
+       bt      ebp,21                                  ;writeback?\r
+       jc      ERROR_register_writeback_not_allowed\r
+    .writeback_okay:\r
+       bsf     edx,ebp\r
+       cmp     edx,ecx\r
+       jz      .dest_okay\r
+    .ldm_check:\r
+       bt      ebp,ecx\r
+       jc      ERROR_destination_register_not_allowed_in_list\r
+    .dest_okay:\r
+       cmp     ecx,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .do_single:\r
+       and     eax,2\r
+       shl     eax,21-1\r
+       or      ebp,eax\r
+       bsf     ecx,[reg_list_bitmap]\r
+       mov     ch,[operand_register0]\r
+       mov     [operand_registers],ecx\r
+       mov     [operand_size],4\r
+       mov     ecx,ebp\r
+       and     ecx,1 shl 24 + 1 shl 21\r
+       ;IA,DA          ; 0=rd,[rn]\r
+       ;IA!,DA!        ; 4=rd,[rn],imm\r
+       ;IB,DB          ; 5=rd,[rn,imm]\r
+       ;IB!,DB!        ; 6=rd,[rn,imm]!\r
+       mov     eax,0                                   ; 0=rd,[rn]\r
+       mov     edx,4                                   ; 4=rd,[rn],imm\r
+       cmp     ecx,0 shl 24 + 1 shl 21\r
+       cmovz   eax,edx\r
+       mov     edx,5                                   ; 5=rd,[rn,imm]\r
+       cmp     ecx,1 shl 24 + 0 shl 21\r
+       cmovz   eax,edx\r
+       mov     edx,6                                   ; 6=rd,[rn,imm]!\r
+       cmp     ecx,1 shl 24 + 1 shl 21\r
+       cmovz   eax,edx\r
+       mov     ecx,eax\r
+       and     ecx,4\r
+       mov     edx,ecx\r
+       neg     edx\r
+       test    ebp,1 shl 23\r
+       cmovz   ecx,edx\r
+       mov     [immediate_value],ecx\r
+       movzx   ecx,[instruction_condition]\r
+       and     ecx,0xf0\r
+       shl     ecx,24\r
+       and     ebp,0x00100000\r
+       lea     ebp,[ebp+ecx+0x04000000]\r
+       jmp     ARM_rd_address2.process\r
+\r
+ARM_address4:\r
+       ;used by PUSH, POP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_reg_list>                                 ;0={..}\r
+       mov     [operand_size],4\r
+       mov     [operand_register0],13  ;sp\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_address4\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       mov     al,2                                    ;2=rn!,{..}\r
+       jmp     ARM_rn_address4.do\r
+\r
+ARM_target:\r
+       ;used by B, BL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_address>                                  ;0=imm  PC relative\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_B_target\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       add     eax,[immediate_value]\r
+       sub     eax,edi\r
+       sub     eax,8\r
+       test    eax,3\r
+       jnz     .not_aligned\r
+       cmp     eax,1 shl 25\r
+       jge     .jump_out_of_range\r
+       cmp     eax,-(1 shl 25)\r
+       jl      .jump_out_of_range\r
+       shr     eax,2\r
+       and     eax,0x00ffffff\r
+       or      ebp,eax\r
+       or      ebp,1 shl 27 + 1 shl 25\r
+       jmp     ARM_store_instruction\r
+    .jump_out_of_range:\r
+       mov     ecx,ERROR_relative_jump_out_of_range\r
+       jmp     ARM_store_instruction_with_error\r
+    .not_aligned:\r
+       mov     ecx,ERROR_relative_jump_not_aligned\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM_immediate24:\r
+       ;used by SWI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_immediate8\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x00ffffff\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0xffffff\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM_rd_target:\r
+       ;used by ADR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_address>                    ;0=reg,imm\r
+       mov     [operand_register1],0xf                 ;rn=pc\r
+       mov     ecx,[addressing_space]\r
+       mov     ecx,[ecx+0x00]\r
+       add     ecx,[immediate_value]\r
+       sub     ecx,edi\r
+       sub     ecx,8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .offset_done\r
+       call    THUMB_query_condition_pc                ;adjust for THUMB\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       add     ecx,4\r
+       and     ecx,not 3\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       cmp     [value_undefined],0\r
+       jz      .offset_done\r
+       xor     ecx,ecx\r
+    .offset_done:\r
+       mov     [immediate_value],ecx\r
+       mov     al,6                                    ;6=reg,reg,imm\r
+       jmp     ARM_rd_rn_shifter.encode_instruction\r
+\r
+ARM_rd_rm:\r
+       ;used by NEG\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>,\                               ;0=reg\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;1=reg,reg\r
+       cmp     al,0\r
+       jnz     .registers_shifted\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+    .registers_shifted:\r
+       mov     al,0                                    ;reg,reg,imm\r
+       jmp     ARM_rd_rn_shifter.encode_shifter\r
+\r
+;V2\r
+\r
+ARM_copro_op1_crd_crn_crm_op2:\r
+       ;used by CDP, CDP2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg>,\                  ;0=copro,op1,crd,crn,crm\r
+       <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2> ;1=copro,op1,crd,crn,crm,op2\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .check_v7m\r
+       cmp     ebp,0xf shl 28                          ;CDP2?\r
+       jae     .check_v5\r
+       jmp     .check_v2\r
+    .check_v7m:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .version_check_okay\r
+    .check_v2:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2\r
+       jz      ERROR_requires_cpu_capability_arm_v2\r
+       jmp     .version_check_okay\r
+    .check_v5:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+    .version_check_okay:\r
+       movzx   eax,[operand_register0]                 ;cpnum\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode1]                     ;op1\r
+       shl     eax,20\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;crm\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode2]                     ;op2\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+ARM_copro_crd_address5:\r
+       ;used by LDC, LDCL, LDC2, LDC2L, STC, STCL, STC2, STC2L\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                      ;0=copro,crd,[rn]\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                             ;1=copro,crd,[rn],imm\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                          ;2=copro,crd,[rn],{imm}\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                             ;3=copro,crd,[rn,imm]\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ;4=copro,crd,[rn,imm]!\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                       ;5=copro,crd,[imm]      PC relative\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                    ;6=copro,crd,[exp]      implicit reg from structure\r
+       <TMPL_cpro_sel,TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                ;7=copro,crd,[exp]!     implicit reg from structure\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .check_v7m\r
+       cmp     ebp,0xf shl 28                          ;LDC2/STC2?\r
+       jae     .check_v5\r
+       jmp     .check_v2\r
+    .check_v7m:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .version_check_okay\r
+    .check_v2:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2\r
+       jz      ERROR_requires_cpu_capability_arm_v2\r
+       jmp     .version_check_okay\r
+    .check_v5:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+    .version_check_okay:\r
+       cmp     al,0\r
+       jz      .copro_crd_q_rn_p\r
+       cmp     al,1\r
+       jz      .copro_crd_q_rn_p_imm\r
+       cmp     al,2\r
+       jz      .copro_crd_q_rn_p_option\r
+       cmp     al,3\r
+       jz      .copro_crd_q_rn_imm_p\r
+       cmp     al,4\r
+       jz      .copro_crd_q_rn_imm_p!\r
+       cmp     al,5\r
+       jz      .copro_crd_q_imm_p\r
+       cmp     al,6\r
+       jz      .copro_crd_q_exp_p\r
+       cmp     al,7\r
+       jz      .copro_crd_q_exp_p!\r
+       ud2\r
+    .copro_crd_q_rn_p_option:\r
+       cmp     [immediate_value],0xff\r
+       ja      .option_out_of_range\r
+       shl     [immediate_value],2\r
+       jmp     .encode\r
+    .copro_crd_q_imm_p:\r
+       mov     [operand_register2],0xf\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       and     ecx,not 3                               ;round down\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       setnz   al\r
+       movzx   eax,al\r
+       shl     eax,2\r
+       add     eax,4                                   ;offset=4 for THUMB and 8 for ARM\r
+       sub     ecx,eax\r
+       mov     [immediate_value],ecx\r
+    .copro_crd_q_rn_p:\r
+    .copro_crd_q_exp_p:\r
+    .copro_crd_q_rn_imm_p:\r
+       or      ebp,1 shl 24                            ;P bit\r
+       jmp     .encode\r
+    .copro_crd_q_exp_p!:\r
+    .copro_crd_q_rn_imm_p!:\r
+       cmp     [operand_register2],0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,1 shl 24                            ;P bit\r
+    .copro_crd_q_rn_p_imm:\r
+       cmp     [immediate_value],0\r
+       jz      .copro_crd_q_rn_p\r
+       or      ebp,1 shl 21                            ;W bit\r
+       cmp     [operand_register2],0xf\r
+       jz      ERROR_r15_not_valid.third\r
+    .encode:\r
+       movzx   eax,[operand_register0]                 ;cpnum\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       test    eax,3\r
+       jnz     .out_of_range\r
+       sar     eax,2\r
+       mov     ecx,1 shl 23                            ;U bit\r
+       or      ecx,ebp\r
+       mov     edx,eax\r
+       neg     edx\r
+       test    eax,eax\r
+       cmovns  ebp,ecx\r
+       cmovs   eax,edx\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0x3fc\r
+       jmp     ARM_post_process_copro_with_error\r
+    .option_out_of_range:\r
+       mov     ecx,ERROR_option_out_of_range\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+ARM_copro_op1_rd_crn_crm_op2:\r
+       ;used by MCR, MCR2, MRC, MRC2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg>,\                  ;0=copro,op1,rd,crn,crm\r
+       <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2> ;1=copro,op1,rd,crn,crm,op2\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .check_v7m\r
+       cmp     ebp,0xf shl 28                          ;MCR2 or MRC2?\r
+       jae     .check_v5\r
+       jmp     .check_v2\r
+    .check_v7m:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .version_check_okay\r
+    .check_v2:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2\r
+       jz      ERROR_requires_cpu_capability_arm_v2\r
+       jmp     .version_check_okay\r
+    .check_v5:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+    .version_check_okay:\r
+       movzx   eax,[operand_register0]                 ;cpnum\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode1]                     ;op1\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       shl     eax,21\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       test    ebp,1 shl 20                            ;MCR?\r
+       jnz     .rd_check_okay\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.third\r
+    .rd_check_okay:\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;crm\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode2]                     ;op2\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_opcode3_out_of_range\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+ARM_rd_rm_rs_rn:\r
+       ;used by MLA, MLS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rd,rm,rs,rn\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm_rs_rn.7m\r
+       test    ebp,1 shl 22                            ;MLS?\r
+       jz      .do\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       jmp     .encode\r
+    .do:\r
+       ;used by MUL\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V2\r
+       jz      ERROR_requires_cpu_capability_arm_v2\r
+    .encode:\r
+       ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.fourth\r
+       shl     eax,12\r
+       or      ebp,eax\r
+    ;version 6 and above relax the rd!=rm restriction\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jnz     ARM_store_instruction\r
+       mov     al,[operand_register0]                  ;rd\r
+       mov     ah,[operand_register1]                  ;rm\r
+       cmp     al,ah\r
+       jz      ERROR_source_rm_and_dest_must_differ\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm_rs_rn.7m:\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       jmp     .THUMB_rd_rm_rs_rn.encode\r
+    .THUMB_rd_rm_rs_rn:\r
+       ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_t2\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      THUMB_post_process\r
+    .THUMB_rd_rm_rs_rn.encode:\r
+       mov     cl,0xff\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rn\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_rs:\r
+       ;used by MUL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=rd,rm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=rd,rm,rs\r
+       mov     [operand_register3],0                   ;rn=0\r
+       cmp     al,0\r
+       jnz     .do\r
+       mov     al,[operand_register0]\r
+       mov     [operand_register2],al\r
+    .do:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_MUL_rd_rm_rs\r
+       jmp     ARM_rd_rm_rs_rn.do\r
+\r
+;v2a\r
+\r
+ARM_rd_rm_q_rn_p:\r
+       ;used by SWP, SWPB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>        ;0=rd,rm,[rn]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ERROR_instruction_not_16bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_A\r
+       jz      ERROR_requires_cpu_capability_arm_v2a\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     al,[operand_register0]                  ;rd\r
+       mov     ah,[operand_register1]                  ;rm\r
+       mov     cl,[operand_register2]                  ;rn\r
+       cmp     cl,al\r
+       jz      ERROR_memory_address_cannot_be_source_or_dest\r
+       cmp     cl,ah\r
+       jz      ERROR_memory_address_cannot_be_source_or_dest\r
+       jmp     ARM_store_instruction\r
+\r
+;v3\r
+\r
+ARM_rd_psr:\r
+       ;used by MRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_sysm_reg>,\                 ;0=rd,sysm\r
+       <TMPL_base_reg,TMPL_psr>,\                      ;1=rd,psr\r
+       <TMPL_base_reg,TMPL_banked_reg>                 ;2=rd,banked_reg\r
+       cmp     al,2\r
+       jz      .banked\r
+       cmp     al,0\r
+       jz      .THUMB_sysm\r
+       movzx   ecx,[operand_register1]                 ;PSR\r
+       mov     edx,32\r
+       cmp     ecx,15\r
+       cmovz   ecx,edx\r
+       mov     edx,33\r
+       cmp     ecx,31\r
+       cmovz   ecx,edx\r
+       cmp     ecx,32\r
+       jb      ERROR_must_use_full_psr\r
+       and     ecx,1                                   ;ecx = R bit\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_psr\r
+    .encode:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3\r
+       jz      ERROR_requires_cpu_capability_arm_v3\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       shl     ecx,22\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .ARM_sysm:\r
+       movzx   ecx,[operand_register1]\r
+       test    ecx,ecx                                 ;APSR?\r
+       jnz     ERROR_instruction_not_32bit\r
+       jmp     .encode\r
+    .THUMB_sysm:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .ARM_sysm\r
+       xor     ecx,ecx\r
+       movzx   edx,[operand_register1]\r
+       or      [thumb32_instruction],edx\r
+       cmp     edx,20                                  ;control is 6M\r
+       jz      .THUMB_check_6M\r
+       cmp     edx,17                                  ;17+ are 7M\r
+       jae     .THUMB_check_7M\r
+    .THUMB_check_6M:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jz      ERROR_requires_cpu_capability_arm_6m\r
+       jmp     .THUMB_rd_psr.encode\r
+    .THUMB_check_7M:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .THUMB_rd_psr.encode\r
+    .THUMB_rd_psr:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+    .THUMB_rd_psr.encode:\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_error],ERROR_r13_r15_not_valid\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      THUMB_post_process\r
+       cmp     eax,0xd\r
+       jz      THUMB_post_process\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       shl     ecx,20\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .banked:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE\r
+       jz      ERROR_requires_cpu_capability_arm_ve\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       movzx   ebp,[operand_register1]\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       and     ebp,0x0f                                ;get m1 field\r
+       and     ecx,0x10                                ;get m field\r
+       and     edx,0x20                                ;get R field\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_banked\r
+       shl     ebp,16\r
+       shl     ecx,8-4\r
+       shl     edx,22-5\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       or      ebp,0x0100f200\r
+       movzx   eax,[instruction_condition]\r
+       and     eax,0xf0\r
+       shl     eax,28-4\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_banked:\r
+       cmp     eax,0xd\r
+       jz      ERROR_r13_not_valid.second\r
+       shl     ebp,8\r
+       shl     ecx,4-4\r
+       shl     edx,20-5\r
+       shl     eax,16\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       or      ebp,0xf3e08020\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_psr_value:\r
+       ;used by MSR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_sysm_reg,TMPL_base_reg>,\                 ;0=sysm,rn\r
+       <TMPL_psr,TMPL_base_reg>,\                      ;1=psr,rn\r
+       <TMPL_psr,TMPL_imm>,\                           ;2=psr,imm\r
+       <TMPL_banked_reg,TMPL_base_reg>                 ;3=banked_reg,rn\r
+       cmp     al,3\r
+       jz      .banked\r
+       sub     al,1\r
+       jc      .THUMB_sysm\r
+       movzx   edx,[operand_register0]                 ;psr\r
+       mov     ecx,0x09                                ;CPSR_fc\r
+       cmp     edx,32                                  ;CPSR?\r
+       cmovz   edx,ecx\r
+       mov     ecx,0x19                                ;SPSR_fc\r
+       cmp     edx,33                                  ;SPSR?\r
+       cmovz   edx,ecx\r
+       mov     ecx,0x0c                                ;APSR_nzcvqg\r
+       cmp     edx,34                                  ;APSR?\r
+       cmovz   edx,ecx\r
+       mov     ecx,0x10                                ;extract R bit\r
+       and     ecx,edx\r
+       and     edx,0xf\r
+       cmp     al,1\r
+       jz      .psr_imm\r
+    .psr_rm:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_psr_rm\r
+    .encode:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3\r
+       jz      ERROR_requires_cpu_capability_arm_v3\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       shl     ecx,22-4\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .psr_imm:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ERROR_instruction_not_16bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V3\r
+       jz      ERROR_requires_cpu_capability_arm_v3\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       shl     ecx,22-4\r
+       or      ebp,ecx\r
+       or      ebp,1 shl 25\r
+       call    ARM_encode_immediate\r
+       jc      ERROR_immediate_cannot_be_encoded\r
+       or      ebp,[immediate_value]\r
+       jmp     ARM_store_instruction\r
+    .ARM_sysm:\r
+       xor     ecx,ecx\r
+       movzx   edx,[operand_register0]\r
+       test    edx,edx                                 ;APSR?\r
+       jnz     ERROR_instruction_not_32bit\r
+       mov     edx,0x0c                                ;APSR_nzcvqg\r
+       jmp     .encode\r
+    .THUMB_sysm:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .ARM_sysm\r
+       movzx   ecx,[operand_register0]\r
+       or      [thumb32_instruction],ecx\r
+       cmp     ecx,20                                  ;control is 6M\r
+       jz      .THUMB_check_6M\r
+       cmp     ecx,17                                  ;17+ are 7M\r
+       jae     .THUMB_check_7M\r
+    .THUMB_check_6M:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jz      ERROR_requires_cpu_capability_arm_6m\r
+       xor     ecx,ecx\r
+       mov     edx,8\r
+       jmp     .THUMB_rd_psr.encode\r
+    .THUMB_check_7M:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       xor     ecx,ecx\r
+       mov     edx,8\r
+       jmp     .THUMB_rd_psr.encode\r
+    .THUMB_psr_rm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+    .THUMB_rd_psr.encode:\r
+       mov     ebp,[thumb32_instruction]\r
+       shl     edx,8\r
+       or      ebp,edx\r
+       shl     ecx,20-4\r
+       or      ebp,ecx\r
+       mov     [thumb32_error],ERROR_r13_r15_not_valid\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      THUMB_post_process\r
+       cmp     eax,0xd\r
+       jz      THUMB_post_process\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .banked:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE\r
+       jz      ERROR_requires_cpu_capability_arm_ve\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       cmp     eax,0xd\r
+       jz      ERROR_r13_not_valid.second\r
+       movzx   ebp,[operand_register0]\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       and     ebp,0x0f                                ;get m1 field\r
+       and     ecx,0x10                                ;get m field\r
+       and     edx,0x20                                ;get R field\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_banked\r
+       shl     ebp,16\r
+       shl     ecx,8-4\r
+       shl     edx,22-5\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       or      ebp,0x0120f200\r
+       movzx   eax,[instruction_condition]\r
+       and     eax,0xf0\r
+       shl     eax,28-4\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_banked:\r
+       shl     ebp,8\r
+       shl     ecx,4-4\r
+       shl     edx,20-5\r
+       shl     eax,16\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       or      ebp,0xf3808020\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rdlo_rdhi_rm_rs:\r
+       ;used by UMLAL, UMULL, SMLAL, SMULL, UMAAL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rdlo,rdhi,rm,rs\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rdlo_rdhi_rn_rm.7m\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21 + 0xf shl 4\r
+       cmp     edx,2 shl 21 + 9 shl 4                  ;UMAAL?\r
+       jnz     .check_M\r
+    ;check v6\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       jmp     .encode\r
+    .check_M:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_M\r
+       jz      ERROR_requires_cpu_capability_arm_m\r
+    .encode:\r
+       movzx   eax,[operand_register0]                 ;rdlo\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rdhi\r
+       shl     eax,16\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.fourth\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       mov     ax,word[operand_registers+0]            ;rdlo & rdhi\r
+       cmp     al,ah\r
+       jz      ERROR_destination_registers_must_differ\r
+    ;version 6 and above relax the rd!=rm restriction\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jnz     ARM_store_instruction\r
+       mov     cl,[operand_register2]                  ;rm\r
+       cmp     cl,al\r
+       jz      ERROR_source_rm_and_dest_must_differ\r
+       cmp     cl,ah\r
+       jz      ERROR_source_rm_and_dest_must_differ\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rdlo_rdhi_rn_rm.7m:\r
+       test    [thumb32_instruction],0x60              ;UMAAL is T2\r
+       jnz     .THUMB_rdlo_rdhi_rn_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .THUMB_rdlo_rdhi_rn_rm.encode\r
+    .THUMB_rdlo_rdhi_rn_rm:\r
+       ;used by SMLALD, SMLALDX, SMLSLD, SMLSLDX, SMLALBB, SMLALBT, SMLALTB, SMLALTT\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+    .THUMB_rdlo_rdhi_rn_rm.encode:\r
+       mov     cl,0xff\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_destination_registers_must_differ\r
+       mov     ax,word[operand_registers+0]            ;rdlo & rdhi\r
+       cmp     al,ah\r
+       jz      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rdlo\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rdhi\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rm\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v4\r
+\r
+ARM_rd_address3D:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_rd_address\r
+       ;used by STRD, LDRD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                                            ; 0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                                           ; 1=rd,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                                   ; 2=rd,[rn],imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                                   ; 3=rd,[rn,imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\                             ; 4=rd,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                                           ; 5=rd,[rn,+-rm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\                     ; 6=rd,[rn,+-rm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                                             ; 7=rd,[imm]    PC relative\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                                          ; 8=rd,[exp]    implicit reg from structure\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                                    ; 9=rd,[exp]!   implicit reg from structure\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                              ;10=rd,rd2,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                             ;11=rd,rd2,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                     ;12=rd,rd2,[rn],imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                     ;13=rd,rd2,[rn,imm]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\               ;14=rd,rd2,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                             ;15=rd,rd2,[rn,+-rm]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ;16=rd,rd2,[rn,+-rm]!\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                               ;17=rd,rd2,[imm]        PC relative\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                            ;18=rd,rd2,[exp]        implicit reg from structure\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                        ;19=rd,rd2,[exp]!       implicit reg from structure\r
+       cmp     al,10\r
+       jb      .dest_registers_defined\r
+       mov     ecx,[operand_registers]\r
+       mov     dl,cl\r
+       shr     ecx,8\r
+       dec     cl\r
+       mov     [operand_registers],ecx\r
+       cmp     dl,cl\r
+       jnz     ERROR_source_registers_must_be_consecutive\r
+       sub     al,10\r
+    .dest_registers_defined:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_P\r
+       jz      ERROR_requires_cpu_capability_arm_p\r
+       mov     cl,[operand_register0]\r
+       test    cl,1                                    ;even register?\r
+       jnz     ERROR_destination_register_must_be_even\r
+       cmp     cl,14\r
+       jz      ERROR_r14_not_valid.first\r
+       jmp     ARM_rd_address3.version_check_okay\r
+\r
+ARM_rd_address3:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_rd_address\r
+       ;used by LDRH, LDRSH, LDRSB, STRH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                            ;0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                           ;1=rd,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                   ;2=rd,[rn],imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                   ;3=rd,[rn,imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ;4=rd,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                           ;5=rd,[rn,+-rm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;6=rd,[rn,+-rm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                             ;7=rd,[imm]     PC relative\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                          ;8=rd,[exp]     implicit reg from structure\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                      ;9=rd,[exp]!    implicit reg from structure\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4\r
+       jz      ERROR_requires_cpu_capability_arm_v4\r
+    .version_check_okay:\r
+       mov     cl,[operand_register0]\r
+       cmp     cl,15\r
+       jz      ERROR_r15_not_valid.first\r
+       cmp     al,0\r
+       jz      .rd_q_rn_p\r
+       cmp     al,1\r
+       jz      .rd_q_rn_p_PMrm\r
+       cmp     al,2\r
+       jz      .rd_q_rn_p_imm\r
+       cmp     al,3\r
+       jz      .rd_q_rn_imm_p\r
+       cmp     al,4\r
+       jz      .rd_q_rn_imm_p!\r
+       cmp     al,5\r
+       jz      .rd_q_rn_PMrm_p\r
+       cmp     al,6\r
+       jz      .rd_q_rn_PMrm_p!\r
+       cmp     al,7\r
+       jz      .rd_q_imm_p\r
+       cmp     al,8\r
+       jz      .rd_q_exp_p\r
+       cmp     al,9\r
+       jz      .rd_q_exp_p!\r
+       ud2\r
+    .rd_q_imm_p:\r
+       mov     [operand_register1],0xf                 ;rn=r15\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       add     eax,[immediate_value]\r
+       sub     eax,edi\r
+       sub     eax,8\r
+       mov     [immediate_value],eax\r
+    .rd_q_exp_p:\r
+    .rd_q_rn_p:\r
+    .rd_q_rn_imm_p:\r
+       or      ebp,0x2 shl 21\r
+       test    ebp,1 shl 21                            ;W=1 if T specified\r
+       jnz     .encode_imm\r
+       or      ebp,0x8 shl 21                          ;P\r
+       jmp     .encode_imm\r
+    .rd_q_rn_p_imm:\r
+       cmp     [immediate_value],0\r
+       jz      .rd_q_rn_p\r
+       or      ebp,0x2 shl 21\r
+       jmp     .check_rn\r
+    .rd_q_exp_p!:\r
+    .rd_q_rn_imm_p!:\r
+       cmp     [immediate_value],0\r
+       jz      .rd_q_rn_p\r
+       or      ebp,0xb shl 21\r
+    .check_rn:\r
+       mov     ax,word[operand_register0]              ;ah=rn, al=rd\r
+       cmp     ah,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       cmp     [operand_size],8                        ;LDRD or STRD?\r
+       setz    cl\r
+       not     cl\r
+       and     al,cl\r
+       and     ah,cl\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+    .encode_imm:\r
+       or      ebp,1 shl 23\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax\r
+       jns     .positive_imm\r
+       and     ebp,not (1 shl 23)\r
+       neg     eax\r
+    .positive_imm:\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     ecx,0xf shl 4\r
+       and     eax,0xf\r
+       shl     ecx,4\r
+       or      eax,ecx\r
+       or      ebp,eax\r
+       or      ebp,1 shl 22\r
+    .encode_rd_rn:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .rd_q_rn_PMrm_p:\r
+       or      ebp,0x8 shl 21\r
+       jmp     .encode_reg\r
+    .rd_q_rn_PMrm_p!:\r
+       or      ebp,0x9 shl 21\r
+    .rd_q_rn_p_PMrm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jnz     .base_offset_okay\r
+       mov     ax,word[operand_register1]\r
+       and     ax,0x7f7f\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_offset_must_differ_with_writeback\r
+    .base_offset_okay:\r
+       mov     al,[operand_register1]                  ;rn\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       cmp     al,[operand_register0]                  ;rd\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       cmp     [operand_size],8                        ;LDRD or STRD?\r
+       jnz     .encode_reg\r
+       mov     ah,[operand_register0]                  ;rd\r
+       and     ax,0xfefe\r
+       cmp     al,ah\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+    .encode_reg:\r
+       cmp     [operand_size],8                        ;LDRD or STRD?\r
+       jnz     .encode_reg.do\r
+       test    ebp,1 shl 20                            ;STRD=0\r
+       jz      .encode_reg.do\r
+       mov     ah,[operand_register0]                  ;rd\r
+       mov     al,[operand_register2]                  ;rm\r
+       and     ax,0x7e7e\r
+       cmp     al,ah\r
+       jz      ERROR_offset_and_dest_must_differ_with_LDRD\r
+    .encode_reg.do:\r
+       or      ebp,1 shl 23\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       test    al,al\r
+       jns     .store_reg\r
+       and     eax,0xf\r
+       btr     ebp,23\r
+    .store_reg:\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       jmp     .encode_rd_rn\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0xff\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+;v4T\r
+\r
+THUMB2_check_bad_regs:\r
+       ;cl has the bitmap for registers to check\r
+       ;cl[3..0] check for reg[3..0] <> pc\r
+       ;cl[7..4] check for reg[3..0] <> sp\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      .sp_check_okay\r
+       and     cl,0xf                  ;v8 instructions allow usage of SP in THUMB instructions\r
+    .sp_check_okay:\r
+       mov     edx,[operand_registers]\r
+       test    cl,0x01 shl 0\r
+       jz      .reg0_pc_okay\r
+       cmp     dl,0xf\r
+       jz      .bad_reg\r
+    .reg0_pc_okay:\r
+       test    cl,0x10 shl 0\r
+       jz      .reg0_sp_okay\r
+       cmp     dl,0xd\r
+       jz      .bad_reg\r
+    .reg0_sp_okay:\r
+       shr     cl,1\r
+       test    cl,0x01\r
+       jz      .reg1_pc_okay\r
+       cmp     dh,0xf\r
+       jz      .bad_reg\r
+    .reg1_pc_okay:\r
+       test    cl,0x10\r
+       jz      .reg1_sp_okay\r
+       cmp     dh,0xd\r
+       jz      .bad_reg\r
+    .reg1_sp_okay:\r
+       shr     cl,1\r
+       shr     edx,16\r
+       test    cl,0x01\r
+       jz      .reg2_pc_okay\r
+       cmp     dl,0xf\r
+       jz      .bad_reg\r
+    .reg2_pc_okay:\r
+       test    cl,0x10\r
+       jz      .reg2_sp_okay\r
+       cmp     dl,0xd\r
+       jz      .bad_reg\r
+    .reg2_sp_okay:\r
+       shr     cl,1\r
+       test    cl,0x01\r
+       jz      .reg3_pc_okay\r
+       cmp     dh,0xf\r
+       jz      .bad_reg\r
+    .reg3_pc_okay:\r
+       test    cl,0x10\r
+       jz      .reg3_sp_okay\r
+       cmp     dh,0xd\r
+       jz      .bad_reg\r
+    .reg3_sp_okay:\r
+       clc\r
+       ret\r
+    .bad_reg:\r
+       and     cl,0x11\r
+       cmp     cl,0x10\r
+       mov     [thumb32_error],ERROR_r15_not_valid\r
+       jb      .fail\r
+       mov     [thumb32_error],ERROR_r13_not_valid\r
+       jz      .fail\r
+       mov     [thumb32_error],ERROR_r13_r15_not_valid\r
+    .fail:\r
+       stc\r
+       ret\r
+\r
+THUMB_rd_rn_shifter:\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21\r
+       shr     edx,21\r
+       mov     ah,dl\r
+       mov     [can_swap_rm_rn],0\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_AND\r
+       jz      THUMB_AND_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_EOR\r
+       jz      THUMB_EOR_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_SUB\r
+       jz      THUMB_SUB_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_RSB\r
+       jz      THUMB_RSB_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_ADD\r
+       jz      THUMB_ADD_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_ADC\r
+       jz      THUMB_ADC_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_SBC\r
+       jz      THUMB_SBC_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_RSC\r
+       jz      THUMB_RSC_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_TST\r
+       jz      THUMB_TST_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_TEQ\r
+       jz      THUMB_TEQ_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_CMP\r
+       jz      THUMB_CMP_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_CMN\r
+       jz      THUMB_CMN_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_ORR\r
+       jz      THUMB_ORR_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_MOV\r
+       jz      THUMB_MOV_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_BIC\r
+       jz      THUMB_BIC_rd_rn_shifter\r
+       cmp     ah,ARM_INSTRUCTION_OPCODE_MVN\r
+       jz      THUMB_MVN_rd_rn_shifter\r
+       ud2\r
+\r
+THUMB_AND_rd_rn_shifter:\r
+       mov     [can_swap_rm_rn],-1\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_AND\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_EOR_rd_rn_shifter:\r
+       mov     [can_swap_rm_rn],-1\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_EOR\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_ADC_rd_rn_shifter:\r
+       mov     [can_swap_rm_rn],-1\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_ADC\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_SBC_rd_rn_shifter:\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_SBC\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_TST_rd_rn_shifter:\r
+       mov     edx,[operand_registers]\r
+       mov     dl,dh\r
+       mov     [operand_registers],edx\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_TST\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_CMN_rd_rn_shifter:\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dh\r
+       shl     ecx,16\r
+       or      [thumb32_instruction],ecx\r
+       mov     cx,0x0800\r
+       cmp     dh,13                                   ;SP is okay here\r
+       cmove   edx,ecx\r
+       mov     dl,dh\r
+       mov     word[operand_registers+0],dx\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_CMN\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_ORR_rd_rn_shifter:\r
+       mov     [can_swap_rm_rn],-1\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_ORR\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_BIC_rd_rn_shifter:\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_BIC\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_MVN_rd_rn_shifter:\r
+       mov     edx,[operand_registers]\r
+       mov     dh,dl\r
+       mov     [operand_registers],edx\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_MVN\r
+       jmp     THUMB_GEN_rd_rn_shifter\r
+\r
+THUMB_GEN_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      .reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      .reg_reg_reg\r
+       cmp     al,9\r
+       jz      .reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      .reg_reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      .reg_reg_reg_shift_reg\r
+       ud2\r
+    .reg_reg_reg:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_reg.32\r
+       mov     [thumb16_error],ERROR_dest_and_source_must_be_the_same\r
+       mov     eax,[operand_registers]\r
+       test    eax,0x080808\r
+       jnz     .register_swap_done\r
+       mov     ecx,[force_wide_flag]\r
+       test    byte[ecx-1],FLAG_FORCE_WIDE\r
+       jnz     .register_swap_done\r
+       cmp     [can_swap_rm_rn],-1\r
+       jnz     .register_swap_done\r
+       mov     ecx,eax\r
+       shr     ecx,16\r
+       cmp     cl,al\r
+       jnz     .register_swap_done\r
+       xchg    cl,ah\r
+       shl     ecx,16\r
+       and     eax,not (0xff shl 16)\r
+       or      eax,ecx\r
+    .register_swap_done:\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jnz     .reg_reg_reg.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       shr     eax,8\r
+       test    ax,0x0808\r
+       jnz     .reg_reg_reg.32\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x40\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_reg.32:\r
+       mov     cl,0x77\r
+    .reg_reg_reg.32.valid_regs_set:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     edx,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      edx,eax\r
+       movzx   eax,[operand_register2]\r
+       or      edx,eax\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       setnz   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,20\r
+       or      edx,ecx\r
+       or      edx,1 shl 27 + 1 shl 25\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .reg_reg_imm:\r
+       mov     cl,0x33\r
+    .reg_reg_imm.valid_regs_set:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       push    ecx\r
+       call    THUMB_encode_immediate_with_opcode_swap\r
+       pop     ecx\r
+       mov     [thumb32_error],ERROR_immediate_cannot_be_encoded\r
+       jc      THUMB_post_process\r
+    .reg_reg_imm.encode:\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     edx,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      edx,eax\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       setnz   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,20\r
+       or      edx,ecx\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,eax\r
+       and     ecx,7 shl 8\r
+       shl     ecx,12-8\r
+       or      edx,ecx\r
+       mov     ecx,eax\r
+       and     eax,0xff\r
+       and     ecx,1 shl 11\r
+       shl     ecx,26-11\r
+       or      edx,eax\r
+       or      edx,ecx\r
+       or      edx,1 shl 28\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .reg_reg_reg_rrx:\r
+       mov     cl,0x77\r
+    .reg_reg_reg_rrx.valid_regs_set:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     [instruction_shift_op],ARM_SHIFT_OPCODE_ROR\r
+       jmp     .reg_reg_reg_shift_imm.do\r
+    .reg_reg_reg_shift_imm:\r
+       mov     cl,0x77\r
+    .reg_reg_reg_shift_imm.valid_regs_set:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       push    ecx\r
+       call    ARM_check_shift_range\r
+       pop     ecx\r
+    .reg_reg_reg_shift_imm.do:\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     edx,[thumb32_instruction]\r
+       movzx   ecx,[instruction_shift_op]\r
+       mov     eax,[immediate_value]\r
+       shl     ecx,4\r
+       or      edx,ecx\r
+       mov     ecx,eax\r
+       and     eax,0x3\r
+       and     ecx,0x7 shl 2\r
+       shl     eax,6\r
+       shl     ecx,12-2\r
+       or      edx,eax\r
+       or      edx,ecx\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      edx,eax\r
+       movzx   eax,[operand_register2]\r
+       or      edx,eax\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       setnz   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,20\r
+       or      edx,ecx\r
+       or      edx,1 shl 27 + 1 shl 25\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .reg_reg_reg_shift_reg:\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_CMP_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      .reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      .reg_reg\r
+       cmp     al,9\r
+       jz      .reg_transfer\r
+       cmp     al,10\r
+       jz      .reg_transfer\r
+       cmp     al,11\r
+       jz      THUMB_post_process\r
+       ud2\r
+    .reg_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_imm.32\r
+       mov     eax,[operand_registers]\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,0xff\r
+       ja      .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     ah,7\r
+       ja      .reg_reg_imm.32\r
+       mov     al,dl\r
+       or      ah,0x28\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_imm.32:\r
+       mov     al,6\r
+    .reg_transfer:\r
+       mov     edx,[operand_registers]\r
+       mov     dl,dh\r
+       mov     word[operand_registers+0],dx\r
+       mov     cl,0x02\r
+       cmp     al,6\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set\r
+       cmp     al,8\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg.32.valid_regs_set\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx.valid_regs_set\r
+       cmp     al,10\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm.valid_regs_set\r
+       ud2\r
+    .reg_reg:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_transfer\r
+       mov     edx,[operand_registers]\r
+       shr     edx,8\r
+       test    dx,0x0808\r
+       jnz     .hreg1_hreg2\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_CMP\r
+       mov     eax,[operand_registers]\r
+       shr     eax,8\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x40\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       mov     al,6\r
+       jmp     .reg_transfer\r
+    .hreg1_hreg2:\r
+       mov     al,dl\r
+       and     al,0x8\r
+       and     dl,0x7\r
+       shl     al,4\r
+       or      al,dl\r
+       shl     dh,3\r
+       or      al,dh\r
+       mov     ah,0x45\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       mov     al,6\r
+       jmp     .reg_transfer\r
+\r
+THUMB_RSB_rd_rn_shifter:\r
+    ;NEG\r
+       cmp     al,6\r
+       jz      .reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg.32\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      THUMB_post_process\r
+       ud2\r
+    .reg_reg_imm:\r
+       cmp     [immediate_value],0\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     eax,[operand_registers]\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ax,0x0808\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x40\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_NEG\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+\r
+THUMB_TEQ_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg.32\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      THUMB_post_process\r
+       ud2\r
+\r
+THUMB_RSC_rd_rn_shifter:\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_SUB_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      .reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      .reg_reg_reg\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      THUMB_ADD_rd_rn_shifter.reg_reg_reg.32\r
+       cmp     al,11\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_reg\r
+       ud2\r
+    .reg_reg_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_imm.32\r
+       mov     edx,eax\r
+       mov     eax,[operand_registers]\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jnz     .reg_reg_imm3\r
+       cmp     al,13                                   ;SP?\r
+       jz      .sp_imm7\r
+       shr     edx,24\r
+       jz      .reg.imm8\r
+       cmp     [immediate_value],7                     ;for small immediates honour two reg encoding\r
+       jbe     .reg_reg_imm3\r
+    .reg.imm8:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     ch,0x38\r
+       mov     edx,[immediate_value]\r
+       test    edx,edx                                 ;negative?\r
+       jns     .reg_imm8_check_range\r
+       neg     edx\r
+       mov     ch,0x30                                 ;change to add reg,imm8\r
+    .reg_imm8_check_range:\r
+       cmp     edx,0xff\r
+       ja      .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     al,7\r
+       ja      .reg_reg_imm.32\r
+       mov     al,dl\r
+       or      ah,ch\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .reg_reg_imm3:\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_7\r
+       mov     edx,[immediate_value]\r
+       mov     ch,0x1e\r
+       test    edx,edx                                 ;negative?\r
+       jns     .reg_reg_imm3_check_range\r
+       neg     edx\r
+       mov     ch,0x1c                                 ;change to add reg,reg,imm3\r
+    .reg_reg_imm3_check_range:\r
+       cmp     edx,7\r
+       ja      .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ax,0x0808\r
+       jnz     .reg_reg_imm.32\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,ch\r
+       shl     edx,6\r
+       or      eax,edx\r
+       movzx   eax,ax\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .sp_imm7:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x1fc\r
+       mov     ecx,0xb080\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax                                 ;negative?\r
+       jns     .sp_imm7_check_range\r
+       neg     eax\r
+       mov     cl,0                                    ;change to add sp,imm7\r
+    .sp_imm7_check_range:\r
+       cmp     eax,0x7f*4\r
+       ja      .reg_reg_imm.32\r
+       test    eax,3\r
+       jnz     .reg_reg_imm.32\r
+       shr     eax,2\r
+       or      eax,ecx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_imm.32:\r
+       cmp     word[operand_registers+0],0x0e0f        ;sub pc,lr,imm?\r
+       jnz     .reg_reg_imm.not_pc_lr\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .subs_pc_lr\r
+    .reg_reg_imm.not_pc_lr:\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_instruction],0xf2a00000        ;SUBW\r
+       call    THUMB_check_12bit_immediate\r
+       jnc     THUMB_rd_rn_imm12.encode\r
+       cmp     [operand_register1],15                  ;PC?\r
+       jz      THUMB_rd_rn_imm12.encode\r
+       mov     [thumb32_instruction],ebp\r
+       cmp     [operand_register1],13\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     cl,0x03\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set\r
+    .subs_pc_lr:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_t2\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_immediate_value_out_of_range.0_0xff\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      THUMB_post_process\r
+       or      eax,0xf3de8f00\r
+       mov     [thumb32_instruction],eax\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .reg_reg_reg:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_ADD_rd_rn_shifter.reg_reg_reg.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       mov     eax,[operand_registers]\r
+       test    eax,0x080808\r
+       jnz     THUMB_ADD_rd_rn_shifter.reg_reg_reg.32\r
+       mov     edx,eax\r
+       shr     edx,16\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0\r
+       mov     dh,0\r
+       shl     edx,6\r
+       or      eax,edx\r
+       or      ah,0x1a\r
+       movzx   eax,ax\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_ADD_rd_rn_shifter.reg_reg_reg.32\r
+\r
+THUMB_ADD_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      .reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      .reg_reg_reg\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      .reg_reg_reg.32\r
+       cmp     al,11\r
+       jz      THUMB_post_process\r
+       ud2\r
+    .reg_reg_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_imm.32\r
+       mov     edx,eax\r
+       mov     eax,[operand_registers]\r
+       cmp     ax,13*0x100+13                          ;SP,SP,imm?\r
+       jz      .sp_imm7\r
+       cmp     ah,13                                   ;SP?\r
+       jz      .rd_sp_imm8\r
+       cmp     ah,15                                   ;PC?\r
+       jz      .rd_pc_imm8\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jnz     .reg_reg_imm3\r
+       shr     edx,24\r
+       jz      .reg.imm8\r
+       cmp     [immediate_value],7                     ;for small immediates honour two reg encoding\r
+       jbe     .reg_reg_imm3\r
+    .reg.imm8:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     ch,0x30\r
+       mov     edx,[immediate_value]\r
+       test    edx,edx                                 ;negative?\r
+       jns     .reg_imm8_check_range\r
+       neg     edx\r
+       mov     ch,0x38                                 ;change to sub reg,imm8\r
+    .reg_imm8_check_range:\r
+       cmp     edx,0xff\r
+       ja      .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     ah,7\r
+       ja      .reg_reg_imm.32\r
+       mov     al,dl\r
+       or      ah,ch\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .reg_reg_imm3:\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_7\r
+       mov     edx,[immediate_value]\r
+       mov     ch,0x1c\r
+       test    edx,edx                                 ;negative?\r
+       jns     .reg_reg_imm3_check_range\r
+       neg     edx\r
+       mov     ch,0x1e                                 ;change to sub reg,reg,imm3\r
+    .reg_reg_imm3_check_range:\r
+       cmp     edx,7\r
+       ja      .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ax,0x0808\r
+       jnz     .reg_reg_imm.32\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,ch\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .sp_imm7:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x1fc\r
+       mov     ecx,0xb000\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax                                 ;negative?\r
+       jns     .sp_imm7_check_range\r
+       neg     eax\r
+       mov     cl,0x80                                 ;change to sub sp,imm7\r
+    .sp_imm7_check_range:\r
+       cmp     eax,0x7f*4\r
+       ja      .reg_reg_imm.32\r
+       test    eax,3\r
+       jnz     .reg_reg_imm.32\r
+       shr     eax,2\r
+       or      eax,ecx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .rd_sp_imm8:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,0xff*4\r
+       ja      .reg_reg_imm.32\r
+       test    edx,3\r
+       jnz     .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     al,7\r
+       ja      .reg_reg_imm.32\r
+       mov     ah,al\r
+       shr     edx,2\r
+       mov     al,dl\r
+       or      ah,0xa8\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_imm.32\r
+    .rd_pc_imm8:\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,0xff*4\r
+       ja      .reg_reg_imm.32\r
+       test    edx,3\r
+       jnz     .reg_reg_imm.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     al,7\r
+       ja      .reg_reg_imm.32\r
+       mov     ah,al\r
+       shr     edx,2\r
+       mov     al,dl\r
+       or      ah,0xa0\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_imm.32:\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_instruction],0xf2000000        ;ADDW\r
+       call    THUMB_check_12bit_immediate\r
+       jnc     THUMB_rd_rn_imm12.encode\r
+       cmp     [operand_register1],15                  ;PC?\r
+       jz      THUMB_rd_rn_imm12.encode\r
+       mov     [thumb32_instruction],ebp\r
+       cmp     [operand_register1],13\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     cl,0x03\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_imm.valid_regs_set\r
+    .reg_reg_reg:\r
+       mov     eax,[operand_registers]\r
+       mov     edx,eax\r
+       shr     edx,16\r
+       cmp     dl,al                                   ;rd=rm?\r
+       jz      .check_hregs\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jne     .reg1_reg2_reg3\r
+    .check_hregs:\r
+       test    eax,0x080808\r
+       jnz     .hreg1_hreg1_hreg2\r
+       ;special case for 'add lreg,lreg'\r
+       ;if:\r
+       ;1. UAL\r
+       ;2. no S and not conditional\r
+       ;3. V6M\r
+       ;then use 'add hreg,hreg' version\r
+       test    [code_type],CPU_ACTIVITY_THUMB_UAL\r
+       jz      .reg1_reg2_reg3                         ;encode the lreg version 'adds lreg,lreg,lreg'\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .reg1_reg2_reg3                         ;encode the lreg version 'adds lreg,lreg,lreg'\r
+       cmp     [instruction_condition],0xe shl 4\r
+       jb      .reg1_reg2_reg3\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_6m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jnz     .hreg1_hreg1_hreg2.do                   ;encode the hreg version in UAL without S\r
+    .reg1_reg2_reg3:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_reg.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    eax,0x080808\r
+       jnz     .reg_reg_reg.32\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0\r
+       mov     dh,0\r
+       shl     edx,6\r
+       or      eax,edx\r
+       or      ah,0x18\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     .reg_reg_reg.32\r
+    .hreg1_hreg1_hreg2:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_reg.32\r
+    .hreg1_hreg1_hreg2.do:\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jz      .swap_okay\r
+       xchg    dl,ah\r
+    .swap_okay:\r
+       and     ax,0x0807\r
+       shl     ah,4\r
+       or      al,ah\r
+       shl     dl,3\r
+       or      al,dl\r
+       mov     ah,0x44\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_reg.32:\r
+       cmp     [operand_register1],13\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     [operand_register0],13\r
+       jnz     .shift_checked\r
+       mov     [thumb32_error],ERROR_shift_type_must_be_LSL\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.0_3\r
+       cmp     [immediate_value],3\r
+       ja      THUMB_post_process\r
+    .shift_checked:\r
+       mov     cl,0x47\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm.valid_regs_set\r
+\r
+THUMB_MOV_rd_rn_shifter:\r
+       cmp     al,6\r
+       jz      .reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      .reg_reg\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      .reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      .reg_reg_shift_reg\r
+       ud2\r
+    .reg_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     ah,[operand_register0]\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,0xff\r
+       ja      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     ah,7\r
+       ja      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       mov     al,dl\r
+       or      ah,0x20\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+    .reg_reg:\r
+       ;special case for 'mov lreg,lreg'\r
+       ;if:\r
+       ;1. UAL\r
+       ;2. no S\r
+       ;3. V6T\r
+       ;then use 'cpy reg,reg'\r
+       mov     al,[operand_register0]\r
+       mov     ah,[operand_register2]\r
+       mov     word[operand_registers+0],ax\r
+       test    ax,0x0808                               ;any high registers used?\r
+       jnz     .hreg1_hreg2\r
+       test    [code_type],CPU_ACTIVITY_THUMB_UAL\r
+       jz      .lreg1_lreg2                            ;encode the lreg version 'adds reg,reg,0'\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     .lreg1_lreg2                            ;encode the lreg version 'adds reg,reg,0'\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v6t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T\r
+       jnz     .hreg1_hreg2\r
+    .lreg1_lreg2:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x1c\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_reg.32\r
+    .hreg1_hreg2:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg\r
+    .hreg1_hreg2.do:\r
+       mov     dl,ah\r
+       mov     ah,al\r
+       and     ax,0x0807\r
+       shl     ah,4\r
+       or      al,ah\r
+       shl     dl,3\r
+       or      al,dl\r
+       mov     ah,0x46\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       cmp     [operand_register0],0xf\r
+       jnz     .T2\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+    .T2:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     cl,0x55\r
+       call    THUMB2_check_bad_regs\r
+       jnc     .T2.do\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     THUMB_post_process\r
+       mov     cl,0x11                                 ;mov rx,{sp|pc} is allowed\r
+       call    THUMB2_check_bad_regs\r
+       jnc     .T2.do\r
+       mov     cl,0x45                                 ;mov sp,rx is allowed\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+    .T2.do:\r
+       mov     edx,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register2]\r
+       or      edx,eax\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       setnz   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,20\r
+       or      edx,ecx\r
+       or      edx,1 shl 27 + 1 shl 25\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .reg_reg_shift_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_ROR\r
+       jnz     .not_ror\r
+       cmp     [immediate_value],0\r
+       jnz     THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       mov     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+    .not_ror:\r
+       call    ARM_check_shift_range\r
+       movzx   eax,[instruction_shift_op]\r
+       mov     ecx,0 shl 11\r
+       mov     edx,1 shl 11\r
+       cmp     al,ARM_SHIFT_OPCODE_LSR\r
+       cmovz   ecx,edx\r
+       mov     edx,2 shl 11\r
+       cmp     al,ARM_SHIFT_OPCODE_ASR\r
+       cmovz   ecx,edx\r
+       mov     al,[operand_register0]\r
+       mov     ah,[operand_register2]\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     al,7\r
+       ja      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     ah,7\r
+       ja      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,ch\r
+       mov     edx,[immediate_value]\r
+       and     edx,0x1f\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+    .reg_reg_shift_reg:\r
+       mov     eax,[operand_registers]\r
+       mov     ecx,eax\r
+       shr     eax,8\r
+       mov     al,cl\r
+       mov     [operand_registers],eax\r
+       movzx   eax,[instruction_shift_op]\r
+       mov     dx,THUMB_INSTRUCTION_OPCODE_LSL\r
+       mov     cx,THUMB_INSTRUCTION_OPCODE_LSR\r
+       cmp     al,ARM_SHIFT_OPCODE_LSR\r
+       cmovz   dx,cx\r
+       mov     cx,THUMB_INSTRUCTION_OPCODE_ASR\r
+       cmp     al,ARM_SHIFT_OPCODE_ASR\r
+       cmovz   dx,cx\r
+       mov     cx,THUMB_INSTRUCTION_OPCODE_ROR\r
+       cmp     al,ARM_SHIFT_OPCODE_ROR\r
+       cmovz   dx,cx\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .reg_reg_shift_reg.32\r
+       mov     [thumb16_error],ERROR_dest_and_source_must_be_the_same\r
+       mov     eax,[operand_registers]\r
+       cmp     ah,al                                   ;rd=rn?\r
+       jnz     .reg_reg_shift_reg.32\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       shr     eax,8\r
+       cmp     al,7\r
+       ja      .reg_reg_shift_reg.32\r
+       cmp     ah,7\r
+       ja      .reg_reg_shift_reg.32\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x40\r
+       shl     edx,6\r
+       or      eax,edx\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .reg_reg_shift_reg.32:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     edx,0xfa00f000\r
+       movzx   eax,[instruction_shift_op]\r
+       shl     eax,21\r
+       or      edx,eax\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      edx,eax\r
+       movzx   eax,[operand_register2]\r
+       or      edx,eax\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       setnz   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,20\r
+       or      edx,ecx\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_rd_rn_shifter_ORN:\r
+       ;used by ORN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                                              ; 0=reg,imm             alternate for reg,reg,imm\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\                         ; 1=reg,byte,rot        alternate for reg,reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                         ; 2=reg,reg             alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\                             ; 3=reg,reg,rrx         alternate for reg,reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\                  ; 4=reg,reg,shift imm   alternate for reg,reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg>,\             ; 5=reg,reg,shift reg   alternate for reg,reg,reg,shift reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm>,\                                ; 6=reg,reg,imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\           ; 7=reg,reg,byte,rot\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\                           ; 8=reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_rrx_op>,\               ; 9=reg,reg,reg,rrx\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\    ;10=reg,reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_base_reg> ;11=reg,reg,reg,shift reg\r
+       cmp     al,6\r
+       jae     .encode_instruction\r
+       mov     edx,[operand_registers]\r
+       movzx   ecx,dl\r
+       shl     edx,8\r
+       or      edx,ecx\r
+       mov     [operand_registers],edx\r
+       add     al,6\r
+    .encode_instruction:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       cmp     al,6\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_imm\r
+       cmp     al,7\r
+       jz      ERROR_byte_rotation_in_thumb\r
+       cmp     al,8\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg.32\r
+       cmp     al,9\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_rrx\r
+       cmp     al,10\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg_shift_imm\r
+       cmp     al,11\r
+       jz      THUMB_post_process\r
+       ud2\r
+\r
+THUMB_MUL_rd_rm_rs:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m\r
+       mov     al,[operand_register0]\r
+       mov     cl,[operand_register1]\r
+       mov     ah,[operand_register2]\r
+       cmp     al,cl\r
+       jz      .encode_al_ah\r
+       xchg    cl,ah\r
+    .encode_al_ah:\r
+    ;v6t allows rd=rs\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v6t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T\r
+       jnz     .encode\r
+       cmp     al,ah\r
+       jz      ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m\r
+    .encode:\r
+       mov     [thumb16_error],ERROR_dest_and_source_must_be_the_same\r
+       cmp     al,cl\r
+       jnz     ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ax,0x0808\r
+       jnz     ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m\r
+       shl     ah,3\r
+       or      al,ah\r
+       mov     ah,0x40\r
+       or      eax,THUMB_INSTRUCTION_OPCODE_MUL shl 6\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn.7m\r
+\r
+;      Branch Length   Condition       matched?        b.n cc  b.n     b.w cc  b.w     T16 is BCC      T32 is BCC\r
+;      <0x7f           al              x               x       Plain   x       Plain   n               n\r
+;      <0x7ff          al              x               x       Plain   x       Plain   n               n\r
+;      <0xfffff        al              x               x       x       x       Plain   x               n\r
+;      <0xffffff       al              x               x       x       x       Plain   x               n\r
+;      <0x7f           mi              n               Plain   x       Plain   x       y               y\r
+;      <0x7ff          mi              n               x       New IT  Plain   x       n               y\r
+;      <0xfffff        mi              n               x       x       Plain   x       x               y\r
+;      <0xffffff       mi              n               x       x       x       New IT  x               n\r
+;      <0x7f           mi              y               x       Extend  x       Extend  n               n\r
+;      <0x7ff          mi              y               x       Extend  x       Extend  n               n\r
+;      <0xfffff        mi              y               x       x       x       Extend  x               n\r
+;      <0xffffff       mi              y               x       x       x       Extend  x               n\r
+\r
+THUMB_B_target:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     ecx,[addressing_space]\r
+       mov     ecx,[ecx+0x00]\r
+       add     ecx,[immediate_value]\r
+       sub     ecx,edi\r
+       sub     ecx,4\r
+       cmp     [value_undefined],0\r
+       jz      .offset_okay\r
+       xor     ecx,ecx\r
+    .offset_okay:\r
+       sar     ecx,1\r
+       jc      .not_aligned\r
+       mov     [thumb16_error],ERROR_relative_jump_out_of_range\r
+       mov     [thumb32_error],ERROR_relative_jump_out_of_range\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21\r
+       cmp     edx,8 shl 21\r
+       jz      .linked\r
+       mov     al,4\r
+       irp     v,7,10,19,23 {                          ;Bcc.n, B.n, Bcc.w, B.w\r
+               cmp     ecx,1 shl v\r
+               setl    dl\r
+               cmp     ecx,-(1 shl v)\r
+               setge   dh\r
+               and     dl,dh\r
+               sub     al,dl\r
+       }                                               ;al=branch distance 0-4\r
+       cmp     al,4                                    ;branch too far?\r
+       jae     THUMB_post_process\r
+       mov     ah,[instruction_condition]\r
+       and     ah,0xf0\r
+       cmp     ah,0xe0\r
+       jae     .unconditional_16\r
+       push    eax ecx\r
+       call    THUMB_query_condition_match\r
+       pop     ecx eax\r
+       jnc     .unconditional_16\r
+       cmp     al,2\r
+       je      .conditional_32\r
+       cmp     al,0\r
+       je      .conditional_16\r
+       dec     ecx                                     ;adjust for IT block inclusion\r
+       cmp     al,3\r
+       je      .unconditional_32\r
+       inc     ecx                                     ;adjust for no IT block inclusion\r
+       cmp     ecx,-(1 shl 10)                         ;can fit into narrow branch?\r
+       jle     .conditional_32\r
+       dec     ecx                                     ;adjust for IT block inclusion\r
+    ;set unconditional 16\r
+       mov     edx,ecx\r
+       and     edx,0x7ff\r
+       or      dh,0xe0\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       inc     ecx                                     ;adjust for no IT block inclusion\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jnz     .conditional_32\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       jmp     .conditional_32\r
+    .conditional_16:\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_IS_BCC\r
+       mov     dl,cl\r
+       mov     dh,ah\r
+       shr     dh,4\r
+       or      dh,0xd0\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jnz     .conditional_32\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+    .conditional_32:\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT + THUMB_FLAG_IS_BCC\r
+       xor     edx,edx\r
+       mov     dl,ah\r
+       shl     edx,22-4\r
+    ;imm11\r
+       mov     eax,ecx\r
+       and     eax,0x7ff\r
+       or      edx,eax\r
+    ;imm6\r
+       mov     eax,ecx\r
+       and     eax,0x3f shl 11\r
+       shl     eax,16-11\r
+       or      edx,eax\r
+    ;j1\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+6)\r
+       shr     eax,11+6-13\r
+       or      edx,eax\r
+    ;j2\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+6+1)\r
+       shr     eax,11+6+1-11\r
+       or      edx,eax\r
+    ;s\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+6+1+1)\r
+       shl     eax,26-(11+6+1+1)\r
+       or      edx,eax\r
+       or      edx,0xf0008000\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       jmp     THUMB_post_process\r
+    .unconditional_16:\r
+       cmp     al,1\r
+       ja      .unconditional_32\r
+       mov     edx,ecx\r
+       and     edx,0x7ff\r
+       or      dh,0xe0\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jnz     .unconditional_32\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+    .unconditional_32:\r
+       mov     edx,0xf0009000\r
+       mov     [thumb32_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jnz     .encode_b_bl\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+    .encode_b_bl:\r
+    ;imm11\r
+       mov     eax,ecx\r
+       and     eax,0x7ff\r
+       or      edx,eax\r
+    ;imm10\r
+       mov     eax,ecx\r
+       and     eax,0x3ff shl 11\r
+       shl     eax,16-11\r
+       or      edx,eax\r
+    ;j2\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+10)\r
+       shr     eax,11+10-11\r
+       or      edx,eax\r
+    ;j1\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+10+1)\r
+       shr     eax,11+10+1-13\r
+       or      edx,eax\r
+    ;s\r
+       mov     eax,ecx\r
+       and     eax,1 shl (11+10+1+1)\r
+       shl     eax,26-(11+10+1+1)\r
+       or      edx,eax\r
+    ;fixup i1 and i2\r
+       sar     ecx,31                                  ;get the sign\r
+       not     ecx\r
+       and     ecx,1 shl 13 + 1 shl 11\r
+       xor     edx,ecx\r
+       mov     [thumb32_instruction],edx\r
+       jmp     THUMB_post_process\r
+    .linked:\r
+       mov     ah,[instruction_condition]\r
+       and     ah,0xf0\r
+       cmp     ah,0xe0\r
+       jae     .unconditional_linked\r
+       push    eax ecx\r
+       call    THUMB_query_condition_match\r
+       pop     ecx eax\r
+       setc    dl\r
+       movzx   edx,dl\r
+       sub     ecx,edx                                 ;adjust for IT block\r
+    .unconditional_linked:\r
+       cmp     ecx,1 shl 23\r
+       jge     THUMB_post_process                      ;use default error of out of range\r
+       cmp     ecx,-(1 shl 23)\r
+       jl      THUMB_post_process                      ;use default error of out of range\r
+       mov     [thumb32_error],0\r
+       mov     edx,0xf000d000\r
+       cmp     ecx,1 shl 21\r
+       setl    al\r
+       cmp     ecx,-(1 shl 21)\r
+       setge   ah\r
+       and     al,ah\r
+       jnz     .check_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jnz     .encode_b_bl\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_6m\r
+       jmp     .encode_b_bl\r
+    .check_v4t:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jnz     .encode_b_bl\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_v4t\r
+       jmp     .encode_b_bl\r
+    .not_aligned:\r
+       mov     [thumb16_error],ERROR_relative_jump_not_aligned\r
+       mov     [thumb32_error],ERROR_relative_jump_not_aligned\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rm:\r
+       ;used by BX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>                                 ;0=rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      ERROR_requires_cpu_capability_arm_v4t\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_rm\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+\r
+THUMB_rm:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     al,[operand_register0]\r
+       shl     al,3\r
+       mov     ah,0x47\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_rn_address4:\r
+       ;used by LDM, STM\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .T2\r
+       cmp     [operand_register0],8                   ;<r8\r
+       jae     .check_v4\r
+       mov     [thumb16_error],ERROR_instruction_not_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jnz     .T2\r
+    .check_v4:\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       ;if LDM and reg is in set then must be rn,{..}\r
+       ;if STM then reg in set can only be first register\r
+       cmp     [operand_register0],13                  ;SP\r
+       jz      .high_reg_okay\r
+       test    [operand_register0],8                   ;high reg?\r
+       jnz     .T2\r
+    .high_reg_okay:\r
+       test    ebp,1 shl 20                            ;1=LDM\r
+       jz      .check_list_stm\r
+       movzx   ecx,[operand_register0]\r
+       bt      [reg_list_bitmap],ecx\r
+       jnc     .check_rn!_list\r
+       test    [code_type],CPU_ACTIVITY_THUMB_UAL\r
+       jz      .check_rn!_list\r
+       cmp     al,0                                    ;0=rn,{..}\r
+       jz      .do_16\r
+       jmp     .T2\r
+    .check_rn!_list:\r
+       cmp     al,2                                    ;2=rn!,{..}\r
+       jz      .do_16\r
+       jmp     .T2\r
+    .check_list_stm:\r
+       cmp     al,2                                    ;2=rn!,{..}\r
+       jnz     .T2\r
+       movzx   ecx,[operand_register0]\r
+       bt      [reg_list_bitmap],ecx\r
+       jnc     .do_16\r
+       bsf     edx,[reg_list_bitmap]\r
+       cmp     ecx,edx\r
+       jnz     .T2\r
+    .do_16:\r
+       cmp     [operand_register0],13                  ;SP\r
+       jz      THUMB_address4\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21\r
+       cmp     edx,4 shl 21                            ;IA version of LDM & STM?\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       jnz     .T2\r
+       mov     cl,[operand_register0]\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       cmp     cl,7\r
+       ja      .T2\r
+       mov     edx,[reg_list_bitmap]\r
+       test    edx,0xff00\r
+       mov     [thumb16_error],ERROR_high_base_registers_not_allowed_in_list\r
+       jnz     .T2\r
+       mov     dh,cl\r
+       or      dh,0xc0\r
+       bt      ebp,20                                  ;1=LDM, 0=STM\r
+       jnc     .store\r
+       or      dh,0x8\r
+    .store:\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       bt      ebp,20                                  ;1=LDM, 0=STM\r
+       jnc     .T2\r
+       mov     edx,[reg_list_bitmap]\r
+       dec     edx\r
+       and     edx,[reg_list_bitmap]\r
+       jnz     .T2\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     edx,0xf8500b04\r
+       mov     eax,0xf8d00000\r
+       bsr     ecx,[reg_list_bitmap]\r
+       cmp     cl,[operand_register0]\r
+       cmovz   edx,eax\r
+       shl     ecx,12\r
+       or      edx,ecx\r
+       movzx   ecx,[operand_register0]\r
+       shl     ecx,16\r
+       or      edx,ecx\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .T2_2:\r
+       mov     al,2\r
+    .T2:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       ;only IA and DB are valid, bit24 <> bit23\r
+       lea     ecx,[ebp*2]\r
+       xor     ecx,ebp\r
+       test    ecx,1 shl 24\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       jz      THUMB_post_process\r
+       cmp     al,0\r
+       jz      .rn_list\r
+       cmp     al,1\r
+       jz      .rn_list_t\r
+       cmp     al,2\r
+       jz      .rn!_list\r
+       cmp     al,3\r
+       jz      .rn!_list_t\r
+       ud2\r
+    .rn!_list:\r
+       or      [thumb32_instruction],1 shl 21\r
+       movzx   eax,[operand_register0]\r
+       bt      [reg_list_bitmap],eax\r
+       mov     [thumb32_error],ERROR_destination_register_not_allowed_in_list\r
+       jc      THUMB_post_process\r
+    .rn_list:\r
+       mov     eax,[reg_list_bitmap]\r
+       lea     ecx,[eax-1]\r
+       and     eax,ecx\r
+       jz      .small_set\r
+       cmp     [operand_register0],0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       test    [reg_list_bitmap],1 shl 13\r
+       jnz     ERROR_sp_in_set\r
+       test    ebp,1 shl 20                            ;1=LDM, 0=STM\r
+       jnz     .T2_LDM_checks\r
+       test    [reg_list_bitmap],1 shl 15\r
+       jnz     ERROR_pc_in_set\r
+       jmp     .encode\r
+    .T2_LDM_checks:\r
+       cmp     [reg_list_bitmap],0xc000\r
+       jae     ERROR_invalid_set_with_lr_pc\r
+       test    [reg_list_bitmap],1 shl 15\r
+       jz      .encode\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+    .encode:\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       or      ebp,[reg_list_bitmap]\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .rn!_list_t:\r
+    .rn_list_t:\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       jmp     THUMB_post_process\r
+    .small_set:\r
+       ;convert to ldr/str for a register set of 1\r
+       mov     eax,[reg_list_bitmap]\r
+       mov     ebp,[thumb32_instruction]\r
+       bsf     eax,eax\r
+       mov     ah,[operand_register0]\r
+       mov     word[operand_registers+0],ax\r
+       ;IA  = [reg]     type 0\r
+       ;IA! = [reg],4   type 1\r
+       ;DB  = [reg,-4]  type 2\r
+       ;DB! = [reg,-4]! type 3\r
+       mov     ecx,ebp\r
+       and     ebp,1 shl 20\r
+       or      ebp,0xf8400000                          ;LDR/STR\r
+       mov     [thumb32_instruction],ebp\r
+       and     ecx,1 shl 23 + 1 shl 21\r
+       mov     [immediate_value],0\r
+       mov     al,0\r
+       cmp     ecx,1 shl 23 + 0 shl 21                 ;IA\r
+       jz      THUMB2_rd_address.do\r
+       mov     [immediate_value],4\r
+       mov     al,1\r
+       cmp     ecx,1 shl 23 + 1 shl 21                 ;IA!\r
+       jz      THUMB2_rd_address.do\r
+       mov     [immediate_value],-4\r
+       mov     al,2\r
+       cmp     ecx,0 shl 23 + 0 shl 21                 ;DB\r
+       jz      THUMB2_rd_address.do\r
+       mov     al,3                                    ;DB!\r
+       jmp     THUMB2_rd_address.do\r
+\r
+THUMB_address4:\r
+       ;used by POP, PUSH\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      THUMB_rn_address4.T2_2\r
+       mov     edx,[arm_instruction]\r
+       and     edx,0xf shl 21\r
+       shr     edx,21\r
+       mov     eax,[reg_list_bitmap]\r
+       bt      ebp,20                                  ;1=POP, 0=PUSH\r
+       jc      .pop\r
+    ;push\r
+       cmp     dl,0x8                                  ;DB version of STM?\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       jnz     THUMB_rn_address4.T2_2\r
+       test    ax,not 0x40ff                           ;LR with STM\r
+       mov     [thumb16_error],ERROR_high_base_registers_not_allowed_in_list.not_lr\r
+       jnz     THUMB_rn_address4.T2_2\r
+       mov     ch,0xb4\r
+       jmp     .encode\r
+    .pop:\r
+       cmp     dl,0x4                                  ;IA version of LDM?\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       jnz     THUMB_rn_address4.T2_2\r
+       test    ax,not 0x80ff                           ;PC with LDM\r
+       mov     [thumb16_error],ERROR_high_base_registers_not_allowed_in_list.not_pc\r
+       jnz     THUMB_rn_address4.T2_2\r
+       mov     ch,0xbc\r
+       test    [reg_list_bitmap],1 shl 15\r
+       jz      .encode\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+    .encode:\r
+       test    ah,ah\r
+       setnz   cl\r
+       or      ch,cl\r
+       mov     ah,ch\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_rn_address4.T2_2\r
+\r
+THUMB_immediate8:\r
+       ;used by SWI\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      ERROR_requires_cpu_capability_arm_v4t\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      THUMB_post_process\r
+       mov     ah,0xdf\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v5\r
+\r
+ARM_immediate16:\r
+       ;used by BKPT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       call    BKPT_force_condition_match\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_immediate8\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x0000ffff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0xf\r
+       and     ecx,0xfff0\r
+       shl     ecx,4\r
+       or      eax,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0xffff\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_immediate8:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5T\r
+       jz      ERROR_requires_cpu_capability_arm_v5t\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      THUMB_post_process\r
+       mov     ah,0xbe\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_Xtarget:\r
+       ;used by BLX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_address>,\                                ;0=imm  PC relative\r
+       <TMPL_base_reg>                                 ;1=rm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_Xtarget\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+       cmp     al,0\r
+       jz      .address\r
+       cmp     al,1\r
+       jz      .rm\r
+       ud2\r
+    .address:\r
+       mov     eax,[addressing_space]\r
+       mov     eax,[eax+0x00]\r
+       add     eax,[immediate_value]\r
+       sub     eax,edi\r
+       sub     eax,8\r
+       test    eax,1\r
+       jnz     .not_aligned\r
+       cmp     eax,1 shl 25\r
+       jge     .jump_out_of_range\r
+       cmp     eax,-(1 shl 25)\r
+       jl      .jump_out_of_range\r
+       shr     eax,2\r
+       setc    cl\r
+       or      cl,0xfa\r
+       and     eax,0x00ffffff\r
+       or      ebp,eax\r
+       shl     ecx,24\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .jump_out_of_range:\r
+       mov     ecx,ERROR_relative_jump_out_of_range\r
+       jmp     ARM_store_instruction_with_error\r
+    .not_aligned:\r
+       mov     ecx,ERROR_relative_jump_not_aligned\r
+       jmp     ARM_store_instruction_with_error\r
+    .rm:\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15                                  ;PC?\r
+       je      ERROR_r15_not_valid\r
+       or      ebp,eax\r
+       or      ebp,0x012fff30\r
+       jmp     ARM_store_instruction\r
+    .THUMB_Xtarget:\r
+       cmp     al,1\r
+       jz      .rm32\r
+       mov     [thumb32_error],ERROR_instruction_not_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jnz     THUMB_post_process\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       btr     ecx,1\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       sub     ecx,4\r
+       test    ecx,3\r
+       jnz     .not_aligned32\r
+       sar     ecx,1\r
+       mov     [thumb32_error],ERROR_relative_jump_out_of_range\r
+       cmp     ecx,1 shl 23\r
+       jge     THUMB_post_process\r
+       cmp     ecx,-(1 shl 23)\r
+       jl      THUMB_post_process\r
+       mov     [thumb32_error],0\r
+       mov     edx,0xf000c000\r
+       cmp     ecx,1 shl 21\r
+       setl    al\r
+       cmp     ecx,-(1 shl 21)\r
+       setge   ah\r
+       and     al,ah\r
+       jnz     .check_x\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jnz     THUMB_B_target.encode_b_bl\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_t2\r
+       jmp     THUMB_B_target.encode_b_bl\r
+    .check_x:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_X\r
+       jnz     THUMB_B_target.encode_b_bl\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_x\r
+       jmp     THUMB_B_target.encode_b_bl\r
+    .rm32:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v5t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5T\r
+       jz      THUMB_post_process\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15                                  ;PC?\r
+       je      ERROR_r15_not_valid\r
+       shl     eax,3\r
+       or      eax,0x4780\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+    .not_aligned32:\r
+       mov     [thumb32_error],ERROR_relative_jump_not_aligned\r
+       jmp     THUMB_post_process\r
+\r
+ARM_nop:\r
+       ;used by NOP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_nop\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_K\r
+       jnz     ARM_store_instruction\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V1\r
+       jz      ERROR_requires_cpu_capability_arm_v1\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,24\r
+       or      ebp,0x01a00000                          ;movcc r0,r0\r
+       jmp     ARM_store_instruction\r
+    .THUMB_nop:\r
+       mov     [thumb16_instruction],0xbf00            ;nop.n\r
+       mov     [thumb16_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jnz     .32\r
+       mov     [thumb16_instruction],0x46C0            ;mov r8,r8\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jnz     .32\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+    .32:\r
+       mov     [thumb32_instruction],0xf3af8000        ;nop.w\r
+       mov     [thumb32_error],0\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_CLZ:\r
+       ;used by CLZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;0=rd,rm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm_CLZ\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V5\r
+       jz      ERROR_requires_cpu_capability_arm_v5\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15                                  ;PC?\r
+       je      ERROR_r15_not_valid.first\r
+       movzx   ecx,[operand_register1]\r
+       cmp     ecx,15                                  ;PC?\r
+       je      ERROR_r15_not_valid.second\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm_CLZ:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     cl,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     edx,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       or      edx,eax\r
+       shl     eax,16\r
+       or      edx,eax\r
+       mov     [thumb32_instruction],edx\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;E\r
+\r
+ARM_rd_rm_rn:\r
+       ;used by QADD, QSUB, QDADD, QDSUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=rdm,rn       alternate for rd,rm,rn\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=rd,rm,rn\r
+       cmp     al,0\r
+       jnz     .registers_defined\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     cl,ch\r
+       mov     [operand_registers],ecx\r
+    .registers_defined:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm_rn\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_E\r
+       jz      ERROR_requires_cpu_capability_arm_e\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.all\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm_rn:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_rs_rn_E:\r
+       ;used by SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rd,rm,rs,rn\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm_rn_ra\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_E\r
+       jz      ERROR_requires_cpu_capability_arm_e\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.fourth\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm_rn_ra:\r
+       ;used by SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     cl,0xff\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;ra\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rdlo_rdhi_rm_rs_E:\r
+       ;used by SMLALBB, SMLALBT, SMLALTB, SMLALTT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rdlo,rdhi,rm,rs\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rdlo_rdhi_rm_rs.THUMB_rdlo_rdhi_rn_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_E\r
+       jz      ERROR_requires_cpu_capability_arm_e\r
+       movzx   eax,[operand_register0]                 ;rdlo\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rdhi\r
+       shl     eax,16\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.fourth\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       mov     al,[operand_register0]                  ;rdlo\r
+       mov     ah,[operand_register1]                  ;rdhi\r
+       cmp     al,ah\r
+       jz      ERROR_destination_registers_must_differ\r
+       jmp     ARM_store_instruction\r
+\r
+ARM_rd_rm_rs_E:\r
+       ;used by SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=rdm,rs\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=rd,rm,rs\r
+       cmp     al,0\r
+       jnz     .registers_defined\r
+       mov     ax,word[operand_registers+0]\r
+       mov     word[operand_registers+1],ax\r
+    .registers_defined:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rd_rm_rs_rn_E.THUMB_rd_rm_rn_ra\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_E\r
+       jz      ERROR_requires_cpu_capability_arm_e\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,16\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+\r
+;P\r
+\r
+ARM_copro_op1_rd_rn_crm:\r
+       ;used by MCRR, MRRC, MCRR2, MRRC2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_sel,TMPL_copro_opcode1,TMPL_base_reg,TMPL_base_reg,TMPL_cpro_reg>    ;0=copro,op1,rd,rn,crm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .check_v7m\r
+       cmp     ebp,0xf shl 28                          ;MCRR2 or MRRC2?\r
+       jae     .check_v6\r
+       jmp     .check_p\r
+    .check_v7m:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       jmp     .version_check_okay\r
+    .check_p:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_P\r
+       jz      ERROR_requires_cpu_capability_arm_p\r
+       jmp     .version_check_okay\r
+    .check_v6:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+    .version_check_okay:\r
+       movzx   eax,[operand_register0]                 ;cpnum\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode1]                     ;op1\r
+       cmp     eax,15\r
+       ja      .out_of_range\r
+       shl     eax,4\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.fourth\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;crm\r
+       or      ebp,eax\r
+       test    ebp,1 shl 20                            ;MRRC?\r
+       jz      ARM_post_process_copro\r
+       movzx   eax,word[operand_register1]             ;rd,rn\r
+       cmp     al,ah\r
+       jz      ERROR_destination_registers_must_differ\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_opcode4_out_of_range\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+ARM_address2:\r
+       ;used by PLD, PLDW, PLI\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_address\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                          ;0=[rn]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                 ;1=[rn,imm]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                         ;2=[rn,+-rm]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\  ;3=[rn,+-rm,shift imm]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_rrx_op,TMPL_bracket_right>,\             ;4=[rn,+-rm,rrx]\r
+       <TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                           ;5=[imm]        PC relative\r
+       <TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                                          ;6=[exp]        implicit reg from structure\r
+       test    ebp,1 shl 24                            ;PLI=1?\r
+       jnz     .check_v7\r
+       test    ebp,1 shl 22                            ;PLDW=0?\r
+       jnz     .check_P\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_MP\r
+       jz      ERROR_requires_cpu_capability_arm_mp\r
+       cmp     [operand_register0],0xf\r
+       jz      ERROR_r15_not_valid.base\r
+       jmp     .version_check_okay\r
+    .check_v7:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      ERROR_requires_cpu_capability_arm_v7\r
+       jmp     .version_check_okay\r
+    .check_P:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_P\r
+       jz      ERROR_requires_cpu_capability_arm_p\r
+    .version_check_okay:\r
+       or      ebp,0xf shl 28\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     cl,0xf\r
+       mov     [operand_registers],ecx\r
+       cmp     al,0\r
+       jz      ARM_rd_address2.rd_q_rn_p\r
+       cmp     al,1\r
+       jz      ARM_rd_address2.rd_q_rn_imm_p\r
+       cmp     al,2\r
+       jz      ARM_rd_address2.rd_q_rn_PMrm_p\r
+       cmp     al,3\r
+       jz      ARM_rd_address2.rd_q_rn_PMrm_shift_imm_p\r
+       cmp     al,4\r
+       jz      ARM_rd_address2.rd_q_rn_PMrm_rrx_p\r
+       cmp     al,5\r
+       jz      ARM_rd_address2.rd_q_imm_p\r
+       cmp     al,6\r
+       jz      ARM_rd_address2.rd_q_exp_p\r
+       ud2\r
+\r
+THUMB2_address:\r
+       ;used by PLD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                          ;0(0)=[rn]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                 ;1(2)=[rn,imm]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                         ;2(4)=[rn,rm]\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm2,TMPL_bracket_right>,\ ;3(5)=[rn,rm,shift imm]\r
+       <TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                           ;4(6)=[imm]     PC relative\r
+       <TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                                          ;5(7)=[exp]     implicit reg from structure\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       or      ecx,8                                   ;fake rd as r8 to prevent 16bit code generation\r
+       mov     [operand_registers],ecx\r
+       add     al,2\r
+       cmp     al,3\r
+       ja      THUMB2_rd_address.do\r
+       dec     al\r
+       shr     al,1\r
+       add     al,al\r
+       jmp     THUMB2_rd_address.do\r
+\r
+;J\r
+\r
+ARM_rm_J:\r
+       ;used by BXJ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>                                 ;0=rm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rm_j\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_J\r
+       jz      ERROR_requires_cpu_capability_arm_j\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rm_j:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     ecx,0x11\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v6\r
+\r
+ARM_mode:\r
+       ;used by CPS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm5\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_mode\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0x1f\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_mode:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_iflags_mode:\r
+       ;used by CPSID, CPSIE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iflags>,\                                 ;0=flags\r
+       <TMPL_iflags,TMPL_imm>                          ;1=flags,mode\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_iflags_mode\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       cmp     al,1\r
+       jnz     .iflags\r
+    .iflags_mode:\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      .out_of_range\r
+       or      ebp,1 shl 17\r
+       or      ebp,eax\r
+    .iflags:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,6\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0x1f\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_iflags_mode:\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_7m\r
+       cmp     al,1\r
+       jz      .T2\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_ALIGN\r
+       jnz     .THUMB_iflags_aif\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_align\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jnz     .THUMB_iflags_if\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jnz     .THUMB_iflags_i\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_6m\r
+       jmp     .T2\r
+    .THUMB_iflags_i:\r
+       test    [operand_register0],101b\r
+       jnz     .T2\r
+    .THUMB_iflags_if:\r
+       test    [operand_register0],100b\r
+       jnz     .T2\r
+    .THUMB_iflags_aif:\r
+       mov     ebp,0xb660\r
+       mov     ecx,[arm_instruction]\r
+       and     ecx,1 shl 18\r
+       shr     ecx,18-4\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register0]\r
+       or      ebp,ecx\r
+       mov     [thumb16_instruction],bp\r
+       mov     [thumb16_error],0\r
+    .T2:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_t2\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       cmp     al,1\r
+       jnz     .T2_iflags\r
+    .T2_iflags_mode:\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      THUMB_post_process\r
+       or      ebp,1 shl 8\r
+       or      ebp,eax\r
+    .T2_iflags:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_CPY:\r
+       ;used by CPY\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;0=reg,reg\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       mov     al,2\r
+       jnz     ARM_rd_shifter.do\r
+    .THUMB_rd_rm:\r
+       mov     ax,word[operand_registers+0]\r
+       mov     [operand_register2],ah\r
+       test    ax,0x0808                               ;any high registers used?\r
+       jnz     THUMB_MOV_rd_rn_shifter.hreg1_hreg2\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v6t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T\r
+       jz      THUMB_GEN_rd_rn_shifter.reg_reg_reg\r
+       jmp     THUMB_MOV_rd_rn_shifter.hreg1_hreg2.do\r
+\r
+ARM_rd_q_rn_p:\r
+       ;used by LDREX, LDREXB, LDREXH, LDA, LDAB, LDAH, LDAEX, LDAEXB, LDAEXH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\            ;0=reg,[reg]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\   ;1=reg,[reg,imm] (for T2 ldrex only)\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>            ;2=reg,[exp]     (for T2 ldrex only)\r
+       test    ebp,1 shl 8\r
+       jnz     .not_v8\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .version_okay\r
+       cmp     [immediate_value],0\r
+       jnz     ERROR_immediate_cannot_be_encoded\r
+       jmp     .THUMB_version_okay\r
+    .not_v8:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_q_rn_imm_p\r
+       test    ebp,3 shl 21                            ;LDREXB or LDREXH?\r
+       jz      .check_v6\r
+    .check_v6k:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_K\r
+       jz      ERROR_requires_cpu_capability_arm_k\r
+       jmp     .version_okay\r
+    .check_v6:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+    .version_okay:\r
+       cmp     [immediate_value],0\r
+       jnz     ERROR_immediate_cannot_be_encoded\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_q_rn_imm_p:\r
+       test    ebp,3 shl 21                            ;LDREXB or LDREXH (!=0)?\r
+       jz      .check_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_SYNC\r
+       jz      ERROR_requires_cpu_capability_arm_sync\r
+       cmp     [immediate_value],0\r
+       jnz     ERROR_immediate_cannot_be_encoded\r
+       jmp     .THUMB_version_okay\r
+    .check_7m:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+    .THUMB_version_okay:\r
+       mov     cl,0x13\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       test    eax,not (0xff shl 2)\r
+       jnz     THUMB_post_process\r
+       shr     eax,2\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rn_rm_shift_imm:\r
+       ;used by PKHBT, PKHTB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                                         ;0=reg,reg              alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\                  ;1=reg,reg,shift imm    alternate for reg,reg,reg,shift imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\                           ;2=reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>      ;3=reg,reg,reg,shift imm\r
+       cmp     al,2\r
+       jae     .do\r
+       mov     cx,word[operand_register0]\r
+       mov     word[operand_register1],cx\r
+    .do:\r
+       test    ebp,1 shl 6\r
+       jz      .lsl\r
+       test    al,1\r
+       jnz     .asr\r
+    ;convert to pkhbt rd,rm,rn\r
+    .convert:\r
+       mov     ax,word[operand_register1]\r
+       xchg    ah,al\r
+       mov     word[operand_register1],ax\r
+       and     ebp,not (1 shl 6)\r
+       and     [thumb32_instruction],not (1 shl 5)\r
+       jmp     .encode\r
+    .asr:\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_ASR\r
+       jnz     ERROR_shift_type_must_be_ASR\r
+       mov     eax,[immediate_value]\r
+       sub     eax,1\r
+       jc      .convert\r
+       cmp     eax,31\r
+       ja      ERROR_shift_value_out_of_range.1_32\r
+       inc     eax\r
+       and     eax,0x1f\r
+       mov     [immediate_value],eax\r
+       jmp     .encode\r
+    .lsl:\r
+       cmp     al,0\r
+       jz      .encode\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     ERROR_shift_type_must_be_LSL\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      ERROR_shift_value_out_of_range.0_31\r
+    .encode:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_encode\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       mov     eax,[immediate_value]\r
+       shl     eax,7\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_encode:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,eax\r
+       and     eax,0x3\r
+       and     ecx,0x7 shl 2\r
+       shl     eax,6\r
+       shl     ecx,12-2\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rn_rm:\r
+       ;used by QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX,\r
+       ;        SADD16, SADD8, SADDSUBX, SSUB16, SSUB8, SSUBADDX,\r
+       ;        SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX,\r
+       ;        UADD16, UADD8, UADDSUBX, USUB16, USUB8, USUBADDX,\r
+       ;        UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX,\r
+       ;        UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX,\r
+       ;        SEL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=reg,reg      alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=reg,reg,reg\r
+       cmp     al,0\r
+       jnz     .encode\r
+       mov     ax,word[operand_register0]\r
+       mov     word[operand_register1],ax\r
+    .encode:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rn_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rn_rm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_REV:\r
+       ;used by RBIT, REV, REV16, REVSH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;0=rd,rm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm\r
+       mov     ecx,ebp\r
+       and     ecx,1 shl 22 + 1 shl 7\r
+       cmp     ecx,1 shl 22 + 0 shl 7                  ;RBIT?\r
+       jnz     .check_v6\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       jmp     .ARM_version_okay\r
+    .check_v6:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+    .ARM_version_okay:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm:\r
+       mov     ecx,ebp\r
+       and     ecx,1 shl 22 + 1 shl 7\r
+       cmp     ecx,1 shl 22 + 0 shl 7                  ;RBIT?\r
+       jz      .T2\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v6t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T\r
+       jz      .T2\r
+       mov     eax,ebp\r
+       and     eax,1 shl 7\r
+       and     ebp,1 shl 22\r
+       shr     eax,7-6\r
+       shr     ebp,22-7\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,7\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       ja      .T2\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,7\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       ja      .T2\r
+       shl     eax,3\r
+       or      ebp,eax\r
+       or      ebp,0xba00\r
+       mov     [thumb16_instruction],bp\r
+       mov     [thumb16_error],0\r
+    .T2:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     cl,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       or      ebp,eax\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rn:\r
+       ;used by RFE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>,\                               ;0=rn\r
+       <TMPL_base_reg!>                                ;1=rn!\r
+       movzx   eax,al\r
+       shl     eax,21\r
+       movzx   ecx,[operand_register0]                 ;rn\r
+       cmp     ecx,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,16\r
+       or      ecx,eax                                 ;define W bit\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rn\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rn:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     eax,ebp\r
+       shl     eax,1\r
+       xor     eax,ebp\r
+       test    eax,1 shl 24                            ;bit23 <> bit24?\r
+       jz      ERROR_instruction_not_16bit\r
+       mov     ebp,[thumb32_instruction]\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_endian:\r
+       ;used by SETEND\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_endian>                                   ;0=endian\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_endian\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   eax,[operand_register0]                 ;endian\r
+       shl     eax,9\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_endian:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_ALIGN\r
+       jz      ERROR_requires_cpu_capability_arm_align\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       movzx   ebp,[operand_register0]                 ;endian\r
+       shl     ebp,3\r
+       or      ebp,0xb650\r
+       mov     [thumb16_instruction],bp\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_rs_rn_D:\r
+       ;used by SMLAD, SMLADX, SMLSD, SMLSDX, SMMLA, SMMLAR, SMMLS, SMMLSR, USADA8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rd,rm,rs,rn\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       jmp     ARM_rd_rm_rs_rn.encode\r
+\r
+ARM_rdlo_rdhi_rm_rs_D:\r
+       ;used by SMLALD, SMLALDX, SMLSLD, SMLSLDX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>       ;0=rdlo,rdhi,rm,rs\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rdlo_rdhi_rm_rs.THUMB_rdlo_rdhi_rn_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       jmp     ARM_rdlo_rdhi_rm_rs.encode\r
+\r
+ARM_rd_rm_rs_M:\r
+       ;used by SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, SMUSDX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=rd,rm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=rd,rm,rs\r
+       mov     [operand_register3],0                   ;rn=0\r
+       cmp     al,0\r
+       jnz     .do\r
+       mov     ax,word[operand_registers+0]\r
+       mov     word[operand_registers+1],ax\r
+    .do:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rd_rm_rs_rn.THUMB_rd_rm_rs_rn\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       jmp     ARM_rd_rm_rs_rn.encode\r
+\r
+ARM_reg_mode:\r
+       ;used by SRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>,\                                    ;0=mode\r
+       <TMPL_imm,TMPL_modifier_exclaim>,\              ;1=mode !\r
+       <TMPL_base_reg,TMPL_imm>,\                      ;2=sp,mode\r
+       <TMPL_base_reg!,TMPL_imm>                       ;3=sp!,mode\r
+       cmp     al,2\r
+       jb      .set_mode\r
+       cmp     [operand_register0],13                  ;SP?\r
+       jnz     ERROR_register_out_of_range.must_be_sp\r
+    .set_mode:\r
+       mov     ecx,eax\r
+       and     ecx,1\r
+       shl     ecx,21\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_reg_mode\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       or      ebp,ecx                                 ;define W bit\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0x1f\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_reg_mode:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     eax,ebp\r
+       shl     eax,1\r
+       xor     eax,ebp\r
+       test    eax,1 shl 24                            ;bit23 <> bit24?\r
+       jz      ERROR_instruction_not_16bit\r
+       mov     ebp,[thumb32_instruction]\r
+       or      ebp,ecx\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x1f\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_imm_rm_shift:\r
+       ;used by SSAT, USAT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg>,\                             ;0=reg,imm,reg\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg,TMPL_shift_op,TMPL_imm2>       ;1=reg,imm,reg,shift imm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_imm_rm_shift\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       cmp     ecx,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       cmp     ecx,15\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,ecx\r
+       mov     ecx,[immediate_value]\r
+       test    ebp,1 shl 22                            ;USAT=1?\r
+       setz    dl\r
+       movzx   edx,dl\r
+       sub     ecx,edx\r
+       cmp     ecx,31\r
+       ja      .immediate_value_out_of_range\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       cmp     al,1                                    ;reg,imm,reg,shift imm?\r
+       jnz     ARM_store_instruction\r
+       mov     dl,[instruction_shift_op]\r
+       cmp     dl,ARM_SHIFT_OPCODE_LSL\r
+       jz      .lsl\r
+       cmp     dl,ARM_SHIFT_OPCODE_ASR\r
+       jnz     ERROR_shift_type_must_be_LSL_or_ASR\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_32\r
+       mov     edx,[immediate_value2]\r
+       test    edx,edx\r
+       jz      .lsl\r
+       cmp     edx,32\r
+       ja      ARM_store_instruction_with_error\r
+       and     edx,0x1f\r
+       shl     edx,7\r
+       or      ebp,edx\r
+       or      ebp,1 shl 6\r
+       jmp     ARM_store_instruction\r
+    .lsl:\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_31\r
+       mov     edx,[immediate_value2]\r
+       cmp     edx,31\r
+       ja      ARM_store_instruction_with_error\r
+       shl     edx,7\r
+       or      ebp,edx\r
+       jmp     ARM_store_instruction\r
+    .immediate_value_out_of_range:\r
+       test    ebp,1 shl 22                            ;USAT=1?\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_32\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_31\r
+       cmovnz  ecx,edx\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_rd_imm_rm_shift:\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     cl,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       shl     ecx,8\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_32\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_31\r
+       test    ebp,1 shl 23                            ;USAT=1?\r
+       cmovnz  ecx,edx\r
+       mov     [thumb32_error],ecx\r
+       mov     ecx,[immediate_value]\r
+       setz    dl\r
+       movzx   edx,dl\r
+       sub     ecx,edx\r
+       cmp     ecx,31\r
+       ja      THUMB_post_process\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       cmp     al,1                                    ;reg,imm,reg,shift imm?\r
+       jnz     THUMB_post_process\r
+       mov     dl,[instruction_shift_op]\r
+       cmp     dl,ARM_SHIFT_OPCODE_LSL\r
+       jz      .THUMB_lsl\r
+       cmp     dl,ARM_SHIFT_OPCODE_ASR\r
+       jnz     ERROR_shift_type_must_be_LSL_or_ASR\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.1_31\r
+       mov     edx,[immediate_value2]\r
+       test    edx,edx\r
+       jz      .THUMB_encode_shift\r
+       cmp     edx,31\r
+       ja      THUMB_post_process\r
+       or      ebp,1 shl 21\r
+    .THUMB_encode_shift:\r
+       mov     eax,edx\r
+       and     eax,3\r
+       and     edx,7 shl 2\r
+       shl     eax,6\r
+       shl     edx,12-2\r
+       or      ebp,eax\r
+       or      ebp,edx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .THUMB_lsl:\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.0_31\r
+       mov     edx,[immediate_value2]\r
+       cmp     edx,31\r
+       ja      THUMB_post_process\r
+       jmp     .THUMB_encode_shift\r
+\r
+ARM_rd_imm_rm:\r
+       ;used by SSAT16, USAT16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_base_reg>       ;0=reg,imm,reg\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_imm_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       cmp     ecx,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       cmp     ecx,15\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,ecx\r
+       mov     ecx,[immediate_value]\r
+       test    ebp,1 shl 22                            ;USAT16=1?\r
+       setz    dl\r
+       movzx   edx,dl\r
+       sub     ecx,edx\r
+       cmp     ecx,15\r
+       ja      .immediate_value_out_of_range\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .immediate_value_out_of_range:\r
+       test    ebp,1 shl 22                            ;USAT16=1?\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_16\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_15\r
+       cmovnz  ecx,edx\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_rd_imm_rm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     cl,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       shl     ecx,8\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_16\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_15\r
+       test    ebp,1 shl 23                            ;USAT16=1?\r
+       cmovnz  ecx,edx\r
+       mov     [thumb32_error],ecx\r
+       mov     ecx,[immediate_value]\r
+       setz    dl\r
+       movzx   edx,dl\r
+       sub     ecx,edx\r
+       cmp     ecx,15\r
+       ja      THUMB_post_process\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_q_rn_p_STREX:\r
+       ;used by STREX, STREXB, STREXH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\              ;0=rd,rm,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\     ;1=rd,rm,[rn,imm]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>              ;2=rd,rm,[exp]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_rd_rm_q_rn_p_STREX\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     ARM_store_instruction_with_error\r
+       test    ebp,3 shl 21                            ;STREXB or STREXH?\r
+       jz      .check_v6\r
+    .check_v6k:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_K\r
+       jz      ERROR_requires_cpu_capability_arm_k\r
+       jmp     .version_okay\r
+    .check_v6:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+    .version_okay:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     al,[operand_register0]                  ;rd\r
+       mov     ah,[operand_register1]                  ;rm\r
+       mov     cl,[operand_register2]                  ;rn\r
+       cmp     al,cl\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+       cmp     al,ah\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+       jmp     ARM_store_instruction\r
+\r
+THUMB_rd_rm_q_rn_p_STREX:\r
+       mov     cl,0x37\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_dest_cannot_be_source_or_memory_address\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       movzx   edx,[operand_register2]                 ;rn\r
+       cmp     eax,ecx\r
+       jz      THUMB_post_process\r
+       cmp     eax,edx\r
+       jz      THUMB_post_process\r
+       test    ebp,3 shl 21                            ;STREXB or STREXH?\r
+       mov     ebp,[thumb32_instruction]\r
+       jz      .strex\r
+       ;STREXB or STREXH\r
+       or      ebp,eax\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_SYNC\r
+       jz      ERROR_requires_cpu_capability_arm_sync\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .strex:\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       mov     eax,[immediate_value]\r
+       test    eax,not (0xff shl 2)\r
+       jnz     THUMB_post_process\r
+       shr     eax,2\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rn_rm_rotation:\r
+       ;used by SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>,\                           ;0=rd,rn,rm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>      ;1=rd,rn,rm,ror imm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rn_rm_rotation\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       cmp     ecx,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rn\r
+       cmp     ecx,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register2]                 ;rm\r
+       cmp     ecx,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       jnz     ARM_store_instruction\r
+       mov     cl,[instruction_shift_op]\r
+       cmp     cl,ARM_SHIFT_OPCODE_ROR\r
+       jnz     ERROR_shift_type_must_be_ROR\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not (3 shl 3)\r
+       jnz     ERROR_shift_value_out_of_range.0_24\r
+       shl     ecx,10-3\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rn_rm_rotation:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       shl     ecx,8\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rn\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register2]                 ;rm\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_type_must_be_ROR\r
+       mov     cl,[instruction_shift_op]\r
+       cmp     cl,ARM_SHIFT_OPCODE_ROR\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.0_24\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not (3 shl 3)\r
+       jnz     THUMB_post_process\r
+       shl     ecx,4-3\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_rotation:\r
+       ;used by SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>,\                                       ;0=rdm\r
+       <TMPL_base_reg,TMPL_shift_op,TMPL_imm>,\                ;1=rdm,ror imm\r
+       <TMPL_base_reg,TMPL_base_reg>,\                         ;2=rd,rm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm>    ;3=rd,rm,ror imm\r
+       sub     al,2\r
+       jnc     .registers_okay\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+    .registers_okay:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       cmp     ecx,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       cmp     ecx,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       jnz     ARM_store_instruction\r
+       mov     cl,[instruction_shift_op]\r
+       cmp     cl,ARM_SHIFT_OPCODE_ROR\r
+       jnz     ERROR_shift_type_must_be_ROR\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not (3 shl 3)\r
+       jnz     ERROR_shift_value_out_of_range.0_24\r
+       shl     ecx,10-3\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rm:\r
+       test    ebp,1 shl 21\r
+       jz      .THUMB_rd_rm_rotation.t2                ;SXTB16, UXTB16 not encodable\r
+       cmp     al,0\r
+       jz      .rotation_okay\r
+       cmp     [immediate_value],0\r
+       jnz     .THUMB_rd_rm_rotation\r
+    .rotation_okay:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v6t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6T\r
+       jz      .THUMB_rd_rm_rotation\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       movzx   edx,word[operand_register0]             ;rd,rm\r
+       test    dx,0x0808\r
+       jnz     .THUMB_rd_rm_rotation\r
+       shl     dh,3\r
+       or      dl,dh\r
+       test    ebp,1 shl 20\r
+       setz    cl\r
+       shl     cl,6\r
+       or      dl,cl\r
+       test    ebp,1 shl 22\r
+       setnz   cl\r
+       shl     cl,7\r
+       or      dl,cl\r
+       mov     dh,0xb2\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+    .THUMB_rd_rm_rotation.t2:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_t2\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      THUMB_post_process\r
+       jmp     .THUMB_rd_rm_rotation.do\r
+    .THUMB_rd_rm_rotation:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+    .THUMB_rd_rm_rotation.do:\r
+       mov     cl,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       shl     ecx,8\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;rm\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_type_must_be_ROR\r
+       mov     cl,[instruction_shift_op]\r
+       cmp     cl,ARM_SHIFT_OPCODE_ROR\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.0_24\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not (3 shl 3)\r
+       jnz     THUMB_post_process\r
+       shl     ecx,4-3\r
+       or      ebp,ecx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rm_rs_SAD:\r
+       ;used by USAD8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;0=rd,rm,rs\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rd_rn_rm.THUMB_rd_rn_rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V6\r
+       jz      ERROR_requires_cpu_capability_arm_v6\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+\r
+;K\r
+\r
+ARM_clrex:\r
+       ;used by CLREX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_clrex\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_K\r
+       jz      ERROR_requires_cpu_capability_arm_k\r
+       jmp     ARM_store_instruction\r
+    .THUMB_clrex:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rt_rt2_q_rn_p:\r
+       ;used by LDREXD, LDAEXD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                    ;0=rt,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>        ;1=rt,rt2,[rn]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rt_rt2_q_rn_p\r
+       mov     ecx,[operand_registers]                 ;rt,rt2,rn\r
+       cmp     al,1\r
+       jnz     .check_rt\r
+       sub     ch,1\r
+       cmp     ch,cl\r
+       jnz     ERROR_destination_registers_must_be_consecutive\r
+       shr     ecx,8\r
+    .check_rt:\r
+       test    cl,1\r
+       jnz     ERROR_destination_register_must_be_even\r
+       cmp     cl,14\r
+       jz      ERROR_r14_not_valid.first\r
+       mov     [operand_registers],ecx                 ;rt,rn\r
+       test    ebp,1 shl 8\r
+       jnz     ARM_rd_q_rn_p.check_v6k\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       jmp     ARM_rd_q_rn_p.version_okay\r
+    .THUMB_rt_rt2_q_rn_p:\r
+       test    ebp,1 shl 8\r
+       jnz     .check_v7\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       jmp     .THUMB_version_okay\r
+    .check_v7:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      ERROR_requires_cpu_capability_arm_v7\r
+    .THUMB_version_okay:\r
+       cmp     al,1\r
+       jz      .check_bad\r
+       mov     ecx,[operand_registers]                 ;rt,rn\r
+       shl     ecx,8\r
+       mov     cl,ch\r
+       inc     ch\r
+       mov     [operand_registers],ecx                 ;rt,rt2,rn\r
+    .check_bad:\r
+       mov     cl,0x37\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_destination_registers_must_differ\r
+       mov     ecx,[operand_registers]\r
+       cmp     ch,cl\r
+       jz      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rt\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rt2\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rt_rt2_q_rn_p:\r
+       ;used by STREXD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\              ;0=rd,rt,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>  ;1=rd,rt,rt2,[rn]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rt_rt2_q_rn_p\r
+       mov     ecx,[operand_registers]                 ;rd,rt,rt2,rn\r
+       cmp     al,1\r
+       jnz     .check_rt\r
+       mov     eax,ecx\r
+       shr     eax,8\r
+       sub     ah,1\r
+       cmp     ah,al\r
+       jnz     ERROR_source_registers_must_be_consecutive\r
+       mov     eax,ecx\r
+       shr     ecx,8\r
+       mov     ch,cl\r
+       mov     cl,al\r
+    .check_rt:\r
+       test    ch,1\r
+       jnz     ERROR_source_register_must_be_even\r
+       cmp     ch,14\r
+       jz      ERROR_r14_not_valid.second\r
+       mov     [operand_registers],ecx                 ;rd,rt,rn\r
+       inc     ch\r
+       cmp     ch,cl\r
+       jz      ERROR_source_and_dest_must_differ\r
+       jmp     ARM_rd_rm_q_rn_p_STREX.check_v6k\r
+    .THUMB_rd_rt_rt2_q_rn_p:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      ERROR_requires_cpu_capability_arm_v7\r
+    .THUMB_adjust_three_to_four:\r
+       cmp     al,1\r
+       jz      .check_bad\r
+       mov     ecx,[operand_registers]                 ;rd,rt,rn\r
+       mov     edx,ecx\r
+       inc     ch\r
+       shl     ecx,8\r
+       mov     cx,dx\r
+       mov     [operand_registers],ecx\r
+    .check_bad:\r
+       mov     cl,0x7f\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_source_and_dest_must_differ\r
+       mov     cl,[operand_register0]\r
+       cmp     cl,[operand_register1]\r
+       jz      THUMB_post_process\r
+       cmp     cl,[operand_register2]\r
+       jz      THUMB_post_process\r
+       cmp     cl,[operand_register3]\r
+       jz      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rt\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rt2\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;Z\r
+\r
+ARM_immediate4:\r
+       ;used by SMC, SMI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_Z\r
+       jz      ERROR_requires_cpu_capability_arm_z\r
+       mov     eax,[immediate_value]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_immediate4\r
+       cmp     eax,0xf\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_15\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_immediate4:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb32_error],ERROR_immediate_value_out_of_range.0_15\r
+       cmp     eax,0xf\r
+       ja      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v6T2\r
+\r
+ARM_rd_address3T:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB2_rd_address\r
+       ;used by LDRHT, LDRSHT, LDRSBT, STRHT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                    ;0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\   ;1=rd,[rn],+-rm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>             ;2=rd,[rn],imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       jmp     ARM_rd_address3.version_check_okay\r
+\r
+THUMB_rd_rn_imm12:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_rd_rn_shifter\r
+       ;used by ADDW, SUBW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>,\                      ;0=reg,imm              alternate for reg,reg,imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm>          ;1=reg,reg,imm\r
+       cmp     al,1\r
+       jz      .encode\r
+       mov     al,[operand_register0]\r
+       mov     [operand_register1],al\r
+    .encode:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     THUMB_post_process\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0xfff\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[thumb32_instruction]\r
+       mov     ecx,eax\r
+       mov     ebp,edx\r
+       xor     ebp,5 shl 21\r
+       neg     ecx\r
+       cmovns  eax,ecx\r
+       cmovns  edx,ebp\r
+       mov     [thumb32_instruction],edx\r
+       mov     [immediate_value],eax\r
+       test    eax,not 0xfff\r
+       jnz     THUMB_post_process\r
+       mov     cl,0x31\r
+       cmp     [operand_register1],13\r
+       jnz     .check_bad_regs\r
+       mov     cl,0x03\r
+    .check_bad_regs:\r
+       jmp     THUMB_GEN_rd_rn_shifter.reg_reg_imm.encode\r
+\r
+ARM_rd_imm_imm:\r
+       ;used by BFC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>   ;0=reg,imm,imm\r
+       jmp     ARM_rd_rn_imm_imm.do\r
+\r
+ARM_rd_rn_imm_imm:\r
+       ;used by BFI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>     ;0=reg,reg,imm,imm\r
+    .do:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rn_imm_imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       mov     ecx,ERROR_lsb_out_of_range.0_31\r
+       ja      ARM_store_instruction_with_error\r
+       shl     eax,7\r
+       or      ebp,eax\r
+       mov     ecx,ERROR_width_out_of_range\r
+       mov     edx,[immediate_value2]\r
+       shr     eax,7\r
+       add     eax,edx\r
+       jc      ARM_store_instruction_with_error\r
+       cmp     eax,32\r
+       ja      ARM_store_instruction_with_error\r
+       dec     eax\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rn_imm_imm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     ecx,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_error],ERROR_lsb_out_of_range.0_31\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      THUMB_post_process\r
+       mov     ecx,eax\r
+       mov     edx,eax\r
+       and     ecx,3\r
+       and     edx,0x1c\r
+       shl     ecx,6\r
+       shl     edx,12-2\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       mov     [thumb32_error],ERROR_width_out_of_range\r
+       mov     edx,[immediate_value2]\r
+       add     eax,edx\r
+       jc      THUMB_post_process\r
+       cmp     eax,32\r
+       ja      THUMB_post_process\r
+       dec     eax\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_reg_address:\r
+       ;used by CBNZ, CBZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_address>                    ;0=reg,imm      PC relative\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,7\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       mov     [thumb16_error],ERROR_relative_jump_not_aligned\r
+       mov     ecx,edi\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       sub     ecx,4\r
+       cmp     [value_undefined],0\r
+       jz      .offset_okay\r
+       xor     ecx,ecx\r
+    .offset_okay:\r
+       test    ecx,1\r
+       jnz     THUMB_post_process\r
+       sar     ecx,1\r
+       mov     [thumb32_error],ERROR_relative_jump_out_of_range\r
+       cmp     ecx,1 shl 6\r
+       jae     THUMB_post_process\r
+       mov     eax,ecx\r
+       and     eax,0x1f\r
+       and     ecx,0x20\r
+       shl     eax,3\r
+       shl     ecx,9-5\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       mov     [thumb16_instruction],bp\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_condition:\r
+       ;used by IT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_condition>                                ;0=condition\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .version_check_okay\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+    .version_check_okay:\r
+       cmp     [explicit_IT_state],0\r
+       jnz     ERROR_instruction_not_conditional\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,0xe                                 ;AL?\r
+       jnz     .AL_okay\r
+       bsf     ecx,ebp\r
+       mov     edx,ebp\r
+       btr     edx,ecx\r
+       and     edx,0xf\r
+       jnz     ERROR_al_has_no_inverse\r
+    .AL_okay:\r
+       shl     eax,4\r
+       mov     edx,eax\r
+       or      edx,1\r
+       or      ebp,eax\r
+       and     eax,0x10\r
+       bsf     ecx,ebp\r
+       cmp     ecx,3\r
+       jz      .store\r
+       mov     ebx,8\r
+    .next_bit:\r
+       shl     edx,8\r
+       mov     dl,[operand_register0]\r
+       test    ebp,ebx\r
+       setnz   ch\r
+       xor     dl,ch\r
+       shl     dl,4\r
+       or      dl,1\r
+       shr     eax,1\r
+       xor     ebp,eax\r
+       shr     ebx,1\r
+       inc     cl\r
+       cmp     cl,3\r
+       jnz     .next_bit\r
+    .store:\r
+       xor     eax,eax\r
+    .swap_order:\r
+       shl     eax,8\r
+       mov     al,dl\r
+       shr     edx,8\r
+       jnz     .swap_order\r
+       or      eax,2\r
+       mov     [explicit_IT_state],eax\r
+       mov     [thumb16_instruction],bp\r
+       mov     [thumb16_error],0\r
+    .finalise:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      THUMB_post_process\r
+       and     eax,not 2                               ;activate the block\r
+       mov     [explicit_IT_state],eax\r
+       jmp     instruction_assembled\r
+\r
+THUMB2_rd_address_rm_translate_table:\r
+       ;bits 24..20 translate to 11..9\r
+       ;used for rd,[rn,rm] 16bit encoding\r
+       db      00100b  ;000    str\r
+       db      00010b  ;001    strh\r
+       db      00000b  ;010    strb\r
+       db      10001b  ;011    ldrsb\r
+       db      00101b  ;100    ldr\r
+       db      00011b  ;101    ldrh\r
+       db      00001b  ;110    ldrb\r
+       db      10011b  ;111    ldrsh\r
+\r
+THUMB2_rd_address_imm_translate_table:\r
+       ;bits 22..20 translate to 15..11\r
+       ;used for rd,[rn,imm] 16bit encoding\r
+       db      01110b  ;strb   000\r
+       db      01111b  ;ldrb   001\r
+       db      10000b  ;strh   010\r
+       db      10001b  ;ldrh   011\r
+       db      01100b  ;str    100\r
+       db      01101b  ;ldr    101\r
+\r
+THUMB2_rd_address:\r
+       cmp     [operand_size],8                        ;LDRD or STRD?\r
+       jz      THUMB2_rd_rd2_address\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                            ;0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                   ;1=rd,[rn],imm  POP {reg}\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                   ;2=rd,[rn,imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ;3=rd,[rn,imm]! PUSH {reg}\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                           ;4=rd,[rn,rm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm2,TMPL_bracket_right>,\   ;5=rd,[rn,rm,shift imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                             ;6=rd,[imm]     PC relative\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                          ;7=rd,[exp]     implicit reg from structure\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                      ;8=rd,[exp]!    implicit reg from structure\r
+       ;       T2 encoding, *???(??) = available in T1, ??? = bits 11..9, ????? = bits 15..11, ^=modified behaviour in T2EE mode\r
+       ;\r
+       ;*      ldr     11111000u101<pc>ttttiiiiiiiiiiii if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE\r
+       ;       ldrb    11111000u001<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLD if t=15 (6T2)\r
+       ;       ldrh    11111000u011<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;       ldrsb   11111001u001<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLI if t=15 (v7)\r
+       ;       ldrsh   11111001u011<pc>ttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;\r
+       ;*01101 ldr     111110001101nnnnttttiiiiiiiiiiii if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE\r
+       ;*01111 ldrb    111110001001nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLD if t=15 (6T2)\r
+       ;*10001 ldrh    111110001011nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLDW if t=15 (MP)\r
+       ;       ldrsb   111110011001nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE; PLI if t=15 (v7)\r
+       ;       ldrsh   111110011011nnnnttttiiiiiiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;\r
+       ;       ldrt    111110000101nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;       ldrbt   111110000001nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;       ldrht   111110000011nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;       ldrsbt  111110010001nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;       ldrsht  111110010011nnnntttt1110iiiiiiii if BadReg(t) then UNPREDICTABLE;\r
+       ;\r
+       ;       ldr     111110000101nnnntttt1puwiiiiiiii if (wback & n=t) | (t=15 & InITBlock() & !LastInITBlock()) then UNPREDICTABLE; POP {reg}\r
+       ;       ldrb    111110000001nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLD if t=15 (6T2)\r
+       ;       ldrh    111110000011nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLDW if t=15 (MP)\r
+       ;       ldrsb   111110010001nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE; PLI if t=15 (v7)\r
+       ;       ldrsh   111110010011nnnntttt1puwiiiiiiii if BadReg(t) | (wback & n=t) then UNPREDICTABLE;\r
+       ;\r
+       ;*100^  ldr     111110000101nnnntttt000000iimmmm if BadReg(m) then UNPREDICTABLE; if t=15 & InITBlock() & !LastInITBlock() then UNPREDICTABLE\r
+       ;*110   ldrb    111110000001nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLD if t=15 (6T2)\r
+       ;*101^  ldrh    111110000011nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLDW if t=15 (MP)\r
+       ;*011   ldrsb   111110010001nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE; PLI if t=15 (v7)\r
+       ;*111^  ldrsh   111110010011nnnntttt000000iimmmm if BadReg(t) | n=15 | BadReg(m) then UNPREDICTABLE;\r
+       ;\r
+       ;*01100 str     111110001100nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if t=15 then UNPREDICTABLE;\r
+       ;*01110 strb    111110001000nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE;\r
+       ;*10000 strh    111110001010nnnnttttiiiiiiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE;\r
+       ;\r
+       ;       strt    111110000100nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE;\r
+       ;       strbt   111110000000nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE;\r
+       ;       strht   111110000010nnnntttt1110iiiiiiii if n=15 then UNDEFINED; if BadReg(t) then UNPREDICTABLE;\r
+       ;\r
+       ;       str     111110000100nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if t=15 | (wback & n=t) then UNPREDICTABLE; PUSH {reg}\r
+       ;       strb    111110000000nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if BadReg(t) | (wback & n=t) then UNPREDICTABLE;\r
+       ;       strh    111110000010nnnntttt1puwiiiiiiii if n=15 then UNDEFINED; if BadReg(t) | (wback & n=t) then UNPREDICTABLE;\r
+       ;\r
+       ;*000^  str     111110000100nnnntttt000000iimmmm if n=15 then UNDEFINED; if t=15 | BadReg(m) then UNPREDICTABLE;\r
+       ;*010   strb    111110000000nnnntttt000000iimmmm if n=15 then UNDEFINED; if BadReg(t) | BadReg(m) then UNPREDICTABLE;\r
+       ;*001^  strh    111110000010nnnntttt000000iimmmm if n=15 then UNDEFINED; if BadReg(t) | BadReg(m) then UNPREDICTABLE;\r
+       ;\r
+    .do:\r
+       mov     ebp,[thumb32_instruction]\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     .check_bad_rn\r
+       test    ebp,1 shl 20                            ;0=STRx, 1=LDRx\r
+       jnz     .check_rd\r
+    .check_bad_rn:\r
+       cmp     [operand_register1],0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       cmp     [value_undefined],0\r
+       jnz     .check_rd\r
+       cmp     al,6\r
+       jz      ERROR_r15_not_valid.second\r
+    .check_rd:\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     .check_bad_rd\r
+       test    ebp,1 shl 22                            ;word?\r
+       jz      .check_bad_rd\r
+       test    ebp,1 shl 20                            ;0=STRx, 1=LDRx\r
+       jz      .check_rd_for_pc\r
+       jmp     .check_rm                               ;word loads to PC are okay\r
+    .check_bad_rd:\r
+       cmp     [operand_register0],0xd\r
+       jz      ERROR_dest_cannot_be_sp_pc\r
+    .check_rd_for_pc:\r
+       cmp     [operand_register0],0xf\r
+       jz      ERROR_dest_cannot_be_sp_pc\r
+    .check_rm:\r
+       test    [operand_register2],0x80                ;-rm?\r
+       jnz     ERROR_instruction_not_16bit\r
+       cmp     [operand_register2],0xd\r
+       jz      ERROR_offset_register_cannot_be_sp_pc\r
+       cmp     [operand_register2],0xf\r
+       jz      ERROR_offset_register_cannot_be_sp_pc\r
+       cmp     [operand_register0],0xf\r
+       jnz     .IT_block_okay\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+    .IT_block_okay:\r
+       mov     ecx,[operand_registers]\r
+       cmp     al,0\r
+       jz      .rd_q_rn_p\r
+       cmp     al,1\r
+       jz      .rd_q_rn_p_imm\r
+       cmp     al,2\r
+       jz      .rd_q_rn_imm_p\r
+       cmp     al,3\r
+       jz      .rd_q_rn_imm_p!\r
+       cmp     al,4\r
+       jz      .rd_q_rn_rm_p\r
+       cmp     al,5\r
+       jz      .rd_q_rn_rm_shift_imm_p\r
+       cmp     al,6\r
+       jz      .rd_q_imm_p\r
+       cmp     al,7\r
+       jz      .rd_q_exp_p\r
+       cmp     al,8\r
+       jz      .rd_q_exp_p!\r
+       ud2\r
+    .rd_q_rn_p_imm:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .rd_q_rn_p_imm.32\r
+       cmp     [operand_size],4\r
+       jnz     .rd_q_rn_p_imm.32\r
+       ;special case for ldr lreg|pc,[sp],4 to use pop {lreg}\r
+       cmp     [immediate_value],4\r
+       jnz     .rd_q_rn_p_imm.32\r
+       cmp     ch,13\r
+       jnz     .rd_q_rn_p_imm.not_sp\r
+       test    ebp,1 shl 20                            ;0=STRx, 1=LDRx\r
+       jz      .rd_q_rn_p_imm.32\r
+       cmp     cl,15\r
+       mov     dx,0xbd00\r
+       jz      .rd_q_rn_p_imm.pc\r
+       cmp     cl,7\r
+       ja      .rd_q_rn_p_imm.32\r
+       mov     dx,0xbc01\r
+       shl     dl,cl\r
+    .rd_q_rn_p_imm.pc:\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       jmp     .rd_q_rn_p_imm.32\r
+    .rd_q_rn_p_imm.not_sp:\r
+       ;special case for ldr/str lreg1,[lreg2],4 to use ldmia/stmia lreg2,{lreg1}\r
+       test    cx,0x0808\r
+       jnz     .rd_q_rn_p_imm.32\r
+       test    ebp,1 shl 20                            ;0=STRx, 1=LDRx\r
+       jz      .rd_q_rn_p_imm.ldr_okay\r
+       mov     [thumb16_error],ERROR_base_and_dest_must_differ_with_writeback\r
+       cmp     cl,ch\r
+       jz      .rd_q_rn_p_imm.32\r
+    .rd_q_rn_p_imm.ldr_okay:\r
+       mov     edx,ebp\r
+       shr     edx,20-11\r
+       and     dx,0x0800                               ;get L bit\r
+       or      dx,0xc001\r
+       shl     dl,cl\r
+       or      dh,ch\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+    .rd_q_rn_p_imm.32:\r
+       mov     [thumb32_error],ERROR_base_and_dest_must_differ_with_writeback\r
+       cmp     cl,ch\r
+       jz      THUMB_post_process\r
+       cmp     ch,0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       cmp     [immediate_value],0\r
+       jz      .rd_q_rn_imm_p\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     THUMB_post_process\r
+       or      ebp,1 shl 8\r
+       jmp     .encode_imm8\r
+    .rd_q_exp_p!:\r
+    .rd_q_rn_imm_p!:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .rd_q_rn_imm_p!.32\r
+       cmp     [operand_size],4\r
+       jnz     .rd_q_rn_imm_p!.32\r
+       ;special case for str lreg|pc,[sp,-4]! to use push {lreg}\r
+       test    ebp,1 shl 20                            ;0=STRx, 1=LDRx\r
+       jnz     .rd_q_rn_imm_p!.32\r
+       cmp     ch,13\r
+       jnz     .rd_q_rn_imm_p!.32\r
+       cmp     [immediate_value],-4\r
+       jnz     .rd_q_rn_imm_p!.32\r
+       cmp     cl,14\r
+       mov     dx,0xb500\r
+       jz      .rd_q_rn_imm_p!.lr\r
+       cmp     cl,7\r
+       ja      .rd_q_rn_imm_p!.32\r
+       mov     dx,0xb401\r
+       shl     dl,cl\r
+    .rd_q_rn_imm_p!.lr:\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+    .rd_q_rn_imm_p!.32:\r
+       cmp     cl,ch\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       cmp     ch,0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     THUMB_post_process\r
+       or      ebp,1 shl 10 + 1 shl 8\r
+       jmp     .encode_imm8\r
+    .rd_q_imm_p:\r
+       mov     [operand_register1],0xf\r
+       push    ecx\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,ecx\r
+       pop     ecx\r
+       mov     ch,0xf\r
+       cmp     [value_undefined],0\r
+       jnz     .rd_q_exp_p\r
+       mov     edx,[addressing_space]\r
+       sub     eax,[edx+0x00]\r
+       and     eax,not 3                               ;round down\r
+       neg     eax\r
+       add     eax,[immediate_value]\r
+       sub     eax,4\r
+       test    eax,3\r
+       jz      .place_aligned_offset\r
+       cmp     dword[adjustment],0\r
+       jz      .place_aligned_offset\r
+       mov     [next_pass_needed],-1\r
+       and     eax,not 3                               ;assume the offset will be aligned\r
+    .place_aligned_offset:\r
+       mov     [immediate_value],eax\r
+    .rd_q_exp_p:\r
+    .rd_q_rn_imm_p:\r
+    .rd_q_rn_p:\r
+       mov     [thumb16_error],ERROR_immediate_cannot_be_encoded\r
+       test    [immediate_value],-1\r
+       jns     .positive_offset\r
+       test    ebp,1 shl 20                            ;LDRx=1?\r
+       jz      .rd_q_rn_p.thumb\r
+       test    ebp,1 shl 22                            ;LDR=1?\r
+       jz      .rd_q_rn_p.thumb\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      .rd_q_rn_p.thumb\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      .rd_q_rn_p.thumb\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ecx,0x0808                              ;any high registers?\r
+       jnz     .rd_q_rn_p.thumb\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.m28_0\r
+       mov     edx,[immediate_value]\r
+       neg     edx\r
+       test    edx,not (7 shl 2)\r
+       jnz     .rd_q_rn_p.thumb\r
+       movzx   eax,ch\r
+       shl     eax,3\r
+       or      al,cl\r
+       shl     edx,6-2\r
+       or      eax,edx\r
+       or      ax,0xc800\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+    .rd_q_rn_p.thumb:\r
+       cmp     ch,0xf\r
+       jz      .encode_imm12\r
+       or      ebp,1 shl 10\r
+       jmp     .encode_imm8\r
+    .positive_offset:\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     .encode_imm8\r
+       or      ebp,1 shl 23\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       test    ebp,1 shl 24                            ;if it is a signed load then no 16bit form is available\r
+       jnz     .encode_imm12\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      .positive_offset.v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      .positive_offset.v4t\r
+       cmp     ch,9\r
+       jz      .positive_offset.r9\r
+       cmp     ch,10\r
+       jnz     .positive_offset.v4t\r
+       test    ebp,1 shl 20                            ;LDRx=1?\r
+       jz      .encode_imm12\r
+       test    ebp,1 shl 22                            ;LDR=1?\r
+       jz      .encode_imm12\r
+       ;ldr rt,[r10,imm]\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    cl,0x08                                 ;high register?\r
+       jnz     .encode_imm12\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x7c\r
+       mov     edx,[immediate_value]\r
+       test    edx,not (0x1f shl 2)\r
+       jnz     .encode_imm12\r
+       shl     edx,3-2\r
+       movzx   ecx,cl\r
+       lea     edx,[edx+ecx+0xcb00]\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       jmp     .encode_imm12\r
+    .positive_offset.r9:\r
+       test    ebp,1 shl 22                            ;LDR or STR (=1)?\r
+       jz      .encode_imm12\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    cl,0x08                                 ;high register?\r
+       jnz     .encode_imm12\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xfc\r
+       mov     edx,[immediate_value]\r
+       test    edx,not (0x3f shl 2)\r
+       jnz     .encode_imm12\r
+       shl     edx,3-2\r
+       movzx   ecx,cl\r
+       lea     edx,[edx+ecx+0xcc00]\r
+       bt      ebp,20\r
+       setnc   cl\r
+       movzx   ecx,cl\r
+       shl     ecx,9\r
+       or      edx,ecx\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       jmp     .encode_imm12\r
+    .positive_offset.v4t:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .encode_imm12\r
+       mov     dx,0x9000\r
+       cmp     ch,0xd                                  ;SP?\r
+       jz      .16bit_imm8\r
+       mov     dx,0x4000\r
+       cmp     ch,0xf                                  ;PC?\r
+       jz      .16bit_imm8\r
+       mov     [thumb16_error],ERROR_register_out_of_range\r
+       test    ecx,0x0808                              ;any high registers?\r
+       jnz     .encode_imm12\r
+       mov     [thumb16_error],ERROR_immediate_cannot_be_encoded\r
+       mov     ecx,ebp\r
+       shr     ecx,20\r
+       and     ecx,6\r
+       setz    dl\r
+       add     cl,dl                                   ;ecx=1, 2 or 4 for B, H, W\r
+       imul    edx,ecx,31\r
+       not     edx\r
+       test    [immediate_value],edx\r
+       jnz     .encode_imm12\r
+       mov     edx,ebp\r
+       shr     edx,20\r
+       and     edx,111b\r
+       movzx   edx,byte[edx+THUMB2_rd_address_imm_translate_table]\r
+       shl     edx,11\r
+       movzx   eax,[operand_register0]\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,3\r
+       or      edx,eax\r
+       mov     eax,[immediate_value]\r
+       shl     eax,6\r
+       shr     ecx,1\r
+       shr     eax,cl\r
+       or      edx,eax\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       jmp     .encode_imm12\r
+    .16bit_imm8:\r
+       mov     [thumb16_error],ERROR_instruction_not_16bit\r
+       cmp     [operand_size],4                        ;LDR or STR?\r
+       jnz     .encode_imm12\r
+       mov     [thumb16_error],ERROR_register_out_of_range\r
+       test    ecx,0x08                                ;a high register?\r
+       jnz     .encode_imm12\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       test    [immediate_value],not (0xff shl 2)\r
+       jnz     .encode_imm12\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      edx,eax\r
+       mov     eax,[immediate_value]\r
+       shr     eax,2\r
+       mov     dl,al\r
+       mov     eax,ebp\r
+       shr     eax,20-11\r
+       and     eax,1 shl 11\r
+       or      edx,eax\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+       jmp     .encode_imm12\r
+    .rd_q_rn_rm_p:\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     .rd_q_rn_rm_shift_imm_p\r
+       mov     [thumb16_error],ERROR_register_out_of_range.r0_r7\r
+       test    ecx,0x080808                            ;any high registers?\r
+       jnz     .rd_q_rn_rm_shift_imm_p\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      .rd_q_rn_rm_p.thumb\r
+       ;only byte version encodings are available in T2EE mode\r
+       mov     [thumb16_error],ERROR_instruction_not_t2ee\r
+       test    ebp,01110b shl 20\r
+       jnz     .rd_q_rn_rm_shift_imm_p\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      .rd_q_rn_rm_shift_imm_p\r
+       jmp     .rd_q_rn_rm_p.thumbee\r
+    .rd_q_rn_rm_p.thumb:\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_v4t\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V4T\r
+       jz      .rd_q_rn_rm_shift_imm_p\r
+    .rd_q_rn_rm_p.thumbee:\r
+    ;encode a 16bit form\r
+       mov     eax,ebp\r
+       shr     eax,20\r
+       and     eax,11111b\r
+       mov     edx,THUMB2_rd_address_rm_translate_table\r
+    .find_16bit_rm_code:\r
+       cmp     al,[edx]\r
+       jz      .found_16bit_rm_code\r
+       inc     edx\r
+       cmp     edx,THUMB2_rd_address_rm_translate_table+8\r
+       jb      .find_16bit_rm_code\r
+       ud2\r
+    .found_16bit_rm_code:\r
+       sub     edx,THUMB2_rd_address_rm_translate_table\r
+       shl     edx,9\r
+       or      edx,0x5000\r
+       movzx   eax,[operand_register0]\r
+       or      edx,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,3\r
+       or      edx,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,6\r
+       or      edx,eax\r
+       mov     [thumb16_instruction],dx\r
+       mov     [thumb16_error],0\r
+    .rd_q_rn_rm_shift_imm_p:\r
+       mov     [thumb32_error],ERROR_r15_not_valid.base\r
+       cmp     ch,0xf\r
+       jz      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_shift_type_must_be_LSL\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     THUMB_post_process\r
+       ;T2EE\r
+       cmp     [thumb16_error],0                       ;second time around?\r
+       jz      .rd_q_rn_rm_shift_imm_p.thumb\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      .rd_q_rn_rm_shift_imm_p.thumb\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     .rd_q_rn_rm_shift_imm_p.thumb\r
+       mov     [thumb16_error],ERROR_register_out_of_range\r
+       test    ecx,0x080808                            ;any high registers?\r
+       jnz     .rd_q_rn_rm_shift_imm_p.thumb\r
+       ;hword and word version encodings are available in T2EE mode\r
+       mov     [thumb16_error],ERROR_instruction_not_t2ee\r
+       test    ebp,01110b shl 20\r
+       jz      .rd_q_rn_rm_shift_imm_p.thumb\r
+       mov     [thumb16_error],ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      .rd_q_rn_rm_shift_imm_p.thumb\r
+       ;check bits 22:21 match the shift count\r
+       mov     ecx,ERROR_shift_value_out_of_range.1\r
+       mov     edx,ERROR_shift_value_out_of_range.2\r
+       test    ebp,1 shl 22\r
+       cmovnz  ecx,edx\r
+       mov     [thumb16_error],ecx\r
+       mov     ecx,ebp\r
+       shr     ecx,21\r
+       and     ecx,3\r
+       cmp     ecx,[immediate_value2]\r
+       jz      .rd_q_rn_rm_p.thumbee\r
+    .rd_q_rn_rm_shift_imm_p.thumb:\r
+       mov     [thumb32_error],ERROR_shift_value_out_of_range.0_3\r
+       cmp     [immediate_value2],3\r
+       ja      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_instruction_not_16bit\r
+       test    ebp,1111b shl 8                         ;STRxT/LDRxT?\r
+       jnz     THUMB_post_process\r
+       jmp     .encode_regs\r
+    .encode_imm12:\r
+       mov     eax,[immediate_value]\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xfff\r
+       test    ebp,1 shl 23\r
+       jnz     .imm12_positive_only\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0xfff\r
+       or      ebp,1 shl 23\r
+       test    eax,eax\r
+       jns     .imm12_positive_only\r
+       and     ebp,not (1 shl 23)\r
+       neg     eax\r
+    .imm12_positive_only:\r
+       cmp     eax,0xfff\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       jmp     .encode_regs\r
+    .encode_imm8:\r
+       or      ebp,1 shl 11\r
+       mov     eax,[immediate_value]\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       test    ebp,1 shl 9\r
+       jnz     .imm8_positive_only\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0xff\r
+       or      ebp,1 shl 9\r
+       test    eax,eax\r
+       jns     .imm8_positive_only\r
+       and     ebp,not (1 shl 9)\r
+       neg     eax\r
+    .imm8_positive_only:\r
+       cmp     eax,0xff\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+    .encode_regs:\r
+       mov     ecx,ebp\r
+       and     ecx,0x17 shl 20 + 0xf shl 12\r
+       ;if bits[24..20]=0x011 and bits[15..12]=1111 then check for MP (PLDW)\r
+       cmp     ecx,0x03 shl 20 + 0xf shl 12\r
+       jz      .check_PLDW\r
+       ;if bits[24..20]=1x001 and bits[15..12]=1111 then check for v7 (PLI)\r
+       cmp     ecx,0x11 shl 20 + 0xf shl 12\r
+       jz      .check_PLI\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_7m\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       jmp     .version_check_okay\r
+    .check_PLDW:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_mp\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_MP\r
+       jz      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_r15_not_valid.base\r
+       cmp     [operand_register1],0xf\r
+       jz      THUMB_post_process\r
+       jmp     .version_check_okay\r
+    .check_PLI:\r
+       mov     [thumb32_error],ERROR_requires_cpu_capability_arm_v7\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      THUMB_post_process\r
+    .version_check_okay:\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value2]\r
+       shl     eax,4\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB2_rd_rd2_address:\r
+       ;used by STRD, LDRD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                                    ; 0=rd,[rn]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                           ; 1=rd,[rn],imm\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                           ; 2=rd,[rn,imm]\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\                     ; 3=rd,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                                     ; 4=rd,[imm]    PC relative\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                                  ; 5=rd,[exp]    implicit reg from structure\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                            ; 6=rd,[exp]!   implicit reg from structure\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                      ; 7=rd,rd2,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                             ; 8=rd,rd2,[rn],imm\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                             ; 9=rd,rd2,[rn,imm]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ;10=rd,rd2,[rn,imm]!\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                       ;11=rd,rd2,[imm]        PC relative\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                    ;12=rd,rd2,[exp]        implicit reg from structure\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                ;13=rd,rd2,[exp]!       implicit reg from structure\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     ebp,[thumb32_instruction]\r
+       sub     al,7\r
+       jae     .dest_registers_defined\r
+       mov     ecx,[operand_registers]\r
+       mov     dl,cl\r
+       inc     cl\r
+       shl     ecx,8\r
+       mov     cl,dl\r
+       mov     [operand_registers],ecx\r
+       add     al,7\r
+    .dest_registers_defined:\r
+       mov     cl,0x33\r
+       mov     dl,0x37\r
+       test    ebp,1 shl 20    ;LDRD?\r
+       cmovz   ecx,edx\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       test    ebp,1 shl 20    ;LDRD?\r
+       jz      .same_regs_okay\r
+       mov     ecx,[operand_registers]\r
+       cmp     cl,ch\r
+       mov     [thumb32_error],ERROR_destination_registers_must_differ\r
+       jz      THUMB_post_process\r
+    .same_regs_okay:\r
+       cmp     al,0\r
+       jz      .rd_q_rn_p\r
+       cmp     al,1\r
+       jz      .rd_q_rn_p_imm\r
+       cmp     al,2\r
+       jz      .rd_q_rn_imm_p\r
+       cmp     al,3\r
+       jz      .rd_q_rn_imm_p!\r
+       cmp     al,4\r
+       jz      .rd_q_imm_p\r
+       cmp     al,5\r
+       jz      .rd_q_exp_p\r
+       cmp     al,6\r
+       jz      .rd_q_exp_p!\r
+       ud2\r
+    .rd_q_rn_p_imm:\r
+       cmp     [operand_register2],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       or      ebp,1 shl 21                            ;set W\r
+       jmp     .check_dest_and_source_differ\r
+    .rd_q_imm_p:\r
+       mov     [operand_register2],0xf\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,ecx\r
+       mov     ch,0xf\r
+       cmp     [value_undefined],0\r
+       jnz     .rd_q_exp_p\r
+       mov     edx,[addressing_space]\r
+       sub     eax,[edx+0x00]\r
+       and     eax,not 3                               ;round down\r
+       neg     eax\r
+       add     eax,[immediate_value]\r
+       sub     eax,4\r
+       mov     [immediate_value],eax\r
+    .rd_q_exp_p:\r
+    .rd_q_rn_imm_p:\r
+    .rd_q_rn_p:\r
+       or      ebp,1 shl 24                            ;set P\r
+       jmp     .encode\r
+    .rd_q_exp_p!:\r
+    .rd_q_rn_imm_p!:\r
+       cmp     [operand_register2],0xf\r
+       jz      ERROR_r15_not_valid.post\r
+       or      ebp,1 shl 24 + 1 shl 21                 ;set P & W\r
+    .check_dest_and_source_differ:\r
+       mov     [thumb32_error],ERROR_base_and_dest_must_differ_with_writeback\r
+       mov     cl,[operand_register2]\r
+       cmp     cl,[operand_register1]\r
+       jz      THUMB_post_process\r
+       cmp     cl,[operand_register0]\r
+       jz      THUMB_post_process\r
+    .encode:\r
+       mov     eax,[immediate_value]\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0x3fc\r
+       or      ebp,1 shl 23\r
+       test    eax,eax\r
+       jns     .imm8_positive\r
+       and     ebp,not (1 shl 23)\r
+       neg     eax\r
+    .imm8_positive:\r
+       test    eax,not (0xff shl 2)\r
+       jnz     THUMB_post_process\r
+       shr     eax,2\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_imm16:\r
+       ;used by MOVW, MOVT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>                        ;0=reg,imm\r
+    .do:\r
+       ;entry from MOV\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_imm16\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xffff\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xffff\r
+       ja      ARM_store_instruction_with_error\r
+       mov     ecx,eax\r
+       and     eax,0x0fff\r
+       and     ecx,0xf000\r
+       shl     ecx,16-12\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_imm16:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     cl,0x11\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xffff\r
+       mov     [thumb32_error],ERROR_immediate_value_out_of_range.0_0xffff\r
+       ja      THUMB_post_process\r
+       mov     ecx,eax\r
+       mov     edx,eax\r
+       mov     ebx,eax\r
+       and     eax,0x00ff\r
+       and     ecx,0x0700\r
+       and     edx,0x0800\r
+       and     ebx,0xf000\r
+       shl     ecx,12-8\r
+       shl     edx,26-11\r
+       shl     ebx,16-12\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,ebx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rn_imm_imm_X:\r
+       ;used by SBFX, UBFX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_imm,TMPL_comma,TMPL_imm2>     ;0=reg,reg,imm,imm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rn_imm_imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2\r
+       jz      ERROR_requires_cpu_capability_arm_t2\r
+       movzx   eax,[operand_register0]\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       mov     ecx,ERROR_lsb_out_of_range.0_31\r
+       ja      ARM_store_instruction_with_error\r
+       shl     eax,7\r
+       or      ebp,eax\r
+       mov     ecx,ERROR_width_out_of_range\r
+       mov     edx,[immediate_value2]\r
+       shr     eax,7\r
+       add     eax,edx\r
+       jc      ARM_store_instruction_with_error\r
+       cmp     eax,32\r
+       ja      ARM_store_instruction_with_error\r
+       dec     edx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rn_imm_imm:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     ecx,0x33\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_error],ERROR_lsb_out_of_range.0_31\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,31\r
+       ja      THUMB_post_process\r
+       mov     ecx,eax\r
+       mov     edx,eax\r
+       and     ecx,3\r
+       and     edx,0x1c\r
+       shl     ecx,6\r
+       shl     edx,12-2\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       mov     [thumb32_error],ERROR_width_out_of_range\r
+       mov     edx,[immediate_value2]\r
+       add     eax,edx\r
+       jc      THUMB_post_process\r
+       cmp     eax,32\r
+       ja      THUMB_post_process\r
+       dec     edx\r
+       or      ebp,edx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_q_rn_rm_p:\r
+       ;used by TBB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_right>      ;0=[rn,rm]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     ecx,0x32\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMB_q_rn_rm_lsl_1_p:\r
+       ;used by TBH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_bracket_left,TMPL_base_reg,TMPL_base_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>       ;0=[rn,rm]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     ecx,0x32\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     ERROR_shift_type_must_be_LSL\r
+       cmp     [immediate_value],1\r
+       jnz     ERROR_immediate_offset_out_of_range.1\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;thumbee\r
+\r
+THUMBEE_enterx:\r
+       ;used by ENTERX, LEAVEX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=EOL\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMBEE_rn_rm:\r
+       ;used by CHKA\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>                   ;0=rn,rm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      ERROR_instruction_needs_t2ee\r
+       mov     cl,0x23\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       movzx   eax,[operand_register0]\r
+       movzx   ecx,[operand_register1]\r
+       mov     edx,eax\r
+       and     eax,7\r
+       and     edx,8\r
+       shl     edx,7-3\r
+       or      eax,edx\r
+       shl     ecx,3\r
+       lea     eax,[eax+ecx+0xca00]\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMBEE_imm:\r
+       ;used by HB, HBL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      ERROR_instruction_needs_t2ee\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_0xff\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      THUMB_post_process\r
+       or      eax,ebp\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMBEE_imm5_imm5:\r
+       ;used by HBLP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm,TMPL_comma,TMPL_imm2>                         ;0=imm,imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      ERROR_instruction_needs_t2ee\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_31\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x1f\r
+       ja      THUMB_post_process\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value2]\r
+       cmp     eax,0x1f\r
+       ja      THUMB_post_process\r
+       or      eax,ebp\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+THUMBEE_imm3_imm5:\r
+       ;used by HBP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm,TMPL_comma,TMPL_imm2>                         ;0=imm,imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_T2EE\r
+       jz      ERROR_requires_cpu_capability_arm_t2ee\r
+       test    [code_type],CPU_ACTIVITY_THUMBEE\r
+       jz      ERROR_instruction_needs_t2ee\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_7\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      THUMB_post_process\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       mov     [thumb16_error],ERROR_immediate_value_out_of_range.0_31\r
+       mov     eax,[immediate_value2]\r
+       cmp     eax,0x1f\r
+       ja      THUMB_post_process\r
+       or      eax,ebp\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v7\r
+\r
+ARM_imm4:\r
+       ;used by DBG\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_imm4\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      ERROR_requires_cpu_capability_arm_v7\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,15\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_15\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_imm4:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      ERROR_requires_cpu_capability_arm_7m\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_error],ERROR_immediate_value_out_of_range.0_15\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,15\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_barrier:\r
+       ;used by DMB, DSB, ISB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_barrier>,\                                ;0=barrier\r
+       <TMPL_imm>,\                                    ;1=imm\r
+       <TMPL_EOL>                                      ;2=default\r
+       cmp     al,1\r
+       jz      .encode\r
+       mov     [immediate_value],0xf\r
+       cmp     al,2\r
+       jz      .encode\r
+       movzx   eax,[operand_register0]\r
+       mov     [immediate_value],eax\r
+    .encode:\r
+       test    ebp,0x20                                ;ISB?\r
+       jz      .do\r
+       cmp     [immediate_value],0xf                   ;only SY is valid\r
+       jnz     ERROR_parameter_n_not_valid.all\r
+    .do:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_barrier\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V7\r
+       jz      ERROR_requires_cpu_capability_arm_v7\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,15\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_15\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_barrier:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       jz      ERROR_requires_cpu_capability_arm_6m\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     [thumb32_error],ERROR_immediate_value_out_of_range.0_15\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,15\r
+       ja      THUMB_post_process\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_nops:\r
+       ;used by SEV, SEVL, WFE, WFI, YIELD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_nops\r
+       mov     ecx,ebp\r
+       and     cl,0xf\r
+       cmp     cl,5                                    ;SEVL?\r
+       jnz     .check_k\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       jmp     ARM_store_instruction\r
+    .check_k:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_K\r
+       jz      ERROR_requires_cpu_capability_arm_k\r
+       jmp     ARM_store_instruction\r
+    .THUMB_nops:\r
+       mov     ecx,ebp\r
+       and     cl,0xf\r
+       cmp     cl,5                                    ;SEVL?\r
+       jnz     .THUMB_check_k\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       mov     [thumb32_error],0\r
+       mov     [thumb16_error],0\r
+       jmp     .THUMB_version_okay\r
+    .THUMB_check_k:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       setz    cl\r
+       movzx   ecx,cl\r
+       neg     ecx\r
+       and     ecx,ERROR_requires_cpu_capability_arm_7m\r
+       mov     [thumb32_error],ecx\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_6M\r
+       setz    cl\r
+       movzx   ecx,cl\r
+       neg     ecx\r
+       and     ecx,ERROR_requires_cpu_capability_arm_6m\r
+       mov     [thumb16_error],ecx\r
+    .THUMB_version_okay:\r
+       mov     eax,[thumb32_instruction]\r
+       and     eax,0xf\r
+       shl     eax,4\r
+       or      eax,0xbf00\r
+       mov     [thumb16_instruction],ax\r
+       jmp     THUMB_post_process\r
+\r
+;DIV\r
+\r
+ARM_rd_rn_rm_DIV:\r
+       ;used by SDIV, UDIV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg>,\                 ;0=reg,reg      alternate for reg,reg,reg\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;1=reg,reg,reg\r
+       cmp     al,0\r
+       jnz     .encode\r
+       mov     ax,word[operand_register0]\r
+       mov     word[operand_register1],ax\r
+    .encode:\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .v7ve\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_DIV\r
+       jz      ERROR_requires_cpu_capability_arm_div\r
+       mov     cl,0x77\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+    .v7ve:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE\r
+       jz      ERROR_requires_cpu_capability_arm_ve\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.all\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+\r
+;versionless\r
+\r
+ARM_und:\r
+       ;used by UND\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>,\                                    ;0=imm\r
+       <TMPL_EOL>                                      ;1=empty\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_und\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xffff\r
+       ja      ERROR_immediate_offset_out_of_range.0_0xffff\r
+       mov     ecx,eax\r
+       and     eax,0x000f\r
+       and     ecx,0xfff0\r
+       shl     ecx,4\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_store_instruction\r
+    .THUMB_und:\r
+       mov     eax,[immediate_value]\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0xff\r
+       cmp     eax,0xff\r
+       ja      .T2\r
+       mov     ah,0xde\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       mov     eax,[immediate_value]\r
+    .T2:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_7M\r
+       jz      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xfff\r
+       cmp     eax,0xfff\r
+       ja      THUMB_post_process\r
+       mov     ecx,eax\r
+       mov     edx,eax\r
+       and     eax,0x00f\r
+       and     ecx,0x0f0\r
+       and     edx,0xf00\r
+       shl     ecx,8-4\r
+       shl     edx,16-8\r
+       or      eax,ecx\r
+       or      eax,edx\r
+       or      [thumb32_instruction],eax\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;FPA\r
+\r
+FPA_fn_fm:\r
+       ;used by CMF, CMFE, CNF, CNFE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_fpa_freg>,\                 ;0=fn,fm\r
+       <TMPL_fpa_freg,TMPL_imm_float>                  ;1=fn,const\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   ecx,[operand_register0]                 ;fn\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       jz      FPA_encode_constant\r
+       movzx   ecx,[operand_register1]                 ;fm\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_rd:\r
+       ;used by RFC, RFS, WFC, WFS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>                                 ;0=rd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_fd_fn_fm:\r
+       ;used by ADFD, ADFDM, ADFDP, ADFDZ, ADFE, ADFEM, ADFEP, ADFEZ, ADFS, ADFSM, ADFSP, ADFSZ,\r
+       ;        DVFD, DVFDM, DVFDP, DVFDZ, DVFE, DVFEM, DVFEP, DVFEZ, DVFS, DVFSM, DVFSP, DVFSZ,\r
+       ;        FDVD, FDVDM, FDVDP, FDVDZ, FDVE, FDVEM, FDVEP, FDVEZ, FDVS, FDVSM, FDVSP, FDVSZ,\r
+       ;        FMLD, FMLDM, FMLDP, FMLDZ, FMLE, FMLEM, FMLEP, FMLEZ, FMLS, FMLSM, FMLSP, FMLSZ,\r
+       ;        FRDD, FRDDM, FRDDP, FRDDZ, FRDE, FRDEM, FRDEP, FRDEZ, FRDS, FRDSM, FRDSP, FRDSZ,\r
+       ;        MUFD, MUFDM, MUFDP, MUFDZ, MUFE, MUFEM, MUFEP, MUFEZ, MUFS, MUFSM, MUFSP, MUFSZ,\r
+       ;        POLD, POLDM, POLDP, POLDZ, POLE, POLEM, POLEP, POLEZ, POLS, POLSM, POLSP, POLSZ,\r
+       ;        POWD, POWDM, POWDP, POWDZ, POWE, POWEM, POWEP, POWEZ, POWS, POWSM, POWSP, POWSZ,\r
+       ;        RDFD, RDFDM, RDFDP, RDFDZ, RDFE, RDFEM, RDFEP, RDFEZ, RDFS, RDFSM, RDFSP, RDFSZ,\r
+       ;        RMFD, RMFDM, RMFDP, RMFDZ, RMFE, RMFEM, RMFEP, RMFEZ, RMFS, RMFSM, RMFSP, RMFSZ,\r
+       ;        RPWD, RPWDM, RPWDP, RPWDZ, RPWE, RPWEM, RPWEP, RPWEZ, RPWS, RPWSM, RPWSP, RPWSZ,\r
+       ;        RSFD, RSFDM, RSFDP, RSFDZ, RSFE, RSFEM, RSFEP, RSFEZ, RSFS, RSFSM, RSFSP, RSFSZ,\r
+       ;        SUFD, SUFDM, SUFDP, SUFDZ, SUFE, SUFEM, SUFEP, SUFEZ, SUFS, SUFSM, SUFSP, SUFSZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_fpa_freg,TMPL_fpa_freg>,\   ;0=fd,fn,fm\r
+       <TMPL_fpa_freg,TMPL_fpa_freg,TMPL_imm_float>    ;1=fd,fn,const\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   ecx,[operand_register0]                 ;fd\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;fn\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       jz      FPA_encode_constant\r
+       movzx   ecx,[operand_register2]                 ;fm\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_fn_rd:\r
+       ;used by FLTD, FLTDM, FLTDP, FLTDZ, FLTE, FLTEM, FLTEP, FLTEZ, FLTS, FLTSM, FLTSP, FLTSZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_base_reg>                   ;0=fn,rd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   eax,[operand_register0]                 ;fn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_fd_imm_address5:\r
+       ;used by LFM, SFM\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                               ;0=fd,imm2,[rn]\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                      ;1=fd,imm2,[rn],imm\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                   ;2=fd,imm2,[rn],{imm}\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                      ;3=fd,imm2,[rn,imm]\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\;4=fd,imm2,[rn,imm]!\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                ;5=fd,imm2,[imm]        PC relative\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                             ;6=fd,imm2,[exp]        implicit reg from structure\r
+       <TMPL_fpa_freg,TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>         ;7=fd,imm2,[exp]!       implicit reg from structure\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V2\r
+       jz      ERROR_requires_copro_capability_fpa_v2\r
+       mov     ecx,[immediate_value2]\r
+       dec     ecx\r
+       cmp     ecx,4\r
+       ja      ERROR_count_value_out_of_range.1_4\r
+       inc     ecx\r
+       and     ecx,3\r
+       mov     edx,ecx\r
+       and     ecx,1\r
+       and     edx,2\r
+       shl     ecx,15\r
+       shl     edx,22-1\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM_copro_crd_address5.version_check_okay\r
+\r
+FPA_fd_imm_rn:\r
+       ;used by LFMEA, LFMFD, SFMEA, SFMFD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_imm,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                        ;0=fd,imm,[rn]\r
+       <TMPL_fpa_freg,TMPL_imm,TMPL_comma,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_modifier_exclaim>    ;1=fd,imm,[rn]!\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V2\r
+       jz      ERROR_requires_copro_capability_fpa_v2\r
+       movzx   eax,al\r
+       shl     eax,21\r
+       or      ebp,eax                                 ;set W bit\r
+       movzx   eax,[operand_register0]                 ;fd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       mov     ecx,[immediate_value]\r
+       dec     ecx\r
+       cmp     ecx,4\r
+       ja      ERROR_count_value_out_of_range.1_4\r
+       inc     ecx\r
+       and     ecx,3\r
+       mov     edx,ecx\r
+       and     ecx,1\r
+       and     edx,2\r
+       shl     ecx,15\r
+       shl     edx,22-1\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       test    ebp,1 shl 21                            ;W?\r
+       jz      .rn_okay\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.third\r
+    .rn_okay:\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     ecx,ebp\r
+       and     ecx,1 shl 24 + 1 shl 23 + 1 shl 21      ;P, U, W\r
+       cmp     ecx,0 shl 24 + 1 shl 23 + 0 shl 21      ;0, 1, 0\r
+       jz      ARM_post_process_copro\r
+       mov     ecx,[immediate_value]\r
+       imul    ecx,3\r
+       or      ebp,ecx                                 ;set the offset field\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_fd_address5:\r
+       ;used by LDFD, LDFE, LDFP, LDFS, STFD, STFE, STFP, STFS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                    ;0=fd,[rn]\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                           ;1=fd,[rn],imm\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                        ;2=fd,[rn],{imm}\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                           ;3=fd,[rn,imm]\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;4=fd,[rn,imm]!\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                     ;5=fd,[imm]     PC relative\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                  ;6=fd,[exp]     implicit reg from structure\r
+       <TMPL_fpa_freg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>              ;7=fd,[exp]!    implicit reg from structure\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM_copro_crd_address5.version_check_okay\r
+\r
+FPA_fd_fm:\r
+       ;used by ABSD, ABSDM, ABSDP, ABSDZ, ABSE, ABSEM, ABSEP, ABSEZ, ABSS, ABSSM, ABSSP, ABSSZ,\r
+       ;        ACSD, ACSDM, ACSDP, ACSDZ, ACSE, ACSEM, ACSEP, ACSEZ, ACSS, ACSSM, ACSSP, ACSSZ,\r
+       ;        ASND, ASNDM, ASNDP, ASNDZ, ASNE, ASNEM, ASNEP, ASNEZ, ASNS, ASNSM, ASNSP, ASNSZ,\r
+       ;        ATND, ATNDM, ATNDP, ATNDZ, ATNE, ATNEM, ATNEP, ATNEZ, ATNS, ATNSM, ATNSP, ATNSZ,\r
+       ;        COSD, COSDM, COSDP, COSDZ, COSE, COSEM, COSEP, COSEZ, COSS, COSSM, COSSP, COSSZ,\r
+       ;        EXPD, EXPDM, EXPDP, EXPDZ, EXPE, EXPEM, EXPEP, EXPEZ, EXPS, EXPSM, EXPSP, EXPSZ,\r
+       ;        LGND, LGNDM, LGNDP, LGNDZ, LGNE, LGNEM, LGNEP, LGNEZ, LGNS, LGNSM, LGNSP, LGNSZ,\r
+       ;        LOGD, LOGDM, LOGDP, LOGDZ, LOGE, LOGEM, LOGEP, LOGEZ, LOGS, LOGSM, LOGSP, LOGSZ,\r
+       ;        MNFD, MNFDM, MNFDP, MNFDZ, MNFE, MNFEM, MNFEP, MNFEZ, MNFS, MNFSM, MNFSP, MNFSZ,\r
+       ;        MVFD, MVFDM, MVFDP, MVFDZ, MVFE, MVFEM, MVFEP, MVFEZ, MVFS, MVFSM, MVFSP, MVFSZ,\r
+       ;        NRMD, NRMDM, NRMDP, NRMDZ, NRME, NRMEM, NRMEP, NRMEZ, NRMS, NRMSM, NRMSP, NRMSZ,\r
+       ;        RNDD, RNDDM, RNDDP, RNDDZ, RNDE, RNDEM, RNDEP, RNDEZ, RNDS, RNDSM, RNDSP, RNDSZ,\r
+       ;        SIND, SINDM, SINDP, SINDZ, SINE, SINEM, SINEP, SINEZ, SINS, SINSM, SINSP, SINSZ,\r
+       ;        SQTD, SQTDM, SQTDP, SQTDZ, SQTE, SQTEM, SQTEP, SQTEZ, SQTS, SQTSM, SQTSP, SQTSZ,\r
+       ;        TAND, TANDM, TANDP, TANDZ, TANE, TANEM, TANEP, TANEZ, TANS, TANSM, TANSP, TANSZ,\r
+       ;        URDD, URDDM, URDDP, URDDZ, URDE, URDEM, URDEP, URDEZ, URDS, URDSM, URDSP, URDSZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_fpa_freg,TMPL_fpa_freg>,\                 ;0=fd,fm\r
+       <TMPL_fpa_freg,TMPL_imm_float>                  ;1=fd,const\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   ecx,[operand_register0]                 ;fd\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       cmp     al,1\r
+       jz      FPA_encode_constant\r
+       movzx   ecx,[operand_register1]                 ;fm\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+FPA_rd_fm:\r
+       ;used by FIX, FIXM, FIXP, FIXZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_fpa_freg>                   ;0=rd,fm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_FPA_V1\r
+       jz      ERROR_requires_copro_capability_fpa_v1\r
+       movzx   ecx,[operand_register0]                 ;rd\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       movzx   ecx,[operand_register1]                 ;fm\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+       align 4\r
+FPA_constants:\r
+       dd      0.0\r
+       dd      1.0\r
+       dd      2.0\r
+       dd      3.0\r
+       dd      4.0\r
+       dd      5.0\r
+       dd      0.5\r
+       dd      10.0\r
+\r
+FPA_encode_constant:\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,FPA_constants\r
+       mov     edx,8\r
+    .find_constant:\r
+       dec     edx\r
+       js      .not_found\r
+       cmp     eax,[ecx+edx*4]\r
+       jnz     .find_constant\r
+       lea     eax,[edx+8]\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .not_found:\r
+       mov     ecx,ERROR_constant_cannot_be_encoded\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+;MAVERICK\r
+\r
+MAVERICK_crd_crn:\r
+       ;used by CFABS32, CFABS64, CFABSS, CFABSD, CFCPYS, CFCPYD, CFCVT32S, CFCVT32D, CFCVT64S, CFCVT64D, CFCVTD32,\r
+       ;        CFCVTDS, CFCVTS32, CFCVTSD, CFNEG32, CFNEG64, CFNEGS, CFNEGD, CFTRUNCS32, CFTRUNCD32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_cpro_reg>                   ;0=crd,crn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crd_crn_crm:\r
+       ;used by CFADD32, CFADD64, CFADDD, CFADDS, CFMAC32, CFMSC32, CFMUL32, CFMUL64, CFMULS, CFMULD,\r
+       ;        CFSUB32, CFSUB64, CFSUBD, CFSUBS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg>     ;0=crd,crn,crm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_rd_crn_crm:\r
+       ;used by CFCMP32, CFCMP64, CFCMPS, CFCMPD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_cpro_reg,TMPL_cpro_reg>     ;0=rd,crn,crm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crd_address5:\r
+       ;used by CFLDR32, CFLDR64, CFLDRS, CFLDRD, CFSTR32, CFSTR64, CFSTRS, CFSTRD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                    ;0=crd,[rn]\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                           ;1=crd,[rn],imm\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                        ;2=crd,[rn],{imm}\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                           ;3=crd,[rn,imm]\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;4=crd,[rn,imm]!\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                     ;5=crd,[imm]    PC relative\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                  ;6=crd,[exp]    implicit reg from structure\r
+       <TMPL_cpro_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>              ;7=crd,[exp]!   implicit reg from structure\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM_copro_crd_address5.version_check_okay\r
+\r
+MAVERICK_aa_crd_crn_crm:\r
+       ;used by CFMADD32, CFMSUB32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_mvrk_areg,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_cpro_reg>      ;0=aa,crd,crn,crm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;aa\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;crm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_aa_ad_crn_crm:\r
+       ;used by CFMADDA32, CFMSUBA32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_mvrk_areg,TMPL_mvrk_areg,TMPL_cpro_reg,TMPL_cpro_reg>     ;0=aa,ad,crn,crm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;aa\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;ad\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;crm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crd_an:\r
+       ;used by CFMV32A, CFMV32AH, CFMV32AL, CFMV32AM, CFMV64A\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_mvrk_areg>                  ;0=crd,an\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;an\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crd_psc:\r
+       ;used by CFMV32SC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_mvrk_psc>                   ;0=crd,psc\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_psc_crd:\r
+       ;used by CFMVSC32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_mvrk_psc,TMPL_cpro_reg>                   ;0=psc,crd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crn_rd:\r
+       ;used by CFMV64HR, CFMV64LR, CFMVDHR, CFMVDLR, CFMVSR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_base_reg>                   ;0=crn,rd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_ad_crn:\r
+       ;used by CFMVA32, CFMVA64, CFMVAH32, CFMVAL32, CFMVAM32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_mvrk_areg,TMPL_cpro_reg>                  ;0=ad,crn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;ad\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_rd_crn:\r
+       ;used by CFMVR64H, CFMVR64L, CFMVRDH, CFMVRDL, CFMVRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_cpro_reg>                   ;0=rd,crn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crm_crn_rd:\r
+       ;used by CFRSHL32, CFRSHL64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_base_reg>     ;0=crm,crn,rd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crm\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+MAVERICK_crd_crn_imm:\r
+       ;used by CFSH32, CFSH64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_cpro_reg,TMPL_cpro_reg,TMPL_imm>          ;0=crm,crn,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_MAVERICK\r
+       jz      ERROR_requires_copro_capability_maverick\r
+       movzx   eax,[operand_register0]                 ;crd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;crn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]                   ;imm\r
+       cmp     eax,-64\r
+       jl      .out_of_range\r
+       cmp     eax,63\r
+       jg      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0x0f\r
+       and     ecx,0x70\r
+       shl     ecx,1\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.m64_63\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+;vfp1\r
+\r
+VFP_sd_sn_sm:\r
+       ;used by FMULS, FNMULS, FADDS, FSUBS, FDIVS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;0=sdn,sm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;1=sd,sn,sm\r
+    .v1xd_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+    .do:\r
+       cmp     al,0\r
+       jnz     .registers_shifted\r
+       mov     eax,[operand_registers]\r
+       mov     cl,al\r
+       shl     eax,8\r
+       mov     al,cl\r
+       mov     [operand_registers],eax\r
+    .registers_shifted:\r
+       movzx   eax,[operand_register0]                 ;fd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;fn\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,16\r
+       shl     ecx,7\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register2]                 ;fm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_dd_dn_dm:\r
+       ;used by FMULD, FNMULD, FADDD, FSUBD, FDIVD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;1=dd,dn,dm\r
+    .begin:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sn_sm.do\r
+       mov     edx,[operand_registers]                 ;fd,fn,fm\r
+       test    edx,0x010101\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sn_sm.do\r
+\r
+VFP_sd_sm:\r
+       ;used by FABSS, FCPYS, FNEGS, FSITOS, FSQRTS, FTOSIS, FTOSIZS, FTOUIS, FTOUIZS, FUITOS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>                   ;0=sd,sm\r
+    .v1xd_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+    .do:\r
+       movzx   eax,[operand_register0]                 ;fd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;fm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_dd_dm:\r
+       ;used by FABSD, FCPYD, FNEGD, FSQRTD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>                   ;0=dd,dm\r
+    .encode:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sm.do\r
+       mov     edx,[operand_registers]                 ;fd,fm\r
+       test    edx,0x0101\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_sd_sm_zero:\r
+       ;used by FCMPS, FCMPES\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;0=sd,sm\r
+       <TMPL_vfps_reg,TMPL_imm>                        ;1=sd,0.0\r
+       test    al,al\r
+       jz      VFP_sd_sm.v1xd_test\r
+       cmp     [immediate_value],0\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       jnz     ARM_post_process_copro_with_error\r
+       or      ebp,1 shl 16                            ;set for FCMP(E)Z\r
+       jmp     VFP_sd_sm.v1xd_test\r
+\r
+VFP_dd_dm_zero:\r
+       ;used by FCMPD, FCMPED\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=dd,dm\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,0.0\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       test    al,al\r
+       jnz     .zero\r
+    .check_d32:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sm.do\r
+       mov     edx,[operand_registers]                 ;fd,fm\r
+       test    edx,0x0101\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sm.do\r
+    .zero:\r
+       cmp     [immediate_value],0\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       jnz     ARM_post_process_copro_with_error\r
+       or      ebp,1 shl 16                            ;set for FCMP(E)Z\r
+       jmp     .check_d32\r
+\r
+VFP_sd:\r
+       ;used by FCMPZS, FCMPEZS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg>                                 ;0=sd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       mov     [operand_register1],0                   ;fm\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_dd:\r
+       ;used by FCMPZD, FCMPEZD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg>                                 ;0=dd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       mov     [operand_register1],0           ;fm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sm.do\r
+       mov     edx,[operand_registers]                 ;fd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_dd_sm:\r
+       ;used by FCVTDS, FSITOD, FUITOD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfps_reg>                   ;0=dd,sm\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sm.do\r
+       mov     edx,[operand_registers]                 ;fd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_sd_dm:\r
+       ;used by FCVTSD, FTOSID, FTOSIZD, FTOUID, FTOUIZD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfpd_reg>                   ;0=sd,dm\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1\r
+       jz      ERROR_requires_copro_capability_vfp_v1\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_sm.do\r
+       mov     edx,[operand_registers]                 ;fm\r
+       test    edx,0x0100\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_sd_sm_HP:\r
+       ;used by VCVTB, VCVTT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>                   ;0=sd,sm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_HP\r
+       jz      ERROR_requires_copro_capability_vfp_hp\r
+       jmp     VFP_sd_sm.do\r
+\r
+VFP_sd_rn_offset:\r
+       ;used by FLDS, FSTS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\            ;0=sd,[rn]\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\   ;1=sd,[rn,imm]\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\             ;2=sd,[imm]     PC relative\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>            ;3=sd,[exp]     implicit reg from structure\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+       cmp     al,0\r
+       jz      .fd_q_rn_p\r
+       cmp     al,1\r
+       jz      .fd_q_rn_imm_p\r
+       cmp     al,2\r
+       jz      .fd_q_imm_p\r
+       cmp     al,3\r
+       jz      .fd_q_exp_p\r
+       ud2\r
+    .fd_q_imm_p:\r
+       mov     [operand_register1],0xf\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       and     ecx,not 3                               ;round down\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       setnz   al\r
+       movzx   eax,al\r
+       shl     eax,2\r
+       add     eax,4                                   ;offset=4 for THUMB and 8 for ARM\r
+       sub     ecx,eax\r
+       mov     [immediate_value],ecx\r
+    .fd_q_exp_p:\r
+    .fd_q_rn_p:\r
+    .fd_q_rn_imm_p:\r
+       or      ebp,1 shl 23\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax\r
+       jns     .positive_imm\r
+       and     ebp,not (1 shl 23)\r
+       neg     eax\r
+    .positive_imm:\r
+       test    eax,3\r
+       jnz     .out_of_range\r
+       shr     eax,2\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]                 ;fd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0x3fc\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+VFP_dd_rn_offset:\r
+       ;used by FLDD, FSTD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\            ;0=dd,[rn]\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\   ;1=dd,[rn,imm]\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\             ;2=dd,[imm]     PC relative\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>            ;3=dd,[exp]     implicit reg from structure\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_sd_rn_offset.do\r
+       mov     edx,[operand_registers]                 ;fd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_sd_rn_offset.do\r
+\r
+VFP_rn_list_s:\r
+       ;used by FLDMIAS, FLDMDBS, FSTMIAS, FSTMDBS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfp_reg_list_s>,\           ;0=rn,{..}\r
+       <TMPL_base_reg!,TMPL_vfp_reg_list_s>            ;1=rn!,{..}\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+       cmp     al,1                                    ;writeback?\r
+       jnz     .rn_okay\r
+       cmp     [operand_register0],15                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       or      ebp,1 shl 21\r
+    .rn_okay:\r
+       mov     eax,ebp\r
+       and     eax,1 shl 24 + 1 shl 21                 ;isolate P and W\r
+       xor     eax,1 shl 24                            ;P=!P\r
+       jz      ERROR_must_have_writeback_operator      ;P=1 & W=0 is FLD/FST, not valid\r
+       mov     edx,[reg_list_bitmap]\r
+       bsf     eax,edx\r
+       bsr     ecx,edx\r
+    ;check for a contiguous set\r
+       xor     ecx,31\r
+       shl     edx,cl\r
+       add     ecx,eax\r
+       sar     edx,cl\r
+       inc     edx\r
+       jnz     ERROR_non_contiguous_set\r
+       mov     ecx,[reg_list_bitmap]\r
+       bsf     eax,ecx                                 ;eax=start register\r
+       bsr     edx,ecx\r
+       sub     edx,eax\r
+       inc     edx                                     ;edx=register count\r
+       test    ebp,1 shl 8                             ;FLDMD?\r
+       jz      .encode\r
+       cmp     edx,16\r
+       ja      ERROR_large_set\r
+    ;double everything\r
+       add     eax,eax\r
+       add     edx,edx\r
+    ;shift high bit to LSb\r
+       mov     ah,al\r
+       shr     ah,5\r
+       and     ax,0x011e\r
+       or      al,ah\r
+       movzx   eax,al\r
+    .encode:\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       movzx   eax,[operand_register0]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_rn_list_d:\r
+       ;used by FLDMIAD, FLDMDBD, FLDMIAX, FLDMDBX, FSTMIAD, FSTMDBD, FSTMIAX, FSTMDBX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfp_reg_list_d>,\           ;0=rn,{..}\r
+       <TMPL_base_reg!,TMPL_vfp_reg_list_d>            ;1=rn!,{..}\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     VFP_rn_list_s.do\r
+       mov     edx,[reg_list_bitmap]\r
+       test    edx,0xffff0000\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       jmp     VFP_rn_list_s.do\r
+\r
+VFP_dn_rd:\r
+       ;used by FMDHR, FMDLR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_base_reg>                   ;0=dn,rd\r
+    .test_version:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+       movzx   eax,[operand_register0]                 ;dn\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,16\r
+       shl     ecx,7\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_rd_dn:\r
+       ;used by FMRDH, FMRDL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfpd_reg>                   ;0=rd,dn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x0100\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+    .encode:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       and     eax,0xf\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;dn\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,16\r
+       shl     ecx,7\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_rd_sn:\r
+       ;used by FMRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfps_reg>                   ;0=rd,sn\r
+       jmp     VFP_rd_dn.do\r
+\r
+VFP_sn_rd:\r
+       ;used by FMSR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_base_reg>                   ;0=sn,rd\r
+    .do:\r
+       mov     ax,word[operand_register0]\r
+       xchg    ah,al\r
+       mov     word[operand_register0],ax\r
+       jmp     VFP_rd_dn.do\r
+\r
+VFP_rd_sysreg:\r
+       ;used by FMRX, VMRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfp_syst>,\                 ;0=rd,sysreg\r
+       <TMPL_psr,TMPL_vfp_syst>                        ;0=apsr_nzcv,sysreg\r
+       cmp     al,0\r
+       mov     ax,word[operand_registers+0]\r
+       jz      .dest_okay\r
+       cmp     al,34                                   ;apsr?\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       mov     al,0xf\r
+    .dest_okay:\r
+       shl     ah,1                                    ;set sysreg encoding\r
+       cmp     ah,1 shl 1                              ;fpscr?\r
+       setz    cl\r
+       shl     cl,4\r
+       or      al,cl                                   ;disable r15 check, r15 is okay here if reading fpscr\r
+       mov     word[operand_registers+0],ax\r
+       jmp     VFP_rd_dn.do\r
+\r
+VFP_sysreg_rd:\r
+       ;used by FMXR, VMSR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfp_syst,TMPL_base_reg>                   ;0=sysreg,rd\r
+       mov     ax,word[operand_registers+0]\r
+       xchg    ah,al\r
+       shl     ah,1                                    ;set sysreg encoding\r
+       mov     word[operand_registers+0],ax\r
+       jmp     VFP_rd_dn.do\r
+\r
+;vfp2\r
+\r
+VFP_dm_rd_rn:\r
+       ;used by FMDRR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_base_reg,TMPL_base_reg>     ;0=dm,rd,rn\r
+    .test_version:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2\r
+       jz      ERROR_requires_copro_capability_vfp_v2\r
+       movzx   eax,[operand_register0]                 ;dm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_rd_rn_dm:\r
+       ;used by FMRRD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_vfpd_reg>     ;0=rd,rn,dm\r
+    .test_version:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x010000\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2\r
+       jz      ERROR_requires_copro_capability_vfp_v2\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;dm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_rd_rn_sm:\r
+       ;used by FMRRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_vfp_reg_list_s>       ;0=rd,rn,{..}\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V2\r
+       jz      ERROR_requires_copro_capability_vfp_v2\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     ecx,[reg_list_bitmap]\r
+       bsf     eax,ecx                                 ;eax=start register\r
+       bsr     edx,ecx\r
+    ;check for a 2 register set\r
+       dec     edx\r
+       cmp     edx,eax\r
+       jnz     ERROR_two_registers_required\r
+       cmp     eax,30\r
+       ja      ERROR_two_registers_required\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_sm_rd_rn:\r
+       ;used by FMSRR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfp_reg_list_s,TMPL_comma,TMPL_base_reg,TMPL_base_reg>    ;0={..},rd,rn\r
+       jmp     VFP_rd_rn_sm.do\r
+\r
+VFP_fmstat:\r
+       ;used by FMSTAT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V1xD\r
+       jz      ERROR_requires_copro_capability_vfp_v1xd\r
+       jmp     ARM_post_process_copro\r
+\r
+VFP_convert_single_to_quarter:\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,eax\r
+       mov     edx,eax\r
+       and     eax,1 shl 23-1                          ;eax=mantissa\r
+       shr     ecx,23\r
+       and     ecx,0xff                                ;ecx=exponent\r
+       add     eax,1 shl 18\r
+       shr     eax,19\r
+       cmp     eax,0xf\r
+       jbe     .rounding_done\r
+       xor     eax,eax\r
+       inc     ecx\r
+    .rounding_done:\r
+       cmp     cl,01111100b\r
+       jb      .out_of_range\r
+       cmp     cl,10000011b\r
+       ja      .out_of_range\r
+       shr     edx,31-7\r
+       and     edx,0x80                                ;dl=sign\r
+       and     ecx,7\r
+       shl     ecx,4\r
+       or      edx,ecx\r
+       or      eax,edx\r
+       mov     [immediate_value],eax\r
+       ret\r
+    .out_of_range:\r
+       or      eax,-1\r
+       mov     [immediate_value],eax\r
+       ret\r
+\r
+VFP_dm_imm:\r
+       ;used by FCONSTD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm_float>,\                ;0=dd,float\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,imm\r
+    .vesion_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x01\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V3\r
+       jz      ERROR_requires_copro_capability_vfp_v3\r
+       cmp     al,1\r
+       jz      .constant_converted\r
+       call    VFP_convert_single_to_quarter\r
+    .constant_converted:\r
+       movzx   eax,[operand_register0]                 ;dd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0xf\r
+       and     ecx,0xf0\r
+       shl     ecx,16-4\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0xff\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+VFP_sm_imm:\r
+       ;used by FCONSTS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_imm_float>,\                ;0=sd,float\r
+       <TMPL_vfps_reg,TMPL_imm>                        ;1=sd,imm\r
+       jmp     VFP_dm_imm.do\r
+\r
+VFP_dd_dd_imm:\r
+       ;used by FSHTOD, FSLTOD, FUHTOD, FULTOD, FTOSHD, FTOSLD, FTOUHD, FTOULD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=dd,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>          ;1=dd,dd,imm\r
+    .test_version:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     .do\r
+       mov     edx,[operand_registers]                 ;dd\r
+       test    edx,0x0101\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+    .do:\r
+       shr     al,1\r
+       jc      .register_okay\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+    .register_okay:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V3\r
+       jz      ERROR_requires_copro_capability_vfp_v3\r
+       movzx   eax,word[operand_register0]             ;dd,dd\r
+       cmp     ah,al\r
+       jnz     ERROR_dest_and_source_must_be_the_same\r
+       mov     ah,0\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       mov     ecx,[immediate_value]\r
+       test    ebp,1 shl 7\r
+       jz      .half\r
+    ;long\r
+       cmp     ecx,1\r
+       jb      .out_of_range_long\r
+       cmp     ecx,32\r
+       ja      .out_of_range_long\r
+       mov     eax,32\r
+       jmp     .encode\r
+    .half:\r
+       cmp     ecx,16\r
+       ja      .out_of_range_half\r
+       mov     eax,16\r
+    .encode:\r
+       sub     eax,ecx\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range_long:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_32\r
+       jmp     ARM_post_process_copro_with_error\r
+    .out_of_range_half:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_16\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+VFP_sd_sd_imm:\r
+       ;used by FSHTOS, FSLTOS, FUHTOS, FULTOS, FTOSHS, FTOSLS, FTOUHS, FTOULS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_imm>,\                      ;0=sd,imm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_imm>          ;1=sd,sd,imm\r
+       jmp     VFP_dd_dd_imm.do\r
+\r
+;xScale\r
+\r
+XSCALE_acc_rm_rs:\r
+       ;used by MIA, MIAPH, MIABB, MIABT, MIATB, MIATT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_acc_40bt,TMPL_base_reg,TMPL_base_reg>     ;0=acc,rm,rs\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE\r
+       jz      ERROR_requires_copro_capability_xscale\r
+       movzx   eax,[operand_register0]                 ;acc\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+XSCALE_acc_rdlo_rdhi:\r
+       ;used by MAR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_acc_40bt,TMPL_base_reg,TMPL_base_reg>     ;0=acc,rdlo,rdhi\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE\r
+       jz      ERROR_requires_copro_capability_xscale\r
+       movzx   eax,[operand_register0]                 ;acc\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+XSCALE_rdlo_rdhi_acc:\r
+       ;used by MRA\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_acc_40bt>     ;0=rdlo,rdhi,acc\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_XSCALE\r
+       jz      ERROR_requires_copro_capability_xscale\r
+       mov     eax,[operand_registers]\r
+       mov     ecx,eax\r
+       shl     eax,8\r
+       shr     ecx,16\r
+       mov     al,cl\r
+       mov     [operand_registers],eax\r
+       jmp     XSCALE_acc_rdlo_rdhi.do\r
+\r
+;IWMMXT V1\r
+\r
+IWMMXT_r15:\r
+       ;used by TANDCB, TANDCH, TANDCW, TORCB, TORCH, TORCW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>                                 ;0=r15\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;r15\r
+       cmp     eax,15                                  ;PC?\r
+       jnz     ERROR_must_be_r15.first\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_rn:\r
+       ;used by TBCSTB, TBCSTH, TBCSTW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_base_reg>                 ;0=wrd,rn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_r15_imm:\r
+       ;used by TEXTRCB, TEXTRCH, TEXTRCW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_imm>                        ;0=r15,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;r15\r
+       cmp     eax,15                                  ;PC?\r
+       jnz     ERROR_must_be_r15.first\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_rd_wrn_imm:\r
+       ;used by TEXTRMSB, TEXTRMSH, TEXTRMSW, TEXTRMUB, TEXTRMUH, TEXTRMUW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_iwmmx_wreg,TMPL_imm>        ;0=rd,wrn,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_wrd_rn_imm:\r
+       ;used by TINSRB, TINSRH, TINSRW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_imm>        ;0=wrd,rn,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_wcd_rn:\r
+       ;used by TMCR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_creg,TMPL_base_reg>                 ;0=wcd,rn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wcd\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_rdlo_rdhi:\r
+       ;used by TMCRR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_base_reg>   ;0=wrd,rdlo,rdhi\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rdlo\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rdhi\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_rm_rs:\r
+       ;used by TMIA, TMIAPH, TMIAxy\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_base_reg,TMPL_base_reg>   ;0=wrd,rm,rs\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rm\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rs\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_rd_wrn:\r
+       ;used by TMOVMSKB, TMOVMSKH, TMOVMSKW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_iwmmx_wreg>                 ;0=rd,wrn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_rd_wcn:\r
+       ;used by TMRC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_iwmmx_creg>                 ;0=rd,wcn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wcn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_rdlo_rdhi_wrn:\r
+       ;used by TMRRC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_iwmmx_wreg>   ;0=rdlo,rdhi,wrn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,word[operand_register0]\r
+       cmp     ah,al\r
+       jz      ERROR_destination_registers_must_differ\r
+       movzx   eax,[operand_register0]                 ;rdlo\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rdhi\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrn\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn:\r
+       ;used by WACCB, WACCH, WACCW, WUNPCKEHUB, WUNPCKEHUH, WUNPCKEHUW, WUNPCKEHSB, WUNPCKEHSH, WUNPCKEHSW\r
+       ;        WUNPCKELUB, WUNPCKELUH, WUNPCKELUW, WUNPCKELSB, WUNPCKELSH, WUNPCKELSW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>               ;0=wrd,wrn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn_wrm:\r
+       ;used by WADDB, WADDH, WADDW, WADDBSS, WADDHSS, WADDWSS, WADDBUS, WADDHUS, WADDWUS,\r
+       ;        WALIGNR0, WALIGNR1, WALIGNR2, WALIGNR3, WAND, WANDN, WAVG2B, WAVG2H, WAVG2BR, WAVG2HR,\r
+       ;        WCMPEQB, WCMPEQH, WCMPEQW, WCMPGTSB, WCMPGTSH, WCMPGTSW, WCMPGTUB, WCMPGTUH, WCMPGTUW,\r
+       ;        WMACS, WMACU, WMACSZ, WMACUZ, WMADDU, WMADDS, WMAXUB, WMAXUH, WMAXUW, WMAXSB, WMAXSH, WMAXSW,\r
+       ;        WMINUB, WMINUH, WMINUW, WMINSB, WMINSH, WMINSW, WMULSM, WMULSL, WMULUM, WMULUL,\r
+       ;        WPACKDSS, WPACKDUS, WPACKHSS, WPACKHUS, WPACKWSS, WPACKWUS, WSADB, WSADH, WSADBZ, WSADHZ,\r
+       ;        WSUBB, WSUBH, WSUBW, WSUBBSS, WSUBHSS, WSUBWSS, WSUBBUS, WSUBHUS, WSUBWUS,\r
+       ;        WUNPCKIHB, WUNPCKIHH, WUNPCKIHW, WUNPCKILB, WUNPCKILH, WUNPCKILW, WXOR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>       ;0=wrd,wrn,wrm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn_wrm_imm:\r
+       ;used by WALIGNI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm>      ;0=wrd,wrn,wrm,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrm\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       shl     eax,20\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_wrd_address5:\r
+       ;used by WLDRB, WLDRH, WLDRW, WSTRB, WSTRH, WSTRW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                  ; 0=wrd,[rn]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                         ; 1=wrd,[rn],imm\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                      ; 2=wrd,[rn],{imm}\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                         ; 3=wrd,[rn,imm]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\   ; 4=wrd,[rn,imm]!\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                   ; 5=wrd,[imm]   PC relative\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                ; 6=wrd,[exp]   implicit reg from structure\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\          ; 7=wrd,[exp]!  implicit reg from structure\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                  ; 8=crd,[rn]\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                         ; 9=crd,[rn],imm\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                      ;10=crd,[rn],{imm}\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                         ;11=crd,[rn,imm]\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\   ;12=crd,[rn,imm]!\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                   ;13=crd,[imm]   PC relative\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                ;14=crd,[exp]   implicit reg from structure\r
+       <TMPL_iwmmx_creg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>            ;15=crd,[exp]!  implicit reg from structure\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       cmp     al,8                                    ;wcr?\r
+       jb      .wcr_okay\r
+    ;check for W mode\r
+       mov     ecx,ebp\r
+       and     ecx,1 shl 22 + 1 shl 8\r
+       cmp     ecx,1 shl 8\r
+       jnz     ERROR_control_register_only_valid_with_word\r
+       sub     al,8\r
+       or      ebp,0xf shl 28\r
+    .wcr_okay:\r
+       cmp     al,5                                    ;wrd,[imm]?\r
+       jnz     .offset_okay\r
+       mov     [operand_register1],0xf\r
+       call    THUMB_query_condition_pc\r
+       mov     eax,[addressing_space]\r
+       sub     ecx,[eax+0x00]\r
+       and     ecx,not 3                               ;round down\r
+       neg     ecx\r
+       add     ecx,[immediate_value]\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       setnz   al\r
+       movzx   eax,al\r
+       shl     eax,2\r
+       add     eax,4                                   ;offset=4 for THUMB and 8 for ARM\r
+       sub     ecx,eax\r
+       mov     [immediate_value],ecx\r
+       mov     eax,3                                   ;wrd,[rn,imm]\r
+    .offset_okay:\r
+       test    ebp,1 shl 8                             ;WLDRB/WLDRH?\r
+       jnz     .imm_adjusted\r
+       cmp     al,2                                    ;option?\r
+       jz      .imm_adjusted\r
+       shl     [immediate_value],2\r
+    .imm_adjusted:\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM_copro_crd_address5.version_check_okay\r
+\r
+IWMMXT_wrd_wrn_WMOV:\r
+       ;used by WMOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>               ;0=wrd,wrn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       or      ebp,eax\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn_wcm:\r
+       ;used by  WRORHG, WRORWG, WRORDG, WSLLHG, WSLLWG, WSLLDG, WSRAHG, WSRAWG, WSRADG, WSRLHG, WSRLWG, WSRLDG\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_creg>       ;0=wrd,wrn,wcm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wcm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn_imm:\r
+       ;used by WSHUFH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm>      ;0=wrd,wrn,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0xf\r
+       and     ecx,0xf0\r
+       shl     ecx,20-4\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xff\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_wrd:\r
+       ;used by WZERO\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg>                               ;0=wrd\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       or      ebp,eax\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       shl     eax,4\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+;IWMMXT V2\r
+\r
+IWMMXT_r15_v2:\r
+       ;used by TORVSCB, TORVSCH, TORVSCW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg>                                 ;0=r15\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       movzx   eax,[operand_register0]                 ;r15\r
+       cmp     eax,15                                  ;PC?\r
+       jnz     ERROR_must_be_r15.first\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_rd_rn_rm_imm:\r
+       ;used by WMERGE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm>      ;0=wrd,wrn,wrm,imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrm\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,7\r
+       ja      .out_of_range\r
+       shl     eax,21\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_rd_rn_v2:\r
+       ;used by WABSB, WABSH, WABSW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>               ;0=wrd,wrn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_rd_rn_rm_v2:\r
+       ;used by WABSDIFFB, WABSDIFFH, WABSDIFFW, WADDBHUSL, WADDBHUSM, WADDHC, WADDSUBHX, WADDWC,\r
+       ;        WAVG4, WAVG4R, WMADDSN, WMADDSX, WMADDUN, WMADDUX, WMIABB, WMIABBN, WMIABT, WMIABTN,\r
+       ;        WMIATB, WMIATBN, WMIATT, WMIATTN, WMIAWBB, WMIAWBBN, WMIAWBT, WMIAWBTN, WMIAWTB,\r
+       ;        WMIAWTBN, WMIAWTT, WMIAWTTN, WMULSMR, WMULUMR, WMULWL, WMULWSM, WMULWSMR, WMULWUM,\r
+       ;        WMULWUMR, WQMIABB, WQMIABBN, WQMIABT, WQMIABTN, WQMIATB, WQMIATBN, WQMIATT, WQMIATTN,\r
+       ;        WQMULM, WQMULMR, WQMULWM, WQMULWMR, WSUBADDHX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>       ;0=wrd,wrn,wrm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+\r
+IWMMXT_wrd_wrn_param:\r
+       ;used by WSLLH, WSLLW, WSLLD, WSRAH, WSRAW, WSRAD, WSRLH, WSRLW, WSRLD, WRORH, WRORW, WRORD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_iwmmx_wreg>,\     ;0=wrd,wrn,wrm\r
+       <TMPL_iwmmx_wreg,TMPL_iwmmx_wreg,TMPL_imm>              ;1=wrd,wrn,imm\r
+       cmp     al,1\r
+       jz      .wrd_wrn_imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V1\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v1\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;wrm\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .wrd_wrn_imm:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       or      ebp,0xf shl 28\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,32\r
+       ja      .out_of_range\r
+       cmp     eax,0\r
+       jz      .shift_0\r
+       mov     ecx,eax\r
+       and     ecx,0x10\r
+       and     eax,0x0f\r
+       shl     ecx,8-4\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_copro\r
+    .shift_0:\r
+       or      ebp,3 shl 20                            ;force to WROR\r
+       mov     ecx,ebp\r
+       and     ecx,3 shl 22\r
+       cmp     ecx,1 shl 22                            ;H?\r
+       jz      .shift_0_H\r
+       cmp     ecx,2 shl 22                            ;W?\r
+       jz      ARM_post_process_copro                  ;WRORW wrd,wrn,32\r
+    ;shift 0 D\r
+       and     ebp,not (0x10f00ff0)                    ;force to WOR\r
+       movzx   eax,[operand_register1]                 ;wrn\r
+       or      ebp,eax                                 ;WOR wrd,wrn,wrn\r
+       jmp     ARM_post_process_copro\r
+    .shift_0_H:\r
+       or      ebp,1 shl 8                             ;WRORH wrd,wrn,16\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_32\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+IWMMXT_wrd_address5_reg_offset_translate:\r
+       db      0       ;0      0=wrd,[rn]\r
+       db      -1      ;1\r
+       db      -1      ;2\r
+       db      1       ;3      1=wrd,[rn],imm\r
+       db      2       ;4      2=wrd,[rn],{imm}\r
+       db      3       ;5      3=wrd,[rn,imm]\r
+       db      4       ;6      4=wrd,[rn,imm]!\r
+       db      -1      ;7\r
+       db      -1      ;8\r
+       db      -1      ;9\r
+       db      -1      ;10\r
+       db      5       ;11     5=wrd,[imm]     PC relative\r
+       db      6       ;12     6=wrd,[exp]     implicit reg from structure\r
+       db      7       ;13     7=wrd,[exp]!    implicit reg from structure\r
+\r
+IWMMXT_wrd_address5_reg_offset:\r
+       ;used by WLDRD, WSTRD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\                                                                  ; 0=wrd,[rn]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg>,\                                                 ; 1=wrd,[rn],+-rm\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm>,\                          ; 2=wrd,[rn],+-rm,lsl imm\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_imm>,\                                                         ; 3=wrd,[rn],imm\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right,TMPL_option>,\                                                      ; 4=wrd,[rn],{imm}\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\                                                         ; 5=wrd,[rn,imm]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\                                   ; 6=wrd,[rn,imm]!\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right>,\                                                 ; 7=wrd,[rn,+-rm]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_bracket_right,TMPL_modifier_exclaim>,\                           ; 8=wrd,[rn,+-rm]!\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right>,\                          ; 9=wrd,[rn,+-rm,lsl imm]\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_base_reg,TMPL_add_sub_reg,TMPL_shift_op,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\    ;10=wrd,[rn,+-rm,lsl imm]!\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\                                                                   ;11=wrd,[imm]   PC relative\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                                                ;12=wrd,[exp]   implicit reg from structure\r
+       <TMPL_iwmmx_wreg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                                            ;13=wrd,[exp]!  implicit reg from structure\r
+       mov     cl,al\r
+       movzx   eax,al\r
+       mov     al,[eax+IWMMXT_wrd_address5_reg_offset_translate]\r
+       cmp     al,-1\r
+       jnz     IWMMXT_wrd_address5.do\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_IWMMXT_V2\r
+       jz      ERROR_requires_copro_capability_iwmmxt_v2\r
+       or      ebp,0xf shl 28\r
+       mov     al,[operand_register2]                  ;rm\r
+       movzx   edx,al\r
+       not     edx\r
+       and     edx,0x80                                ;get '+' state\r
+       shl     edx,23-7\r
+       or      ebp,edx                                 ;set U if '+'\r
+       and     al,0xf\r
+       cmp     al,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       mov     [operand_register2],al                  ;rm\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,15\r
+       ja      .out_of_range\r
+       cmp     cl,1\r
+       jz      .wrd_q_rn_p_PMrm\r
+       cmp     cl,2\r
+       jz      .wrd_q_rn_p_PMrm_lsl_imm\r
+       cmp     cl,7\r
+       jz      .wrd_q_rn_PMrm_p\r
+       cmp     cl,8\r
+       jz      .wrd_q_rn_PMrm_p!\r
+       cmp     cl,9\r
+       jz      .wrd_q_rn_PMrm_lsl_imm_p\r
+       cmp     cl,10\r
+       jz      .wrd_q_rn_PMrm_lsl_imm_p!\r
+       ud2\r
+    .wrd_q_rn_p_PMrm_lsl_imm:\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     ERROR_shift_type_must_be_LSL\r
+    .wrd_q_rn_p_PMrm:\r
+       or      ebp,1 shl 21                            ;set W\r
+       jmp     .encode\r
+    .wrd_q_rn_PMrm_lsl_imm_p!:\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     ERROR_shift_type_must_be_LSL\r
+    .wrd_q_rn_PMrm_p!:\r
+       or      ebp,1 shl 21 + 1 shl 24                 ;set W & P\r
+       jmp     .encode\r
+    .wrd_q_rn_PMrm_lsl_imm_p:\r
+       cmp     [instruction_shift_op],ARM_SHIFT_OPCODE_LSL\r
+       jnz     ERROR_shift_type_must_be_LSL\r
+    .wrd_q_rn_PMrm_p:\r
+       or      ebp,1 shl 24                            ;set P\r
+    .encode:\r
+       movzx   eax,[operand_register0]                 ;wrd\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       shl     eax,4\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_15\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+;SIMD\r
+\r
+SIMD_INT_vd_vn_vm:\r
+       ;used by VABA.S16, VABA.S32, VABA.S8, VABA.U16, VABA.U32, VABA.U8,\r
+       ;        VMLA.S8, VMLA.U8, VMLA.I8, VMLS.S8, VMLS.U8, VMLS.I8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;0=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;1=qd,qn,qm\r
+    .int_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+    .encode:\r
+       movzx   eax,al\r
+       shl     eax,6\r
+       or      ebp,eax                                 ;set Q bit\r
+       movzx   eax,[operand_register0]                 ;vd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22                                  ;D bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;vn\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,16\r
+       shl     ecx,7                                   ;N bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register2]                 ;vm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5                                   ;M bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction\r
+       cmp     ebp,0xf0000000\r
+       jb      ARM_post_process_copro.thumb\r
+       jmp     ARM_post_process_simd\r
+\r
+SIMD_INT_vd_vn_vm_alt:\r
+       ;used by VABD.S16, VABD.S32, VABD.S8, VABD.U16, VABD.U32, VABD.U8,\r
+       ;        VADD.I8, VADD.I16, VADD.I32, VADD.I64, VAND, VBIC, VBIF, VBIT, VBSL,\r
+       ;        VCGE.U8, VCGE.U16, VCGE.U32, VCGT.U8, VCGT.U16, VCGT.U32, VEOR,\r
+       ;        VHADD.S8, VHADD.S16, VHADD.S32, VHADD.U8, VHADD.U16, VHADD.U32,\r
+       ;        VHSUB.S8, VHSUB.S16, VHSUB.S32, VHSUB.U8, VHSUB.U16, VHSUB.U32,\r
+       ;        VMAX.S8, VMAX.S16, VMAX.S32, VMAX.U8, VMAX.U16, VMAX.U32,\r
+       ;        VMIN.S8, VMIN.S16, VMIN.S32, VMIN.U8, VMIN.U16, VMIN.U32,\r
+       ;        VMUL.I8, VMUL.S8, VMUL.S16, VMUL.S32, VMUL.U8, VMUL.U16, VMUL.U32, VMUL.P8,\r
+       ;        VQADD.S8, VQADD.S16, VQADD.S32, VQADD.S64, VQADD.U8, VQADD.U16, VQADD.U32, VQADD.U64,\r
+       ;        VQRSHL.S8, VQRSHL.S16, VQRSHL.S32, VQRSHL.S64, VQRSHL.U8, VQRSHL.U16, VQRSHL.U32, VQRSHL.U64,\r
+       ;        VQSUB.S8, VQSUB.S16, VQSUB.S32, VQSUB.S64, VQSUB.U8, VQSUB.U16, VQSUB.U32, VQSUB.U64,\r
+       ;        VRHADD.S8, VRHADD.S16, VRHADD.S32, VRHADD.U8, VRHADD.U16, VRHADD.U32,\r
+       ;        VRSHL.S16, VRSHL.S32, VRSHL.S64, VRSHL.S8, VRSHL.U16, VRSHL.U32, VRSHL.U64, VRSHL.U8,\r
+       ;        VSHL.S16, VSHL.S32, VSHL.S64, VSHL.S8, VSHL.U16, VSHL.U32, VSHL.U64, VSHL.U8,\r
+       ;        VSUB.I8, VSUB.I16, VSUB.I32, VSUB.I64, VTST.8, VTST.16, VTST.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;1=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;3=qd,qn,qm\r
+    .encode:\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm.int_test\r
+       mov     cx,word[operand_registers+0]\r
+       mov     word[operand_registers+1],cx\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+\r
+SIMD_INT_vd_vn_vm_alt_zero:\r
+       ;used by VCEQ.I8, VCEQ.I16, VCEQ.I32, VCGE.S8, VCGE.S16, VCGE.S32, VCGT.S8, VCGT.S16, VCGT.S32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qdm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;5=qd,qm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       test    al,010b\r
+       jnz     .not_zero\r
+    .zero:\r
+       cmp     [immediate_value],0\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       jnz     ARM_post_process_simd_with_error\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       mov     ah,al\r
+       shr     al,2\r
+       test    ah,1\r
+       jnz     SIMD_INT_vd_vm.int_test\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+       jmp     SIMD_INT_vd_vm.int_test\r
+    .not_zero:\r
+       mov     ah,al\r
+       and     ax,0x0401\r
+       shr     ah,1\r
+       or      al,ah\r
+       jmp     SIMD_INT_vd_vn_vm_alt.encode\r
+\r
+SIMD_INT_vd_vn_vm_long:\r
+       ;used by VABAL.S16, VABAL.S32, VABAL.S8, VABAL.U16, VABAL.U32, VABAL.U8,\r
+       ;        VABDL.S16, VABDL.S32, VABDL.S8, VABDL.U16, VABDL.U32, VABDL.U8,\r
+       ;        VADDL.S16, VADDL.S32, VADDL.S8, VADDL.U16, VADDL.U32, VADDL.U8,\r
+       ;        VSUBL.S16, VSUBL.S32, VSUBL.S8, VSUBL.U16, VSUBL.U32, VSUBL.U8,\r
+       ;        VMLAL.S8, VMLAL.U8, VMLSL.S8, VMLSL.U8, VMULL.S8, VMULL.U8, VMULL.P8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg>    ;0=qd,dn,dm\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+\r
+SIMD_INT_vd_vn_vm_wide:\r
+       ;used by VADDW.S16, VADDW.S32, VADDW.S8, VADDW.U16, VADDW.U32, VADDW.U8\r
+       ;        VSUBW.S16, VSUBW.S32, VSUBW.S8, VSUBW.U16, VSUBW.U32, VSUBW.U8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg>,\                ;0=qdn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpd_reg>   ;1=qd,qn,dm\r
+       jmp     SIMD_INT_vd_vn_vm_alt.encode\r
+\r
+SIMD_FLOAT_vd_vn_vm_alt:\r
+       ;used by VABD.F32, VACGE.F32, VACGT.F32, VMAX.F32, VMIN.F32, VRECPS.F32, VRSQRTS.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;1=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;3=qd,qn,qm\r
+    .float_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm.encode\r
+       mov     cx,word[operand_registers+0]\r
+       mov     word[operand_registers+1],cx\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_FLOAT_vd_vn_vm_alt_zero:\r
+       ;used by VCEQ.F32, VCGE.F32, VCGT.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qdm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;5=qd,qm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       test    al,010b\r
+       jnz     .not_zero\r
+    .zero:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       cmp     [immediate_value],0\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       jnz     ARM_post_process_simd_with_error\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       mov     ah,al\r
+       shr     al,2\r
+       test    ah,1\r
+       jnz     SIMD_INT_vd_vm.encode\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+       jmp     SIMD_INT_vd_vm.encode\r
+    .not_zero:\r
+       mov     ah,al\r
+       and     ax,0x0401\r
+       shr     ah,1\r
+       or      al,ah\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt.float_test\r
+\r
+SIMD_FLOAT_vd_vm_vn_alt:\r
+       ;used by VACLE.F32, VACLT.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddm,dn\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;1=dd,dm,dn\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qdm,qn\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;3=qd,qm,qn\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+    .swap:\r
+       mov     cx,word[operand_registers+1]\r
+       xchg    ch,cl\r
+       mov     word[operand_registers+1],cx\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm.encode\r
+       mov     cl,ch\r
+       mov     ch,[operand_register0]\r
+       mov     word[operand_registers+1],cx\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_INT_vd_vn_vm_alt_swap:\r
+       ;used by VCLE.U8, VCLE.U16, VCLE.U32, VCLT.U8, VCLT.U16, VCLT.U32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;1=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;3=qd,qn,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       jmp     SIMD_FLOAT_vd_vm_vn_alt.swap\r
+\r
+SIMD_INT_vd_vn_vm_alt_zero_swap:\r
+       ;used by VCLE.S8, VCLE.S16, VCLE.S32, VCLT.S8, VCLT.S16, VCLT.S32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qdm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;5=qd,qm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       test    al,010b\r
+       jz      SIMD_INT_vd_vn_vm_alt_zero.zero\r
+       mov     ah,al\r
+       and     ax,0x0401\r
+       shr     ah,1\r
+       or      al,ah\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       jmp     SIMD_FLOAT_vd_vm_vn_alt.swap\r
+\r
+SIMD_FLOAT_vd_vn_vm_alt_zero_swap:\r
+       ;used by VCLE.F32, VCLT.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,0\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qdm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;5=qd,qm,0\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       test    al,010b\r
+       jz      SIMD_FLOAT_vd_vn_vm_alt_zero.zero\r
+       mov     ah,al\r
+       and     ax,0x0401\r
+       shr     ah,1\r
+       or      al,ah\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       jmp     SIMD_FLOAT_vd_vm_vn_alt.swap\r
+\r
+SIMD_INT_vd_vm:\r
+       ;used by VABS.S8, VABS.S16, VABS.S32, VCLS.S8, VCLS.S16, VCLS.S32, VCLZ.S8, VCLZ.S16, VCLZ.S32, VCNT.8,\r
+       ;        VMVN, VNEG.S8, VNEG.S16, VNEG.S32, VPADAL.S8, VPADAL.S16, VPADAL.S32, VPADAL.U8, VPADAL.U16, VPADAL.U32\r
+       ;        VPADDL.S8, VPADDL.S16, VPADDL.S32, VPADDL.U8, VPADDL.U16, VPADDL.U32, VQABS.S8, VQABS.S16, VQABS.S32,\r
+       ;        VQNEG.S8, VQNEG.S16, VQNEG.S32, VRECPE.U32, VREV16.8, VREV32.16, VREV32.8, VREV64.16, VREV64.32, VREV64.8,\r
+       ;        VRSQRTE.U32, VSWP, VTRN.8, VTRN.16, VTRN.32, VUZP.8, VUZP.16, VUZP.32, VZIP.8, VZIP.16, VZIP.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=dd,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>                 ;1=qd,qm\r
+    .int_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+    .encode:\r
+       movzx   eax,al\r
+       shl     eax,6\r
+       or      ebp,eax                                 ;set Q bit\r
+       movzx   eax,[operand_register0]                 ;vd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22                                  ;D bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;vm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5                                   ;M bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_simd\r
+\r
+SIMD_FLOAT_vd_vm_imm:\r
+       ;used by VCVT.F32.S32, VCVT.F32.U32, VCVT.S32.F32, VCVT.U32.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=dd,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qd,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;3=qd,qm,imm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;4=sd,sm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_imm>,\        ;5=sd,sm,imm\r
+       <TMPL_vfps_reg,TMPL_imm>                        ;6=sdm,imm\r
+       cmp     al,6\r
+       jnz     .registers_okay\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+       mov     al,5\r
+    .registers_okay:\r
+       shr     al,1\r
+       jnc     SIMD_FLOAT_vd_vm_f32.encode\r
+    ;recode for immediate forms\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       and     ecx,1 shl 7                             ;signed=0, unsigned=1\r
+       and     edx,1 shl 8                             ;to float=0, to int=1\r
+       shl     edx,(18-8)-(16-7)\r
+       or      edx,ecx\r
+       shl     edx,16-7\r
+       or      edx,0x0eba0ac0                          ;fsltos\r
+       mov     [thumb32_instruction],edx\r
+       shl     ecx,24-7\r
+       and     ebp,1 shl 8\r
+       or      ebp,ecx\r
+       or      ebp,0xf2a00e10                          ;vcvt.f32.s32 without imm\r
+       cmp     al,2\r
+       jz      .VFP_alias\r
+       mov     ecx,[immediate_value]\r
+       cmp     ecx,1\r
+       jb      .out_of_range\r
+       cmp     ecx,32\r
+       ja      .out_of_range\r
+       mov     edx,32\r
+       sub     edx,ecx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       jmp     SIMD_FLOAT_vd_vm_f32.float_test\r
+    .VFP_alias:\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       jmp     VFP_dd_dd_imm.do\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_32\r
+       jmp     ARM_post_process_copro_with_error\r
+\r
+SIMD_FLOAT_vd_vm_f32:\r
+       ;used by VABS.F32, VNEG.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=dd,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;1=qd,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>                   ;2=sd,sm\r
+    .encode:\r
+       cmp     al,2\r
+       jnz     .float_test\r
+    ;VFP alias\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       jmp     VFP_sd_sm.v1xd_test\r
+    .float_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       jmp     SIMD_INT_vd_vm.encode\r
+\r
+SIMD_FLOAT_vd_vn_vm_f32:\r
+       ;used by VADD.F32, VSUB.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;1=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;2=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;3=qd,qn,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;4=sdn,sm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;5=sd,sn,sm\r
+    .do:\r
+       cmp     al,4\r
+       jb      SIMD_FLOAT_vd_vn_vm_alt.float_test\r
+    ;VFP alias\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       sub     al,4\r
+       jmp     VFP_sd_sn_sm.v1xd_test\r
+\r
+SIMD_INT_vd_vn_vm_narrow:\r
+       ;used by VADDHN.I16, VADDHN.I32, VADDHN.I64, VRADDHN.I16, VRADDHN.I32, VRADDHN.I64,\r
+       ;        VRSUBHN.I16, VRSUBHN.I32, VRSUBHN.I64, VSUBHN.I16, VSUBHN.I32, VSUBHN.I64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_simd_qreg,TMPL_simd_qreg>   ;0=dd,qn,qm\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+\r
+SIMD_INT_vd_imm:\r
+       ;used by VAND.I32, VAND.I16, VBIC.I32, VBIC.I16, VORN.I32, VORN.I16, VORR.I32, VORR.I16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;0=qd,imm\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,imm\r
+       mov     ecx,[immediate_value]\r
+       btr     ebp,0                                   ;test for VAND\r
+       jnc     .inversion_done\r
+       not     ecx\r
+       test    ebp,1000b shl 8                         ;test for .I16 instruction\r
+       jz      .inversion_done\r
+       cmp     ecx,0xffff0000\r
+       jb      .inversion_done\r
+       movzx   ecx,cx\r
+    .inversion_done:\r
+       test    ecx,not 0xff\r
+       jz      .encode\r
+       xor     ebp,0010b shl 8\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      .encode\r
+       test    ebp,1000b shl 8                         ;test for .I16 instruction\r
+       jnz     .out_of_range\r
+       xor     ebp,0110b shl 8\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      .encode\r
+       xor     ebp,0010b shl 8\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jnz     .out_of_range\r
+    .encode:\r
+       and     eax,1\r
+       xor     eax,1\r
+       shl     eax,6\r
+       or      ebp,eax                                 ;set Q\r
+       mov     eax,ecx\r
+       mov     edx,ecx\r
+       and     eax,0x0f\r
+       and     ecx,0x70\r
+       and     edx,0x80\r
+       shl     ecx,16-4\r
+       shl     edx,24-7\r
+       or      ebp,eax                                 ;imm4\r
+       or      ebp,ecx                                 ;imm3\r
+       or      ebp,edx                                 ;i\r
+       movzx   eax,[operand_register0]                 ;vd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22                                  ;D bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM_post_process_simd\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_FLOAT_qd_dm:\r
+       ;used by VCVT.F32.F16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg>                  ;0=qd,dm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_HP\r
+       jz      ERROR_requires_copro_capability_simd_hp\r
+       jmp     SIMD_INT_vd_vm.encode\r
+\r
+SIMD_FLOAT_dd_qm:\r
+       ;used by VCVT.F16.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_simd_qreg>                  ;0=dd,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_HP\r
+       jz      ERROR_requires_copro_capability_simd_hp\r
+       jmp     SIMD_INT_vd_vm.encode\r
+\r
+SIMD_INT_qd_dmx:\r
+       ;used by VDUP.8, VDUP.16, VDUP.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\                ;0=dd,dm[x]\r
+       <TMPL_vfpd_reg,TMPL_base_reg>,\                 ;1=dd,rt\r
+       <TMPL_simd_qreg,TMPL_vfpdx_reg>,\               ;2=qd,dm[x]\r
+       <TMPL_simd_qreg,TMPL_base_reg>                  ;3=qd,rt\r
+       shr     al,1\r
+       jc      .reg\r
+       mov     ecx,ebp\r
+       shr     ecx,16\r
+       and     ecx,0xf                                 ;ecx=1, 2 or 3 for 8, 16 or 32 size\r
+       and     ebp,not (0xf shl 16)\r
+       mov     edx,16\r
+       shr     edx,cl\r
+       cmp     edx,[immediate_value]\r
+       jbe     .out_of_range\r
+       mov     edx,[immediate_value]\r
+       shl     edx,1\r
+       or      edx,1\r
+       add     ecx,16-1\r
+       shl     edx,cl\r
+       or      ebp,edx\r
+       jmp     SIMD_INT_vd_vm.int_test\r
+    .reg:\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       shl     eax,21\r
+       or      ebp,eax                                 ;set Q\r
+       movzx   eax,[operand_register0]                 ;vd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,16\r
+       shl     ecx,7                                   ;D bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;rt\r
+       cmp     eax,15                                  ;PC?\r
+       jz      ERROR_r15_not_valid\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_post_process_copro\r
+       cmp     eax,13 shl 12                           ;SP?\r
+       jz      ERROR_r13_not_valid\r
+       jmp     ARM_post_process_copro\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_INT_vd_vn_vm_imm:\r
+       ;used by VEXT.8, VEXT.16, VEXT.32, VEXT.64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\                ;0=ddn,dm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\  ;1=dd,dn,dm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\              ;2=qdn,qm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm> ;3=qd,qn,qm,imm\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,ebp\r
+       shr     ecx,8\r
+       and     ecx,0xf                                 ;ecx=multiplier\r
+       imul    edx,ecx\r
+       mov     ecx,eax\r
+       shr     ecx,1\r
+       and     ecx,1\r
+       xor     ecx,1\r
+       shl     edx,cl\r
+       cmp     edx,16\r
+       jae     .out_of_range\r
+       shr     edx,cl\r
+       and     ebp,not (0xf shl 8)\r
+       shl     edx,8\r
+       or      ebp,edx\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm.int_test\r
+       mov     cx,word[operand_registers+0]\r
+       mov     word[operand_registers+1],cx\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_INT_list_rn_rm_1:\r
+       ;used by VLD1.8, VLD1.16, VLD1.32, VLD1.64, VST1.8, VST1.16, VST1.32, VST1.64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\                           ;0={dy[x]},[rn]\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;1={dy[x]},[rn]!\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\             ;2={dy[x]},[rn],rm\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm>                    ;3={dy[x]},[rn],imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       jz      .element\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       jz      .vector\r
+    ;register\r
+       mov     ah,[simd_reg_list_count]\r
+       xor     ecx,ecx\r
+       mov     edx,7 shl 8                             ;type = 0111\r
+       cmp     ah,1\r
+       cmovz   ecx,edx\r
+       mov     edx,10 shl 8                            ;type = 1010\r
+       cmp     ah,2\r
+       cmovz   ecx,edx\r
+       mov     edx,6 shl 8                             ;type = 0110\r
+       cmp     ah,3\r
+       cmovz   ecx,edx\r
+       mov     edx,2 shl 8                             ;type = 0010\r
+       cmp     ah,4\r
+       cmovz   ecx,edx\r
+       or      ebp,ecx\r
+       test    ecx,ecx\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       mov     ah,[operand_register0]                  ;rn\r
+       mov     ecx,0 shl 4                             ;align = 00\r
+       shr     ah,4\r
+       jz      .set_alignment\r
+       mov     ecx,1 shl 4                             ;align = 01\r
+       cmp     ah,3                                    ;@64\r
+       jz      .set_alignment\r
+       mov     ecx,2 shl 4                             ;align = 10\r
+       cmp     ah,4                                    ;@128\r
+       jz      .set_alignment\r
+       cmp     ah,5                                    ;@256\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,3 shl 4                             ;align = 11\r
+    .set_alignment:\r
+       or      ebp,ecx\r
+       movzx   ebx,[simd_reg_list_count]\r
+       shl     ebx,3                                   ;ebx=writeback offset\r
+    .encode:\r
+       mov     edx,0xf\r
+       cmp     al,0\r
+       jz      .set_rm\r
+       mov     edx,0xd\r
+       cmp     al,1\r
+       jz      .set_rm\r
+       movzx   edx,[operand_register1]                 ;rm\r
+       mov     ecx,ERROR_r13_r15_not_valid.third\r
+       cmp     edx,13\r
+       jz      ARM_post_process_simd_with_error\r
+       cmp     edx,15\r
+       jz      ARM_post_process_simd_with_error\r
+       cmp     al,2\r
+       jz      .set_rm\r
+    ;immediate post update\r
+       cmp     ebx,[immediate_value]\r
+       mov     ecx,ERROR_immediate_offset_out_of_range\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     edx,0xd\r
+    .set_rm:\r
+       or      ebp,edx\r
+       movzx   eax,[simd_reg_list_first]               ;vd\r
+       mov     ecx,eax\r
+       and     eax,0x0f\r
+       and     ecx,0x10\r
+       shl     eax,12\r
+       shl     ecx,22-4                                ;D bit\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register0]                 ;rn\r
+       and     eax,0xf\r
+       cmp     eax,0xf\r
+       mov     ecx,ERROR_r15_not_valid.second\r
+       jz      ARM_post_process_simd_with_error\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_post_process_simd\r
+    .element:\r
+       or      ebp,1 shl 23\r
+       cmp     [simd_reg_list_count],1\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       cmp     edx,3 shl 6                             ;.64 size?\r
+       mov     ecx,ERROR_use_fldr_for_single_reg\r
+       jz      ARM_post_process_simd_with_error\r
+       and     ebp,not (3 shl 6)\r
+       shl     edx,10-6\r
+       or      ebp,edx\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 10\r
+       movzx   edx,[simd_reg_list_x]\r
+       ja      .element.32\r
+       jz      .element.16\r
+   ;element.8\r
+       test    ah,ah\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       cmp     edx,7\r
+       mov     ecx,ERROR_element_value_out_of_range.0_7\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,4+1\r
+       or      ebp,edx\r
+       mov     ebx,1\r
+       jmp     .encode\r
+    .element.16:\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     edx,3\r
+       mov     ecx,ERROR_element_value_out_of_range.0_3\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,2\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,2\r
+       jmp     .encode\r
+    .element.32:\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,3\r
+       or      dl,ah\r
+       shr     ah,1\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     .encode\r
+    .vector:\r
+       mov     ecx,ERROR_register_list_invalid\r
+       test    ebp,1 shl 21                            ;VST1=0\r
+       jz      ARM_post_process_simd_with_error\r
+       or      ebp,1 shl 23 + 3 shl 10\r
+       movzx   edx,[simd_reg_list_count]\r
+       cmp     edx,2\r
+       mov     ecx,ERROR_register_list_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     edx\r
+       shl     edx,5\r
+       or      ebp,edx                                 ;set T bit\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       cmp     edx,3 shl 6                             ;.64 size?\r
+       mov     ecx,ERROR_reg_size_64_not_encodable\r
+       jz      ARM_post_process_simd_with_error\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 6\r
+       movzx   edx,ah\r
+       ja      .vector.32\r
+       jz      .vector.16\r
+   ;vector.8\r
+       test    ah,ah\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ebx,1\r
+       jmp     .encode\r
+    .vector.16:\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,2\r
+       jmp     .encode\r
+    .vector.32:\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       shl     edx,3\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     .encode\r
+\r
+SIMD_INT_list_rn_rm_2:\r
+       ;used by VLD2.8, VLD2.16, VLD2.32, VST2.8, VST2.16, VST2.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\                           ;0={dy[x]},[rn]\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;1={dy[x]},[rn]!\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\             ;2={dy[x]},[rn],rm\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm>                    ;3={dy[x]},[rn],imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       jz      .element\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       jz      .vector\r
+    ;register\r
+       mov     ah,[simd_reg_list_count]\r
+       xor     ecx,ecx\r
+       mov     edx,8 shl 8                             ;type = 1000\r
+       cmp     ah,2\r
+       cmovz   ecx,edx\r
+       mov     edx,9 shl 8                             ;type = 1001\r
+       cmp     ah,0x82\r
+       cmovz   ecx,edx\r
+       mov     edx,3 shl 8                             ;type = 0011\r
+       cmp     ah,4\r
+       cmovz   ecx,edx\r
+       or      ebp,ecx\r
+       test    ecx,ecx\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       mov     ah,[operand_register0]                  ;rn\r
+       mov     ecx,0 shl 4                             ;align = 00\r
+       shr     ah,4\r
+       jz      .set_alignment\r
+       mov     ecx,1 shl 4                             ;align = 01\r
+       cmp     ah,3                                    ;@64\r
+       jz      .set_alignment\r
+       mov     ecx,2 shl 4                             ;align = 10\r
+       cmp     ah,4                                    ;@128\r
+       jz      .set_alignment\r
+       cmp     ah,5                                    ;@256\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       cmp     [simd_reg_list_count],4\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,3 shl 4                             ;align = 11\r
+    .set_alignment:\r
+       or      ebp,ecx\r
+       mov     bl,[simd_reg_list_count]\r
+       and     ebx,0x7f\r
+       shl     ebx,3                                   ;ebx=writeback offset\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element:\r
+       or      ebp,1 shl 23 + 1 shl 8\r
+       mov     cl,[simd_reg_list_count]\r
+       test    ebp,3 shl 6                             ;.8?\r
+       setz    ch\r
+       shl     ch,7\r
+       or      ch,0x7f\r
+       and     cl,ch\r
+       cmp     cl,2\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       and     ebp,not (3 shl 6)\r
+       shl     edx,10-6\r
+       or      ebp,edx\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 10\r
+       movzx   edx,[simd_reg_list_x]\r
+       ja      .element.32\r
+       jz      .element.16\r
+   ;element.8\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     edx,7\r
+       mov     ecx,ERROR_element_value_out_of_range.0_7\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,2\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.16:\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       cmp     edx,3\r
+       mov     ecx,ERROR_element_value_out_of_range.0_3\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       mov     cl,[simd_reg_list_count]\r
+       shr     cl,7\r
+       or      dl,cl\r
+       shl     edx,1\r
+       shr     ah,1\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.32:\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       mov     cl,[simd_reg_list_count]\r
+       shr     cl,7\r
+       or      dl,cl\r
+       shl     edx,2\r
+       and     ah,1\r
+       xor     ah,1\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,8\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector:\r
+       mov     ecx,ERROR_register_list_invalid\r
+       test    ebp,1 shl 21                            ;VST2=0\r
+       jz      ARM_post_process_simd_with_error\r
+       or      ebp,1 shl 23 + 0xd shl 8\r
+       mov     dl,[simd_reg_list_count]\r
+       mov     dh,dl\r
+       and     dx,0x7f80\r
+       cmp     dh,2\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       shr     edx,7-5\r
+       and     edx,0x20\r
+       or      ebp,edx                                 ;set T bit\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 6\r
+       movzx   edx,ah\r
+       ja      .vector.32\r
+       jz      .vector.16\r
+   ;vector.8\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,2\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector.16:\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       shl     edx,3\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector.32:\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       and     edx,1\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,8\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+\r
+SIMD_INT_list_rn_rm_3:\r
+       ;used by VLD3.8, VLD3.16, VLD3.32, VST3.8, VST3.16, VST3.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\                           ;0={dy[x]},[rn]\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;1={dy[x]},[rn]!\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\             ;2={dy[x]},[rn],rm\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm>                    ;3={dy[x]},[rn],imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       jz      .element\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       jz      .vector\r
+    ;register\r
+       mov     ah,[simd_reg_list_count]\r
+       xor     ecx,ecx\r
+       mov     edx,4 shl 8                             ;type = 0100\r
+       cmp     ah,3\r
+       cmovz   ecx,edx\r
+       mov     edx,5 shl 8                             ;type = 0101\r
+       cmp     ah,0x83\r
+       cmovz   ecx,edx\r
+       or      ebp,ecx\r
+       test    ecx,ecx\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       mov     ah,[operand_register0]                  ;rn\r
+       mov     ecx,0 shl 4                             ;align = 00\r
+       shr     ah,4\r
+       jz      .set_alignment\r
+       cmp     ah,3                                    ;@64\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,1 shl 4                             ;align = 01\r
+    .set_alignment:\r
+       or      ebp,ecx\r
+       mov     ebx,24                                  ;ebx=writeback offset\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element:\r
+       or      ebp,1 shl 23 + 2 shl 8\r
+       mov     ah,[simd_reg_list_count]\r
+       and     ah,0x7f\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       and     ebp,not (3 shl 6)\r
+       shl     edx,10-6\r
+       or      ebp,edx\r
+       mov     ah,[simd_reg_list_count]\r
+       shr     ah,7\r
+       test    [operand_register0],0xf0\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       cmp     edx,1 shl 10\r
+       movzx   edx,[simd_reg_list_x]\r
+       ja      .element.32\r
+       jz      .element.16\r
+   ;element.8\r
+       test    [simd_reg_list_count],0x80\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       cmp     edx,7\r
+       mov     ecx,ERROR_element_value_out_of_range.0_7\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,4+1\r
+       or      ebp,edx\r
+       mov     ebx,3\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.16:\r
+       cmp     edx,3\r
+       mov     ecx,ERROR_element_value_out_of_range.0_3\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       or      dl,ah\r
+       shl     edx,4+1\r
+       or      ebp,edx\r
+       mov     ebx,6\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.32:\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       or      dl,ah\r
+       shl     edx,4+2\r
+       or      ebp,edx\r
+       mov     ebx,12\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector:\r
+       mov     ecx,ERROR_register_list_invalid\r
+       test    ebp,1 shl 21                            ;VST3=0\r
+       jz      ARM_post_process_simd_with_error\r
+       or      ebp,1 shl 23 + 0xe shl 8\r
+       mov     ah,[simd_reg_list_count]\r
+       and     ah,0x7f\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       movzx   edx,[simd_reg_list_count]\r
+       shr     edx,7-5\r
+       or      ebp,edx                                 ;set T bit\r
+       test    [operand_register0],0xf0\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,ebp\r
+       shr     ecx,6\r
+       and     ecx,3\r
+       mov     ebx,3\r
+       shl     ebx,cl\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+\r
+SIMD_INT_list_rn_rm_4:\r
+       ;used by VLD4.8, VLD4.16, VLD4.32, VST4.8, VST4.16, VST4.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right>,\                           ;0={dy[x]},[rn]\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;1={dy[x]},[rn]!\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_base_reg>,\             ;2={dy[x]},[rn],rm\r
+       <TMPL_simd_reg_list,TMPL_bracket_left,TMPL_address_reg@,TMPL_bracket_right,TMPL_imm>                    ;3={dy[x]},[rn],imm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_ELEMENT\r
+       jz      .element\r
+       cmp     [simd_reg_list_type],SIMD_REG_LIST_TYPE_VECTOR\r
+       jz      .vector\r
+    ;register\r
+       mov     ah,[simd_reg_list_count]\r
+       or      ecx,-1\r
+       mov     edx,0 shl 8                             ;type = 0000\r
+       cmp     ah,4\r
+       cmovz   ecx,edx\r
+       mov     edx,1 shl 8                             ;type = 0001\r
+       cmp     ah,0x84\r
+       cmovz   ecx,edx\r
+       or      ebp,ecx\r
+       inc     ecx\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       mov     ah,[operand_register0]                  ;rn\r
+       mov     ecx,0 shl 4                             ;align = 00\r
+       shr     ah,4\r
+       jz      .set_alignment\r
+       mov     ecx,1 shl 4                             ;align = 01\r
+       cmp     ah,3                                    ;@64\r
+       jz      .set_alignment\r
+       mov     ecx,2 shl 4                             ;align = 10\r
+       cmp     ah,4                                    ;@128\r
+       jz      .set_alignment\r
+       cmp     ah,5                                    ;@256\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,3 shl 4                             ;align = 11\r
+    .set_alignment:\r
+       or      ebp,ecx\r
+       mov     ebx,32\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element:\r
+       or      ebp,1 shl 23 + 3 shl 8\r
+       mov     cl,[simd_reg_list_count]\r
+       test    ebp,3 shl 6                             ;.8?\r
+       setz    ch\r
+       shl     ch,7\r
+       or      ch,0x7f\r
+       and     cl,ch\r
+       cmp     cl,4\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       and     ebp,not (3 shl 6)\r
+       shl     edx,10-6\r
+       or      ebp,edx\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 10\r
+       movzx   edx,[simd_reg_list_x]\r
+       ja      .element.32\r
+       jz      .element.16\r
+   ;element.8\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       cmp     edx,7\r
+       mov     ecx,ERROR_element_value_out_of_range.0_7\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,2\r
+       or      dl,ah\r
+       shl     edx,3\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.16:\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       cmp     edx,3\r
+       mov     ecx,ERROR_element_value_out_of_range.0_3\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       mov     cl,[simd_reg_list_count]\r
+       shr     cl,7\r
+       or      dl,cl\r
+       shl     edx,1\r
+       and     ah,1\r
+       xor     ah,1\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,8\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .element.32:\r
+       cmp     ah,4\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,1\r
+       mov     cl,[simd_reg_list_count]\r
+       shr     cl,7\r
+       or      dl,cl\r
+       shl     edx,2\r
+       inc     ah\r
+       shr     ah,1\r
+       and     ah,3\r
+       or      dl,ah\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,16\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector:\r
+       mov     ecx,ERROR_register_list_invalid\r
+       test    ebp,1 shl 21                            ;VST4=0\r
+       jz      ARM_post_process_simd_with_error\r
+       or      ebp,1 shl 23 + 0xf shl 8\r
+       mov     dl,[simd_reg_list_count]\r
+       mov     dh,dl\r
+       and     dx,0x7f80\r
+       cmp     dh,4\r
+       mov     ecx,ERROR_register_list_invalid\r
+       jnz     ARM_post_process_simd_with_error\r
+       shr     edx,7-5\r
+       and     edx,0x20\r
+       or      ebp,edx                                 ;set T bit\r
+       mov     edx,ebp\r
+       and     edx,3 shl 6\r
+       mov     ah,[operand_register0]                  ;rn\r
+       shr     ah,4\r
+       cmp     edx,1 shl 6\r
+       movzx   edx,ah\r
+       ja      .vector.32\r
+       jz      .vector.16\r
+   ;vector.8\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       cmp     ah,1\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jz      ARM_post_process_simd_with_error\r
+       shl     edx,3\r
+       or      ebp,edx\r
+       mov     ebx,4\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector.16:\r
+       cmp     ah,3\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       and     edx,1\r
+       shl     edx,4\r
+       or      ebp,edx\r
+       mov     ebx,8\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+    .vector.32:\r
+       cmp     ah,4\r
+       mov     ecx,ERROR_alignment_invalid\r
+       ja      ARM_post_process_simd_with_error\r
+       dec     ah\r
+       cmp     ah,2\r
+       mov     ecx,ERROR_alignment_invalid\r
+       jb      ARM_post_process_simd_with_error\r
+       and     edx,4\r
+       shl     edx,6-2\r
+       not     ah\r
+       and     ah,0x10\r
+       or      dl,ah\r
+       or      ebp,edx\r
+       mov     ebx,16\r
+       jmp     SIMD_INT_list_rn_rm_1.encode\r
+\r
+SIMD_INT_rn_list:\r
+       ;used by VLDMIA, VLDMDB, VSTMIA, VSTMDB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfp_reg_list_s>,\           ;0=rn,{s..}\r
+       <TMPL_base_reg,TMPL_vfp_reg_list_d>,\           ;1=rn,{d..}\r
+       <TMPL_base_reg!,TMPL_vfp_reg_list_s>,\          ;2=rn!,{s..}\r
+       <TMPL_base_reg!,TMPL_vfp_reg_list_d>            ;3=rn!,{d..}\r
+       shr     al,1\r
+       jnc     VFP_rn_list_s.do\r
+       or      ebp,1 shl 8\r
+       jmp     VFP_rn_list_d.do\r
+\r
+SIMD_INT_vd_rn_offset:\r
+       ;used by VLDR, VSTR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\            ;0=sd,[rn]\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\   ;1=sd,[rn,imm]\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\             ;2=sd,[imm]     PC relative\r
+       <TMPL_vfps_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\          ;3=sd,[exp]     implicit reg from structure\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\            ;4=dd,[rn]\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\   ;5=dd,[rn,imm]\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_address,TMPL_bracket_right>,\             ;6=dd,[imm]     PC relative\r
+       <TMPL_vfpd_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>            ;7=dd,[exp]     implicit reg from structure\r
+       cmp     al,3\r
+       jbe     VFP_sd_rn_offset.do\r
+       or      ebp,1 shl 8\r
+       sub     al,4\r
+       jmp     VFP_dd_rn_offset.do\r
+\r
+SIMD_INT_vd_vn_vmx:\r
+       ;used by VMLA.S16, VMLA.S32, VMLA.U16, VMLA.U32, VMLA.I16, VMLA.I32,\r
+       ;        VMLS.S16, VMLS.S32, VMLS.U16, VMLS.U32, VMLS.I16, VMLS.I32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;0=dd,dn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\  ;1=dd,dn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;2=qd,qn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>  ;3=qd,qn,dm[x]\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       shr     al,1\r
+       jnc     SIMD_INT_vd_vn_vm.encode\r
+       mov     ecx,ebp\r
+       and     ebp,0x00300000\r
+       and     ecx,0x01000000\r
+       or      ebp,0xf2800040\r
+       shr     ecx,24-10\r
+       or      ebp,ecx\r
+    .encode:\r
+       mov     dl,[operand_register2]\r
+       shr     dl,1\r
+       sbb     cl,cl\r
+       and     cl,0x10\r
+       or      dl,cl\r
+       mov     [operand_register2],dl\r
+       movzx   eax,al\r
+       shl     eax,24\r
+       or      ebp,eax                                 ;set Q\r
+       mov     ecx,ebp\r
+       shr     ecx,21\r
+       and     ecx,1                                   ;ecx=1 for size .32\r
+       mov     eax,3\r
+       mov     edx,8\r
+       shr     eax,cl                                  ;eax=maximum index value\r
+       shl     edx,cl                                  ;edx=maximum register + 1\r
+       test    ecx,ecx\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       mov     ebx,ERROR_element_value_out_of_range.0_3\r
+       cmovz   ecx,ebx\r
+       cmp     [immediate_value],eax\r
+       ja      ARM_post_process_simd_with_error\r
+       mov     ecx,ERROR_scalar_register_out_of_range.0_7\r
+       mov     ebx,ERROR_scalar_register_out_of_range.0_15\r
+       cmp     edx,8\r
+       cmovnz  ecx,ebx\r
+       cmp     [operand_register2],dl\r
+       jae     ARM_post_process_simd_with_error\r
+       shr     edx,4\r
+       mov     ecx,edx\r
+       mov     eax,[immediate_value]\r
+       shl     eax,cl\r
+       mov     edx,eax\r
+       and     edx,1\r
+       shl     edx,3\r
+       or      dl,[operand_register2]\r
+       shr     eax,2\r
+       rcl     edx,1\r
+       mov     [operand_register2],dl\r
+       xor     eax,eax\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_FLOAT_vd_vn_vmx_f32:\r
+       ;used by VMLA.F32, VMLS.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;0=dd,dn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\  ;1=dd,dn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;2=qd,qn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;3=qd,qn,dm[x]\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;4=sd,sn,sm\r
+       cmp     al,4\r
+       jae     .vfp_alias\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       shr     al,1\r
+       jnc     SIMD_INT_vd_vn_vm.encode\r
+       and     ebp,0x00200000\r
+       shr     ebp,21-10\r
+       or      ebp,0xf2a00140\r
+       jmp     SIMD_INT_vd_vn_vmx.encode\r
+    .vfp_alias:\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       mov     al,1\r
+       jmp     VFP_sd_sn_sm.v1xd_test\r
+\r
+SIMD_INT_vd_vn_vmx_long:\r
+       ;used by VMLAL.S16, VMLAL.S32, VMLAL.U16, VMLAL.U32, VMLSL.S16, VMLSL.S32, VMLSL.U16, VMLSL.U32,\r
+       ;        VMULL.S16, VMULL.S32, VMULL.U16, VMULL.U32, VQDMLAL.S16, VQDMLAL.S32, VQDMLSL.S16, VQDMLSL.S32,\r
+       ;        VQDMULL.S16, VQDMULL.S32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\  ;0=qd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpdx_reg>   ;1=qd,dn,dm[x]\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       shr     al,1\r
+       jnc     SIMD_INT_vd_vn_vm.encode\r
+       mov     ebp,[thumb32_instruction]\r
+       jmp     SIMD_INT_vd_vn_vmx.encode\r
+\r
+SIMD_INT_vd_imm_i8:\r
+       ;used by VMOV.I8, VMOV.I64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;0=qd,imm\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,imm\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       jmp     SIMD_INT_vd_imm.out_of_range\r
+\r
+SIMD_INT_vd_imm_i16:\r
+       ;used by VMOV.I16, VMVN.I16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;0=qd,imm\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,imm\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       xor     ebp,0x00000200                          ;cmode=a\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       xor     ebp,1 shl 5 + 0x00000200                ;cmode=8, invert op, VMVN<-->VMOV\r
+       mov     ecx,[immediate_value]\r
+       not     cx\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       xor     ebp,0x00000200                          ;cmode=a\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       jmp     SIMD_INT_vd_imm.out_of_range\r
+\r
+SIMD_INT_vd_imm_i32:\r
+       ;used by VMOV.I32, VMVN.I32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;0=qd,imm\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;1=dd,imm\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=2\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=4\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=6\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000600                          ;cmode=c\r
+       ror     ecx,8+8\r
+       xor     ecx,0xff000000\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000100                          ;cmode=d\r
+       ror     ecx,8\r
+       xor     ecx,0xff000000\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       xor     ebp,1 shl 5 + 0x00000d00                ;cmode=0, invert op, VMVN<-->VMOV\r
+       mov     ecx,[immediate_value]\r
+       not     ecx\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=2\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=4\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000200                          ;cmode=6\r
+       ror     ecx,8\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000600                          ;cmode=c\r
+       ror     ecx,8+8\r
+       xor     ecx,0xff000000\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       add     ebp,0x00000100                          ;cmode=d\r
+       ror     ecx,8\r
+       xor     ecx,0xff000000\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       jmp     SIMD_INT_vd_imm.out_of_range\r
+\r
+SIMD_FLOAT_dm_imm:\r
+       ;used by VMOV.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm_float>,\                ;0=dd,float\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;1=dd,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>                   ;2=dd,dm\r
+       cmp     al,2\r
+       jb      VFP_dm_imm.vesion_test\r
+       or      ebp,0x00000040                          ;FCPYD\r
+       jmp     VFP_dd_dm.encode\r
+\r
+SIMD_FLOAT_sm_imm:\r
+       ;used by VMOV.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_imm_float>,\                ;0=sd,float\r
+       <TMPL_vfps_reg,TMPL_imm>,\                      ;1=sd,imm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;2=sd,sm\r
+       <TMPL_simd_qreg,TMPL_imm_float>,\               ;3=qd,float\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qd,imm\r
+       <TMPL_vfpd_reg,TMPL_imm_float>,\                ;5=dd,float\r
+       <TMPL_vfpd_reg,TMPL_imm>                        ;6=dd,imm\r
+       cmp     al,2\r
+       jb      VFP_dm_imm.do\r
+       lea     ebp,[ebp+0x00000040]                    ;FCPYS\r
+       jz      VFP_sd_sm.v1xd_test\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       sub     al,3\r
+       shr     al,1\r
+       movzx   ebp,al\r
+       jc      .constant_converted\r
+       call    VFP_convert_single_to_quarter\r
+    .constant_converted:\r
+       mov     eax,ebp\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     ecx,[immediate_value]\r
+       test    ecx,not 0xff\r
+       jz      SIMD_INT_vd_imm.encode\r
+       jmp     SIMD_INT_vd_imm.out_of_range\r
+\r
+SIMD_INT_rd_dnx:\r
+       ;used by VMOV.S8, VMOV.S16, VMOV.U8, VMOV.U16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_vfpdx_reg>                  ;0=rd,dn[x]\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,ebp\r
+       shr     ecx,5\r
+       and     ecx,1\r
+       shl     edx,cl\r
+       test    ecx,ecx\r
+       mov     ecx,ERROR_element_value_out_of_range.0_3\r
+       mov     ebx,ERROR_element_value_out_of_range.0_7\r
+       cmovz   ecx,ebx\r
+       cmp     edx,7\r
+       ja      ARM_post_process_simd_with_error\r
+       mov     ecx,edx\r
+       and     edx,3\r
+       and     ecx,4\r
+       shl     edx,5\r
+       shl     ecx,21-2\r
+       or      ebp,edx\r
+       or      ebp,ecx\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     VFP_rd_dn.encode\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,13                                  ;SP?\r
+       jz      ERROR_r13_not_valid\r
+       jmp     VFP_rd_dn.encode\r
+\r
+SIMD_INT_ddx_rn:\r
+       ;used by VMOV.8, VMOV.16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpdx_reg,TMPL_base_reg>                  ;0=dd[x],rn\r
+       mov     ax,word[operand_registers+0]\r
+       xchg    ah,al\r
+       mov     word[operand_registers+0],ax\r
+       jmp     SIMD_INT_rd_dnx.do\r
+\r
+SIMD_INT_rdd_rdn:\r
+       ;used by VMOV.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpdx_reg,TMPL_base_reg>,\                ;0=dd[x],rn\r
+       <TMPL_base_reg,TMPL_vfpdx_reg>                  ;1=rd,dn[x]\r
+    .do:\r
+       movzx   eax,al\r
+       mov     cx,word[operand_registers+0]\r
+       mov     dx,cx\r
+       xchg    ch,cl\r
+       shl     eax,20\r
+       cmovz   ecx,edx\r
+       mov     word[operand_registers+0],cx\r
+       or      ebp,eax\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_element_value_out_of_range.0_1\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,21\r
+       or      ebp,edx\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     VFP_dn_rd.test_version\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,13                                  ;SP?\r
+       jz      ERROR_r13_not_valid\r
+       jmp     VFP_dn_rd.test_version\r
+\r
+       align 4\r
+SIMD_INT_MOV_table:\r
+       dd      0x0e000a10,VFP_sn_rd.do,0               ;0=FMSR\r
+       dd      0x0c400a10,SIMD_INT_MOV.msrr,0          ;1=FMSRR\r
+       dd      0x0e000b10,SIMD_INT_rdd_rdn.do,0        ;2=VMOV.32\r
+       dd      0xf2200110,SIMD_INT_MOV.vd_vm,0         ;3=dd,dn\r
+       dd      0x0c400b10,VFP_dm_rd_rn.test_version,0  ;4=FMDRR\r
+       dd      0x0e000b10,SIMD_INT_rdd_rdn.do,1        ;5=VMOV.32\r
+       dd      0x0e100a10,VFP_rd_dn.do,0               ;6=FMRS\r
+       dd      0x0c500a10,SIMD_INT_MOV.mrrs,0          ;7=FMRRS\r
+       dd      0x0c500b10,VFP_rd_rn_dm.test_version,0  ;8=FMRRD\r
+       dd      0xf2200150,SIMD_INT_MOV.vd_vm,0         ;9=qd,qn\r
+\r
+SIMD_INT_MOV:\r
+       ;used by VMOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_base_reg>,\                                 ;0=sn,rd\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_base_reg,TMPL_base_reg>,\     ;1=sd1,sd2,rn1,rn2\r
+       <TMPL_vfpdx_reg,TMPL_base_reg>,\                                ;2=dd[x],rn\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                                 ;3=dd,dn\r
+       <TMPL_vfpd_reg,TMPL_base_reg,TMPL_base_reg>,\                   ;4=dd,rn1,rn2\r
+       <TMPL_base_reg,TMPL_vfpdx_reg>,\                                ;5=rd,dn[x]\r
+       <TMPL_base_reg,TMPL_vfps_reg>,\                                 ;6=rd,sn\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_vfps_reg,TMPL_vfps_reg>,\     ;7=rd1,rd2,sn1,sn2\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_vfpd_reg>,\                   ;8=rd1,rd2,dn\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>                                 ;9=qd,qn\r
+       movzx   eax,al\r
+       imul    eax,12\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[eax+SIMD_INT_MOV_table+0]\r
+       mov     ecx,[eax+SIMD_INT_MOV_table+4]\r
+       mov     eax,[eax+SIMD_INT_MOV_table+8]\r
+       jmp     vcx\r
+    .msrr:\r
+       xor     edx,edx\r
+       movzx   ecx,[operand_register0]\r
+       bts     edx,ecx\r
+       movzx   ecx,[operand_register1]\r
+       bts     edx,ecx\r
+       mov     [reg_list_bitmap],edx\r
+       mov     ecx,[operand_registers]\r
+       shr     ecx,16\r
+       mov     [operand_registers],ecx\r
+       jmp     VFP_rd_rn_sm.do\r
+    .mrrs:\r
+       xor     edx,edx\r
+       movzx   ecx,[operand_register2]\r
+       bts     edx,ecx\r
+       movzx   ecx,[operand_register3]\r
+       bts     edx,ecx\r
+       mov     [reg_list_bitmap],edx\r
+       jmp     VFP_rd_rn_sm.do\r
+    .vd_vm:\r
+       mov     cl,[operand_register1]\r
+       mov     [operand_register2],cl\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+\r
+SIMD_INT_qd_dm:\r
+       ;used by VMOVL.S8, VMOVL.S16, VMOVL.S32, VMOVL.U8, VMOVL.U16, VMOVL.U32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg>                  ;0=qd,dm\r
+       jmp     SIMD_INT_vd_vm.int_test\r
+\r
+SIMD_INT_dd_qm:\r
+       ;used by VMOVN.I8, VMOVN.I16, VMOVN.I32, VQMOVN.S16, VQMOVN.S32, VQMOVN.S64, VQMOVN.U16,\r
+       ;        VQMOVN.U32, VQMOVN.U64, VQMOVUN.S16, VQMOVUN.S32, VQMOVUN.S64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_simd_qreg>                  ;0=dd,qm\r
+       jmp     SIMD_INT_vd_vm.int_test\r
+\r
+SIMD_INT_vd_vn_vmx_alt:\r
+       ;used by VMUL.I16, VMUL.I32, VQDMULH.S16, VQDMULH.S32, VQRDMULH.S16, VQRDMULH.S32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\                ;0=ddn,dm[x]\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\  ;1=dd,dn,dm[x]\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_vfpdx_reg>,\               ;4=qdn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;5=qd,qn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_INT\r
+       jz      ERROR_requires_copro_capability_simd_int\r
+    .do:\r
+       shr     al,1\r
+       jc      .registers_okay\r
+       mov     cx,word[operand_registers+0]\r
+       mov     word[operand_registers+1],cx\r
+    .registers_okay:\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm.encode\r
+       mov     ebp,[thumb32_instruction]\r
+       jmp     SIMD_INT_vd_vn_vmx.encode\r
+\r
+SIMD_FLOAT_vd_vn_vmx_alt_f32:\r
+       ;used by VMUL.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpdx_reg>,\                ;0=ddn,dm[x]\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpdx_reg>,\  ;1=dd,dn,dm[x]\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;2=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_vfpdx_reg>,\               ;4=qdn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_vfpdx_reg>,\;5=qd,qn,dm[x]\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;6=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;7=qd,qn,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;8=sdn,sm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;9=sd,sn,sm\r
+       cmp     al,8\r
+       jae     .vfp_alias\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       mov     [thumb32_instruction],0xf2a00940        ;scalar\r
+       jmp     SIMD_INT_vd_vn_vmx_alt.do\r
+    .vfp_alias:\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       sub     al,8\r
+       jmp     VFP_sd_sn_sm.v1xd_test\r
+\r
+SIMD_INT_dd_dn_dm_alt:\r
+       ;used by VPADD.I8, VPADD.I16, VPADD.I32, VPMAX.S8, VPMAX.S16, VPMAX.S32, VPMAX.U8, VPMAX.U16, VPMAX.U32\r
+       ;        VPMIN.S8, VPMIN.S16, VPMIN.S32, VPMIN.U8, VPMIN.U16, VPMIN.U32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;1=dd,dn,dm\r
+       jmp     SIMD_INT_vd_vn_vm_alt.encode\r
+\r
+SIMD_FLOAT_dd_dn_dm_alt:\r
+       ;used by VPADD.F32, VPMAX.F32, VPMIN.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;1=dd,dn,dm\r
+       jmp     SIMD_FLOAT_vd_vn_vm_alt.float_test\r
+\r
+SIMD_INT_list:\r
+       ;used by VPOP, VPUSH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfp_reg_list_s>,\                         ;0={s..}\r
+       <TMPL_vfp_reg_list_d>                           ;1={d..}\r
+       cmp     al,0\r
+       mov     [operand_register0],13                  ;SP\r
+       mov     al,1                                    ;rn!\r
+       jz      VFP_rn_list_s.do\r
+       or      ebp,0x00000100\r
+       jmp     VFP_rn_list_d.do\r
+\r
+SIMD_INT_list.32:\r
+       ;used by VPOP, VPUSH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfp_reg_list_s>                           ;0={s..}\r
+       mov     [operand_register0],13                  ;SP\r
+       mov     al,1                                    ;rn!\r
+       jmp     VFP_rn_list_s.do\r
+\r
+SIMD_INT_list.64:\r
+       ;used by VPOP, VPUSH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfp_reg_list_d>                           ;0={d..}\r
+       mov     [operand_register0],13                  ;SP\r
+       mov     al,1                                    ;rn!\r
+       jmp     VFP_rn_list_d.do\r
+\r
+SIMD_INT_dd_qm_imm:\r
+       ;used by VQRSHRN.S16, VQRSHRN.S32, VQRSHRN.S64, VQRSHRN.U16, VQRSHRN.U32, VQRSHRN.U64,\r
+       ;        VQRSHRUN.S16, VQRSHRUN.S32, VQRSHRUN.S64, VQSHRN.S16, VQSHRN.S32, VQSHRN.S64,\r
+       ;        VQSHRN.U16, VQSHRN.U32, VQSHRN.U64, VQSHRUN.S16, VQSHRUN.S32, VQSHRUN.S64,\r
+       ;        VRSHRUN.I16, VRSHRUN.I32, VRSHRUN.I64, VSHRN.I16, VSHRN.I32, VSHRN.I64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_simd_qreg,TMPL_imm>         ;0=dd,qm,imm\r
+    .encode:\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       shr     ecx,16\r
+       shr     edx,7-6\r
+       and     ecx,0x3f\r
+       and     edx,0x40\r
+       or      ecx,edx\r
+       mov     edx,ecx\r
+       sub     ecx,[immediate_value]\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       shr     ecx,16\r
+       dec     edx\r
+       not     edx\r
+       test    ecx,edx\r
+       jz      SIMD_INT_vd_vm.int_test\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_8\r
+       mov     eax,ERROR_shift_value_out_of_range.1_16\r
+       test    edx,1 shl 3\r
+       cmovz   ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.1_32\r
+       test    edx,1 shl 4\r
+       cmovz   ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.1_64\r
+       test    edx,1 shl 5\r
+       cmovz   ecx,eax\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_INT_vd_vn_vm_imm_alt:\r
+       ;used by VQSHL.S8, VQSHL.S16, VQSHL.S32, VQSHL.S64, VQSHL.U8, VQSHL.U16, VQSHL.U32, VQSHL.U64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;1=ddn,dm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;2=dd,dm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;3=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;4=qdm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\               ;5=qdn,qm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>,\      ;6=qd,qm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;7=qd,qn,qm\r
+       shr     al,1\r
+       jc      SIMD_INT_vd_vn_vm_alt.encode\r
+       mov     ebp,[thumb32_instruction]\r
+    .encode:\r
+       shr     al,1\r
+       jc      .registers_okay\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+    .registers_okay:\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       shr     ecx,16\r
+       shr     edx,7-6\r
+       and     ecx,0x3f\r
+       and     edx,0x40\r
+       or      edx,ecx\r
+       mov     ecx,[immediate_value]\r
+       shl     ecx,16\r
+       or      ebp,ecx\r
+       cmp     edx,[immediate_value]\r
+       ja      SIMD_INT_vd_vm.int_test\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_7\r
+       mov     eax,ERROR_shift_value_out_of_range.0_15\r
+       test    edx,1 shl 4\r
+       cmovnz  ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.0_31\r
+       test    edx,1 shl 5\r
+       cmovnz  ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.0_63\r
+       test    edx,1 shl 6\r
+       cmovnz  ecx,eax\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_INT_vd_vm_imm_alt:\r
+       ;used by VQSHLU.S8, VQSHLU.S16, VQSHLU.S32, VQSHLU.S64,\r
+       ;        VSHL.I8, VSHL.I16, VSHL.I32, VSHL.I64, VSLI.8, VSLI.16, VSLI.32, VSLI.64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,imm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;2=qdm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>        ;3=qd,qm,imm\r
+       jmp     SIMD_INT_vd_vn_vm_imm_alt.encode\r
+\r
+SIMD_INT_vd_vm_imm_alt_neg:\r
+       ;used by VRSHR.S8, VRSHR.S16, VRSHR.S32, VRSHR.S64, VRSHR.U8, VRSHR.U16, VRSHR.U32, VRSHR.U64,\r
+       ;        VRSRA.S8, VRSRA.S16, VRSRA.S32, VRSRA.S64, VRSRA.U8, VRSRA.U16, VRSRA.U32, VRSRA.U64,\r
+       ;        VSHR.S8, VSHR.S16, VSHR.S32, VSHR.S64, VSHR.U8, VSHR.U16, VSHR.U32, VSHR.U64,\r
+       ;        VSRA.S8, VSRA.S16, VSRA.S32, VSRA.S64, VSRA.U8, VSRA.U16, VSRA.U32, VSRA.U64,\r
+       ;        VSRI.8, VSRI.16, VSRI.32, VSRI.64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;0=ddm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>,\        ;1=dd,dm,imm\r
+       <TMPL_simd_qreg,TMPL_imm>,\                     ;2=qdm,imm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_imm>        ;3=qd,qm,imm\r
+       shr     al,1\r
+       jc      .registers_okay\r
+       mov     cl,[operand_register0]\r
+       mov     [operand_register1],cl\r
+    .registers_okay:\r
+       jmp     SIMD_INT_dd_qm_imm.encode\r
+\r
+SIMD_FLOAT_vd_vm:\r
+       ;used by VRECPE.F32, VRSQRTE.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;0=dd,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>                 ;1=qd,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_FLOAT\r
+       jz      ERROR_requires_copro_capability_simd_float\r
+       jmp     SIMD_INT_vd_vm.encode\r
+\r
+SIMD_INT_qd_dm_imm:\r
+       ;used by VSHLL.S8, VSHLL.S16, VSHLL.S32, VSHLL.U8, VSHLL.U16, VSHLL.U32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_imm>         ;0=qd,qm,imm\r
+       mov     ecx,[immediate_value]\r
+       mov     edx,ebp\r
+       and     edx,0x3f shl 16\r
+       rol     ecx,16\r
+       or      ebp,ecx\r
+       cmp     ecx,edx                                 ;imm=size?\r
+       jz      .imm_eq_size\r
+       dec     edx\r
+       and     edx,0x3f shl 16\r
+       not     edx\r
+       test    ecx,edx\r
+       jz      SIMD_INT_vd_vm.int_test\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_8\r
+       mov     eax,ERROR_shift_value_out_of_range.0_16\r
+       test    edx,1 shl (3+16)\r
+       cmovz   ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.0_32\r
+       test    edx,1 shl (4+16)\r
+       cmovz   ecx,eax\r
+       jmp     ARM_post_process_simd_with_error\r
+    .imm_eq_size:\r
+       mov     ebp,[thumb32_instruction]\r
+       jmp     SIMD_INT_vd_vm.int_test\r
+\r
+SIMD_INT_qd_dm_imm_I:\r
+       ;used by VSHLL.I8, VSHLL.I16, VSHLL.I32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_imm>         ;0=qd,qm,imm\r
+       mov     ecx,ebp\r
+       shr     ecx,18\r
+       and     ecx,3\r
+       mov     edx,8\r
+       shl     edx,cl\r
+       mov     ecx,[immediate_value]\r
+       cmp     ecx,edx                                 ;imm=size?\r
+       jz      SIMD_INT_vd_vm.int_test\r
+       mov     ecx,ERROR_shift_value_out_of_range.8\r
+       mov     eax,ERROR_shift_value_out_of_range.16\r
+       cmp     edx,16\r
+       cmovz   ecx,eax\r
+       mov     eax,ERROR_shift_value_out_of_range.32\r
+       cmp     edx,32\r
+       cmovz   ecx,eax\r
+       jmp     ARM_post_process_simd_with_error\r
+\r
+SIMD_dn_list_dm:\r
+       ;used by VTBL.8, VTBX.8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfp_reg_list_d,TMPL_comma,TMPL_vfpd_reg>    ;0=dd,{dn,..},dm\r
+       mov     edx,[reg_list_bitmap]\r
+       bsf     eax,edx\r
+       bsr     ecx,edx\r
+    ;check for a contiguous set\r
+       xor     ecx,31\r
+       shl     edx,cl\r
+       add     ecx,eax\r
+       sar     edx,cl\r
+       inc     edx\r
+       mov     ecx,ERROR_non_contiguous_set\r
+       jnz     ARM_post_process_simd_with_error\r
+       mov     ecx,[reg_list_bitmap]\r
+       bsf     eax,ecx                                 ;eax=start register\r
+       bsr     edx,ecx\r
+       sub     edx,eax                                 ;edx=register count - 1\r
+       cmp     edx,3\r
+       mov     ecx,ERROR_register_list_invalid         ;too many registers\r
+       ja      ARM_post_process_simd_with_error\r
+       shl     edx,8\r
+       or      ebp,edx\r
+       mov     cl,[operand_register1]                  ;dm\r
+       mov     [operand_register2],cl                  ;dm\r
+       add     eax,eax\r
+       mov     ah,al\r
+       shr     ah,5\r
+       and     ax,0x011e\r
+       or      al,ah\r
+       mov     [operand_register1],al                  ;dn\r
+       xor     eax,eax\r
+       jmp     SIMD_INT_vd_vn_vm.int_test\r
+\r
+SIMD_FLOAT_dd_sm_CVT:\r
+       ;used by VCVT.F64.S32, VCVT.F64.U32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfps_reg>,\                 ;0=dd,sm\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;1=ddm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>          ;2=dd,dm,imm\r
+       sub     al,1\r
+       jc      VFP_dd_sm.do\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       jmp     VFP_dd_dd_imm.test_version\r
+\r
+SIMD_FLOAT_sd_dm_CVT:\r
+       ;used by VCVT.S32.F64, VCVT.U32.F64,\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfpd_reg>,\                 ;0=sd,dm\r
+       <TMPL_vfpd_reg,TMPL_imm>,\                      ;1=ddm,imm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_imm>          ;2=dd,dm,imm\r
+       sub     al,1\r
+       jc      VFP_sd_dm.do\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       jmp     VFP_dd_dd_imm.test_version\r
+\r
+VFP_FLOAT_dd_dn_dm:\r
+       ;used by FMACD, FNMACD, FMSCD, FNMSCD, VNMLA.F64, VNMLS.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;0=dd,dn,dm\r
+       mov     al,1\r
+       jmp     VFP_dd_dn_dm.begin\r
+\r
+VFP_FLOAT_sd_sn_sm:\r
+       ;used by FMACS, FNMACS, FMSCS, FNMSCS, VNMLA.F32, VNMLS.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;0=sd,sn,sm\r
+       mov     al,1\r
+       jmp     VFP_sd_sn_sm.v1xd_test\r
+\r
+;VFPv4 and SIMDv2\r
+\r
+SIMD_FLOAT_vd_vn_vm:\r
+       ;used by VFMA.F32, VFMS.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;0=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;1=qd,qn,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;2=sd,sn,sm\r
+       cmp     al,2\r
+       jb      .simdv2_test\r
+    .vfpv4_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_V4\r
+       jz      ERROR_requires_copro_capability_vfp_v4\r
+       movzx   ebp,[instruction_condition]\r
+       and     ebp,0xf0\r
+       shl     ebp,28-4\r
+       or      ebp,[thumb32_instruction]\r
+       jmp     VFP_sd_sn_sm.registers_shifted\r
+    .simdv2_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V2\r
+       jz      ERROR_requires_copro_capability_simd_v2\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_FLOAT_dd_dn_dm:\r
+       ;used by VFMA.F64, VFMS.F64, VFNMA.F64, VFNMS.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;0=dd,dn,dm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_VFP_D32\r
+       jnz     SIMD_FLOAT_vd_vn_vm.vfpv4_test\r
+       mov     edx,[operand_registers]                 ;fd,fn,fm\r
+       test    edx,0x010101\r
+       jnz     ERROR_requires_copro_capability_vfp_d32\r
+       mov     al,1\r
+       jmp     SIMD_FLOAT_vd_vn_vm.vfpv4_test\r
+\r
+SIMD_FLOAT_sd_sn_sm:\r
+       ;used by VFNMA.F32, VFNMS.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;0=sd,sn,sm\r
+       mov     al,1\r
+       jmp     SIMD_FLOAT_vd_vn_vm.vfpv4_test\r
+\r
+;v7VE\r
+\r
+ARM_eret:\r
+       ;used by ERET\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE\r
+       jz      ERROR_requires_cpu_capability_arm_ve\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_eret\r
+       jmp     ARM_store_instruction\r
+    .THUMB_eret:\r
+       or      [thumb_flags_16],THUMB_FLAG_ONLY_LAST_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_ONLY_LAST_IT\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_immediate16_ve:\r
+       ;used by HVC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_VE\r
+       jz      ERROR_requires_cpu_capability_arm_ve\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x0000ffff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0xf\r
+       and     ecx,0xfff0\r
+       shl     ecx,4\r
+       or      eax,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0xffff\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB:\r
+       or      [thumb_flags_16],THUMB_FLAG_NOT_INSIDE_IT\r
+       or      [thumb_flags_32],THUMB_FLAG_NOT_INSIDE_IT\r
+       mov     [thumb32_error],ERROR_immediate_offset_out_of_range.0_0xffff\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xffff\r
+       ja      THUMB_post_process\r
+       mov     ecx,eax\r
+       and     eax,0xfff\r
+       and     ecx,0xf000\r
+       shl     ecx,4\r
+       or      eax,ecx\r
+       or      [thumb32_instruction],eax\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+;v8\r
+\r
+ARM_immediate16_v8:\r
+       ;used by HLT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>                                      ;0=imm\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_immediate6\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x0000ffff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0xf\r
+       and     ecx,0xfff0\r
+       shl     ecx,4\r
+       or      eax,ecx\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0_0xffff\r
+       jmp     ARM_store_instruction_with_error\r
+    .THUMB_immediate6:\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       mov     [thumb16_error],ERROR_immediate_offset_out_of_range.0_0x3f\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x3f\r
+       ja      THUMB_post_process\r
+       or      ax,0xba80\r
+       mov     [thumb16_instruction],ax\r
+       mov     [thumb16_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rt_q_rn_p:\r
+       ;used by STL, STLB, STLH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>              ;0=reg,[reg]\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rt_q_rn_p\r
+       movzx   eax,[operand_register0]                 ;rt\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rt_q_rn_p:\r
+       mov     cl,0x03\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rt\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rt_q_rn_p_STLEX:\r
+       ;used by STLEX, STLEXB, STLEXH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\              ;0=rd,rm,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_imm,TMPL_bracket_right>,\     ;1=rd,rm,[rn,imm]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>              ;2=rd,rm,[exp]\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     ARM_store_instruction_with_error\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rt_q_rn_p_STLEX\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rt\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.second\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rn\r
+       cmp     eax,0xf\r
+       jz      ERROR_r15_not_valid.third\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       mov     al,[operand_register0]                  ;rd\r
+       mov     ah,[operand_register1]                  ;rt\r
+       mov     cl,[operand_register2]                  ;rn\r
+       cmp     al,cl\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+       cmp     al,ah\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rt_q_rn_p_STLEX:\r
+       mov     ebp,[thumb32_instruction]\r
+       mov     cl,0x07\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     [thumb32_error],ERROR_dest_cannot_be_source_or_memory_address\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       movzx   ecx,[operand_register1]                 ;rt\r
+       movzx   edx,[operand_register2]                 ;rn\r
+       cmp     eax,ecx\r
+       jz      THUMB_post_process\r
+       cmp     eax,edx\r
+       jz      THUMB_post_process\r
+       or      ebp,eax\r
+       shl     ecx,12\r
+       or      ebp,ecx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+ARM_rd_rt_rt2_q_rn_p_STLEXD:\r
+       ;used by STLEXD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>,\              ;0=rd,rt,[rn]\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg,TMPL_bracket_left,TMPL_base_reg,TMPL_bracket_right>  ;1=rd,rt,rt2,[rn]\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      ARM_rd_rt_rt2_q_rn_p.THUMB_adjust_three_to_four\r
+       mov     ecx,[operand_registers]                 ;rd,rt,rt2,rn\r
+       cmp     al,1\r
+       jnz     .check_rt\r
+       mov     eax,ecx\r
+       shr     eax,8\r
+       sub     ah,1\r
+       cmp     ah,al\r
+       jnz     ERROR_source_registers_must_be_consecutive\r
+       mov     eax,ecx\r
+       shr     ecx,8\r
+       mov     ch,cl\r
+       mov     cl,al\r
+    .check_rt:\r
+       test    ch,1\r
+       jnz     ERROR_source_register_must_be_even\r
+       cmp     ch,14\r
+       jz      ERROR_r14_not_valid.second\r
+       mov     [operand_registers],ecx                 ;rd,rt,rn\r
+       inc     ch\r
+       cmp     ch,cl\r
+       jz      ERROR_source_and_dest_must_differ\r
+       jmp     ARM_rd_rm_q_rn_p_STREX.version_okay\r
+\r
+THUMB_v8:\r
+       ;used by DCPS1, DCPS2, DCPS3\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>                                      ;0=empty\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ERROR_instruction_not_32bit\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_V8\r
+       jz      ERROR_requires_cpu_capability_arm_v8\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+SIMD_sd_sm:\r
+       ;used by VCVTM.S32.F32, VCVTM.U32.F32, VCVTN.S32.F32, VCVTN.U32.F32, VCVTP.S32.F32, VCVTP.U32.F32, VCVTA.S32.F32, VCVTA.U32.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>,\                 ;0=sd,sm\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\                 ;1=dd,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>                 ;2=qd,qm\r
+    .do:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V8\r
+       jz      ERROR_requires_copro_capability_simd_v8\r
+       cmp     al,0\r
+       jz      .encode\r
+       mov     ebp,[thumb32_instruction]               ;get the SIMD encoding\r
+       cmp     al,2\r
+       jnz     .encode\r
+       or      ebp,1 shl 6                             ;set the Q bit\r
+    .encode:\r
+       movzx   eax,[operand_register0]                 ;fd\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     eax,12\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register1]                 ;fm\r
+       xor     ecx,ecx\r
+       shr     eax,1\r
+       setc    cl\r
+       shl     ecx,5\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       xor     ecx,ecx                                 ;clear the error code\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     ARM_store_instruction\r
+       cmp     ebp,0xf0000000\r
+       jb      ARM_post_process_copro.thumb\r
+       jmp     ARM_post_process_simd\r
+\r
+SIMD_sd_dm:\r
+       ;used by VCVTM.S32.F64, VCVTM.U32.F64, VCVTN.S32.F64, VCVTN.U32.F64, VCVTP.S32.F64, VCVTP.U32.F64, VCVTA.S32.F64, VCVTA.U32.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfpd_reg>                   ;0=sd,dm\r
+       jmp     SIMD_sd_sm.do\r
+\r
+VFP_sd_dm_HP:\r
+       ;used by VCVTB.F16.F64, VCVTT.F16.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfpd_reg>                   ;0=sd,dm\r
+       jmp     SIMD_sd_sm.do\r
+\r
+VFP_dd_sm_HP:\r
+       ;used by VCVTB.F64.F16, VCVTT.F64.F16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfps_reg>                   ;0=dd,sm\r
+       jmp     SIMD_sd_sm.do\r
+\r
+SIMD_FLOAT_vd_vn_vm_v8:\r
+       ;used by VMAXNM.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>,\   ;0=dd,dn,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>,\;1=qd,qn,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;2=sd,sn,sm\r
+    .v8_test:\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_V8\r
+       jz      ERROR_requires_copro_capability_simd_v8\r
+       cmp     al,2\r
+       jz      .encode\r
+       mov     ebp,[thumb32_instruction]               ;get the SIMD encoding\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jnz     .encode\r
+       ;in THUMB mode no v8 SIMD instructions can be conditional\r
+       mov     ah,[instruction_condition]\r
+       and     ah,0xf0\r
+       cmp     ah,0xe0\r
+       jb      ERROR_instruction_not_conditional\r
+    .encode:\r
+       and     al,1                                    ;extract the Q bit\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_FLOAT_sd_sn_sm_v8:\r
+       ;used by VSELEQ.F32, VSELVS.F32, VSELGE.F32, VSELGT.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg,TMPL_vfps_reg>     ;0=sd,sn,sm\r
+       jmp     SIMD_FLOAT_vd_vn_vm_v8.v8_test\r
+\r
+SIMD_FLOAT_dd_dn_dm_v8:\r
+       ;used by VMAXNM.F64, VSELEQ.F64, VSELVS.F64, VSELGE.F64, VSELGT.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg,TMPL_vfpd_reg>     ;0=dd,dn,dm\r
+       jmp     SIMD_FLOAT_vd_vn_vm_v8.v8_test\r
+\r
+SIMD_FLOAT_vd_vn_v8:\r
+       ;used by VRINTM.F32.F32, VRINTN.F32.F32, VRINTP.F32.F32, VRINTA.F32.F32, VRINTX.F32.F32, VRINTZ.F32.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>,\         ;0=dd,dm\r
+       <TMPL_simd_qreg,TMPL_simd_qreg>,\       ;1=qd,qm\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>           ;2=sd,sm\r
+    .do:\r
+       mov     cl,[operand_register1]\r
+       mov     [operand_register1],0\r
+       mov     [operand_register2],cl\r
+       jmp     SIMD_FLOAT_vd_vn_vm_v8.v8_test\r
+\r
+SIMD_FLOAT_sd_sn_v8:\r
+       ;used by VRINTR.F32.F32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfps_reg,TMPL_vfps_reg>           ;0=sd,sm\r
+       mov     al,2\r
+       jmp     SIMD_FLOAT_vd_vn_v8.do\r
+\r
+SIMD_FLOAT_dd_dn_v8:\r
+       ;used by VRINTM.F64.F64, VRINTN.F64.F64, VRINTP.F64.F64, VRINTA.F64.F64, VRINTX.F64.F64, VRINTR.F64.F64, VRINTZ.F64.F64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vfpd_reg,TMPL_vfpd_reg>           ;0=dd,dm\r
+       mov     al,2\r
+       jmp     SIMD_FLOAT_vd_vn_v8.do\r
+\r
+ARM_rd_rn_rm_crc:\r
+       ;used by CRC32B\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_base_reg,TMPL_base_reg,TMPL_base_reg>     ;0=reg,reg,reg\r
+       test    [cpu_capability_flags],1 shl CPU32_CAPABILITY_CRC\r
+       jz      ERROR_requires_cpu_capability_crc\r
+       test    [code_type],CPU_ACTIVITY_ARM\r
+       jz      .THUMB_rd_rn_rm\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.first\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.second\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       cmp     eax,15\r
+       jz      ERROR_r15_not_valid.third\r
+       or      ebp,eax\r
+       and     ebp,not 0x10000000                      ;force to 0xE... opcode\r
+       jmp     ARM_store_instruction\r
+    .THUMB_rd_rn_rm:\r
+       mov     cl,0x07\r
+       call    THUMB2_check_bad_regs\r
+       jc      THUMB_post_process\r
+       mov     ebp,[thumb32_instruction]\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       or      ebp,eax\r
+       mov     [thumb32_instruction],ebp\r
+       mov     [thumb32_error],0\r
+       jmp     THUMB_post_process\r
+\r
+SIMD_CRYPTO_qd_qm:\r
+       ;used by AESD.8, AESE.8, AESIMC.8, AESMC.8, SHA1H.32, SHA1SU1.32, SHA256SU0.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_simd_qreg> ;0=qd,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO\r
+       jz      ERROR_requires_copro_capability_simd_crypto\r
+       mov     cl,[operand_register1]\r
+       mov     [operand_register1],0\r
+       mov     [operand_register2],cl\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_CRYPTO_qd_qn_qm:\r
+       ;used by SHA1C.32, SHA1P.32, SHA1M.32, SHA1SU0.32, SHA256H.32, SHA256H2.32, SHA256SU1.32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_simd_qreg,TMPL_simd_qreg>  ;0=qd,qn,qm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO\r
+       jz      ERROR_requires_copro_capability_simd_crypto\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+SIMD_INT_qd_dn_dm:\r
+       ;used by VMULL.P64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_simd_qreg,TMPL_vfpd_reg,TMPL_vfpd_reg>    ;0=qd,dn,dm\r
+       test    [copro_capability_flags],1 shl COPRO_CAPABILITY_SIMD_CRYPTO\r
+       jz      ERROR_requires_copro_capability_simd_crypto\r
+       jmp     SIMD_INT_vd_vn_vm.encode\r
+\r
+;v8 64 bit\r
+\r
+ARM64_encode_bitmask:\r
+       ;create N:immr:imms from immediate_value_high:immediate_value\r
+       ;return carry = true if failed\r
+       ;return eax = N:immr:imms if successful\r
+       ;first stage: find the smallest unit that can be replicated\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ebx,64          ;ebx = current replicate bit size\r
+       cmp     edx,eax\r
+       jnz     .find_rotation\r
+       shr     ebx,1           ;32\r
+       ror     edx,16\r
+       cmp     dx,ax\r
+       jnz     .find_rotation\r
+       shr     ebx,1           ;16\r
+       cmp     ah,al\r
+       jnz     .find_rotation\r
+       shr     ebx,1           ;8\r
+       ror     ah,4\r
+       cmp     ah,al\r
+       jnz     .find_rotation\r
+       shr     ebx,1           ;4\r
+       ror     ah,2\r
+       cmp     ah,al\r
+       jnz     .find_rotation\r
+       shr     ebx,1           ;2\r
+       cmp     al,-1           ;all ones?\r
+       jz      .cannot_encode\r
+    .find_rotation:\r
+       push    ebx\r
+       ;second stage: find a rotation that puts all the bits at the lower end\r
+       cmp     bl,64\r
+       jz      .mask_done\r
+       mov     ecx,ebx\r
+       neg     ecx\r
+       rol     eax,cl\r
+       cdq\r
+       sar     eax,cl\r
+    .mask_done:\r
+       ;count leading 1's\r
+       not     edx\r
+       not     eax\r
+       bsr     ecx,edx\r
+       lea     ecx,[ecx+32]\r
+       jnz     .leading_ones_count_okay\r
+       bsr     ecx,eax\r
+    .leading_ones_count_okay:\r
+       not     edx\r
+       not     eax\r
+       not     ecx\r
+       and     ecx,0x3f\r
+       jnz     .rotate_and_check\r
+       ;count trailing 0's\r
+       bsf     ecx,eax\r
+       jnz     .trailing_zeros_count_okay\r
+       bsf     ecx,edx\r
+       jz      .zero_value\r
+       add     ecx,32\r
+    .trailing_zeros_count_okay:\r
+       ;invert the count\r
+       sub     ecx,64\r
+       neg     ecx\r
+       and     ecx,0x3f\r
+    .rotate_and_check:\r
+       push    ecx\r
+       ;rotate left by ecx bits\r
+       cmp     ecx,32\r
+       jb      .rotate_small\r
+       xchg    edx,eax\r
+    .rotate_small:\r
+       mov     ebx,eax\r
+       shld    eax,edx,cl\r
+       shld    edx,ebx,cl\r
+       ;check that it is one less than a power of 2\r
+       mov     ecx,eax\r
+       mov     ebx,edx\r
+       add     ecx,1\r
+       adc     ebx,0\r
+       and     eax,ecx\r
+       and     edx,ebx\r
+       or      eax,edx\r
+       jnz     .fail\r
+       ;get the bit size\r
+       bsf     eax,ecx\r
+       jnz     .trailing_zeros_count_okay2\r
+       bsf     eax,ebx\r
+       add     eax,32\r
+    .trailing_zeros_count_okay2:\r
+       dec     eax             ;get length (imms)\r
+       pop     ecx             ;get rotation (immr)\r
+       pop     ebx             ;get replicate bit size\r
+       lea     edx,[ebx-1]\r
+       and     eax,edx\r
+       and     ecx,edx\r
+       not     edx\r
+       shl     edx,1\r
+       or      eax,edx\r
+       and     eax,0x3f\r
+       shl     ecx,6\r
+       or      eax,ecx\r
+       and     ebx,0x40\r
+       shl     ebx,12-6\r
+       or      eax,ebx\r
+       ;success\r
+       clc\r
+       ret\r
+    .fail:\r
+       pop     eax             ;dummy to restore stack\r
+    .zero_value:\r
+       pop     eax             ;dummy to restore stack\r
+    .cannot_encode:\r
+       stc\r
+       ret\r
+\r
+ARM64_dz_nz_mz:\r
+       ;used by ADC, ADCS, MNEG, SBC, SBCS, SDIV, UDIV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>    ;1=xd,xn,xm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+    .do:\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+    .encode_rd:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_wz_wz_wz:\r
+       ;used by CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, CRC32CW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>       ;0=wd,wn,wm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_CRC shr 32\r
+       jz      ERROR_requires_cpu64_capability_crc\r
+       jmp     ARM64_dz_nz_mz.do\r
+\r
+ARM64_wz_wz_xz:\r
+       ;used by CRC32X, CRC32CX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_dword_z_reg>      ;0=wd,wn,xm\r
+       jmp     ARM64_wz_wz_wz.encode\r
+\r
+ARM64_xz_xz_xz:\r
+       ;used by SMULH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>    ;0=xd,xn,xm\r
+       jmp     ARM64_dz_nz_mz.encode\r
+\r
+ARM64_dz_nz_mz_az:\r
+       ;used by MADD, MSUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn,wm,wa\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>   ;1=xd,xn,xm,xa\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+    .encode_rd:\r
+       movzx   eax,[operand_register0]                 ;rd\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;rn\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;rm\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;ra\r
+       shl     eax,10\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_dx_nw_mw_ax:\r
+       ;used by SMADDL, SMSUBL, UMADDL, UMSUBL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_dword_z_reg>     ;0=xd,wn,wm,xa\r
+       jmp     ARM64_dz_nz_mz_az.encode\r
+\r
+ARM64_dx_nw_mw:\r
+       ;used by SMNEGL, UMNEGL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>      ;0=xd,wn,wm\r
+       jmp     ARM64_dz_nz_mz_az.encode\r
+\r
+ARM64_dz_nw:\r
+       ;used by SXTB, SXTH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn\r
+       <TMPL_dword_z_reg,TMPL_word_z_reg>      ;1=xd,wn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   ecx,al\r
+       shl     ecx,22\r
+       shl     eax,31\r
+       or      ebp,ecx                                 ;set N\r
+       or      ebp,eax                                 ;set sf\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+\r
+ARM64_dw_nw:\r
+       ;used by UXTB, UXTH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>       ;0=wd,wn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       jmp     ARM64_dz_nz_mz.encode\r
+\r
+ARM64_dx_nw:\r
+       ;used by SXTW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_word_z_reg>      ;0=xd,wn\r
+       jmp     ARM64_dz_nz_mz.encode\r
+\r
+ARM64_arithmetic1:\r
+       ;used by ADD, ADDS, SUB, SUBS\r
+       bt      ecx,29\r
+       jnc     .non_S\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_sp_reg>,\                            ; 0=wd,wn,wm (reversed sp without imm)\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\                             ; 1=wd,wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\     ; 2=wd,wn,wm,shift imm\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\                 ; 3=wd,wn,wm,extend\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\        ; 4=wd,wn,wm,extend imm\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\           ; 5=wd,wn,wm,lsl imm\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\                 ; 6=wd,wn,wm (catch sp without imm)\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_imm>,\                                    ; 7=wd,wn,imm\r
+       <TMPL_word_z_reg,TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\      ; 8=wd,wn,imm,lsl imm2\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_sp_reg>,\                         ; 9=xd,xn,xm (reversed sp without imm)\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\                          ;10=xd,xn,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\  ;11=xd,xn,xm,shift imm\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\              ;12=xd,xn,xm,extend\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\     ;13=xd,xn,xm,extend imm\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\        ;14=xd,xn,xm,lsl imm\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\              ;15=xd,xn,xm (catch sp without imm)\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_imm>,\                                  ;16=xd,xn,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\    ;17=xd,xn,imm,lsl imm2\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\               ;18=xd,xn,wm,extend\r
+       <TMPL_dword_z_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>        ;19=xd,xn,wm,extend imm\r
+       jmp     .encode\r
+    .non_S_adjust_table:\r
+       db      1,2,3,4,5,6,7,8,0\r
+       db      10,11,12,13,14,15,16,17,18,19,9\r
+       db      20,21,22,23,24,25,26,27\r
+    .non_S:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\                             ; 0=wd,wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\     ; 1=wd,wn,wm,shift imm\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\                 ; 2=wd,wn,wm,extend\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\        ; 3=wd,wn,wm,extend imm\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\           ; 4=wd,wn,wm,lsl imm\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\                 ; 5=wd,wn,wm (catch sp without imm)\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_imm>,\                                    ; 6=wd,wn,imm\r
+       <TMPL_word_s_reg,TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\      ; 7=wd,wn,imm,lsl imm2\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_word_sp_reg>,\                            ; 8=wd,wn,wm (reversed sp without imm)\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\                          ; 9=xd,xn,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\  ;10=xd,xn,xm,shift imm\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\              ;11=xd,xn,xm,extend\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\     ;12=xd,xn,xm,extend imm\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\        ;13=xd,xn,xm,lsl imm\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\              ;14=xd,xn,xm (catch sp without imm)\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_imm>,\                                  ;15=xd,xn,imm\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\    ;16=xd,xn,imm,lsl imm2\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\               ;17=xd,xn,wm,extend\r
+       <TMPL_dword_s_reg,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\      ;18=xd,xn,wm,extend imm\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_dword_sp_reg>,\                         ;19=xd,xn,xm (reversed sp without imm)\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\                                   ;20=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\                                ;21=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\                                   ;22=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\                                   ;23=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\                                   ;24=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\                                   ;25=vd,vn,vm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\                                ;26=dd,dn,dm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>                                     ;27=vd,vn,vm\r
+       movzx   eax,al\r
+       mov     al,[.non_S_adjust_table+eax]\r
+    .encode:\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,20\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       cmp     al,9\r
+       cmc\r
+       sbb     ecx,ecx\r
+       and     cl,9\r
+       sub     al,cl\r
+       mov     cl,ch\r
+       shl     ecx,31\r
+       or      ebp,ecx                                 ;set sf\r
+       cmp     al,0\r
+       jnz     .swap_okay\r
+       bt      ebp,30                                  ;sub?\r
+       jc      ERROR_parameter_n_not_valid.third       ;can't swap r,r,sp with sub\r
+       mov     cl,[operand_register1]\r
+       mov     ch,[operand_register2]\r
+       mov     [operand_register1],ch\r
+       mov     [operand_register2],cl\r
+       add     al,6\r
+    .swap_okay:\r
+       cmp     al,9\r
+       jae     .extended_register_xxw\r
+       cmp     al,2\r
+       jbe     .shifted_register\r
+       cmp     al,6\r
+       ja      .immediate\r
+       jmp     .extended_register\r
+    .extended_register_xxw:\r
+       mov     cl,[instruction_shift_op]\r
+       and     cl,0x3\r
+       cmp     cl,0x3\r
+       jz      ERROR_parameter_n_not_valid.third       ;can't have w with [su]xtx\r
+       sub     al,7\r
+    .extended_register:\r
+       or      ebp,0x59 shl 21\r
+       ;set lsl\r
+       cmp     al,5\r
+       jz      .set_lsl\r
+       cmp     al,6\r
+       jnz     .lsl_okay\r
+    .set_lsl:\r
+       test    ebp,ebp\r
+       sets    cl\r
+       add     cl,2\r
+       mov     [instruction_shift_op],cl\r
+    .lsl_okay:\r
+       movzx   ecx,[instruction_shift_op]\r
+       shl     ecx,13\r
+       or      ebp,ecx\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,4\r
+       ja      ERROR_shift_value_out_of_range.0_4\r
+       jmp     .encode_immediate\r
+    .shifted_register:\r
+       or      ebp,0xb shl 24\r
+    .encode_shifted_register:\r
+       movzx   eax,[instruction_shift_op]\r
+       shl     eax,22\r
+       or      ebp,eax\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_63\r
+       mov     edx,ERROR_shift_value_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,eax\r
+       jae     ARM_store_instruction_with_error\r
+    .encode_immediate:\r
+       shl     edx,10\r
+       or      ebp,edx\r
+    .encode_rm:\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+    .encode_rn:\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+    .encode_rd:\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+    .immediate:\r
+       or      ebp,0x11 shl 24\r
+       mov     edx,[immediate_value]\r
+       test    edx,edx\r
+       jz      .encode_immediate\r
+       jns     .immediate_positive\r
+       neg     edx\r
+       xor     ebp,1 shl 30                            ;invert the operation ADD<-->SUB\r
+    .immediate_positive:\r
+       mov     ecx,[immediate_value2]\r
+       cmp     ecx,32\r
+       jae     .immediate_out_of_range\r
+       xor     eax,eax\r
+       shld    eax,edx,cl\r
+       test    eax,eax\r
+       jnz     .immediate_out_of_range\r
+       shl     edx,cl\r
+       cmp     edx,0xfff\r
+       jbe     .encode_immediate\r
+       or      ebp,1 shl 22                            ;enable lsl 12\r
+       test    edx,0xfff\r
+       jnz     .immediate_out_of_range\r
+       shr     edx,12\r
+       cmp     edx,0xfff\r
+       jbe     .encode_immediate\r
+    .immediate_out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xfff_lsl_12\r
+       jmp     ARM_store_instruction_with_error\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       and     ebp,1 shl 30                            ;isolate the add/sub bit\r
+       shr     ebp,1\r
+       or      ebp,0x0e208400\r
+       sub     al,18+2\r
+    .vector_encode:\r
+       cmp     al,6                                    ;scalar?\r
+       setz    dl\r
+       shr     al,1\r
+       setc    cl\r
+       shl     ecx,30\r
+       or      ebp,ecx                                 ;set Q\r
+       mov     ah,0\r
+       shl     eax,22\r
+       or      ebp,eax                                 ;set size\r
+       neg     dl\r
+       and     dl,5\r
+       shl     edx,28\r
+       or      ebp,edx                                 ;set for scalar\r
+       jmp     .encode_rm\r
+\r
+ARM64_arithmetic1_zr:\r
+       ;used by CMN, CMP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_never>,\                                                  ; 0=sp swap not valid\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\                             ; 1=wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\     ; 2=wn,wm,shift imm\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend>,\                 ; 3=wn,wm,extend\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>,\        ; 4=wn,wm,extend imm\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm>,\           ; 5=wn,wm,lsl imm\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_always>,\                 ; 6=wn,wm (catch sp without imm)\r
+       <TMPL_word_s_reg,TMPL_imm>,\                                    ; 7=wn,imm\r
+       <TMPL_word_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\      ; 8=wn,imm,lsl imm2\r
+       <TMPL_never>,\                                                  ; 9=sp swap not valid\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\                           ;10=xn,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\   ;11=xn,xm,shift imm\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend>,\               ;12=xn,xm,extend\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm>,\      ;13=xn,xm,extend imm\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm>,\         ;14=xn,xm,lsl imm\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_always>,\               ;15=xn,xm (catch sp without imm)\r
+       <TMPL_dword_s_reg,TMPL_imm>,\                                   ;16=xn,imm\r
+       <TMPL_dword_s_reg,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\     ;17=xn,imm,lsl imm2\r
+       <TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend>,\                ;18=xn,wm,extend\r
+       <TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm>         ;19=xd,xn,wm,extend imm\r
+       mov     edx,[operand_registers]\r
+       shl     edx,8\r
+       or      edx,0x1f\r
+       mov     [operand_registers],edx\r
+       jmp     ARM64_arithmetic1.encode\r
+\r
+ARM64_arithmetic2:\r
+       ;used by AND, ANDS, BIC, BICS, EOR, EON, ORN, ORR\r
+       test    al,FLAG_CONDITION_SET\r
+       setnz   bl\r
+       shl     ebx,30\r
+       or      ecx,ebx\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\                             ; 0=wd,wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\      ; 1=wd,wn,wm,shift imm\r
+       <TMPL_word_s_reg,TMPL_word_z_reg,TMPL_imm>,\                                    ; 2=wd,wn,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\                          ; 3=xd,xn,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\   ; 4=xd,xn,xm,shift imm\r
+       <TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_imm64>,\                                ; 5=xd,xn,imm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\                                   ; 6=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\                                ; 7=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_imm>,\                                                      ; 8=vd,imm\r
+       <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\                        ; 9=vd,imm,lsl imm\r
+       <TMPL_vect_v8h,TMPL_imm>,\                                                      ;10=vd,imm\r
+       <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\                        ;11=vd,imm,lsl imm\r
+       <TMPL_vect_v2s,TMPL_imm>,\                                                      ;12=vd,imm\r
+       <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\                        ;13=vd,imm,lsl imm\r
+       <TMPL_vect_v4s,TMPL_imm>,\                                                      ;14=vd,imm\r
+       <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>                          ;15=vd,imm,lsl imm\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+    .encode:\r
+       cmp     al,6\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       cmp     al,3\r
+       cmc\r
+       sbb     ecx,ecx\r
+       and     cl,3\r
+       sub     al,cl\r
+       mov     cl,ch\r
+       shl     ecx,31\r
+       or      ebp,ecx                                 ;set sf\r
+       cmp     al,2\r
+       je      .immediate\r
+    .shifted_register:\r
+       or      ebp,0xa shl 24\r
+       jmp     ARM64_arithmetic1.encode_shifted_register\r
+    .immediate:\r
+       btr     ebp,21\r
+       jnc     .inversion_okay\r
+    .invert:\r
+       ;for BIC, BICS, EON and ORN the immediate is inverted\r
+       mov     ecx,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       not     ecx\r
+       not     edx\r
+       mov     [immediate_value],ecx\r
+       mov     [immediate_value_high],edx\r
+    .inversion_okay:\r
+       or      ebp,0x12 shl 24\r
+       js      .immediate_prepared\r
+       mov     eax,[immediate_value]\r
+       mov     [immediate_value_high],eax\r
+    .immediate_prepared:\r
+       call    ARM64_encode_bitmask\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jc      ARM_store_instruction_with_error\r
+       mov     edx,eax\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       ;S forms are invalid\r
+       test    [instruction_condition],FLAG_CONDITION_SET\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       ;EON is invalid\r
+       mov     ecx,ebp\r
+       and     ecx,3 shl 29 + 1 shl 21\r
+       cmp     ecx,2 shl 29 + 1 shl 21\r
+       jz      ERROR_parameter_n_not_valid.first\r
+       cmp     al,8\r
+       jae     .vector_immediate\r
+       mov     ecx,ebp\r
+       mov     edx,ebp\r
+       and     ebp,1 shl 30\r
+       and     ecx,1 shl 29\r
+       and     edx,1 shl 21\r
+       shr     ebp,30-29\r
+       shr     ecx,29-23\r
+       shl     edx,22-21\r
+       or      ebp,ecx\r
+       or      ebp,edx\r
+       or      ebp,0x0e201c00\r
+       sub     al,6\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+    .vector_immediate:\r
+       ;EOR is invalid\r
+       test    ebp,1 shl 30\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       mov     edx,[immediate_value]\r
+       test    al,4\r
+       setz    bl\r
+       mov     bh,0\r
+       shl     ebx,16\r
+       neg     ebx\r
+       test    edx,ebx\r
+       jz      .primary_range_okay\r
+       xor     edx,ebx\r
+       test    edx,ebx\r
+       jnz     .out_of_range\r
+    .primary_range_okay:\r
+       not     ebx\r
+       ;invert AND\r
+       test    ebp,ebp\r
+       jz      .vector_invert\r
+       ;invert ORN\r
+       cmp     ebp,1 shl 29 + 1 shl 21\r
+       jnz     .vector_invert_okay\r
+    .vector_invert:\r
+       ;for AND and ORN the immediate is inverted\r
+       xor     edx,ebx\r
+       ;convert AND to BIC and ORN to ORR\r
+       xor     ebp,1 shl 21\r
+    .vector_invert_okay:\r
+       ;build the number\r
+       test    edx,edx\r
+       jz      .immediate_built\r
+       mov     ecx,[immediate_value2]\r
+       cmp     cl,32\r
+       jae     .out_of_range\r
+       push    ebx\r
+       xor     ebx,ebx\r
+       shld    ebx,edx,cl\r
+       test    ebx,ebx\r
+       pop     ebx\r
+       jnz     .out_of_range\r
+       shl     edx,cl\r
+       not     ebx\r
+       test    edx,ebx\r
+       jnz     .out_of_range\r
+    .immediate_built:\r
+       and     ebp,1 shl 21\r
+       shl     ebp,29-21\r
+       or      ebp,0x0f001400\r
+       sub     al,8\r
+       test    al,2\r
+       setnz   cl\r
+       shl     ecx,30\r
+       or      ebp,ecx                                 ;set Q\r
+       test    al,4\r
+       setz    cl\r
+       shl     ecx,15\r
+       or      ebp,ecx                                 ;set cmode = x001b\r
+       shr     ecx,14\r
+       sub     ecx,4\r
+       neg     ecx\r
+       xor     ebx,ebx\r
+    .try_immediate:\r
+       cmp     edx,0xff\r
+       jbe     .immediate_ready\r
+       test    edx,0xff\r
+       jnz     .out_of_range\r
+       shr     edx,8\r
+       inc     bl\r
+       cmp     bl,cl\r
+       jae     .out_of_range\r
+       jmp     .try_immediate\r
+    .immediate_ready:\r
+       shl     ebx,13\r
+       or      ebp,ebx\r
+       mov     eax,edx\r
+       and     edx,0x1f\r
+       and     eax,0xe0\r
+       shl     edx,5\r
+       shl     eax,16-5\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rd\r
+    .out_of_range:\r
+       test    ebp,1 shl 15\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xff_lsl_8\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_0xff_lsl_24\r
+       cmovz   ecx,edx\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_arithmetic3:\r
+       ;used by ASR, LSL, LSR, ROR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm>,\            ;1=wd,wn,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\  ;2=wd,wn,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm>            ;3=wd,wn,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,2\r
+       setae   cl\r
+       shl     ecx,31\r
+       or      ebp,ecx                                 ;set sf\r
+       and     al,1\r
+       jz      ARM64_arithmetic1.encode_rm\r
+       ;immediate\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_63\r
+       mov     edx,ERROR_shift_value_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       sets    bl\r
+       movzx   ebx,bl\r
+       shl     ebx,22\r
+       cmp     eax,[immediate_value]\r
+       jbe     ARM_store_instruction_with_error\r
+       test    ebp,3 shl 10\r
+       jnz     .asr_lsr_ror\r
+    .lsl:\r
+       dec     eax\r
+       mov     edx,[immediate_value]\r
+       and     ebp,1 shl 31\r
+       or      ebp,ebx                                 ;set N\r
+       or      ebp,0x53000000\r
+       mov     ecx,edx\r
+       neg     edx\r
+       and     edx,eax\r
+       sub     eax,ecx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       shl     eax,10\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+    .asr_lsr_ror:\r
+       mov     edx,ebp\r
+       shl     edx,30-10\r
+       cmp     edx,0xc0000000\r
+       jae     .ror\r
+       and     edx,1 shl 30\r
+       and     ebp,1 shl 31\r
+       or      ebp,edx\r
+       or      ebp,ebx                                 ;set N\r
+       shr     ebx,22-15\r
+       or      ebp,0x13007c00\r
+       mov     edx,[immediate_value]\r
+       shl     edx,16\r
+    .set_shift_and_N:\r
+       or      ebp,edx\r
+       or      ebp,ebx\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+    .ror:\r
+       and     ebp,1 shl 31\r
+       or      ebp,0x13800000\r
+       mov     cl,[operand_register1]\r
+       mov     [operand_register2],cl\r
+       mov     edx,[immediate_value]\r
+       shl     edx,10\r
+       jmp     .set_shift_and_N\r
+\r
+ARM64_arithmetic4:\r
+       ;used by CLS, CLZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\   ;1=xd,xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;2=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\       ;3=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\         ;4=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>,\         ;5=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;6=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>           ;7=vd,vn\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,2\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       not     ebp\r
+       and     ebp,1 shl 10\r
+       shl     ebp,29-10\r
+       or      ebp,0x0e204800\r
+       sub     al,2\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_arithmetic5:\r
+       ;used by EXTR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm>,\    ;0=wd,wn,wm,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm>   ;1=xd,xn,xm,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       shr     eax,31-22\r
+       or      ebp,eax                                 ;set N\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_63\r
+       mov     edx,ERROR_shift_value_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,eax\r
+       jae     ARM_store_instruction_with_error\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+\r
+ARM64_register_rotate:\r
+       ;used by ASRV, LSLV, LSRV, RORV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>    ;1=xd,xn,xm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_adr:\r
+       ;used by ADR, ADRP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_address64>       ;0=xd,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ecx,[addressing_space]\r
+       add     eax,[ecx+0]\r
+       adc     edx,[ecx+4]\r
+       sub     eax,edi\r
+       sbb     edx,0\r
+       test    ebp,ebp                         ;ADRP?\r
+       jns     .offset_okay\r
+       shrd    eax,edx,12\r
+       sar     edx,12\r
+    .offset_okay:\r
+       mov     ecx,edx\r
+       cdq\r
+       cmp     ecx,edx\r
+       mov     ecx,ERROR_branch_too_far\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     eax,0xfffff\r
+       jg      ARM_store_instruction_with_error\r
+       cmp     eax,-0x100000\r
+       jl      ARM_store_instruction_with_error\r
+       mov     ecx,eax\r
+       and     eax,0x1ffffc\r
+       and     ecx,0x000003\r
+       shl     eax,5-2\r
+       shl     ecx,29\r
+       or      eax,ecx\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_sys_predefined_at:\r
+       ;used by AT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_at_op,TMPL_dword_z_reg>   ;0=at,xd\r
+       mov     edx,sys_encode_table_at\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       mov     eax,[immediate_value]\r
+       movzx   ecx,word[edx+eax*2]\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_sys_predefined_dc:\r
+       ;used by DC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dc_op,TMPL_dword_z_reg>   ;0=dc,xd\r
+       mov     edx,sys_encode_table_dc\r
+       jmp     ARM64_sys_predefined_at.encode\r
+\r
+ARM64_sys_predefined_ic:\r
+       ;used by IC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_ic_op>,\                  ;0=ic\r
+       <TMPL_ic_op,TMPL_dword_z_reg>   ;1=ic,xd\r
+       mov     edx,sys_encode_table_ic\r
+    .do:\r
+       mov     cl,[operand_register0]\r
+       mov     bl,0x1f                 ;defailt to xzr\r
+       test    al,al\r
+       cmovz   ecx,ebx\r
+       mov     [operand_register0],cl\r
+       jmp     ARM64_sys_predefined_at.encode\r
+\r
+ARM64_sys_predefined_tlbi:\r
+       ;used by TLBI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_tlbi_op>,\                ;0=tlbi\r
+       <TMPL_tlbi_op,TMPL_dword_z_reg> ;1=tlbi,xd\r
+       mov     edx,sys_encode_table_tlbi\r
+       jmp     ARM64_sys_predefined_ic.do\r
+\r
+ARM64_sys_predefined_mrs:\r
+       ;used by MRS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_msr_reg>,\       ;0=xd,sysreg (predefined)\r
+       <TMPL_dword_z_reg,TMPL_sysreg_dynamic>  ;1=xd,sysreg (implementation defined)\r
+       test    al,al\r
+       mov     edx,sys_encode_table_msr\r
+       jz      ARM64_sys_predefined_at.encode\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+    .dynamic_reg:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ecx,[immediate_value]\r
+       shl     ecx,5\r
+       or      ebp,ecx\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_sys_predefined_msr:\r
+       ;used by MSR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_msr_reg,TMPL_dword_z_reg>,\       ;0=sysreg,xd\r
+       <TMPL_msr_reg,TMPL_imm2>,\              ;1=sysreg,imm (catch spsel)\r
+       <TMPL_pstate_reg,TMPL_imm2>,\           ;2=sysreg,imm\r
+       <TMPL_sysreg_dynamic,TMPL_dword_z_reg>  ;3=sysreg,xd\r
+       test    al,al\r
+       mov     edx,sys_encode_table_msr\r
+       jz      ARM64_sys_predefined_at.encode\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       cmp     al,2\r
+       jz      .pstate\r
+       cmp     al,3\r
+       jz      ARM64_sys_predefined_mrs.dynamic_reg\r
+       cmp     [immediate_value],(sys_encode_spsel-sys_encode_table_msr) shr 1\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       mov     [immediate_value],(sys_pencode_spsel-sys_encode_table_pstate) shr 1\r
+       mov     edx,[immediate_value2]\r
+       cmp     edx,1\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_1\r
+       ja      ARM_store_instruction_with_error\r
+    .pstate:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     edx,[immediate_value2]\r
+       cmp     edx,15\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_15\r
+       ja      ARM_store_instruction_with_error\r
+       shl     edx,8\r
+       or      ebp,edx\r
+       or      ebp,0x1f\r
+       mov     [arm64_instruction],ebp\r
+       mov     edx,sys_encode_table_pstate\r
+       jmp     ARM64_sys_predefined_at.encode\r
+\r
+ARM64_b_cond:\r
+       ;used by B.<cond>\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_address64>        ;0=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+    .encode:\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ecx,[addressing_space]\r
+       add     eax,[ecx+0]\r
+       adc     edx,[ecx+4]\r
+       sub     eax,edi\r
+       sbb     edx,0\r
+       test    eax,3\r
+       mov     ecx,ERROR_branch_misaligned\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     ebx,edx\r
+       cdq\r
+       cmp     ebx,edx\r
+       mov     ecx,ERROR_branch_too_far\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     eax,0xfffff\r
+       jg      ARM_store_instruction_with_error\r
+       cmp     eax,-0x100000\r
+       jl      ARM_store_instruction_with_error\r
+       and     eax,0x1ffffc\r
+       shl     eax,(5-2)\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_b_reg:\r
+       ;used by CBNZ, CBZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_address64>,\      ;0=wt,imm\r
+       <TMPL_dword_z_reg,TMPL_address64>       ;1=xt,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_b_cond.encode\r
+\r
+ARM64_b:\r
+       call    decode_template\r
+       ;used by B, BL\r
+    TEMPLATE \\r
+       <TMPL_address64>        ;0=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ecx,[addressing_space]\r
+       add     eax,[ecx+0]\r
+       adc     edx,[ecx+4]\r
+       sub     eax,edi\r
+       sbb     edx,0\r
+       test    eax,3\r
+       mov     ecx,ERROR_branch_misaligned\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     ecx,edx\r
+       cdq\r
+       cmp     ecx,edx\r
+       mov     ecx,ERROR_branch_too_far\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     eax,0x7ffffff\r
+       jg      ARM_store_instruction_with_error\r
+       cmp     eax,-0x8000000\r
+       jl      ARM_store_instruction_with_error\r
+       and     eax,0xffffffc\r
+       shr     eax,2\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_bfi:\r
+       ;used by BFI, SBFIZ, UBFIZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\       ;0=wd,wn,imm,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>       ;1=wd,wn,imm,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,al\r
+       shl     eax,22\r
+       or      ebp,eax                                 ;set N\r
+       shl     eax,(31-22)\r
+       or      ebp,eax                                 ;set sf\r
+       ;if BFI then check that rn <> 0x1f\r
+       test    ebp,1 shl 29\r
+       jz      .rn_okay\r
+       cmp     [operand_register1],0x1f\r
+       jz      ERROR_zr_not_valid.second\r
+    .rn_okay:\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_lsb_out_of_range.0_63\r
+       mov     edx,ERROR_lsb_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       cmp     eax,[immediate_value]\r
+       jbe     ARM_store_instruction_with_error\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_width_out_of_range.1_64\r
+       mov     edx,ERROR_width_out_of_range.1_32\r
+       cmovns  ecx,edx\r
+       mov     ebx,[immediate_value2]\r
+       cmp     eax,ebx\r
+       jb      ARM_store_instruction_with_error\r
+       test    ebx,ebx\r
+       jz      ARM_store_instruction_with_error\r
+       ;encode the immediate\r
+       mov     edx,[immediate_value]\r
+       dec     eax\r
+       neg     edx\r
+       and     edx,eax\r
+       dec     ebx\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_width_out_of_range.64\r
+       mov     eax,ERROR_width_out_of_range\r
+       cmovns  ecx,eax\r
+       cmp     ebx,edx\r
+       jae     ARM_store_instruction_with_error\r
+       shl     edx,6\r
+       or      edx,ebx\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+\r
+ARM64_bfm:\r
+       ;used by BFM, SBFM, UBFM\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\       ;0=wd,wn,imm,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>       ;1=wd,wn,imm,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,al\r
+       shl     eax,22\r
+       or      ebp,eax                                 ;set N\r
+       shl     eax,(31-22)\r
+       or      ebp,eax                                 ;set sf\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_immr_out_of_range.0_63\r
+       mov     edx,ERROR_immr_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       cmp     eax,[immediate_value]\r
+       jbe     ARM_store_instruction_with_error\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_imms_out_of_range.0_63\r
+       mov     edx,ERROR_imms_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     ebx,[immediate_value2]\r
+       cmp     eax,ebx\r
+       jbe     ARM_store_instruction_with_error\r
+       ;encode the immediate\r
+       mov     edx,[immediate_value]\r
+       shl     edx,6\r
+       or      edx,ebx\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+\r
+ARM64_bfxil:\r
+       ;used by BFXIL, SBFX, UBFX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>,\       ;0=wd,wn,imm,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_imm2>       ;1=wd,wn,imm,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,al\r
+       shl     eax,22\r
+       or      ebp,eax                                 ;set N\r
+       shl     eax,(31-22)\r
+       or      ebp,eax                                 ;set sf\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_lsb_out_of_range.0_63\r
+       mov     edx,ERROR_lsb_out_of_range.0_31\r
+       cmovns  ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovns  eax,edx\r
+       cmp     eax,[immediate_value]\r
+       jbe     ARM_store_instruction_with_error\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_width_out_of_range.1_64\r
+       mov     edx,ERROR_width_out_of_range.1_32\r
+       cmovns  ecx,edx\r
+       mov     ebx,[immediate_value2]\r
+       cmp     eax,ebx\r
+       jb      ARM_store_instruction_with_error\r
+       test    ebx,ebx\r
+       jz      ARM_store_instruction_with_error\r
+       ;encode the immediate\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_width_out_of_range.64\r
+       mov     edx,ERROR_width_out_of_range\r
+       cmovns  ecx,edx\r
+       mov     edx,[immediate_value]\r
+       lea     ebx,[edx+ebx-1]\r
+       cmp     ebx,eax\r
+       jae     ARM_store_instruction_with_error\r
+       shl     edx,6\r
+       or      edx,ebx\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+\r
+ARM64_br:\r
+       ;used by BLR, BR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg>      ;0=xd\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_debug:\r
+       ;used by BRK, HLT, HVC, SMC, SVC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>      ;0=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x10000\r
+       jae     ERROR_immediate_value_out_of_range.0_0xffff\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_debug2:\r
+       ;used by DCPS1, DCPS2, DCPS3\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>,\    ;0=empty\r
+       <TMPL_imm>      ;1=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xffff\r
+       ja      ERROR_immediate_value_out_of_range.0_0xffff\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_hint:\r
+       ;used by HINT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm>      ;0=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0x7f\r
+       ja      ERROR_immediate_value_out_of_range.0_0x7f\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_debug3:\r
+       ;used by DRPS, ERET, NOP, SEV, SEVL, WFE, WFI, YIELD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>      ;0=empty\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_conditional_compare:\r
+       ;used by CCMN, CCMP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\       ;0=wn,wm,imm,cond\r
+       <TMPL_word_z_reg,TMPL_imm2,TMPL_comma,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\  ;1=wn,imm,imm,cond\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\     ;2=xn,xm,imm,cond\r
+       <TMPL_dword_z_reg,TMPL_imm2,TMPL_comma,TMPL_imm,TMPL_comma,TMPL_condition_nv>   ;3=xn,imm,imm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       cmp     al,2\r
+       setae   cl\r
+       shl     ecx,31\r
+       or      ebp,ecx                                 ;set sf\r
+       and     eax,1\r
+       shl     eax,11\r
+       or      ebp,eax                                 ;set immediate bit\r
+    .encode:\r
+       mov     ecx,ERROR_condition_value_out_of_range\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,15\r
+       ja      ARM_store_instruction_with_error\r
+       or      ebp,edx\r
+       movzx   edx,[operand_register0]\r
+       shl     edx,5\r
+       or      ebp,edx\r
+       test    eax,eax\r
+       jnz     .immediate\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+    .store_condition:\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+    .immediate:\r
+       mov     edx,[immediate_value2]\r
+       test    edx,edx\r
+       jns     .positive\r
+       neg     edx\r
+       xor     ebp,1 shl 30\r
+    .positive:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_31\r
+       cmp     edx,31\r
+       ja      ARM_store_instruction_with_error\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       movzx   eax,[operand_register1]\r
+       jmp     .store_condition\r
+\r
+ARM64_conditional_modify:\r
+       ;used by CINC, CINV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\   ;0=wn,wm,cond\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv>   ;1=xn,xm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       movzx   edx,[operand_register1]\r
+       cmp     edx,31\r
+       jz      ERROR_zr_not_valid.second\r
+    .encode:\r
+       shl     edx,5\r
+       or      ebp,edx\r
+       shl     edx,16-5\r
+       or      ebp,edx\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]                 ;get condition\r
+    .check_condition:\r
+       cmp     eax,14\r
+       jae     ERROR_al_nv_not_valid\r
+       xor     al,1\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_conditional_modify_zr:\r
+       ;used by CNEG\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\   ;0=wn,wm,cond\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv>   ;1=xn,xm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       movzx   edx,[operand_register1]\r
+       jmp     ARM64_conditional_modify.encode\r
+\r
+ARM64_conditional_select:\r
+       ;used by CSEL, CSINC, CSINV, CSNEG\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_condition_nv>,\   ;0=wd,wn,wm,cond\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_condition_nv>  ;1=xd,xn,xm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       shl     eax,31\r
+    .encode:\r
+       or      ebp,eax                                 ;set sf\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register3]                 ;get condition\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_conditional_set:\r
+       ;used by CSET, CSETM\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_condition_nv>,\   ;0=wd,cond\r
+       <TMPL_dword_z_reg,TMPL_condition_nv>    ;1=xd,cond\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]                 ;get condition\r
+       jmp     ARM64_conditional_modify.check_condition\r
+\r
+ARM64_clrex:\r
+       ;used by CLREX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>,\    ;0=empty\r
+       <TMPL_imm>      ;1=imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       test    al,al\r
+       mov     eax,[immediate_value]\r
+       mov     ecx,0xf\r
+       cmovz   eax,ecx\r
+       cmp     eax,0xf\r
+       ja      ERROR_immediate_value_out_of_range.0_15\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_data_barrier:\r
+       ;used by DMB, DSB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_barrier>,\        ;0=barrier\r
+       <TMPL_imm>              ;1=imm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       test    al,al\r
+       mov     eax,[immediate_value]\r
+       movzx   ecx,[operand_register0]\r
+       cmovz   eax,ecx\r
+       cmp     eax,0xf\r
+       ja      ERROR_immediate_value_out_of_range.0_15\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_instruction_barrier:\r
+       ;used by ISB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_barrier>,\        ;0=barrier\r
+       <TMPL_imm>,\            ;1=imm\r
+       <TMPL_EOL>              ;2=empty\r
+       cmp     al,2\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,0xf\r
+       cmovz   edx,ecx\r
+       mov     [immediate_value],edx\r
+       jmp     ARM64_data_barrier.encode\r
+\r
+ARM64_memory_single_fixed:\r
+       ;used by LDAR, LDAXR, LDXR, STLR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\           ;0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\  ;1=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\            ;2=wt,[address]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\          ;3=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>             ;5=xt,[address]\r
+    .encode:\r
+       mov     ebp,[arm64_instruction]\r
+    .encode2:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       test    edx,edx\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     al,3\r
+       setae   al\r
+       shl     eax,30\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+ARM64_memory_word_single_fixed:\r
+       ;used by LDARB, LDARH, LDAXRB, LDAXRH, LDXRB, LDXRH, STLRB, STLRH\r
+       test    ecx,1 shl 30\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\               ;0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\      ;1=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                  ;2=wt,[address]\r
+       jmp     ARM64_memory_single_fixed.encode\r
+\r
+ARM64_memory_double_fixed:\r
+       ;used by LDAXP, LDXP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                   ;0=wt1,wt2,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\          ;1=wt1,wt2,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                    ;2=wt1,wt2,[address]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                ;3=xt1,xt2,[xn]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\       ;4=xt1,xt2,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                   ;5=xt1,xt2,[address]\r
+       mov     ebp,[arm64_instruction]\r
+    .encode:\r
+       mov     edx,[operand_registers]\r
+       cmp     dh,dl\r
+       jz      ERROR_destination_registers_must_differ\r
+       shr     edx,8\r
+       mov     [operand_register1],dh\r
+       movzx   edx,dl\r
+       shl     edx,10\r
+       or      ebp,edx\r
+       jmp     ARM64_memory_single_fixed.encode2\r
+\r
+ARM64_memory_word_double_release_fixed:\r
+       ;used by STLXRB, STLRXH, STXRB, STRRH\r
+       test    ecx,1 shl 30\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\               ;0=ws,wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\      ;1=ws,wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                  ;2=ws,wt,[address]\r
+    .encode:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ecx,[operand_registers]\r
+       movzx   edx,cl\r
+       shr     ecx,8\r
+       mov     [operand_registers],ecx\r
+       cmp     dl,cl\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+       cmp     ch,31\r
+       jz      .regs_okay\r
+       cmp     dl,ch\r
+       jz      ERROR_dest_cannot_be_source_or_memory_address\r
+    .regs_okay:\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       jmp     ARM64_memory_single_fixed.encode2\r
+\r
+ARM64_memory_double_release_fixed:\r
+       ;used by STLXR, STXR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\           ;0=ws,wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\  ;1=ws,wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\            ;2=ws,wt,[address]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\          ;3=ws,xt,[xn]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=ws,xt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>             ;5=ws,xt,[address]\r
+       jmp     ARM64_memory_word_double_release_fixed.encode\r
+\r
+ARM64_memory_triple_fixed:\r
+       ;used by STLXP, STXP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                   ;0=ws,wt1,wt2,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\          ;1=ws,wt1,wt2,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                    ;2=ws,wt1,wt2,[address]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                ;3=ws,xt1,xt2,[xn]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\       ;4=ws,xt1,xt2,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                   ;5=ws,xt1,xt2,[address]\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ecx,[operand_registers]         ;n,t2,t1,s\r
+       movzx   ebx,cl                          ;Ws\r
+       shl     ebx,16\r
+       or      ebp,ebx\r
+       shr     ebx,16\r
+       shr     ecx,8                           ;n,t2,t1\r
+       cmp     bl,cl                           ;t1\r
+       jz      .bad_regs\r
+       cmp     bl,ch                           ;t2\r
+       jz      .bad_regs\r
+       xchg    ch,cl                           ;n,t1,t2\r
+       movzx   edx,cl\r
+       shl     edx,10\r
+       or      ebp,edx\r
+       shr     ecx,8                           ;n,t1\r
+       mov     [operand_registers],ecx\r
+       cmp     ch,31\r
+       jz      ARM64_memory_single_fixed.encode2\r
+       cmp     bl,ch\r
+       jnz     ARM64_memory_single_fixed.encode2\r
+    .bad_regs:\r
+       jmp     ERROR_dest_cannot_be_source_or_memory_address\r
+\r
+ARM64_memory_double_imm7_post_pre_offset:\r
+       ;used by LDP, STP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                   ; 0=wt1,wt2,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                          ; 1=wt1,wt2,[xn],imm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                          ; 2=wt1,wt2,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\    ; 3=wt1,wt2,[xn,imm]!\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                    ; 4=wt1,wt2,[address]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\              ; 5=wt1,wt2,[address]!\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                ; 6=xt1,xt2,[xn]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                       ; 7=xt1,xt2,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                       ; 8=xt1,xt2,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\ ; 9=xt1,xt2,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                 ;10=xt1,xt2,[address]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\           ;11=xt1,xt2,[address]!\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                     ;12=st1,st2,[xn]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                            ;13=st1,st2,[xn],imm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                            ;14=st1,st2,[xn,imm]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\      ;15=st1,st2,[xn,imm]!\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                      ;16=st1,st2,[address]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                ;17=st1,st2,[address]!\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                    ;18=dt1,dt2,[xn]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                           ;19=dt1,dt2,[xn],imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                           ;20=dt1,dt2,[xn,imm]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;21=dt1,dt2,[xn,imm]!\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                     ;22=dt1,dt2,[address]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\               ;23=dt1,dt2,[address]!\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                    ;24=qt1,qt2,[xn]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                           ;25=qt1,qt2,[xn],imm\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                           ;26=qt1,qt2,[xn,imm]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\     ;27=qt1,qt2,[xn,imm]!\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                     ;28=qt1,qt2,[address]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                 ;29=qt1,qt2,[address]!\r
+    .do:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ah,0\r
+       mov     cl,6\r
+       div     cl\r
+       cmp     ah,4\r
+       setae   cl\r
+       add     cl,cl\r
+       sub     ah,cl\r
+       movzx   ecx,ah\r
+       setz    dl\r
+       add     dl,dl\r
+       or      cl,dl\r
+       shl     ecx,23\r
+       or      ebp,ecx\r
+    .encode:\r
+       mov     dx,word[operand_register0]\r
+       test    ebp,1 shl 22\r
+       jz      .reg_pair_okay\r
+       cmp     dh,dl\r
+       jz      ERROR_destination_registers_must_differ\r
+    .reg_pair_okay:\r
+       cmp     al,2\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       test    ah,1\r
+       jz      .writeback_okay\r
+       cmp     [operand_register2],31\r
+       jz      .writeback_okay\r
+       cmp     dl,[operand_register2]\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+       cmp     dh,[operand_register2]\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+    .writeback_okay:\r
+       shl     eax,31\r
+       or      ebp,eax\r
+       shr     eax,31\r
+       jmp     .set_multiplier\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       or      ebp,1 shl 26\r
+       sub     al,2\r
+       shl     eax,30\r
+       or      ebp,eax\r
+       shr     eax,30\r
+    .set_multiplier:\r
+       lea     ecx,[eax+2]\r
+       mov     eax,ERROR_immediate_offset_out_of_range.m256_252\r
+       mov     edx,ERROR_immediate_offset_out_of_range.m512_504\r
+       mov     ebx,ERROR_immediate_offset_out_of_range.m1024_1008\r
+       cmp     ecx,3\r
+       cmovz   eax,edx\r
+       cmova   eax,ebx\r
+       mov     ebx,[immediate_value]\r
+       or      edx,-1\r
+       shl     edx,cl\r
+       not     edx\r
+       test    ebx,edx\r
+       cmovnz  ecx,eax\r
+       jnz     ARM_store_instruction_with_error\r
+       sar     ebx,cl\r
+       mov     ecx,eax\r
+       cmp     ebx,-64\r
+       jl      ARM_store_instruction_with_error\r
+       cmp     ebx,+64\r
+       jge     ARM_store_instruction_with_error\r
+       and     ebx,0x7f\r
+       shl     ebx,15\r
+       or      ebp,ebx\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,10\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_memory_double_imm7:\r
+       ;used by LDNP, STNP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                   ; 0=wt1,wt2,[xn]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\          ; 1=wt1,wt2,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                    ; 2=wt1,wt2,[address]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                ; 3=xt1,xt2,[xn]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\       ; 4=xt1,xt2,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                 ; 5=xt1,xt2,[address]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 6=st1,st2,[xn]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\            ; 7=st1,st2,[xn,imm]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                      ; 8=st1,st2,[address]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                    ; 9=dt1,dt2,[xn]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\           ;10=dt1,dt2,[xn,imm]\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                     ;11=dt1,dt2,[address]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                    ;12=qt1,qt2,[xn]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\           ;13=qt1,qt2,[xn,imm]\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_size_32,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                       ;14=qt1,qt2,[address]\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ah,0\r
+       mov     cl,3\r
+       div     cl\r
+       add     ah,ah\r
+       jmp     ARM64_memory_double_imm7_post_pre_offset.encode\r
+\r
+ARM64_memory_double_imm7_signed:\r
+       ;used by LDPSW\r
+       mov     [operand_size],8\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                     ;0=xt1,xt2,[xn]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                            ;1=xt1,xt2,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                            ;2=xt1,xt2,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\      ;3=xt1,xt2,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                      ;4=wt1,wt2,[address]\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                  ;5=wt1,wt2,[address]!\r
+       mov     ebp,[arm64_instruction]\r
+       jmp     ARM64_memory_double_imm7_post_pre_offset.do\r
+\r
+ARM64_memory:\r
+       ;used by LDR, STR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                           ;  0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                  ;  1=wt,[xn],imm\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                  ;  2=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\            ;  3=wt,[xn,imm]!\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                           ;  4=wt,[xn,wm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\               ;  5=wt,[xn,wm,extend]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ;  6=wt,[xn,wm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ;  7=wt,[xn,wm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                          ;  8=wt,[xn,xm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\              ;  9=wt,[xn,xm,extend]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\     ; 10=wt,[xn,xm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\        ; 11=wt,[xn,xm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                            ; 12=wt,[address]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                      ; 13=wt,[address]!\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                             ; 14=wt,[address]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_address64>,\                                                                                  ; 15=wt,address\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                          ; 16=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                 ; 17=xt,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                 ; 18=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\           ; 19=xt,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                          ; 20=xt,[xn,wm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\              ; 21=xt,[xn,wm,extend]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\     ; 22=xt,[xn,wm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\        ; 23=xt,[xn,wm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                         ; 24=xt,[xn,xm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\             ; 25=xt,[xn,xm,extend]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\    ; 26=xt,[xn,xm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\       ; 27=xt,[xn,xm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                           ; 28=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                     ; 29=xt,[address]!\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                            ; 30=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_address64>,\                                                                                 ; 31=xt,address\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                            ; 32=bt,[xn]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                   ; 33=bt,[xn],imm\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                   ; 34=bt,[xn,imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ; 35=bt,[xn,imm]!\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                            ; 36=bt,[xn,wm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\                ; 37=bt,[xn,wm,extend]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\       ; 38=bt,[xn,wm,extend imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\          ; 39=bt,[xn,wm,lsl imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                           ; 40=bt,[xn,xm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\               ; 41=bt,[xn,xm,extend]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ; 42=bt,[xn,xm,extend imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ; 43=bt,[xn,xm,lsl imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                             ; 44=bt,[address]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                       ; 45=bt,[address]!\r
+       <TMPL_never>,\                                                                                                                  ; 46=-\r
+       <TMPL_never>,\                                                                                                                  ; 47=-\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                            ; 48=ht,[xn]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                   ; 49=ht,[xn],imm\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                   ; 50=ht,[xn,imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ; 51=ht,[xn,imm]!\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                            ; 52=ht,[xn,wm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\                ; 53=ht,[xn,wm,extend]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\       ; 54=ht,[xn,wm,extend imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\          ; 55=ht,[xn,wm,lsl imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                           ; 56=ht,[xn,xm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\               ; 57=ht,[xn,xm,extend]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ; 58=ht,[xn,xm,extend imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ; 59=ht,[xn,xm,lsl imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                             ; 60=ht,[address]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                       ; 61=ht,[address]!\r
+       <TMPL_never>,\                                                                                                                  ; 62=-\r
+       <TMPL_never>,\                                                                                                                  ; 63=-\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                            ; 64=st,[xn]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                   ; 65=st,[xn],imm\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                   ; 66=st,[xn,imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ; 67=st,[xn,imm]!\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                            ; 68=st,[xn,wm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\                ; 69=st,[xn,wm,extend]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\       ; 70=st,[xn,wm,extend imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\          ; 71=st,[xn,wm,lsl imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                           ; 72=st,[xn,xm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\               ; 73=st,[xn,xm,extend]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ; 74=st,[xn,xm,extend imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ; 75=st,[xn,xm,lsl imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                             ; 76=st,[address]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                       ; 77=st,[address]!\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                              ; 78=st,[address]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_address64>,\                                                                                   ; 79=st,address\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                            ; 80=dt,[xn]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                   ; 81=dt,[xn],imm\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                   ; 82=dt,[xn,imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\             ; 83=dt,[xn,imm]!\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                            ; 84=dt,[xn,wm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\                ; 85=dt,[xn,wm,extend]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\       ; 86=dt,[xn,wm,extend imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\          ; 87=dt,[xn,wm,lsl imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                           ; 88=dt,[xn,xm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\               ; 89=dt,[xn,xm,extend]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ; 90=dt,[xn,xm,extend imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ; 91=dt,[xn,xm,lsl imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                             ; 92=dt,[address]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                       ; 93=dt,[address]!\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                              ; 94=dt,[address]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_address64>,\                                                                                   ; 95=dt,address\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                           ; 96=qt,[xn]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                                  ; 97=qt,[xn],imm\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                  ; 98=qt,[xn,imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\            ; 99=qt,[xn,imm]!\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                           ;100=qt,[xn,wm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\               ;101=qt,[xn,wm,extend]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\      ;102=qt,[xn,wm,extend imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\         ;103=qt,[xn,wm,lsl imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                          ;104=qt,[xn,xm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\              ;105=qt,[xn,xm,extend]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\     ;106=qt,[xn,xm,extend imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\        ;107=qt,[xn,xm,lsl imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                            ;108=qt,[address]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                      ;109=qt,[address]!\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                             ;110=qt,[address]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_address64>                                                                                    ;111=qt,address\r
+               ;\r
+               ;W&X\r
+               ;unscaled off   AB11-1000-CD0i-iiii-iiii-00nn-nnnt-tttt\r
+               ;immediate post AB11-1000-CD0i-iiii-iiii-01nn-nnnt-tttt\r
+               ;unprivileged   AB11-1000-010i-iiii-iiii-10nn-nnnt-tttt\r
+               ;immediate pre  AB11-1000-CD0i-iiii-iiii-11nn-nnnt-tttt\r
+               ;register       AB11-1000-CD1m-mmmm-xxxx-10nn-nnnt-tttt\r
+               ;immediate off  AB11-1001-CDii-iiii-iiii-iinn-nnnt-tttt\r
+               ;literal        JK01-1000-iiii-iiii-iiii-iiii-iiit-tttt\r
+               ;\r
+               ;ABCD=0000 ---> strb W  B(st)   sttrb W\r
+               ;ABCD=0001 ---> ldrb W  B(ld)   ldtrb W\r
+               ;ABCD=0010 ---> ldrsb X Q(st)   ldtrsb X\r
+               ;ABCD=0011 ---> ldrsb W Q(ld)   ldtrsb W\r
+               ;ABCD=0100 ---> strh W  H(st)   sttrh W\r
+               ;ABCD=0101 ---> ldrh W  H(ld)   ldtrh W\r
+               ;ABCD=0110 ---> ldrsh X         ldtrsh X\r
+               ;ABCD=0111 ---> ldrsh W         ldtrsh W\r
+               ;ABCD=1000 ---> str W   S(st)   sttr W\r
+               ;ABCD=1001 ---> ldr W   S(ld)   ldtr W\r
+               ;ABCD=1010 ---> ldrsw X         ldtrsw X\r
+               ;ABCD=1011 ---> ----\r
+               ;ABCD=1100 ---> str X   D(st)   sttr X\r
+               ;ABCD=1101 ---> ldr X   D(ld)   ldtr X\r
+               ;ABCD=1110 ---> prfm i\r
+               ;ABCD=1111 ---> ----\r
+               ;\r
+               ;JK=00 ---> W\r
+               ;JK=01 ---> X\r
+               ;JK=10 ---> SW\r
+               ;JK=11 ---> PRFM\r
+               ;\r
+               ;BHSD&Q\r
+               ;immediate post EF11-1100-G10i-iiii-iiii-01nn-nnnt-tttt\r
+               ;immediate pre  EF11-1100-G10i-iiii-iiii-11nn-nnnt-tttt\r
+               ;immediate off  EF11-1101-G1ii-iiii-iiii-iinn-nnnt-tttt\r
+               ;register       EF11-1100-G11m-mmmm-xxxx-10nn-nnnt-tttt\r
+               ;literal        KL01-1100-iiii-iiii-iiii-iiii-iiit-tttt\r
+               ;EFG=000 ---> B\r
+               ;EFG=010 ---> H\r
+               ;EFG=100 ---> S\r
+               ;EFG=110 ---> D\r
+               ;EFG=001 ---> Q\r
+               ;\r
+               ;KL=00 ---> S\r
+               ;KL=01 ---> D\r
+               ;KL=10 ---> Q\r
+    .decode:\r
+       mov     ch,2                    ;set register offset for Wt and Xt\r
+    .do:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ah,al\r
+       shr     al,4\r
+       and     ah,0xf                  ;al=target reg index, ah=parameters\r
+       ;set target register\r
+       cmp     al,1\r
+       ja      .set_vector_reg\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       cmp     ah,1                    ;t,[n],imm\r
+       jz      .check_writeback\r
+       cmp     ah,3                    ;t,[n,imm]!\r
+       jz      .check_writeback\r
+       cmp     ah,13                   ;t,[exp]!\r
+       jnz     .writeback_okay\r
+    .check_writeback:\r
+       mov     dx,word[operand_register0]\r
+       cmp     dh,31\r
+       jz      .writeback_okay\r
+       cmp     dl,dh\r
+       jz      ERROR_base_and_dest_must_differ_with_writeback\r
+    .writeback_okay:\r
+       cmp     al,1\r
+       ja      .set_vector_reg\r
+       setz    cl\r
+       add     cl,ch                   ;cl=log register size\r
+       mov     edx,ecx\r
+       shl     edx,30\r
+       or      ebp,edx\r
+       jmp     .set_paramters\r
+    .set_vector_reg:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       or      ebp,1 shl 26\r
+       lea     ecx,[eax-2]             ;cl=log register size\r
+       mov     ebx,ecx\r
+       shl     ebx,30\r
+       setc    dl\r
+       mov     dh,0\r
+       or      ebp,ebx\r
+       shl     edx,23\r
+       or      ebp,edx\r
+       cmp     al,2                    ;b?\r
+       jnz     .set_paramters\r
+       mov     dl,ah\r
+       and     dl,0xe\r
+       cmp     dl,6\r
+       setz    dh\r
+       cmp     dl,10\r
+       setz    dl\r
+       or      dl,dh\r
+       shl     dx,12\r
+       or      bp,dx                   ;set S\r
+    .set_paramters:\r
+       cmp     ah,14\r
+       jae     .literal\r
+       cmp     ah,12\r
+       jae     .expression\r
+       cmp     ah,3\r
+       ja      .register\r
+    .indexed:\r
+       test    ah,1\r
+       jnz     .pre_post\r
+       ;offset\r
+       or      ebp,1 shl 24\r
+       mov     eax,ERROR_immediate_offset_out_of_range.0_0xfff.m256_255\r
+       mov     edx,ERROR_immediate_offset_out_of_range.0_0x1ffe.m256_255\r
+       mov     ebx,ERROR_immediate_offset_out_of_range.0_0x3ffc.m256_255\r
+       cmp     cl,1\r
+       cmovz   eax,edx\r
+       cmp     cl,2\r
+       cmovz   eax,ebx\r
+       mov     edx,ERROR_immediate_offset_out_of_range.0_0x7ff8.m256_255\r
+       mov     ebx,ERROR_immediate_offset_out_of_range.0_0xfff0.m256_255\r
+       cmp     cl,3\r
+       cmovz   eax,edx\r
+       cmova   eax,ebx\r
+       mov     ebx,[immediate_value]\r
+       or      edx,-1\r
+       shl     edx,cl\r
+       not     edx\r
+       test    ebx,edx\r
+       jnz     .try_unscaled\r
+       sar     ebx,cl\r
+       cmp     ebx,0xfff\r
+       ja      .try_unscaled\r
+       shl     ebx,10\r
+    .encode_imm:\r
+       or      ebp,ebx\r
+    .encode_rt:\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+    .expression:\r
+       sub     ah,10\r
+       jmp     .indexed\r
+    .try_unscaled:\r
+       xor     ebp,1 shl 24\r
+       mov     ecx,eax\r
+       xor     eax,eax\r
+       jmp     .pre_post.do\r
+    .pre_post:\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.m256_255\r
+    .pre_post.do:\r
+       and     eax,3 shl 8\r
+       shl     eax,10-8\r
+       xor     ebp,eax\r
+       mov     ebx,[immediate_value]\r
+       cmp     ebx,-0x100\r
+       jl      ARM_store_instruction_with_error\r
+       cmp     ebx,0xff\r
+       jg      ARM_store_instruction_with_error\r
+       and     ebx,0x1ff\r
+       shl     ebx,12\r
+       jmp     .encode_imm\r
+    .register:\r
+       or      ebp,1 shl 11 + 1 shl 21\r
+       movzx   edx,[instruction_shift_op]\r
+       xchg    ch,cl\r
+       mov     cl,3\r
+       mov     al,ah\r
+       and     al,3\r
+       cmovz   dx,cx                   ;set default to LSL\r
+       cmp     al,3                    ;LSL specified?\r
+       cmovz   dx,cx\r
+       mov     dh,0\r
+       xchg    ch,cl\r
+       test    dl,010b\r
+       jz      ERROR_extend_type\r
+       test    ah,8\r
+       jnz     .extend_reg_okay\r
+       test    dl,1\r
+       jnz     ERROR_parameter_n_not_valid.third       ;can't have w with [su]xtx\r
+    .extend_reg_okay:\r
+       mov     eax,[immediate_value]\r
+       test    eax,eax\r
+       jz      .extend_amount_okay\r
+       or      ebp,1 shl 12\r
+       cmp     cl,al\r
+       jz      .extend_amount_okay\r
+       mov     eax,ERROR_shift_value_out_of_range.0\r
+       mov     edx,ERROR_shift_value_out_of_range.0or1\r
+       mov     ebx,ERROR_shift_value_out_of_range.0or2\r
+       cmp     cl,1\r
+       cmovz   eax,edx\r
+       cmp     cl,2\r
+       cmovz   eax,ebx\r
+       mov     edx,ERROR_shift_value_out_of_range.0or3\r
+       mov     ebx,ERROR_shift_value_out_of_range.0or4\r
+       cmp     cl,3\r
+       cmovz   eax,edx\r
+       cmova   eax,ebx\r
+       mov     ecx,eax\r
+       jmp     ARM_store_instruction_with_error\r
+    .extend_amount_okay:\r
+       shl     edx,13\r
+       or      ebp,edx\r
+       jmp     .encode_rt\r
+    .literal:\r
+       cmp     [arm64_instruction],0x38000000  ;STR?\r
+       jz      ERROR_parameter_n_not_valid.second\r
+       and     ebp,not (7 shl 29 + 3 shl 22)\r
+       sub     cl,2\r
+       shl     ecx,30\r
+       or      ebp,ecx\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ecx,[addressing_space]\r
+       add     eax,[ecx+0]\r
+       adc     edx,[ecx+4]\r
+       sub     eax,edi\r
+       sbb     edx,0\r
+       test    eax,3\r
+       mov     ecx,ERROR_branch_misaligned\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     ebx,edx\r
+       cdq\r
+       cmp     ebx,edx\r
+       mov     ecx,ERROR_branch_too_far\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     eax,0xfffff\r
+       jg      ARM_store_instruction_with_error\r
+       cmp     eax,-0x100000\r
+       jl      ARM_store_instruction_with_error\r
+       and     eax,0x1ffffc\r
+       shl     eax,(5-2)\r
+       or      ebp,eax\r
+       jmp     .encode_rt\r
+\r
+ARM64_memory_byte_hword:\r
+       ;used by LDRB, LDRH, STRB, STRH\r
+       test    cl,1\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                       ; 0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                              ; 1=wt,[xn],imm\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                              ; 2=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\        ; 3=wt,[xn,imm]!\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                       ; 4=wt,[xn,wm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\           ; 5=wt,[xn,wm,extend]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\  ; 6=wt,[xn,wm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\     ; 7=wt,[xn,wm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                      ; 8=wt,[xn,xm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\          ; 9=wt,[xn,xm,extend]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;10=wt,[xn,xm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\    ;11=wt,[xn,xm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                        ;12=wt,[address]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                  ;13=wt,[address]!\r
+       <TMPL_never>,\  ;Note: the following template section is non standard to allow both Xt and Wt syntax            ;14=-\r
+       <TMPL_never>,\  ;they encode to the same instructions                                                           ;15=-\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                      ;16=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                             ;17=xt,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                             ;18=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ;19=xt,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                      ;20=xt,[xn,wm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\          ;21=xt,[xn,wm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;22=xt,[xn,wm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\    ;23=xt,[xn,wm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                     ;24=xt,[xn,xm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\         ;25=xt,[xn,xm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;26=xt,[xn,xm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\   ;27=xt,[xn,xm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                       ;28=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                   ;29=xt,[address]!\r
+       mov     edx,[arm64_instruction]\r
+       and     al,0xf                  ;X and W forms are the same instruction\r
+       test    dl,1\r
+       jnz     .byte_imm_done\r
+       mov     cl,al\r
+       and     cl,0xe\r
+       cmp     cl,6\r
+       setz    ch\r
+       cmp     cl,10\r
+       setz    cl\r
+       or      cl,ch\r
+       shl     cx,12\r
+       or      dx,cx                   ;set S\r
+    .byte_imm_done:\r
+       btr     edx,0\r
+       setc    ch                      ;set register offset for Wt\r
+       mov     [arm64_instruction],edx\r
+       jmp     ARM64_memory.do\r
+\r
+ARM64_memory_signed_byte_hword:\r
+       ;used by LDRSB, LDRSH\r
+       test    cl,1\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                      ; 0=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                             ; 1=xt,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                             ; 2=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ; 3=xt,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                      ; 4=xt,[xn,wm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\          ; 5=xt,[xn,wm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=xt,[xn,wm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\    ; 7=xt,[xn,wm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                     ; 8=xt,[xn,xm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\         ; 9=xt,[xn,xm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;10=xt,[xn,xm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\   ;11=xt,[xn,xm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                       ;12=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                 ;13=xt,[address]!\r
+       <TMPL_never>,\                                                                                                  ;14=-\r
+       <TMPL_never>,\                                                                                                  ;15=-\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                       ;16=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                              ;17=wt,[xn],imm\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                              ;18=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\        ;19=wt,[xn,imm]!\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                       ;20=wt,[xn,wm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\           ;21=wt,[xn,wm,extend]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\  ;22=wt,[xn,wm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\     ;23=wt,[xn,wm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                      ;24=wt,[xn,xm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\          ;25=wt,[xn,xm,extend]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ;26=wt,[xn,xm,extend imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\    ;27=wt,[xn,xm,lsl imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                        ;28=wt,[address]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>                    ;29=wt,[address]!\r
+       mov     edx,[arm64_instruction]\r
+       test    dl,1\r
+       jnz     .byte_imm_done\r
+       mov     cl,al\r
+       and     cl,0xe\r
+       cmp     cl,6\r
+       setz    ch\r
+       cmp     cl,10\r
+       setz    cl\r
+       or      cl,ch\r
+       shl     cx,12\r
+       or      dx,cx                   ;set S\r
+    .byte_imm_done:\r
+       btr     edx,0\r
+       setc    ch                      ;set register offset for Wt/Xt\r
+       mov     [arm64_instruction],edx\r
+       cmp     al,15\r
+       jbe     ARM64_memory.do\r
+       sub     al,16\r
+       or      edx,1 shl 22\r
+       mov     [arm64_instruction],edx\r
+       jmp     ARM64_memory.do\r
+\r
+ARM64_memory_signed_word:\r
+       ;used by LDRSW\r
+       mov     [operand_size],4\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                      ; 0=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm>,\                             ; 1=xt,[xn],imm\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                             ; 2=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right,TMPL_modifier_exclaim>,\       ; 3=xt,[xn,imm]!\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                      ; 4=xt,[xn,wm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\          ; 5=xt,[xn,wm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\ ; 6=xt,[xn,wm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\    ; 7=xt,[xn,wm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                     ; 8=xt,[xn,xm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\         ; 9=xt,[xn,xm,extend]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\;10=xt,[xn,xm,extend imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\   ;11=xt,[xn,xm,lsl imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                       ;12=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right,TMPL_modifier_exclaim>,\                 ;13=xt,[address]!\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                        ;14=xt,[address]\r
+       <TMPL_dword_z_reg,TMPL_address64>                                                                               ;15=xt,address\r
+       cmp     al,13\r
+       jbe     ARM64_memory.decode\r
+       mov     ch,4                    ;set literal size for Xt\r
+       jmp     ARM64_memory.do\r
+\r
+ARM64_memory_unprivileged:\r
+       ;used by LDTR, STTR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\           ;0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\  ;1=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\            ;2=wt,[address]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\          ;3=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ;4=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>             ;5=xt,[address]\r
+    .decode_v8:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+    .decode:\r
+       mov     ebp,[arm64_instruction]\r
+       mov     cl,3\r
+       xor     ah,ah\r
+       div     cl\r
+       mov     ah,1\r
+       mov     ch,2                    ;set register offset for Wt and Xt\r
+       jmp     ARM64_memory.writeback_okay\r
+\r
+ARM64_memory_unscaled:\r
+       ;used by LDUR, STUR\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\           ; 0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\  ; 1=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\            ; 2=wt,[address]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\          ; 3=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\ ; 4=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\           ; 5=xt,[address]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\            ; 6=bt,[xn]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\   ; 7=bt,[xn,imm]\r
+       <TMPL_vect_breg,TMPL_size_1,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\             ; 8=bt,[address]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\            ; 9=ht,[xn]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\   ;10=ht,[xn,imm]\r
+       <TMPL_vect_hreg,TMPL_size_2,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\             ;11=ht,[address]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\            ;12=st,[xn]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\   ;13=st,[xn,imm]\r
+       <TMPL_vect_sreg,TMPL_size_4,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\             ;14=st,[address]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\            ;15=dt,[xn]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\   ;16=dt,[xn,imm]\r
+       <TMPL_vect_dreg,TMPL_size_8,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\             ;17=dt,[address]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\           ;18=qt,[xn]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\  ;19=qt,[xn,imm]\r
+       <TMPL_vect_qreg,TMPL_size_16,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>              ;20=qt,[address]\r
+       cmp     al,6\r
+       jb      ARM64_memory_unprivileged.decode_v8\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       jmp     ARM64_memory_unprivileged.decode\r
+\r
+ARM64_memory_unprivileged_byte_hword:\r
+       ;used by LDTRB, LDTRH, LDURB, LDURH, STTRB, STTRH, STURB, STURH\r
+       test    cl,1\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\               ;0=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\      ;1=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                  ;2=wt,[address]\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       btr     ebp,0\r
+       setc    ch                      ;set register offset for Wt\r
+       mov     ax,0x100\r
+       jmp     ARM64_memory.writeback_okay\r
+\r
+ARM64_memory_unprivileged_signed_byte_hword:\r
+       ;used by LDTRSB, LDTRSH, LDURSB, LDURSH\r
+       test    cl,1\r
+       setnz   dl\r
+       add     dl,1\r
+       mov     [operand_size],dl\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\              ;0=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\     ;1=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\               ;2=xt,[address]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\               ;3=wt,[xn]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\      ;4=wt,[xn,imm]\r
+       <TMPL_word_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                  ;5=wt,[address]\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       btr     ebp,0\r
+       setc    ch                      ;set register offset for Wt/Xt\r
+       cmp     al,3\r
+       setae   al\r
+       movzx   eax,al\r
+       shl     eax,22\r
+       or      ebp,eax\r
+       mov     ax,0x100\r
+       jmp     ARM64_memory.writeback_okay\r
+\r
+ARM64_memory_unprivileged_signed_word:\r
+       ;used by LDTRSW, LDURSW\r
+       mov     [operand_size],4\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\              ;0=xt,[xn]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\     ;1=xt,[xn,imm]\r
+       <TMPL_dword_z_reg,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>                 ;2=xt,[address]\r
+       jmp     ARM64_memory_unprivileged.decode_v8\r
+\r
+ARM64_mov_aliases:\r
+       ;used by MOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_sp_reg,TMPL_word_s_reg>,\            ; 0=wd,wn\r
+       <TMPL_word_sp_reg,TMPL_imm>,\                   ; 1=wd,imm\r
+       <TMPL_word_zr_reg,TMPL_word_z_reg>,\            ; 2=wd,wn\r
+       <TMPL_word_zr_reg,TMPL_imm>,\                   ; 3=wd,imm\r
+       <TMPL_word_zr_reg,TMPL_vect_element_s>,\        ; 4=wd,vn.s[]\r
+       <TMPL_word_gen_reg,TMPL_word_sp_reg>,\          ; 5=wd,wn\r
+       <TMPL_word_gen_reg,TMPL_word_zr_reg>,\          ; 6=wd,wn\r
+       <TMPL_word_gen_reg,TMPL_word_gen_reg>,\         ; 7=wd,wn\r
+       <TMPL_word_gen_reg,TMPL_imm>,\                  ; 8=wd,imm\r
+       <TMPL_word_gen_reg,TMPL_vect_element_s>,\       ; 9=wd,vn.s[]\r
+       <TMPL_dword_sp_reg,TMPL_dword_s_reg>,\          ;10=xd,xn\r
+       <TMPL_dword_sp_reg,TMPL_imm64>,\                ;11=xd,imm\r
+       <TMPL_dword_zr_reg,TMPL_dword_z_reg>,\          ;12=xd,xn\r
+       <TMPL_dword_zr_reg,TMPL_imm64>,\                ;13=xd,imm\r
+       <TMPL_dword_zr_reg,TMPL_vect_element_d>,\       ;14=xd,vn.d[]\r
+       <TMPL_dword_gen_reg,TMPL_dword_sp_reg>,\        ;15=xd,wn\r
+       <TMPL_dword_gen_reg,TMPL_dword_zr_reg>,\        ;16=xd,wn\r
+       <TMPL_dword_gen_reg,TMPL_dword_gen_reg>,\       ;17=xd,wn\r
+       <TMPL_dword_gen_reg,TMPL_imm64>,\               ;18=xd,imm\r
+       <TMPL_dword_gen_reg,TMPL_vect_element_d>,\      ;19=xd,vn.d[]\r
+       <TMPL_vect_breg,TMPL_vect_element_b>,\          ;20=bd,vn.b[]\r
+       <TMPL_vect_hreg,TMPL_vect_element_h>,\          ;21=hd,vn.h[]\r
+       <TMPL_vect_sreg,TMPL_vect_element_s>,\          ;22=sd,vn.s[]\r
+       <TMPL_vect_dreg,TMPL_vect_element_d>,\          ;23=dd,vn.d[]\r
+       <TMPL_vect_element_b,TMPL_vect_element_b>,\     ;24=vd.b[],vn.b[]\r
+       <TMPL_vect_element_b,TMPL_word_z_reg>,\         ;25=vd.b[],wn\r
+       <TMPL_vect_element_h,TMPL_vect_element_h>,\     ;26=vd.h[],vn.h[]\r
+       <TMPL_vect_element_h,TMPL_word_z_reg>,\         ;27=vd.h[],wn\r
+       <TMPL_vect_element_s,TMPL_vect_element_s>,\     ;28=vd.s[],vn.s[]\r
+       <TMPL_vect_element_s,TMPL_word_z_reg>,\         ;29=vd.s[],wn\r
+       <TMPL_vect_element_d,TMPL_vect_element_d>,\     ;30=vd.d[],vn.d[]\r
+       <TMPL_vect_element_d,TMPL_dword_z_reg>,\        ;31=vd.d[],xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\                 ;32=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>                 ;33=vd,vn\r
+    .encode:\r
+       cmp     al,20\r
+       jae     .vector\r
+       cmp     al,10\r
+       setae   cl\r
+       shl     ecx,31\r
+       mov     ebp,ecx\r
+       sets    cl\r
+       neg     cl\r
+       and     cl,10\r
+       sub     al,cl\r
+       cmp     al,4\r
+       jz      .gen_vect\r
+       cmp     al,9\r
+       jz      .gen_vect\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       cmp     al,0\r
+       jz      .reg_sp\r
+       cmp     al,1\r
+       jz      .imm_sp\r
+       cmp     al,3\r
+       jz      .imm_gen\r
+       cmp     al,8\r
+       jz      .imm_gen\r
+       cmp     al,5\r
+       jz      .reg_sp\r
+    .reg_gen:\r
+       mov     cl,[operand_register1]\r
+       mov     [operand_register2],cl\r
+       or      ebp,0x2a0003e0\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .reg_sp:\r
+       or      ebp,0x11000000\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .imm_gen:\r
+       or      ebp,0x52800000\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+    .try_wide_immediate:\r
+       mov     cl,0\r
+       test    ebp,ebp\r
+       js      .check_wide_loop\r
+       xor     edx,edx\r
+    .check_wide_loop:\r
+       test    edx,edx\r
+       setz    bh\r
+       test    eax,0xffff0000\r
+       setz    bl\r
+       and     bl,bh\r
+       jnz     .put_wide_immediate\r
+       mov     ebx,eax\r
+       shrd    eax,edx,16\r
+       shrd    edx,ebx,16\r
+       inc     cl\r
+       cmp     cl,4\r
+       jb      .check_wide_loop\r
+       not     edx\r
+       not     eax\r
+       btr     ebp,30                          ;try inverted\r
+       jc      .try_wide_immediate\r
+       cmp     [operand_register0],0x1f        ;ZR?\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jz      ARM_store_instruction_with_error\r
+       and     ebp,1 shl 31\r
+    .imm_sp:\r
+       or      ebp,0x320003e0\r
+       js      .immediate_prepared\r
+       mov     eax,[immediate_value]\r
+       mov     [immediate_value_high],eax\r
+    .immediate_prepared:\r
+       call    ARM64_encode_bitmask\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jc      ARM_store_instruction_with_error\r
+       mov     edx,eax\r
+       jmp     ARM64_arithmetic1.encode_immediate\r
+    .put_wide_immediate:\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       movzx   ecx,cl\r
+       shl     ecx,21\r
+       or      ebp,ecx\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .gen_vect:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       shr     ebp,1                           ;set Q\r
+       setnz   cl\r
+       add     cl,18\r
+       or      ebp,0x0e003c00\r
+       mov     eax,[immediate_value2]\r
+    .encode_imm5:\r
+       add     eax,eax\r
+       inc     eax\r
+       shl     eax,cl\r
+       or      ebp,eax\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       cmp     al,24\r
+       jb      .scalar\r
+       cmp     al,32\r
+       jae     .vect_vect\r
+       shr     al,1\r
+       jc      .vect_gen\r
+       ;vector element to vector element\r
+       lea     ecx,[eax-12+11]\r
+       mov     eax,[immediate_value2]\r
+       shl     eax,cl\r
+       lea     ebp,[eax+0x6e000400]\r
+       add     cl,5\r
+       mov     eax,[immediate_value]\r
+       jmp     .encode_imm5\r
+    .scalar:\r
+       lea     ecx,[eax-20+16]\r
+       mov     ebp,0x5e000400\r
+       mov     eax,[immediate_value2]\r
+       jmp     .encode_imm5\r
+    .vect_vect:\r
+       shr     al,1\r
+       setc    al\r
+       shl     eax,30\r
+       lea     ebp,[eax+0x0ea01c00]\r
+       mov     al,[operand_register1]\r
+       mov     [operand_register2],al\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .vect_gen:\r
+       lea     ecx,[eax-12+16]\r
+       mov     ebp,0x4e001c00\r
+       mov     eax,[immediate_value]\r
+       jmp     .encode_imm5\r
+\r
+ARM64_mov_wide:\r
+       ;used by MOVK, MOVN, MOVZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_imm64>,\                                  ;0=wd,imm\r
+       <TMPL_word_z_reg,TMPL_imm64,TMPL_comma,TMPL_lsl,TMPL_imm2>,\    ;1=wd,imm,lsl imm\r
+       <TMPL_dword_z_reg,TMPL_imm64>,\                                 ;2=xd,imm\r
+       <TMPL_dword_z_reg,TMPL_imm64,TMPL_comma,TMPL_lsl,TMPL_imm2>     ;3=xd,imm,lsl imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]\r
+       shr     al,1\r
+       shl     eax,31\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ebx,eax\r
+       or      ebx,edx\r
+       jz      .check_immediate_zero\r
+       mov     ecx,[immediate_value2]\r
+       cmp     ecx,64\r
+       jae     .out_of_range\r
+       cmp     ecx,32\r
+       jb      .do_shift\r
+       mov     edx,eax\r
+       xor     eax,eax\r
+       sub     ecx,32\r
+    .do_shift:\r
+       xor     ebx,ebx\r
+       shld    ebx,edx,cl\r
+       test    ebx,ebx\r
+       jnz     .out_of_range\r
+       shld    edx,eax,cl\r
+       test    edx,edx\r
+       jz      .imm32_okay\r
+       test    ebp,ebp\r
+       jns     .out_of_range\r
+    .imm32_okay:\r
+       shl     eax,cl\r
+    .check_immediate:\r
+       test    edx,edx\r
+       jnz     .try_next_shift\r
+       test    eax,0xffff0000\r
+       jz      .immediate_okay\r
+    .try_next_shift:\r
+       test    eax,0xffff\r
+       jnz     .out_of_range\r
+       shrd    eax,edx,16\r
+       shr     edx,16\r
+       inc     bl\r
+       cmp     bl,4\r
+       jb      .check_immediate\r
+       jmp     .out_of_range\r
+    .check_immediate_zero:\r
+       mov     ebx,[immediate_value2]\r
+       bt      ebp,29                  ;MOVK?\r
+       jnc     .scale_shift\r
+       ;for MOVK we have to honour the shift value\r
+    .encode_shift:\r
+       test    ebx,not 3 shl 4\r
+       jnz     .out_of_range\r
+    .scale_shift:\r
+       ;otherwise use floor(value/16)\r
+       shr     ebx,4\r
+    .immediate_okay:\r
+       shl     ebx,21\r
+       shl     eax,5\r
+       or      ebp,ebx\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+    .out_of_range:\r
+       test    ebp,ebp\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xffff_lsl_16\r
+       mov     edx,ERROR_immediate_value_out_of_range.0_0xffff_lsl_48\r
+       cmovs   ecx,edx\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_arithmetic6:\r
+       ;used by MUL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\     ; 0=wd,wn,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_dword_z_reg>,\  ; 1=xd,xn,xm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ; 2=vd,vn,vm\r
+       <TMPL_never>,\                                          ; 3\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ; 4=vd,vn,vm\r
+       <TMPL_never>,\                                          ; 5\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ; 6=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\     ; 7=vd,vn,vm.h[]\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ; 8=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\     ; 9=vd,vn,vm.h[]\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;10=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\     ;11=vd,vn,vm.s[]\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;12=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>       ;13=vd,vn,vm.s[]\r
+       cmp     al,1\r
+       ja      .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       shl     eax,31\r
+       lea     ebp,[eax+0x1b007c00]\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       sub     al,2\r
+       mov     ebp,0x0e209c00          ;vector\r
+       mov     ebx,0x0f008000          ;element\r
+    .vector_encode:\r
+       shr     al,1\r
+       setc    dl                      ;element flag\r
+       shr     al,1\r
+       setc    cl                      ;Q\r
+       shl     ecx,30\r
+       movzx   eax,al                  ;size\r
+       shl     eax,22\r
+       or      ecx,eax\r
+       test    dl,dl\r
+       jnz     .element\r
+       or      ebp,ecx\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+    .element:\r
+       lea     ebp,[ecx+ebx]\r
+       mov     edx,[immediate_value2]\r
+       shr     eax,22-4\r
+       cmp     al,[operand_register2]\r
+       jbe     ERROR_vector_register_out_of_range\r
+       mov     cl,al\r
+       shr     cl,5\r
+       shl     edx,cl\r
+       mov     eax,edx\r
+       mov     ecx,edx\r
+       and     edx,100b\r
+       and     eax,011b\r
+       shl     edx,11-2                ;H\r
+       shl     eax,20-0                ;L:M\r
+       or      ebp,edx\r
+       or      ebp,eax\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+\r
+ARM64_arithmetic7:\r
+       ;used by MVN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\                             ;0=wd,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\      ;1=wd,wm,shift imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\                           ;2=xd,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\    ;3=xd,xm,shift imm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\                                 ;4=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>                                 ;5=vd,vn\r
+       cmp     al,4\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       shr     al,2\r
+       setc    al\r
+       shl     eax,31\r
+       lea     ebp,[eax+0x2a2003e0]\r
+       mov     al,[operand_register1]\r
+       mov     [operand_register2],al\r
+       jmp     ARM64_arithmetic1.encode_shifted_register\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       shl     eax,31\r
+       shr     eax,1\r
+       lea     ebp,[eax+0x2e205800]\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+\r
+ARM64_arithmetic8:\r
+       ;used by NEG, NEGS\r
+       bt      ecx,29\r
+       jnc     .non_S\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\                             ;0=wd,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\     ;1=wd,wm,shift imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\                           ;2=xd,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>     ;3=xd,xm,shift imm\r
+       jmp     .encode\r
+    .non_S:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\                             ; 0=wd,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op3,TMPL_imm>,\     ; 1=wd,wm,shift imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\                           ; 2=xd,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op3,TMPL_imm>,\   ; 3=xd,xm,shift imm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\                                 ; 4=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\                               ; 5=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\                                 ; 6=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>,\                                 ; 7=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\                                 ; 8=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\                                 ; 9=vd,vn\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\                               ;10=dd,dn\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>                                   ;11=vd,vn\r
+    .encode:\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,4\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     dl,[operand_register1]\r
+       mov     [operand_register2],dl\r
+       cmp     al,2\r
+       setae   cl\r
+       add     al,cl\r
+       jmp     ARM64_arithmetic2.encode\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,0x2e20b800\r
+       sub     al,4\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_arithmetic9:\r
+       ;used by NGC, NGCS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>     ;1=xd,xm\r
+       mov     dl,[operand_register1]\r
+       mov     [operand_register2],dl\r
+       jmp     ARM64_dz_nz_mz.encode\r
+\r
+ARM64_prefetch:\r
+       ;used by PRFM\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                          ; 0=op,[xn]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\                                                  ; 1\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                 ; 2=op,[xn,imm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\                                                  ; 3\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                          ; 4=op,[xn,wm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\              ; 5=op,[xn,wm,extend]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\     ; 6=op,[xn,wm,extend imm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\        ; 7=op,[xn,wm,lsl imm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                         ; 8=op,[xn,xm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\             ; 9=op,[xn,xm,extend]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\    ;10=op,[xn,xm,extend imm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\       ;11=op,[xn,xm,lsl imm]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                           ;12=op,[address]\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_never>,\                                                                   ;13=\r
+       <TMPL_imm2,TMPL_comma,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                            ;14=op,[address]\r
+       <TMPL_imm2,TMPL_comma,TMPL_address64>,\                                                                                 ;15=op,address\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                                                   ;16=op,[xn]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\                                                           ;17\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_imm,TMPL_bracket_right>,\                                          ;18=op,[xn,imm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_never>,\                                                           ;19\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_bracket_right>,\                                   ;20=op,[xn,wm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_bracket_right>,\                       ;21=op,[xn,wm,extend]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\              ;22=op,[xn,wm,extend imm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_word_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\                 ;23=op,[xn,wm,lsl imm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_bracket_right>,\                                  ;24=op,[xn,xm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_bracket_right>,\                      ;25=op,[xn,xm,extend]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_extend,TMPL_imm,TMPL_bracket_right>,\             ;26=op,[xn,xm,extend imm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_dword_z_reg,TMPL_lsl,TMPL_imm,TMPL_bracket_right>,\                ;27=op,[xn,xm,lsl imm]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_expression,TMPL_bracket_right>,\                                                    ;28=op,[address]\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_never>,\                                                                            ;29=\r
+       <TMPL_prf_op,TMPL_bracket_left,TMPL_address64,TMPL_bracket_right>,\                                                     ;30=op,[address]\r
+       <TMPL_prf_op,TMPL_address64>                                                                                            ;31=op,address\r
+       cmp     al,16\r
+       jae     .check_literal\r
+       mov     edx,[operand_registers]\r
+       mov     ecx,[immediate_value2]\r
+       shl     edx,8\r
+       mov     dl,cl\r
+       mov     [operand_registers],edx\r
+       cmp     ecx,0x1f\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_31\r
+       ja      ARM_store_instruction_with_error\r
+       add     al,16\r
+    .check_literal:\r
+       cmp     al,30\r
+       jb      ARM64_memory.decode\r
+       mov     ch,4                    ;set literal size for Xt\r
+       jmp     ARM64_memory.do\r
+\r
+ARM64_arithmetic10:\r
+       ;used by RBIT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\   ;1=xd,xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;2=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>         ;3=vd,vn\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,2\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       and     al,1\r
+       shl     eax,30                                  ;set Q\r
+       lea     ebp,[eax+0x2e605800]\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+ARM64_ret:\r
+       ;used by RET\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_EOL>,\            ;0=empty\r
+       <TMPL_dword_z_reg>      ;1=xn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,[operand_register0]\r
+       mov     ecx,30\r
+       cmp     al,1\r
+       cmovnz  eax,ecx\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_arithmetic11:\r
+       ;used by REV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>     ;1=xd,xm\r
+       movzx   ecx,al\r
+       shl     ecx,10\r
+       or      [arm64_instruction],ecx\r
+       jmp     ARM64_dz_nz_mz.encode\r
+\r
+ARM64_arithmetic12:\r
+       ;used by REV16\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\     ;0=wd,wn\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\   ;1=xd,xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;2=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>         ;3=vd,vn\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,2\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       shl     eax,31\r
+       or      ebp,eax                                 ;set sf\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       and     al,1\r
+       shl     eax,30                                  ;set Q\r
+       lea     ebp,[eax+0x0e201800]\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+ARM64_arithmetic13:\r
+       ;used by REV32\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\   ;1=xd,xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;2=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\       ;3=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\         ;4=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>           ;5=vd,vn\r
+       mov     ebx,0x2e200800\r
+    .do:\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,1\r
+       jae     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,ebx\r
+       dec     al\r
+       shr     al,1\r
+       setc    cl\r
+       shl     ecx,30                                  ;set Q\r
+       mov     ah,0\r
+       shl     eax,22                                  ;set size\r
+       or      ebp,ecx\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+ARM64_arithmetic14:\r
+       ;used by REV64\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\   ;1=xd,xn\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;2=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\       ;3=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\         ;4=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>,\         ;5=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;6=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>           ;7=vd,vn\r
+       mov     ebx,0x0e200800\r
+       jmp     ARM64_arithmetic13.do\r
+\r
+ARM64_arithmetic15:\r
+       ;used by SMULL, UMULL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_word_z_reg,TMPL_word_z_reg>,\    ;0=xd,wn,wm\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\           ;1=vd,vn,vm\r
+       <TMPL_never>,\                                          ;2\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;3=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\     ;4=vd,vn,vm.h[]\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;5=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s>       ;6=vd,vn,vm.s[]\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       dec     al\r
+       jns     .vector\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       jmp     ARM64_dz_nz_mz_az.encode\r
+    .vector:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       shr     al,1\r
+       lea     eax,[eax+eax]\r
+       rcl     al,1\r
+       and     ebp,1 shl 23            ;isolate U\r
+       shl     ebp,29-23\r
+       lea     ebx,[ebp+0x0f00a000]    ;element\r
+       or      ebp,0x0e20c000          ;vector\r
+       jmp     ARM64_arithmetic6.vector_encode\r
+\r
+ARM64_sys:\r
+       ;used by SYS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2>,\                   ;0=op1,crn,crm,op2\r
+       <TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2,TMPL_dword_z_reg>    ;1=op1,crn,crm,op2,xt\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       dec     al\r
+       and     al,0x1f                                 ;default register\r
+       or      al,[operand_register2]\r
+       movzx   eax,al\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode1]\r
+       cmp     eax,7\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       ja      ARM_store_instruction_with_error\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode2]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_sysl:\r
+       ;used by SYSL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_dword_z_reg,TMPL_copro_opcode1,TMPL_cpro_reg,TMPL_cpro_reg,TMPL_copro_opcode2>    ;0=xt,op1,crn,crm,op2\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode1]\r
+       cmp     eax,7\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       ja      ARM_store_instruction_with_error\r
+       shl     eax,16\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register1]\r
+       shl     eax,12\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register2]\r
+       shl     eax,8\r
+       or      ebp,eax\r
+       movzx   eax,[copro_opcode2]\r
+       shl     eax,5\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_tb:\r
+       ;used by TBNZ\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_imm2,TMPL_comma,TMPL_address64>,\ ;0=wt,imm,address\r
+       <TMPL_dword_z_reg,TMPL_imm2,TMPL_comma,TMPL_address64>  ;1=xt,imm,address\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_V8 shr 32\r
+       jz      ERROR_requires_cpu64_capability_v8\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       test    al,al\r
+       mov     ecx,ERROR_bit_out_of_range.0_63\r
+       mov     edx,ERROR_bit_out_of_range.0_31\r
+       cmovz   ecx,edx\r
+       mov     eax,1 shl 6\r
+       mov     edx,1 shl 5\r
+       cmovz   eax,edx\r
+       cmp     eax,[immediate_value2]\r
+       jbe     ARM_store_instruction_with_error\r
+       mov     eax,[immediate_value2]\r
+       mov     ecx,eax\r
+       and     eax,0x1f\r
+       shl     eax,19\r
+       or      ebp,eax\r
+       and     ecx,0x20\r
+       shl     ecx,31-5\r
+       or      ebp,ecx\r
+       mov     eax,[immediate_value]\r
+       mov     edx,[immediate_value_high]\r
+       mov     ecx,[addressing_space]\r
+       add     eax,[ecx+0]\r
+       adc     edx,[ecx+4]\r
+       sub     eax,edi\r
+       sbb     edx,0\r
+       test    eax,3\r
+       mov     ecx,ERROR_branch_misaligned\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     ecx,edx\r
+       cdq\r
+       cmp     ecx,edx\r
+       mov     ecx,ERROR_branch_too_far\r
+       jnz     ARM_store_instruction_with_error\r
+       cmp     eax,0x7fff\r
+       jg      ARM_store_instruction_with_error\r
+       cmp     eax,-0x8000\r
+       jl      ARM_store_instruction_with_error\r
+       and     eax,0xfffc\r
+       shl     eax,5-2\r
+       or      ebp,eax\r
+       movzx   eax,[operand_register0]\r
+       or      ebp,eax\r
+       jmp     ARM64_store_instruction\r
+\r
+ARM64_arithmetic16:\r
+       ;used by TST\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_word_z_reg>,\                             ;0=wn,wm\r
+       <TMPL_word_z_reg,TMPL_word_z_reg,TMPL_shift_op,TMPL_imm>,\      ;1=wn,wm,shift imm\r
+       <TMPL_word_z_reg,TMPL_imm>,\                                    ;2=wn,imm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg>,\                           ;3=xn,xm\r
+       <TMPL_dword_z_reg,TMPL_dword_z_reg,TMPL_shift_op,TMPL_imm>,\    ;4=xn,xm,shift imm\r
+       <TMPL_dword_z_reg,TMPL_imm64>                                   ;5=xn,imm\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       or      ecx,0x1f\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM64_arithmetic2.encode\r
+\r
+ARM64_vector_scalar_bhsd_two_reg:\r
+       ;used by ABS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ;0=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\       ;1=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\         ;2=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>,\         ;3=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;4=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\         ;5=vd,vn\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\       ;6=dd,dn\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>           ;7=vd,vn\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_vector_narrow_low:\r
+       ;used by ADDHN, RADDHN, RSUBHN, SUBHN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_vect_v2d>             ;2=vd,vn,vm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     ah,0\r
+       shl     eax,22\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_narrow_high:\r
+       ;used by ADDHN2, RADDHN2, RSUBHN2, SUBHN2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v16b,TMPL_vect_v8h,TMPL_vect_v8h>,\          ;0=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v2d,TMPL_vect_v2d>             ;2=vd,vn,vm\r
+       jmp     ARM64_vector_narrow_low.encode\r
+\r
+ARM64_vector_narrow_3reg_scalar_2reg:\r
+       ;used by ADDP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ;1=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;3=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;4=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;5=vd,vn,vm\r
+       <TMPL_vect_dreg,TMPL_vect_v2d>,\                        ;6=dn,vn\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>             ;7=vd,vn,vm\r
+       cmp     al,6\r
+       jnz     ARM64_vector_scalar_bhsd_two_reg.encode\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       xor     ebp,0x50110400\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_vector_reduce_bhs:\r
+       ;used by ADDV, SMAXV, SMINV, UMAXV, UMINV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_breg,TMPL_vect_v8b>,\        ;0=vd,vn\r
+       <TMPL_vect_breg,TMPL_vect_v16b>,\       ;1=vd,vn\r
+       <TMPL_vect_hreg,TMPL_vect_v4h>,\        ;2=vd,vn\r
+       <TMPL_vect_hreg,TMPL_vect_v8h>,\        ;3=vd,vn\r
+       <TMPL_never>,\                          ;4=-\r
+       <TMPL_vect_sreg,TMPL_vect_v4s>          ;5=vd,vn\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_crypto_two_reg:\r
+       ;used by AESD, AESE, AESIMC, AESMC\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v16b,TMPL_vect_v16b> ;0=vd,vn\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_CRYPTO shr 32\r
+       jz      ERROR_requires_cpu64_capability_crypto\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_scalar_b_three_reg:\r
+       ;used by BIF, BIT, BSL, PMUL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\   ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>  ;1=vd,vn,vm\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_scalar_bhsd_three_reg_zero:\r
+       ;used by CMEQ, CMGE, CMGT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\   ; 0=vd,vn,vm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\        ; 1=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\; 2=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\      ; 3=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\   ; 4=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\        ; 5=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\   ; 6=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\        ; 7=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ; 8=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ; 9=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\   ;10=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\        ;11=vd,vn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;12=dd,dn,dm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;13=dd,dn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\   ;14=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>          ;15=vd,vn,imm\r
+       shr     al,1\r
+       jnc     ARM64_vector_scalar_bhsd_two_reg.encode\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     ARM_store_instruction_with_error\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ebx,1 shl 29 + 0x05 shl 10              ;eq\r
+       mov     edx,0 shl 29 + 0x2f shl 10              ;gt\r
+       mov     ecx,1 shl 29 + 0x2d shl 10              ;eq\r
+       test    ebp,1 shl 11\r
+       cmovz   ecx,edx\r
+       test    ebp,1 shl 13                            ;cmeq?\r
+       cmovz   ecx,ebx\r
+       xor     ebp,ecx\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_vector_scalar_bhsd_three_reg:\r
+       ;used by CMHI, CMHS, CMTST, SRSHL, SSHL, URSHL, USHL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\   ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\;1=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\   ;2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\   ;3=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ;4=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\   ;5=vd,vn,vm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;6=dd,dn,dm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>     ;7=vd,vn,vm\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_scalar_bhsd_two_reg_zero:\r
+       ;used by CMLE, CMLT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\      ;1=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\        ;2=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\        ;3=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;4=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\        ;5=vd,vn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;6=dd,dn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>          ;7=vd,vn,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     ARM_store_instruction_with_error\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_b_two_reg:\r
+       ;used by CNT, NOT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\                 ;0=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>                 ;1=vd,vn\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_dup:\r
+       ;used by DUP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_breg,TMPL_vect_element_b>,\          ; 0=bd,vn.b[]\r
+       <TMPL_vect_hreg,TMPL_vect_element_h>,\          ; 1=hd,vn.h[]\r
+       <TMPL_vect_sreg,TMPL_vect_element_s>,\          ; 2=sd,vn.s[]\r
+       <TMPL_vect_dreg,TMPL_vect_element_d>,\          ; 3=dd,vn.d[]\r
+       <TMPL_vect_v8b,TMPL_vect_element_b>,\           ; 4=bd,vn.b[]\r
+       <TMPL_vect_v8b,TMPL_word_z_reg>,\               ; 5=bd,wn\r
+       <TMPL_vect_v16b,TMPL_vect_element_b>,\          ; 6=bd,vn.b[]\r
+       <TMPL_vect_v16b,TMPL_word_z_reg>,\              ; 7=bd,wn\r
+       <TMPL_vect_v4h,TMPL_vect_element_h>,\           ; 8=hd,vn.h[]\r
+       <TMPL_vect_v4h,TMPL_word_z_reg>,\               ; 9=hd,wn\r
+       <TMPL_vect_v8h,TMPL_vect_element_h>,\           ;10=hd,vn.h[]\r
+       <TMPL_vect_v8h,TMPL_word_z_reg>,\               ;11=hd,wn\r
+       <TMPL_vect_v2s,TMPL_vect_element_s>,\           ;12=sd,vn.s[]\r
+       <TMPL_vect_v2s,TMPL_word_z_reg>,\               ;13=sd,wn\r
+       <TMPL_vect_v4s,TMPL_vect_element_s>,\           ;14=sd,vn.s[]\r
+       <TMPL_vect_v4s,TMPL_word_z_reg>,\               ;15=sd,wn\r
+       <TMPL_never>,\                                  ;16=-\r
+       <TMPL_never>,\                                  ;17=-\r
+       <TMPL_vect_v2d,TMPL_vect_element_d>,\           ;18=dd,vn.d[]\r
+       <TMPL_vect_v2d,TMPL_dword_z_reg>                ;19=dd,xn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       sub     al,4\r
+       jae     .reg_element\r
+       lea     ecx,[eax+4+16]\r
+       mov     ebp,0x5e000400\r
+       mov     eax,[immediate_value2]\r
+       jmp     ARM64_mov_aliases.encode_imm5\r
+    .reg_element:\r
+       mov     ebp,0x0e000400\r
+       shr     al,1\r
+       setc    dl\r
+       movzx   edx,dl\r
+       shl     edx,11\r
+       or      ebp,edx\r
+       shr     al,1\r
+       lea     ecx,[eax+16]\r
+       setc    al\r
+       shl     eax,30\r
+       or      ebp,eax\r
+       mov     eax,[immediate_value2]\r
+       jmp     ARM64_mov_aliases.encode_imm5\r
+\r
+ARM64_vector_b_three_reg_imm:\r
+       ;used by EXT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\  ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm> ;1=vd,vn,vm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_7\r
+       mov     ebx,ERROR_immediate_value_out_of_range.0_15\r
+       test    al,al\r
+       cmovnz  ecx,ebx\r
+       setnz   bl\r
+       movzx   ebx,bl\r
+       lea     ebx,[ebx*8+8]\r
+       cmp     edx,ebx\r
+       jae     ARM_store_instruction_with_error\r
+       shl     edx,11\r
+       or      ebp,edx\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+\r
+ARM64_vector_scalar_sd_three_reg:\r
+       ;used by FABD, FACGE, FACGT, FADD, FDIV, FMAX, FMAXNM, FMIN, FMINNM, FRECPS, FRSQRTS, FSUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm     sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;1=dd,dn,dm     sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ;2=vd,vn,vm     sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\   ;3=vd,vn,vm     sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>     ;4=vd,vn,vm     sz=0 q=1\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       cmp     al,2\r
+       cmovb   ebp,[arm64_instruction]         ;recover the scalar template\r
+       cmovae  ebp,[arm64_instruction2]        ;recover the vector template\r
+       cmp     al,3\r
+       setae   cl\r
+       and     eax,1\r
+       shl     eax,22\r
+       or      ebp,eax                                 ;set sz\r
+       shl     ecx,30\r
+       or      ebp,ecx                                 ;set Q\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_scalar_sd_two_reg:\r
+       ;used by FABS, FNEG, FRECPE, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, FRINTZ, FRSQRTE, FSQRT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\       ;0=sd,sn        sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\       ;1=dd,dn        sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;2=vd,vn        sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>,\         ;3=vd,vn        sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>           ;4=vd,vn        sz=0 q=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_scalar_sd_pairs:\r
+       ;used by FADDP, FMAXNMP, FMAXP, FMINNMP, FMINP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_v2s>,\                ;0=sd,vn        sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_v2d>,\                ;1=dd,vn        sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ;2=vd,vn,vm     sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\   ;3=vd,vn,vm     sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>     ;4=vd,vn,vm     sz=0 q=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_conditional_compare_float:\r
+       ;used by FCCMP, FCCMPE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm,TMPL_comma,TMPL_condition_nv>,\ ;0=sn,sm,imm,cond\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm,TMPL_comma,TMPL_condition_nv>   ;1=dn,dm,imm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       mov     ebp,[arm64_instruction]\r
+       and     eax,1\r
+       shl     eax,22                          ;set sz\r
+       or      ebp,eax\r
+       xor     eax,eax\r
+       jmp     ARM64_conditional_compare.encode\r
+\r
+ARM64_vector_scalar_sd_compare_mask_eq:\r
+       ;used by FCMEQ\r
+       push    0x00803c00\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm     sz=0\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\      ;1=sd,sn,imm    sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\;2=dd,dn,dm     sz=1\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;3=dd,dn,imm    sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ;4=vd,vn,vm     sz=0 q=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;5=vd,vn,imm    sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\   ;6=vd,vn,vm     sz=1 q=1\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\        ;7=vd,vn,imm    sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\   ;8=vd,vn,vm     sz=0 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>          ;9=vd,vn,imm    sz=0 q=1\r
+       pop     edx\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       shr     al,1\r
+       jnc     ARM64_vector_scalar_sd_three_reg.do\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.0\r
+       cmp     [immediate_value],0\r
+       jnz     ARM_store_instruction_with_error\r
+       xor     [arm64_instruction],edx\r
+       xor     [arm64_instruction2],edx\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_scalar_sd_compare_mask_ge:\r
+       ;used by FCMGE\r
+       push    0x00802c00\r
+       jmp     ARM64_vector_scalar_sd_compare_mask_eq.do\r
+\r
+ARM64_vector_scalar_sd_compare_mask_gt:\r
+       ;used by FCMGT\r
+       push    0x20002c00\r
+       jmp     ARM64_vector_scalar_sd_compare_mask_eq.do\r
+\r
+ARM64_vector_scalar_sd_compare_mask_le:\r
+       ;used by FCMLE, FCMLT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\      ;0=sd,sn,imm    sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;1=dd,dn,imm    sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;2=vd,vn,imm    sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\        ;3=vd,vn,imm    sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>          ;4=vd,vn,imm    sz=0 q=1\r
+       xor     edx,edx\r
+       lea     eax,[eax*2+1]\r
+       jmp     ARM64_vector_scalar_sd_compare_mask_eq.encode\r
+\r
+ARM64_scalar_sd_compare:\r
+       ;used by FCMP, FCMPE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\       ;0=sd,sn        sz=0 opc=0\r
+       <TMPL_vect_sreg,TMPL_imm>,\             ;1=sd,imm       sz=0 opc=1\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\       ;2=dd,dn        sz=1 opc=0\r
+       <TMPL_vect_dreg,TMPL_imm>               ;3=dd,imm       sz=1 opc=1\r
+       mov     edx,0x00000008\r
+       mov     ecx,[operand_registers]\r
+       shl     ecx,8\r
+       mov     [operand_registers],ecx\r
+       jmp     ARM64_vector_scalar_sd_compare_mask_eq.encode\r
+\r
+ARM64_scalar_conditional_select:\r
+       ;used by FCSEL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg,TMPL_condition_nv>,\      ;0=sd,sn,sm,cond\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg,TMPL_condition_nv>        ;1=dd,dn,dm,cond\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       mov     ebp,[arm64_instruction]\r
+       and     eax,1\r
+       shl     eax,22\r
+       jmp     ARM64_conditional_select.encode\r
+\r
+ARM64_scalar_hsd_convert:\r
+       ;used by FCVT\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_hreg,TMPL_never>,\           ;0=-            opc=11 type=11\r
+       <TMPL_vect_hreg,TMPL_vect_sreg>,\       ;1=hd,sn        opc=11 type=00\r
+       <TMPL_vect_hreg,TMPL_vect_dreg>,\       ;2=hd,dn        opc=11 type=01\r
+       <TMPL_vect_sreg,TMPL_vect_hreg>,\       ;3=sd,hn        opc=00 type=11\r
+       <TMPL_vect_sreg,TMPL_never>,\           ;4=-            opc=00 type=00\r
+       <TMPL_vect_sreg,TMPL_vect_dreg>,\       ;5=sd,dn        opc=00 type=01\r
+       <TMPL_vect_dreg,TMPL_vect_hreg>,\       ;6=dd,hn        opc=01 type=11\r
+       <TMPL_vect_dreg,TMPL_vect_sreg>         ;7=dd,sn        opc=01 type=00\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       mov     ebp,[arm64_instruction]\r
+       mov     ah,0\r
+       mov     cl,3\r
+       div     cl                      ;al=opc, ah=type\r
+       dec     ah\r
+       dec     al\r
+       mov     cl,ah\r
+       and     eax,3\r
+       and     ecx,3\r
+       shl     eax,15\r
+       shl     ecx,22\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_as:\r
+       ;used by FCVTAS\r
+       push    0x1e240000\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\       ;0=sd,sn        sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\       ;1=dd,dn        sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;2=vd,vn        sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>,\         ;3=vd,vn        sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\         ;4=vd,vn        sz=0 q=1\r
+       <TMPL_word_z_reg,TMPL_vect_sreg>,\      ;5=wd,sn\r
+       <TMPL_word_z_reg,TMPL_vect_dreg>,\      ;6=wd,dn\r
+       <TMPL_dword_z_reg,TMPL_vect_sreg>,\     ;7=xd,sn\r
+       <TMPL_dword_z_reg,TMPL_vect_dreg>       ;8=xd,dn\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       pop     edx\r
+       cmp     al,4\r
+       jbe     ARM64_vector_scalar_sd_three_reg.do\r
+       sub     al,5\r
+       shr     al,1\r
+       setc    cl\r
+       shl     eax,31\r
+       mov     ch,0\r
+       shl     ecx,22\r
+       lea     ebp,[edx+eax]\r
+       or      ebp,ecx\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_au:\r
+       ;used by FCVTAU\r
+       push    0x1e250000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_ms:\r
+       ;used by FCVTMS\r
+       push    0x1e300000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_mu:\r
+       ;used by FCVTMU\r
+       push    0x1e310000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_ns:\r
+       ;used by FCVTNS\r
+       push    0x1e200000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_nu:\r
+       ;used by FCVTNU\r
+       push    0x1e210000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_ps:\r
+       ;used by FCVTPS\r
+       push    0x1e280000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_scalar_sdwx_two_reg_pu:\r
+       ;used by FCVTPU\r
+       push    0x1e290000\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.do\r
+\r
+ARM64_vector_convert_long:\r
+       ;used by FCVTL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v4h>,\         ;0=vd,vn        sz=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2s>           ;1=vd,vn        sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_convert_long2:\r
+       ;used by FCVTL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v8h>,\         ;0=vd,vn        sz=0\r
+       <TMPL_vect_v2d,TMPL_vect_v4s>           ;1=vd,vn        sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_convert_narrow:\r
+       ;used by FCVTN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4h,TMPL_vect_v4s>,\         ;0=vd,vn        sz=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2d>           ;1=vd,vn        sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_convert_narrow2:\r
+       ;used by FCVTN2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v4s>,\         ;0=vd,vn        sz=0\r
+       <TMPL_vect_v4s,TMPL_vect_v2d>           ;1=vd,vn        sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_convert_odd_narrow:\r
+       ;used by FCVTXN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_dreg>,\       ;0=sd,dn\r
+       <TMPL_vect_v2s,TMPL_vect_v2d>           ;1=vd,vn\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_convert_odd_narrow2:\r
+       ;used by FCVTXN2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v2d>           ;0=vd,vn\r
+       shl     al,2\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_scalar_sd_convert_zero_s:\r
+       ;used by FCVTZS\r
+       push    0x1e380000\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\               ; 0=sd,sn,sm    sz=0\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\      ; 1=sd,sn,imm   sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\               ; 2=dd,dn,dm    sz=1\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ; 3=dd,dn,imm   sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\                 ; 4=vd,vn,vm    sz=0 q=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ; 5=vd,vn,imm   sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>,\                 ; 6=vd,vn,vm    sz=1 q=1\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\        ; 7=vd,vn,imm   sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\                 ; 8=vd,vn,vm    sz=0 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\        ; 9=vd,vn,imm   sz=0 q=1\r
+       <TMPL_word_z_reg,TMPL_vect_sreg>,\              ;10=wd,sn\r
+       <TMPL_word_z_reg,TMPL_vect_sreg,TMPL_imm>,\     ;11=wd,sn,imm\r
+       <TMPL_word_z_reg,TMPL_vect_dreg>,\              ;12=wd,dn\r
+       <TMPL_word_z_reg,TMPL_vect_dreg,TMPL_imm>,\     ;13=wd,dn,imm\r
+       <TMPL_dword_z_reg,TMPL_vect_sreg>,\             ;14=xd,sn\r
+       <TMPL_dword_z_reg,TMPL_vect_sreg,TMPL_imm>,\    ;15=xd,sn,imm\r
+       <TMPL_dword_z_reg,TMPL_vect_dreg>,\             ;16=xd,dn\r
+       <TMPL_dword_z_reg,TMPL_vect_dreg,TMPL_imm>      ;17=xd,dn,imm\r
+       shr     al,1\r
+       jnc     ARM64_vector_scalar_sdwx_two_reg_as.encode\r
+       ;fixed point\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       xor     dword[esp],1 shl 21\r
+       xor     [arm64_instruction],0x01a14400\r
+       xor     [arm64_instruction2],0x01a14400\r
+    .encode:\r
+       cmp     al,5\r
+       jae     .gp_reg\r
+       bt      eax,0\r
+       call    .test_immediate_size\r
+       shl     ebx,1\r
+       sub     ebx,edx\r
+       shl     ebx,16\r
+       or      [arm64_instruction],ebx\r
+       or      [arm64_instruction2],ebx\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.encode\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+    .gp_reg:\r
+       cmp     al,7\r
+       cmc\r
+       call    .test_immediate_size\r
+       neg     edx\r
+       and     edx,0x3f\r
+       shl     edx,10\r
+       or      dword[esp],edx\r
+       jmp     ARM64_vector_scalar_sdwx_two_reg_as.encode\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+    .test_immediate_size:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.1_32\r
+       mov     edx,ERROR_immediate_value_out_of_range.1_64\r
+       cmovc   ecx,edx\r
+       mov     ebx,32\r
+       mov     edx,64\r
+       cmovc   ebx,edx\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,ebx\r
+       jae     ARM_store_instruction_with_error\r
+       ret\r
+\r
+ARM64_vector_scalar_sd_convert_zero_u:\r
+       ;used by FCVTZU\r
+       push    0x1e390000\r
+       jmp     ARM64_vector_scalar_sd_convert_zero_s.do\r
+\r
+ARM64_scalar_sd_four_reg:\r
+       ;used by FMADD, FMSUB, FNMADD, FNMSUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\ ;0=sd,sn,sm,sa  sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>   ;1=dd,dn,dm,sa  sz=1\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       mov     ebp,[arm64_instruction]\r
+    .encode_size:\r
+       mov     ah,0\r
+       shl     eax,22\r
+       or      ebp,eax\r
+       jmp     ARM64_dz_nz_mz_az.encode_rd\r
+\r
+ARM64_vector_4_to_1:\r
+       ;used by FMAXNMV, FMAXV, FMINNMV, FMINV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_v4s>          ;0=sd,vn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       jmp     ARM64_dz_nz_mz.do\r
+\r
+ARM64_vector_scalar_sd_two_reg_element_add:\r
+       ;used by FMLA\r
+       push    0x0e20cc00\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s>,\   ;0=sd,sn,vn.s[] sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_element_d>,\   ;1=dd,dn,vn.d[] sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\     ;2=vd,vn,vn.s[] sz=0 q=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;3=vd,vn,vm     sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_element_d>,\     ;4=vd,vn,vn.d[] sz=1 q=1\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\           ;5=vd,vn,vm     sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>,\     ;6=vd,vn,vn.s[] sz=0 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>             ;7=vd,vn,vm     sz=0 q=1\r
+       pop     edx\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       cmp     al,2\r
+       jb      .scalar\r
+       shr     al,1\r
+       cmovnc  edx,[arm64_instruction2]\r
+       inc     al\r
+       mov     [arm64_instruction2],edx\r
+    .scalar:\r
+       mov     edx,[immediate_value2]\r
+       mov     cl,al\r
+       and     cl,1\r
+       shl     edx,cl\r
+       mov     ecx,edx\r
+       and     edx,10b\r
+       and     ecx,01b\r
+       shl     edx,11-1                ;H\r
+       shl     ecx,21-0                ;L\r
+       or      edx,ecx\r
+       or      [arm64_instruction],edx\r
+       or      [arm64_instruction2],edx\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_scalar_sd_two_reg_element_sub:\r
+       ;used by FMLS\r
+       push    0x0ea0cc00\r
+       jmp     ARM64_vector_scalar_sd_two_reg_element_add.do\r
+\r
+align 4\r
+ARM64_fmov_table:\r
+       dd      0x1e260000      ;wd,sn\r
+       dd      0x9e660000      ;xd,dn\r
+       dd      0x9eae0003      ;xd,vn.d[]\r
+       dd      0x9eaf0003      ;vd.d[],xn\r
+       dd      0x1e270000      ;sd,wn\r
+       dd      0x1e204000      ;sd,sn\r
+       dd      0x1e201001      ;sd,imm\r
+       dd      0x9e670000      ;dd,xn\r
+       dd      0x1e604000      ;dd,dn\r
+       dd      0x1e601001      ;dd,imm\r
+       dd      0x0f00f402      ;vd,imm\r
+       dd      0x6f00f402      ;vd,imm\r
+       dd      0x4f00f402      ;vd,imm\r
+\r
+ARM64_fmov:\r
+       ;used by FMOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_vect_sreg>,\              ; 0=wd,sn\r
+       <TMPL_dword_z_reg,TMPL_vect_dreg>,\             ; 1=xd,dn\r
+       <TMPL_dword_z_reg,TMPL_vect_element_d>,\        ; 2=xd,vn.d[]\r
+       <TMPL_vect_element_d,TMPL_dword_z_reg>,\        ; 3=vd.d[],xn\r
+       <TMPL_vect_sreg,TMPL_word_z_reg>,\              ; 4=sd,wn\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\               ; 5=sd,sn\r
+       <TMPL_vect_sreg,TMPL_imm_float>,\               ; 6=sd,imm\r
+       <TMPL_vect_dreg,TMPL_dword_z_reg>,\             ; 7=dd,xn\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\               ; 8=dd,dn\r
+       <TMPL_vect_dreg,TMPL_imm_float>,\               ; 9=dd,imm\r
+       <TMPL_vect_v2s,TMPL_imm_float>,\                ;10=vd,imm      op=0 q=0\r
+       <TMPL_vect_v2d,TMPL_imm_float>,\                ;11=vd,imm      op=1 q=1\r
+       <TMPL_vect_v4s,TMPL_imm_float>                  ;12=vd,imm      op=0 q=1\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       movzx   eax,al\r
+       mov     ebp,[ARM64_fmov_table+eax*4]\r
+       mov     edx,ebp\r
+       and     ebp,not 3\r
+       cmp     dl,1\r
+       jb      ARM64_arithmetic1.encode_rn\r
+       je      .scalar_immediate\r
+       cmp     dl,2\r
+       ja      .check_element\r
+       ;vector immediate\r
+       call    VFP_convert_single_to_quarter\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       mov     ecx,eax\r
+       and     eax,0x1f\r
+       and     ecx,0xe0\r
+       shl     eax,5\r
+       shl     ecx,16-5\r
+       or      ebp,eax\r
+       or      ebp,ecx\r
+       jmp     ARM64_arithmetic1.encode_rd\r
+    .scalar_immediate:\r
+       call    VFP_convert_single_to_quarter\r
+       mov     eax,[immediate_value]\r
+       cmp     eax,0xff\r
+       ja      .out_of_range\r
+       shl     eax,13\r
+       or      ebp,eax\r
+       jmp     ARM64_arithmetic1.encode_rd\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.quarter\r
+       jmp     ARM_store_instruction_with_error\r
+    .check_element:\r
+       mov     ebx,[immediate_value]\r
+       mov     edx,[immediate_value2]\r
+       test    al,1\r
+       cmovz   ebx,edx\r
+       mov     ecx,ERROR_immediate_offset_out_of_range.1\r
+       cmp     ebx,1\r
+       jnz     ARM_store_instruction_with_error\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+ARM64_vector_scalar_sd_three_reg_element:\r
+       ;used by FMUL\r
+       push    0x5f809000\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\        ;0=sd,sn,sm     sz=0\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s>,\   ;1=sd,sn,v.s[]  sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\        ;2=dd,dn,dm     sz=1\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_element_d>,\   ;3=dd,dn,v.d[]  sz=1\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;4=vd,vn,vm     sz=0 q=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\     ;5=vd,vn,v.s[]  sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\           ;6=vd,vn,vm     sz=1 q=1\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_element_d>,\     ;7=vd,vn,v.d[]  sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;8=vd,vn,vm     sz=0 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>       ;9=vd,vn,v.s[]  sz=0 q=1\r
+       pop     edx\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       shr     al,1\r
+       jnc     ARM64_vector_scalar_sd_three_reg.do\r
+       mov     ebx,[immediate_value2]\r
+       mov     cl,al\r
+       and     cl,1\r
+       shl     ebx,cl\r
+       mov     ecx,ebx\r
+       and     ebx,10b\r
+       and     ecx,01b\r
+       shl     ebx,11-1                ;H\r
+       shl     ecx,21-0                ;L\r
+       or      ebx,ecx\r
+       or      edx,ebx\r
+       mov     [arm64_instruction],edx\r
+       xor     edx,5 shl 28\r
+       mov     [arm64_instruction2],edx\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_vector_scalar_sd_three_reg_element_x:\r
+       ;used by FMULX\r
+       push    0x7f809000\r
+       jmp     ARM64_vector_scalar_sd_three_reg_element.do\r
+\r
+ARM64_scalar_sd_three_reg:\r
+       ;used by FNMUL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\;0=sd,sn,sm     sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>  ;1=dd,dn,dm     sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_scalar_sd_rwo_reg:\r
+       ;used by FRECPX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\       ;0=sd,sn        sz=0\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>         ;1=dd,dn        sz=1\r
+       jmp     ARM64_vector_scalar_sd_three_reg.do\r
+\r
+ARM64_ins:\r
+       ;used by INS\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_element_b,TMPL_vect_element_b>,\     ;0=vd.b[],vn.b[]\r
+       <TMPL_vect_element_b,TMPL_word_z_reg>,\         ;1=vd.b[],wn\r
+       <TMPL_vect_element_h,TMPL_vect_element_h>,\     ;2=vd.h[],vn.h[]\r
+       <TMPL_vect_element_h,TMPL_word_z_reg>,\         ;3=vd.h[],wn\r
+       <TMPL_vect_element_s,TMPL_vect_element_s>,\     ;4=vd.s[],vn.s[]\r
+       <TMPL_vect_element_s,TMPL_word_z_reg>,\         ;5=vd.s[],wn\r
+       <TMPL_vect_element_d,TMPL_vect_element_d>,\     ;6=vd.d[],vn.d[]\r
+       <TMPL_vect_element_d,TMPL_dword_z_reg>          ;7=vd.d[],xn\r
+       add     al,24\r
+       jmp     ARM64_mov_aliases.encode\r
+\r
+align 4\r
+ARM64_ld1_error_table1:\r
+       dd      ERROR_immediate_offset_out_of_range.8\r
+       dd      ERROR_immediate_offset_out_of_range.16\r
+       dd      ERROR_immediate_offset_out_of_range.24\r
+       dd      ERROR_immediate_offset_out_of_range.32\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.48\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.64\r
+ARM64_ld1_opcode_table1:\r
+       db      5,8,4,0\r
+ARM64_ld1_error_table2:\r
+       dd      ERROR_immediate_offset_out_of_range.1\r
+       dd      ERROR_immediate_offset_out_of_range.2\r
+       dd      ERROR_immediate_offset_out_of_range.3\r
+       dd      ERROR_immediate_offset_out_of_range.4\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.6\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.8\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.12\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.16\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.24\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      0\r
+       dd      ERROR_immediate_offset_out_of_range.32\r
+ARM64_ld1_opcode_table2:\r
+       db      0,16,32,33\r
+\r
+ARM64_ld1:\r
+       ;used by LD1, ST1\r
+       push    0x00000401\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 0={vt.8b},[xn]\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ; 1={vt.8b},[xn],xm\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ; 2={vt.8b},[xn],imm\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                    ; 3={vt.16b},[xn]\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 4={vt.16b},[xn],xm\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\          ; 5={vt.16b},[xn],imm\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 6={vt.4h},[xn]\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ; 7={vt.4h},[xn],xm\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ; 8={vt.4h},[xn],imm\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 9={vt.8h},[xn]\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;10={vt.8h},[xn],xm\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;11={vt.8h},[xn],imm\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;12={vt.2s},[xn]\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;13={vt.2s},[xn],xm\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;14={vt.2s},[xn],imm\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;15={vt.4s},[xn]\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;16={vt.4s},[xn],xm\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;17={vt.4s},[xn],imm\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;18={vt.1d},[xn]\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;19={vt.1d},[xn],xm\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;20={vt.1d},[xn],imm\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;21={vt.2d},[xn]\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;22={vt.2d},[xn],xm\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;23={vt.2d},[xn],imm\r
+       <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;24={vt.b}[imm],[xn]\r
+       <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;25={vt.b}[imm],[xn],xm\r
+       <TMPL_vect_list_vb,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;26={vt.b}[imm],[xn],imm\r
+       <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;27={vt.h}[imm],[xn]\r
+       <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;28={vt.h}[imm],[xn],xm\r
+       <TMPL_vect_list_vh,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;29={vt.h}[imm],[xn],imm\r
+       <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;30={vt.s}[imm],[xn]\r
+       <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;31={vt.s}[imm],[xn],xm\r
+       <TMPL_vect_list_vs,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;32={vt.s}[imm],[xn],imm\r
+       <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;33={vt.d}[imm],[xn]\r
+       <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;34={vt.d}[imm],[xn],xm\r
+       <TMPL_vect_list_vd,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>             ;35={vt.d}[imm],[xn],imm\r
+       pop     ebx\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       cmp     [simd_reg_list_count],bl\r
+       jb      ERROR_parameter_n_not_valid.first\r
+       cmp     [simd_reg_list_count],bh\r
+       ja      ERROR_parameter_n_not_valid.first\r
+       mov     ah,0\r
+       mov     cl,3\r
+       div     cl                      ;al=reg selection, ah=address mode\r
+       cmp     bl,bh\r
+       jnz     .1d_okay\r
+       cmp     al,6\r
+       jz      ERROR_parameter_n_not_valid.first\r
+    .1d_okay:\r
+       cmp     al,8\r
+       jae     .single\r
+       mov     ebp,[arm64_instruction2]\r
+       cmp     ah,1\r
+       jz      .encode_multiple\r
+       ;check immediate\r
+       btr     ebp,23\r
+       test    ah,ah\r
+       jz      .encode_multiple\r
+       bts     ebp,23\r
+       mov     [operand_register2],0x1f\r
+       movzx   edx,[simd_reg_list_count]\r
+       mov     cl,al\r
+       and     cl,1\r
+       shl     edx,cl\r
+       mov     ecx,[ARM64_ld1_error_table1-4+edx*4]\r
+       shl     edx,3\r
+       cmp     edx,[immediate_value2]\r
+       jnz     ARM_store_instruction_with_error\r
+    .encode_multiple:\r
+       movzx   eax,al\r
+       mov     edx,eax\r
+       and     eax,110b\r
+       and     edx,001b\r
+       shl     eax,10-1\r
+       shl     edx,30-0\r
+       or      ebp,eax                 ;set size\r
+       or      ebp,edx                 ;set Q\r
+       movzx   edx,[simd_reg_list_count]\r
+       mov     dl,[ARM64_ld1_opcode_table1-1+edx]\r
+       shl     edx,12\r
+       or      ebp,edx\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+    .single:\r
+       cmp     [simd_reg_list_count],bl\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       sub     al,8\r
+       mov     ebp,[arm64_instruction]\r
+       cmp     ah,1\r
+       jz      .encode_single\r
+       ;check immediate\r
+       btr     ebp,23\r
+       test    ah,ah\r
+       jz      .encode_single\r
+       bts     ebp,23\r
+       mov     [operand_register2],0x1f\r
+       movzx   ecx,al\r
+       movzx   edx,[simd_reg_list_count]\r
+       shl     edx,cl\r
+       mov     ecx,[ARM64_ld1_error_table2-4+edx*4]\r
+       cmp     edx,[immediate_value2]\r
+       jnz     ARM_store_instruction_with_error\r
+    .encode_single:\r
+       movzx   eax,al\r
+       mov     ecx,eax\r
+       mov     al,[ARM64_ld1_opcode_table2+eax]\r
+       shl     eax,10\r
+       or      ebp,eax                 ;set size and opcode\r
+       mov     edx,[immediate_value]\r
+       shl     edx,cl\r
+       mov     eax,edx\r
+       and     edx,1000b\r
+       and     eax,0111b\r
+       shl     edx,30-3\r
+       shl     eax,10-0\r
+       or      ebp,edx                 ;set Q\r
+       or      ebp,eax                 ;set S:size\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_ld2:\r
+       ;used by LD2, ST2\r
+       push    0x00000202\r
+       jmp     ARM64_ld1.do\r
+\r
+ARM64_ld3:\r
+       ;used by LD3, ST3\r
+       push    0x00000303\r
+       jmp     ARM64_ld1.do\r
+\r
+ARM64_ld4:\r
+       ;used by LD4, ST4\r
+       push    0x00000404\r
+       jmp     ARM64_ld1.do\r
+\r
+ARM64_ld1r:\r
+       ;used by LD1R\r
+       push    1\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 0={vt.8b},[xn]\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ; 1={vt.8b},[xn],xm\r
+       <TMPL_vect_list_8b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ; 2={vt.8b},[xn],imm\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                    ; 3={vt.16b},[xn]\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\ ; 4={vt.16b},[xn],xm\r
+       <TMPL_vect_list_16b,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\          ; 5={vt.16b},[xn],imm\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 6={vt.4h},[xn]\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ; 7={vt.4h},[xn],xm\r
+       <TMPL_vect_list_4h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ; 8={vt.4h},[xn],imm\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ; 9={vt.8h},[xn]\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;10={vt.8h},[xn],xm\r
+       <TMPL_vect_list_8h,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;11={vt.8h},[xn],imm\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;12={vt.2s},[xn]\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;13={vt.2s},[xn],xm\r
+       <TMPL_vect_list_2s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;14={vt.2s},[xn],imm\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;15={vt.4s},[xn]\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;16={vt.4s},[xn],xm\r
+       <TMPL_vect_list_4s,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;17={vt.4s},[xn],imm\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;18={vt.1d},[xn]\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;19={vt.1d},[xn],xm\r
+       <TMPL_vect_list_1d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>,\           ;20={vt.1d},[xn],imm\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right>,\                     ;21={vt.2d},[xn]\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_dword_gen_reg>,\  ;22={vt.2d},[xn],xm\r
+       <TMPL_vect_list_2d,TMPL_bracket_left,TMPL_dword_s_reg,TMPL_bracket_right,TMPL_imm2>             ;23={vt.2d},[xn],imm\r
+       pop     ebx\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       cmp     [simd_reg_list_count],bl\r
+       jnz     ERROR_parameter_n_not_valid.first\r
+       mov     ah,0\r
+       mov     cl,3\r
+       div     cl                      ;al=reg selection, ah=address mode\r
+       mov     ebp,[arm64_instruction]\r
+       cmp     ah,1\r
+       jz      .encode\r
+       ;check immediate\r
+       btr     ebp,23\r
+       test    ah,ah\r
+       jz      .encode\r
+       bts     ebp,23\r
+       mov     [operand_register2],0x1f\r
+       movzx   ecx,al\r
+       shr     ecx,1\r
+       movzx   edx,[simd_reg_list_count]\r
+       shl     edx,cl\r
+       mov     ecx,[ARM64_ld1_error_table2-4+edx*4]\r
+       cmp     edx,[immediate_value2]\r
+       jnz     ARM_store_instruction_with_error\r
+    .encode:\r
+       movzx   eax,al\r
+       mov     edx,eax\r
+       and     eax,110b\r
+       and     edx,001b\r
+       shl     eax,10-1\r
+       shl     edx,30-0\r
+       or      ebp,eax                 ;set size\r
+       or      ebp,edx                 ;set Q\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_ld2r:\r
+       ;used by LD2R\r
+       push    2\r
+       jmp     ARM64_ld1r.do\r
+\r
+ARM64_ld3r:\r
+       ;used by LD3R\r
+       push    3\r
+       jmp     ARM64_ld1r.do\r
+\r
+ARM64_ld4r:\r
+       ;used by LD4R\r
+       push    4\r
+       jmp     ARM64_ld1r.do\r
+\r
+ARM64_arithmetic17:\r
+       ;used by MLA\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ; 0=vd,vn,vm\r
+       <TMPL_never>,\                                          ; 1\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ; 2=vd,vn,vm\r
+       <TMPL_never>,\                                          ; 3\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ; 4=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\     ; 5=vd,vn,vm.h[]\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ; 6=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\     ; 7=vd,vn,vm.h[]\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ; 8=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\     ; 9=vd,vn,vm.s[]\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;10=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>       ;11=vd,vn,vm.s[]\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;vector\r
+       mov     ebx,[arm64_instruction2]        ;element\r
+       jmp     ARM64_arithmetic6.vector_encode\r
+\r
+ARM64_movi_table:\r
+               ;Q:op,cmode\r
+       db      0000b,1110b,0+0 shl 4,12-3+1    ; 0=vd,imm\r
+       db      0000b,1110b,0+0 shl 4,12-3+1    ; 1=vd,imm,lsl imm\r
+       db      0100b,1110b,0+0 shl 4,12-3+1    ; 2=vd,imm\r
+       db      0100b,1110b,0+0 shl 4,12-3+1    ; 3=vd,imm,lsl imm\r
+       db      0000b,1000b,0+1 shl 4,12-3+1    ; 4=vd,imm\r
+       db      0000b,1000b,0+1 shl 4,12-3+1    ; 5=vd,imm,lsl imm\r
+       db      0100b,1000b,0+1 shl 4,12-3+1    ; 6=vd,imm\r
+       db      0100b,1000b,0+1 shl 4,12-3+1    ; 7=vd,imm,lsl imm\r
+       db      0000b,0000b,0+3 shl 4,12-3+1    ; 8=vd,imm\r
+       db      0000b,0000b,0+3 shl 4,12-3+1    ; 9=vd,imm,lsl imm\r
+       db      0000b,1100b,1+2 shl 4,12-3+0    ;10=vd,imm,msl imm\r
+       db      0100b,0000b,0+3 shl 4,12-3+1    ;11=vd,imm\r
+       db      0100b,0000b,0+3 shl 4,12-3+1    ;12=vd,imm,lsl imm\r
+       db      0100b,1100b,1+2 shl 4,12-3+0    ;13=vd,imm,msl imm\r
+       db      0010b,1110b,0,0                 ;14=dd,imm\r
+       db      0110b,1110b,0,0                 ;15=vd,imm\r
+\r
+ARM64_movi:\r
+       ;used by MOVI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_imm>,\                                      ; 0=vd,imm\r
+       <TMPL_vect_v8b,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ; 1=vd,imm,lsl imm\r
+       <TMPL_vect_v16b,TMPL_imm>,\                                     ; 2=vd,imm\r
+       <TMPL_vect_v16b,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\       ; 3=vd,imm,lsl imm\r
+       <TMPL_vect_v4h,TMPL_imm>,\                                      ; 4=vd,imm\r
+       <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ; 5=vd,imm,lsl imm\r
+       <TMPL_vect_v8h,TMPL_imm>,\                                      ; 6=vd,imm\r
+       <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ; 7=vd,imm,lsl imm\r
+       <TMPL_vect_v2s,TMPL_imm>,\                                      ; 8=vd,imm\r
+       <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ; 9=vd,imm,lsl imm\r
+       <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\        ;10=vd,imm,msl imm\r
+       <TMPL_vect_v4s,TMPL_imm>,\                                      ;11=vd,imm\r
+       <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ;12=vd,imm,lsl imm\r
+       <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\        ;13=vd,imm,msl imm\r
+       <TMPL_vect_dreg,TMPL_imm64>,\                                   ;14=dd,imm\r
+       <TMPL_vect_v2d,TMPL_imm64>                                      ;15=vd,imm\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]\r
+       cmp     al,14\r
+       jae     .imm64\r
+       xor     ah,ah\r
+       ;construct the immediate\r
+       mov     edx,[immediate_value]\r
+       mov     ecx,[immediate_value2]\r
+       xor     ebx,ebx\r
+       cmp     al,10                           ;imm,msl imm\r
+       jz      .msl\r
+       cmp     al,13                           ;imm,msl imm\r
+       jz      .msl\r
+       test    edx,edx\r
+       jz      .immediate_ready\r
+       cmp     ecx,32\r
+       jae     .out_of_range\r
+       shld    ebx,edx,cl\r
+       test    ebx,ebx\r
+       jnz     .out_of_range\r
+       shl     edx,cl\r
+       jmp     .immediate_ready\r
+    .msl:\r
+       sub     al,2\r
+       cmp     ecx,32\r
+       jae     .out_of_range\r
+       inc     edx\r
+       shld    ebx,edx,cl\r
+       shl     edx,cl\r
+       sub     edx,1\r
+       sbb     ebx,0\r
+       jnz     .out_of_range\r
+    .immediate_ready:\r
+       push    eax edx\r
+       xor     ecx,ecx\r
+       test    edx,edx\r
+       jz      .immediate_shifted\r
+       bsf     ecx,edx\r
+       and     ecx,not 7\r
+       shr     edx,cl\r
+       cmp     edx,0xff\r
+       jbe     .immediate_shifted\r
+       test    ecx,ecx\r
+       jnz     .try_inverse\r
+       cmp     al,8\r
+       jb      .try_inverse\r
+       setz    cl\r
+       cmp     al,11\r
+       setz    ch\r
+       or      cl,ch\r
+       lea     eax,[eax+ecx+1]\r
+       cmp     dl,0xff\r
+       jnz     .try_inverse\r
+       mov     ecx,8\r
+       shr     edx,8\r
+       cmp     dl,0xff\r
+       jnz     .immediate_shifted\r
+       mov     ecx,16\r
+       shr     edx,8\r
+    .immediate_shifted:\r
+       cmp     edx,0xff\r
+       ja      .try_inverse\r
+       mov     [immediate_value],edx\r
+       mov     [immediate_value2],ecx\r
+       movzx   eax,al\r
+       movzx   ecx,byte[ARM64_movi_table+eax*4+2]\r
+       shl     ecx,3\r
+       mov     ebx,ecx\r
+       and     ecx,0x78\r
+       shr     ebx,4\r
+       and     ebx,0x78\r
+       mov     edx,[immediate_value2]\r
+       test    edx,0x7\r
+       jnz     .try_inverse\r
+       cmp     edx,ecx\r
+       jz      .imm2_okay\r
+       cmp     edx,ebx\r
+       ja      .try_inverse\r
+    .imm2_okay:\r
+       sub     edx,ecx\r
+       movzx   ecx,byte[ARM64_movi_table+eax*4+3]\r
+       shl     edx,cl\r
+       or      ebp,edx\r
+       mov     edx,[immediate_value]\r
+       add     esp,8\r
+    .encode_imm:\r
+       mov     ecx,edx\r
+       and     edx,00011111b\r
+       and     ecx,11100000b\r
+       shl     edx,5\r
+       shl     ecx,16-5\r
+       or      ebp,edx\r
+       or      ebp,ecx\r
+       movzx   eax,al\r
+       movzx   edx,byte[ARM64_movi_table+eax*4+0]\r
+       movzx   ecx,byte[ARM64_movi_table+eax*4+1]\r
+       shl     edx,28\r
+       shl     ecx,12\r
+       or      ebp,edx\r
+       or      ebp,ecx\r
+       jmp     ARM64_arithmetic1.encode_rd\r
+    .imm64:\r
+       mov     ecx,[immediate_value]\r
+       mov     ebx,[immediate_value_high]\r
+       mov     edx,1 shl 7\r
+    .check_imm64:\r
+       inc     cl\r
+       cmp     cl,1\r
+       ja      .cannot_encode\r
+       rcr     dl,1\r
+       jc      .encode_imm\r
+       shrd    ecx,ebx,8\r
+       shr     ebx,8\r
+       jmp     .check_imm64\r
+    .cannot_encode:\r
+       mov     ecx,ERROR_immediate_cannot_be_encoded\r
+       jmp     ARM_store_instruction_with_error\r
+    .try_inverse:\r
+       xor     ebp,1 shl 29\r
+       pop     edx eax\r
+       cmp     al,4\r
+       jb      .out_of_range\r
+       mov     ecx,0xffff\r
+       mov     ebx,0xffffffff\r
+       cmp     al,8\r
+       cmovb   ebx,ecx\r
+       xor     edx,ebx\r
+       xor     ah,0xff\r
+       jnz     .immediate_ready\r
+    .out_of_range:\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xff\r
+       cmp     al,4\r
+       jb      ARM_store_instruction_with_error\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xff_lsl_8\r
+       cmp     al,8\r
+       jb      ARM_store_instruction_with_error\r
+       mov     ecx,ERROR_immediate_value_out_of_range.0_0xff_msl\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_mvni:\r
+       ;used by MVNI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4h,TMPL_imm>,\                                      ;0=vd,imm\r
+       <TMPL_vect_v4h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ;1=vd,imm,lsl imm\r
+       <TMPL_vect_v8h,TMPL_imm>,\                                      ;2=vd,imm\r
+       <TMPL_vect_v8h,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ;3=vd,imm,lsl imm\r
+       <TMPL_vect_v2s,TMPL_imm>,\                                      ;4=vd,imm\r
+       <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ;5=vd,imm,lsl imm\r
+       <TMPL_vect_v2s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>,\        ;6=vd,imm,msl imm\r
+       <TMPL_vect_v4s,TMPL_imm>,\                                      ;7=vd,imm\r
+       <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_lsl,TMPL_imm2>,\        ;8=vd,imm,lsl imm\r
+       <TMPL_vect_v4s,TMPL_imm,TMPL_comma,TMPL_msl,TMPL_imm2>          ;9=vd,imm,msl imm\r
+       add     al,4\r
+       jmp     ARM64_movi.do\r
+\r
+ARM64_polynomial:\r
+       ;used by PMULL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\   ;0=vd,vn,vm\r
+       <TMPL_vect_v1q,TMPL_vect_v1d,TMPL_vect_v1d>     ;1=vd,vn,vm\r
+       test    al,al\r
+       jz      ARM64_vector_scalar_bhsd_two_reg.encode\r
+       or      [arm64_instruction],11b shl 22\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_polynomial2:\r
+       ;used by PMULL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\ ;0=vd,vn,vm\r
+       <TMPL_vect_v1q,TMPL_vect_v2d,TMPL_vect_v2d>     ;1=vd,vn,vm\r
+       test    al,al\r
+       jz      ARM64_vector_scalar_bhsd_two_reg.encode\r
+       or      [arm64_instruction],11b shl 22\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_vector_narrow_shift_low:\r
+       ;used by RSHRN, SHRN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_imm>          ;2=vd,vn,imm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       mov     cl,al\r
+       mov     ebx,8\r
+       shl     ebx,cl\r
+       mov     edx,[immediate_value]\r
+       cmp     edx,ebx\r
+       ja      .out_of_range\r
+       test    edx,edx\r
+       jz      .out_of_range\r
+       shl     ebx,1\r
+       sub     ebx,edx\r
+       shl     ebx,16\r
+       or      ebp,ebx\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_8\r
+       mov     edx,ERROR_shift_value_out_of_range.1_16\r
+       mov     eax,ERROR_shift_value_out_of_range.1_32\r
+       cmp     ebx,16\r
+       cmovz   ecx,edx\r
+       cmova   ecx,eax\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_vector_narrow_shift_high:\r
+       ;used by RSHRN2, SHRN2, SQRSHRN2, SQRSHRUN2, SQSRHN2, SQSHRUN2, UQRSHRN2, UQSHRN2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v16b,TMPL_vect_v8h,TMPL_imm>,\       ;0=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v4s,TMPL_imm>,\        ;1=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v2d,TMPL_imm>          ;2=vd,vn,vm\r
+       jmp     ARM64_vector_narrow_shift_low.encode\r
+\r
+ARM64_vector_bhs_three_reg:\r
+       ;used by SABA, SABD, SHADD, SHSUB, SMAX, SMAXP, SMIN, SMINP, SRHADD,\r
+       ;        UABA, UABD, UHADD, UHSUB, UMAX, UMAXP, UMIN, UMINP, URHADD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ;1=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;3=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;4=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>             ;5=vd,vn,vm\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_bhs_three_reg_long:\r
+       ;used by SABAL, SABDL, SADDL, SSUBL, UABAL, SABDL, UADDL, USUBL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>             ;2=vd,vn,vm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_bhs_three_reg_long2:\r
+       ;used by SABAL2, SABDL2, SADDL2, SSUBL2, UABAL2, SABDL2, UADDL2, USUBL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\         ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s>             ;2=vd,vn,vm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_bhs_two_reg_pair:\r
+       ;used by SADALP, SADDLP, UADALP, UADDLP\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4h,TMPL_vect_v8b>,\         ;0=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v16b>,\        ;1=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v4h>,\         ;2=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v8h>,\         ;3=vd,vn\r
+       <TMPL_vect_v1d,TMPL_vect_v2s>,\         ;4=vd,vn\r
+       <TMPL_vect_v2d,TMPL_vect_v4s>           ;5=vd,vn\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_scalar_vector_bhs_two_reg:\r
+       ;used by SADALV, UADDLV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_hreg,TMPL_vect_v8b>,\        ;0=hd,vn\r
+       <TMPL_vect_hreg,TMPL_vect_v16b>,\       ;1=hd,vn\r
+       <TMPL_vect_sreg,TMPL_vect_v4h>,\        ;2=sd,vn\r
+       <TMPL_vect_sreg,TMPL_vect_v8h>,\        ;3=sd,vn\r
+       <TMPL_never>,\                          ;4=-\r
+       <TMPL_vect_dreg,TMPL_vect_v4s>          ;5=dd,vn\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_bhs_three_reg_wide:\r
+       ;used by SADDW, SSUBW, UADDW, USUBW\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8b>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4h>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2s>             ;2=vd,vn,vm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_vector_bhs_three_reg_wide2:\r
+       ;used by SADDW2, SSUBW2, UADDW2, USUBW2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v16b>,\          ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v8h>,\           ;1=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v4s>             ;2=vd,vn,vm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_scalar_vector_sd_convert_zero_s_table:\r
+       db      0,1,10,11,14,15,2,3,12,13,16,17,4,5,6,7,8,9\r
+\r
+ARM64_scalar_vector_sd_convert_zero_s:\r
+       ;used by SCVTF\r
+       push    0x1e220000\r
+    .do:\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\               ; 0=sd,sn       sz=0\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\      ; 1=sd,sn,imm   sz=0\r
+       <TMPL_vect_sreg,TMPL_word_z_reg>,\              ; 2=sd,wn\r
+       <TMPL_vect_sreg,TMPL_word_z_reg,TMPL_imm>,\     ; 3=sd,wn,imm\r
+       <TMPL_vect_sreg,TMPL_dword_z_reg>,\             ; 4=sd,xn\r
+       <TMPL_vect_sreg,TMPL_dword_z_reg,TMPL_imm>,\    ; 5=sd,xn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>,\               ; 6=dd,dn       sz=1\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ; 7=dd,dn,imm   sz=1\r
+       <TMPL_vect_dreg,TMPL_word_z_reg>,\              ; 8=dd,wn\r
+       <TMPL_vect_dreg,TMPL_word_z_reg,TMPL_imm>,\     ; 9=dd,wn,imm\r
+       <TMPL_vect_dreg,TMPL_dword_z_reg>,\             ;10=dd,xn\r
+       <TMPL_vect_dreg,TMPL_dword_z_reg,TMPL_imm>,\    ;11=dd,xn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\                 ;12=vd,vn       sz=0 q=0\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;13=vd,vn,imm   sz=0 q=0\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>,\                 ;14=vd,vn       sz=1 q=1\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\        ;15=vd,vn,imm   sz=1 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\                 ;16=vd,vn       sz=0 q=1\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>          ;17=vd,vn,imm   sz=0 q=1\r
+       movzx   eax,al\r
+       mov     al,[ARM64_scalar_vector_sd_convert_zero_s_table+eax]\r
+       shr     al,1\r
+       jnc     ARM64_vector_scalar_sdwx_two_reg_as.encode\r
+       ;fixed point\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       xor     dword[esp],1 shl 21\r
+       xor     [arm64_instruction],0x01213c00\r
+       xor     [arm64_instruction2],0x01213c00\r
+       jmp     ARM64_vector_scalar_sd_convert_zero_s.encode\r
+\r
+ARM64_scalar_vector_sd_convert_zero_u:\r
+       ;used by UCVTF\r
+       push    0x1e230000\r
+       jmp     ARM64_scalar_vector_sd_convert_zero_s.do\r
+\r
+ARM64_sha_qsv:\r
+       ;used by SHA1C, SHA1M, SHA1P\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_qreg,TMPL_vect_sreg,TMPL_vect_v4s>   ;0=qd,sn,vm\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_sha_s_two_reg:\r
+       ;used by SHA1H\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_sreg,TMPL_vect_sreg> ;0=sd,sn\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_sha_vs_three_reg:\r
+       ;used by SHA1SU0, SHA256SU1\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>     ;0=vd,vn,vm\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_sha_vs_two_reg:\r
+       ;used by SHA1SU1, SHA256SU0\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>   ;0=vd,vn\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_sha_qqv:\r
+       ;used by SHA256H, SHA256H2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_qreg,TMPL_vect_qreg,TMPL_vect_v4s>   ;0=qd,qn,vm\r
+       jmp     ARM64_crypto_two_reg.do\r
+\r
+ARM64_vector_scalar_bhsd_two_reg_left_imm:\r
+       ;used by SHL, SLI\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\      ;1=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\        ;2=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\        ;3=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;4=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\        ;5=vd,vn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;6=dd,dn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>          ;7=vd,vn,imm\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+    .immediate_encode:\r
+       movzx   ecx,al\r
+       shr     ecx,1\r
+       mov     edx,8\r
+       shl     edx,cl\r
+       cmp     edx,[immediate_value]\r
+       jbe     .out_of_range\r
+       add     edx,[immediate_value]\r
+       shl     edx,16\r
+       or      ebp,edx\r
+    .vector_encode:\r
+       cmp     al,6                                    ;scalar?\r
+       setz    dl\r
+       shr     al,1\r
+       setc    cl\r
+       shl     ecx,30\r
+       or      ebp,ecx                                 ;set Q\r
+       neg     dl\r
+       and     dl,5\r
+       shl     edx,28\r
+       or      ebp,edx                                 ;set for scalar\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.0_7\r
+       mov     ebx,ERROR_shift_value_out_of_range.0_15\r
+       mov     eax,ERROR_shift_value_out_of_range.0_31\r
+       mov     ebp,ERROR_shift_value_out_of_range.0_63\r
+       cmp     edx,16\r
+       cmovz   ecx,ebx\r
+       cmp     edx,32\r
+       cmovz   ecx,eax\r
+       cmova   ecx,ebp\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_vector_scalar_bhsd_two_reg_right_imm:\r
+       ;used by SRI, SRSHR, SRSRA, SSHR, SSRA, URSHR, URSRA, USHR, USRA\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\      ;1=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\        ;2=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\        ;3=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\        ;4=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\        ;5=vd,vn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>,\      ;6=dd,dn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>          ;7=vd,vn,imm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+    .immediate_encode:\r
+       movzx   ecx,al\r
+       shr     ecx,1\r
+       mov     edx,8\r
+       shl     edx,cl\r
+       mov     ebx,[immediate_value]\r
+       test    ebx,ebx\r
+       je      .out_of_range\r
+       cmp     edx,ebx\r
+       jb      .out_of_range\r
+       add     edx,edx\r
+       sub     edx,ebx\r
+       shl     edx,16\r
+       or      ebp,edx\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.vector_encode\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.1_8\r
+       mov     ebx,ERROR_shift_value_out_of_range.1_16\r
+       mov     eax,ERROR_shift_value_out_of_range.1_32\r
+       mov     ebp,ERROR_shift_value_out_of_range.1_64\r
+       cmp     edx,16\r
+       cmovz   ecx,ebx\r
+       cmp     edx,32\r
+       cmovz   ecx,eax\r
+       cmova   ecx,ebp\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_vector_scalar_bhs_long_size:\r
+       ;used by SHLL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_imm>          ;2=vd,vn,imm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   ecx,al\r
+       mov     edx,8\r
+       shl     edx,cl\r
+       cmp     edx,[immediate_value]\r
+       jne     .out_of_range\r
+       add     al,al\r
+       jmp     ARM64_arithmetic1.vector_encode\r
+    .out_of_range:\r
+       mov     ecx,ERROR_shift_value_out_of_range.8\r
+       mov     ebx,ERROR_shift_value_out_of_range.16\r
+       mov     eax,ERROR_shift_value_out_of_range.32\r
+       cmp     edx,16\r
+       cmovz   ecx,ebx\r
+       cmova   ecx,eax\r
+       jmp     ARM_store_instruction_with_error\r
+\r
+ARM64_vector_scalar_bhs_long2_size:\r
+       ;used by SHLL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_imm>,\       ;0=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_imm>          ;2=vd,vn,imm\r
+       jmp     ARM64_vector_scalar_bhs_long_size.encode\r
+\r
+ARM64_arithmetic18_long:\r
+       ;used by SMLAL, SMLSL, UMLAL, UMLSL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_vect_v8b>,\           ;0=vd,vn,vm\r
+       <TMPL_never>,\                                          ;1=-\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\     ;3=vd,vn,vm.h[]\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;4=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s>       ;5=vd,vn,vm.s[]\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;vector\r
+       mov     ebx,[arm64_instruction2]        ;element\r
+       shr     al,1\r
+       lea     eax,[eax+eax]\r
+       rcl     al,1\r
+       jmp     ARM64_arithmetic6.vector_encode\r
+\r
+ARM64_arithmetic18_long2:\r
+       ;used by SMLAL2, SMLSL2, SMULL2, UMLAL2, UMLSL2, UMULL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_vect_v16b>,\         ;0=vd,vn,vm\r
+       <TMPL_never>,\                                          ;1=-\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_element_h>,\     ;3=vd,vn,vm.h[]\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;4=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_element_s>       ;5=vd,vn,vm.s[]\r
+       jmp     ARM64_arithmetic18_long.do\r
+\r
+ARM64_smov:\r
+       ;used by SMOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_vect_element_b>,\         ;0=wd,vn.b[]\r
+       <TMPL_word_z_reg,TMPL_vect_element_h>,\         ;1=wd,vn.h[]\r
+       <TMPL_never>,\                                  ;2=-\r
+       <TMPL_dword_z_reg,TMPL_vect_element_b>,\        ;3=xd,vn.b[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_h>,\        ;4=xd,vn.h[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_s>          ;5=xd,vn.s[]\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,3\r
+       jb      .Q_okay\r
+       or      ebp,1 shl 30\r
+       sub     al,3\r
+    .Q_okay:\r
+       lea     ecx,[eax+16]\r
+       mov     eax,[immediate_value2]\r
+       add     eax,eax\r
+       inc     eax\r
+       shl     eax,cl\r
+       or      ebp,eax\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+\r
+ARM64_umov:\r
+       ;used by UMOV\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_word_z_reg,TMPL_vect_element_b>,\         ;0=wd,vn.b[]\r
+       <TMPL_word_z_reg,TMPL_vect_element_h>,\         ;1=wd,vn.h[]\r
+       <TMPL_word_z_reg,TMPL_vect_element_s>,\         ;2=wd,vn.s[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_d>,\        ;3=xd,vn.d[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_b>,\        ;4=xd,vn.b[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_h>,\        ;5=xd,vn.h[]\r
+       <TMPL_dword_z_reg,TMPL_vect_element_s>          ;6=xd,vn.s[]\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       and     al,3\r
+       cmp     al,3\r
+       setae   cl\r
+       shl     ecx,30\r
+       or      ebp,ecx\r
+       lea     ecx,[eax+16]\r
+       mov     eax,[immediate_value2]\r
+       add     eax,eax\r
+       inc     eax\r
+       shl     eax,cl\r
+       or      ebp,eax\r
+       jmp     ARM64_dz_nz_mz.encode_rd\r
+\r
+ARM64_vector_scalar_bhsd_two_reg_q:\r
+       ;used by SQABS, SQNEG, SUQADD, USQADD\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b>,\         ; 0=vd,vn\r
+       <TMPL_vect_v16b,TMPL_vect_v16b>,\       ; 1=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4h>,\         ; 2=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v8h>,\         ; 3=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ; 4=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>,\         ; 5=vd,vn\r
+       <TMPL_never>,\                          ; 6=-\r
+       <TMPL_vect_v2d,TMPL_vect_v2d>,\         ; 7=vd,vn\r
+       <TMPL_vect_breg,TMPL_vect_breg>,\       ; 8=bd,bn\r
+       <TMPL_vect_hreg,TMPL_vect_hreg>,\       ; 9=hd,hn\r
+       <TMPL_vect_sreg,TMPL_vect_sreg>,\       ;10=sd,sn\r
+       <TMPL_vect_dreg,TMPL_vect_dreg>         ;11=dd,dn\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,7\r
+       jbe     ARM64_arithmetic1.vector_encode\r
+       sub     al,8\r
+       or      ebp,5 shl 28\r
+       jmp     ARM64_scalar_sd_four_reg.encode_size\r
+\r
+ARM64_vector_scalar_bhsd_three_reg_q:\r
+       ;used by SQADD, SQRSHL, SQSUB, UQADD, UQRSHL, UQSUB\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ; 0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ; 1=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ; 2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ; 3=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ; 4=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ; 5=vd,vn,vm\r
+       <TMPL_never>,\                                          ; 6=-\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\           ; 7=vd,vn,vm\r
+       <TMPL_vect_breg,TMPL_vect_breg,TMPL_vect_breg>,\        ; 8=bd,bn,bm\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\        ; 9=hd,hn,hm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\        ;10=sd,sn,sm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>          ;11=dd,dn,dm\r
+    .encode:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,7\r
+       jbe     ARM64_arithmetic1.vector_encode\r
+       sub     al,8\r
+       or      ebp,5 shl 28\r
+       jmp     ARM64_scalar_sd_four_reg.encode_size\r
+\r
+ARM64_arithmetic19_long:\r
+       ;used by SQDMLAL, SQDMLSL, SQDMULL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_v4h>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_vect_element_h>,\     ;1=vd,vn,vm.h[]\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_v2s>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_vect_element_s>       ;3=vd,vn,vm.s[]\r
+    .do:\r
+       add     al,2\r
+       jmp     ARM64_arithmetic18_long.do\r
+\r
+ARM64_arithmetic19_long2:\r
+       ;used by SQDMLAL2, SQDMLSL2, SQDMULL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_v8h>,\           ;0=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_vect_element_h>,\     ;1=vd,vn,vm.h[]\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;2=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_vect_element_s>       ;3=vd,vn,vm.s[]\r
+       jmp     ARM64_arithmetic19_long.do\r
+\r
+ARM64_arithmetic20:\r
+       ;used by SQDMULH, SQRDMULH\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ; 0=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_element_h>,\     ; 1=vd,vn,vm.h[]\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ; 2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_element_h>,\     ; 3=vd,vn,vm.h[]\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ; 4=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_element_s>,\     ; 5=vd,vn,vm.s[]\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ; 6=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_element_s>,\     ; 7=vd,vn,vm.s[]\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\        ; 8=hd,hn,hm\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_element_h>,\   ; 9=hd,hn,vm.h[]\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\        ;10=sd,sn,sm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_element_s>     ;11=sd,sn,vm.s[]\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       cmp     al,7\r
+       jbe     .vector\r
+       sub     al,8\r
+       shr     al,1\r
+       lea     eax,[eax+eax]\r
+       rcl     al,1\r
+       or      [arm64_instruction],5 shl 28\r
+       or      [arm64_instruction2],5 shl 28\r
+    .vector:\r
+       add     al,4\r
+       jmp     ARM64_arithmetic17.do\r
+\r
+ARM64_vector_scalar_narrow_shift_high:\r
+       ;used by SQRSHRN, SQRSHRUN, SQSHRN, SQSHRUN, UQRSHRN, UQSHRN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8h,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4s,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2d,TMPL_imm>,\        ;2=vd,vn,imm\r
+       <TMPL_vect_breg,TMPL_vect_hreg,TMPL_imm>,\      ;3=bd,hn,imm\r
+       <TMPL_vect_hreg,TMPL_vect_sreg,TMPL_imm>,\      ;4=hd,sn,imm\r
+       <TMPL_vect_sreg,TMPL_vect_dreg,TMPL_imm>        ;5=sd,dn,imm\r
+       cmp     al,3\r
+       jb      ARM64_vector_narrow_shift_low.encode\r
+       sub     al,3\r
+       or      [arm64_instruction],0x5 shl 28\r
+       jmp     ARM64_vector_narrow_shift_low.encode\r
+\r
+ARM64_vector_scalar_bhsd_shift_reg_imm:\r
+       ;used by SQSHL, UQSHL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\           ; 0=vd,vn,vm\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\                ; 1=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\        ; 2=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\              ; 3=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\           ; 4=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\                ; 5=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\           ; 6=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\                ; 7=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\           ; 8=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\                ; 9=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\           ;10=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\                ;11=vd,vn,imm\r
+       <TMPL_never>,\                                          ;12=-\r
+       <TMPL_never>,\                                          ;13=-\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>,\           ;14=vd,vn,vm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\                ;15=vd,vn,imm\r
+       <TMPL_vect_breg,TMPL_vect_breg,TMPL_vect_breg>,\        ;16=bd,bn,bm\r
+       <TMPL_vect_breg,TMPL_vect_breg,TMPL_imm>,\              ;17=bd,bn,imm\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_vect_hreg>,\        ;18=hd,hn,hm\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_imm>,\              ;19=hd,hn,imm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_vect_sreg>,\        ;20=sd,sn,sm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\              ;21=sd,sn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_vect_dreg>,\        ;22=dd,dn,dm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>                ;23=dd,dn,imm\r
+    .do:\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       shr     al,1\r
+       jc      .immediate\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       cmp     al,7\r
+       jbe     ARM64_arithmetic1.vector_encode\r
+       sub     al,8\r
+       or      ebp,5 shl 28\r
+       jmp     ARM64_scalar_sd_four_reg.encode_size\r
+    .immediate:\r
+       mov     ebp,[arm64_instruction2]        ;recover the other template\r
+       cmp     al,7\r
+       jbe     ARM64_vector_scalar_bhsd_two_reg_left_imm.immediate_encode\r
+       sub     al,8\r
+       add     al,al\r
+       or      ebp,5 shl 28\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.immediate_encode\r
+\r
+ARM64_vector_scalar_bhsd_shift_imm:\r
+       ;used by SQSHLU\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_imm>,\                ; 0=vd,vn,imm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_imm>,\              ; 1=vd,vn,imm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_imm>,\                ; 2=vd,vn,imm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_imm>,\                ; 3=vd,vn,imm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_imm>,\                ; 4=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_imm>,\                ; 5=vd,vn,imm\r
+       <TMPL_never>,\                                          ; 6=-\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_imm>,\                ; 7=vd,vn,imm\r
+       <TMPL_vect_breg,TMPL_vect_breg,TMPL_imm>,\              ; 8=bd,bn,imm\r
+       <TMPL_vect_hreg,TMPL_vect_hreg,TMPL_imm>,\              ; 9=hd,hn,imm\r
+       <TMPL_vect_sreg,TMPL_vect_sreg,TMPL_imm>,\              ;10=sd,sn,imm\r
+       <TMPL_vect_dreg,TMPL_vect_dreg,TMPL_imm>                ;11=dd,dn,imm\r
+       lea     eax,[eax+eax+1]\r
+       jmp     ARM64_vector_scalar_bhsd_shift_reg_imm.do\r
+\r
+ARM64_vector_scalar_narrow_extract_low:\r
+       ;used by SQXTN, SQXTUN, UQXTN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8h>,\         ;0=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4s>,\         ;1=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2d>,\         ;2=vd,vn\r
+       <TMPL_vect_breg,TMPL_vect_hreg>,\       ;3=bd,hn\r
+       <TMPL_vect_hreg,TMPL_vect_sreg>,\       ;4=hd,sn\r
+       <TMPL_vect_sreg,TMPL_vect_dreg>         ;5=sd,dn\r
+       cmp     al,3\r
+       jb      ARM64_vector_narrow_low.encode\r
+       sub     al,3\r
+       or      [arm64_instruction],0x5 shl 28\r
+       jmp     ARM64_vector_narrow_low.encode\r
+\r
+ARM64_vector_narrow_extract_low:\r
+       ;used by XTN\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8h>,\         ;0=vd,vn\r
+       <TMPL_vect_v4h,TMPL_vect_v4s>,\         ;1=vd,vn\r
+       <TMPL_vect_v2s,TMPL_vect_v2d>           ;2=vd,vn\r
+       jmp     ARM64_vector_narrow_low.encode\r
+\r
+ARM64_vector_narrow_extract_high:\r
+       ;used by SQXTN2, SQXTUN2, UQXTN2, XTN2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v16b,TMPL_vect_v8h>,\        ;0=vd,vn\r
+       <TMPL_vect_v8h,TMPL_vect_v4s>,\         ;1=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v2d>           ;2=vd,vn\r
+       jmp     ARM64_vector_narrow_low.encode\r
+\r
+ARM64_vector_scalar_bhs_long_imm:\r
+       ;used by SSHLL, USHLL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b,TMPL_imm>,\        ;0=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v4h,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v2s,TMPL_imm>          ;2=vd,vn,imm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.do\r
+\r
+ARM64_vector_scalar_bhs_long2_imm:\r
+       ;used by SSHLL2, USHLL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b,TMPL_imm>,\       ;0=vd,vn,imm\r
+       <TMPL_vect_v4s,TMPL_vect_v8h,TMPL_imm>,\        ;1=vd,vn,imm\r
+       <TMPL_vect_v2d,TMPL_vect_v4s,TMPL_imm>          ;2=vd,vn,imm\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.do\r
+\r
+ARM64_vector_scalar_bhs_long:\r
+       ;used by SXTL, UXTL\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v8b>,\ ;0=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4h>,\ ;1=vd,vn\r
+       <TMPL_vect_v2d,TMPL_vect_v2s>   ;2=vd,vn\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.do\r
+\r
+ARM64_vector_scalar_bhs_long2:\r
+       ;used by SXTL2, UXTL2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8h,TMPL_vect_v16b>,\        ;0=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v8h>,\         ;1=vd,vn\r
+       <TMPL_vect_v2d,TMPL_vect_v4s>           ;2=vd,vn\r
+       add     al,al\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg_left_imm.do\r
+\r
+ARM64_tb1:\r
+       ;used by TBL, TBX\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_list_16b,TMPL_vect_v8b>,\      ;0=vd,{vn.16b},vm\r
+       <TMPL_vect_v16b,TMPL_vect_list_16b,TMPL_vect_v16b>      ;1=vd,{vn.16b},vm\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_SIMD shr 32\r
+       jz      ERROR_requires_cpu64_capability_SIMD\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       movzx   edx,[simd_reg_list_count]\r
+       shl     eax,30\r
+       or      ebp,eax                         ;set Q\r
+       dec     edx\r
+       shl     edx,13\r
+       or      ebp,edx                         ;set len\r
+       jmp     ARM64_arithmetic1.encode_rm\r
+\r
+ARM64_vector_bhsd_three_reg:\r
+       ;used by TRN1, TRN2, UZP1, UZP2, ZIP1, ZIP2\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v8b,TMPL_vect_v8b,TMPL_vect_v8b>,\   ;0=vd,vn,vm\r
+       <TMPL_vect_v16b,TMPL_vect_v16b,TMPL_vect_v16b>,\;1=vd,vn,vm\r
+       <TMPL_vect_v4h,TMPL_vect_v4h,TMPL_vect_v4h>,\   ;2=vd,vn,vm\r
+       <TMPL_vect_v8h,TMPL_vect_v8h,TMPL_vect_v8h>,\   ;3=vd,vn,vm\r
+       <TMPL_vect_v2s,TMPL_vect_v2s,TMPL_vect_v2s>,\   ;4=vd,vn,vm\r
+       <TMPL_vect_v4s,TMPL_vect_v4s,TMPL_vect_v4s>,\   ;5=vd,vn,vm\r
+       <TMPL_never>,\                                  ;6=dd,dn,dm\r
+       <TMPL_vect_v2d,TMPL_vect_v2d,TMPL_vect_v2d>     ;7=vd,vn,vm\r
+       jmp     ARM64_vector_scalar_bhsd_two_reg.encode\r
+\r
+ARM64_arithmetic21:\r
+       ;used by URECPE, URSQRTE\r
+       call    decode_template\r
+    TEMPLATE \\r
+       <TMPL_vect_v2s,TMPL_vect_v2s>,\         ;0=vd,vn\r
+       <TMPL_vect_v4s,TMPL_vect_v4s>           ;1=vd,vn\r
+       test    [cpu_capability_flags2],1 shl CPU64_CAPABILITY_FP shr 32\r
+       jz      ERROR_requires_cpu64_capability_FP\r
+       mov     ebp,[arm64_instruction]         ;recover the template\r
+       shl     eax,30\r
+       or      ebp,eax                 ;set Q\r
+       jmp     ARM64_arithmetic1.encode_rn\r
+\r
+;CRC\r
+\r
+CRC32_polynomial_ISO3309       = 0xedb88320    ;x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + x^0\r
+CRC32_table_length             = 256*4*4       ;a constant, don't adjust\r
+CRC32_loop_size                        = 4             ;an optimising parameter, adjust if you want\r
+\r
+CRC_32:\r
+       ;used by CRC32\r
+       ;crc32 dest_var from start,length[,polynomial]\r
+       lodsw\r
+       cmp     ax,0x1128               ;'(' + 0x11\r
+       jne     ERROR_parameter_n_not_valid.first\r
+       lodsd\r
+       push    eax                     ;save dest_var\r
+       lodsb\r
+       cmp     al,')'\r
+       jne     ERROR_parameter_n_not_valid.first\r
+       mov     [operand_size],1\r
+       and     dword[value],0\r
+       and     dword[value+4],0\r
+       lodsb\r
+       cmp     al,82h                  ;from?\r
+       jne     ERROR_parameter_n_not_valid.second\r
+       call    get_data_point\r
+       sbb     ecx,ecx\r
+       not     ecx\r
+       and     ebx,ecx\r
+       lodsb\r
+       cmp     al,','\r
+       jnz     ERROR_parameter_n_not_valid.second\r
+       push    ebx\r
+       call    get_value\r
+       pop     ebx\r
+       cmp     [value_type],0\r
+       jne     ERROR_parameter_n_not_valid.third\r
+       test    edx,edx\r
+       jne     ERROR_parameter_n_not_valid.third\r
+       lea     edx,[eax+ebx]\r
+       sub     edx,[ds:ebp+0x18]\r
+       cmp     [ds:ebp+0x1c],edx\r
+       sbb     ecx,ecx\r
+       not     ecx\r
+       and     ebx,ecx\r
+       mov     ebp,CRC32_polynomial_ISO3309\r
+       push    ebx eax\r
+       cmp     byte[esi],','           ;is the polynomial specified?\r
+       jnz     .construct\r
+       inc     esi\r
+       call    get_value\r
+       cmp     [value_type],0\r
+       jne     ERROR_parameter_n_not_valid.fourth\r
+       test    edx,edx\r
+       jne     ERROR_parameter_n_not_valid.fourth\r
+       mov     ebp,eax\r
+    .construct:\r
+       call    CRC32_construct_table\r
+       pop     ecx edx\r
+       test    edx,edx\r
+       jz      .out_of_range\r
+       or      eax,-1                  ;eax=crc\r
+       test    ecx,ecx\r
+       jz      .done\r
+       test    dl,3\r
+       jne     .align\r
+    .begin:\r
+       sub     ecx,CRC32_loop_size*8\r
+       jb      .tail\r
+    .main_loop:\r
+        repeat CRC32_loop_size\r
+       xor     eax,[edx+(%-1)*8]\r
+       movzx   ebp,al\r
+       mov     ebx,[edi+3*256*4+4*ebp]\r
+       movzx   ebp,ah\r
+       xor     ebx,[edi+2*256*4+4*ebp]\r
+       shr     eax,16\r
+       movzx   ebp,al\r
+       xor     ebx,[edi+1*256*4+4*ebp]\r
+       shr     eax,8\r
+       xor     ebx,[edi+0*256*4+4*eax]\r
+       xor     ebx,[edx+(%-1)*8+4]\r
+       movzx   ebp,bl\r
+       mov     eax,[edi+3*256*4+4*ebp]\r
+       movzx   ebp,bh\r
+       xor     eax,[edi+2*256*4+4*ebp]\r
+       shr     ebx,16\r
+       movzx   ebp,bl\r
+       xor     eax,[edi+1*256*4+4*ebp]\r
+       shr     ebx,8\r
+       xor     eax,[edi+0*256*4+4*ebx]\r
+        end repeat\r
+       add     edx,CRC32_loop_size*8\r
+       sub     ecx,CRC32_loop_size*8\r
+       jae     .main_loop\r
+    .tail:\r
+       sub     ecx,4-CRC32_loop_size*8\r
+       jb      .finish\r
+    .tail_loop:\r
+       xor     eax,[edx]\r
+       add     edx,4\r
+       movzx   ebp,al\r
+       mov     ebx,[edi+3*256*4+4*ebp]\r
+       movzx   ebp,ah\r
+       xor     ebx,[edi+2*256*4+4*ebp]\r
+       shr     eax,16\r
+       movzx   ebp,al\r
+       xor     ebx,[edi+1*256*4+4*ebp]\r
+       shr     eax,8\r
+       xor     ebx,[edi+0*256*4+4*eax]\r
+       mov     eax,ebx\r
+       sub     ecx,4\r
+       jae     .tail_loop\r
+    .finish:\r
+       sub     ecx,1-4\r
+       jb      .done\r
+    .prolog:\r
+       movzx   ebx,byte[edx]\r
+       xor     bl,al\r
+       shr     eax,8\r
+       xor     eax,[edi+4*ebx]\r
+       inc     edx\r
+       dec     ecx\r
+       jns     .prolog\r
+    .done:\r
+       mov     dword[value],eax\r
+    .store_crc:\r
+       mov     [value_sign],0\r
+       mov     eax,dword[value]\r
+       mov     edx,dword[value+4]\r
+       pop     ebx\r
+       xor     cx,cx\r
+       jmp     make_constant\r
+    .align:\r
+       movzx   ebx,byte[edx]\r
+       xor     bl,al\r
+       shr     eax,8\r
+       xor     eax,[edi+4*ebx]\r
+       inc     edx\r
+       dec     ecx\r
+       je      .done\r
+       test    dl,3\r
+       jne     .align\r
+       jmp     .begin\r
+    .out_of_range:\r
+       call    recoverable_overflow\r
+       jmp     .store_crc\r
+\r
+CRC32_construct_table:\r
+       lea     eax,[edi+CRC32_table_length]\r
+       cmp     eax,[tagged_blocks]\r
+       jae     out_of_memory\r
+       xor     edx,edx\r
+    .a:        mov     eax,edx\r
+       mov     ebx,8\r
+    .b:        shr     eax,1\r
+       sbb     ecx,ecx\r
+       and     ecx,ebp\r
+       xor     eax,ecx\r
+       dec     ebx\r
+       jnz     .b\r
+       mov     [edi+4*edx],eax\r
+       inc     dl\r
+       jnz     .a\r
+       xor     edx,edx\r
+    .c:        mov     eax,[edi+4*edx]\r
+       mov     ebx,3\r
+       lea     ebp,[edi+4*edx+1*256*4]\r
+    .d:        movzx   ecx,al\r
+       mov     ecx,[edi+4*ecx]\r
+       shr     eax,8\r
+       xor     eax,ecx\r
+       mov     [ebp],eax\r
+       add     ebp,1*256*4\r
+       dec     ebx\r
+       jnz     .d\r
+       inc     dl\r
+       jnz     .c\r
+       ret\r
+\r
+;shared errors\r
+\r
+ERROR_illegal_instruction              =illegal_instruction\r
+ERROR_value_out_of_range               =value_out_of_range\r
+ERROR_relative_jump_out_of_range       =relative_jump_out_of_range\r
+ERROR_operand_sizes_do_not_match       =operand_sizes_do_not_match\r
+\r
+ERROR_code_is_not_in_a_section:\r
+       call    assembler_error\r
+       db      'Code placed before section defined',0\r
+ERROR_expecting_section_name:\r
+       call    assembler_error\r
+       db      'Section directive must be followed by the section name',0\r
+ERROR_duplicate_align_setting:\r
+       call    assembler_error\r
+       db      'An alignment setting was specified twice',0\r
+ERROR_duplicate_flag_setting:\r
+       call    assembler_error\r
+       db      'A flag setting was specified twice',0\r
+ERROR_invalid_use_of_symbol_in_align:\r
+       call    assembler_error\r
+       db      'Invalid use of symbol for "align" setting',0\r
+ERROR_invalid_use_of_symbol_in_at:\r
+       call    assembler_error\r
+       db      'Invalid use of symbol for "at" setting',0\r
+ERROR_section_flags_zero:\r
+       call    assembler_error\r
+       db      'At least one section flag (executable, readable or writeable) must be specified',0\r
+ERROR_section_align_zero:\r
+       call    assembler_error\r
+       db      'Section alignment must be specified',0\r
+ERROR_line_processing_error:\r
+       call    fatal_error\r
+       db      'Fatal: Failure when processing line numbers. There is a bug!',0\r
+ERROR_thumb_recode_error:\r
+       call    assembler_error\r
+       db      'Fatal: Unable to recode instruction for thumb. There is a bug!',0\r
+ERROR_org_not_allowed:\r
+       call    assembler_error\r
+       db      '"ORG" not allowed in DWARF, use "SECTION ... at X" instead',0\r
+ERROR_section_at_not_aligned:\r
+       call    assembler_error\r
+       db      'Section alignement and "AT" specified are not compatible',0\r
+ERROR_instruction_not_aligned:\r
+       call    assembler_error\r
+       db      'Instruction origin not aligned',0\r
+ERROR_relative_jump_not_aligned:\r
+       call    assembler_error\r
+       db      'Relative jump destination not aligned',0\r
+ERROR_shift_value_out_of_range:\r
+    .0:\r
+       call    assembler_error\r
+       db      'Shift value out of range, only 0 allowed',0\r
+    .0or1:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 0 or 1)',0\r
+    .0or2:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 0 or 2)',0\r
+    .0or3:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 0 or 3)',0\r
+    .0or4:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 0 or 4)',0\r
+    .0_3:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-3)',0\r
+    .0_4:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-4)',0\r
+    .0_7:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-7)',0\r
+    .0_8:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-8)',0\r
+    .0_15:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-15)',0\r
+    .0or16:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0 or 16)',0\r
+    .0_16:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-16)',0\r
+    .0_24:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0, 8, 16 or 24)',0\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-31)',0\r
+    .0_32:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-32)',0\r
+    .0_48:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0, 16, 32 or 48)',0\r
+    .1:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 1)',0\r
+    .2:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 2)',0\r
+    .8:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 8)',0\r
+    .12:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 0 or 12)',0\r
+    .16:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 16)',0\r
+    .32:\r
+       call    assembler_error\r
+       db      'Shift value out of range (must be 32)',0\r
+    .1_8:\r
+       call    assembler_error\r
+       db      'Shift value out of range (1-8)',0\r
+    .1_16:\r
+       call    assembler_error\r
+       db      'Shift value out of range (1-16)',0\r
+    .1_31:\r
+       call    assembler_error\r
+       db      'Shift value out of range (1-31)',0\r
+    .1_32:\r
+       call    assembler_error\r
+       db      'Shift value out of range (1-32)',0\r
+    .0_63:\r
+       call    assembler_error\r
+       db      'Shift value out of range (0-63)',0\r
+    .1_64:\r
+       call    assembler_error\r
+       db      'Shift value out of range (1-64)',0\r
+ERROR_immediate_offset_out_of_range:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range',0\r
+    .0:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 0)',0\r
+    .1:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 1)',0\r
+    .2:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 2)',0\r
+    .3:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 3)',0\r
+    .4:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 4)',0\r
+    .6:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 6)',0\r
+    .8:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 8)',0\r
+    .12:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 12)',0\r
+    .16:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 16)',0\r
+    .24:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 24)',0\r
+    .32:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 32)',0\r
+    .48:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 48)',0\r
+    .64:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (must be 64)',0\r
+    .0xff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-0xff to 0xff)',0\r
+    .0x3fc:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-0xff to 0xff)*4',0\r
+    .0xfff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-0xfff to 0xfff)',0\r
+    .0_0xffffff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xffffff)',0\r
+    .0_0x3f:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x3f)',0\r
+    .0_0xff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xff)',0\r
+    .0_0xfff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff)',0\r
+    .0_0xfff.m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff) and (-0x100 to +0xff)',0\r
+    .0_0x1ffe.m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff)*2 and (-0x100 to +0xff)',0\r
+    .0_0x3ffc.m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff)*4 and (-0x100 to +0xff)',0\r
+    .0_0x7ff8.m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff)*8 and (-0x100 to +0xff)',0\r
+    .0_0xfff0.m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xfff)*16 and (-0x100 to +0xff)',0\r
+    .0_0xffff:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xffff)',0\r
+    .0_0x1f:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x1f)',0\r
+    .0_0x3e:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x1f)*2',0\r
+    .0_0x7c:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x1f)*4',0\r
+    .0_0xfc:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x3f)*4',0\r
+    .0_0x1fc:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0x7f)*4',0\r
+    .0_0x3fc:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (0 to 0xff)*4',0\r
+    .m28_0:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-7 to 0)*4',0\r
+    .m256_252:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-64 to +63)*4, (-256 to +252 in multiples of 4)',0\r
+    .m256_255:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-256 to +255)',0\r
+    .m512_504:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-64 to +63)*8, (-512 to +504 in multiples of 8)',0\r
+    .m1024_1008:\r
+       call    assembler_error\r
+       db      'Immediate offset out of range (-64 to +63)*16, (-1024 to +1008 in multiples of 16)',0\r
+ERROR_immediate_value_out_of_range:\r
+    .0_1:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (can only be 0 or 1)',0\r
+    .0_7:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 7)',0\r
+    .0_15:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 15)',0\r
+    .0_16:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 16)',0\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 31)',0\r
+    .0_0x7f:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0x7f)',0\r
+    .0_0xff:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xff)',0\r
+    .0_0xff_lsl_8:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xff with optional left shift of 8)',0\r
+    .0_0xff_msl:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xff with optional ones shift of 8 or 16 or left shift of 8, 16 or 24)',0\r
+    .0_0xff_lsl_24:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xff with optional left shift of 8, 16 or 24)',0\r
+    .0_0xfff:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xfff)',0\r
+    .0_0xfff_lsl_12:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xfff with optional left shift of 12)',0\r
+    .0_0xffff:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xffff)',0\r
+    .0_0xffff_lsl_16:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xffff with optional left shift of 16)',0\r
+    .0_0xffff_lsl_48:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (0 to 0xffff with optional left shift of 16, 32 or 48)',0\r
+    .1_16:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (1 to 16)',0\r
+    .1_32:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (1 to 32)',0\r
+    .1_64:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (1 to 64)',0\r
+    .m64_63:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (-64 to 63)',0\r
+    .quarter:\r
+       call    assembler_error\r
+       db      'Immediate value out of range (-31.0 to +31.0)',0\r
+ERROR_byte_value_out_of_range:\r
+       call    assembler_error\r
+       db      'Byte value out of range (0 to 0xff)',0\r
+ERROR_rotation_value_out_of_range:\r
+       call    assembler_error\r
+       db      'Rotation value out of range (0 to 0xf)*2',0\r
+ERROR_byte_rotation_in_thumb:\r
+       call    assembler_error\r
+       db      'Explicit byte and rotation values not valid in THUMB mode',0\r
+ERROR_count_value_out_of_range:\r
+    .1_4:\r
+       call    assembler_error\r
+       db      'Count value out of range (1 to 4)',0\r
+ERROR_lsb_out_of_range:\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'LSB value out of range (0 to 31)',0\r
+    .0_63:\r
+       call    assembler_error\r
+       db      'LSB value out of range (0 to 63)',0\r
+ERROR_immr_out_of_range:\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'IMMR value out of range (0 to 31)',0\r
+    .0_63:\r
+       call    assembler_error\r
+       db      'IMMR value out of range (0 to 63)',0\r
+ERROR_imms_out_of_range:\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'IMMS value out of range (0 to 31)',0\r
+    .0_63:\r
+       call    assembler_error\r
+       db      'IMMS value out of range (0 to 63)',0\r
+ERROR_bit_out_of_range:\r
+    .0_31:\r
+       call    assembler_error\r
+       db      'Bit number out of range (0 to 31)',0\r
+    .0_63:\r
+       call    assembler_error\r
+       db      'Bit number out of range (0 to 63)',0\r
+ERROR_width_out_of_range:\r
+       call    assembler_error\r
+       db      'Width field + LSB cannot exceed 32',0\r
+    .64:\r
+       call    assembler_error\r
+       db      'Width field + LSB cannot exceed 64',0\r
+    .1_32:\r
+       call    assembler_error\r
+       db      'Width value out of range (1 to 32)',0\r
+    .1_64:\r
+       call    assembler_error\r
+       db      'Width value out of range (1 to 64)',0\r
+ERROR_constant_cannot_be_encoded:\r
+       call    assembler_error\r
+       db      'Constant cannot be encoded (0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 or 10.0 only)',0\r
+ERROR_immediate_cannot_be_encoded:\r
+       call    assembler_error\r
+       db      'Immediate value cannot be encoded',0\r
+ERROR_must_have_writeback_operator:\r
+       call    assembler_error\r
+       db      'Must have writeback operator "!"',0\r
+ERROR_option_out_of_range:\r
+       call    assembler_error\r
+       db      'Option out of range (0x00-0xff)',0\r
+ERROR_opcode4_out_of_range:\r
+       call    assembler_error\r
+       db      'Coprocessor opcode out of range (0-15) in second parameter',0\r
+ERROR_opcode3_out_of_range:\r
+       call    assembler_error\r
+       db      'Coprocessor opcode out of range (0-7) in sixth parameter',0\r
+ERROR_expecting_curly_bracket_close:\r
+       call    assembler_error\r
+       db      'Expecting curly bracket "}"',0\r
+ERROR_expecting_square_bracket_close:\r
+       call    assembler_error\r
+       db      'Expecting square bracket "]"',0\r
+ERROR_repeated_register_in_list:\r
+       call    assembler_error\r
+       db      'Repeated register in list',0\r
+ERROR_instruction_not_16bit:\r
+       call    assembler_error\r
+       db      'Instruction not encodable in THUMB',0\r
+ERROR_instruction_not_t2ee:\r
+       call    assembler_error\r
+       db      'Instruction not encodable in THUMBEE',0\r
+ERROR_instruction_needs_t2ee:\r
+       call    assembler_error\r
+       db      'Instruction requires THUMBEE mode, use "THUMBEE" to select',0\r
+ERROR_instruction_not_32bit:\r
+       call    assembler_error\r
+       db      'Instruction not encodable in ARM',0\r
+ERROR_instruction_not_64bit:\r
+       call    assembler_error\r
+       db      'Instruction not encodable in ARM64',0\r
+ERROR_register_out_of_range:\r
+    .r0_r7:\r
+       call    assembler_error\r
+       db      'Register out of range (R0-R7)',0\r
+    .r0_r7_sp_pc:\r
+       call    assembler_error\r
+       db      'Register out of range (R0-R7, SP or PC)',0\r
+    .must_be_sp:\r
+       call    assembler_error\r
+       db      'Register must be SP',0\r
+    .sp:\r
+       call    assembler_error\r
+       db      'Register cannot be SP',0\r
+    .pc:\r
+       call    assembler_error\r
+       db      'Register cannot be PC',0\r
+    .sp_pc:\r
+       call    assembler_error\r
+       db      'Register cannot be SP or PC',0\r
+    .too_complex:\r
+       call    assembler_error\r
+       db      'Expression can only have one register with no scaling',0\r
+    .only_base:\r
+       call    assembler_error\r
+       db      'Expression can only have an unaligned register (R0-R15)',0\r
+    .only_base64:\r
+       call    assembler_error\r
+       db      'Expression can only have 64-bit register (X0-X30,SP)',0\r
+ERROR_dest_cannot_be_sp_pc:\r
+       call    assembler_error\r
+       db      'Destination register cannot be SP or PC',0\r
+ERROR_offset_register_cannot_be_sp_pc:\r
+       call    assembler_error\r
+       db      'Offset register cannot be SP or PC',0\r
+ERROR_dest_and_source_must_be_the_same:\r
+       call    assembler_error\r
+       db      'Destination register and first source register must be the same',0\r
+ERROR_r14_not_valid:\r
+    .first:\r
+       call    assembler_error\r
+       db      'LR (R14) not valid as first parameter',0\r
+    .second:\r
+       call    assembler_error\r
+       db      'LR (R14) not valid as second parameter',0\r
+ERROR_r13_not_valid:\r
+       call    assembler_error\r
+       db      'SP (R13) not valid',0\r
+    .second:\r
+       call    assembler_error\r
+       db      'SP (R13) not valid as second parameter',0\r
+ERROR_r13_r15_not_valid:\r
+       call    assembler_error\r
+       db      'SP (R13) and PC (R15) not valid',0\r
+    .third:\r
+       call    assembler_error\r
+       db      'SP (R13) and PC (R15) not valid as third parameter',0\r
+ERROR_r15_not_valid:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid',0\r
+    .all:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid for any parameter',0\r
+    .first:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as first parameter',0\r
+    .second:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as second parameter',0\r
+    .third:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as third parameter',0\r
+    .fourth:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as fourth parameter',0\r
+    .base:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as base register',0\r
+    .post:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid as base register with post update',0\r
+ERROR_register_writeback_not_allowed:\r
+       call    assembler_error\r
+       db      'Register writeback not allowed here',0\r
+ERROR_destination_register_not_allowed_in_list:\r
+       call    assembler_error\r
+       db      'Destination register with writeback not allowed in source list',0\r
+ERROR_source_and_dest_must_differ:\r
+       call    assembler_error\r
+       db      'Source and destination registers must differ',0\r
+ERROR_base_and_dest_must_differ_with_writeback:\r
+       call    assembler_error\r
+       db      'Base and destination registers must differ when using writeback',0\r
+ERROR_offset_and_dest_must_differ_with_LDRD:\r
+       call    assembler_error\r
+       db      'Offset and destination registers must differ with LDRD',0\r
+ERROR_source_register_must_be_even:\r
+       call    assembler_error\r
+       db      'First source register must be even',0\r
+ERROR_destination_register_must_be_even:\r
+       call    assembler_error\r
+       db      'First destination register must be even',0\r
+ERROR_source_registers_must_be_consecutive:\r
+       call    assembler_error\r
+       db      'Source registers must be consecutive',0\r
+ERROR_destination_registers_must_be_consecutive:\r
+       call    assembler_error\r
+       db      'Destination registers must be consecutive',0\r
+ERROR_source_rm_and_dest_must_differ:\r
+       call    assembler_error\r
+       db      'Destination and first source must differ',0\r
+ERROR_base_and_offset_must_differ_with_writeback:\r
+       call    assembler_error\r
+       db      'Base and offset registers must differ when using writeback',0\r
+ERROR_must_use_full_psr:\r
+       call    assembler_error\r
+       db      'Must use full PSR here, either APSR, CPSR or SPSR',0\r
+ERROR_must_specify_psr_bit_fields:\r
+       call    assembler_error\r
+       db      'Must specify PSR bit fields here, (APSR_nzcvqg, CPSR_fsxc or SPSR_fsxc)',0\r
+ERROR_memory_address_cannot_be_source_or_dest:\r
+       call    assembler_error\r
+       db      'Address register cannot be source or destination',0\r
+ERROR_dest_cannot_be_source_or_memory_address:\r
+       call    assembler_error\r
+       db      'Destination cannot be source or address register',0\r
+ERROR_destination_registers_must_differ:\r
+       call    assembler_error\r
+       db      'Destination registers must differ',0\r
+ERROR_empty_set:\r
+       call    assembler_error\r
+       db      'Cannot use empty set',0\r
+ERROR_sp_in_set:\r
+       call    assembler_error\r
+       db      'SP (R13) not valid in register list',0\r
+ERROR_pc_in_set:\r
+       call    assembler_error\r
+       db      'PC (R15) not valid in register list',0\r
+ERROR_invalid_set_with_lr_pc:\r
+       call    assembler_error\r
+       db      'Cannot have LR (R14) and PC (R15) both in the list',0\r
+ERROR_shift_type_must_be_LSL:\r
+       call    assembler_error\r
+       db      'Shift type must be LSL',0\r
+ERROR_shift_type_must_be_LSL_or_ASR:\r
+       call    assembler_error\r
+       db      'Shift type must be LSL or ASR',0\r
+ERROR_shift_type_must_be_ASR:\r
+       call    assembler_error\r
+       db      'Shift type must be ASR',0\r
+ERROR_shift_type_must_be_ROR:\r
+       call    assembler_error\r
+       db      'Shift type must be ROR',0\r
+ERROR_extend_type:\r
+       call    assembler_error\r
+       db      'Extend type must be UXTW, UXTX, SXTW, SXTX or LSL',0\r
+ERROR_requires_cpu_capability_arm_26bit:\r
+       call    assembler_error\r
+       db      'Requires CPU capability 26BIT, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v1:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V1, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v2:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V2, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v2a:\r
+       call    assembler_error\r
+       db      'Requires CPU capability A, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v3:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V3, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_m:\r
+       call    assembler_error\r
+       db      'Requires CPU capability M, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v4:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V4, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v4t:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V4T, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v5:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V5, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v5t:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V5T, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_p:\r
+       call    assembler_error\r
+       db      'Requires CPU capability P, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_e:\r
+       call    assembler_error\r
+       db      'Requires CPU capability E, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_j:\r
+       call    assembler_error\r
+       db      'Requires CPU capability J, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_x:\r
+       call    assembler_error\r
+       db      'Requires CPU capability X, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v6:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V6, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v6t:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V6T, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_align:\r
+       call    assembler_error\r
+       db      'Requires CPU capability ALIGN, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_k:\r
+       call    assembler_error\r
+       db      'Requires CPU capability K, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_z:\r
+       call    assembler_error\r
+       db      'Requires CPU capability Z, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_6m:\r
+       call    assembler_error\r
+       db      'Requires CPU capability 6M, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_7m:\r
+       call    assembler_error\r
+       db      'Requires CPU capability 7M, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_t2:\r
+       call    assembler_error\r
+       db      'Requires CPU capability T2, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v7:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V7, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_sync:\r
+       call    assembler_error\r
+       db      'Requires CPU capability SYNC, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_div:\r
+       call    assembler_error\r
+       db      'Requires CPU capability DIV, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_t2ee:\r
+       call    assembler_error\r
+       db      'Requires CPU capability T2EE, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_mp:\r
+       call    assembler_error\r
+       db      'Requires CPU capability MP, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_ve:\r
+       call    assembler_error\r
+       db      'Requires CPU capability VE, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_crc:\r
+       call    assembler_error\r
+       db      'Requires CPU capability CRC, use directive "processor" to select',0\r
+ERROR_requires_cpu_capability_arm_v8:\r
+       call    assembler_error\r
+       db      'Requires CPU capability V8, use directive "processor" to select',0\r
+ERROR_requires_cpu64_capability_v8:\r
+       call    assembler_error\r
+       db      'Requires CPU64 capability V8, use directive "processor" to select',0\r
+ERROR_requires_cpu64_capability_FP:\r
+       call    assembler_error\r
+       db      'Requires CPU64 capability FP, use directive "processor" to select',0\r
+ERROR_requires_cpu64_capability_SIMD:\r
+       call    assembler_error\r
+       db      'Requires CPU64 capability SIMD, use directive "processor" to select',0\r
+ERROR_requires_cpu64_capability_crc:\r
+       call    assembler_error\r
+       db      'Requires CPU64 capability CRC, use directive "processor" to select',0\r
+ERROR_requires_cpu64_capability_crypto:\r
+       call    assembler_error\r
+       db      'Requires CPU64 capability CRYPTO, use directive "processor" to select',0\r
+ERROR_requires_copro_capability_fpa_v1:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability FPA V1, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_fpa_v2:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability FPA V2, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_v1xd:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP V1xD, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_v1:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP V1, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_v2:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP V2, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_v3:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP V3, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_v4:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP V4, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_d32:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP D32, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_vfp_hp:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability VFP HP, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_xscale:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability XSCALE, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_iwmmxt_v1:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability IWMMXT V1, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_iwmmxt_v2:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability IWMMXT V2, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_maverick:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability MAVERICK, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_int:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD INT, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_float:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD FLOAT, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_hp:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD HP, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_v2:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD V2, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_v8:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD V8, use directive "coprocessor" to select',0\r
+ERROR_requires_copro_capability_simd_crypto:\r
+       call    assembler_error\r
+       db      'Requires coprocessor capability SIMD CRYPTO, use directive "coprocessor" to select',0\r
+ERROR_narrow_instructions_are_not_encodable_in_arm_mode:\r
+       call    assembler_error\r
+       db      'Narrow instructions are not encodable in ARM mode',0\r
+ERROR_unexpected_end_of_line:\r
+       call    assembler_error\r
+       db      'Unexpected end of line',0\r
+ERROR_parameter_n_not_valid:\r
+    .all:\r
+       call    assembler_error\r
+       db      'Parameter is invalid',0\r
+    .first:\r
+       call    assembler_error\r
+       db      'First parameter is invalid',0\r
+    .second:\r
+       call    assembler_error\r
+       db      'Second parameter is invalid',0\r
+    .third:\r
+       call    assembler_error\r
+       db      'Third parameter is invalid',0\r
+    .fourth:\r
+       call    assembler_error\r
+       db      'Fourth parameter is invalid',0\r
+    .fifth:\r
+       call    assembler_error\r
+       db      'Fifth parameter is invalid',0\r
+    .sixth:\r
+       call    assembler_error\r
+       db      'Sixth parameter is invalid',0\r
+ERROR_high_base_registers_not_allowed_in_list:\r
+       call    assembler_error\r
+       db      'High registers (R8-R15) not allowed in list',0\r
+    .not_pc:\r
+       call    assembler_error\r
+       db      'High registers (R8-R14) not allowed in list',0\r
+    .not_lr:\r
+       call    assembler_error\r
+       db      'High registers (R8-R13,R15) not allowed in list',0\r
+ERROR_instruction_not_conditional:\r
+       call    assembler_error\r
+       db      'Instruction cannot be conditional',0\r
+ERROR_non_contiguous_set:\r
+       call    assembler_error\r
+       db      'Register set must be contiguous',0\r
+ERROR_large_set:\r
+       call    assembler_error\r
+       db      'Register set cannot contain more than 16 registers',0\r
+ERROR_two_registers_required:\r
+       call    assembler_error\r
+       db      'Register list must have two consecutive registers',0\r
+ERROR_must_be_r15:\r
+    .first:\r
+       call    assembler_error\r
+       db      'First parameter must be PC {R15}',0\r
+ERROR_control_register_only_valid_with_word:\r
+       call    assembler_error\r
+       db      'Control register only valid with word size operations',0\r
+ERROR_condition_does_not_match_IT_specifier:\r
+       call    assembler_error\r
+       db      'Condition does not match IT specifier',0\r
+ERROR_instruction_must_be_last_in_IT_block:\r
+       call    assembler_error\r
+       db      'Instruction must be last in IT block',0\r
+ERROR_al_has_no_inverse:\r
+       call    assembler_error\r
+       db      'No "else" condition available with AL',0\r
+ERROR_label_inside_IT_block:\r
+       call    assembler_error\r
+       db      'Cannot access labels inside of an IT block',0\r
+ERROR_mode_change_inside_IT_block:\r
+       call    assembler_error\r
+       db      'Cannot change CPU mode inside of an IT block',0\r
+ERROR_register_list_invalid:\r
+       call    assembler_error\r
+       db      'The register list cannot be encoded',0\r
+ERROR_alignment_invalid:\r
+       call    assembler_error\r
+       db      'The alignment cannot be encoded',0\r
+ERROR_use_fldr_for_single_reg:\r
+       call    assembler_error\r
+       db      'Use VLDR or FLDR to load single 64 bit registers',0\r
+ERROR_element_value_out_of_range:\r
+    .0_1:\r
+       call    assembler_error\r
+       db      'Element value out of range (0 to 1)',0\r
+    .0_3:\r
+       call    assembler_error\r
+       db      'Element value out of range (0 to 3)',0\r
+    .0_7:\r
+       call    assembler_error\r
+       db      'Element value out of range (0 to 7)',0\r
+ERROR_scalar_register_out_of_range:\r
+    .0_7:\r
+       call    assembler_error\r
+       db      'Scalar register out of range (d0 to d7)',0\r
+    .0_15:\r
+       call    assembler_error\r
+       db      'Scalar register out of range (d0 to d15)',0\r
+ERROR_reg_size_64_not_encodable:\r
+       call    assembler_error\r
+       db      'Register size of 64 bits is not encodable',0\r
+ERROR_zr_not_valid:\r
+    .second:\r
+       call    assembler_error\r
+       db      'Second parameter cannot be the zero register (WZR or XZR)',0\r
+ERROR_condition_value_out_of_range:\r
+    .0_15:\r
+       call    assembler_error\r
+       db      'Condition value out of range (0 to 15)',0\r
+ERROR_al_nv_not_valid:\r
+       call    assembler_error\r
+       db      'Conditions AL and NV are not valid',0\r
+ERROR_cannot_set_flags:\r
+       call    assembler_error\r
+       db      'This instruction cannot set the flags in ARM64 mode',0\r
+ERROR_vector_register_out_of_range:\r
+       call    assembler_error\r
+       db      'Indexed vector register can be v0 to v15 only',0\r
+ERROR_branch_misaligned:\r
+       call    assembler_error\r
+       db      'Address is not aligned',0\r
+ERROR_branch_too_far:\r
+       call    assembler_error\r
+       db      'Address cannot be reached',0\r
+ERROR_expecting_CPU_selection_symbol:\r
+       call    assembler_error\r
+       db      'Expecting a CPU selection symbol after the PROCESSOR operator',0\r
+ERROR_expecting_COPRO_selection_symbol:\r
+       call    assembler_error\r
+       db      'Expecting a COPRO selection symbol after the COPROCESSOR operator',0\r

diff --git a/source/ide/fasmw/fasmarm.inc b/source/ide/fasmw/fasmarm.inc
new file mode 100644 (file)
index 0000000..aa1f919
--- /dev/null
+++ b/source/ide/fasmw/fasmarm.inc
@@ -0,0 +1,465 @@
+\r
+; flat assembler interface for Win32 IDE\r
+; Copyright (c) 1999-2016, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+flat_assembler:\r
+\r
+       mov     [initial_definitions],0\r
+       mov     edx,[esp+4]\r
+       mov     [input_file],edx\r
+       invoke  GetFullPathName,edx,1000h,path_buffer,param_buffer\r
+       mov     edi,[param_buffer]\r
+       mov     byte [edi-1],0\r
+       mov     [symbols_file],0\r
+       test    [command_flags],2\r
+       jz      symbols_file_name_ok\r
+       mov     [symbols_file],edi\r
+       mov     ecx,eax\r
+       add     ecx,path_buffer\r
+       sub     ecx,edi\r
+       lea     edi,[edi+ecx-1]\r
+       mov     ebx,edi\r
+       mov     al,'.'\r
+       std\r
+       repne   scasb\r
+       cld\r
+       je      attach_fas_extension\r
+       mov     edi,ebx\r
+      attach_fas_extension:\r
+       inc     edi\r
+       mov     eax,'.fas'\r
+       stosd\r
+       xor     al,al\r
+       stosb\r
+      symbols_file_name_ok:\r
+       invoke  SetCurrentDirectory,path_buffer\r
+       mov     [hfile],0\r
+       invoke  GlobalAlloc,GMEM_MOVEABLE,1\r
+       mov     [hmem_display],eax\r
+       invoke  GlobalLock,[hmem_display]\r
+       mov     byte [eax],0\r
+       invoke  GlobalUnlock,[hmem_display]\r
+       mov     [display_size],1\r
+       mov     [error_data_size],0\r
+       mov     [allocated_memory],0\r
+       mov     eax,[compiler_memory]\r
+       shl     eax,10\r
+       jz      out_of_memory\r
+      allocate_memory:\r
+       mov     edx,eax\r
+       shr     edx,2\r
+       mov     ecx,eax\r
+       sub     ecx,edx\r
+       mov     [memory_end],ecx\r
+       mov     [additional_memory_end],edx\r
+       invoke  VirtualAlloc,0,eax,MEM_COMMIT,PAGE_READWRITE\r
+       or      eax,eax\r
+       jnz     memory_allocated\r
+       mov     eax,[additional_memory_end]\r
+       shl     eax,1\r
+       cmp     eax,4000h\r
+       jb      out_of_memory\r
+       jmp     allocate_memory\r
+      memory_allocated:\r
+       mov     [allocated_memory],eax\r
+       mov     [memory_start],eax\r
+       mov     [code_start],eax\r
+       add     eax,[memory_end]\r
+       mov     [memory_end],eax\r
+       mov     [additional_memory],eax\r
+       add     [additional_memory_end],eax\r
+       mov     [tagged_blocks],0\r
+\r
+       mov     eax,esp\r
+       and     eax,not 0FFFh\r
+       add     eax,1000h-10000h\r
+       mov     [stack_limit],eax\r
+\r
+       invoke  PostMessage,[hwnd_progress],PBM_SETPOS,0,0\r
+       invoke  SetThreadPriority,[hthread],[compiler_priority]\r
+       invoke  GetTickCount\r
+       mov     [start_time],eax\r
+       mov     [preprocessing_done],0\r
+       call    preprocessor\r
+       invoke  PostMessage,[hwnd_progress],PBM_SETPOS,1,0\r
+       or      [preprocessing_done],-1\r
+       call    parser\r
+       invoke  PostMessage,[hwnd_progress],PBM_SETPOS,2,0\r
+       call    ARM_label_walker        ;this line added for ARM\r
+       call    assembler\r
+       call    ARM_close_dwarf         ;this line added for ARM\r
+       invoke  PostMessage,[hwnd_progress],PBM_SETPOS,3,0\r
+       call    formatter\r
+       invoke  PostMessage,[hwnd_progress],PBM_SETPOS,4,0\r
+       call    show_display_buffer\r
+       invoke  GetTickCount\r
+       sub     eax,[start_time]\r
+       mov     [total_time],eax\r
+       mov     esi,[output_file]\r
+       mov     edi,path_buffer\r
+      copy_executable_name:\r
+       lodsb\r
+       stosb\r
+       or      al,al\r
+       jnz     copy_executable_name\r
+       xor     al,al\r
+\r
+exit_program:\r
+       movzx   eax,al\r
+       push    eax\r
+       mov     eax,[allocated_memory]\r
+       or      eax,eax\r
+       jz      memory_ok\r
+       invoke  VirtualFree,eax,0,MEM_RELEASE\r
+       mov     [allocated_memory],0\r
+      memory_ok:\r
+       mov     eax,[hfile]\r
+       or      eax,eax\r
+       jz      handle_ok\r
+       invoke  CloseHandle,eax\r
+      handle_ok:\r
+       invoke  PostMessage,[hwnd_compiler],WM_COMMAND,IDOK,0\r
+       call    [ExitThread]\r
+\r
+get_environment_variable:\r
+       invoke  GetEnvironmentVariable,esi,string_buffer,1000h\r
+       mov     ecx,[memory_end]\r
+       sub     ecx,edi\r
+       cmp     ecx,1000h\r
+       jbe     get_local_variable\r
+       mov     ecx,1000h\r
+      get_local_variable:\r
+       invoke  GetPrivateProfileString,_section_environment,esi,string_buffer,edi,ecx,ini_path\r
+       add     edi,eax\r
+       cmp     edi,[memory_end]\r
+       jae     out_of_memory\r
+       retn\r
+\r
+open:\r
+       mov     ebx,edx\r
+       invoke  WaitForSingleObject,[mutex],-1\r
+       invoke  CreateFile,ebx,GENERIC_READ,FILE_SHARE_READ,0,OPEN_EXISTING,0,0\r
+       cmp     eax,-1\r
+       je      file_error\r
+       mov     [hfile],eax\r
+       mov     ebx,eax\r
+       clc\r
+       retn\r
+    file_error:\r
+       stc\r
+       retn\r
+create:\r
+       mov     ebx,edx\r
+       invoke  WaitForSingleObject,[mutex],-1\r
+       invoke  CreateFile,ebx,GENERIC_WRITE,0,0,CREATE_ALWAYS,0,0\r
+       cmp     eax,-1\r
+       je      file_error\r
+       mov     ebx,eax\r
+       clc\r
+       retn\r
+write:\r
+       invoke  WriteFile,ebx,edx,ecx,bytes_count,0\r
+       or      eax,eax\r
+       jz      file_error\r
+       clc\r
+       retn\r
+read:\r
+       mov     ebp,ecx\r
+       invoke  ReadFile,ebx,edx,ecx,bytes_count,0\r
+       or      eax,eax\r
+       jz      file_error\r
+       cmp     ebp,[bytes_count]\r
+       jne     file_error\r
+       clc\r
+       retn\r
+close:\r
+       cmp     ebx,[hfile]\r
+       jne     close_handle\r
+       mov     [hfile],0\r
+      close_handle:\r
+       invoke  CloseHandle,ebx\r
+       invoke  ReleaseMutex,[mutex]\r
+       retn\r
+lseek:\r
+       movzx   eax,al\r
+       invoke  SetFilePointer,ebx,edx,0,eax\r
+       cmp     eax,-1\r
+       je      file_error\r
+       retn\r
+\r
+display_block:\r
+       push    edi\r
+       push    ecx\r
+       add     ecx,[display_size]\r
+       invoke  GlobalReAlloc,[hmem_display],ecx,GMEM_MOVEABLE\r
+       or      eax,eax\r
+       jz      out_of_memory\r
+       mov     [hmem_display],eax\r
+       invoke  GlobalLock,[hmem_display]\r
+       add     eax,[display_size]\r
+       lea     edi,[eax-1]\r
+       pop     ecx\r
+       add     [display_size],ecx\r
+       rep     movsb\r
+       xor     al,al\r
+       stosb\r
+       invoke  GlobalUnlock,[hmem_display]\r
+       pop     edi\r
+       retn\r
+fatal_error:\r
+       cmp     [hthread],0\r
+       je      error_outside_compiler\r
+       pop     [error_message]\r
+      error_with_no_source:\r
+       mov     al,0FFh\r
+       jmp     exit_program\r
+assembler_error:\r
+       cmp     [hthread],0\r
+       je      error_outside_compiler\r
+       call    show_display_buffer\r
+       pop     [error_message]\r
+       mov     ebx,[current_line]\r
+       test    ebx,ebx\r
+       jz      error_with_no_source\r
+       xor     ecx,ecx\r
+      get_error_lines:\r
+       mov     eax,[ebx]\r
+       cmp     byte [eax],0\r
+       je      get_next_error_line\r
+       test    byte [ebx+7],80h\r
+       jz      error_lines_ok\r
+       inc     ecx\r
+       mov     edx,ebx\r
+      find_definition_origin:\r
+       mov     edx,[edx+12]\r
+       test    byte [edx+7],80h\r
+       jnz     find_definition_origin\r
+       mov     eax,[edx+4]\r
+       and     eax,7FFFFFFFh\r
+       push    eax\r
+       mov     edx,[edx]\r
+       push    edx\r
+      get_next_error_line:\r
+       mov     ebx,[ebx+8]\r
+       jmp     get_error_lines\r
+      error_lines_ok:\r
+       inc     ecx\r
+       mov     eax,[ebx+4]\r
+       and     eax,7FFFFFFFh\r
+       push    eax\r
+       mov     edx,[ebx]\r
+       push    edx\r
+       mov     ebx,ecx\r
+       inc     ecx\r
+       shl     ecx,3\r
+       mov     [error_data_size],ecx\r
+       invoke  GlobalAlloc,GMEM_MOVEABLE,ecx\r
+       mov     [hmem_error_data],eax\r
+       invoke  GlobalLock,[hmem_error_data]\r
+       mov     [eax],ebx\r
+       invoke  GlobalUnlock,[hmem_error_data]\r
+       xor     ebx,ebx\r
+      store_error_lines:\r
+       pop     edx\r
+       invoke  GetFullPathName,edx,1000h,path_buffer,param_buffer\r
+       inc     eax\r
+       mov     esi,eax\r
+       add     eax,[error_data_size]\r
+       invoke  GlobalReAlloc,[hmem_error_data],eax,GMEM_MOVEABLE\r
+       invoke  GlobalLock,[hmem_error_data]\r
+       mov     edi,eax\r
+       add     edi,[error_data_size]\r
+       mov     ecx,esi\r
+       mov     esi,path_buffer\r
+       rep     movsb\r
+       pop     edx\r
+       mov     [eax+8+ebx*8+4],edx\r
+       sub     edi,eax\r
+       xchg    [error_data_size],edi\r
+       mov     [eax+8+ebx*8],edi\r
+       mov     esi,[eax]\r
+       invoke  GlobalUnlock,[hmem_error_data]\r
+       inc     ebx\r
+       cmp     ebx,esi\r
+       jb      store_error_lines\r
+       mov     edi,[additional_memory]\r
+       cmp     [preprocessing_done],0\r
+       jne     error_in_preprocessed\r
+       xor     al,al\r
+       stosb\r
+       jmp     instruction_converted\r
+      error_in_preprocessed:\r
+       mov     esi,[current_line]\r
+       add     esi,16\r
+       xor     dl,dl\r
+      convert_instruction:\r
+       lodsb\r
+       cmp     al,1Ah\r
+       je      copy_symbol\r
+       cmp     al,22h\r
+       je      copy_symbol\r
+       cmp     al,3Bh\r
+       je      ignore_preprocessor_symbols\r
+       stosb\r
+       or      al,al\r
+       jz      instruction_converted\r
+       xor     dl,dl\r
+       jmp     convert_instruction\r
+      copy_symbol:\r
+       or      dl,dl\r
+       jz      space_ok\r
+       mov     byte [edi],20h\r
+       inc     edi\r
+      space_ok:\r
+       cmp     al,22h\r
+       je      quoted\r
+       lodsb\r
+       movzx   ecx,al\r
+       rep     movsb\r
+       or      dl,-1\r
+       jmp     convert_instruction\r
+      quoted:\r
+       mov     al,27h\r
+       stosb\r
+       lodsd\r
+       mov     ecx,eax\r
+       jecxz   quoted_copied\r
+      copy_quoted:\r
+       lodsb\r
+       stosb\r
+       cmp     al,27h\r
+       jne     quote_ok\r
+       stosb\r
+      quote_ok:\r
+       loop    copy_quoted\r
+      quoted_copied:\r
+       mov     al,27h\r
+       stosb\r
+       or      dl,-1\r
+       jmp     convert_instruction\r
+      ignore_preprocessor_symbols:\r
+       xor     al,al\r
+       stosb\r
+      instruction_converted:\r
+       sub     edi,[additional_memory]\r
+       mov     ebx,[error_data_size]\r
+       lea     eax,[ebx+edi]\r
+       invoke  GlobalReAlloc,[hmem_error_data],eax,GMEM_MOVEABLE\r
+       invoke  GlobalLock,[hmem_error_data]\r
+       mov     ecx,edi\r
+       mov     [eax+4],ebx\r
+       lea     edi,[eax+ebx]\r
+       mov     esi,[additional_memory]\r
+       rep     movsb\r
+       invoke  GlobalUnlock,[hmem_error_data]\r
+       mov     al,2\r
+       jmp     exit_program\r
+      error_outside_compiler:\r
+       mov     esp,[resume_esp]\r
+       jmp     [resume_eip]\r
+\r
+make_timestamp:\r
+       invoke  GetSystemTime,systime\r
+       movzx   ecx,[systime.wYear]\r
+       mov     eax,ecx\r
+       sub     eax,1970\r
+       mov     ebx,365\r
+       mul     ebx\r
+       mov     ebp,eax\r
+       mov     eax,ecx\r
+       sub     eax,1969\r
+       shr     eax,2\r
+       add     ebp,eax\r
+       mov     eax,ecx\r
+       sub     eax,1901\r
+       mov     ebx,100\r
+       div     ebx\r
+       sub     ebp,eax\r
+       mov     eax,ecx\r
+       xor     edx,edx\r
+       sub     eax,1601\r
+       mov     ebx,400\r
+       div     ebx\r
+       add     ebp,eax\r
+       movzx   ecx,[systime.wMonth]\r
+       mov     eax,ecx\r
+       dec     eax\r
+       mov     ebx,30\r
+       mul     ebx\r
+       add     ebp,eax\r
+       cmp     ecx,8\r
+       jbe     months_correction\r
+       mov     eax,ecx\r
+       sub     eax,7\r
+       shr     eax,1\r
+       add     ebp,eax\r
+       mov     ecx,8\r
+      months_correction:\r
+       mov     eax,ecx\r
+       shr     eax,1\r
+       add     ebp,eax\r
+       cmp     ecx,2\r
+       jbe     day_correction_ok\r
+       sub     ebp,2\r
+       movzx   ecx,word [systime.wYear]\r
+       test    ecx,11b\r
+       jnz     day_correction_ok\r
+       xor     edx,edx\r
+       mov     eax,ecx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      edx,edx\r
+       jnz     day_correction\r
+       mov     eax,ecx\r
+       mov     ebx,400\r
+       div     ebx\r
+       or      edx,edx\r
+       jnz     day_correction_ok\r
+      day_correction:\r
+       inc     ebp\r
+      day_correction_ok:\r
+       movzx   eax,[systime.wDay]\r
+       dec     eax\r
+       add     eax,ebp\r
+       mov     ebx,24\r
+       mul     ebx\r
+       movzx   ecx,[systime.wHour]\r
+       add     eax,ecx\r
+       mov     ebx,60\r
+       mul     ebx\r
+       movzx   ecx,[systime.wMinute]\r
+       add     eax,ecx\r
+       mov     ebx,60\r
+       mul     ebx\r
+       movzx   ecx,[systime.wSecond]\r
+       add     eax,ecx\r
+       adc     edx,0\r
+       retn\r
+\r
+include '..\..\errors.inc'\r
+include '..\..\symbdump.inc'\r
+include '..\..\preproce.inc'\r
+include '..\..\parser.inc'\r
+include '..\..\exprpars.inc'\r
+include '..\..\exprcalc.inc'\r
+include '..\..\assemble.inc'\r
+include '..\..\formats.inc'\r
+include '..\..\armv8.inc'\r
+\r
+include '..\..\armtable.inc'\r
+include '..\..\messages.inc'\r
+\r
+_logo db 'flat assembler for ARM  version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0\r
+\r
+section '.bss' readable writeable\r
+\r
+include '..\..\variable.inc'\r
+\r
+allocated_memory dd ?\r
+start_time dd ?\r
+total_time dd ?\r
+display_size dd ?\r
+error_message dd ?\r
+error_data_size dd ?\r
+preprocessing_done db ?\r

diff --git a/source/ide/fasmw/make_arm.bat b/source/ide/fasmw/make_arm.bat
new file mode 100644 (file)
index 0000000..a8ff189
--- /dev/null
+++ b/source/ide/fasmw/make_arm.bat
@@ -0,0 +1,6 @@
+@echo off\r
+ren FASM.INC FASMx86.INC\r
+ren FASMARM.INC FASM.INC\r
+..\..\..\fasm fasmw.asm ..\..\..\FASMWARM.EXE\r
+ren FASM.INC FASMARM.INC\r
+ren FASMx86.INC FASM.INC\r

diff --git a/source/libc/fasmarm.asm b/source/libc/fasmarm.asm
new file mode 100644 (file)
index 0000000..ec83dd1
--- /dev/null
+++ b/source/libc/fasmarm.asm
@@ -0,0 +1,356 @@
+\r
+; flat assembler interface for Unix/libc\r
+; Copyright (c) 1999-2016, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+       format  ELF\r
+       public  main\r
+\r
+macro ccall proc,[arg]\r
+  { common\r
+     local size\r
+     size = 0\r
+     mov ebp,esp\r
+     if ~ arg eq\r
+    forward\r
+     size = size + 4\r
+    common\r
+     sub esp,size\r
+     end if\r
+     and esp,-16\r
+     if ~ arg eq\r
+     add esp,size\r
+    reverse\r
+     pushd arg\r
+    common\r
+     end if\r
+     call proc\r
+     mov esp,ebp }\r
+\r
+extrn gettimeofday\r
+\r
+section '.text' executable align 16\r
+\r
+main:\r
+       mov     ecx,[esp+4]\r
+       mov     [argc],ecx\r
+       mov     ebx,[esp+8]\r
+       mov     [argv],ebx\r
+       push    ebp\r
+       mov     [stack_frame],esp\r
+\r
+       mov     [con_handle],1\r
+       mov     esi,_logo\r
+       call    display_string\r
+\r
+       call    get_params\r
+       jc      information\r
+\r
+       call    init_memory\r
+\r
+       mov     esi,_memory_prefix\r
+       call    display_string\r
+       mov     eax,[memory_end]\r
+       sub     eax,[memory_start]\r
+       add     eax,[additional_memory_end]\r
+       sub     eax,[additional_memory]\r
+       shr     eax,10\r
+       call    display_number\r
+       mov     esi,_memory_suffix\r
+       call    display_string\r
+\r
+       ccall   gettimeofday,buffer,0\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       mov     [start_time],eax\r
+\r
+       and     [preprocessing_done],0\r
+       call    preprocessor\r
+       or      [preprocessing_done],-1\r
+       call    parser\r
+       call    ARM_label_walker        ;this line added for ARM\r
+       call    assembler\r
+       call    ARM_close_dwarf         ;this line added for ARM\r
+       call    formatter\r
+\r
+       call    display_user_messages\r
+       movzx   eax,[current_pass]\r
+       inc     eax\r
+       call    display_number\r
+       mov     esi,_passes_suffix\r
+       call    display_string\r
+       ccall   gettimeofday,buffer,0\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       sub     eax,[start_time]\r
+       jnc     time_ok\r
+       add     eax,3600000\r
+      time_ok:\r
+       xor     edx,edx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      eax,eax\r
+       jz      display_bytes_count\r
+       xor     edx,edx\r
+       mov     ebx,10\r
+       div     ebx\r
+       push    edx\r
+       call    display_number\r
+       mov     dl,'.'\r
+       call    display_character\r
+       pop     eax\r
+       call    display_number\r
+       mov     esi,_seconds_suffix\r
+       call    display_string\r
+      display_bytes_count:\r
+       mov     eax,[written_size]\r
+       call    display_number\r
+       mov     esi,_bytes_suffix\r
+       call    display_string\r
+       xor     al,al\r
+       jmp     exit_program\r
+\r
+information:\r
+       mov     esi,_usage\r
+       call    display_string\r
+       mov     al,1\r
+       jmp     exit_program\r
+\r
+get_params:\r
+       mov     [input_file],0\r
+       mov     [output_file],0\r
+       mov     [symbols_file],0\r
+       mov     [memory_setting],0\r
+       mov     [passes_limit],100\r
+\r
+       mov     ecx,[argc]\r
+       mov     ebx,[argv]\r
+       add     ebx,4\r
+       dec     ecx\r
+       jz      bad_params\r
+       mov     [definitions_pointer],predefinitions\r
+      get_param:\r
+       mov     esi,[ebx]\r
+       mov     al,[esi]\r
+       cmp     al,'-'\r
+       je      option_param\r
+       cmp     [input_file],0\r
+       jne     get_output_file\r
+       mov     [input_file],esi\r
+       jmp     next_param\r
+      get_output_file:\r
+       cmp     [output_file],0\r
+       jne     bad_params\r
+       mov     [output_file],esi\r
+       jmp     next_param\r
+      option_param:\r
+       inc     esi\r
+       lodsb\r
+       cmp     al,'m'\r
+       je      memory_option\r
+       cmp     al,'M'\r
+       je      memory_option\r
+       cmp     al,'p'\r
+       je      passes_option\r
+       cmp     al,'P'\r
+       je      passes_option\r
+       cmp     al,'d'\r
+       je      definition_option\r
+       cmp     al,'D'\r
+       je      definition_option\r
+       cmp     al,'s'\r
+       je      symbols_option\r
+       cmp     al,'S'\r
+       je      symbols_option\r
+      bad_params:\r
+       stc\r
+       ret\r
+      memory_option:\r
+       cmp     byte [esi],0\r
+       jne     get_memory_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_memory_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,1 shl (32-10)\r
+       jae     bad_params\r
+       mov     [memory_setting],edx\r
+       jmp     next_param\r
+      passes_option:\r
+       cmp     byte [esi],0\r
+       jne     get_passes_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_passes_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,10000h\r
+       ja      bad_params\r
+       mov     [passes_limit],dx\r
+      next_param:\r
+       add     ebx,4\r
+       dec     ecx\r
+       jnz     get_param\r
+       cmp     [input_file],0\r
+       je      bad_params\r
+       mov     eax,[definitions_pointer]\r
+       mov     byte [eax],0\r
+       mov     [initial_definitions],predefinitions\r
+       clc\r
+       ret\r
+      definition_option:\r
+       cmp     byte [esi],0\r
+       jne     get_definition\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_definition:\r
+       push    edi\r
+       mov     edi,[definitions_pointer]\r
+       call    convert_definition_option\r
+       mov     [definitions_pointer],edi\r
+       pop     edi\r
+       jc      bad_params\r
+       jmp     next_param\r
+      symbols_option:\r
+       cmp     byte [esi],0\r
+       jne     get_symbols_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_symbols_setting:\r
+       mov     [symbols_file],esi\r
+       jmp     next_param\r
+      get_option_value:\r
+       xor     eax,eax\r
+       mov     edx,eax\r
+      get_option_digit:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      option_value_ok\r
+       cmp     al,0Dh\r
+       je      option_value_ok\r
+       or      al,al\r
+       jz      option_value_ok\r
+       sub     al,30h\r
+       jc      invalid_option_value\r
+       cmp     al,9\r
+       ja      invalid_option_value\r
+       imul    edx,10\r
+       jo      invalid_option_value\r
+       add     edx,eax\r
+       jc      invalid_option_value\r
+       jmp     get_option_digit\r
+      option_value_ok:\r
+       dec     esi\r
+       clc\r
+       ret\r
+      invalid_option_value:\r
+       stc\r
+       ret\r
+      convert_definition_option:\r
+       mov     edx,edi\r
+       xor     al,al\r
+       stosb\r
+      copy_definition_name:\r
+       lodsb\r
+       cmp     al,'='\r
+       je      copy_definition_value\r
+       cmp     al,20h\r
+       je      bad_definition_option\r
+       or      al,al\r
+       jz      bad_definition_option\r
+       stosb\r
+       inc     byte [edx]\r
+       jnz     copy_definition_name\r
+      bad_definition_option:\r
+       stc\r
+       ret\r
+      copy_definition_value:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      definition_value_end\r
+       or      al,al\r
+       jz      definition_value_end\r
+       stosb\r
+       jmp     copy_definition_value\r
+      definition_value_end:\r
+       dec     esi\r
+       xor     al,al\r
+       stosb\r
+       clc\r
+       ret\r
+\r
+include 'system.inc'\r
+\r
+include '..\version.inc'\r
+\r
+include '..\errors.inc'\r
+include '..\symbdump.inc'\r
+include '..\preproce.inc'\r
+include '..\parser.inc'\r
+include '..\exprpars.inc'\r
+include '..\exprcalc.inc'\r
+include '..\assemble.inc'\r
+include '..\formats.inc'\r
+include '..\armv8.inc'\r
+\r
+include '..\armtable.inc'\r
+include '..\messages.inc'\r
+\r
+_copyright db  'Copyright (c) 2005-2023, revolution',0Ah,\\r
+               'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0\r
+\r
+_logo db 'flat assembler for ARM  version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0\r
+_usage db 0xA\r
+       db 'usage: fasmasm <source> [output]',0xA\r
+       db 'optional settings:',0xA\r
+       db ' -m <limit>         set the limit in kilobytes for the available memory',0Ah\r
+       db ' -p <limit>         set the maximum allowed number of passes',0Ah\r
+       db ' -d <name>=<value>  define symbolic variable',0Ah\r
+       db ' -s <file>          dump symbolic information for debugging',0Ah\r
+       db 0\r
+_memory_prefix db '  (',0\r
+_memory_suffix db ' kilobytes memory)',0xA,0\r
+_passes_suffix db ' passes, ',0\r
+_seconds_suffix db ' seconds, ',0\r
+_bytes_suffix db ' bytes.',0xA,0\r
+\r
+section '.bss' writeable align 4\r
+\r
+include '..\variable.inc'\r
+\r
+argc dd ?\r
+argv dd ?\r
+stack_frame dd ?\r
+memory_setting dd ?\r
+definitions_pointer dd ?\r
+start_time dd ?\r
+timestamp dq ?\r
+con_handle dd ?\r
+displayed_count dd ?\r
+last_displayed db ?\r
+character db ?\r
+preprocessing_done db ?\r
+\r
+predefinitions rb 1000h\r
+buffer rb 1000h\r

diff --git a/source/linux/fasmarm.asm b/source/linux/fasmarm.asm
new file mode 100644 (file)
index 0000000..78f7992
--- /dev/null
+++ b/source/linux/fasmarm.asm
@@ -0,0 +1,441 @@
+\r
+; flat assembler interface for Linux\r
+; Copyright (c) 1999-2016, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+       format  ELF executable 3\r
+       entry   start\r
+\r
+stdin  = 0\r
+stdout = 1\r
+stderr = 2\r
+\r
+segment readable executable\r
+\r
+start:\r
+\r
+       mov     [con_handle],stdout\r
+       mov     [command_line],esp\r
+       mov     ecx,[esp]\r
+       lea     ebx,[esp+4+ecx*4+4]\r
+       mov     [environment],ebx\r
+       call    get_params\r
+       pushf\r
+       jc      show_logo\r
+       cmp     [con_handle],stdout\r
+       jnz     logo_done\r
+      show_logo:\r
+       mov     esi,_logo\r
+       call    display_string\r
+      logo_done:\r
+       popf\r
+       jc      information\r
+\r
+       call    init_memory\r
+\r
+       cmp     [con_handle],stdout\r
+       jnz     memory_done\r
+       mov     esi,_memory_prefix\r
+       call    display_string\r
+       mov     eax,[memory_end]\r
+       sub     eax,[memory_start]\r
+       add     eax,[additional_memory_end]\r
+       sub     eax,[additional_memory]\r
+       shr     eax,10\r
+       call    display_number\r
+       mov     esi,_memory_suffix\r
+       call    display_string\r
+      memory_done:\r
+\r
+       mov     eax,78\r
+       mov     ebx,buffer\r
+       xor     ecx,ecx\r
+       int     0x80\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       mov     [start_time],eax\r
+\r
+       and     [preprocessing_done],0\r
+       call    preprocessor\r
+       or      [preprocessing_done],-1\r
+       call    parser\r
+       call    ARM_label_walker        ;this line added for ARM\r
+       call    assembler\r
+       call    ARM_close_dwarf         ;this line added for ARM\r
+       call    formatter\r
+\r
+       call    display_user_messages\r
+       cmp     [con_handle],stdout\r
+       jnz     details_done\r
+       movzx   eax,[current_pass]\r
+       inc     eax\r
+       call    display_number\r
+       mov     esi,_passes_suffix\r
+       call    display_string\r
+       mov     eax,78\r
+       mov     ebx,buffer\r
+       xor     ecx,ecx\r
+       int     0x80\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       sub     eax,[start_time]\r
+       jnc     time_ok\r
+       add     eax,3600000\r
+      time_ok:\r
+       xor     edx,edx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      eax,eax\r
+       jz      display_bytes_count\r
+       xor     edx,edx\r
+       mov     ebx,10\r
+       div     ebx\r
+       push    edx\r
+       call    display_number\r
+       mov     dl,'.'\r
+       call    display_character\r
+       pop     eax\r
+       call    display_number\r
+       mov     esi,_seconds_suffix\r
+       call    display_string\r
+      display_bytes_count:\r
+       mov     eax,[written_size]\r
+       call    display_number\r
+       mov     esi,_bytes_suffix\r
+       call    display_string\r
+      details_done:\r
+       xor     al,al\r
+       jmp     exit_program\r
+\r
+information:\r
+       mov     esi,_usage\r
+       call    display_string\r
+       mov     al,1\r
+       jmp     exit_program\r
+\r
+get_params:\r
+       mov     ebx,[command_line]\r
+       mov     [input_file],0\r
+       mov     [output_file],0\r
+       mov     [symbols_file],0\r
+       mov     [memory_setting],0\r
+       mov     [passes_limit],100\r
+       mov     ecx,[ebx]\r
+       add     ebx,8\r
+       dec     ecx\r
+       jz      bad_params\r
+       mov     [definitions_pointer],predefinitions\r
+      get_param:\r
+       mov     esi,[ebx]\r
+       mov     ax,[esi]\r
+       cmp     ax,'-'\r
+       jz      stdin_stdout\r
+       cmp     al,'-'\r
+       je      option_param\r
+      stdin_stdout:\r
+       cmp     [input_file],0\r
+       jne     get_output_file\r
+       mov     [input_file],esi\r
+       jmp     next_param\r
+      get_output_file:\r
+       cmp     [output_file],0\r
+       jne     bad_params\r
+       mov     [output_file],esi\r
+       jmp     next_param\r
+      option_param:\r
+       inc     esi\r
+       lodsb\r
+       cmp     al,'m'\r
+       je      memory_option\r
+       cmp     al,'M'\r
+       je      memory_option\r
+       cmp     al,'p'\r
+       je      passes_option\r
+       cmp     al,'P'\r
+       je      passes_option\r
+       cmp     al,'d'\r
+       je      definition_option\r
+       cmp     al,'D'\r
+       je      definition_option\r
+       cmp     al,'s'\r
+       je      symbols_option\r
+       cmp     al,'S'\r
+       je      symbols_option\r
+      bad_params:\r
+       stc\r
+       ret\r
+      memory_option:\r
+       cmp     byte [esi],0\r
+       jne     get_memory_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_memory_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,1 shl (32-10)\r
+       jae     bad_params\r
+       mov     [memory_setting],edx\r
+       jmp     next_param\r
+      passes_option:\r
+       cmp     byte [esi],0\r
+       jne     get_passes_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_passes_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,10000h\r
+       ja      bad_params\r
+       mov     [passes_limit],dx\r
+      next_param:\r
+       add     ebx,4\r
+       dec     ecx\r
+       jnz     get_param\r
+       mov     eax,[input_file]\r
+       test    eax,eax\r
+       je      bad_params\r
+       mov     ecx,[output_file]\r
+       cmp     word[eax],'-'\r
+       jnz     output_file_okay\r
+       test    ecx,ecx\r
+       jnz     check_con_handle\r
+       mov     [output_file],eax\r
+       mov     ecx,eax\r
+      output_file_okay:\r
+       test    ecx,ecx\r
+       jz      con_handle_okay\r
+      check_con_handle:\r
+       cmp     word[ecx],'-'\r
+       jnz     con_handle_okay\r
+       mov     [con_handle],stderr\r
+      con_handle_okay:\r
+       mov     eax,[definitions_pointer]\r
+       mov     byte [eax],0\r
+       mov     [initial_definitions],predefinitions\r
+       clc\r
+       ret\r
+      definition_option:\r
+       cmp     byte [esi],0\r
+       jne     get_definition\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_definition:\r
+       push    edi\r
+       mov     edi,[definitions_pointer]\r
+       call    convert_definition_option\r
+       mov     [definitions_pointer],edi\r
+       pop     edi\r
+       jc      bad_params\r
+       jmp     next_param\r
+      symbols_option:\r
+       cmp     byte [esi],0\r
+       jne     get_symbols_setting\r
+       dec     ecx\r
+       jz      bad_params\r
+       add     ebx,4\r
+       mov     esi,[ebx]\r
+      get_symbols_setting:\r
+       mov     [symbols_file],esi\r
+       jmp     next_param\r
+      get_option_value:\r
+       xor     eax,eax\r
+       mov     edx,eax\r
+      get_option_digit:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      option_value_ok\r
+       or      al,al\r
+       jz      option_value_ok\r
+       sub     al,30h\r
+       jc      invalid_option_value\r
+       cmp     al,9\r
+       ja      invalid_option_value\r
+       imul    edx,10\r
+       jo      invalid_option_value\r
+       add     edx,eax\r
+       jc      invalid_option_value\r
+       jmp     get_option_digit\r
+      option_value_ok:\r
+       dec     esi\r
+       clc\r
+       ret\r
+      invalid_option_value:\r
+       stc\r
+       ret\r
+      convert_definition_option:\r
+       mov     edx,edi\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       xor     al,al\r
+       stosb\r
+      copy_definition_name:\r
+       lodsb\r
+       cmp     al,'='\r
+       je      copy_definition_value\r
+       cmp     al,20h\r
+       je      bad_definition_option\r
+       or      al,al\r
+       jz      bad_definition_option\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       stosb\r
+       inc     byte [edx]\r
+       jnz     copy_definition_name\r
+      bad_definition_option:\r
+       stc\r
+       ret\r
+      copy_definition_value:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      definition_value_end\r
+       or      al,al\r
+       jz      definition_value_end\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       stosb\r
+       jmp     copy_definition_value\r
+      definition_value_end:\r
+       dec     esi\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       xor     al,al\r
+       stosb\r
+       clc\r
+       ret\r
+\r
+open_stdin:\r
+       cmp     word[edx],'-'\r
+       jnz     adapt_path\r
+       mov     ebx,stdin\r
+       pop     eax ebp edi esi\r
+       clc\r
+       ret\r
+\r
+open_stdout:\r
+       cmp     word[edx],'-'\r
+       jnz     adapt_path\r
+       mov     ebx,stdout\r
+       pop     eax edx ebp edi esi\r
+       clc\r
+       ret\r
+\r
+ARM_preprocess_file:\r
+       push    [memory_end]\r
+       push    esi\r
+       ;ebx = file handle\r
+       ;edi = start of free memory\r
+       push    edi\r
+       mov     edx,edi         ; destination\r
+      keep_reading:\r
+       mov     ecx,[memory_end]\r
+       dec     ecx\r
+       sub     ecx,edx         ; memory buffer size\r
+       jbe     out_of_memory\r
+       call    read\r
+       add     edx,eax\r
+       test    eax,eax\r
+       jnz     keep_reading\r
+       lea     esi,[edx-1]\r
+       sub     edx,edi         ; input length\r
+       mov     ecx,edx\r
+       mov     edi,[memory_end]\r
+       sub     edi,2\r
+       mov     byte [edi+1],1Ah\r
+       std\r
+       rep     movs byte [edi],[esi]\r
+       cld\r
+       inc     edi\r
+       mov     [memory_end],edi\r
+       mov     esi,edi\r
+       pop     edi\r
+       call    close\r
+       pop     edx\r
+       xor     ecx,ecx\r
+       mov     ebx,esi\r
+       jmp     preprocess_source\r
+\r
+include 'system.inc'\r
+\r
+include '..\version.inc'\r
+\r
+include '..\errors.inc'\r
+include '..\symbdump.inc'\r
+include '..\preproce.inc'\r
+include '..\parser.inc'\r
+include '..\exprpars.inc'\r
+include '..\exprcalc.inc'\r
+include '..\assemble.inc'\r
+include '..\formats.inc'\r
+include '..\armv8.inc'\r
+\r
+;patches to enable "-" to read/write using stdin/stdout\r
+\r
+patch open, call adapt_path, call open_stdin, 3\r
+patch create, call adapt_path, call open_stdout, 4\r
+patch read, <<cmp eax,ecx>>, <<cmp eax,eax>>, 23\r
+patch predefinitions_ok, call preprocess_file, call ARM_preprocess_file, 25\r
+patch copy_preprocessed_path, call preprocess_file, call ARM_preprocess_file, 28\r
+\r
+;patch to fix bug with lseek error detection\r
+\r
+patch lseek, <<cmp eax,-1>,<je file_error>,<clc>>, <<cmp eax,-4095>,<cmc>>, 13\r
+\r
+include '..\armtable.inc'\r
+include '..\messages.inc'\r
+\r
+_copyright db  'Copyright (c) 2005-2023, revolution',0Ah,\\r
+               'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0\r
+\r
+_logo db 'flat assembler for ARM  version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0\r
+_usage db 0xA\r
+       db 'usage: fasmarm <source> [output]',0xA\r
+       db 'optional settings:',0xA\r
+       db ' -m <limit>         set the limit in kilobytes for the available memory',0Ah\r
+       db ' -p <limit>         set the maximum allowed number of passes',0Ah\r
+       db ' -d <name>=<value>  define symbolic variable',0Ah\r
+       db ' -s <file>          dump symbolic information for debugging',0Ah\r
+       db 0\r
+_memory_prefix db '  (',0\r
+_memory_suffix db ' kilobytes memory)',0xA,0\r
+_passes_suffix db ' passes, ',0\r
+_seconds_suffix db ' seconds, ',0\r
+_bytes_suffix db ' bytes.',0xA,0\r
+\r
+segment readable writeable\r
+\r
+align 4\r
+\r
+include '..\variable.inc'\r
+\r
+command_line dd ?\r
+memory_setting dd ?\r
+definitions_pointer dd ?\r
+environment dd ?\r
+timestamp dq ?\r
+start_time dd ?\r
+con_handle dd ?\r
+displayed_count dd ?\r
+last_displayed db ?\r
+character db ?\r
+preprocessing_done db ?\r
+\r
+predefinitions rb 1000h\r
+buffer rb 1000h\r

diff --git a/source/linux/x64/fasmarm.asm b/source/linux/x64/fasmarm.asm
new file mode 100644 (file)
index 0000000..5dfd274
--- /dev/null
+++ b/source/linux/x64/fasmarm.asm
@@ -0,0 +1,460 @@
+\r
+; flat assembler interface for Linux x64\r
+; Copyright (c) 1999-2022, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+       format  ELF64 executable 3 at 400000h\r
+       entry   start\r
+\r
+stdin  = 0\r
+stdout = 1\r
+stderr = 2\r
+\r
+       include 'modes.inc'\r
+\r
+segment readable executable\r
+\r
+start:\r
+\r
+       mov     [con_handle],stdout\r
+\r
+       mov     [command_line],rsp\r
+       mov     rcx,[rsp]\r
+       lea     rbx,[rsp+8+rcx*8+8]\r
+       mov     [environment],rbx\r
+       call    get_params\r
+       pushf\r
+       jc      show_logo\r
+       cmp     [con_handle],stdout\r
+       jnz     logo_done\r
+      show_logo:\r
+       mov     esi,_logo\r
+       call    display_string\r
+      logo_done:\r
+       popf\r
+       jc      information\r
+       call    init_memory\r
+\r
+       cmp     [con_handle],stdout\r
+       jnz     memory_done\r
+       mov     esi,_memory_prefix\r
+       call    display_string\r
+       mov     eax,[memory_end]\r
+       sub     eax,[memory_start]\r
+       add     eax,[additional_memory_end]\r
+       sub     eax,[additional_memory]\r
+       shr     eax,10\r
+       call    display_number\r
+       mov     esi,_memory_suffix\r
+       call    display_string\r
+      memory_done:\r
+\r
+       mov     eax,96\r
+       mov     edi,buffer\r
+       xor     esi,esi\r
+       syscall\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       mov     [start_time],eax\r
+\r
+       and     [preprocessing_done],0\r
+       call    preprocessor\r
+       or      [preprocessing_done],-1\r
+       call    parser\r
+       call    ARM_label_walker        ;this line added for ARM\r
+       call    assembler\r
+       call    ARM_close_dwarf         ;this line added for ARM\r
+       call    formatter\r
+\r
+       call    display_user_messages\r
+       cmp     [con_handle],stdout\r
+       jnz     details_done\r
+       movzx   eax,[current_pass]\r
+       inc     eax\r
+       call    display_number\r
+       mov     esi,_passes_suffix\r
+       call    display_string\r
+       mov     eax,96\r
+       mov     edi,buffer\r
+       xor     esi,esi\r
+       syscall\r
+       mov     eax,dword [buffer]\r
+       mov     ecx,1000\r
+       mul     ecx\r
+       mov     ebx,eax\r
+       mov     eax,dword [buffer+4]\r
+       div     ecx\r
+       add     eax,ebx\r
+       sub     eax,[start_time]\r
+       jnc     time_ok\r
+       add     eax,3600000\r
+      time_ok:\r
+       xor     edx,edx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      eax,eax\r
+       jz      display_bytes_count\r
+       xor     edx,edx\r
+       mov     ebx,10\r
+       div     ebx\r
+       push    edx\r
+       call    display_number\r
+       mov     dl,'.'\r
+       call    display_character\r
+       pop     eax\r
+       call    display_number\r
+       mov     esi,_seconds_suffix\r
+       call    display_string\r
+      display_bytes_count:\r
+       mov     eax,[written_size]\r
+       call    display_number\r
+       mov     esi,_bytes_suffix\r
+       call    display_string\r
+      details_done:\r
+       xor     al,al\r
+       jmp     exit_program\r
+\r
+information:\r
+       mov     esi,_usage\r
+       call    display_string\r
+       mov     al,1\r
+       jmp     exit_program\r
+\r
+get_params:\r
+       mov     rbx,[command_line]\r
+       mov     [input_file],0\r
+       mov     [output_file],0\r
+       mov     [symbols_file],0\r
+       mov     [memory_setting],0\r
+       mov     [passes_limit],100\r
+       mov     rcx,[rbx]\r
+       add     rbx,8*2\r
+       dec     rcx\r
+       jz      bad_params\r
+       mov     [definitions_pointer],predefinitions\r
+       mov     [path_pointer],paths\r
+      get_param:\r
+       mov     rsi,[rbx]\r
+       mov     ax,[rsi]\r
+       cmp     ax,'-'\r
+       jz      stdin_stdout\r
+       cmp     al,'-'\r
+       je      option_param\r
+      stdin_stdout:\r
+       cmp     [input_file],0\r
+       jne     get_output_file\r
+       call    collect_path\r
+       mov     [input_file],edx\r
+       jmp     next_param\r
+      get_output_file:\r
+       cmp     [output_file],0\r
+       jne     bad_params\r
+       call    collect_path\r
+       mov     [output_file],edx\r
+       jmp     next_param\r
+      option_param:\r
+       inc     rsi\r
+       lodsb\r
+       cmp     al,'m'\r
+       je      memory_option\r
+       cmp     al,'M'\r
+       je      memory_option\r
+       cmp     al,'p'\r
+       je      passes_option\r
+       cmp     al,'P'\r
+       je      passes_option\r
+       cmp     al,'d'\r
+       je      definition_option\r
+       cmp     al,'D'\r
+       je      definition_option\r
+       cmp     al,'s'\r
+       je      symbols_option\r
+       cmp     al,'S'\r
+       je      symbols_option\r
+      bad_params:\r
+       stc\r
+       ret\r
+      memory_option:\r
+       cmp     byte [rsi],0\r
+       jne     get_memory_setting\r
+       dec     rcx\r
+       jz      bad_params\r
+       add     rbx,8\r
+       mov     rsi,[rbx]\r
+      get_memory_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,1 shl (32-10)\r
+       jae     bad_params\r
+       mov     [memory_setting],edx\r
+       jmp     next_param\r
+      passes_option:\r
+       cmp     byte [rsi],0\r
+       jne     get_passes_setting\r
+       dec     rcx\r
+       jz      bad_params\r
+       add     rbx,8\r
+       mov     rsi,[rbx]\r
+      get_passes_setting:\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,10000h\r
+       ja      bad_params\r
+       mov     [passes_limit],dx\r
+      next_param:\r
+       add     rbx,8\r
+       dec     rcx\r
+       jnz     get_param\r
+       mov     eax,[input_file]\r
+       test    eax,eax\r
+       je      bad_params\r
+       mov     ecx,[output_file]\r
+       cmp     word[eax],'-'\r
+       jnz     output_file_okay\r
+       test    ecx,ecx\r
+       jnz     check_con_handle\r
+       mov     [output_file],eax\r
+       mov     ecx,eax\r
+      output_file_okay:\r
+       test    ecx,ecx\r
+       jz      con_handle_okay\r
+      check_con_handle:\r
+       cmp     word[ecx],'-'\r
+       jnz     con_handle_okay\r
+       mov     [con_handle],stderr\r
+      con_handle_okay:\r
+       mov     eax,[definitions_pointer]\r
+       mov     byte [eax],0\r
+       mov     [initial_definitions],predefinitions\r
+       clc\r
+       ret\r
+      definition_option:\r
+       cmp     byte [rsi],0\r
+       jne     get_definition\r
+       dec     rcx\r
+       jz      bad_params\r
+       add     rbx,8\r
+       mov     rsi,[rbx]\r
+      get_definition:\r
+       mov     r12d,edi\r
+       mov     edi,[definitions_pointer]\r
+       call    convert_definition_option\r
+       mov     [definitions_pointer],edi\r
+       mov     edi,r12d\r
+       jc      bad_params\r
+       jmp     next_param\r
+      symbols_option:\r
+       cmp     byte [rsi],0\r
+       jne     get_symbols_setting\r
+       dec     rcx\r
+       jz      bad_params\r
+       add     rbx,8\r
+       mov     rsi,[rbx]\r
+      get_symbols_setting:\r
+       call    collect_path\r
+       mov     [symbols_file],edx\r
+       jmp     next_param\r
+      get_option_value:\r
+       xor     eax,eax\r
+       mov     edx,eax\r
+      get_option_digit:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      option_value_ok\r
+       or      al,al\r
+       jz      option_value_ok\r
+       sub     al,30h\r
+       jc      invalid_option_value\r
+       cmp     al,9\r
+       ja      invalid_option_value\r
+       imul    edx,10\r
+       jo      invalid_option_value\r
+       add     edx,eax\r
+       jc      invalid_option_value\r
+       jmp     get_option_digit\r
+      option_value_ok:\r
+       dec     rsi\r
+       clc\r
+       ret\r
+      invalid_option_value:\r
+       stc\r
+       ret\r
+      convert_definition_option:\r
+       mov     edx,edi\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       xor     al,al\r
+       stosb\r
+      copy_definition_name:\r
+       lodsb\r
+       cmp     al,'='\r
+       je      copy_definition_value\r
+       cmp     al,20h\r
+       je      bad_definition_option\r
+       or      al,al\r
+       jz      bad_definition_option\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       stosb\r
+       inc     byte [edx]\r
+       jnz     copy_definition_name\r
+      bad_definition_option:\r
+       stc\r
+       ret\r
+      copy_definition_value:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      definition_value_end\r
+       or      al,al\r
+       jz      definition_value_end\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       stosb\r
+       jmp     copy_definition_value\r
+      definition_value_end:\r
+       dec     rsi\r
+       cmp     edi,predefinitions+1000h\r
+       jae     bad_definition_option\r
+       xor     al,al\r
+       stosb\r
+       clc\r
+       ret\r
+collect_path:\r
+       mov     edi,[path_pointer]\r
+       mov     edx,edi\r
+     copy_path_to_low_memory:\r
+       lodsb\r
+       stosb\r
+       test    al,al\r
+       jnz     copy_path_to_low_memory\r
+       mov     [path_pointer],edi\r
+       retn\r
+\r
+open_stdin:\r
+       cmp     word[edx],'-'\r
+       jnz     adapt_path\r
+       mov     ebx,stdin\r
+       POP     rcx\r
+       clc\r
+       ret\r
+\r
+open_stdout:\r
+       cmp     word[edx],'-'\r
+       jnz     adapt_path\r
+       mov     ebx,stdout\r
+       POP     rcx\r
+       clc\r
+       ret\r
+\r
+ARM_preprocess_file:\r
+       push    [memory_end]\r
+       push    esi\r
+       ;ebx = file handle\r
+       ;edi = start of free memory\r
+       push    edi\r
+       mov     edx,edi         ; destination\r
+      keep_reading:\r
+       mov     ecx,[memory_end]\r
+       dec     ecx\r
+       sub     ecx,edx         ; memory buffer size\r
+       jbe     out_of_memory\r
+       call    read\r
+       add     edx,eax\r
+       test    eax,eax\r
+       jnz     keep_reading\r
+       lea     esi,[edx-1]\r
+       sub     edx,edi         ; input length\r
+       mov     ecx,edx\r
+       mov     edi,[memory_end]\r
+       sub     edi,2\r
+       mov     byte [edi+1],1Ah\r
+       std\r
+       rep     movs byte [edi],[esi]\r
+       cld\r
+       inc     edi\r
+       mov     [memory_end],edi\r
+       mov     esi,edi\r
+       pop     edi\r
+       call    close\r
+       pop     edx\r
+       xor     ecx,ecx\r
+       mov     ebx,esi\r
+       jmp     preprocess_source\r
+\r
+include 'system.inc'\r
+\r
+include '..\..\version.inc'\r
+\r
+include '..\..\errors.inc'\r
+include '..\..\symbdump.inc'\r
+include '..\..\preproce.inc'\r
+include '..\..\parser.inc'\r
+include '..\..\exprpars.inc'\r
+include '..\..\exprcalc.inc'\r
+include '..\..\assemble.inc'\r
+include '..\..\formats.inc'\r
+include '..\..\armv8.inc'\r
+\r
+;patches to enable "-" to read/write using stdin/stdout\r
+\r
+patch open, call adapt_path, call open_stdin, 6\r
+patch create, call adapt_path, call open_stdout, 9\r
+patch read, <<cmp eax,ecx>>, <<cmp eax,eax>>, 33\r
+patch predefinitions_ok, call preprocess_file, call ARM_preprocess_file, 25\r
+patch copy_preprocessed_path, call preprocess_file, call ARM_preprocess_file, 49\r
+\r
+;patch to fix bug with lseek error detection\r
+\r
+patch lseek, <<cmp eax,-1>,<je file_error>,<clc>>, <<cmp eax,-4095>,<cmc>>, 27\r
+\r
+include '..\..\armtable.inc'\r
+include '..\..\messages.inc'\r
+\r
+_copyright db  'Copyright (c) 2005-2023, revolution',0Ah,\\r
+               'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Ah,0\r
+\r
+_logo db 'flat assembler for ARM  version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0\r
+_usage db 0xA\r
+       db 'usage: fasmarm <source> [output]',0xA\r
+       db 'optional settings:',0xA\r
+       db ' -m <limit>         set the limit in kilobytes for the available memory',0xA\r
+       db ' -p <limit>         set the maximum allowed number of passes',0xA\r
+       db ' -d <name>=<value>  define symbolic variable',0xA\r
+       db ' -s <file>          dump symbolic information for debugging',0xA\r
+       db 0\r
+_memory_prefix db '  (',0\r
+_memory_suffix db ' kilobytes memory, x64)',0xA,0\r
+_passes_suffix db ' passes, ',0\r
+_seconds_suffix db ' seconds, ',0\r
+_bytes_suffix db ' bytes.',0xA,0\r
+_no_low_memory db 'failed to allocate memory within 32-bit addressing range',0\r
+\r
+segment readable writeable\r
+\r
+align 4\r
+\r
+include '..\..\variable.inc'\r
+\r
+command_line dq ?\r
+memory_setting dd ?\r
+path_pointer dd ?\r
+definitions_pointer dd ?\r
+environment dq ?\r
+timestamp dq ?\r
+start_time dd ?\r
+con_handle dd ?\r
+displayed_count dd ?\r
+last_displayed db ?\r
+character db ?\r
+preprocessing_done db ?\r
+\r
+buffer rb 1000h\r
+predefinitions rb 1000h\r
+paths rb 10000h\r

diff --git a/source/win32/fasmarm.asm b/source/win32/fasmarm.asm
new file mode 100644 (file)
index 0000000..cb42e06
--- /dev/null
+++ b/source/win32/fasmarm.asm
@@ -0,0 +1,423 @@
+\r
+; flat assembler interface for Win32\r
+; Copyright (c) 1999-2016, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+       format  PE console large\r
+\r
+section '.text' code readable executable\r
+\r
+start:\r
+\r
+       mov     [con_handle],STD_OUTPUT_HANDLE\r
+       mov     esi,_logo\r
+       call    display_string\r
+\r
+       call    get_params\r
+       jc      information\r
+\r
+       call    init_memory\r
+\r
+       mov     esi,_memory_prefix\r
+       call    display_string\r
+       mov     eax,[memory_end]\r
+       sub     eax,[memory_start]\r
+       add     eax,[additional_memory_end]\r
+       sub     eax,[additional_memory]\r
+       shr     eax,10\r
+       call    display_number\r
+       mov     esi,_memory_suffix\r
+       call    display_string\r
+\r
+       call    [GetTickCount]\r
+       mov     [start_time],eax\r
+\r
+       and     [preprocessing_done],0\r
+       call    preprocessor\r
+       or      [preprocessing_done],-1\r
+       call    parser\r
+       call    ARM_label_walker        ;this line added for ARM\r
+       call    assembler\r
+       call    ARM_close_dwarf         ;this line added for ARM\r
+       call    formatter\r
+\r
+       call    display_user_messages\r
+       movzx   eax,[current_pass]\r
+       inc     eax\r
+       call    display_number\r
+       mov     esi,_passes_suffix\r
+       call    display_string\r
+       call    [GetTickCount]\r
+       sub     eax,[start_time]\r
+       xor     edx,edx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      eax,eax\r
+       jz      display_bytes_count\r
+       xor     edx,edx\r
+       mov     ebx,10\r
+       div     ebx\r
+       push    edx\r
+       call    display_number\r
+       mov     dl,'.'\r
+       call    display_character\r
+       pop     eax\r
+       call    display_number\r
+       mov     esi,_seconds_suffix\r
+       call    display_string\r
+      display_bytes_count:\r
+       mov     eax,[written_size]\r
+       call    display_number\r
+       mov     esi,_bytes_suffix\r
+       call    display_string\r
+       xor     al,al\r
+       jmp     exit_program\r
+\r
+information:\r
+       mov     esi,_usage\r
+       call    display_string\r
+       mov     al,1\r
+       jmp     exit_program\r
+\r
+get_params:\r
+       mov     [input_file],0\r
+       mov     [output_file],0\r
+       mov     [symbols_file],0\r
+       mov     [memory_setting],0\r
+       mov     [passes_limit],100\r
+       call    [GetCommandLine]\r
+       mov     [definitions_pointer],predefinitions\r
+       mov     esi,eax\r
+       mov     edi,params\r
+    find_command_start:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      find_command_start\r
+       cmp     al,22h\r
+       je      skip_quoted_name\r
+    skip_name:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      find_param\r
+       or      al,al\r
+       jz      all_params\r
+       jmp     skip_name\r
+    skip_quoted_name:\r
+       lodsb\r
+       cmp     al,22h\r
+       je      find_param\r
+       or      al,al\r
+       jz      all_params\r
+       jmp     skip_quoted_name\r
+    find_param:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      find_param\r
+       cmp     al,'-'\r
+       je      option_param\r
+       cmp     al,0Dh\r
+       je      all_params\r
+       or      al,al\r
+       jz      all_params\r
+       cmp     [input_file],0\r
+       jne     get_output_file\r
+       mov     [input_file],edi\r
+       jmp     process_param\r
+      get_output_file:\r
+       cmp     [output_file],0\r
+       jne     bad_params\r
+       mov     [output_file],edi\r
+    process_param:\r
+       cmp     al,22h\r
+       je      string_param\r
+    copy_param:\r
+       stosb\r
+       lodsb\r
+       cmp     al,20h\r
+       je      param_end\r
+       cmp     al,0Dh\r
+       je      param_end\r
+       or      al,al\r
+       jz      param_end\r
+       jmp     copy_param\r
+    string_param:\r
+       lodsb\r
+       cmp     al,22h\r
+       je      string_param_end\r
+       cmp     al,0Dh\r
+       je      param_end\r
+       or      al,al\r
+       jz      param_end\r
+       stosb\r
+       jmp     string_param\r
+    option_param:\r
+       lodsb\r
+       cmp     al,'m'\r
+       je      memory_option\r
+       cmp     al,'M'\r
+       je      memory_option\r
+       cmp     al,'p'\r
+       je      passes_option\r
+       cmp     al,'P'\r
+       je      passes_option\r
+       cmp     al,'d'\r
+       je      definition_option\r
+       cmp     al,'D'\r
+       je      definition_option\r
+       cmp     al,'s'\r
+       je      symbols_option\r
+       cmp     al,'S'\r
+       je      symbols_option\r
+    bad_params:\r
+       stc\r
+       ret\r
+    get_option_value:\r
+       xor     eax,eax\r
+       mov     edx,eax\r
+    get_option_digit:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      option_value_ok\r
+       cmp     al,0Dh\r
+       je      option_value_ok\r
+       or      al,al\r
+       jz      option_value_ok\r
+       sub     al,30h\r
+       jc      invalid_option_value\r
+       cmp     al,9\r
+       ja      invalid_option_value\r
+       imul    edx,10\r
+       jo      invalid_option_value\r
+       add     edx,eax\r
+       jc      invalid_option_value\r
+       jmp     get_option_digit\r
+    option_value_ok:\r
+       dec     esi\r
+       clc\r
+       ret\r
+    invalid_option_value:\r
+       stc\r
+       ret\r
+    memory_option:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      memory_option\r
+       cmp     al,0Dh\r
+       je      bad_params\r
+       or      al,al\r
+       jz      bad_params\r
+       dec     esi\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,1 shl (32-10)\r
+       jae     bad_params\r
+       mov     [memory_setting],edx\r
+       jmp     find_param\r
+    passes_option:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      passes_option\r
+       cmp     al,0Dh\r
+       je      bad_params\r
+       or      al,al\r
+       jz      bad_params\r
+       dec     esi\r
+       call    get_option_value\r
+       or      edx,edx\r
+       jz      bad_params\r
+       cmp     edx,10000h\r
+       ja      bad_params\r
+       mov     [passes_limit],dx\r
+       jmp     find_param\r
+    definition_option:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      definition_option\r
+       cmp     al,0Dh\r
+       je      bad_params\r
+       or      al,al\r
+       jz      bad_params\r
+       dec     esi\r
+       push    edi\r
+       mov     edi,[definitions_pointer]\r
+       call    convert_definition_option\r
+       mov     [definitions_pointer],edi\r
+       pop     edi\r
+       jc      bad_params\r
+       jmp     find_param\r
+    symbols_option:\r
+       mov     [symbols_file],edi\r
+      find_symbols_file_name:\r
+       lodsb\r
+       cmp     al,20h\r
+       jne     process_param\r
+       jmp     find_symbols_file_name\r
+    param_end:\r
+       dec     esi\r
+    string_param_end:\r
+       xor     al,al\r
+       stosb\r
+       jmp     find_param\r
+    all_params:\r
+       cmp     [input_file],0\r
+       je      bad_params\r
+       mov     eax,[definitions_pointer]\r
+       mov     byte [eax],0\r
+       mov     [initial_definitions],predefinitions\r
+       clc\r
+       ret\r
+    convert_definition_option:\r
+       mov     ecx,edi\r
+       xor     al,al\r
+       stosb\r
+      copy_definition_name:\r
+       lodsb\r
+       cmp     al,'='\r
+       je      copy_definition_value\r
+       cmp     al,20h\r
+       je      bad_definition_option\r
+       cmp     al,0Dh\r
+       je      bad_definition_option\r
+       or      al,al\r
+       jz      bad_definition_option\r
+       stosb\r
+       inc     byte [ecx]\r
+       jnz     copy_definition_name\r
+      bad_definition_option:\r
+       stc\r
+       ret\r
+      copy_definition_value:\r
+       lodsb\r
+       cmp     al,20h\r
+       je      definition_value_end\r
+       cmp     al,0Dh\r
+       je      definition_value_end\r
+       or      al,al\r
+       jz      definition_value_end\r
+       cmp     al,'\'\r
+       jne     definition_value_character\r
+       cmp     byte [esi],20h\r
+       jne     definition_value_character\r
+       lodsb\r
+      definition_value_character:\r
+       stosb\r
+       jmp     copy_definition_value\r
+      definition_value_end:\r
+       dec     esi\r
+       xor     al,al\r
+       stosb\r
+       clc\r
+       ret\r
+\r
+include '..\version.inc'\r
+include 'systemarm.inc'\r
+\r
+include '..\errors.inc'\r
+include '..\symbdump.inc'\r
+include '..\preproce.inc'\r
+include '..\parser.inc'\r
+include '..\exprpars.inc'\r
+include '..\exprcalc.inc'\r
+include '..\assemble.inc'\r
+include '..\formats.inc'\r
+include '..\armv8.inc'\r
+\r
+include '..\armtable.inc'\r
+include '..\messages.inc'\r
+\r
+section '.data' data readable writeable\r
+\r
+_copyright db  'Copyright (c) 2005-2023, revolution',0Dh,0Ah,\\r
+               'Some portions copyright (c) 1999-2016, Tomasz Grysztar',0Dh,0Ah,0\r
+\r
+_logo db 'flat assembler for ARM  version ',ARM_VERSION_STRING,' (built on fasm ',VERSION_STRING,')',0\r
+_usage db 0Dh,0Ah\r
+       db 'usage: fasmarm <source> [output]',0Dh,0Ah\r
+       db 'optional settings:',0Dh,0Ah\r
+       db ' -m <limit>         set the limit in kilobytes for the available memory',0Dh,0Ah\r
+       db ' -p <limit>         set the maximum allowed number of passes',0Dh,0Ah\r
+       db ' -d <name>=<value>  define symbolic variable',0Dh,0Ah\r
+       db ' -s <file>          dump symbolic information for debugging',0Dh,0Ah\r
+       db 0\r
+_memory_prefix db '  (',0\r
+_memory_suffix db ' kilobytes memory)',0Dh,0Ah,0\r
+_passes_suffix db ' passes, ',0\r
+_seconds_suffix db ' seconds, ',0\r
+_bytes_suffix db ' bytes.',0Dh,0Ah,0\r
+\r
+align 4\r
+\r
+include '..\variable.inc'\r
+\r
+con_handle dd ?\r
+memory_setting dd ?\r
+start_time dd ?\r
+definitions_pointer dd ?\r
+bytes_count dd ?\r
+displayed_count dd ?\r
+character db ?\r
+last_displayed rb 2\r
+preprocessing_done db ?\r
+\r
+params rb 1000h\r
+options rb 1000h\r
+predefinitions rb 1000h\r
+buffer rb 4000h\r
+\r
+stack 10000h\r
+\r
+section '.idata' import data readable writeable\r
+\r
+  dd 0,0,0,rva kernel_name,rva kernel_table\r
+  dd 0,0,0,0,0\r
+\r
+  kernel_table:\r
+    ExitProcess dd rva _ExitProcess\r
+    CreateFile dd rva _CreateFileA\r
+    ReadFile dd rva _ReadFile\r
+    WriteFile dd rva _WriteFile\r
+    CloseHandle dd rva _CloseHandle\r
+    SetFilePointer dd rva _SetFilePointer\r
+    GetCommandLine dd rva _GetCommandLineA\r
+    GetEnvironmentVariable dd rva _GetEnvironmentVariable\r
+    GetStdHandle dd rva _GetStdHandle\r
+    VirtualAlloc dd rva _VirtualAlloc\r
+    VirtualFree dd rva _VirtualFree\r
+    GetTickCount dd rva _GetTickCount\r
+    GetSystemTime dd rva _GetSystemTime\r
+    SetUnhandledExceptionFilter dd rva _SetUnhandledExceptionFilter\r
+    dd 0\r
+\r
+  kernel_name db 'KERNEL32.DLL',0\r
+\r
+  _ExitProcess dw 0\r
+    db 'ExitProcess',0\r
+  _CreateFileA dw 0\r
+    db 'CreateFileA',0\r
+  _ReadFile dw 0\r
+    db 'ReadFile',0\r
+  _WriteFile dw 0\r
+    db 'WriteFile',0\r
+  _CloseHandle dw 0\r
+    db 'CloseHandle',0\r
+  _SetFilePointer dw 0\r
+    db 'SetFilePointer',0\r
+  _GetCommandLineA dw 0\r
+    db 'GetCommandLineA',0\r
+  _GetEnvironmentVariable dw 0\r
+    db 'GetEnvironmentVariableA',0\r
+  _GetStdHandle dw 0\r
+    db 'GetStdHandle',0\r
+  _VirtualAlloc dw 0\r
+    db 'VirtualAlloc',0\r
+  _VirtualFree dw 0\r
+    db 'VirtualFree',0\r
+  _GetTickCount dw 0\r
+    db 'GetTickCount',0\r
+  _GetSystemTime dw 0\r
+    db 'GetSystemTime',0\r
+  _SetUnhandledExceptionFilter dw 0\r
+    db 'SetUnhandledExceptionFilter',0\r
+\r
+section '.reloc' fixups data readable discardable\r

diff --git a/source/win32/systemarm.inc b/source/win32/systemarm.inc
new file mode 100644 (file)
index 0000000..510f489
--- /dev/null
+++ b/source/win32/systemarm.inc
@@ -0,0 +1,628 @@
+MEMORY_ALLOCATION_BLOCK_SIZE   = 1 shl 16      ;64kB. Higher numbers reduce the number of calls to the allocator. A value of 1 will allocate just the page where the memory is accessed\r
+MEMORY_ALLOCATION_MAX_SIZE     = 0x7ffc0000    ;Windows fails all calls that try to allocate more than this\r
+\r
+; flat assembler interface for Win32\r
+; Copyright (c) 1999-2015, Tomasz Grysztar.\r
+; All rights reserved.\r
+\r
+CREATE_NEW            = 1\r
+CREATE_ALWAYS         = 2\r
+OPEN_EXISTING         = 3\r
+OPEN_ALWAYS           = 4\r
+TRUNCATE_EXISTING      = 5\r
+\r
+FILE_SHARE_READ        = 1\r
+FILE_SHARE_WRITE       = 2\r
+FILE_SHARE_DELETE      = 4\r
+\r
+GENERIC_READ          = 80000000h\r
+GENERIC_WRITE         = 40000000h\r
+\r
+STD_INPUT_HANDLE       = 0FFFFFFF6h\r
+STD_OUTPUT_HANDLE      = 0FFFFFFF5h\r
+STD_ERROR_HANDLE       = 0FFFFFFF4h\r
+\r
+MEM_COMMIT            = 1000h\r
+MEM_RESERVE           = 2000h\r
+MEM_DECOMMIT          = 4000h\r
+MEM_RELEASE           = 8000h\r
+MEM_FREE              = 10000h\r
+MEM_PRIVATE           = 20000h\r
+MEM_MAPPED            = 40000h\r
+MEM_RESET             = 80000h\r
+MEM_TOP_DOWN          = 100000h\r
+\r
+PAGE_NOACCESS         = 1\r
+PAGE_READONLY         = 2\r
+PAGE_READWRITE        = 4\r
+PAGE_WRITECOPY        = 8\r
+PAGE_EXECUTE          = 10h\r
+PAGE_EXECUTE_READ      = 20h\r
+PAGE_EXECUTE_READWRITE = 40h\r
+PAGE_EXECUTE_WRITECOPY = 80h\r
+PAGE_GUARD            = 100h\r
+PAGE_NOCACHE          = 200h\r
+\r
+init_memory:\r
+       xor     eax,eax\r
+       mov     [memory_start],eax\r
+       mov     eax,esp\r
+       and     eax,not 0FFFh\r
+       add     eax,1000h-10000h\r
+       mov     [stack_limit],eax\r
+       mov     ebx,[memory_setting]\r
+       shl     ebx,10\r
+       jnz     allocate_memory\r
+       mov     ebx,MEMORY_ALLOCATION_MAX_SIZE\r
+    allocate_memory:\r
+       push    PAGE_READWRITE\r
+       push    MEM_RESERVE\r
+       push    ebx\r
+       push    0\r
+       call    [VirtualAlloc]          ;allocate the main section\r
+       test    eax,eax\r
+       jz      not_enough_memory\r
+       mov     [memory_start],eax\r
+       add     eax,ebx\r
+       mov     [memory_end],eax\r
+       cmp     [memory_setting],0\r
+       jnz     .use_single_section\r
+       mov     eax,ebx\r
+       shr     eax,1\r
+       push    PAGE_READWRITE\r
+       push    MEM_RESERVE\r
+       push    eax\r
+       push    0\r
+       call    [VirtualAlloc]          ;allocate the additional section\r
+       test    eax,eax\r
+       jz      .use_single_section\r
+       mov     [additional_memory],eax\r
+       shr     ebx,1\r
+       add     eax,ebx\r
+       mov     [additional_memory_end],eax\r
+    .memory_okay:\r
+       push    memory_allocation_handler\r
+       call    [SetUnhandledExceptionFilter]\r
+       ret\r
+    .use_single_section:\r
+       mov     eax,[memory_end]\r
+       mov     [additional_memory_end],eax\r
+       shr     ebx,2\r
+       sub     eax,ebx\r
+       mov     [memory_end],eax\r
+       mov     [additional_memory],eax\r
+       jmp     .memory_okay\r
+    not_enough_memory:\r
+       shr     ebx,2\r
+       lea     ebx,[ebx*3]\r
+       cmp     ebx,4000h\r
+       jae     allocate_memory\r
+       jmp     out_of_memory\r
+\r
+exit_program:\r
+       movzx   eax,al\r
+       push    eax\r
+       mov     eax,[memory_start]\r
+       test    eax,eax\r
+       jz      do_exit\r
+       push    MEM_RELEASE\r
+       push    0\r
+       push    eax\r
+       call    [VirtualFree]\r
+       push    MEM_RELEASE\r
+       push    0\r
+       push    [additional_memory]\r
+       call    [VirtualFree]\r
+    do_exit:\r
+       call    [ExitProcess]\r
+\r
+memory_allocation_handler:\r
+       mov     eax,[esp+4]     ;get pointer to exception information\r
+       mov     ecx,[eax]       ;EXCEPTION_POINTERS.ExceptionRecord\r
+       mov     edx,[ecx]       ;EXCEPTION_RECORD.ExceptionCode\r
+       cmp     edx,0xc0000005  ;EXCEPTION_ACCESS_VIOLATION\r
+       jnz     .fail\r
+       mov     edx,[ecx+24]    ;EXCEPTION_RECORD.ExceptionAddress\r
+       cmp     edx,[memory_start]\r
+       jb      .check_additional\r
+       mov     eax,[memory_end]\r
+       sub     eax,edx         ;don't allocate more than EAX bytes\r
+       ja      .allocate\r
+    .check_additional:\r
+       cmp     edx,[additional_memory]\r
+       jb      .fail\r
+       mov     eax,[additional_memory_end]\r
+       sub     eax,edx         ;don't allocate more than EAX bytes\r
+       jbe     .fail\r
+    .allocate:\r
+       mov     ecx,MEMORY_ALLOCATION_BLOCK_SIZE\r
+       cmp     eax,ecx\r
+       jbe     .allocation_size_defined\r
+       mov     eax,ecx         ;don't allocate more than ECX bytes\r
+    .allocation_size_defined:\r
+       push    PAGE_READWRITE\r
+       push    MEM_COMMIT\r
+       push    eax             ;allocate this many bytes\r
+       push    edx             ;at this address\r
+       call    [VirtualAlloc]\r
+       test    eax,eax\r
+       jz      out_of_memory\r
+       mov     eax,-1          ;EXCEPTION_CONTINUE_EXECUTION\r
+       retn    4\r
+    .fail:                     ;some other exception happened\r
+       mov     eax,0           ;EXCEPTION_CONTINUE_SEARCH\r
+       retn    4\r
+\r
+get_environment_variable:\r
+       mov     ecx,[memory_end]\r
+       sub     ecx,edi\r
+       cmp     ecx,4000h\r
+       jbe     buffer_for_variable_ok\r
+       mov     ecx,4000h\r
+    buffer_for_variable_ok:\r
+       push    ecx\r
+       push    edi\r
+       push    esi\r
+       call    [GetEnvironmentVariable]\r
+       add     edi,eax\r
+       cmp     edi,[memory_end]\r
+       jae     out_of_memory\r
+       ret\r
+\r
+open:\r
+       push    0\r
+       push    0\r
+       push    OPEN_EXISTING\r
+       push    0\r
+       push    FILE_SHARE_READ\r
+       push    GENERIC_READ\r
+       push    edx\r
+       call    [CreateFile]\r
+       cmp     eax,-1\r
+       je      file_error\r
+       mov     ebx,eax\r
+       clc\r
+       ret\r
+    file_error:\r
+       stc\r
+       ret\r
+create:\r
+       push    0\r
+       push    0\r
+       push    CREATE_ALWAYS\r
+       push    0\r
+       push    FILE_SHARE_READ\r
+       push    GENERIC_WRITE\r
+       push    edx\r
+       call    [CreateFile]\r
+       cmp     eax,-1\r
+       je      file_error\r
+       mov     ebx,eax\r
+       clc\r
+       ret\r
+write:\r
+       push    0\r
+       push    bytes_count\r
+       push    ecx\r
+       push    edx\r
+       push    ebx\r
+       call    [WriteFile]\r
+       or      eax,eax\r
+       jz      file_error\r
+       clc\r
+       ret\r
+read:\r
+       mov     ebp,ecx\r
+       test    ecx,ecx\r
+       jz      .zero_length\r
+       push    edx\r
+       push    PAGE_READWRITE\r
+       push    MEM_COMMIT\r
+       push    ecx             ;allocate the required number of bytes\r
+       push    edx             ;at this address\r
+       call    [VirtualAlloc]\r
+       pop     edx\r
+       test    eax,eax\r
+       jz      out_of_memory\r
+    .zero_length:\r
+       push    0\r
+       push    bytes_count\r
+       push    ebp\r
+       push    edx\r
+       push    ebx\r
+       call    [ReadFile]\r
+       or      eax,eax\r
+       jz      file_error\r
+       cmp     ebp,[bytes_count]\r
+       jne     file_error\r
+       clc\r
+       ret\r
+close:\r
+       push    ebx\r
+       call    [CloseHandle]\r
+       ret\r
+lseek:\r
+       movzx   eax,al\r
+       push    eax\r
+       push    0\r
+       push    edx\r
+       push    ebx\r
+       call    [SetFilePointer]\r
+       ret\r
+\r
+display_string:\r
+       push    [con_handle]\r
+       call    [GetStdHandle]\r
+       mov     ebp,eax\r
+       mov     edi,esi\r
+       or      ecx,-1\r
+       xor     al,al\r
+       repne   scasb\r
+       neg     ecx\r
+       sub     ecx,2\r
+       push    0\r
+       push    bytes_count\r
+       push    ecx\r
+       push    esi\r
+       push    ebp\r
+       call    [WriteFile]\r
+       ret\r
+display_character:\r
+       push    ebx\r
+       mov     [character],dl\r
+       push    [con_handle]\r
+       call    [GetStdHandle]\r
+       mov     ebx,eax\r
+       push    0\r
+       push    bytes_count\r
+       push    1\r
+       push    character\r
+       push    ebx\r
+       call    [WriteFile]\r
+       pop     ebx\r
+       ret\r
+display_number:\r
+       push    ebx\r
+       mov     ecx,1000000000\r
+       xor     edx,edx\r
+       xor     bl,bl\r
+      display_loop:\r
+       div     ecx\r
+       push    edx\r
+       cmp     ecx,1\r
+       je      display_digit\r
+       or      bl,bl\r
+       jnz     display_digit\r
+       or      al,al\r
+       jz      digit_ok\r
+       not     bl\r
+      display_digit:\r
+       mov     dl,al\r
+       add     dl,30h\r
+       push    ecx\r
+       call    display_character\r
+       pop     ecx\r
+      digit_ok:\r
+       mov     eax,ecx\r
+       xor     edx,edx\r
+       mov     ecx,10\r
+       div     ecx\r
+       mov     ecx,eax\r
+       pop     eax\r
+       or      ecx,ecx\r
+       jnz     display_loop\r
+       pop     ebx\r
+       ret\r
+\r
+display_user_messages:\r
+       mov     [displayed_count],0\r
+       call    show_display_buffer\r
+       cmp     [displayed_count],1\r
+       jb      line_break_ok\r
+       je      make_line_break\r
+       mov     ax,word [last_displayed]\r
+       cmp     ax,0A0Dh\r
+       je      line_break_ok\r
+       cmp     ax,0D0Ah\r
+       je      line_break_ok\r
+      make_line_break:\r
+       mov     word [buffer],0A0Dh\r
+       push    [con_handle]\r
+       call    [GetStdHandle]\r
+       push    0\r
+       push    bytes_count\r
+       push    2\r
+       push    buffer\r
+       push    eax\r
+       call    [WriteFile]\r
+      line_break_ok:\r
+       ret\r
+display_block:\r
+       add     [displayed_count],ecx\r
+       cmp     ecx,1\r
+       ja      take_last_two_characters\r
+       jb      block_displayed\r
+       mov     al,[last_displayed+1]\r
+       mov     ah,[esi]\r
+       mov     word [last_displayed],ax\r
+       jmp     block_ok\r
+      take_last_two_characters:\r
+       mov     ax,[esi+ecx-2]\r
+       mov     word [last_displayed],ax\r
+      block_ok:\r
+       push    ecx\r
+       push    [con_handle]\r
+       call    [GetStdHandle]\r
+       pop     ecx\r
+       push    0\r
+       push    bytes_count\r
+       push    ecx\r
+       push    esi\r
+       push    eax\r
+       call    [WriteFile]\r
+      block_displayed:\r
+       ret\r
+\r
+fatal_error:\r
+       mov     [con_handle],STD_ERROR_HANDLE\r
+       mov     esi,error_prefix\r
+       call    display_string\r
+       pop     esi\r
+       call    display_string\r
+       mov     esi,error_suffix\r
+       call    display_string\r
+       mov     al,0FFh\r
+       jmp     exit_program\r
+assembler_error:\r
+       mov     [con_handle],STD_ERROR_HANDLE\r
+       call    display_user_messages\r
+       mov     ebx,[current_line]\r
+       test    ebx,ebx\r
+       jz      display_error_message\r
+       push    dword 0\r
+      get_error_lines:\r
+       mov     eax,[ebx]\r
+       cmp     byte [eax],0\r
+       je      get_next_error_line\r
+       push    ebx\r
+       test    byte [ebx+7],80h\r
+       jz      display_error_line\r
+       mov     edx,ebx\r
+      find_definition_origin:\r
+       mov     edx,[edx+12]\r
+       test    byte [edx+7],80h\r
+       jnz     find_definition_origin\r
+       push    edx\r
+      get_next_error_line:\r
+       mov     ebx,[ebx+8]\r
+       jmp     get_error_lines\r
+      display_error_line:\r
+       mov     esi,[ebx]\r
+       call    display_string\r
+       mov     esi,line_number_start\r
+       call    display_string\r
+       mov     eax,[ebx+4]\r
+       and     eax,7FFFFFFFh\r
+       call    display_number\r
+       mov     dl,']'\r
+       call    display_character\r
+       pop     esi\r
+       cmp     ebx,esi\r
+       je      line_number_ok\r
+       mov     dl,20h\r
+       call    display_character\r
+       push    esi\r
+       mov     esi,[esi]\r
+       movzx   ecx,byte [esi]\r
+       inc     esi\r
+       call    display_block\r
+       mov     esi,line_number_start\r
+       call    display_string\r
+       pop     esi\r
+       mov     eax,[esi+4]\r
+       and     eax,7FFFFFFFh\r
+       call    display_number\r
+       mov     dl,']'\r
+       call    display_character\r
+      line_number_ok:\r
+       mov     esi,line_data_start\r
+       call    display_string\r
+       mov     esi,ebx\r
+       mov     edx,[esi]\r
+       call    open\r
+       mov     al,2\r
+       xor     edx,edx\r
+       call    lseek\r
+       mov     edx,[esi+8]\r
+       sub     eax,edx\r
+       jz      line_data_displayed\r
+       push    eax\r
+       xor     al,al\r
+       call    lseek\r
+       mov     ecx,[esp]\r
+       mov     edx,[additional_memory]\r
+       lea     eax,[edx+ecx]\r
+       cmp     eax,[additional_memory_end]\r
+       ja      out_of_memory\r
+       call    read\r
+       call    close\r
+       pop     ecx\r
+       mov     esi,[additional_memory]\r
+      get_line_data:\r
+       mov     al,[esi]\r
+       cmp     al,0Ah\r
+       je      display_line_data\r
+       cmp     al,0Dh\r
+       je      display_line_data\r
+       cmp     al,1Ah\r
+       je      display_line_data\r
+       or      al,al\r
+       jz      display_line_data\r
+       inc     esi\r
+       loop    get_line_data\r
+      display_line_data:\r
+       mov     ecx,esi\r
+       mov     esi,[additional_memory]\r
+       sub     ecx,esi\r
+       call    display_block\r
+      line_data_displayed:\r
+       mov     esi,cr_lf\r
+       call    display_string\r
+       pop     ebx\r
+       or      ebx,ebx\r
+       jnz     display_error_line\r
+       cmp     [preprocessing_done],0\r
+       je      display_error_message\r
+       mov     esi,preprocessed_instruction_prefix\r
+       call    display_string\r
+       mov     esi,[current_line]\r
+       add     esi,16\r
+       mov     edi,[additional_memory]\r
+       xor     dl,dl\r
+      convert_instruction:\r
+       lodsb\r
+       cmp     al,1Ah\r
+       je      copy_symbol\r
+       cmp     al,22h\r
+       je      copy_symbol\r
+       cmp     al,3Bh\r
+       je      instruction_converted\r
+       stosb\r
+       or      al,al\r
+       jz      instruction_converted\r
+       xor     dl,dl\r
+       jmp     convert_instruction\r
+      copy_symbol:\r
+       or      dl,dl\r
+       jz      space_ok\r
+       mov     byte [edi],20h\r
+       inc     edi\r
+      space_ok:\r
+       cmp     al,22h\r
+       je      quoted\r
+       lodsb\r
+       movzx   ecx,al\r
+       rep     movsb\r
+       or      dl,-1\r
+       jmp     convert_instruction\r
+      quoted:\r
+       mov     al,27h\r
+       stosb\r
+       lodsd\r
+       mov     ecx,eax\r
+       jecxz   quoted_copied\r
+      copy_quoted:\r
+       lodsb\r
+       stosb\r
+       cmp     al,27h\r
+       jne     quote_ok\r
+       stosb\r
+      quote_ok:\r
+       loop    copy_quoted\r
+      quoted_copied:\r
+       mov     al,27h\r
+       stosb\r
+       or      dl,-1\r
+       jmp     convert_instruction\r
+      instruction_converted:\r
+       xor     al,al\r
+       stosb\r
+       mov     esi,[additional_memory]\r
+       call    display_string\r
+       mov     esi,cr_lf\r
+       call    display_string\r
+      display_error_message:\r
+       mov     esi,error_prefix\r
+       call    display_string\r
+       pop     esi\r
+       call    display_string\r
+       mov     esi,error_suffix\r
+       call    display_string\r
+       mov     al,2\r
+       jmp     exit_program\r
+\r
+make_timestamp:\r
+       push    buffer\r
+       call    [GetSystemTime]\r
+       movzx   ecx,word [buffer]\r
+       mov     eax,ecx\r
+       sub     eax,1970\r
+       mov     ebx,365\r
+       mul     ebx\r
+       mov     ebp,eax\r
+       mov     eax,ecx\r
+       sub     eax,1969\r
+       shr     eax,2\r
+       add     ebp,eax\r
+       mov     eax,ecx\r
+       sub     eax,1901\r
+       mov     ebx,100\r
+       div     ebx\r
+       sub     ebp,eax\r
+       mov     eax,ecx\r
+       xor     edx,edx\r
+       sub     eax,1601\r
+       mov     ebx,400\r
+       div     ebx\r
+       add     ebp,eax\r
+       movzx   ecx,word [buffer+2]\r
+       mov     eax,ecx\r
+       dec     eax\r
+       mov     ebx,30\r
+       mul     ebx\r
+       add     ebp,eax\r
+       cmp     ecx,8\r
+       jbe     months_correction\r
+       mov     eax,ecx\r
+       sub     eax,7\r
+       shr     eax,1\r
+       add     ebp,eax\r
+       mov     ecx,8\r
+      months_correction:\r
+       mov     eax,ecx\r
+       shr     eax,1\r
+       add     ebp,eax\r
+       cmp     ecx,2\r
+       jbe     day_correction_ok\r
+       sub     ebp,2\r
+       movzx   ecx,word [buffer]\r
+       test    ecx,11b\r
+       jnz     day_correction_ok\r
+       xor     edx,edx\r
+       mov     eax,ecx\r
+       mov     ebx,100\r
+       div     ebx\r
+       or      edx,edx\r
+       jnz     day_correction\r
+       mov     eax,ecx\r
+       mov     ebx,400\r
+       div     ebx\r
+       or      edx,edx\r
+       jnz     day_correction_ok\r
+      day_correction:\r
+       inc     ebp\r
+      day_correction_ok:\r
+       movzx   eax,word [buffer+6]\r
+       dec     eax\r
+       add     eax,ebp\r
+       mov     ebx,24\r
+       mul     ebx\r
+       movzx   ecx,word [buffer+8]\r
+       add     eax,ecx\r
+       mov     ebx,60\r
+       mul     ebx\r
+       movzx   ecx,word [buffer+10]\r
+       add     eax,ecx\r
+       mov     ebx,60\r
+       mul     ebx\r
+       movzx   ecx,word [buffer+12]\r
+       add     eax,ecx\r
+       adc     edx,0\r
+       ret\r
+\r
+error_prefix db 'error: ',0\r
+error_suffix db '.'\r
+cr_lf db 0Dh,0Ah,0\r
+line_number_start db ' [',0\r
+line_data_start db ':',0Dh,0Ah,0\r
+preprocessed_instruction_prefix db 'processed: ',0\r